COMP-261 Computer Organization and

Assembly Language

Lecture
Basic Concepts & Top-level View of Computer Functio
Dr Hashim Al

Fall - 2021

Department of IT and Computer Scienc

Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology

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 Introduction
Chapter - 1.1, 1.
Computer Organization Architecture — William Stallings

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Architecture & Organization

• Computer Architecture refers to those attributes which are visible to a
programme

• Examples of architectural attributes includes

• Instruction set, number of bits used for various data types (e.g.,
numbers, characters etc.), I/O mechanisms and techniques for
addressing memory

• For example, it is an architectural design issue whether a computer will

have a multiply instruction.

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Architecture & Organization —Contd.

• Computer Organization refers to the operational units and their interconnections that realises
the architectural speci cations (In simple words, how features are implemented

• Organizational attributes include those hardware details which are transparent to the
programmer, such as
• Control signals, interfaces between computer and peripherals and the memory technology
used

• For example, it is an Organizational issue whether multiply instruction will be implemented by a

special multiply unit or by a mechanism that makes repeated use of the add unit of the system

• The Organizational decision may be based on the anticipated frequency of the use of the
multiply instruction, the relative speed of two approaches, and the cost and physical size of a
special multiply unit.

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What is Computer Architecture?
• Computer Architecture is the set of pre-de ned rules and methods that describes the
functionality of computer system
• In other words, a computer consists of both hardware and software and using some rules and
methods for the interaction of both hardware and software of a computer is known as computer
architecture
• Hardware consists of parts like CPU, hard drives, various circuit chips and
• Integrating their functionality with the software that is, the programs (code) to make a
computer system work is the main objective an
• this is done by Computer Architects and designers and coders

• There are mainly three sub-categories in computer architecture

• Instruction Set Architecture (ISA
• Micro Architecture system desig
• Macro Architecture system design

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Instruction Set Architecture (ISA)

• Instruction Set Architecture is a group of instructions that are understood by a processor and the set
of instructions is what makes it an architecture.

There are two types under instruction set

• CISC (Complex Instruction Set Computer
• e.g. single instruction for multiplicatio
• CISC architectures are used to design computers at cheap cos
• Examples; PDP-11, VAX, Motorola 68k, and Intel’s x86 architecture
• RISC (Reduced Instruction Set Computer
• e.g. executing multiplication using multiple addition instructio
• Amount of work that can be done is limited by having separate LOAD and STORE instructions
• Examples; DEC Alpha, AMD 29k, ARC, Atmel AVR, Black n, Intel i860 and i960, MIPS,
Motorola 88000, PA-RISC, Power (including PowerPC), SuperH, SPARC, ARM

Types of Computer (design) Architecture

• Computer Architecture can be categorised on different basis like
• the number of instructions being executed per clock cycle an
• another way of classi cation of architecture is that the connections
between CPU and Memory

• Two types of architectures are

• Harvard Architectur
• John Von-Neumann Architecture

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Harvard Architecture
• “Harvard Mark I” was the name of a computer which
stored instructions on a punched tapes

• This architecture consists of two memory or address

busses between the CPU and the memory

• One notable thing about this architecture is that most of

the modern computers use this Harvard architecture

• Memory is divided into two different parts namely data

and instruction (program) memory

• Harvard Architecture is used primary for small embedded

computers and Digital Signal Processing (DSP).

John von Neumann Architecture

• This Architecture was named after a computer scientist named John
Von-Neumann

• Von-Neumann architecture used hardwired programs that is if one

want to program a computer again or change the existing program
functionality, the hardware switches should be changed manually
which results in potential errors

• Both data transfer and the instruction or program execution is

done by a single bus

• The main difference between Harvard and von-Neumann

Architectures lies in how they execute and transfer their data

• Von Neumann is better for desktop computers, laptops,

workstations and performance computers.

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Structure & Function of Computer

• A computer is a complex system; contains millions of elementary electronic
components
• The key is to organise the hierarchical nature of most complex systems,
including the computer
• Hierarchical system; set of interrelated subsystems

• Structure is the way in which the components are interrelated

• Function is the operation of individual components as part of the

structure.

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Structural View

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COMPUTER

• CPU – controls the operation of !"#$%&'(

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the computer and performs its

data processing functions Structural Components of
Computer
• Main Memory – stores data 6,'3%(478944:/(41$2.3#(%

Peripherals Computer
• I/O – moves data between the
Central
computer and its external Processing
Main
Memory
Unit
environment Computer
Systems

• System Interconnection/Bus – some Bus

mechanism that provides for Input

Output
communication among CPU, main Communication
lines
memory, and I/O

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 COMPUTER

Structural Components of CPU I/O Main

memory

System
Bus

• Control Unit — Controls the operation of the CPU

CPU and hence the computer CPU

Registers ALU
• Arithmetic and Logic Unit (ALU) — Performs Internal
the computer’s data processing function Bus

Control
Unit
• Registers — Provide storage internal to the CONTROL
CPU Sequencing
UNIT

Logic

• CPU Interconnection/Bus — Some

Control Unit
Registers and
Decoders

mechanism that provides for communication Control

among the control unit, ALU, and registers Memory

Figure 1.4 A Top-Down View of a Computer

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Functional View of the Computer

• All computer can perform four basic

functions, which are

a) Data processin

b) Data storag

c) Data movemen

d) Control

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 Storage Processing Storage

(a) (b)

Movement Movement

Operations (1/4) Movement Movement

Control Control

(a) Data Processin Control Control

Storage Processing Storage Processing

• The computer, of course, must be able to

process data (a) Storage Processing (b) Storage

• The data may take a wide variety of forms, and (c) (d)

the range of processing requirements. Movement

Figure 1.2 PossibleMovement
Computer Operations

• Processing from/to storag Control Control

• Processing from storage to I/O

Storage Processing Storage Processing

(c) (d)

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Figure 1.2 Possible Computer Operations
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Operations (2/4)
Movement Movement
(b) Data Storag

• It is also essential that a computer store data

• Even if the computer is processing data (i.e.,
data come in and get processed,
Controland the results Control

go out immediately), the computer must

temporarily store at least those pieces of data
that are being worked on at any given moment.
Storage Processing Storage Processing

(a) (b)

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Movement Movement
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Operations (3/4)
Movement
(c) Data Movemen

• The computer must be able to move data

between itself and the outside world
• The computer’s operating environment consists Control

of devices that serves as either sources or

destinations of the data
• When data are received from or delivered to a
Storage Processing
device that is directly connected to the
computer, the process is known as Input-Output
(a)
(I/O), and the device is referred to as a peripheral.

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Movement
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Operations (4/4)
(d) Contro

• Finally, there must be control of these three

functions
• Within the computer, a control unit manages
the computer’s resources and the performance
of its functional parts in response to
instructions.

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 A Top-Level Vie
of
Computer Function and Interconnection
Chapter - 3.1, 3.2, 3.3, 3.
Computer Organisation Architecture — William Stallings

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Approaches to Design Digital System (1/2)

Hardware Approac
• Small set of logical components combined in various ways to store binary data and perform
arithmetic and logical operations on that data
• e.g., addition of two numbers
• If there is a particular computation to be performed, a con guration of logic components designed
speci cally for that computation could be constructed
• e.g., dedicated component for multiplication.
Hardwired Progra
• The result of the process of connecting the various
components in the desired con guration as a form
of programming
• The resulting program in the form of hardware
called as Hardwired Program.

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Approaches to Design Digital System (2/2)

Software Approac
Control Unit
• Construction of a general-purpose (or
con guration of arithmetic and logic functions Controller)

• This set of hardware will perform various

functions on data depending on control
signals applied to hardware
• With general-purpose hardware, the system
accepts data and control signals and produce
results.

How Control Signals are generated?

• Provide a unique code (e.g. ADD — 001011) for each possible set of control signals
• Add general-purpose hardware a segment (register) that can accept a code and generate control
signal.
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 Software I/O Components

Major Components are
• CP
• Instruction interprete
• Module of general-purpose arithmetic and logic function
• I/O Component
• Input Modul
• Contains basic components for accepting data and instructions and converting them into an
internal form of signals usable by the system
• Output Modul
• Means of reporting results
• Memor
• To store instructions and data

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1- CPU Component
Abstract Level View
• CPU exchanges data with memory, using
two internal registers
• Memory Address Register (MAR) —
for instruction addres
• Memory Buffer Register (MBR) — for
dat

• CPU exchanges data with I/O using

• I/O Address Register (I/OAR) — for
addres
• I/O Buffer Register (I/OBR) — for
data

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Computer Function
• The basic function performed by a computer is execution of a program
• A program consists of a set of instructions stored in memory

• The processor does the actual work by executing instructions speci ed in

the program

• The key elements of program execution are

• The processor fetches instructions from memory one at a time and
executes each instruction
• Program execution consists of repeating the process of instruction fetch
and instruction execution.

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Basic Instruction Cycle

• The processing required for a single instruction is called an Instruction Cycle

• In simples form, instruction processing consists of two steps
• Fetch Cycl
• Execute Cycl
• Program execution halts only if the machine is turned off, some sort of unrecoverable
error occurs, or a program instruction that halts the computer is encountered.

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Fetch Cycle
• At the beginning of each instruction cycle the processor fetches an instruction
from Instruction Memory
• The Program Counter (PC) holds the address of the instruction to be fetched
next

• The processor increments the PC after each instruction fetch so that it will fetch
the next instruction in sequenc

• The fetched instruction is loaded into the Instruction Register (IR

• The processor interprets the instruction and performs the required action
(actions are explained in next slide)

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Processor — Action Categories

• Processor-memory
• Data may be transferred from processor to memory or from memory to processor
• Processor-I/O
• Data may be transferred to or from a peripheral device by transferring between the processor and an I/O
module

• Data processing
• The processor may perform some arithmetic or logic operation on data
• Control
• An instruction may specify that the sequence of execution be altered.
For example, the processor may fetch an instruction from location 149, which speci es that the next instruction be from
location 182. The processor will remember this fact by setting the program counter to 182. Thus, on the next fetch cycle, the
instruction will be fetched from location 182 rather than 150

• An instruction’s execution may involve a combination of these actions.

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Example — Hypothetical Machine

Consider a hypothetical machine which
includes
• Single instruction register — IR (16-bit
• Single data register — AC (16-bit

• Instruction format provides

• 4-bit Opcode →
• 24 instruction
• 12-bit Address →
• 212 memory addresses

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Example
Program Execution

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Instruction Cycle State Diagram

• The execution cycle for a particular instruction may involve more than one reference to
memory. Also, instead of memory references, an instruction may specify an I/O operation

• The gure (state diagram) provides more detailed look at the basic instruction cycle.

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Description of States
• Instruction Address Calculation (IAC): Determine the address of the next instruction to be executed.
• For example, if each instruction is 16 bits long and memory is organised into 16-bit words, then
add 1 to the previous address. If, instead, memory is organised as individually addressable 8-bit
bytes, then add 2 to the previous address

• Instruction Fetch (IF): Read instruction from its memory location into the processor
• Instruction Operation Decoding (IOD): Analyse instruction to determine type of operation to be
performed and operand(s) to be used

• Operand Address Calculation (OAC): If the operation involves reference to an operand in memory or
available via I/O, then determine the address of the operand

• Operand Fetch (OF): Fetch the operand from memory or read it in from I/O
• Data Operation (DO): Perform the operation indicated in the instruction
• Operand Store (OS): Write the result into memory or out to I/O.

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Classes of Interrupts
• Virtually all computers provide a mechanism by which other modules (I/
O, memory) may interrupt the normal processing of the processor
• Table lists the most common classes of interrupts.
Program Generated by some condition that occurs as a result of an instruction
execution, such as arithmetic overflow, division by zero, attempt to
execute an illegal machine instruction, or reference outside a user's
allowed memory space.
Timer Generated by a timer within the processor. This allows the operating
system to perform certain functions on a regular basis.
I/O Generated by an I/O controller, to signal normal completion of an
operation, request service from the processor, or to signal a variety of
error conditions.
Hardware failure Generated by a failure such as power failure or memory parity error.
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Interrupts
• Interrupts are a mechanism for peripherals (I/O) to signal to the computer
processor (CPU) that they require attention

• Dedicated wires are used to connect with all of the peripherals connected to
the computer

• When a peripheral requires attention, it sends a unique signal to the CPU for
it to stop what it is doing and service the peripheral

• Once the CPU has identi ed the peripheral that requires attention, control of
the processor is passed to a small program, called an Interrupt Handler or
Interrupt Service Routine (ISR), which deals with the peripheral.

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Sequence of Events in case of Interrupt
The sequence of events are
• Interrupt is raised
• Current CPU instruction is completed
• Contents of internal registers are stored in (pushed in) stack
• The memory address of the ISR is found and transfer control
• ISR is run
• Internal register contents are restored (popped out) from the stack
• Original process continues from where it was stopped.

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 Why to use Interrupts?

• Interrupts are provided primarily as a way to improve processing
ef ciency

• For example, most external devices are much slower than the processor.
Suppose that the processor is transferring data to a printer using the
instruction cycle scheme. After each write operation, the processor must
pause and remain idle until the printer catches up. The length of this pause
may be on the order of many hundreds or even thousands of instruction
cycles that do not involve memory

• Clearly, this is a very wasteful use of the processor.

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User Program Flow Control without Interrupt

• We have a user program that contains two WRITE
commands
• There is a segment of code at the beginning, then one
WRITE command, then a second segment of code, then a
second WRITE command, then a third and nal segment
of code
• The WRITE command invokes the I/O program
provided by the OS

• Similarly, the I/O program consists of a segment of code,

followed by an I/O command, followed by another
segment of code. The I/O command invokes a hardware
I/O operation.
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User Program Flow Control with Interrupt

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Transfer of Control via Interrupts
• From the view point of user program,
an interrupt is an interruption of the
normal sequence of execution

• When interrupt processing is

completed, execution resumes.
• The user program does not have to
contain any special code to accommodate
interrupts; the processor and the
operating system are responsible for
supsnding the user program and then
resuming it at the same time.

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Instruction Cycle With Interrupts (1/2)

• To accommodate interrupts, an interrupt cycle is added to the instruction cycle, as shown in Figure

• In the interrupt cycle, the processor checks to see if any interrupts have occurred, indicated by the
presence of an interrupt signal. If no interrupts are pending, the processor proceeds to the fetch
cycle and fetches the next instruction of the current program.

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Instruction Cycle With Interrupts (2/2)
• If an interrupt is pending, the processor does the following
• It suspends execution of the current program being executed and saves its context.
This means saving the address of the next instruction to be executed (current
contents of the program counter) and any other data relevant to the processor’s
current activity
• It sets the program counter to the starting address of an interrupt handler routine

• The processor now proceeds to the fetch cycle and fetches the rst instruction in the
interrupt handler program, which will service the interrupt

• The interrupt handler program is generally part of the operating system. Typically, this
program determines the nature of the interrupt and performs whatever actions are
needed.

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 Program Timing
Short I/O Wait
• The gure is to visualise the gain in ef ciency
(in terms of time)

• User program code segments are shaded

green, and I/O program code segments are
shaded grey

• In g (a) interrupts are not used. The

processor must wait while an I/O operation is
performed

• In g (b) the time required for the I/O

operation is relatively short: less than the time
to complete the execution of instructions
between write operations in the user program.

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 Program Timing:
Long I/O Wait
• The more typical case, especially for a slow device such
as a printer, is that the I/O operation will take much
more time then executing a sequence of user
instructions

• Figure indicates the case, the user program reaches the

second WRITE call before the I/O operation spawned by
the rst call is complete

• The result is that the user program is hung up at that

point. When the preceding I/O operation is completed,
this new WRITE call may be processed, and a new I/O
operation may be started

• Figure shows the timing for this situation with and

without the use of interrupts. We can see that there is
still a gain in ef ciency because part of the time during
which the I/O operation is under way overlaps with the
execution of user instructions.

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Instruction Cycle State Diagram With Interrupts

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Transfer of Control with Multiple Interrupts (1/2)
Two approaches can be taken to dealing with
multiple interrupts

1. Disable Interrupt
• Disable interrupts while an interrupt is
being processed
• If an interrupt occurs during this time, it
generally remains pending and will be
checked by the processor after the processor
has enabled interrupts
• After the interrupt handler routine
completes, interrupts are enabled before
resuming the user program, and the
processor checks to see if additional
interrupts have occurred.

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Transfer of Control with Multiple Interrupts (2/2)

2. Interrupt Priorit

• A second approach is to de ne
priorities for interrupts and to
allow an interrupt of higher
priority to cause a lower-priority
interrupt handler to be itself
interrupted

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Time Sequence of Multiple Interrupts
Occurrence of
ISR Execution
I/O Device Priority Interrupt
Tme
(in time)

Printer 2 10 10
Communication 5 15 10
Disk 4 25 10

ISR (Priority)

2 - Lowest Priorit
Disk (4)
5 - Highest Priority

Communication (5)

Printer (2)

Time
0 5 10 15 20 25 30 35 40 45

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2- I/O Function
• I/O module can exchange data directly with the processor

• Processor can read data from or write data to an I/O module

• Processor identi es a speci c device that is controlled by a particular I/O modul
• I/O instructions rather than memory referencing instructions

• In some cases it is desirable to allow I/O exchanges to occur directly with memor
• The processor grants to an I/O module the authority to read from or write to
memory so that the I/O memory transfer can occur without tying up the processor
• The I/O module issues read or write commands to memory relieving the processor
of responsibility for the exchange
• This operation is known as direct memory access (DMA).

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 Interconnection Structure
Computer Modules

• A computer consists of a set of components or modules of three basic

types (processor, memory, I/O) that communicate with each other
• In effect, a computer is a network of basic modules. Thus, there
must be paths for connecting the modules

• The collection of paths connecting the various modules is called the

interconnection structure
• The design of this structure will depend on the exchanges that
must be made among modules

• Computer modules are

• Memor
• I/
• CPU

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Types of Transfers
• Memory to Processor
• The processor reads an instruction or a unit of data from memory

• Processor to Memory
• The processor writes unit of data to memory

• Processor to I/O
• The processor reads data from an I/O device via and I/O module

• I/O to Processor
• The processor sends data to the I/O device

• I/O to or from Memory: → (DMA

• For these two cases, an I/O module is allowed to exchange data directly with memory, without
going through the processor, using direct memory access.

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Common Types of Interconnection Structures

Over the years, a number of interconnection structures have been tried. By
far the most common are

1. the bus and various multiple-bus structures, an

2. point-to-point interconnection structures with packetised data transfer

[Point-to-point interconnection is not the scope of this course.]

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Bus Interconnection
• A bus is a communication pathway connecting two or more device
• A key characteristic of a bus is that it is a shared transmission medium
• A bus consists of multiple pathways or lines
• Each line is capable of transmitting signal representing binary digit (1 or 0)
• For example, an 8-bit unit of data can be transmitted over eight bus lines

• A sequence of bits can be transmit across a single line

• Several lines can be used to transmit bits simultaneously (in parallel)
• A bus that connects major components (CPU, Memory, I/O) is called System Bus
• The most common computer interconnection structures are based on the use of
one or more system buses.

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Bus Structure
• A system bus consists of 50-100 lines

• Each line is assigned a particular meaning or function

• On any bus the lines can be classi ed into 3 groups

• Data line
• Address line
• Control lines

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Data Lines
• Data lines that provide a path for moving data among system modules
• These lines, collectively, are called the data bus

• The data bus typically consist of 32, 64, 128, or more separate lines, the
number of lines is referred to as the width of the data bus

• Each line carry only 1 bit at a time, the number of lines determines how
many bits can transferred at a time - overall system performance.

• For example, if the data bus is 32 bits wide and each instruction is 64 bits long, then
the processor must access the memory module twice during each instruction cycle.

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Address Lines
• Used to designate the source or destination of the data on the data bus
• If the processor wishes to read a word of data from memory it puts the address of
the desired word on the address lines

• Width determines the maximum possible memory capacity of the system

• Also used to address I/O ports

• The higher order bits are used to select a particular module on the bus and the
lower order bits select a memory location or I/O port within the module.

• For example, on an 8-bit address bus, address 01111111 and below might reference
locations in a memory module (module 0) with 128 words of memory, and address
10000000 and above refer to devices attached to an I/O module (module 1).

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Control Lines (1/2)

• Used to control the access and the use of the data and address lines
• Because the data and address lines are shared by all components there
must be a means of controlling their use

• Control signals transmit both command and timing information among

system modules
• Timing signals indicate the validity of data and address information
• Command signals specify operations to be performed.

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Control Lines (2/2)

• Typical Control Lines include:
• Memory Write: causes data on the bus to be written into the addressed locatio
• Memory Read: causes data from the addressed location to be placed on the bu
• I/O Write: causes data on the bus to be output to the addressed I/O por
• I/O Read: causes data from the addressed I/O port to be placed on the bu
• Transfer ACK: indicates that data have been accepted from or placed on the bu
• Bus Request: indicates that a module needs to gain control of the bu
• Bus Grant: indicates that a requesting module has been granted control of the bu
• Interrupt Request: indicates that an interrupt is pendin
• Interrupt ACK: acknowledges that the pending interrupt has been recognize
• Clock: is used to synchronise operation
• Reset: initialises all modules
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The Operation of the Bus

• The operation of the bus is as follows

• If one module wishes to send data to another, it must do two things:

1. Obtain the use of the bu
2. transfer data via the bu

• If one module wishes to request data from another module, it must:

1. obtain the use of the bus, an
2. transfer request to the other module over the control and address lines,
then wait for that second module to send the data.

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