Microelectronics Reliability 54 (2014) 2723–2727

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Simulation of flicker noise in gate-all-around Silicon Nanowire MOSFETs

including interface traps
P. Anandan ⇑, A. Nithya, N. Mohankumar
S.K.P. Engineering College, Tiruvannamalai, Tamil Nadu, India

a r t i c l e i n f o a b s t r a c t

Article history: This paper presents a systematic investigation of flicker noise in Gate-all-around Silicon Nanowire
Received 3 July 2013 MOSFET. The 1/f noise is simulated in the presence and absence of interface traps. Moreover the device
Received in revised form 21 July 2014 is simulated under various distributions (Exponential, Gaussian, Uniform) of noise source. Nonuniformity
Accepted 27 July 2014
in the interface of the oxide/semiconductor region as gave rise to increase the threshold voltage, there by
Available online 18 September 2014
increasing the leakage current. The effect of interface traps on different distribution has been explored in
detail. The noise spectral density variations for various traps shows significant increase in flicker noise up
Keywords:
to a magnitude of under 6 ‘‘dB’’ for weak signals. The simulated results matches with the calibrated
Silicon Nanowire MOSFET
GAA (gate-all-around)
experimental data.
Flicker noise Ó 2014 Elsevier Ltd. All rights reserved.
Interface traps

1. Introduction
Silicon Nanowire (Si-NW) MOSFET is emerging as a promising
next-generation nanoscale device, exhibiting high ON/OFF current
ratio, ability to effectively suppress off-leakage current with its
gate-all-around configuration, excellent controllability of device
current and the immunity from the short-channel effects.
However, because of its nanoscale 3-D process configurations and
radial-shaped interface, the Si-NW MOSFETs shows large variations
in performance, especially in the flicker noise, compared with pla-
nar MOSFETs [1]. As well known, the flicker noise is caused by traps
in the oxide and interface and provides a convenient means for
extracting trap densities. Flicker noise is considered as one of the
factors limiting the quality of the device and its reliability.
The number fluctuation theory states that the flicker noise is
generated by fluctuation in the number of carriers due to charge
trapping in surface states. According to this theory, the spectral
density of the drain current is given by [2]:
K F q4 I2D NST
I2nfd ¼
n2 kTWLf ðC ox þ C SS þ C D þ C I Þ2
where NST – surface trap density, CSS – interface state capacitance,
CD – depletion capacitance, CI – inversion layer capacitance
KF is the gate voltage dependence flicker noise coefficient. W
effective channel width (W = pdnw, dnw – diameter of the
⇑ Corresponding author.
E-mail address: anandanvp2000@gmail.com (P. Anandan).
nanowire). NST is the density of traps at the quasi-Fermi level and
can be found as a function of energy if the gate voltage noise is
measured as a function of gate voltage.
The gate-voltage referred noise spectral density is given by [3]:
SV g ¼ SVFB ½1 þ al0 C ox jV gs  V T j2 ð2Þ
where a – scattering coefficient, l0 – low field mobility, Cox– unit
area gate capacitance, SVFB – flat band voltage noise density.
The flat-band voltage depends on the work function difference
between the gate material and the substrate material and the
equivalent (trapped or fixed) oxide charge density at the oxide-
silicon interface. The noise spectral density follows a 1/f c
dependence with the frequency exponent.
2
kkTq Nt
SVFB ¼ c ð3Þ
f WLC 2ox
where k – tunneling attenuation length, W – effective channel
width, Nt – trap density (cm3 eV1).
Traps are very important physical quantities that can drastically
ð1Þ
affect the electrical performance of a device. They act similarly to
doping, supplying free carriers, enhancing recombination, increas-
ing leakage and when charged, also contributing to a total charge
in the right-hand side of the Poisson equation, thereby influencing
device electrical behavior. Traps for various energy distributions
like level, exponential, gaussian and uniform are available. The
density of traps for exponential and gaussian trap energy distribu-
tions are as follows,
The trap density of the exponential distribution is:

http://dx.doi.org/10.1016/j.microrel.2014.07.145
0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
2724 P. Anandan et al. / Microelectronics Reliability 54 (2014) 2723–2727

  
E  E0 
Nmax exp   ð4Þ
Es 
The trap density of Gaussian distribution is:
!
ðE  E0 Þ2
Nmax exp  ð5Þ
Es

The generation of interface traps along the channel region shifts

the threshold voltage, reduces the drive current, shortens the hold-
ing time of dynamic memory transistors, increases leakage current,
Fig. 1. Schematic view of gate-all-around Silicon Nanowire MOSFET.
and consequently degrades device performance [4–7]. Interface
traps or stress generated during device operation is directly related
to transistor electrical characteristics and reliability as well as crit-
ical to device performance. Degradation of device reliability may
be exacerbated under the conditions of strong electric field and
high temperature (see Table 1).
There exist other techniques by which the oxide and interface
trap densities can be analyzed. For instance, the charge pumping
is one of the most extensively used techniques [8]. However, in
devices with small active area or silicon-on-insulator (SOI) struc-
tures, the charge pumping technique is not effective because it
requires sufficient bulk current for detecting the traps. On the
other hand, the flicker noise becomes larger as the channel length
is scaled down, and for its detection, the bulk electrode is not
needed. Hence, the flicker noise technique is suitable for evaluating
the trap density and its profile in devices, such as ultra small active
area planar FET, multigate FET, and NWFETs [9].
In this work, we address the simulation and characterization of
flicker noise in Silicon Nanowire MOSFET by considering interface
traps. The characteristic of flicker noise is investigated by obtaining
the spectral density as a function of frequency, gate to source volt-
age and drain current. The effect of interface traps is analyzed and
simulated for various distributions and the nature of interface trap Fig. 2. Id versus Vgs of Silicon Nanowire MOSFET.
density for each distribution is achieved. The simulation process is
done using a TCAD sentaurus device.
the applied gate voltage [10–15]. Therefore, interface traps could
significantly reduce the drain current. The interface trap density
2. Device structure and parameters
per unit energy is set to be 1011 cm2 eV1. The higher, the inter-
face-trap density, the more prominent effect of interface traps is
The schematic of the gate-all-around Silicon Nanowire MOSFET
on the device surface electric characteristics.
is shown in Fig. 1.
The thickness of the oxide layer (SiO2) is 2 nm, the Si core has a
diameter of 16 nm, the gate height thickness is 10 nm and the gate 3. Simulation results and discussion
length L of the device is 50 nm. We choose a n-type SiNW MOSFET
as a basis of our discussion, but its application to p-type is In this section, the simulation of flicker noise is done with and
straightforward. without interface traps. The analysis includes the investigation of
Fig. 2 shows the IdVgs transfer characteristics of n-type Silicon drain noise current as a function of frequency and gate voltage,
Nanowire MOSFET for both with and without interface traps. The power spectral density of flicker noise and trap density for various
transfer characteristics of SiNW MOSFET investigated without energy distributions.
traps have threshold voltage of 0.5 V. For various interface trap Fig. 3 shows the simulated drain noise current as a function of
density, various energy distributions like exponential, gaussian frequency at the gate voltage of 1 V. The frequency range of
and uniform is obtained and the corresponding IdVgs transfer 10 GHz is selected to observe device performance under various
characteristics are obtained. The interface traps shift the threshold distributions. As expected, the non-trapping noise and interface-
voltage, the slope of drain current (Id) is distorted increasingly as trapping noise shows 1/f noise spectrum. The interface-trapping
the gate to source voltage is increased. Not all interface traps are noise is analyzed under different energy distributions like expo-
trapped with a charge (electron or hole) and the charge trapping nential, gaussian and uniform. The change of slope due to the Non-
rate depends on the surface carrier concentration, the interface- uniform distribution of traps mainly due to random fluctuations in
trap charge not only depends on the interface-trap density but also the number of carriers in the channel, based on the statistical time
dependence of the capture and release of carriers by traps and
these effects are observed in simulation and also validated with
Table 1
Trap density parameters. experimental data [16].
Fig. 4 shows the simulated drain noise current as a function of
Parameter Physical meaning
gate voltage. Three different distributions with respect to interface
Dit Interface trap density 1011 cm2 eV1 trap density are considered. When the gate voltage is below the
E & E0, Es EnergyMid and EnergySig trap distribution parameter
threshold voltage, i.e., 0.5 V for this simulation, the spectral density
Nmax Maximum trap density parameter
of the drain noise current shows a very small value. While the
 P. Anandan et al. / Microelectronics Reliability 54 (2014) 2723–2727
Fig. 3. Spectral density of drain current as a function of frequency.
Fig. 4. Spectral density of drain current as a function of gate to source voltage.
signal is larger than the trap density will increase in the interface
traps, drain current decreases and leakage current increases. That
traps affect 1/f noise shows that applying a large voltage on gate
induces an increase in the number of traps, and this correlates to
increased flicker noise.
Fig. 5 shows the simulated electron voltage spectral density due
to flicker GR as a function of the gate to source voltage. The voltage
spectral density of electrons due to flicker GR local noise source is
achieved by taking into account of interface traps. The number of
free electrons in the conduction band may fluctuate because of
generation and recombination processes between the band and
traps. Generation–recombination processes exchange carriers
between the conduction band and the valence band. For each
individual generation or recombination process, the electrons
and holes involved appear or vanish at the same location.
Fig. 6 shows the simulated current spectral density as a function
of drain current. A small slope deviation is observed for the inter-
face traps comparing to the shape of current spectral density with-
out traps, this is due to the distorted movement of charge carriers
at the interface. The 1/f noise is consistent with the charge carrier
trapping/detrapping process that is near the Si/SiO2 interface, is the
dominant mechanism with negligible scattering. Device with and
without interface trap density are simulated under different
2725
Fig. 5. Electron voltage spectral density due to flicker GR as a function of the gate to
source voltage.
Fig. 6. Current spectral density versus drain current.
distributions and shows the difference in Current spectral density
versus drain current curves. Because, trapped charges at the SiO2/
Si interface along the surface channel region can significantly
impact the surface potential and also the gate voltage modulation,
which impact and affect the behavior of the drain–source current
and terminal charges in SiNW.
Fig. 7 shows the simulated voltage spectral density as a function
of drain current. Interface traps with different energy distributions
are taken into account for simulation. A discernible slope differ-
ence is observed among the noise curves for three different trap
energy distributions. Because, the existence of interface-trap
charges lowers the surface carrier density and gate-voltage
modulation.
In a device with no traps, the number fluctuation noise is com-
pletely eliminated, which evidently reduces the low frequency
noise significantly. The interface traps shift the threshold voltage,
reduce the drive current, increase leakage current and accordingly
increase device power consumption. Not all interface traps are
trapped with a charge (electron or hole) and the charge trapping
rate depends on the surface carrier concentration, which is
2726 P. Anandan et al. / Microelectronics Reliability 54 (2014) 2723–2727
Fig. 7. Voltage spectral density versus drain current.
modulated by gate voltage. The interface-trap charge not only
depends on the interface-trap density but also the applied gate
voltage. As a result, the interface traps could drastically reduce
the drain current and meanwhile, the neutral interface-traps
increases the drain current and also decreases the spectral density
of drain current.
Fig. 8 shows the plot of power spectral density as a function of
drain current. The power spectral density of flicker noise in Silicon
Nanowire MOSFET is investigated for different trap energy distri-
butions like exponential, gaussian and uniform. An apparent differ-
ence is observed in the power spectral density of noise for trap
energy distribution and shows there is a increase in flicker noise
up to a magnitude of 6 ‘‘dB’’ for weak signals.
Trapped charge density, trap occupation probability, and trap
density quantities as functions of energy are trap spatial location
within a specified material, at which a trap distribution or occupa-
tion must be analyzed using different distributions because its
important to include interface traps when investigating device
properties.
Fig. 9 shows the trap density for various trap energy distribu-
tions. The plot shows variation of trap density for each distribution.
Fig. 8. Power spectral density as a function of drain current.
Fig. 9. Trap density versus energy for different distributions.
The traps are considered to be located at the Si/SiO2 interface. The
performance evaluation using different distributions (Gaussian,
exponential, uniform) represents a energy distributed trap inside
a material band gap, controlled by the energy reference point,
EnergyMid parameters. Trap concentration is given in cm3 * eV1
(bulk traps) or cm2 * eV1 (interface traps). The interface trap
density (Dit) per unit energy is set to be 1011 cm2 eV1. Each dis-
tribution shows the energy distributed trap inside a material band
gap, controlled by the energy reference point. The flicker noise
spectral density differs for various distributions of interface traps.
The interface traps capture or emit carrier, which dynamically
changes the carrier quasi fermi level location inside a semiconduc-
tor material. The noise spectral density due to uniform distribution
is more comparing to gaussian and exponential distributions, since
traps are uniformly distributed inside a material.
4. Conclusion
In conclusion, we investigated and study the effect of flicker
noise under the influence of interface traps are characterized and
simulated successfully. The effect of flicker noise on different inter-
face traps distributions thoroughly investigated. An increase in the
electron density will subsequently increase the concentration of
interface traps which are randomly spaced at the oxide region
increasing the flicker noise. Uniformly distributed traps show
increase in 1/f noise up to 6 ‘‘dB’’ in magnitude. The effect of inter-
face traps on the drain current for various ranges of frequencies are
simulated under various spectral densities matches with
experimental data.
References
[1] Baek Rock-Hyun, Baek Chang-Ki, Choi Hyun-Sik, Lee Jeong-Soo, Yeoh Yun
Young, Yeo Kyoung Hwan, et al. Characterization and modeling of 1/f noise in
Si-nanowire FETs: effects of cylindrical geometry and different processing of
oxides. IEEE Trans Nanotechnol 2011;10(3).
[2] Lundberg Kent H. Noise sources in bulk CMOS; 2002.
[3] Wei Chengqing, Yu Jiang, Xiong Yong-Zhong, Zhou Xing, Singh Navab, Subhash
C, et al. Impact of gate electrodes on 1/f noise of gate-all-around silicon
nanowire transistors. IEEE Electron Dev Lett 2009;30(10).
[4] Kumar A, Fischetti MV, Ning TH, Gusev E. Hot-carrier charge trapping and trap
generation in HfO2 and Al2O3 field-effect transistors. J Appl Phys
2003;94:1728.
[5] Bekaddour Abderrezak, Pala Marco G, Chabane-Sari Nasr-Eddine, Ghibaudo
Gérard. Deterministic method to evaluate the threshold voltage variability
induced by discrete trap charges in Si-nanowire FETs. IEEE Trans Electron Dev
2012;59(5).
 P. Anandan et al. / Microelectronics Reliability 54 (2014) 2723–2727
[6] Pud S, Li J, Petrychuk M, Feste S, Offenhäusser A, Mantl S, et al. Noise
spectroscopy of traps in silicon nanowire field-effect transistors. IEEE 2011.
[7] Jiang Y, Liow TY, Singh N, Tan LH, Lo GQ, Chan DSH, et al. Nanowires FETs for
low power CMOS applications featuring novel gate-all-around single
metal FUSI gates with dual Um and VT tune-ability. IEDM Tech Dig 2008:
869–72.
[8] Chu YL, Lin DW, Wu CY. A new charge-pumping technique for profiling the
interface-state and oxide-trapped charges in MOSFET’s. IEEE Trans Electron
Dev 2000;47(2):348–53.
[9] Hong BH, Cho N, Lee SJ, Yu YS, Choi L, Jung YC, et al. Subthreshold degradation
of gate-all-around silicon nanowire field-effect transistors: effect of interface
trap charge. IEEE Electron Dev Lett 2011;32(9).
[10] Chen Zuhui, Zhou Xing, Zhu Guojun, Lin Shihuan. Interface-trap modeling for
silicon-nanowire MOSFETs. IEEE Trans Electron Dev 2010.
2727
[11] Hong Sung-Min, Park Chan Hyeong, Park Young June, Min Hong Shick. Physics-
based analysis and simulation of 1/f noise in MOSFETs under large-signal
operation. IEEE Trans Electron Dev 2010;57(5).
[12] Hooge FN. 1/f noise sources. IEEE Trans Electron Dev 1994;41(11).
[13] Jing Z, Wang R, Huang R, Tian Y, Zhang L, Kim DW, et al. Investigation of low-
frequency noise in silicon nanowire MOSFETs. IEEE Electron Dev Lett
2009;30(1).
[14] Wei C, Xiong YZ, Zhou X, Singh N, Rustagi SC, Lo GQ, et al. Investigation of low-
frequency noise in silicon nanowire MOSFETs in the subthreshold region. IEEE
Electron Dev Lett 2009;30(6).
[15] Vandamme LKJ, Hooge FN. What do we certainly know about 1/f noise in
MOSTs? IEEE Trans Electron Dev 2008;55(11).
[16] Colin MC Andrew. Unified flicker noise model. Freescale Semiconductor
Tempe, Az.