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    memory

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    8 views23 pages

    Test

    Uploaded by

    Abhishek Singhania
    memory

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 23

    VLSI Design

    Memory

    BITS Pilani
    K K Birla Goa Campus November 13, 2017
    Memory classification
    VLSI Design

    1 Memory classification

    Memory Array
    Architecture

    SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    Memory Array Architecture
    VLSI Design

    Memory classification

    2 Memory Array
    Architecture

    SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM Read operation
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    3 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM Read operation
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    4 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM Read operation
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    5 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM write operation
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    6 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM write operation
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    7 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell stability
    VLSI Design
    Hold margin
    Memory classification

    Memory Array
    Architecture

    8 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell stability
    VLSI Design
    Read margin
    Memory classification

    Memory Array
    Architecture

    9 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell stability
    VLSI Design

    Write margin Memory classification

    Memory Array
    Architecture

    10 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell read analysis
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    11 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell read analysis
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    12 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell read analysis
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    13 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell write analysis
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    14 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM cell write analysis
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    15 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    Resistive load SRAM
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    16 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    SRAM comparison
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    17 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    8T dual-port SRAM cell
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    18 SRAM

    DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    3T DRAM cell
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    SRAM

    19 DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    1T DRAM cell
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    SRAM

    20 DRAM

    Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    Sensing circuits
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    SRAM

    DRAM

    21 Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus
    Sensing circuits
    VLSI Design

    Memory classification

    Memory Array
    Architecture

    SRAM

    DRAM

    22 Memory peripheral
    circuits

    BITS Pilani K K Birla Goa


    22 Campus

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