SYSTEM ON CHIP DESIGN : ECE5025

Lecture:9-10 (In last lecture)

Design Process for Soft Firm and Hard Cores

Dr. Vikas Vijayvargiya

Sr. Assistant Professor
Department of Micro and Nano-Electronics
School of Electronics Engineering
1
 SYSTEM ON CHIP DESIGN : ECE5025
Lecture:11-12
Design Methodology for Memory and Analog Cores

Dr. Vikas Vijayvargiya

Sr. Assistant Professor
Department of Micro and Nano-Electronics
School of Electronics Engineering
2
 System on Chip Design Methodology

Design Methodology Part-I

Logic Design Methodology : Soft, Firm and Hard Core

 System on Chip Design Methodology

Design Methodology Part-II

Memory Analog Circuit

 System on Chip Design Methodology

Design Methodology Part-II

Memory Analog Circuit

 Multiple SRAM,  DACs,

 Multiple ROM,  ADCs
 Large DRAM,  PLL
 Flash Memory Blocks
 System on Chip Design Methodology

Design Methodology Part-II

Memory Analog Circuit

 Multiple SRAM,  DACs,

 Multiple ROM,  ADCs
 Large DRAM,  PLL
 Flash Memory Blocks

Sensitive to Noise and Technology parameter

 System on Chip Design Methodology

Design Methodology Part-II Hard Cores are

generally used

Memory Analog Circuit

 Multiple SRAM,  DACs,

 Multiple ROM,  ADCs
 Large DRAM,  PLL
 Flash Memory Blocks

Sensitive to Noise and Technology parameter

 Design Methodology for Embedded Memory

Why large embedded memories ?

 Design Methodology for Embedded Memory

Why large embedded memories

SoC (Present day ) Embedded memories : 50% to 60% of the SoC

 Design Methodology for Embedded Memory

Why large embedded memories

SoC (Present day ) Embedded memories : 50% to 60% of the SoC

 Multiple SRAM,
 Multiple ROM,
 Large DRAM,
 Flash Memory Blocks
Embedded Memory in System on Chip (SoC)
 Design Methodology for Embedded Memory

The motivations of large embedded memories include:

 Design Methodology for Embedded Memory

The motivations of large embedded memories include:

 Significant reduction in cost and size by integration of memory on the chip

 Replacing large off-chip drivers with smaller on-chip drivers.

 This helps reduce the capacitive load, power, heat, and length of wire
required

 Elimination of pad limitations of off-chip modules

 Design Methodology for Embedded Memory

Challenges ( large DRAM with logic) :

 Design Methodology for Embedded Memory

Challenges ( large DRAM with logic) :

 Adds significant complexity to the fabrication process
 It increases mask counts, which affects cost
 Memory density and therefore impacts total capacity
 Timing of peripheral circuits
 Overall system performance
 Design Methodology for Embedded Memory

More Challenges : At Sub-nanometer dimension

 More complex and more trade offs required to solve them

 .The number of PVT (process, voltage and temperature) corners that are
required to accurately characterize memory has gone up significantly
 Design Methodology for Embedded Memory

Optimize large DRAM and logic

 To integrate large DRAM and logic

 Recent manufactures have developed dual gate process

 Two different types of gate oxides optimized for DRAM and Logic Transistors
 Design Methodology for Embedded Memory

Two Parameter need to consider to Optimize large DRAM and logic

Density Performance
 Design Methodology for Embedded Memory

Cell Area and Mask count significantly affected

Design Methodology for Embedded Memory

Why Performance of 1-T Cell low

Design Methodology for Embedded Memory

Why Performance of 1-T Cell low

 Design Methodology for Embedded Memory

Important Note:
To simplify design complexity resulting from the use of two sets
of parameters and the existing memory design technology,
memory manufacturers and fabs have developed DRAM and
flash memory cores and provided them to the SoC designers
 Design Methodology for Embedded Memory

Important Note:
To simplify design complexity resulting from the use of two sets
of parameters and the existing memory design technology,
memory manufacturers and fabs have developed DRAM and
flash memory cores and provided them to the SoC designers
Design Methodology for Embedded Memory : Circuit Techniques

Memory circuits have main design optimization Criteria

Area (Storage Cell) Higher speed and Lower noise

(Address Decoders and Sense
Amplifiers )
Array-Structured Memory Architecture
Design Methodology for Embedded Memory : Circuit Techniques

Memory Cell :

Six-transistor SRAM cell Three-transistor DRAM cell

Design Methodology for Embedded Memory : Circuit Techniques

6-T SRAM Memory Cell : READ ACCESABILITY

 Small bump during the pre charging

may flip the data of the back to
back inverter

 Fixing the timing for the Smaller

and Longer bit lines are difficult

Six-transistor SRAM cell

Design Methodology for Embedded Memory : Circuit Techniques

6-T SRAM Memory Cell : WRITABILITY

 Lower VDD - There is not enough

drive strength for the pass gates to
flip

Six-transistor SRAM cell

Design Methodology for Embedded Memory : Circuit Techniques

6-T SRAM Memory Cell : WRITABILITY

 Lowest VDD – SNM (overlap)

reduces from tech to tech , so
differentiate the high and low level
becomes difficult

 Lowest VDD @ which a memory can

retain its value –Retention Voltage

Six-transistor SRAM cell

Design Methodology for Embedded Memory : Circuit Techniques

6-T SRAM Memory Cell :

 Designing the pass gates to meet
stability and write ability is difficult
in SRAM Design

• When Vth is more - stability is

good and Write ability is poor

• When Vth is less – write ability is

good and stability is poor.

Six-transistor SRAM cell

Design Methodology for Embedded Memory : Circuit Techniques
Design Methodology for Embedded Memory : Circuit Techniques
Memory Circuit Elements :

One-transistor DRAM cell flash cell

 Design Methodology for Embedded Memory : Circuit Techniques

Write Circuit

Differential SRAM Sense Amplifier

Differential DRAM sense amplifier

Design Methodology for Embedded Memory : Circuit Techniques

Structure of commonly used memories in various SoC applications :

Two-port Memory
 Design Methodology for Embedded Memory : Circuit Techniques

Structure of commonly used memories in various SoC applications :

Content-addressable Memory
Design Methodology for Embedded Memory : Circuit Techniques

Structure of commonly used memories in various SoC applications :

Doubled buffer Memory

Design Methodology for Embedded Memory : Circuit Techniques

Sense Amplifier :

Functional Parameter DC Parameter AC Parameter

Design Methodology for Embedded Memory : Circuit Techniques

Sense Amplifier :

Functional Parameter DC Parameter AC Parameter

Fully characterized through a test chip or extensively simulated

Design Methodology for Embedded Memory : Circuit Techniques

Sense Amplifier :

Functional Parameter

Supply currents: The current source/sink by the amplifier power supplies

Output voltage swing (VOP): The maximum output voltage swing that can be
achieved for a specified load without causing voltage limiting.

Closed-loop gain: The ratio of the output voltage to the input voltage when
the amplifier is in a closed-loop configuration.
Design Methodology for Embedded Memory : Circuit Techniques

Sense Amplifier :

DC Parameter

Input offset voltage (VIO): The DC voltage that is applied to the input terminals to force
the quiescent DC output to its zero (null)

Input offset voltage temperature sensitivity : The ratio of the change of the input offset
voltage to the change of circuit temperature

Input bias current (+IB, -IB): The currents flowing into the noninverting and inverting
terminals individually to force the amplifier output to its zero (null) voltage

Common mode rejection ratio (CMRR):

Design Methodology for Embedded Memory : Circuit Techniques

Sense Amplifier :

AC Parameter

Small-signal rise time (tR): The time taken by the output to rise from 10% to
90% of its steady-state value in response to a specified input pulse.

Settling time (tS): The time required by the output to change from some
specified voltage level and to settle within a specified band of steady-state
values, in response to a specified input.

Slew rate (SR): The maximum rate of change of output voltage per unit of
time in response to input.
Design Methodology for Embedded Memory : Circuit Techniques

Sense Amplifier :

Functional Parameter DC Parameter AC Parameter

Many more parameters need to study

 Memory Compiler

Memory Complier

The majority of memories in present-day SoCs are developed

 Memory Compiler

Memory Complier (Framework Includes)

Physical Logical Electrical

Representations in design data bus

 Memory Compiler

Memory Complier (Framework Includes)

Physical Logical Electrical

Linked with front-end design tools

 Memory Compiler

Memory Complier (Framework Includes)

Physical Logical Electrical

Linked with front-end design tools

Generate data
 Memory Compiler

Memory Complier (Framework Includes)

Physical Logical Electrical

Linked with front-end design tools

Generate data

Used by back-end tools

Memory Compiler Flow
Memory Compiler Flow

Compiler generates the

memory block

 Based on user-specified size

 Configuration
• Rows/columns,
• Word size
• Column multiplexing
 Memory Compiler Examples

To support these compilers, standard cell libraries and I/O libraries are
also provided.
Some example compilers include these:
 High-density single-port SRAM generator
 High-speed single-port SRAM generator
 Memory Compiler Examples

To support these compilers, standard cell libraries and I/O libraries are
also provided.
Some example compilers include these:
 High-density single-port SRAM generator
 High-speed single-port SRAM generator
 High-speed dual-port SRAM generator
 High-speed single-port register file generator
 High-speed two-port register file generator
 Specifications of Analog Circuits

Design Methodology Part-II

Memory Analog Circuit

 Multiple SRAM,  DACs,

 Multiple ROM,  ADCs
 Large DRAM,  PLL
 Flash Memory Blocks
 Specifications of Analog Circuits

Design Methodology Part-II

Hardly 5% of SoC area.

Memory Analog Circuit

 Multiple SRAM,  DACs,

 Multiple ROM,  ADCs
 Large DRAM,  PLL
 Flash Memory Blocks
 Specifications of Analog Circuits

The primary design issue in analog circuits ( For SoC Design)

The precise specifications of various parameters

Specifications of Analog Circuits (ADC)
 Specifications of Analog Circuits
Specifications of ADC (Parameter)
Functional DC
 Resolution  Supply currents
 Major transitions  Output logic levels (VOL, VOH)
 Reference voltage  Input leakage currents
 Full-scale range (FSR)  Output high impedance currents
 Offset error  Output short-circuit current
 Gain error  Power supply sensitivity ratio
 Gain error drift  Differential linearity error
 LSB size  Monotonicity:
 Integral linearity error (INL)
 Accuracy
AC
 Input bandwidth
 Conversion time
 Conversion rate
 Aperture delay time
 Aperture uncertainty
 Transient response time
 Dynamic integral linearity:
 Overvoltage recovery time
 Dynamic differential linearity
 Signal-to-noise ratio (SNR)
 Effective number of bits (ENOB)
 Signal-to-noise and distortion
 Specifications of Analog Circuits
Specifications of ADC (Parameter)

Functional DC AC