Low-Power CMOS SRAM

By:
Tony Lugo
Nhan Tran

Adviser: Dr. David Parent
OUTLINE
1 Introduction
2 SRAM Architecture
3 Design Strategy: Self-Timing Concept
4 Design Considerations
5 Conclusion
1 Introduction
1.1: More Memory, More Possibilities, More Power Consumption
Memory is used widely in all electrical systems: mainframes,
microcomputers and cellular phones, etc.
More memory means more information, make the system run faster
but more power consumption--------------> The need for low power
memory
With the emerging of portable and compact devices such as smart
cards, PDAs -------------> The need for low power memory
The demand for Low-Power Memory is very great.


1 Introduction
1.2: Project Goal
Design and characterize an embedded Low-Power, synchronous
CMOS SRAM module in 0.25um process
Wide range applications in electric consumer chips, specially in
ASIC
This memory has a Low AC power consumption

P=V
2
.f.C

2 SRAM Architecture
2.1: Design Specification and Features
Configuration: 64x4m4 (256 bits)
Low voltage operation: 2.25V-2.75V
Zero DC power consumption
Self-timed to reduce AC power consumption and cycle time
Access time: 5.0 ns
Performance: 200 MHz for clock cycle in worst case performance
Power consumption: 0.15 mW/MHz at typical power consumption


2 SRAM Architecture
2.2: Logic Block Diagram
Address latch
& Pre-decoder Control Circuit
Memory Array
Pre-charge & Equalize circuit
Column Decoder
Sense Amplifier
Write
Circuit
Output Buffer/
Tristate
Row Decoder
q[3:0]
d[3:0]
clk
ce
we
oe
a[5:0]
2 SRAM Architecture
2.3: Timing Diagram
READ Cycle

clk
a[i]
we
ce
q[i]
t
AS
t
AH

t
ACC

previous data output valid output valid
output
tristate
2 SRAM Architecture
2.3: Timing Diagram (continued)
WRITE Cycle

clk
a[i]
we
ce
d[i]
t
AS
t
AH

t
DH
t
DS
3 Self-Timing
3.1: SRAM Cell Operation and Short Circuit Current

vdd
gnd
wl
bl
bln
Bitline leakage
current
3 Self-Timing
3.1: SRAM Cell Operation and Short Circuit Current (continued)
Turn on word line (wl) to write to and read from a SRAM cell
Bitline leakage current will appear and dissipate power
Turns on wl long enough to access a SRAM cell, then turn off wl to
save power

3 Self-Timing
3.2: Save Even More Power:
Turning off Pre-Decoder, Row-Decoders and Column Decoder.
Also, in read cycle, every Sense Amplifier can be turned off as long it
finishes sensing data to output

3 Self-Timing
3.3: Self-Timing Signal
Self-Timing Signal generated by memory itself like a feed back loop
Pre-charges the bit lines and makes the memory get ready for the
next evolution
A reference cell (or dummy) is stored (hard coded) with 0 or 1
This cell is get accessed whenever the memory start an evolution
(either READ or WRITE cycle)
3 Self-Timing
3.3: Self-Timing Signal Scheme
Row Decoder
SRAM cell
Mux
Sense Amplifier
Column Decoder
Dummy Cell
Dummy Sense
Amplifier
3 Self-Timing
3.3: Timing Diagram with Self-Timing Signal
clk
self-timing
signal
wl
clksa
4 Design Considerations
4.1: SRAM Cell ( 6 T): Schematic
4 Design Considerations
4.1: SRAM Cell ( 6T): Layout
4 Design Considerations
4.1: SRAM Cell ( 4T): Schematic
4 Design Considerations
4.1: SRAM Cell ( 4T): Layout
4 Design Considerations
4.1: SRAM Cell : d vs. dn
4 Design Considerations
4.1: SRAM Cell : Static Noise Margin (SNM)
SNM depends only on threshold voltage, VDD and the
transconductance factor k ratio or cell ratio, not on the absolute
value of ks.
SNM increase with cell ratio (k
Wn
/k
Wp
) but if it is too high, it is hard to
write
Cell stability is controlled by the cell ratio (k
Wn
/k
Wp
) and effected by:

Bitline bias
Asymmetry (Offsets)
Statistical variations -Defects



4 Design Considerations
4.2 Clock-sense Amplifier: Schematic
4 Design Considerations
4.2 Clock-sense Amplifier : Layout
4 Design Considerations
4.2 Clock-sense Amplifier : Plot
4 Design Considerations
4.2 Clock-sense Amplifier : Clock Sense-Amplifier
Latch is very high gain
V at Clock () rise must be sufficient to reliably set latch
--- Offset voltage, cap mismatch
--- Limits speed compared to static sense-amp
Maintain high performance by limiting voltage swing
t = [C(B/L)/I
read
]* V
Sense Amplifier Clock often generated with self-timing signal

4 Design Considerations
4.3 Control Block: Schematic
4 Design Considerations
4.3 Control Block: Layout
4 Design Considerations
4.3 Control Block: Layout
4 Design Considerations
4.3 Top Level: Schematic
4 Design Considerations
4.3 Top Level: Layout
4 Design Considerations
4.3 Top Level: Plot
4 Design Considerations
4.3 Top Level: Plot
4 Design Considerations
4.3 Top Level: Power
5 Conclusion

SRAM architecture with Self-Timing signal
1. Can save AC Power significantly
2. Uses up little area in the design
Access time of SRAM
1. Limited/enhanced by the fan-out of the word line driver
2. Bit-line multiplexer incurs delay



5 Conclusion
Current and future trends in SRAM design
A. IBM and Motorola collaborated to build SRAM with copper
interconnects
Advantages:
1. A ramp up in frequency
2. Very small access times
3. Memory cells use higher threshold voltage (V
t
)
Future trends
A. Intel built a one-square micron SRAM cell on its 90-nm process
technology
1. 52-Mbit chips
2. SRAM chips aid building and testing