Unit 1: HDL Design

1. What are subprograms? Write VHDL function and procedure for Full Adder.
OR
1. With VHDL codes explain Function and Procedure.
2. What is test bench? With VHDL code Explain synthesizable and Non-
synthesizable test bench.
3. Write short note on (a) Package, (b) Entity & Architecture, (c) Attributes.
4. What are the different modeling styles in VHDL? Explain with example.
5. Explain Data objects and Data types with suitable examples.
6. Write/Explain any three sequential statements with examples.
7. Write/Explain any three con-current statements with examples.
8. What are the types of simulation? Explain simulation process with examples.
9. What is synthesis? Explain the synthesis process. What are the advantages of
synthesis?
10. Draw state diagram & write VHDL code for
o traffic light controller
o Lift controller
11. Write VHDL code using structural modeling style for
o 4-bit Full Adder
o 4-bit Universal Shift register
o 3-bit UP/DOWN Counter with mode control & Asynchronous RESET
12. Write VHDL code using Behavior/Sequential modeling style for
o D or T Flip Flops
o S-R or J-K Flip Flops
o 8:1 or 4:1 MUX
o 4-bit ALU with 4-Arithmetic & 4-Logical Operations
13. Explain the following used in VHDL with the help of suitable examples.
o wait statements
o Generate statement
o Configuration
o operator overloading

.
 Unit 2: Digital Design & Issues

1. What is meta-stability? What are the solutions of it?

2. Write difference between Mealy & Moore Machine.

3. Write short note on 1) Clock jitter 2) EMI immune chip design 3) Off
Chip connections 4) Clock Skew 5) Supply and Ground bounce.

4. What is Clock skew? What are techniques to minimize?

5. Why should supply & ground bounce be taken care? How are these minimized?

6. What are the different Clock distribution techniques available for the VLSI
design?

7. Explain Power distribution and Power optimization techniques.

8. Explain interconnect Routing Techniques OR Explain Global routing & switch

Box routing.

9. What is the wire parasitic? How it affect the performance in the VLSI design?

10. Explain different Signal Integrity issues.

11. Explain input pad design, output pad design and 3-state pad design in chip OR
Explain I/O Architecture in detail.

12. Write VHDL code for FSM which will detect the sequence 1 0 1 1 0 by Moore
method.

13. Write VHDL code for Mealy machine shown in figure

Clock Sequence
Detector Fout
Input 1101
 Unit 3: PLD Architectures and Applications

1. Compare the
o EPROM, PAL & PLA
o CPLD, FPGA & ASIC
2. Explain the following terms 1) CLB 2) UCF 3) GRM 4) EDIF
3. Explain the logic implemented in FPGA & logic implemented in CPLD.
4. Explain with diagram SRAM & Anti-fusable Generic FPGA architecture. What
factors are considered to make a choice in between them?
5. Draw the block diagram & Explain architecture in detail of
o CPLD
o FPGA
6. Explain the features & limitations of CPLD and FPGA devices.
7. Write the specifications of the devices
o FPGA
o CPLD
8. What is necessity of PLDs? Write the applications of CPLD, FPGA and ASIC.
9. Draw and explain the following terms for CPLD
o Macro-Cell
o Functional Block
o Programmable Interconnect & I/O Block
10. Explore CPLD/FPGA oriented design flow.
11. Explain different types of memories.
 Unit 4: Digital CMOS Circuits

1. Draw voltage transfer characteristics of CMOS inverter and explain different

regions of operation of NMOS and PMOS transistor.
2. Write short note on 1) Body Effect 2) Power delay product 3) Hot electron
effect 4) velocity saturation 5) Noise Margin
3. What is Static, Dynamic and Short circuit Power dissipation in CMOS? Derive
the expression for Total Power dissipation. What are the components which
makes the power dissipation in the circuits?
4. Derive the expressions for Power dissipations in CMOS. What are the techniques
to minimize the dissipations?
5. What is technology scaling? Explain three ways of scaling the devices.
6. Explain different Design Rule Check in terms of λ- parameters.
7. What is DRC? Explain in detail Design Rules in CMOS VLSI design.
8. Explain, why the ratio of βn / βp should be equal to be one for CMOS inverter?
9. Design CMOS logic for Y = A B + C D + E. Calculate W/L ratio for NMOS
and PMOS area needed on chip.
10. Explain Transmission Gate. States its advantages. Implement a circuit of 2:1
multiplexer using TG. Comment on the number of transistor required using TG &
conventional method.
11. Draw 8:1 Multiplexer using transmission gates. Compare this schematic with
conventional design.
12. Explain the following
o Velocity Saturation
o Body Effect
o Hot Electron Effect/Impact ionization
o Channel length Modulation
o Power delay product
 Unit 5: Application Specific Integrated Circuit

1. Explain in detail CMOS IC design flow.

2. Explain briefly cell design specifications.
3. What is SPICE? Explain with design flow SPICE simulation.
4. What is need of layout design rules? Which lambda rules are used for CMOS layout?
Give its significance.
5. List and Explain micron rules.
6. What is DRC? Explain in detail design rules in CMOS VLSI design.
7. Explore different types of simulations involved in high level design flow. Explore post
layout simulation in detail.
8. What are the design issues in VLSI Chips
9. Write short note on
o Timing Analysis
o Electrical Rule Check
o Floor Planning
 Unit 6: VLSI Testing & Analysis

1. What are the stuck open and stuck short faults? Also explain stuck at 1 and stuck
at 0 faults with an examples.

2. Why there is need of Design for Testability? Explain Controllability,

Observability and Predictability with the help of example.

3. What is Test Access Port? Draw and explain the state diagram of TAP controller.

4. Define fault coverage. Explain logical and physical faults in detail.

5. What is need of Boundary scan check? Explain boundary scan architecture.

6. What is scan path? Give advantage and disadvantage of scan path.

7. Explain JTAG boundary scan. Which are the various pins involved.

8. Explain partial and full scan check.

9. Compare Testability and Verification.

10. What is Built in Self Test? Explain self test circuit for RAM.

11. Explain the following terms

o JTAG

o Partial Scan

o Full Scan