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System Verilog Interview Questions With Answers
System Verilog Interview Questions With Answers
The basic difference between these two are evident from the nomenclature, i.e, Initial block starts
getting executed during simulation time t=0 while the Final block gets executed when the simulation is
completed.
Before getting into details, there is one similarity between these two sequential block of codes, both of
them gets executed only once during the simulation
Now getting back to the difference between Initial and Final blocks, Initial blocks can contain some #
delays or wait statements or some wait for events, but the Final block should not contains any such
things.
Final block should get executed with 0 simulation time. Ideally this is used for test case status reporting
or some display statements that have to be printed after the test case execution is completed
Here are some pointers from “System verilog for Verification” by Chris Spear that will enhance your
understanding of the simulation phases for system verilog.
Build Phase
– Generate configuration : Randomize the configuration of the DUT and surrounding environment
– Build environment : Allocate and connect the testbench components based on the configuration.
A testbench component is one that only exists in the testbench, as opposed to physical components in
the design that are built with RTL.
– Reset the DUT
– Configure the DUT : Based on the generated configuration from the first step, load the DUT command
registers
Run Phase
– Start environment : Run the testbench components such as BFMs and stimulus generators
– Run the test : Start the test and then wait for it to complete. It is easy to tell when a directed test has
completed, but doing so can be complex for a random test. You can use the testbench layers as a
guide. Starting from the top, wait for layer to drain all the inputs from the previous layer (if any), wait
for the current layer to become idle, and wait for the next lower layer. You should use time-out
checkers to make sure the DUT or testbench does not lock up.
Wrap-up Phase
– Sweep : After the lowest layer completes, you need to wait for the final transactions to drain out of
the DUT.
– Report : Once DUT is idle, sweep the testbench for lost data. Sometimes the scoreboard holds the
transactions which never came out, perhaps because they were dropped by the DUT. Armed with this
information, you can create the final report on whether the test passed or failed. If it failed, be sure to
delete any functional coverage results, as they may not be correct.
// packed array
// unpacked array
class ASICwithAnkit ;
int a ;
function new (int a);
this.a = a;
endfunction : new
endclass : ASICwithAnkit
//Class instantiation and usage
ASICwithAnkit AwA = new (123);
$display ("AwA.a = %d,", AwA.a);
Alias
is system verilog coding technique to model bi-directional mapping for ‘inout’ ports or wires in a
module. In particular, alias mapping is direct connection of one inout port to other. In other way, its a
short-circuit of wires
module tomap
inout [2:0] A, B;
);
// alias 1
endmodule
Randomization
You first create a class to hold a group of related random variables, and then have the random-solver fill
them with random values.
In systemverilog which array type is preferred for memory declaration and why Modeling memories
larger than a few megabytes should be done with an associative array. Note that each element in an
associative array can take several
pointer overhead.
How to avoid race round condition between DUT and test bench in
systemverilog verification
A race condition is a flaw in a system or process that is characterized by an output that exhibits an
unexpected dependence on the relative timing or ordering of events.
As far as I can tell, a program block by itself only addresses two race conditions between the testbench
and DUT, both of which are covered by using a clocking block by itself.
Erroneous use of blocking assignments for sequential logic. You have a race within your DUT regardless
of the race between your testbench and DUT.
Erroneous use of non-blocking assignments in combinational gated clock logic. You may have a race
within your DUT regardless of the race between your testbench and DUT.
cannot cannot contain always procedures, primitive instances, module instances, interface instances
(virtual interface and port interface is allowed), or other programinstances.
has an extra system task $exit, which terminates the program instances that calls it.
The simulation will terminate when all program instances have exited.
The idea of a program block is to create a clear separation between test and design
Today the opinion of usefulness of a program block is divided. From the last few conventions I been to,
the trend seems to be in favor of abandoning program blocks. This is because the advantages can be
achieved by other methods. Scheduling in the Reactive region can be done with clockingblocks.
A mailbox, queue([$]), or associative array ([*]) can be used for intelligently handling simulation
terminate running multiple tests. Personally, I still like using program blocks and use initial forever as
an always equivalent when needed. If you are planning to use UVM, then a non-program blocks test
bench might work better for you.
In the end, it really comes down to a methodology preference. It is best to evaluate and try it on your
own.
Let me turn the question around: Why should anyone use a program block for their testbench, if
everything works fine without them?
The developers of the AVM and OVM do not believe that program block solve timing problems on their
own. Numerous methodologies already in use by RTL designers that eliminate races are sufficient for
testbenches.
This introduces logic which can be used in place of wire and reg.
The type bit and byte have also been created that can only hold 2 states 0 or 1 no x or z. byteimplies bit
[7:0]. Using these types offers a small speed improvement but I would recommend not using them in
RTL as your verification may miss uninitialized values or critical resets.
The usage of bit and byte would be more common in testbench components, but can lead to issues in
case of having to drive x's to stimulate data corruption and recovery.
. Explain the difference between data types logic and reg and wire :
Wire are Reg are present in the verilog and system verilog adds one more data type called logic.
Wire :
Wire data type is used in the continuous assignments or ports list. It is treated as a wire So it can not
hold a value. It can be driven and read. Wires are used for connecting different modules.
Reg :
Reg is a date storage element in system verilog. Its not a actual hardware register but it can store values.
Register retain there value until next assignment statement.
Logic :
System verilog added this additional datatype extends the rand eg type so it can be driven by a single
driver such as gate or module. The main difference between logic dataype and reg/wire is that a logic
can be driven by both continuous assignment or blocking/non blocking assignment.
But Interface can't be instantiated inside program block, class (or similar non-module entity in
SystemVerilog). But they needed to be driven from verification environment like class. To solve this issue
virtual interface concept was introduced in SV.
Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an
interface (that implies the class can drive the interface using the virtual interface). It provides a
mechanism for separating abstract models and test programs from the actual signals that make up the
design. Another big advantage of virtual interface is that class can dynamically connect to different
physical interfaces in run time.
Virtual interfaces provide a mechanism for separating abstract models and test programs from the
actual signals that make up the design. A virtual interface allows the same subprogram to operate on
different portions of a design and to dynamically control the set of signals associated with the
subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set
of virtual signals. Changes to the underlying design do not require the code using virtual interfaces to be
rewritten. By abstracting the connectivity and functionality of a set of blocks, virtual interfaces promote
code reuse.
Virtual interfaces can be declared as class properties, which can be initialized procedurally or by an
argument to new(). This allows the same virtual interface to be used in different classes.
A virtual interface is a pointer to an actual interface in SystemVerilog. It is most often used in classes to
provide a connection point to allow classes to access the signals in the interface through the virtual
interface pointer.
$random system function returns a 32-bit signed random number each time it is called
$urandom system function returns a 32-bit unsigned random number each time it is called. (newly
added in SV, not present in verilog)
Unlike an assert statement, an expect statement starts only a single thread of evaluation. It comes out
of the blocking mode only if the property succeeds or fails.
== tests logical equality (tests for 1 and 0, all other will result in x)
SVA bind file requires assertions be wrapped in module that includes port declaration,
If the assertion module uses the same signal names as the target module, the bind file port declarations
are still required but the bind-instantiation can be done using the SystemVerilog .* implicit port
connections. If signal names are not exactly matching between target and bind file module then we
need to expand the instantiation with respected port names.
The new unique constraint lets you use one statement to constrain a set of variables or array elements
to have unique values. When randomized, this class generates a set of ten unique values from 0 to 15.
You can also add other non-random variables to the set of unique values which has the effect of
excluding the values of those variables from the set of unique values. When randomized, this class
generates a set of ten unique values excluding the values 0, 7 and 15.
When two or more methods (functions) in the same Class have the same name but different parameters
is called method overloading.
Here you can see the functions name are same but parameter type and number of parameters are
different.
Overriding
When two or more methods (functions) have the exact same method name, return type, number of
parameters, and types of parameters as the method in the parent class is called method Overriding.
Here you can see the method name, parameter and return type are same but one method is in the
parent class and another one in the child class.
Shallow Copy:
Simply makes a copy of the reference to A into B. Think about it as a copy of A's Address. So, the
addresses of A and B will be the same i.e. they will be pointing to the same memory location i.e. data
contents.
Deep copy:
Simply makes a copy of all the members of A, allocates memory in a different location for B and then
assigns the copied members to B to achieve deep copy. In this way, if A becomes non-existant B is still
valid in the memory. The correct term to use would be cloning, where you know that they both are
totally the same, but yet different (i.e. stored as two different entities in the memory space). You can
also provide your clone wrapper where you can decide via inclusion/exclusion list which properties to
select during deep copy.