The RISC-V Processor

Control Unit
 Module Outline
● RISC-V datapath implementation
– Register File, Instruction memory, Data memory
● Instruction interpretation and execution.
● Combinational control
● Assignment: Datapath design and Control Unit
design using HDL.
RISC-V Datapath and Control Lines
 Control Unit

Branch
MemRead
MemtoReg
Instruction[6-0] ALUOp
CONTROL
CONTROL
MemWrite
ALUSrc
RegWrite
R-Type – Datapath, Control
R-Type – Datapath, Control

00

00

00 00
11

00

10
10
Load Instruction
Load Instruction

00

11

11 11

00

11

00
00
Branch-on-Equal Instruction
Branch-on-Equal Instruction

11

XX

00 00

00

00

01
01
The Main Control Unit
The Main Control Unit
The Main Control Unit
 The Main Control Unit
Branch=f
Branch=f2⋅f 1⋅f 0
2⋅f 1⋅f 0

MemtoReg=f
MemtoReg=f2⋅f 1⋅f 0 MemRead=f
MemRead=f2⋅f 1⋅f 0 ALUOp
ALUOp0=f
0=f2⋅f 1⋅f 0
2⋅f 1⋅f 0 2⋅f 1⋅f 0 2⋅f 1⋅f 0

ALUSrc=f
ALUSrc=f2⋅f RegWrite=f
RegWrite=f22((f f1⋅f 0 + f 1⋅f 0)
ALUOp1=f
ALUOp1=f2⋅f 1⋅f 0
2⋅f 0 1⋅f 0 + f 1⋅f 0) 2⋅f 1⋅f 0
0

MemWrite=f
MemWrite=f2⋅f 1⋅f 0
2⋅f 1⋅f 0
 Outline
● RISC-V datapath implementation
– Register File, Instruction memory, Data memory
● Instruction interpretation and execution.
● Combinatinal control
● Datapath and Control Unit design using HDL
Control Unit Truth Table