uPSD32xx

8032 MCU with USB and Programmable Logic

DATA BRIEFING

FEATURES SUMMARY
■ FAST 8-BIT 8032 MCU Figure 1. Packages
– 40MHz at 5.0V, 24MHz at 3.3V

■
– Core, 12-clocks per instruction
DUAL FLASH MEMORIES WITH MEMORY
( s )
MANAGEMENT
– Place either memory into 8032 program
u ct
address space or data address space
o d
r
– READ-while-WRITE operation for In- TQFP52 (T)

P
Application Programming and EEPROM 52-lead, Thin,
Quad, Flat
emulation
– Single voltage program and erase
e t e
– 100K minimum erase cycles, 15-year
retention
o l
■ CLOCK, RESET, AND SUPPLY
b s
MANAGEMENT
– SRAM is Battery Backup capable
- O
– Normal, Idle, and Power Down Modes

(s )
– Power-on and Low Voltage reset
supervisor
c t
– Programmable Watchdog Timer
d u
■ PROGRAMMABLE LOGIC, GENERAL
PURPOSE
r o TQFP80 (U)

– 16 macrocells

e P 80-lead, Thin,
Quad, Flat

e t
– Implements state machines, glue-logic,
and so forth
l
■
o
COMMUNICATION INTERFACES

bs
– USB v1.1, low-speed 1.5Mbps, 3 ■ A/D CONVERTER
endpoints – Four channels, 8-bit resolution, 10µs
O – I2C Master/Slave bus controller
– Two UARTs with independent baud rate
■ TIMERS AND INTERRUPTS
– Three 8032 standard 16-bit timers
– Six I/O ports with up to 46 I/O pins – 10 Interrupt sources with two external
– 8032 Address/Data bus available on interrupt pins
TQFP80 package ■ Single Supply Voltage
– 5 PWM outputs, 8-bit resolution – 4.5 to 5.5V
■ JTAG IN-SYSTEM PROGRAMMING – 3.0 to 3.6V
– Program the entire device in as little as
10 seconds

November 2004 1/8

For further information contact your local ST sales office.
 uPSD32xx

Table 1. Device Summary

Max 1st 2nd
SRAM 8032 VCC
Part Number Clock Flash Flash GPIO USB Pkg. Temp.
(bytes) Bus (V)
(MHz) (bytes) (bytes)
uPSD3212C-40T6 40 64K 16K 2K 37 No No 4.5-5.5 TQFP52 –40°C to 85°C
uPSD3212CV-24T6 24 64K 16K 2K 37 No No 3.0-3.6 TQFP52 –40°C to 85°C
uPSD3212C-40U6 40 64K 16K 2K 46 No Yes 4.5-5.5 TQFP80 –40°C to 85°C
uPSD3212CV-24U6 24 64K 16K 2K 46 No Yes 3.0-3.6 TQFP80 –40°C to 85°C
uPSD3233B-40T6 40 128K 32K 8K 37 No No 4.5-5.5 TQFP52 –40°C to 85°C
uPSD3233BV-24T6 24 128K 32K 8K 37 No No 3.0-3.6 TQFP52 –40°C to 85°C
uPSD3233B-40U6 40 128K 32K 8K 46 No Yes 4.5-5.5
s )
TQFP80 –40°C to 85°C
(
uPSD3233BV-24U6 24 128K 32K 8K 46 No Yes 3.0-3.6
ct
TQFP80 –40°C to 85°C

u
d
uPSD3234A-40T6 40 256K 32K 8K 37 Yes No 4.5-5.5 TQFP52 –40°C to 85°C
uPSD3234A-40U6 40 256K 32K 8K 46 Yes Yes
r
4.5-5.5
o
TQFP80 –40°C to 85°C
uPSD3234BV-24U6 24 256K 32K 8K 46 No Yes

e P
3.0-3.6 TQFP80 –40°C to 85°C

let
uPSD3253B-40T6 40 128K 32K 32K 37 No No 4.5-5.5 TQFP52 –40°C to 85°C
uPSD3253BV-24T6 24 128K 32K 32K 37 No No 3.0-3.6 TQFP52 –40°C to 85°C
uPSD3254BV-24U6 24 256K 32K 32K 46
s oNo Yes 3.0-3.6 TQFP80 –40°C to 85°C
uPSD3254A-40T6 40 256K 32K
O
32K 37b Yes No 4.5-5.5 TQFP52 –40°C to 85°C
uPSD3254A-40U6 40 256K 32K

) -32K 46 Yes Yes 4.5-5.5 TQFP80 –40°C to 85°C

t ( s
u c
o d
P r
e t e
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b s
O

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 uPSD32xx

SUMMARY DESCRIPTION
The uPSD32xx Series combines a fast 8051-
based microcontroller with a flexible memory
structure, programmable logic, and a rich periph-
eral mix including USB, to form an ideal embedded
controller. At its core is an industry-standard 8032
MCU operating up to 40MHz.
A JTAG serial interface is used for In-System Pro-
gramming (ISP) in as little as 10 seconds, perfect
for manufacturing and lab development.
The USB 1.1 low-speed interface has one Control
endpoint and two Interrupt endpoints suitable for
HID class drivers.
The 8032 core is coupled to Programmable Sys-
tem Device (PSD) architecture to optimize the
8032 memory structure, offering two independent
banks of Flash memory that can be placed at vir-
tually any address within 8032 program or data ad-
dress space, and easily paged beyond 64K bytes
using on-chip programmable decode logic.
Dual Flash memory banks provide a robust solu-
tion for remote product updates in the field through
In-Application Programming (IAP). Dual Flash
banks also support EEPROM emulation, eliminat-
ing the need for external EEPROM chips.
General purpose programmable logic (PLD) is in-
cluded to build an endless variety of glue-logic,
saving external logic devices. The PLD is config-
ured using the software development tool, PSD-
soft Express, available from the web at
www.st.com/psm, at no charge.
The uPSD32xx also includes supervisor functions
such as a programmable watchdog timer and low-
voltage reset.
( s )
ct
d u
r o

e P
Figure 2. Block Diagram

l e t
uPSD32xx
s o
(3) 16-bit
Timer/
Counters 8032
O b 1st Flash Memory:

)-
MCU 64K, 128K,
(2)
Core or 256K Bytes
External Programmable
Interrupts

t ( s Decode and
Page Logic
2nd Flash Memory:
P3.0:7 I2C
c 16K or 32K Bytes

du
SRAM:
2K, 8K, or 32K Bytes

ro
UART0
(8) GPIO, Port A

e P (8) GPIO, Port 3 General

(80-pin only)
PA0:7

let
SYSTEM BUS

Purpose (8) GPIO, Port B PB0:7

Programmable
P1.0:7 (8) GPIO, Port 1

o
Logic, (2) GPIO, Port D PD1:2

s
16 Macrocells

Ob (4) 8-bit ADC (4) GPIO, Port C

PC0:7
UART1 JTAG ISP

8032 Address/Data/Control Bus MCU

(5) 8-bit PWM (80-pin device only) Bus

Supervisor:
P4.0:7 (8) GPIO, Port 4
Watchdog and Low-Voltage Reset

USB+, VCC, VDD, GND, Reset, Crystal In Dedicated

USB v1.1
USB– Pins

AI10401

3/8
 uPSD32xx

Figure 3. TQFP52 Connections

41 P1.7/ADC3
40 P1.6/ADC2
44 RESET_
46 VREF
45 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5

43 PB6
42 PB7
PD1/CLKIN 1 39 P1.5/ADC1
PC7 2 38 P1.4/ADC0
JTAG TDO 3 37 P1.3/TXD1
JTAG TDI 4 36 P1.2/RXD1
USB–(1) 5 35 P1.1/T2X

( s )
ct
PC4/TERR_ 6 34 P1.0/T2
USB+ 7 33 VCC
VCC 8

d
32 XTAL2
u
GND 9
PC3/TSTAT 10
r o
31 XTAL1
30 P3.7/SCL1
PC2/VSTBY 11

e P
29 P3.6/SDA1

let
JTAG TCK 12 28 P3.5/T1
JTAG TMS 13 27 P3.4/T0

s o
O b
P4.7/PWM4 14
P4.6/PWM3 15
P4.5/PWM2 16
P4.4/PWM1 17
P4.3/PWM0 18
GND 19
P4.2/DDC VSYNC 20
P4.1/DDC SCL 21
P4.0/DDC SDA 22
P3.0/RXD 23
P3.1/TXD 24
P3.2/EXINT0 25
P3.3/EXINT1 26

) -
t ( s
u c
o d AI07423b

r
Note: 1. Pull-up resistor required on pin 5 (2kΩ for 3V devices, 7.5kΩ for 5V devices).

P
e t e
o l
b s
O

4/8
 uPSD32xx

Figure 4. TQFP80 Connections

79 P3.2/EXINT0

75 P3.0/RXD0

64 P1.7/ADC3

61 P1.6/ADC2
77 P3.1/TXD0

68 RESET_

63 PSEN_
71 NC(2)
70 VREF
69 GND

62 WR_
65 RD_
80 PB0

78 PB1

76 PB2

74 PB3
73 PB4
72 PB5

67 PB6
66 PB7
PD2 1 60 P1.5/ADC1
P3.3 /EXINT1 2 59 P1.4/ADC0
PD1/CLKIN 3 58 P1.3/TXD1
ALE 4
PC7 5
57 A11

( s )
56 P1.2/RXD1

ct
JTAG/TDO 6 55 A10

du
JTAG/TDI 7 54 P1.1/TX2
USB–(1) 8 53 A9
PC4/TERR_ 9
r o 52 P1.0/T2
USB+ 10
NC(2) 11
e P 51 A8
50 VCC
VCC 12

e t 49 XTAL2

ol
GND 13 48 XTAL1
PC3/TSTAT 14
PC2/VSTBY 15
b s 47 AD7
46 P3.7/SCL1
JTAG TCK 16
O 45 AD6

)-
NC(2) 17 44 P3.6/SDA1
P4.7/PWM4 18 43 AD5
P4.6/PWM3 19

t ( s 42 P3.5/T1
JTAG TMS 20

u c 41 AD4

o d
P r
PA7 21
PA6 22
P4.5/PWM2 23
PA5 24
P4.4/PWM1 25
PA4 26
P4.3/PWM0 27
PA3 28
GND 29
P4.2/DDC VSYNC 30
P4.1/DDC SCL 31
PA2 32
P4.0/DDC SDA 33
PA1 34
PA0 35
AD0 36
AD1 37
AD2 38
AD3 39
P3.4/T0 40

e t e
o l
b s AI07424b

ONote: 1. Pull-up resistor required on pin 8 (2kΩ for 3V devices, 7.5kΩ for 5V devices).
2. NC = Not Connected.

5/8
 uPSD32xx

Table 2. Major Parameters

Parameters/Conditions/ 5V Test 3.3V Test
5.0V Value 3.3V Value Unit
Comments Conditions Conditions
Operating Voltage – 4.5 to 5.5 – 3.0 to 3.6 V
Operating Temperature – –40 to 85 – –40 to 85 °C
MCU Frequency
12MHz (min) for USB; – 1 Min, 40 Max – 1 Min, 24 Max MHz
8MHz (min) for I2C
Active Current, Typical
(25°C operation; 80% Flash and 24MHz MCU clock, 12MHz MCU clock,
15% SRAM accesses, 45 PLD 12MHz PLD input 72 6MHz PLD input 21 mA
product terms used; PLD Turbo frequency, 4MHz ALE frequency, 2MHz ALE
mode Off)

( s )
ct
Idle Current, Typical
(CPU halted but some peripherals 24MHz MCU clock, 12MHz MCU clock,

du
active; 25°C operation; 45 PLD 12MHz PLD input 25 1MHz PLD input 7 mA
product terms used; PLD Turbo frequency frequency
mode Off)
r o
Standby Current, Typical
(Power-down Mode, requires reset P
ete
180µA with LVD 110 100µA with LVD 60 µA
to exit mode; without Low-Voltage
Detect (LVD) Supervisor)
SRAM Backup Current, Typical
o l
(If external battery is attached.)
I/O Sink/Source Current
–

VOL = 0.25V (max); b

0.5
s
IOL = 8 (max);
–

VOL = 0.15V (max);

0.5

IOL = 4 (max);
µA

Ports A, B, C, and D VOH = 3.9V (min)

- O
IOH = –2 (min) VOH = 2.6V (min) IOH = –1 (min)
mA

PLD Macrocells
(For registered or combinatorial
(s
– ) 16 – 16 –
logic)

c t
PLD Inputs
u
od
(Inputs from pins, macrocell – 69 – 69 –
feedback, or MCU addresses)
PLD Outputs
P r
(Output to pins or internal – 16 – 16 –
feedback)

e t e
o l
PLD Propagation Delay, Typical
(PLD input to output, Turbo Mode)
– 15 – 22 ns

b s
O

6/8
 uPSD32xx

PART NUMBERING

Table 3. Ordering Information Scheme

Example: uPSD 3 2 1 2 C V – 24 U 6 T

Device Type
uPSD = Microcontroller PSD

Family
3 = 8032 core

PLD Size
2 = 16 Macrocells

( s )
ct
SRAM Size
1 = 2K bytes
3 = 8K bytes
d u
5 = 32K bytes
r o
Main Flash Memory Size

e P
2 = 64K bytes
3 = 128K bytes
l e t
4 = 256K bytes

s o
IP Mix
2
A = USB, I C, PWM, DDC, ADC, (2) UARTs,
O b
Supervisor (Reset Out, Reset In, LVD, WD)
) -
(s
B = I2C, PWM, DDC, ADC, (2) UARTs,

C = I2C, PWM, ADC, (2) UARTs,

c t
Supervisor (Reset Out, Reset In, LVD, WD)

u
Supervisor (Reset Out, Reset In, LVD, WD)
d
Operating Voltage
r o
P
blank = VCC = 4.5 to 5.5V

e
t
V = VCC = 3.0 to 3.6V

Speed
o l e
b s
–24 = 24MHz
–40 = 40MHz

OPackage
T = 52-pin TQFP
U = 80-pin TQFP

Temperature Range
6 = –40 to 85°C

Shipping Option
T = Tape and Reel Packing

For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.

7/8
 uPSD32xx

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2004 STMicroelectronics - All rights reserved

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