Eletrocopiadiesel 188

ST7LUS5, ST7LU05, ST7LU09
8-bit low cost, low pin-count MCU for automotive,

with single voltage Flash memory, ADC, timers
Features
Memories
■ 1 to 2 Kbytes single voltage Flash program
memory with readout protection, in-circuit and
in-application programming (ICP and IAP), 10k
( s )
write/erase cycles guaranteed, data retention
20 years
c t SO8 150-mil (1)
■ 128 bytes RAM

d u
■ Up to 128 bytes data EEPROM, 300k
write/erase cycles guaranteed, data retention r o )
2 timers
s
20 years
e P c t (■ One 8-bit lite timer with prescaler including:
Clock, reset and supply management

l e t d u
watchdog, 1 real-time base and 1 input capture
■ One 12-bit auto-reload timer with output
■
o
Internal low voltage supervisor (LVD) for
s
reliable power-on/-off start-up procedures r o compare function and PWM
b
■ Clock sources: Internal trimmable 8 MHz RC
O e P A/D converter
oscillator, internal low power, low frequency
RC oscillator or external clock
- l e t ■ 10-bit resolution for 0 to VDD
s )
■ 5 power saving modes: Halt, auto wake-up
( o
■ 5 input channels
c t
from halt, active halt, wait and slow
b s Instruction set
Interrupt management
d u - O ■
■
8-bit data manipulation
63 basic instructions with illegal opcode
■
r o s )
11 interrupt vectors plus TRAP and reset
■ 5 external interrupt lines (on 5 vectors)
detection
e P c t ( ■ 17 main addressing modes

I/O ports
■
l e t d u
5 multifunctional bidirectional I/O lines
■ 8 x 8 unsigned multiply instruction
Development tools
s o r o
■ 1 additional output line
■ Full hardware/software development package
O b e P
■ 6 alternate function lines
■ Debug module
l e t
■ 5 high sink outputs
s o
Table 1. Device summary
O b Device
Flash program
memory
RAM/EEPROM Peripherals
Operating
voltage
CPU
frequency
Operating
temp.
ST7LUS5 1 Kbyte Lite timer with

128 bytes RAM/no EEPROM watchdog, -40°C to
ST7LU05 3.0V to 5.5V
auto-reload Up to 8 +85°C/
@ fCPU = 8
2 Kbytes timer with 1 MHz RC -40°C to
128 bytes RAM/128 bytes MHz
ST7LU09 PWM, 125°C
EEPROM
10-bit ADC
1. DIP16 package available for development or tool prototyping purposes only. Not orderable in production quantities.
February 2008 Rev 3 1/124

www.st.com 1
Contents ST7LUS5, ST7LU05, ST7LU09
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Package pinout and device pin description . . . . . . . . . . . . . . . . . . . . . 12
3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1
s )
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
(
4.2
c t
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
d u
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1
r o s )
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.2 P c t (
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
e
4.4
e t u
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
l d
4.5
o r o
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
s
4.5.1
b P
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
O e
4.5.2
- t
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
l e
4.6 ) o
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
( s
4.6.1
c t b s
Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 d u - O
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
r o s )
5.1
e P (
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
c t
l e t5.2
5.3
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
d u
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
s o r o 5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
O b e P 5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
l e t 5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
s o 5.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
O b 5.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 29
6.2.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/124
ST7LUS5, ST7LU05, ST7LU09 Contents
6.2.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 30

6.2.4 Internal RC prescaler selection register (INTRCPRR) . . . . . . . . . . . . . . 30
6.2.5 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 31
6.3 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4
s )
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
(
6.4.1
t
Multiplexed I/O reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . 36
c
6.4.2
u
Multiplexed I/O reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . 36
d
r o s )
7
e P c t (
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
7.2
l e t
Non-maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
d u
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3
s o r o
Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3.1
O b e P
External interrupt control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 41
7.3.2
- l e t
External interrupt control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 41
( s ) o
7.4
7.4.1
c b s
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
t Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
d u
7.4.2
- O
SI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
r o s )
8 P t (
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
e c
l e t
8.1
u
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
d
s o 8.2
r oSlow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
O b 8.3
e P Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
l e t
8.4 Active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
s o 8.4.1
8.4.2
Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
O b 8.5 Auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3/124
9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.6 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.1
s )
Lite timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
(
10.1.1
c t
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.1.2
d u
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.1.3
r o )
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
s
10.1.4
P t (
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
e c
10.1.5
t u
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
l e d
10.1.6
s o r o
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.2
10.2.1
O e P
12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
b
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
- l e t
10.2.2
( s )Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
o
10.2.3
c
10.2.4t b s
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
d u
10.2.5
- O
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
r o 10.2.6
s )Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
P
10.3
e t (
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
c
l e t u
10.3.1
d
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
s o r o 10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
O b e P 10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
l e t 10.3.4
10.3.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
s o 10.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
O b
11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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ST7LUS5, ST7LU05, ST7LU09 Contents
11.1.4 Direct indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.1
)
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
( s
12.1.2
t
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
c
12.1.3
u
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
d
12.1.4
r o
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
s )
12.1.5
P (
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
e c t
12.2
12.3
l e t
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
d u
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.1
s o r o
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.4
O b e P
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.5 - l e t
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
( s ) o
12.6
c t b s
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.7
d u
EMC (electromagnetic compatibilty) characteristics . . . . . . . . . . . . . . . . 102
12.7.1
- O
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 102
r o12.7.2
s )
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
e P c
12.7.3 t ( Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 104
l e t
12.8
d u
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
s o 12.9
r oControl pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
O b P
12.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
e
l e t
13
s o Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
O b 13.1
13.2
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.4 Soldering compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 118
5/124
14.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.1.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.1.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.2 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.2.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.2.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.2.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.2.4 Order codes for development and programming tools . . . . . . . . . . . . . 121
14.3 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
( s )
15
t
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
c
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
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ST7LUS5, ST7LU05, ST7LU09 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. CC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. RCCR calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8. RCCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10.
Table 11.
( s )
INTRCPRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CKCNTCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12.
c t
Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13.
Table 14.
d u
MUXCRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Multiplexed I/O register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15.
r o )
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
s
Table 16.
Table 17.
e P c t (
EICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
EICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18.
Table 19.
l e t d u
Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20.
s o r o
System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21.
Table 22.
O b e P
LTC/ATC low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
AWUCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 23.
- e t
AWUPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
l
Table 24.
( s )
AWUPR division factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
o
Table 25.
Table 26.
c b s
AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
t
I/O output mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 27.
Table 28.
d u - O
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 29.
r o )
Effect of ow power modes on I/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
s
Table 30.
Table 31.
e P c t (
I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 32.
l e
Table 33.
t d u
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Effect of low power modes on lite timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
s o
Table 34.
r o
Lite timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
O b
Table 35.
Table 36.
e P
LTCSR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LTICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 37.
l e
Table 38.
t Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Effect of low power modes onthe auto-reload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
s o
Table 39. Auto-reload timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
O b
Table 40.
Table 41.
Table 42.
ATCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
CNTR high and low counter descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ATR high and low register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 43. DCR0 high and low register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 44. PWM0CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 45. PWMCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 46. Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 47. Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 48. ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7/124
List of tables ST7LUS5, ST7LU05, ST7LU09
Table 49. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 50. ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 51. ADC clock speed configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 52. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 54. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 55. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 56. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 57. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 87
Table 58. Available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 59. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 60. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 61. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 62.
s )
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
(
Table 63.
Table 64.
c t
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 65.
u
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
d
Table 66.
Table 67.
r o
Internal RC oscillator calibrated at 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
s )
Internal RC oscillator calibrated at 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 68.
Table 69. P t (
Supply current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
e c
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 70.
e t u
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
l d
Table 71.
Table 72.
s o r o
Auto wake-up RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 73.
b P
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
O e
Table 74.
Table 75.
e t
EEPROM memory (ST7FLU09 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
-
EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
l
Table 76.
) o
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
( s
Table 77.
Table 78.
c t b s
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 79.
Table 80. d u - O
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 81.
r o s )
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 82.
Table 83. P t (
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
e c
ADC accuracy with VDD = 4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
e
Table 84.
l t u
ADC accuracy with VDD = 3.0V to 3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
d
s o
Table 85.
Table 86.
r o
8-pin plastic small outline package, 150-mil width, mechanical data . . . . . . . . . . . . . . . . 115
8-pin plastic small outline package, 150-mil width, mechanical data . . . . . . . . . . . . . . . . 116
O b
Table 87.
Table 88.
e P
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 117
e
Table 89.
l t Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
s o
Table 90.
Table 91.
Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
O b
Table 92.
Table 93.
Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Development and programming tool order codes for the ST7LUxx family . . . . . . . . . . . . 122
Table 94. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8/124
ST7LUS5, ST7LU05, ST7LU09 List of figures
List of figures
Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. 8-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. 16-pin DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Memory map (ST7LUS5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Memory map (ST7LU05 and ST7LU09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10.
Figure 11.
( s )
Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12.
c t
Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13.
Figure 14.
d u
Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15.
r o )
Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
s
Figure 16.
Figure 17.
e P c t (
Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18.
Figure 19.
l e t d u
Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 20.
s o r o
Active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21.
Figure 22.
O b e P
Active halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23.
- e t
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
l
Figure 24.
( s )
AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
o
Figure 25.
Figure 26.
c b s
AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
t
AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 27.
Figure 28.
d u - O
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 29.
r o )
Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
s
Figure 30.
Figure 31.
e P c t (
Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32.
l e
Figure 33.
t d u
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
s o
Figure 34.
r o
PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
O b
Figure 35.
Figure 36.
e P
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 37.
l e
Figure 38.
t Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
fCLKIN maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . 95
s o
Figure 39. Internal RC oscillator frequency vs. temperature (RCCR = RCCR0) at VDD = 5.0V . . . . . 97
O b
Figure 40.
Figure 41.
Figure 42.
Internal RC oscillator frequency vs. temperature (RCCR = RCCR1) at VDD = 3.3V . . . . . 97
Typical IDD in run mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical IDD in slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 43. Typical IDD in wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 44. Typical IDD in slow wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 45. Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . . . 100
Figure 46. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 47. Typical IPU vs. VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 48. Typical VOL at VDD = 3.3V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9/124
List of figures ST7LUS5, ST7LU05, ST7LU09
Figure 49. Typical VOL at VDD = 5V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 50. Typical VOL at VDD = 3.3V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 51. Typical VOL at VDD = 5V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 52. Typical VDD - VOH at VDD = 3.3V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 53. Typical VDD - VOH at VDD = 5V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 54. Typical VOL vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 55. Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 56. Typical VDD - VOH vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 57. RESET pin protection when LVD is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 58. RESET pin protection when LVD is disabled(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 59. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 60. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 61. 8-pin plastic small outline package, 150-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 62.
s )
16-pin plastic dual in-line package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
(
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
10/124
ST7LUS5, ST7LU05, ST7LU09 Description
1 Description
The ST7LUxx devices are members of the ST7 microcontroller family designed for mid-range automotive
applications running from 3 to 5.5V.
All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction
set and are available with Flash or preprogramed memory. The ST7 family architecture offers both power
and flexibility to software developers, enabling the design of highly efficient and compact application
code.
The on-chip peripherals include an A/D converter, a lite timer and and an auto-reload timer. For power
economy, the microcontroller can switch dynamically into halt, auto wake-up from halt, active halt, wait, or
slow mode when the application is in idle or standby state.
( s )
The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD). For a
c t
description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Typical applications include:
d u
●
r o )
All types of car body applications such as window lift, DC motor control, sunroof
s
● Remote keyless entry (RKE)
e P c t (
● Safety microcontroller (sub-MCU)
l e t d u
Figure 1. General block diagram
s o r o
O b e P
- l e t
Internal
Clock
( s )
AWU RC OSC
o
c t b
8 MHz RC OSCs
External
d u - O
Clock
r o s )
Lite timer
with watchdog
e P
VDD
c t ( LVD
ADDRESS AND DATA BUS
t
Power Port A
l e VSS
d u supply
s o RESET
r o Control
12-bit auto-
reload timer
PA5:0
O b e P 8-bit core
(6 bits)
l e t ALU
10-bit ADC
s o Up to 2 Kbytes
O b FLASH
memory
Data EEPROM(1)
(128 bytes)
RAM
(128 bytes)
1. Optional on certain devices
11/124
Package pinout and device pin description ST7LUS5, ST7LU05, ST7LU09
2 Package pinout and device pin description
Figure 2. 8-pin SO package pinout
VDD 1 8 VSS
PA5 (HS)/AIN4/CLKIN 2) ei4 ei0 (7 PA0 (HS)/AIN0/ATPWM/ICCDATA
PA4 (HS)/AIN3/MCO 3) ei3 ei1 (6 PA1 (HS)/AIN1/ICCCLK
PA3/RESET 4 ei2 (5 PA2 (HS)/LTIC/AIN2
( s )
c t
u
(HS): High sink capability
o d )
eix: associated external interrupt vector
P r ( s
Figure 3. 16-pin DIP package pinout(a)
t e c t
l e d u
s o
Reserved(1) 1
r o 16 NC
O b VDD
e P2 15 VSS
- e
RESET
l t 3 ei0 14 PA0 (HS)/AIN0/ATPWM
( s ) o
c t b s ICCCLK 4 ei1 13 PA1 (HS)/AIN1
d u O
PA5 (HS)/AIN4/CLKIN
-
5 ei4 12 NC
r o s )
PA4 (HS)/AIN3/MCO 6 ei3 11 ICCDATA
e P c t ( PA3 7 ei2 10 PA2 (HS)/LTIC/AIN2
l e t d u NC 8 9 NC
s o r o
O b e P (HS): High sink capability
eix: associated external interrupt vector
l e t
s o
Note:
1. Must be tied to ground
The differences between 16-pin and 8-pin packages are listed below:
O b 1. The ICC signals (ICCCLK and ICCDATA) are mapped on dedicated pins.
2. The reset signal is mapped on a dedicated pin. It is not multiplexed with PA3.
3. PA3 pin is always configured as output. Any change on multiplexed IO reset control
registers (MUXCR1 and MUXCR2) will have no effect on PA3 functionality. Refer to
Section 4.6: Register description.
a. For development or tool prototyping purposes only. Package not orderable in production quantities.
12/124
ST7LUS5, ST7LU05, ST7LU09 Package pinout and device pin description
Table 2. Device pin description(1)

Pin Level Port / Control Function
Type(2)
Output(4)
Input(5) Output(6)
Input(3)
Main
No. Name (after Alternate
float
wpu
ana
OD
PP
int
reset)
1 VDD(7) S Main power supply

Analog input 4 or external clock
2 PA5/AIN4/CLKIN I/O CT HS X ei4 X X X Port A5
input
Analog input 3 or main clock
3 PA4/AIN3/MCO I/O CT HS X ei3 X X X Port A4
output
4 PA3/RESET(8) O
( s ) X X X Port A3 Reset(8)
5 PA2/AIN2/LTIC I/O CT HS X
c t ei2 X X X Port A2
Analog input 2 or lite timer input
capture
d u Analog input 1 or in-circuit
r o s ) communication clock
e P c t ( Caution: During normal

Port A1 operation this pin must be
6 PA1/AIN1/ICCCLK
l e t
I/O CT HS X
d u
ei1 X X X
pulled-up, internally or externally
(external pull-up of 10k
s o r o mandatory in noisy
P
environment).
O b e Analog input 0 or auto-reload
-
7 PA0/AIN0/ATPWM/ICCDATA I/O CT HS X
l e t ei0 X X X Port A0 timer PWM or in-circuit
( s ) o
communication data
8 VSS(7)
c t b sS Ground
d u
1. The reset configuration of each pin is shown in bold which is valid as long as the device is in reset state.
- O
2. Type: I = input, O = output, S = supply
r o )
3. In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger
s
P t (
4. Output level: HS = High sink (on N-buffer only)
e c
t
5. Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
l e u
6. Output: OD = open drain, PP = push-pull
d
o o
7. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
s r
P
8. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to
O b MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 6.4: Register description on page 42.
e
l e t
s o
O b
13/124
Register and memory map ST7LUS5, ST7LU05, ST7LU09
3 Register and memory map
As shown in Figure 6 and Figure 8, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte
or 2 Kbytes of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h
to 00FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 6 and Figure 8) mapped in the upper part of the ST7
addressing space whereas the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh for the
ST7LUS5 and FA01h-FFFFh for the ST7LU05/ST7LU09).
( s )
t
The size of Flash sector 0 and other device options are configurable by the option bytes.
c
Caution:
u
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
d
area can have unpredictable effects on the device.
r o s )
Figure 4. Memory map (ST7LUS5)
e P c t (
0000h
l e t d u
HW registers
(see Table 3)
s o r o 0080h
007Fh
0080h
O b e P Short addressing
RAM (zero page)
- l e t 00C0h
RAM
( s )
(128 bytes)
o 00FFh
64-byte stack
00FFh
0100h
c t b s
d u - O DEE0h(1)
DEE1h(1)
RCCRH0
r o s ) DEE2h(1)
RCCRL0
e P c (
Reserved
t 1 Kbyte Flash DEE3h(1)

RCCRH1
l e t d u Program Memory
RCCRL1
s o
FBFFh
FC00h
r o FC00h 0 to 0.5 Kbytes
See also Section 6.1 on page 31
O b e P FDFFh sector 1
l e t Flash memory
(1 Kbyte)
FE00h
FFFFh
0.5 to 1 Kbytes
sector 0(2)
s o
FFDFh
O b FFE0h
Interrupt and reset vectors
(see Table 15)
FFFFh
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC
calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC
calibration values locations) has been erased (after the readout protection removal), then the RC calibration values can still
be obtained through these addresses.
2. Size configurable by option byte
14/124
ST7LUS5, ST7LU05, ST7LU09 Register and memory map
Figure 5. Memory map (ST7LU05 and ST7LU09)
0000h
HW registers
(see Table 3) 0080h
Short addressing
007Fh RAM (zero page)
0080h
00C0h
RAM
(128 bytes) 64-byte stack
00FFh
00FFh
0100h
Reserved DEE0h(2)
0FFFh RCCRH0
DEE1h(2)
1000h
Data EEPROM(1)
( s ) DEE2h(2)
RCCRL0
107Fh
(128 bytes)
c t 2 Kbyte Flash DEE3h(2)

RCCRH1
1080h
Reserved
d u Program Memory
RCCRL1
F7FFh
F800h
r o
F800h
s )
0 to 1.5 Kbytes
See also Section 6.1 on page 31
e PFDFEh
c t ( sector 1
Flash memory
(2 Kbytes)
l e t FA01h
FFFFh
d u 0.5 to 2 Kbytes
sector 0(2)
s o r o
FFDFh
FFE0h
O b e P
Interrupt and reset vectors
-
(see Table 15)
l e t
( s ) o
FFFFh
c t b s
d u - O
1. ST7LU09 only; area reserved in ST7LU05
2. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC
r o )
calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC
s
calibration values locations) has been erased (after the readout protection removal), then the RC calibration values can still
P t (
be obtained through these addresses.
e c
3. Configurable by option byte
l e t d u
s o r o
O b e P
l e t
s o
O b
15/124
Register and memory map ST7LUS5, ST7LU05, ST7LU09
Table 3. Hardware register map(1)

Address Block Register label Register name Reset status Remarks
0000h PADR Port A data register 00h(2) R/W

0001h Port A PADDR Port A data direction register 08h R/W
0002h PAOR Port A option register 02h(3) R/W
0003h-000Ah Reserved area (8 bytes)
000Bh Lite LTCSR Lite timer control/status register 0xh R/W
000Ch timer LTICR Lite timer input capture register 00h Read Only
000Dh ATCSR Timer control/status register 00h R/W
000Eh CNTRH Counter register high 00h Read Only
000Fh Auto- CNTRL Counter register low 00h Read Only
0010h reload ATRH
s )
Auto-reload register high
(
00h R/W
0011h
0012h
timer ATRL
PWMCR
c t
Auto-reload register low
PWM output control register
00h
00h
R/W
R/W
0013h PWM0CSR
u
PWM 0 control/status register
d
00h R/W
0014h to
0016h
r o )
Reserved area (3 bytes)
s
0017h
Auto-
DCR0H
e P c t (
PWM 0 duty cycle register high 00h R/W
0018h
reload
timer
DCR0L
l e t u
PWM 0 duty cycle register low
d
00h R/W
0019h to
s o r o
002Eh
O b e P
0002Fh Flash FCSR
- l e t
Flash control/status register 00h R/W
0030h to
0033h
( s ) o Reserved area (4 bytes)
0034h
c t ADCCSR
b s A/D control status register 00h R/W
0035h
0036h
ADC
d u ADCDRH
-
ADCDRLO A/D data register high
A/D data register low
xxh
00h
Read Only
R/W
0037h
r o ITC
s )
EICR1 External interrupt control register 1 00h R/W
0038h
e P MCC
c t ( MCCSR Main clock control/status register 00h R/W
l e
0039h
003Ah
t d u
Clock and RCCR
reset SICSR
RC oscillator control register
System integrity control/status register
FFh
0000 0x00b
R/W
R/W
s o
003Bh to
r o
O b 003Ch
e P Reserved area (2 bytes)
003Dh
l e t ITC EICR2 External interrupt control register 2 00h R/W
s o
003Eh
RC
prescaler
INTRCPRR Internal RC prescaler selection register 03h R/W
O b 003Fh
Clock
controller
CKCNTCSR Clock controller control/status register 09h R/W
0040h to
0046h
0047h MuxIO- MUXCR0 Mux IO-reset control register 0 00h R/W
0048h reset MUXCR1 Mux IO-reset control register 1 00h R/W
0049h AWUPR AWU prescaler register FFh R/W
AWU
004Ah AWUCSR awu Control/Status Register 00h R/W
16/124
ST7LUS5, ST7LU05, ST7LU09 Register and memory map
Table 3. Hardware register map(1) (continued)

Address Block Register label Register name Reset status Remarks
004Bh DMCR DM control register 00h R/W

004Ch DMSR DM status register 00h R/W
004Dh DMBK1H DM breakpoint register 1 high 00h R/W
DM(4)
004Eh DMBK1L DM breakpoint register 1 low 00h R/W
004Fh DMBK2H DM breakpoint register 2 high 00h R/W
0050h DMBK2L DM breakpoint register 2 low 00h R/W
0051h to
007Fh
1. x = undefined, R/W = read/write
I/O pins are returned instead of the DR register contents.
( s )
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
t
3. The bits associated with unavailable pins must always keep their reset value.
c
u
4. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.
d
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
17/124
Flash program memory ST7LUS5, ST7LU05, ST7LU09
4 Flash program memory
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-
board using in-circuit programming or in-application programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
( s )
4.2 Main features c t
d u
● ICP (in-circuit programming)
r o s )
●
●
IAP (in-application programming)
e P c t (
ICT (in-circuit testing) for downloading and executing user application test patterns in
●
RAM
l e t d u
●
Sector 0 size configurable by option byte
s
Readout and write protectiono r o
O b e P
4.3 Programming modes -
l e t
( s ) o
●
c t b s
The ST7 can be programmed in three different ways:
Insertion in a programming tool - In this mode, Flash sectors 0 and 1 and option byte
d u O
row can be programmed or erased.
-
●
r o )
In-circuit programming - In this mode, Flash sectors 0 and 1 and option byte row can be
s
●
e P c (
programmed or erased without removing the device from the application board.
t
In-application programming - In this mode, sector 1 can be programmed or erased
l e t u
without removing the device from the application board and while the application is
d
running.
s o r o
O b
4.3.1
P
In-circuit programming (ICP)
e
l et
ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
s o via cable. ICP is performed in three steps:
O b 1. Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a
specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low.
When the ST7 enters ICC mode, it fetches a specific reset vector which points to the
ST7 System Memory containing the ICC protocol routine. This routine enables the ST7
to receive bytes from the ICC interface.
2. Download ICP driver code in RAM from the ICCDATA pin
3. Execute ICP driver code in RAM to program the Flash memory
18/124
ST7LUS5, ST7LU05, ST7LU09 Flash program memory
Depending on the ICP driver code downloaded in RAM, Flash memory programming can be
fully customized (number of bytes to program, program locations, or selection of the serial
communication interface for downloading).
4.3.2 In-application programming (IAP)

This mode uses an IAP driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application (user-defined strategy for entering programming mode or choice of
communications protocol used to fetch the data to be stored, etc.).
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
( s )
protected to allow recovery in case errors occur during the programming operation.
c t
4.4 ICC interface
d u
r o )
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
s
pins are:
e P c t (
●
●
RESET:
VSS:
Device reset
l e t
Device power supply ground
d u
● ICCCLK:
s o r o
ICC output serial clock pin(b)
●
b
ICCDATA: ICC input serial data pin
O e P
● CLKIN:
- l e t
Main clock input for external source
Application board power supply(c)
● VDD:
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
b. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As
soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK
and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation
such as a serial resistor has to be implemented in case another device forces the signal. Refer to the
programming tool documentation for recommended resistor values.
c. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply). Please
refer to the programming tool manual.
19/124
Figure 6. Typical ICC interface
Programming tool
ICC connector
ICC cable
ICC connector
(See Note 3) HE10 connector type
Optional
Application board
(See Note 4) 9 7 5 3 1
10 8 6 4 2
Application
Reset source
s ) 3.3kΩ
(See Note 5)
(
See Note 2
Application
c t See Note 1 and Caution
u
Application
power supply
I/O
o d )
See Note 1
r s
CLKIN
RESET
ICCCLK
ICCDATA
VDD
e P ST7
c t (
l e t d u
o r o
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the
s
programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are
b P
not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be
implemented in case another device forces the signal. Refer to the programming tool documentation for recommended
O e
resistor values.
- l e t
2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the
) o
programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up
( s s
resistor<1K). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC
c t
network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components
b
are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.
d u - O
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when
using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool
manual.
r o s )
4. Pin 9 has to be connected to the CLKIN pin of the ST7 when ICC mode is selected with option bytes disabled (35-pulse ICC
P t (
entry mode). When option bytes are enabled (38-pulse ICC entry mode), the internal RC clock (internal RC or AWU RC) is
e c
forced. If internal RC is selected in the option byte, the internal RC is provided. If AWU RC or external clock is selected, the
l e t d u
AWU RC oscillator is provided.
5. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/RESET pin. Contention
s o r o
may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value
is defined to limit the current below 2mA at 5V. If PA3 is used as output push-pull, then the application must be switched off
O b P
to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below VIL,
special care must also be taken when a pull-up is placed on PA3 for application reasons.
e
Caution:
l e t During normal operation, the ICCCLK pin must be pulled up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC
s o mode unexpectedly during a reset. In the application, even if the pin is configured as output,
any reset will put it back in input pull-up.
O b
20/124
ST7LUS5, ST7LU05, ST7LU09 Flash program memory
4.5 Memory protection

There are two different types of memory protection: readout protection and write/erase
protection, either of which can be applied individually.
4.5.1 Readout protection

Readout protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Program memory is protected.
In Flash devices, this protection is removed by reprogramming the option. In this case,
Readout protection selection depends on the device type:

( s )
program memory is automatically erased, and the device can be reprogrammed.
●
c t
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●
d u
In ROM devices it is enabled by mask option specified in the Option List.
r o s )
4.5.2 Flash write/erase protection
e P c t (
l e t
Write/erase protection, when set, makes it impossible to both overwrite and erase program
d u
memory. Its purpose is to provide advanced security to applications and prevent any change
o
being made to the memory content.
s r o
O b e P
Warning:
- t
Once set, write/erase protection can never be removed. A
l e
( s )
write-protected Flash device is no longer reprogrammable.
o
c t b s
u O
Write/erase protection is enabled through the FMP_W bit in the option byte.
d -
o
Related documentation
r s )
P t (
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
e c
l e t
Reference Manual and to the ST7 ICC Protocol Reference Manual.
d u
s o r o
O b e P
l e t
s o
O b
21/124
4.6 Register description
4.6.1 Flash control/status register (FCSR)

1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
FCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
0 0 0 0 0 OPT LAT PGM
R/W R/W R/W R/W R/W R/W R/W R/W
( s )
Note:
t
This register is reserved for programming using ICP, IAP or other programming methods. It
c
controls the XFlash programming and erasing operations.
d u
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
r o s )
Table 4.
e P
Flash register map and reset values
c t (
Address (Hex.)
l
Register label
e t7
d6u 5 4 3 2 1 0
002Fh
FCSR
s o r o OPT LAT PGM
O b
Reset value 0
e P 0 0 0 0 0 0 0
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
22/124
ST7LUS5, ST7LU05, ST7LU09 Central processing unit
5 Central processing unit
5.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2 Main features

● 63 basic instructions
●
●
Fast 8-bit by 8-bit multiply
17 main addressing modes
( s )
● Two 8-bit index registers
c t
● 16-bit stack pointer
d u
● Low power modes
r o s )
●
●
Maskable hardware interrupts
Non-maskable software interrupt
e P c t (
l e t d u
5.3 CPU registers
s o r o
O b e P
The six CPU registers shown in Figure 10 are not present in the memory mapping and are
-
accessed by specific instructions.
l e t
( s ) o
5.3.1 Accumulator (A)
c t b s
d u - O
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
r o s )
5.3.2
P t (
Index registers (X and Y)
e c
l e t d u
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation (the cross-assembler
s o r o
generates a precede instruction (PRE) to indicate that the following instruction refers to the
O b P
Y register).
e
l et
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
s
5.3.3o Program counter (PC)
O b The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
23/124
Central processing unit ST7LUS5, ST7LU05, ST7LU09
Figure 7. CPU registers

7 0
Accumulator
Reset value = XXh
7 0
X index register
Reset value = XXh
7 0
Y index register
Reset value = XXh
15 PCH 8 7 PCL 0
Reset value = Reset vector @ FFFEh-FFFFh

( s )
Program counter
7 0
c t
Reset value = 1 1 1 X 1 X X X
d u
1 1 1 H I N Z C Condition code register
15 8 7
r o 0
s )
e P c t (
Stack pointer
l e t
Reset value = Stack higher address
d u X = Undefined value
s o r o
5.3.4
b
Condition code register (CC)
O e P
- l e t
CC
( s ) o
Reset value: 111x1xxx
7
1
c t
6
1 b s 5
1 H
4 3
I N
2 1
Z
0
-
d u -
- O - R/W R/W R/W R/W R/W
r o s )
e P c t (
The 8-bit condition code register contains the interrupt mask and four flags representative of
the result of the instruction just executed. This register can also be handled by the PUSH
l e t d u
and POP instructions.
s o o
These bits can be individually tested and/or controlled by specific instructions.
r
O b e P
Table 5. CC register description
l e t Bit Name Function
s o 7:5 - Reserved, must remain set.
O b Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
4 H instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
24/124
ST7LUS5, ST7LU05, ST7LU09 Central processing unit
Table 5. CC register description (continued)

Bit Name Function
Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
3 I
and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is
cleared. By default an interrupt routine is not interruptible because the I bit is set by
hardware at the start of the routine and reset by the IRET instruction at the end of the
s )
routine. If the I bit is cleared by software in the interrupt routine, pending interrupts
are serviced regardless of the priority level of the current interrupt routine.
(
Negative
c t
d u
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
2 N
r o )
0: The result of the last operation is positive or null.
s
logic 1).
e P c t (
1: The result of the last operation is negative (that is, the most significant bit is a
l e t d u
This bit is accessed by the JRMI and JRPL instructions.
Zero
s o r o
This bit is set and cleared by hardware. This bit indicates that the result of the last
1 Z
O b e P
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
- e t
1: The result of the last operation is zero.
l
( s )
This bit is accessed by the JREQ and JRNE test instructions.
o
c t
Carry/borrow
b s
This bit is set and cleared by hardware and software. It indicates an overflow or an
d u O
underflow has occurred during the last arithmetic operation.
-
o
0: No overflow or underflow has occurred.
0
P r
C
)
1: An overflow or underflow has occurred.
( s
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
t e c t
instructions. It is also affected by the “bit test and branch”, shift and rotate
l e d u
instructions.
s o r o
O b e P
l e t
s o
O b
25/124
Central processing unit ST7LUS5, ST7LU05, ST7LU09
5.3.5 Stack pointer (SP)
SP Reset value: 00 FFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 1 SP[5:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 11).
( s )
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer (RSP) instruction, the stack pointer
t
contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
c
instruction. d u
The stack pointer least significant byte, called “S”, can be directly accessed by a load (LD)
r o s )
Note:
e P c t (
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
l e t d u
and therefore lost. The stack also wraps in case of an underflow.
s o r o
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
b P
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
O e
Figure 11.
l e t
pointed to by the SP. Then the other registers are stored in the next locations as shown in
-
●
s ) o
When an interrupt is received, the SP is decremented and the context is pushed on the
(
t
stack.
c b s
●
d u
On return from interrupt, the SP is incremented and the context is popped from the
stack.
- O
r o )
A subroutine call occupies two locations and an interrupt five locations in the stack area.
s
e P
Figure 8.
c t ( Stack manipulation example
l e t d u CALL Interrupt PUSH Y POP Y IRET RET
o
Subroutine event or RSP
s r o
@ 00C0h
O b e P
l e t SP
s o SP
Y
SP
O b CC
A
X
CC
A
X
CC
A
X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 00FFh PCL PCL PCL PCL PCL
Stack higher address = 00FFh

Stack lower address = 00C0h
26/124
ST7LUS5, ST7LU05, ST7LU09 Supply, reset and clock management
6 Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components.
Main features
● Clock management
– 8 MHz internal RC oscillator (enabled by option byte)
– External clock input (enabled by option byte)
● Reset Sequence Manager (RSM)
●
s )
System integrity management (SI) - Main supply low voltage detection (LVD) with reset
(
generation (enabled by option byte)
c t
d u
6.1 Internal RC oscillator adjustment
r o s )
P t (
The ST7 contains an internal RC oscillator with a specific accuracy for a given device,
e c
temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0]
e t u
option bits (see Section 14.1 on page 131). It must be calibrated to obtain the frequency
l d
s o r o
required in the application. This is done by software writing a 10-bit calibration value in the
RCCR (RC control register) and in the bits [6:5] in the SICSR (SI control status register).
b P
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), that is,
O e
- t
each time the device is reset, the calibration value must be loaded in the RCCR. Predefined
l e
( s )
calibration values are stored in Flash memory for 3.3 and 5V VDD supply voltages at TAmax,
o
as shown in the following Table 6.
c t b s
Table 6.
d u RCCR calibration values
- O
o
RCCR Conditions ST7LUxx address
P r
RCCRH0
( s ) DEE0h(2) (CR[9:2] bits)
t e RCCRL0
c t VDD = 5V, TAmax, fRC = 8 MHz(1)
DEE1h(2) (CR[1:0] bits)
l e RCCRH1
d u VDD = 3.3V, TAmax, fRC = 8 MHz(1)
DEE2h(2) (CR[9:2] bits)
s o r o
RCCRL1 DEE3h(2) (CR[1:0] bits)
O b e P
1. xxRCCR0 and RCCR1 calibrated within these conditions in order to reach RC accuracy as mentionned in
Table 65: General operating conditions on page 104
l e t2. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area but are special bytes containing also
the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the
s o RC calibration value locations) has been erased (after the readout protection removal), then the RC
calibration values can still be obtained through these two addresses.
O b
Note: 1 In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the
selection in the option byte. Refer to Note 5 in Section 4.4 for further details.
2 See Chapter 12: Electrical characteristics on page 102 for more information on the
frequency and accuracy of the RC oscillator.
3 To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
27/124
Supply, reset and clock management ST7LUS5, ST7LU05, ST7LU09
Caution: If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN2326 for information on how to calibrate the RC frequency using
an external reference signal.
The ST7LUxx also contains an auto wake-up RC oscillator. This RC oscillator should be
enabled to enter auto wake-up from halt mode.
The auto wake-up RC oscillator can also be configured as the startup clock through the
CKSEL[1:0] option bits (see Section 14.1 on page 131).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure 12):
( s )
Case 1: Switching from internal RC to AWU
c t
1.
u
Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator.
d
2.
o
The RC_FLAG is cleared and the clock output is at 1.
r s )
3.
4.
e P
Wait 3 AWU RC cycles until the AWU_FLAG is set.
c t (
The switch to the AWU clock is made at the positive edge of the AWU clock signal.
5.
e t u
Once the switch is made, the internal RC is stopped.
l d
s o r o
Case 2: Switching from AWU RC to internal RC
1. b P
Reset the RC/AWU bit to enable the internal RC oscillator.
O e
2.
- e t
Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
l
( s )
running on internal RC clock.
o
3.
t s
Wait until the AWU_FLAG is cleared (1 AWU RC cycle) and the RC_FLAG is set (2 RC
c
cycles).
b
4.
d u O
The switch to the internal RC clock is made at the positive edge of the internal RC clock
-
r o
signal.
s )
Note: 1
e P
5.
c (
Once the switch is made, the AWU RC is stopped.
t
When the internal RC is not selected, it is stopped so as to save power consumption.
l e2t d u
When the internal RC is selected, the AWU RC is turned on by hardware when entering
s o o
Auto Wake-up from Halt mode.
r
O b 3
e P
When the external clock is selected, the AWU RC oscillator is always on.
l e t Figure 9. Clock switching
s o Set RC/AWU
b
Internal RC AWU RC
Poll AWU_FLAG until set
O
Reset RC/AWU
AWU RC Internal RC
Poll RC_FLAG until set
28/124
6.2.1 Main clock control/status register (MCCSR)
MCCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
Reserved MCO SMS
- R/W R/W
Table 7. MCCSR register description

Bit Name
( s )
Function
7:2 - Reserved, must be kept cleared.

c t
Main clock out enable
d u
1 MCO o
allows to enable the MCO output clock.
s )
This bit is read/write by software and cleared by hardware after a reset. This bit
r
P t (
0: MCO clock disabled; I/O port free for general purpose I/O
1: MCO clock enabled
e c
Slow mode select
l e t d u
0 SMS o r o
s P
selects the input clock fOSC or fOSC/32.
b
0: Normal mode (fCPU = fOSCC)
O e
- l e t
1: Slow mode (fCPU = fOSCC/32)
6.2.2
( s )
RC control register (RCCR) o
c t b s
RCCR
d u - O Reset value: 1111 1111 (FFh)
r7
o s )
6 5 4 3 2 1 0
e P c t ( CR[9:2]
l e t d u R/W
s o r
Table 8.
o RCCR register description
O b Bit
e P Name Function
l e t RC oscillator frequency adjustment bits

These bits, as well as CR[1:0] bits in the SICSR register must be written
s o immediately after reset to adjust the RC oscillator frequency and to obtain the
O b 7:0 CR[9:2]
required accuracy. The application can store the correct value for each voltage
range in Flash memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of different values in the register until the
correct frequency is reached. The fastest method is to use a dichotomy starting with
80h.
29/124
6.2.3 System integrity (SI) control/status register (SICSR)
SICSR Reset value: 0000 0x00 (0xh)

7 6 5 4 3 2 1 0
Reserved CR[1:0] Reserved LVDRF Reserved
- R/W - R/W -
Table 9. SICSR register description

Bit Name Function
7 - Reserved, must be kept cleared.

RC oscillator frequency adjustment bits
( s )
6:5 CR[1:0]
c t
These bits, as well as CR[9:2] bits in the RCCR register must be written
d u
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. Refer to Section 6.1 on page 31.
4:3 -
r o
Reserved, must be kept cleared.
s )
2:0 LVDRF
System integrity bits
e P c t (
1:0 -
l t d
Reserved, must be kept cleared.u
Refer to Section 7.4: System integrity management (SI).
e
s o r o
6.2.4 b P
Internal RC prescaler selection register (INTRCPRR)
O e
- l e t
INTRCPRR
( s ) o
Reset value: 0000 0011 (03h)
7
c t 6
b s 5 4 3 2 1 0
d u CK[2:0]
- O Reserved
r o s )
R/W -
P
Table 10.
e c t (
INTRCPRR register description
l e tBit
d u
Name Function
s o r o Internal RC prescaler selection
O b e P These bits are set by software and cleared by hardware after a reset. These bits
select the prescaler of the internal RC oscillator as follows (see also Figure 13 on
l e t page 37):
000: fOSC = 8 MHz
s o 7:5 CK[2:0]
001: fOSC = 4 MHz
010: fOSC = 2 MHz
O b 011: fOSC = 1 MHz

100: fOSC = 500 kHz
Notes:
1. If the internal RC is used with a supply operating range below 3.3V, a division
ratio of at least 2 must be enabled in the RC prescaler.
2. Configuration '000' is not allowed at 3.3V operation.
30/124
6.2.5 Clock controller control/status register (CKCNTCSR)
CKCNTCSR Reset value: 0000 1001 (09h)

7 6 5 4 3 2 1 0
Reserved AWU_FLAG RC_FLAG Reserved RC/AWU
- R/W R/W - R/W
Table 11. CKCNTCSR register description

Bit Name Function

AWU selection
( s )
3 AWU_FLAG
c t
This bit is set and cleared by hardware.
d u
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
RC Selection
r o s )
2 RC_FLAG
e P c
0: No switch from RC to AWU requestedt (
This bit is set and cleared by hardware.
e t u
1: RC clock activated and temporization completed
l d
1 -
o o
s r
0 RC/AWU
O b
RC/AWU selection
0: RC enabled
e P
- t
1: AWU enabled (default value)
l e
( s ) o
Table 12.
Address Register
c b s
Clock register map and reset values
t
(Hex.) label
d u 7
- O 6 5 4 3 2 1 0
0038h
r
MCCSR
o s ) MCO SMS
e P
Reset value
c t ( 0 0 0 0 0 0 0 0
0039h
l e t RCCR
u
Reset value
d
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
s o
003Ah
SICSR
r o
Reset value 0
CR1
0
CR0
0 0 0
LVDRF
x 0 0
O b e P
INTRCPRR CK2 CK1 CK0
003Eh
l e t Reset value 0 0 0 0 0 0 1 1
o
003Fh
s
CKCNTCSR
Reset value 0 0 0 0
AWU_FLAG RC_FLAG
1 0 0
RC/AWU
1
O b
31/124
Figure 10. Clock management block diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 RCCR
CR1 CR0 SICSR
Tunable
internal RC oscillator RC/AWU CKCNTCSR
8 MHz(fRC)
8 MHz
( s ) Clock
Prescaler
4 MHz
2 MHz
1 MHz
RC OSC
c t controller fOSC
500 kHz
d u AWU CK
r o s ) Ext clock
CK2 CK1 CK0
e P c t ( INTRCPRR
l e t d u CKSEL[1:0]
option bits
AWU
RC
s o 33 kHz
r o
O
/2b e P
CLKIN
fCLKIN
-
divider
l e t
( s ) o
c t b s
d u - O 13-bit
Lite timer counter
fLTIMER
(1ms timebase @ 8 MHz fOSC)
r o s ) fOSC
e P c t ( 0
fCPU
l e t fOSC
d u /32 divider fOSC/32

1
To CPU and
peripherals
s o r o
O b e P MCO SMS MCCSR
l e t MCO
s o
O b
32/124
6.3 Reset sequence manager (RSM)
6.3.1 Introduction
The reset sequence manager includes three reset sources as shown in Figure 15:
● External RESET source pulse
● Internal LVD reset (low voltage detection)
● Internal watchdog reset
Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Figure 15.
These sources act on the RESET pin which is always kept low during the delay phase.
( s )
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
c t
Figure 11. Reset block diagram
d u
VDD
r o s )
e P c t (
l
RON
e t d u
s o r o Internal
RESET
O b e P Filter
reset
- l e t
( s ) o Pulse
Watchdog reset
Illegal opcode reset(1)
c t b s generator
LVD reset
d u - O
r o s )
1. See Illegal opcode reset on page 99 for more details on illegal opcode reset conditions.
P t (
The basic reset sequence consists of three phases as shown in Figure 16:
e c
l e t●
●
d u
Active phase depending on the reset source
64 CPU clock cycle delay
s o ●
r o
Reset vector fetch
O b
Caution: P
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
e
l e tnot programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
s o The 64 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery
O b has taken place from the reset state.

The reset vector fetch phase duration is 2 clock cycles.
Figure 12. Reset sequence phases
Reset
Internal reset Fetch

Active phase
64 clock cycles vector
33/124
6.3.2 Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Chapter 12: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least th(RSTL)in
in order to be recognized (see Figure 17). This detection is asynchronous and therefore the
MCU can enter reset state even in halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 12:
Electrical characteristics.
( s )
6.3.3 External power-on reset
c t
d u
If the LVD is disabled by the option byte, to start up the microcontroller correctly, the user
must ensure by means of an external reset circuit that the reset signal is held low until VDD
r o )
is over the minimum level specified for the selected fCLKIN frequency.
s
P t (
A proper reset signal for a slow rising VDD supply can generally be provided by an external
e c
RC network connected to the RESET pin.
l e t d u
6.3.4
o
Internal low voltage detector (LVD) reset
s r o
b P
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
O e
● Power-on reset
- l e t
●
( s )
Voltage drop reset
o
c t b s
The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or
VDD < VIT- (falling edge) as shown in Figure 17.
d u - O
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
r o s )
6.3.5
P (
Internal watchdog reset
e c t
l e t
Figure 17.
d u
The reset sequence generated by an internal watchdog counter overflow is shown in
s o r o
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
O b P
is pulled low during at least tw(RSTL)out.
e
l e t
s o
O b
34/124
Figure 13. Reset sequences

VDD
VIT+(LVD)
VIT-(LVD)
LVD External Watchdog

reset reset reset
RUN RUN RUN RUN
Active Active
Active phase phase phase
( s )
th(RSTL)in
c t tw(RSTL)out
External
d u
RESET
source
r o s )
e P c t (
RESET pin
l e t d u
Watchdog
reset
s o r o
O b e P Watchdog underflow
- l e t Internal reset (64 TCPU)
)
Vector fetch
t ( s s o
u c O b
o d ) -
P r ( s
t e c t
l e d u
s o r o
O b e P
l e t
s o
O b
35/124
6.4.1 Multiplexed I/O reset control register 1 (MUXCR1)
MUXCR1 Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
MIR[15:8]
Read/write once only
6.4.2 Multiplexed I/O reset control register 0 (MUXCR0)
( s )
MUXCR0
c t Reset value: 0000 0000 (00h)
7 6 5 4
d u 3 2 1 0
r o MIR[7:0]
s )
P t (
Read/write once only
e c
Table 13.
l e t
MUXCRx register description
d u
Bit Name
s o r o Function
b P
This 16-bit register is read/write by software but can be written only once between
O e
l e t
two reset events. It is cleared by hardware after a reset. When both MUXCR0 and
-
MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin acts as RESET. To
s ) o
configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
(
c t b s
These registers are one-time writable only.
– To configure PA3 as general purpose output:
d u
15:0 MIR[15:0]
O
After power-on/reset, the application program has to configure the I/O port by
-
r o writing to these registers as described above. Once the pin is configured as an
s )
I/O output, it cannot be changed back to a RESET pin by the application code.
e P c t (
– To configure PA3 as RESET:
t
An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear
l e d u the two registers and the pin will act again as a reset function. Otherwise, a
power-down is required to put the pin back in reset configuration.
s o r o
O b e P
Table 14. Multiplexed I/O register map and reset values
l e tAddress (Hex.) Register label
MUXCR0
7
MIR7 MIR6
6 5
MIR5
4
MIR4 MIR3
3 2
MIR2
1
MIR1 MIR0
0
s o 0047h
Reset value 0 0 0 0 0 0 0 0
O b 0048h
MUXCR1
Reset value
MIR15 MIR14 MIR13 MIR12 MIR11 MIR10 MIR9
0 0 0 0 0 0 0
MIR8
0
36/124
ST7LUS5, ST7LU05, ST7LU09 Interrupts
7 Interrupts
The ST7 core may be interrupted by one of two different methods: Maskable hardware
interrupts as listed in Table 15: Interrupt mapping on page 46 and a non-maskable software
interrupt (TRAP). The interrupt processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
Section 7.2: External interrupts).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
●
s )
Normal processing is suspended at the end of the current instruction execution.
(
●
t
The PC, X, A and CC registers are saved onto the stack.
c
●
●
d u
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
r o )
instruction of the interrupt service routine is fetched (refer to Table 15: Interrupt
s
mapping for vector addresses).
e P c t (
l e t d u
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
s o r o
As a consequence of the IRET instruction, the I bit is cleared and the main program
resumes.
O b e P
Priority management
- l e t
s ) o
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
(
t
entering in interrupt routine.
c b s
d u - O
In the case when several interrupts are simultaneously pending, a hardware priority defines
which one will be serviced first (see Table 15: Interrupt mapping).
r o s )
e P c t (
Interrupts and low power mode
l e t
All interrupts allow the processor to leave the Wait low power mode. Only external and
d u
specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer
s o o
to the “Exit from HALT” column in Table 15: Interrupt mapping).
r
b P
O7.1 Non-maskable
e
l e t software interrupt
s o This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It is serviced according to the flowchart in Figure 18.
O b
37/124
Interrupts ST7LUS5, ST7LU05, ST7LU09
7.2 External interrupts

External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the miscellaneous or interrupt register (if available) applies
to the ei source.
( s )
7.3 Peripheral interrupts
c t
d u
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
r o s )
●
●
e P
The I bit of the CC register is cleared.
c t (
The corresponding enable bit is set in the control register.
l e t d u
If any of these two conditions is false, the interrupt is latched and thus remains pending.
s o r o
An interrupt request is cleared by doing one of the following:
●
b P
Writing ‘0’ to the corresponding bit in the status register
O e
●
- l e t
Accessing the status register while the flag is set followed by a read or write of an
( s )
associated register.
o
Note:
c t b s
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
38/124
Figure 14. Interrupt processing flowchart
From reset
N
I bit set?
Y N Interrupt
pending?
Y
Fetch next instruction
( s )
N
c t
IRET?
Stack PC, X, A, CC
d u Y
set I bit
load PC from interrupt vector
Execute instruction
r o s )
e P c t (
l e t d u
Restore PC, X, A, CC from stack
this clears I bit by default
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
39/124
Table 15. Interrupt mapping

Exit
Priority
No. Source block Description Register label from Address vector
order
HALT
RESET Reset yes FFFEh-FFFFh

N/A
TRAP Software Interrupt no FFFCh-FFFDh
0 AWU Auto wake-up interrupt AWUCSR yes(1) FFFAh-FFFBh
1 ei0 External interrupt 0 FFF8h-FFF9h
2 ei1 External interrupt 1 Highest yes FFF6h-FFF7h
priority
3 ei2 External interrupt 2 FFF4h-FFF5h
4 Not used
( s ) N/A
no FFF2h-FFF3h
5 ei3 External interrupt 3
c t yes FFF0h-FFF1h
6(2)
ei4(2) External interrupt 4(2)
d u no(2) FFEEh-FFEFh
7 Not used
r o s ) no FFECh-FFEDh
8 Auto-reload
e P
Auto-reload timer output compare
c t ( PWMxCSR or
no FFEAh-FFEBh
9
timer
interrupt
l e t d u
Auto-reload timer overflow interrupt
ATCSR
ATCSR yes(3) FFE8h-FFE9h
10
s o r o
Lite timer input capture interrupt LTCSR no FFE6h-FFE7h
11
Lite timer
b
Lite timer RTC1 interrupt
O e P LTCSR
Lowest
priority yes (3)
FFE4h-FFE5h
12 Not used
- l e t no FFE2h-FFE3h
13
s )
Not used
( o no FFE0h-FFE1h
c t b s
1. This interrupt exits the MCU from “auto wake-up from halt” mode only.
d u - O
2. This interrupt exits the MCU from “wait” and “active halt” modes only. Moreover, IS4[1:0] = 01 is the only safe configuration
to avoid a spurious interrupt in Halt and AWUFH mode.
r o )
3. These interrupts exit the MCU from “active halt” mode only.
s
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
40/124
7.3.1 External interrupt control register 1 (EICR1)
EICR1 Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
Reserved IS2[1:0] IS1[1:0] IS0[1:0]
- R/W R/W R/W
Table 16. EICR1 register description

Bit Name Function
7:6 - Reserved
ei2 sensitivity
( s )
5:4 IS2[1:0]
c t
These bits define the interrupt sensitivity for ei2 according to Table 18.
3:2 IS1[1:0]
ei1 sensitivity
d u
o )
r s
1:0 IS0[1:0]
ei0 sensitivity
e P c t (
Note: 1
l e t d u
These 8 bits can be written only when the I bit in the CC register is set.
2
s o r o
Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
function on page 66.

O b e P
can be used to clear unwanted pending interrupts. Refer to section External interrupt
- l e t
7.3.2
s ) o
External interrupt control register 2 (EICR2)
(
c t b s
EICR2
d u - O Reset value: 0000 0000 (00h)
r o7
s )
6 5 4 3 2 1 0
e P c t ( Reserved IS4[1:0] IS3[1:0]
l e t d u
- R/W R/W
s o r o
Table 17. EICR2 register description
O b e P
Bit Name Function
l e t 7:4 - Reserved
ei4 sensitivity
s o 3:2 IS4[1:0]
O b 1:0 IS3[1:0]
ei3 sensitivity
41/124
Note: 1 These 8 bits can be written only when the I bit in the CC register is set.
2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to section External interrupt
function on page 66.
3 IS4[1:0] = 01 is the only safe configuration to avoid a spurious interrupt in Halt and AWUFH
modes.
Table 18. Interrupt sensitivity bits

ISx1 ISx0 External interrupt sensitivity
0 0 Falling edge and low level

0 1 Rising edge only
1 0
( s )
Falling edge only
1 1
c t
Rising and falling edge
d u
7.4 System integrity management (SI) r o s )
e P c t (
is managed by the SICSR register.
l e t
The system integrity management block contains the low voltage detector (LVD) function. It
d u
Note:
o r o
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
s
b P
Refer to Illegal opcode reset on page 99 for further details.
O e
7.4.1
-
Low voltage detector (LVD)
l e t
( s ) o
The low voltage detector function (LVD) generates a static reset when the VDD supply
t b s
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
c
d u
as the power-down keeping the ST7 in reset.
- O
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
r o s )
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
e P t (
current on the supply (hysteresis).
c
l e t ●
d u
The LVD Reset circuitry generates a reset when VDD is below:
VIT+(LVD) when VDD is rising
s o ●
r o
VIT-(LVD) when VDD is falling
O b e P
The LVD function is illustrated in Figure 19.
l et The high voltage threshold can be activated by option byte. See Section 14.1 on page 131.
s o Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
O b the MCU can only be in two modes:

● under full software control
● in static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
42/124
Note: Use of LVD with capacitive power supply: If power cuts occur in the application with this type
of power supply, it is recommended to pull VDD down to 0V to ensure optimum restart
conditions. Refer to circuit example in Figure 67 and Note 4 on page 124.
The LVD is an optional function which can be selected by option byte (see Section 14.1 on
page 131). It allows the device to be used without any external reset circuitry. If the LVD is
disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from reset, to ensure the application functions properly.
Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD takes priority and
clears the watchdog flag.
Figure 15. Low voltage detector vs. reset

VDD
( s )
c t
Vhys
VIT+(LVD)
VIT-(LVD)
d u
r o s )
e P c t (
RESET
l e t d u
s o r o
b P
Figure 16. Reset and supply management block diagram
O e
- l e t
( s ) o
Watchdog
timer (WDG)
Status flag
c t b s
d u - O Reset sequence
System integrity management
r o
RESET
s ) manager SICSR
e P c t ( (RSM)
0 0 0 0 0
LVD
RF 0 0
l e t d u
7 0
s o r o Low voltage
O b e P VSS detector
l e t VDD (LVD)
s o
O b
43/124
7.4.2 SI register description

System integrity (SI) control/status register (SICSR)
SICSR Reset value: 0000 0x00 (0xh)

7 6 5 4 3 2 1 0
Reserved CR[1:0] Reserved LVDRF Reserved
- R/W - R/W -
Table 19. SICSR register description

Bit Name
( s ) Function
7 -
t
c
6:5 CR[1:0]
d u
RC oscillator frequency adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be written
r o )
immediately after reset to adjust the RC oscillator frequency and to obtain the
s
4:3 -
e P c
Reserved, must be kept cleared (
required accuracy. Refer to Section 6.1 on page 31.
t
LVD reset flag
l e t d u
o r o
This bit indicates that the last reset was generated by the LVD block. It is set by
s
hardware (LVD reset) and cleared when read. See WDGRF flag description in
b P
Section 10.1 for more details. When the LVD is disabled by option byte, the LVDRF
O e
2 LVDRF
- l e t
bit value is undefined.
Note: If the selected clock source is one of the two internal ones, and if VDD
( s ) o
remains below the selected LVD threshold during less than TAWU (33µs typ.), the
c t b s
LVDRF flag cannot be set even if the device is reset by the LVD.
If the selected clock source is the external clock (CLKIN), the flag is never set if the
d u - O
reset occurs during halt mode. In Run mode the flag is set only if fCLKIN is greater
than 10 MHz.
r
1:0 o -
s ) Reserved, must be kept cleared
e P c t (
Application notes
l e t d u
The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the
s o r o
LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset
O b e P
can be detected by software while an external reset can not.
l e t Table 20. System integrity register map and reset values
s o Address
(Hex.)
Register
label
7 6 5 4 3 2 1 0
O b 003Ah
SICSR
Reset value 0
CR1
0
CR0
0 0 0
LVDRF
x 0 0
44/124
ST7LUS5, ST7LU05, ST7LU09 Power saving modes
8 Power saving modes
8.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, five
main power saving modes are implemented in the ST7 (see Figure 21):
● Slow
● Wait (and slow wait)
● Active halt
● Auto wake-up from halt (AWUFH)
● Halt
( s )
c t
After a reset the normal operating mode is selected by default (run mode). This mode drives
the device (CPU and embedded peripherals) by means of a master clock which is based on
the main oscillator frequency (fOSC).
d u
r o )
From run mode, the different power saving modes may be selected by setting the relevant
s
oscillator status.
e P c t (
register bits or by calling the specific ST7 software instruction whose action depends on the
l e t
Figure 17. Power saving mode transitions
d u
s o r oHigh
O b e P
- l e tRun
( s ) o
c t b s Slow
d u - O Wait
r o s )
e P c t ( Slow wait
l e t d u Active halt
s o r o
O b e P Halt
l e t Low power consumption
s o
b
O8.2 Slow mode
This mode has two targets:
● To reduce power consumption by decreasing the internal clock in the device
● To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
slow mode.
45/124
Power saving modes ST7LUS5, ST7LU05, ST7LU09
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note: Slow wait mode is activated when entering wait mode while the device is already in slow
mode.
Figure 18. Slow mode clock transition
fOSC/32 fOSC
fCPU
fOSC
( s )
c t
SMS
d u
r o s )
e P c t (
NORMAL RUN MODE
REQUEST
l e t d u
8.3 Wait mode s o r o
O b e P
- l e t
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
( s )
This power saving mode is selected by calling the WFI instruction.
o
c t b s
All peripherals remain active. During wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
u O
in Wait mode until an interrupt or reset occurs, whereupon the program counter branches to
d -
r o
the starting address of the interrupt or reset service routine.
s )
e P c t (
The MCU will remain in wait mode until a reset or an Interrupt occurs, causing it to wake up.
l e t
Refer to Figure 24 on page 54.
d u
s o r o
O b e P
l et
s o
O b
46/124
Figure 19. Wait mode flowchart
Oscillator On
Peripherals On
WFI instruction
CPU Off
I bit 0
N
Reset
N Y
Interrupt
( s )
Oscillator On
c t Peripherals
CPU
Off
On
d u I bit 0
r o s )
e P c t ( 64 CPU clock cycle
delay
l e t d u Oscillator On
s o r o Peripherals On
O b e P CPU
I bit
On
X (1)
- l e t
( s ) o Fetch reset vector
c t b s or service interrupt
d u - O
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
o )
during the interrupt routine and cleared when the CC register is popped.
r smodes
8.4
e P
Active
c t
halt and halt(
l e t d u
Active halt and halt modes are the two lowest power consumption modes of the MCU. They
s o r o
are both entered by executing the HALT instruction. The decision to enter either in active
O b e P
halt or halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
l et
Table 21. LTC/ATC low power mode selection
s o LTCSR TBIE bit ATCSR OVFIE bit ATCSRCK1 bit ATCSRCK0 bit Meaning
O b 0 x x 0
Active halt mode
0 0 x x
disabled
0 1 1 1
1 x x x Active halt mode
x 1 0 1 enabled
47/124
8.4.1 Active halt mode

Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the HALT instruction when active halt mode is enabled.
The MCU can exit active halt mode on reception of a lite timer/auto-reload timer interrupt or
a reset.
● When exiting active halt mode by means of a reset, a 64 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation by fetching the reset vector which woke
it up (see Figure 27).
● When exiting active halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see Figure 27).
When entering active halt mode, the I bit in the CC register is cleared to enable interrupts.
s )
Therefore, if an interrupt is pending, the MCU wakes up immediately.
(
c t
In active halt mode, only the main oscillator and the selected timer counter (lite timer/auto-
d u
reload timer) are running to keep a wake-up time base. All other peripherals are not clocked
except those which get their clock supply from another clock generator (such as external or
auxiliary oscillator).
r o s )
Caution: P t (
As soon as active halt is enabled, executing a HALT instruction while the watchdog is active
e c
l e t
does not generate a reset if the WDGHALT bit is reset. This means that the device cannot
d u
spend more than a defined delay in this power saving mode.
s o
Figure 20. Active halt timing overview r o
O b e P
- l e t
( s ) o
Run
Active
halt
64 CPU
cycle delay(1) Run
c t b s Reset
d u - O HALT
or
interrupt
r o s ) instruction
[active halt enabled]
Fetch
vector
e P c t (
l e t d u
1. This delay occurs only if the MCU exits active halt mode by means of a reset.
s o r o
O b e P
l e t
s o
O b
48/124
Figure 21. Active halt mode flowchart
Oscillator On
HALT instruction Peripherals(1) Off
(active halt enabled) CPU Off
I bit 0
N
Reset
N Y
Interrupt(2)
Y
( s )
Oscillator On
c t Peripherals(1)
CPU
Off
On
d u I bit X(3)
r o s )
64 CPU clock cycle
e P c t ( delay
l e t d u Oscillator On
s o r o Peripherals
CPU
On
On
O b e P I bits X(3)
- l e t
( s ) o
Fetch reset vector
or service interrupt
c t b s
d u - O
1. Peripherals clocked with an external clock source can still be active.
2. Only the lite timer RTC and auto-reload timer interrupts can exit the MCU from active halt mode.
r o )
s
e P c t (
8.4.2
l e t
Halt mode
d u
s o r o
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the HALT instruction when active halt mode is disabled.
O b P
The MCU can exit halt mode on reception of either a specific interrupt (see Table 15:
e
l e t
Interrupt mapping on page 46) or a reset. When exiting halt mode by means of a reset or an
interrupt, the main oscillator is immediately turned on and the 64 CPU cycle delay is used to
s o stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or
O b by fetching the reset vector which woke it up (see Figure 30).

When entering halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
49/124
The compatibility of watchdog operation with halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see Section 14.1 on page 131 for more
details).
Figure 22. Halt timing overview
64 CPU cycle
Run Halt delay Run
Reset(1)
or
HALT interrupt
instruction
[active halt disabled]
( s ) Fetch
vector
c t
u
1. A reset pulse of at least 42µs must be applied when exiting from halt mode.
d
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
50/124
Figure 23. Halt mode flowchart
HALT instruction
(active halt disabled)
Enable
Watchdog
0 Disable
WDGHALT(1)
Watchdog Oscillator Off

reset Peripherals(2) Off
CPU Off
( s ) I bit 0
c t N
d u Reset
N
r o
Interrupt(3)
s ) Y
e PY
c t ( Oscillator On
l e t d u Peripherals
CPU
Off
On
s o r o I bit X(4)
O b e P 64 CPU clock cycle
- l e t delay(5)
( s ) o
c t b s Oscillator
Peripherals
On
On
d u - O CPU
I bits
On
X(4)
r o s )
e P c t ( Fetch reset vector
or service interrupt
l e t d u
1. WDGHALT is an option bit. See option bytes in Section 14.1.1: Flash configuration for more details.
s o r o
2. Peripheral clocked with an external clock source can still be active.
O b e P
3. Only some specific interrupts can exit the MCU from halt mode (such as external interrupt). Refer to
Table 15: Interrupt mapping on page 46 for more details.
l e t
s o 5. The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering halt mode.
O b
51/124
Halt mode recommendations

● Make sure that an external event is available to wake up the microcontroller from Halt
mode.
● When using an external interrupt to wake up the microcontroller, re-initialize the
corresponding I/O as “input pull-up with interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
● For the same reason, re-initialize the level sensitiveness of each external interrupt as a
precautionary measure.
● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E.
( s )
0x8E from memory. For example, avoid defining a constant in ROM with the value
●
c t
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
d u
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
r o )
interrupt routine corresponding to the wake-up event (reset or external interrupt).
s
e P c t (
8.5 Auto wake-up from halt mode
l e t d u
o r o
Auto Wake-up from Halt (AWUFH) mode is similar to halt mode with the addition of a
s
O b e P
specific internal RC oscillator for wake-up (auto wake-up from halt oscillator) which replaces
the main clock which was active before entering halt mode. Compared to Active Halt mode,
- t
AWUFH has lower power consumption (the main clock is not kept running), but there is no
l e
( s )
accurate real-time clock available.
o
c t
register has been set.
b s
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
d u - O
r o
Figure 24. AWUFH mode block diagram
s )
e P c t ( AWU RC
l e t d u
oscillator
to 8-bit timer input capture
s o r o fAWU_RC
O b e P AWUFH
l et /64
divider
AWUFH
prescaler/1 .. 255
interrupt
s o (ei0 source)
O b
52/124
As soon as halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
● The AWUF flag is set by hardware,
● an interrupt wakes up the MCU from halt mode,
● The main oscillator is immediately turned on and the 64 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
( s )
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
c t
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
d u
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in run
mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the
r o )
fAWU_RC to be measured using the main oscillator clock as a reference timebase.
s
Similarities with halt mode
e P c t (
l e t d u
The following AWUFH mode behavior is the same as normal halt mode:
●
o o
The MCU can exit AWUFH mode by means of any interrupt with exit from halt capability
s r
or a reset (see Section 8.4: Active halt and halt modes).
●
b P
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
O e
- l e t
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
●
( s )
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
o
stopped, including the operation of the on-chip peripherals. None of the peripherals are
t b s
clocked except those which get their clock supply from another clock generator (such
c
●
d u
as an external or auxiliary oscillator like the AWU oscillator).
- O
The compatibility of watchdog operation with AWUFH mode is configured by the
r o )
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
s
e P c t (
when executed while the watchdog system is enabled, can generate a watchdog reset.
l e t d u
Figure 25. AWUF halt timing diagram
s o r o tAWU
O b e P Run mode Halt mode 64 tCPU Run mode
l e t fCPU
s o fAWU_RC
O b AWUFH interrupt
Clear
by software
53/124
Figure 26. AWUFH mode flowchart
HALT instruction
(active halt disabled)
(AWUCSR.AWUEN=1)
Enable
Watchdog
0 Disable
WDGHALT(1)
1
AWU RC OSC On
Watchdog Main OSC Off
reset
( s ) Peripherals(2)
CPU
Off
Off
c t I[1:0] bits 10
d u
r o s ) N
Reset
e P c t ( Y
N
l e t d u
Interrupt(3)
AWU RC OSC Off
s o Y
r o Main OSC On
O b e P Peripherals
CPU
Off
On
XX(4)
- l e t I[1:0] bits
( s ) o 64 CPU clock
c t b s cycle delay
d u - O AWU RC OSC Off
r o s )
Main OSC
Peripherals
On
On
e P c t ( CPU
I[1:0] bits
On
XX(4)
l e t d u Fetch reset vector
s o r o or service interrupt
O b e P
l e t
1. WDGHALT is an option bit. See option bytes in Section 14.1.1: Flash configuration for more details.
2. Peripheral clocked with an external clock source can still be active.
s o 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from halt mode (such as external
interrupt). Refer to Table 15: Interrupt mapping on page 46 for more details.
O b 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
54/124
8.5.1 Register description

AWUFH control/status register (AWUCSR)
AWUCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
Reserved AWUF AWUM AWUEN
- R/W R/W R/W
Table 22. AWUCSR register description

Bit Name
)
Function
( s
7:3 - Reserved
c t
Auto wake-up flag
d u
This bit is set by hardware when the AWU module generates an interrupt and
2 AWUF
r o )
cleared by software on reading AWUCSR. Writing to this bit does not change its
s
value.
P
0: No AWU interrupt occurred
e c t (
l e t
1: AWU interrupt occurred
Auto wake-up measurement
d u
s o r o
This bit enables the AWU RC oscillator and connects its output to the input capture
1 AWUM
O b P
of the 8-bit lite timer. This allows the timer to be used to measure the AWU RC
e
oscillator dispersion and then compensate this dispersion by providing the right
- t
value in the AWUPRE register.
l e
( s )
0: Measurement disabled
o
1: Measurement enabled
c t b s
Auto wake-up from halt enabled
d u - O
This bit enables the auto wake-up from halt feature: Once halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU
0
r o
AWUEN )
prescaler value. It is set and cleared by software.
s
e P c t (
0: AWUFH (auto wake-up from halt) mode disabled
1: AWUFH (auto wake-up from halt) mode enabled
l e t d u Note: Whatever the clock source, this bit should be set to enable the AWUFH mode
once the HALT instruction has been executed.
s o r o
O b e P
l e t
s o
O b
55/124
AWUFH prescaler register (AWUPR)
AWUPR Reset value: 1111 1111 (FFh)

7 6 5 4 3 2 1 0
AWUPR[7:0]
R/W
Table 23. AWUPR register description

Bit Name Function
Auto wake-up prescaler
s )
These 8 bits define the AWUPR division factor (as explained below).
(
7:0 AWUPR[7:0]
c t
This prescaler register can be programmed to modify the time that the MCU stays in halt
mode before waking up automatically.
u
Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated
d
o
immediately after a HALT instruction, or the AWUPR remains unchanged.
P r ( s )
Table 24. AWUPR division factors
t e c t
AWUPR[7:0]
00h
l e d u Division factor
Forbidden
01h
s o r o 1
...
O b e P ...
FEh
- l e t 254
FFh
( s ) o 255
c t b s
In AWU mode, the period that the MCU stays in halt mode (tAWU in Figure 32 on page 61) is defined by:
d u - O 1
t AWU = 64 × AWUPR × -------------------------- + t RCSTRT
r o s )
f AWURC
P t (
This prescaler register can be programmed to modify the time that the MCU stays in halt mode before
e c
Note:
l e t
waking up automatically.
d u
If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately
s o r o
after a HALT instruction, or the AWUPR remains unchanged.
O b
Table 25.
e P AWU register map and reset values
l e t
Address (Hex.) Register label 7 6 5 4 3 2 1 0
s o 004Ah
AWUCSR AWUF AWUM AWUEN
O b 0049h
Reset value
AWUPR
0 0 0 0 0
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0 0 0
Reset value 1 1 1 1 1 1 1 1
56/124
ST7LUS5, ST7LU05, ST7LU09 I/O ports
9 I/O ports
9.1 Introduction
The I/O port offers different functional modes:
● transfer of data through digital inputs and outputs
and for specific pins:
● external interrupt generation
● alternate signal input/output for the on-chip peripherals.
An I/O port contains up to six pins. Each pin (except PA3/RESET) can be programmed
s )
independently as digital input (with or without interrupt generation) or digital output.
(
c t
9.2 Functional description
d u
Each port has two main registers:
r o s )
● Data register (DR)
e P c t (
● Data direction register (DDR)
l e t d u
and one optional register:
● Option register (OR)
s o r o
O b e P
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
- t
registers, with bit X corresponding to pin X of the port. The same correspondence is used for
l e
the DR register.
( s ) o
c t b s
The following description takes into account the OR register (for specific ports which do not
provide this register refer to Section 9.6: I/O port implementation). The generic I/O block
u O
diagram is shown in Figure 35.
d -
9.2.1 r o
Input modes
s )
e P c t (
l e t The input configuration is selected by clearing the corresponding DDR register bit.
d u
In this case, reading the DR register returns the digital value applied to the external I/O pin.
s o r o
Different input modes can be selected by software through the OR register.
O b
Note: 1 P
Writing the DR register modifies the latch value but does not affect the pin status.
e
l
2
et PA3 cannot be configured as input.
s o External interrupt function
O b When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
57/124
I/O ports ST7LUS5, ST7LU05, ST7LU09
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to ‘1’ when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a “safe” edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution: In case a pin level change occurs during these operations (asynchronous signal
input), as interrupts are generated according to the current sensitivity, it is advised to disable
all interrupts before and to re-enable them after the complete previous sequence in order to
( s )
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
1. To enable an external interrupt:
c t
a)
d u
set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
r o s )
b)
c)
select rising edge
e P c t (
enable the external interrupt through the OR register
d)
l e t d u
select the desired sensitivity if different from rising edge
e)
o r o
reset the interrupt mask with the RIM instruction (in cases where a pin level
s
2.
O b
change could occur)
To disable an external interrupt:
e P
a)
- e t
set the interrupt mask with the SIM instruction SIM (in cases where a pin level
l
) o
change could occur)
( s
b)
t s
select falling edge
c b
c)
d)
d u disable the external interrupt through the OR register
- O
select rising edge
r o s )
9.2.2
P
Output modes
e c t (
l e t d u
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
s o r o
reading the DR register returns the previously stored value.
O b P
Two different output modes can be selected by software through the OR register: Output
e
l e t push-pull and open-drain.
s o Table 26. I/O output mode selection
O b DR
0
Push-pull
VSS
Open-drain
VSS
1 VDD Floating
Note: When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
58/124
9.2.3 Alternate functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming under the
following conditions:
● When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
● When the signal is going to an on-chip peripheral, the I/O pin must be configured in
floating input mode. In this case, the pin state is also digitally readable by addressing
the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input.
s )
When an on-chip peripheral use a pin as input and output, this pin has to be configured in
(
input floating mode.
c t
Figure 27. I/O port general block diagram
d u
r o s )
Register
Alternate
e P 1
c t (
t
output VDD P-buffer
access
l e 0
d u (see Table 28 below)
s o
Alternate
enable
r o P-buffer
(see Table 28 below)
DR
O b e P VDD
- l e t
(
DDR
s ) o
c t OR
b s Pull-up
condition
Pad
u O
DATA BUS
If implemented
o d )
OR SEL
-
P r ( s N-buffer
t
Diodes
(see Table 28 below)
e t e u c DDR SEL
Analog
o l o d CMOS
input
b s P r DR SEL
1
SCHMITT
TRIGGER
O t e 0
Alternate
o l e EXTERNAL
FROM
input
b s INTERRUPT
SOURCE (eix)
POLARITY
OTHER
BITS
O
SELECTION
59/124
Table 27. I/O port mode options(1)

Diodes
Configuration mode Pull-up P-buffer
to VDD to VSS
Floating with/without interrupt Off

Input Off
Pull-up with/without interrupt On
On On
Push-pull On
Output Off
Open drain (logic level) Off
1. Off = implemented not activated
On = implemented and activated
Table 28. I/O port configurations
( s )
c t Hardware configuration
VDD
d u DR REGISTER ACCESS
r
RPUo s )
PULL-UP
W
(
DR
Pad
e P c t
CONDITION
REGISTER
R
DATA BUS
l e t d u
Input(1)
s o r o FROM
ALTERNATE INPUT
O b e P OTHER
PINS EXTERNAL INTERRUPT
SOURCE (eix)
- l e t INTERRUPT POLARITY
( s ) o
CONDITION SELECTION
c t b s ANALOG INPUT
d u - O VDD
DR REGISTER ACCESS
Open-drain output(2)
r o s ) RPU
P
R/W
(
DR
t REGISTER DATA BUS

Pad
e t e u c
o l o d
b s P r ALTERNATE
ENABLE
ALTERNATE
OUTPUT
O t e VDD
DR REGISTER ACCESS
e
PUSH-PULL output(2)
o l RPU
b s Pad
DR
REGISTER
R/W
DATA BUS
O
ALTERNATE ALTERNATE
ENABLE OUTPUT
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
60/124
Caution: The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have fast toggling pins
located close to a selected analog pin.
Warning:
s )
The analog input voltage level must be within the limits
(
t
stated in the absolute maximum ratings.
c
d u
r o s )
9.3 Unused I/O pins
e P c t (
l e t d u
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8.
s o r o
9.4 Low power modes
O b e P
Table 29.
- l e t
Effect of ow power modes on I/O ports
( s ) o
Mode
Wait
c t b s Description
No effect on I/O ports. External interrupts cause the device to exit from wait mode.
Halt
d u - O
No effect on I/O ports. External interrupts cause the device to exit from halt mode.
r o s )
9.5
e P
Interrupts
c t (
l e t d u
The external interrupt event generates an interrupt if the corresponding configuration is
s o r o
selected with DDR and OR registers and the interrupt mask in the CC register is not active
O b P
(RIM instruction).
e
l e t
Table 30. I/O port interrupt control/wake-up capability
s o Interrupt event Event flag

Enable
control bit
Exit from
wait
Exit from
halt
O b External interrupt on selected

external event
- DDRx, ORx Yes Yes
61/124
9.6 I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 36.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 28. Interrupt I/O port state transitions
01 00 10 11
Input Input
floating/pull-up floating
( s )
Output
open-drain
Output
push-pull
interrupt (reset state)
c t
d u XX = DDR, OR
r o s )
The I/O port register configurations are summarized in the following table:
e P c t (
Table 31. Port configuration
l e t d u
Input (DDR=0) Output (DDR=1)
Port Pin name
s o r o
O b OR = 0
e P OR = 1 OR = 0 OR = 1
Port A
PA0:2,
-
PA4:5
l e t
Floating Pull-up interrupt Open drain Push-pull
( s )
PA3
o - - Open drain Push-pull
c t b s
Note: After reset, to configure PA3 as a general purpose output, the application has to
u O
program the MUXCR0 and MUXCR1 registers. See Section 6.4 on page 42.
d -
r o
Table 32.
s )
I/O port register map and reset values
e P c t (
Address (Hex.) Register label 7 6 5 4 3 2 1 0
l e t d
0000hu PADR MSB LSB
s o r o Reset value 0 0 0 0 0 0 0 0
O b e P 0001h
PADDR
Reset value
MSB
0 0 0 0 1 0 0
LSB
0
l e t 0002h
PAOR
Reset value
MSB
0 0 0 0 0 0 1
LSB
0
s o
O b
62/124
ST7LUS5, ST7LU05, ST7LU09 On-chip peripherals
10 On-chip peripherals
10.1 Lite timer
10.1.1 Introduction
The lite timer can be used for general-purpose timing functions. It is based on a free-running
13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture
register and watchdog function.
10.1.2 Main features

● Real-time clock
( s )
– 13-bit upcounter
c t
–
u
1 ms or 2 ms timebase period (@ 8 MHz fOSC)
d
– Maskable timebase interrupt
r o s )
● Input capture
–
e P
8-bit input capture register (LTICR)
c t (
–
e t u
Maskable interrupt with wake-up from halt mode capability
l d
● Watchdog
s o r o
–
–
O b e P
Enabled by hardware or software (configurable by option byte)
Optional reset on HALT instruction (configurable by option byte)
–
- e t
Automatically resets the device unless disable bit is refreshed
l
–
s ) o
Software reset (forced watchdog reset)
(
–
t b s
Watchdog reset status flag
c
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
63/124
On-chip peripherals ST7LUS5, ST7LU05, ST7LU09
Figure 29. Lite timer block diagram
fLTIMER
To 12-bit auto-reload tImer
fWDG
Watchdog
Watchdog reset
fOSC
/2 1
Timebase
13-bit upcounter 1 or 2 ms
0
fLTIMER (@ 8 MHz
fOSC)
LTICR
8 MSB
( s )
c t
8-bit
d u
LTIC input capture
register
r o s )
LTCSR
e P c t (
l
ICIE
e t ICF TB
d u TBIE TBF
WDG
RF WDGE WDGD
7
s o r o 0
O b e P LTTB interrupt request
- l e t
( s ) o LTIC interrupt request
c t b s
10.1.3
u O
Functional description
d -
r o )
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts
s
e P c t (
incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the counter rolls over
from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1ms.
l e t d u
This period can be doubled by setting the TB bit in the LTCSR register.
s o r o
When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the
TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
O b e P
Watchdog
l e t
The watchdog is enabled using the WDGE bit. The normal watchdog timeout is 2ms (@ fOSC = 8 MHz),
s o
after which it then generates a reset.
O b
To prevent this watchdog reset from occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after tWDG. This means that software must write to the WDGD bit at regular intervals
to prevent a watchdog reset from occurring. Refer to Figure 38.
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be shorter than
2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed
after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set. For these
reasons, it is recommended to enable the watchdog immediately after reset or else to set the WDGD bit
before the WGDE bit so a watchdog reset will not occur for at least 2ms.
64/124
Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
The WDGRF bit also acts as a flag, indicating that the watchdog was the source of the reset.
It is automatically cleared after it has been read.
Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is
enabled (by hardware or software), the microcontroller will be immediately reset.
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
( s )
information.
c t
Refer to the option byte description in Chapter 14: Device configuration and ordering
Using halt mode with the watchdog (option)

d u
r o s )
If the watchdog reset on halt option is not selected by option byte, the halt mode can be
used when the watchdog is enabled.
e P c t (
l e t d u
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the lite
timer stops counting and is no longer able to generate a watchdog reset until the
o r o
microcontroller receives an external interrupt or a reset.
s
b P
If an external interrupt is received, the WDG restarts counting after 64 CPU clocks. If a reset
O e
- l e t
is generated, the watchdog is disabled (reset state).
( s )
If halt mode with watchdog is enabled by option byte (no watchdog reset on HALT
o
instruction), it is recommended before executing the HALT instruction to refresh the WDG
t b s
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
c
d u - O
Figure 30. Watchdog timing diagram
r o s ) Hardware clears
e P c t ( WDGD bit
l e t fWDG
d u tWDG
(2ms @ 8 MHz fOSC)
s o r o
O b P
WDGD bit
e
l e t Internal
watchdog Software sets
s o RESET WDGD bit

Watchdog RESET
O b
65/124
Input capture
The 8-bit input capture register is used to latch the free-running upcounter after a rising or
falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and
the LTICR register contains the MSB of the free-running upcounter. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
10.1.4 Low power modes
Table 33. Effect of low power modes on lite timer

Mode
( s ) Description
Wait
c t
No effect on lite timer
Active halt
d u
Halt
o )
Lite timer stops counting
r s
10.1.5 Interrupts
e P c t (
l e t d u
Table 34.
s o r o
Lite timer interrupt control/wake-up capability
Interrupt event
O bEvent flag
e P Enable control bit

Exit from
wait
Exit from
halt
Exit from
active halt
Timebase event
- TBF
l e t TBIE Yes
IC event
( s ) oICF ICIE
Yes No
No
Note:
c t b s
The TBF and ICF interrupt events are connected to separate interrupt vectors (see
u O
Chapter 7: Interrupts). They generate an interrupt if the enable bit is set in the LTCSR
d -
r o
register and the interrupt mask in the CC register is reset (RIM instruction).
s )
P t (
Figure 31. Input capture timing diagram
e c
l e t d u 125ns
(@ 8 MHz fOSC)
s o r o
O b e P fCPU
l e t fOSC
Cleared
by S/W
s o 13-bit counter 0001h 0002h 0003h 0004h 0005h 0006h 0007h

reading
LTIC register
O b LTIC pin
ICF flag
LTICR register xxh 04h 07h
66/124

Lite timer control/status register (LTCSR)
LTCSR Reset value: 0000 0x00 (0xh)

7 6 5 4 3 2 1 0
ICIE ICF TB TBIE TBF WDGRF WDGE WDGD
Table 35. LTCSR register description

Bit Name
( )
Function
s
Interrupt enable
c t
This bit is set and cleared by software.
7 ICIE
u
0: Input capture (IC) interrupt disabled
d
r o
1: Input capture (IC) interrupt enabled
s )
Input capture flag
P c t (
This bit is set by hardware and cleared by software by reading the LTICR register.
e
6 ICF
l t
0: No input capture
d u
Writing to this bit does not change the bit value.
e
s o r o
1: An input capture has occurred
Note: After an MCU reset, software must initialize the ICF bit by reading the LTICR
b
register.
O e P
- t
Timebase period selection
l e
5 TB
( s )
o
c t b s
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8 MHz)
d u O
Timebase interrupt enable
-
4
r o TBIE
s
)
0: Timebase (TB) interrupt disabled
e P c t ( 1: Timebase (TB) interrupt enabled
l e t d u
Timebase interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register.
s o 3
r o TBF Writing to this bit has no effect.
0: No counter overflow
O b e P 1: A counter overflow has occurred
l e t Force reset/reset status flag

This bit is used in two ways: It is set by software to force a watchdog reset. It is set
s o 2 WDGRF
by hardware when a watchdog reset occurs and cleared by hardware or by
O b software. It is cleared by hardware only when an LVD reset occurs. It can be

cleared by software after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
67/124
Table 35. LTCSR register description (continued)

Bit Name Function
Watchdog enable
1 WDGE
0: Watchdog disabled
1: Watchdog enabled
Watchdog reset delay
This bit is set by software. It is cleared by hardware at the end of each tWDG period.
0 WDGD
0: Watchdog reset not delayed
1: Watchdog reset delayed
Lite timer input capture register (LTICR)
( s )
LTICR
c t Reset value: 0000 0000 (00h)
7 6 5
d u
4 3 2 1 0
r o )
ICR[7:0]
s
e P c t (
RO
Table 36.
l e t
LTICR register description
d u
Bit Name
s o r o Function
b
Input capture value
O e P
7:0 ICR[7:0]
l e t
These bits are read by software and cleared by hardware after a reset. If the ICF
-
s )
bit in the LTCSR is cleared, the value of the 8-bit upcounter will be captured when
o
a rising or falling edge occurs on the LTIC pin.
(
Table 37.
c t b s
Lite timer register map and reset values
d u
Address
- O
Register
r o
(Hex.)
s ) label
7 6 5 4 3 2 1 0
e P 0B
c t ( LTCSR
Reset value
ICIE
0
ICF
0
TB
0
TBIE
0
TBF
0
WDGRF WDGE
x 0
WDGD
0
l e t d
0C u LTICR ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
s o r o Reset value 0 0 0 0 0 0 0 0
O b e P
l e t
s o
O b
68/124
10.2 12-bit autoreload timer
10.2.1 Introduction
The 12-bit autoreload timer can be used for general-purpose timing functions. It is based on
a free-running 12-bit upcounter with a PWM output channel.

● 12-bit upcounter with 12-bit autoreload register (ATR)
● Maskable overflow interrupt
● PWM signal generator
● Frequency range 2 kHz to 4 MHz (@ 8 MHz fCPU)
( s )
– Programmable duty-cycle
c t
–
–
Polarity control
Maskable compare interrupt
d u
● Output compare function
r o s )
Figure 32. Block diagram
e P c t (
l e t d u
o o
OVF interrupt
b s7 ATCSR
0 0
P0
r CK1 CK0 OVF OVFIE CMPIE
0 request
- O e t e
s ) o l CMPF0
CMP interrupt
request
(
fLTIMER
t
(1ms timebase
@ 8 MHz)
c b s fCOUNTER
u
12-bit upcounter
d
fCPU
- O CNTR Update on OVF event
r o s ) 12-bit autoreload value
e P c t ( ATR
OE0 bit
l e t DCR0H
d u DCR0L
OE0 bit CMPF0 bit
o o OP0 bit
PWM generation
Preload Preload
r
Output control
b s P
0
Compare
fPWM
Polarity PWM0
O t e on OVF event
IF OE0=1
1
o l e 12-bit duty cycle value (shadow)
b s
O 10.2.3 Functional description
PWM mode
This mode allows a pulse width modulated signals to be generated on the PWM0 output pin
with minimum core processing overhead. The PWM0 output signal can be enabled or
disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is
configured as output push-pull alternate function.
Note: CMPF0 is available in PWM mode (see PWM0CSR register description on page 85).
69/124
PWM frequency and duty cycle

The PWM signal frequency (fPWM) is controlled by the counter period and the ATR register
value.
fPWM = fCOUNTER/(4096 - ATR)
Following the above formula, if fCPU is 8 MHz, the maximum value of fPWM is 4 MHz (ATR
register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution below.
( s )
t
When an upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter,
c
d u
the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0
signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals
r o )
is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register
s
e P
must be greater than the contents of the ATR register.
c t (
The polarity bit can be used to invert the output signal.
l e t d u
The maximum available resolution for the PWM0 duty cycle is:
s o r o
Resolution = 1/(4096 - ATR)
Note: b P
To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum
O e
- t
resolution and assuming that DCR = ATR, a 0% or 100% duty cycle can be obtained by
l e
( s )
changing the polarity.
o
Caution:
t s
As soon as the DCR0H is written, the compare function is disabled and will start only when
c b
the DCR0L value is written. If the DCR0H write occurs just before the compare event, the
d u - O
signal on the PWM output may not be set to a low level. In this case, the DCRx register
should be updated just after an OVF event. If the DCR and ATR values are close, then the
r o s )
DCRx register should be updated just before an OVF event, in order not to miss a compare
P t (
event and to have the right signal applied on the PWM output.
e c
l e t u
Figure 33. PWM function
d
s o r o
O b e P 4095
Duty cycle
l e t register
(DCR0)
Counter
s o Auto-reload
O b register
(ATR)
000
t
With OE0 = 1
PWM0 output
And OP0 = 0
With OE0 = 1
And OP0 = 1
70/124
Figure 34. PWM signal example
fCOUNTER
ATR = FFDh
With OE0 = 1
PWM0 output
And OP0 = 0
Counter FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh
DCR0 = FFEh
Output compare mode

To use this function, the OE bit must be 0, otherwise the compare is done with the shadow
( s )
register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H
and DCR0L registers. This value will be loaded immediately (without waiting for an OVF
event).
c t
d u
The DCR0H must be written first, the output compare function starts only when the DCR0L
value is written.
r o s )
P t (
When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L
e c
registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is
generated if the CMPIE bit is set.
l e t d u
Note:
o o
The output compare function is only available for DCRx values other than 0 (reset value).
s r
Caution:
b P
At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value
O e
has not yet been written (in this case, the shadow register will contain the new DCR0H value
-
and the old DCR0L value), then:
l e t
( s )
- If OE = 1 (PWM mode): the compare is done between the timer counter and the shadow
o
register (and not DCRx)
c t b s
- if OE = 0 (OCMP mode): the compare is done between the timer counter and DCRx. There
u
is no PWM signal.
d - O
r o
DCR0L is written.
s )
The compare between DCRx or the shadow register and the timer counter is locked until
e P c t (
10.2.4
l e t u
Low power modes
d
s o r o
Table 38. Effect of low power modes onthe auto-reload timer
O b e P Mode Description
l e t Slow The input frequency is divided by 32
s o Wait No effect on the auto-reload timer
O b Active halt
Halt
Auto-reload timer halted except if CK0 = 1, CK1 = 0 and OVFIE = 1
Auto-reload timer halted
71/124
10.2.5 Interrupts
Table 39. Auto-reload timer interrupt control/wake-up capability

Enable control Exit from Exit from Exit from
Interrupt event(1) Event flag
bit wait halt active halt
Overflow event OVF OVFIE Yes(2)

Yes No
CMP event CMPFx CMPIE No
1. The interrupt events are connected to separate interrupt vectors (see Chapter 7: Interrupts).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
2. Only if CK0 = 1 and CK1 = 0.

( s )
c t
Timer control status register (ATCSR)
d u
ATCSR
r o s ) Reset value: 0000 0000 (00h)
7 6 5
e P 4
c t ( 3 2 1 0
Reserved
l e t d u CK[1:0] OVF OVFIE CMPIE
-
s o r o R/W R/W R/W R/W
Table 40.
O b e P
ATCSR register description
Bit Name
- l e t Function
( s ) o
7:5
c
-
t b s
Counter clock selection
d u O
These bits are set and cleared by software and cleared by hardware after a reset.
-
4:3
r o CK[1:0]
s )
They select the clock frequency of the counter.
00: Off
e P c t ( 01: fLTIMER (1ms timebase @ 8 MHz)

10: fCPU
l e t d u 11: Reserved
s o r o Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR
O b e P register. It indicates the transition of the counter from FFFh to ATR value.
l e t 2 OVF 0: No counter overflow occurred

1: Counter overflow occurred
s o Caution: When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms
depending on the clock selection) after it has been cleared by software.
O b
72/124
Table 40. ATCSR register description

Bit Name Function
Overflow interrupt enable

This bit is read/write by software and cleared by hardware after a reset.
1 OVFIE
0: OVF interrupt disabled
1: OVF interrupt enabled
Compare interrupt enable
This bit is read/write by software and cleared by hardware after a reset. It is used
0 CMPIE to mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
Counter register high (CNTRH)

( s )
c t
CNTRH
d u Reset value: 0000 0000 (00h)

15 14 13
r o 12
s )
11 10 9 8
Reserved
e P c t ( CNTR11 CNTR10 CNTR9 CNTR8
l e t d u
RO RO RO RO
Counter register low (CNTRL)

s o r o
CNTRL
O b e P Reset value: 0000 0000 (00h)
7 6
- l e t
5 4 3 2 1 0
CNTR7
( s )
CNTR6
o CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0
RO
c t RO
b s RO RO RO RO RO RO
d u - O
r o
Table 41. CNTR high and low counter descriptions
s )
e P
Bits Name
c t ( Function
l e t
15:12
d u
- Reserved, must be kept cleared.
Counter value
s o r o This 12-bit register is read by software and cleared by hardware after a reset.
O b e P The counter is incremented continuously as soon as a counter clock is

selected. To obtain the 12-bit value, software should read the counter value in
l e t11:0 CNTR[11:0] two consecutive read operations. The CNTRH register can be incremented
between the two reads, and in order to be accurate when fTIMER = fCPU, the
s o software should take this into account when CNTRL and CNTRH are read. If
CNTRL is close to its highest value, CNTRH could be incremented before it is
O b read. When a counter overflow occurs, the counter restarts from the value
specified in the ATR register.
73/124
Auto reload register high (ATRH)
ATRH Reset value: 0000 0000 (00h)

15 14 13 12 11 10 9 8
Reserved ATR11 ATR10 ATR9 ATR8
- R/W R/W R/W R/W
Auto reload register low (ATRL)
ATRL Reset value: 0000 0000 (00h)

7 6 5 4
( s )3 2 1 0
ATR7 ATR6 ATR5 ATR4

c t ATR3 ATR2 ATR1 ATR0
R/W R/W R/W R/W

d u R/W R/W R/W R/W
Table 42.
r o
ATR high and low register descriptions
s )
Bits Name
e P c t ( Function
15:12 -
e t u
l d
o
Autoreload register
s r o
11:0 ATR[11:0]
b P
This is a 12-bit register which is written by software. The ATR register value is
automatically loaded into the upcounter when an overflow occurs. The register
O e
- l e t
value is used to set the PWM frequency.
s ) o
PWM0 duty cycle register high (DCR0H)
(
c t b s
DCR0H
15
d u 14
- O 13 12 11 10
Reset value: 0000 0000 (00h)
9 8
r o s )
e P c t ( Reserved DCR11 DCR10 DCR9 DCR8
l e t d u
- R/W R/W R/W R/W
s o r o
O b e P
l e t
s o
O b
74/124
PWM0 duty cycle register low (DCR0L)
DCR0L Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Table 43. DCR0 high and low register descriptions

Bits Name Function
15:12 - Reserved, must be kept cleared

PWMx duty cycle value
( s )
c t
This 12-bit value is written by software. The high register must be written first.
11:0 DCR[11:0] In
d u
PWM mode (OE0 = 1 in the PWMCR register) the DCR[11:0] bits define the
duty cycle of the PWM0 output signal (see Figure 41). In output compare
r o )
mode, (OE0 = 0 in the PWMCR register) they define the value to be compared
s
with the 12-bit upcounter value.
e P c t (
PWM0 control/status register (PWM0CSR)
l e t d u
PWM0CSR
s o r o Reset value: 0000 0000 (00h)
7 6
O b 5
e P 4 3 2 1 0
- l e t Reserved OP0 CMPF0
( s ) o - R/W R/W
Table 44.
c t b s
PWM0CSR register description
Bit
d u
Name
- O Function
7:2
r o -
s ) Reserved, must be kept cleared.
e P c t ( PWM0 output polarity
l e t 1
d uOP0
selects the polarity of the PWM0 signal.
s o r o 0: The PWM0 signal is not inverted.
O b e P 1: The PWM0 signal is inverted.

PWM0 compare flag
l e t 0 CMPF0
This bit is set by hardware and cleared by software by reading the PWM0CSR
register. It indicates that the upcounter value matches the DCR0 register value.
s o 0: Upcounter value does not match DCR value
O b 1: Upcounter value matches DCR value
75/124
PWM output control register (PWMCR)
PWMCR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0
Reserved OE0
- R/W
Table 45. PWMCR register description

Bit Name Function

PWM0 output enable
( s )
0 OE0
c t
1: PWM0 output enabled

d u
0: PWM0 output alternate function disabled (I/O pin free for general purpose I/O)
Table 46. r o
Register map and reset values
s )
Address Register
e P c t (
(hex.) label
7
l e t 6
d u
5 4 3 2 1 0
0D
ATCSR
Reset value
s o
0 0
r o 0
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
CNTRH
O b e P CN11 CN10 CN9 CN8
0E
-
Reset value 0
l e t 0 0 0 0 0 0 0
0F
CNTRL
( s ) o
CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0
c t
Reset value
ATRH b s0 0 0 0 0
ATR11
0
ATR10
0
ATR9
0
ATR8
10
d u Reset value
- O 0 0 0 0 0 0 0 0
r o
11
ATRL
s ) ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
e P c t (
Reset value
PWMCR
0 0 0 0 0 0 0 0
OE0
l e t 12
d u Reset value 0 0 0 0 0 0 0 0
s o r o
13
PWM0CSR
Reset value 0 0 0 0 0 0
OP
0
CMPF0
0
O b e P DCR0H DCR11 DCR10 DCR9 DCR8
l e t 17
Reset value 0 0 0 0 0 0 0 0
s o 18
DCR0L
Reset value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
O b
76/124
10.3 10-bit A/D converter (ADC)
10.3.1 Introduction
The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 5
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 5 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is
controlled through a control/status register.

● 10-bit conversion
( s )
● Up to 5 channels with multiplexed input
c t
● Linear successive approximation
d u
●
o
Data register (DR) which contains the results
r s )
●
●
Conversion complete status flag
On/off bit (to reduce consumption)
e P c t (
l e t
The block diagram is shown in Figure 43.
d u
s o r o
10.3.3 Functional description
O b e P
Analog power supply
- l e t
s ) o
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
(
t s
device pin out description) they are internally connected to the VDD and VSS pins.
c b
d u - O
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
77/124
Figure 35. ADC block diagram
DIV 4
fCPU 1 fADC
DIV 2
0
0
1
SLOW
bit
EOC SPEED ADON 0 0 CH2 CH1 CH0 ADCCSR
AIN0
( s )
t
Hold control
AIN1 RADC
u c Analog to digital
Analog
mux
o d )
converter
AINx
P r ( s CADC
t e c t
l e d u
s o ADCDRH
r o D9 D8 D7 D6 D5 D4 D3 D2
O b e P ADCDRL 0 0 0 0 SLOW 0 D1 D0
- l e t
s )
Digital A/D conversion result
( o
c t b s
The conversion is monotonic, meaning that the result never decreases if the analog input
u O
does not and never increases if the analog input does not.
d -
o )
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
r s
e P
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
c t (
overflow indication).
l e t u
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
d
s o conversion result in the ADCDRH and ADCDRL registers is 00 00h.
r o
O b P
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Chapter 12:
e
l e tElectrical characteristics.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
s o is too high, this will result in a loss of accuracy due to leakage and sampling not being
O b completed in the allocated time.
78/124
A/D conversion phases

The A/D conversion is based on two conversion phases:
● Sample capacitor loading [duration: tSAMPLE]
During this phase, the VAIN input voltage to be measured is loaded into the CADC
sample capacitor.
● A/D conversion [duration: tHOLD]
During this phase, the A/D conversion is computed (8 successive approximations
cycles) and the CADC sample capacitor is disconnected from the analog input pin to get
the optimum analog to digital conversion accuracy.
The total conversion time: tCONV = tSAMPLE + tHOLD
While the ADC is on, these two phases are continuously repeated.
( s )
At the end of each conversion, the sample capacitor is kept loaded with the previous
c t
measurement load. The advantage of this behavior is that it minimizes the current
u
consumption on the analog pin in case of single input channel measurement.
d
A/D conversion
r o s )
P t (
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O
e c
read as a logic input.
l e t
ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be
d u
In the ADCCSR register:
s o r o
b P
Select the CH[2:0] bits to assign the analog channel to convert.
O e
ADC conversion mode
- l e t
s )
In the ADCCSR register:
( o
c t b s
Set the ADON bit to enable the A/D converter and to start the conversion. From this
u O
time on, the ADC performs a continuous conversion of the selected channel.
d -
–r o
When a conversion is complete:
s )
The EOC bit is set by hardware.
e P–
c t (
The result is in the ADCDR registers.
l e t u
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
d
s o r o
To read the 10 bits, perform the following steps:
O b 1.
e PPoll EOC bit
l e t
2.
3.
Read ADCDRL
Read ADCDRH. This clears EOC automatically.
s o To read only 8 bits, perform the following steps:
O b 1.
2.
Poll EOC bit
Read ADCDRH. This clears EOC automatically.
Changing the conversion channel

The application can change channels during conversion. When software modifies the
CH[2:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
79/124
10.3.4 Low power modes

Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 47. Effect of low power modes on ADC

Mode Description
Wait No effect on A/D converter

A/D converter disabled
Halt After wake-up from halt mode, the A/D converter requires a stabilization time tSTAB (see
Electrical characteristics) before accurate conversions can be performed.
10.3.5 Interrupts
( s )
None.
c t
d u
r o s )
Control/status register (ADCCSR)
e P c t (
ADCCSR
l e t d u Reset value: 0000 0000 (00h)
7 6
s o 5
r o 4 3 2 1 0
EOC
O
SPEED b ADON
e P Reserved CH[2:0]
- l e t
RO
( s ) R/W
o
R/W - R/W
Table 48.
c t b s
ADCCSR register description
Bit
d uName
- O Function
r o s )End of conversion
e
7P t
EOC
c ( This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
l e t d u 0: Conversion is not complete

1: Conversion complete
s o r o ADC clock selection
O b e
6
P SPEED This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description.
l e t A/D converter on
s o 5 ADON This bit is set and cleared by software.

0: A/D converter is switched off
O b 4:3 -
1: A/D converter is switched on
Reserved, must be kept cleared
80/124
Table 48. ADCCSR register description (continued)

Bit Name Function
Channel selection
These bits are set and cleared by software. They select the analog input to convert
as follows:
000: Channel pin = AIN0
2:0 CH[2:0]
Note: A write to the ADCCSR register (with ADON set) aborts the current
conversion, resets the EOC bit and starts a new conversion.
Data register high (ADCDRH)

( s )
c t
ADCDRH
d u Reset value: 0000 0000 (00h)

7 6 5
r o 4
s ) 3 2 1 0
e P t (
D[9:2]
c
l e t d u RO
Table 49.
o r
ADCDRH register description
s o
Bit Name
O b e P Function
- t
7:0 D[9:2] MSB of analog converted value
l e
s )
Data register low (ADCDRL)
( o
c t b s
ADCDRL
d u - O Reset value: 0000 0000 (00h)
r
7
o s
6
)
5 4 3 2 1 0
e P c t ( Reserved SLOW Reserved D[1:0]
l e t d u
- R/W - R/W
s o r o
Table 50. ADCDRL register description
O b Bit
e P Name Function
l e t7:4 - Reserved, forced by hardware to 0

Slow mode
s o 3 SLOW This bit is set and cleared by software. It is used together with the SPEED bit in the
O b 2 -
ADCCSR register to configure the ADC clock speed as shown in Table 52.
Reserved, forced by hardware to 0
1:0 D[1:0] LSB of analog converted value
81/124
Table 51. ADC clock speed configuration

fADC ADCDRL SLOW bit ADCCSR SPEED bit
fCPU/2 0 0
fCPU 0 1
fCPU/4 1 x
Table 52. ADC register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) label
ADCCSR EOC SPEED ADON CH2 CH1 CH0

0034h
Reset value 0 0 0 0
(
0
s ) 0 0 0
0035h
ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
c
0 t D5
0
D4
0
D3
0
D2
0
ADCDRL
d u SLOW D1 D0
0036h
Reset value 0 0 0
r o 0 0
s ) 0 0 0
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
82/124
ST7LUS5, ST7LU05, ST7LU09 Instruction set
11 Instruction set
11.1 ST7 addressing modes

The ST7 core features 17 different addressing modes which can be classified in seven main
groups.
Table 53. Addressing mode groups

Group Example
Inherent nop
Immediate ld A,#$55
( s )
Direct ld A,$55
c t
Indexed
u
ld A,($55,X)
d
Indirect
r o
ld A,([$55],X)
s )
Relative
Bit operation
e P jrne loop
bset
c t (
byte,#5
l e t d u
The ST7 instruction set is designed to minimize the number of bytes required per
o r o
instruction: To do so, most of the addressing modes may be divided in two submodes called
s
long and short:
●
O b e P
Long addressing mode is more powerful because it can use the full 64 Kbyte address
- e t
space, however it uses more bytes and more CPU cycles.
l
●
) o
Short addressing mode is less powerful because it can generally only access page
( s
c t b s
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
u O
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
d -
r o )
The ST7 assembler optimizes the use of long and short addressing modes.
s
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
83/124
Instruction set ST7LUS5, ST7LU05, ST7LU09
Table 54. ST7 addressing mode overview
Mode Syntax Destination/Source Pointer Pointer Length (bytes)

address size
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF
( s ) +2
Short Indirect ld A,[$10]
c
00..FF
t 00..FF byte +2
Long Indirect ld A,[$10.w]
u
0000..FFFF
d
00..FF word +2
Short Indirect Indexed ld A,([$10],X)
r o00..1FE
s ) 00..FF byte +2
Long Indirect Indexed
P
ld A,([$10.w],X) 0000..FFFF
e c t ( 00..FF word +2
Relative
Relative
Direct
Indirect
jrne loop
l e
jrne [$10]
t d u
PC-128/PC+127
PC-128/PC+127(1)
(1)
00..FF byte
+1
+2
Bit Direct
s o
bset $10,#7
r o00..FF +1
Bit Indirect
O b
bset [$10],#7
e P 00..FF 00..FF byte +2
Bit Direct Relative
- e t
btjt $10,#7,skip
l
00..FF +2
Bit
( s
Indirect Relative) o
btjt [$10],#7,skip 00..FF 00..FF byte +3
c t b s
1. At the time the instruction is executed, the program counter (PC) points to the instruction following JRxx.
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
84/124
11.1.1 Inherent
All inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 55. Inherent instructions

Instruction Function
NOP No operation
TRAP S/W Interrupt
WFI Wait for interrupt (low power mode)
HALT Halt oscillator (lowest power mode)
RET Subroutine return
( s )
IRET
c t
Interrupt subroutine return
SIM
d u
Set interrupt mask
RIM
r o
Reset interrupt mask
s )
SCF
P
Set carry flag
e c t (
RCF
l t u
Reset carry flag
e d
RSP
s o o
Reset stack pointer
r
LD
CLR
O b
Load
Clear
e P
PUSH/POP
- l e t
Push/Pop to/from the stack
( s ) o
INC/DEC
TNZ
c t b s Increment/decrement
Test negative or zero
CPL, NEG
d u - O 1 or 2 complement
MUL
r o s ) Byte multiplication
P t (
SLL, SRL, SRA, RLC, RRC
e c
Shift and rotate operations
l e t
SWAP
d u Swap nibbles
s o r o
O b e P
l e t
s o
O b
85/124
11.1.2 Immediate
Immediate instructions have 2 bytes: The first byte contains the opcode. The second byte
contains the operand value.
Table 56. Immediate instructions

Instruction Function
LD Load
CP Compare
BCP Bit compare
AND, OR, XOR Logical operations
ADC, ADD, SUB, SBC
( s )
Arithmetic operations
c t
11.1.3 Direct
d u
r o )
In direct instructions, the operands are referenced by their memory address.
s
P
The direct addressing mode consists of two submodes:
e c t (
Direct (short)
l e t d u
o r o
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
s
addressing space.
O b e P
Direct (long)
- l e t
s ) o
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
(
the opcode.
c t b s
11.1.4
d u O
Direct indexed (no offset, short, long)
-
r o s )
In this mode, the operand is referenced by its memory address, which is defined by the
P t (
unsigned addition of an index register (X or Y) with an offset.
e c
l e t d u
The direct indexed addressing mode consists of three submodes:
s o o
Direct indexed (no offset)
r
O b P
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
e
l e t Direct indexed (short)
s o The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
O b addressing space.
Direct indexed (long)

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
86/124
11.1.5 Indirect (short, long)

The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (long)
s )
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
(
c t
11.1.6 Indirect indexed (short, long)
d u
r o s )
This is a combination of indirect and short indexed addressing modes. The operand is
P t (
referenced by its memory address, which is defined by the unsigned addition of an index
e c
the opcode.
l e t
register value (X or Y) with a pointer value located in memory. The pointer address follows
d u
s o r o
The indirect indexed addressing mode consists of two submodes:
Indirect indexed (short)

O b e P
- l e t
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
s ) o
(
c t
Indirect indexed (long)
b s
d u - O
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
r o )
s
e P
Table 57.
c t (
Instructions supporting direct, indexed, indirect and indirect indexed
l e t d uaddressing modes
s o Type
r o Instruction Function
O b e P LD Load
l e t
Long and short instructions
CP
AND, OR, XOR
Compare
Logical operations
s o ADC, ADD, SUB, SBC Arithmetic addition/subtraction operations
O b BCP Bit compare
87/124
Table 57. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes (continued)
Type Instruction Function
CLR Clear
INC, DEC Increment/decrement
TNZ Test negative or zero
CPL, NEG 1 or 2 complement
BSET, BRES Bit operations
Short instructions only
BTJT, BTJF Bit test and jump operations
SLL, SRL, SRA, RLC,
RRC
( s )
Shift and rotate operations
SWAP
c t Swap nibbles
CALL, JP
d u Call or jump subroutine
r o s )
11.1.7 Relative mode (direct, indirect)
e P c t (
offset to it.
l e t d u
This addressing mode is used to modify the PC register value by adding an 8-bit signed
s o r o
Table 58.
O
Instruction
e P
Available relative direct/indirect instructions
b Function
- l e t
JRxx
( s ) o
Conditional jump
CALLR
c t b s Call relative
u O
The relative addressing mode consists of two submodes:
d -
o
Relative (direct)
r s )
P t (
The offset follows the opcode.
e c
l e t u
Relative (indirect)
d
s o r o
The offset is defined in memory, of which the address follows the opcode.
b P
O11.2 Instruction
e
l e t groups
s o The ST7 family devices use an instruction set consisting of 63 instructions. The instructions
O b may be subdivided into 13 main groups as illustrated in the following Table 60.
Table 59. Instruction groups

Group Instructions
Load and transfer LD CLR

Stack operation PUSH POP RSP
Increment/decrement INC DEC
88/124
Table 59. Instruction groups (continued)

Group Instructions
Compare and tests CP TNZ BCP

Logical operations AND OR XOR CPL NEG
Bit operation BSET BRES
Conditional bit test and branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional jump or call JRA JRT JRF JP CALL CALLR NOP RET
Conditional branch JRxx
( s )
Interruption management TRAP WFI
c t
HALT IRET
Condition code flag modification SIM RIM
d u SCF RCF
Using a prebyte
r o s )
P
The instructions are described with 1 to 4 bytes.
e c t (
e t u
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
l d
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
s o r o
b
The whole instruction becomes:
O e P
PC-2
- t
End of previous instruction
l e
PC-1
( s )
Prebyte
o
PC
PC+1
c t
Opcode
b s
Additional word (0 to 2) according to the number of bytes required to compute
d u O
the effective address
-
r o )
These prebytes enable instruction in Y as well as indirect addressing modes to be
s
e P c t (
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
l e t u
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
d
s o r o addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing
O b e P mode to an instruction using the corresponding indirect addressing mode.
l e t It also changes an instruction using X indexed addressing mode to an

instruction using indirect X indexed addressing mode.
s o PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
O b
11.2.1 Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
89/124
Table 60. Instruction set overview

Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with carry A=A+M+C A M H N Z C

ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, memory tst (A . M) A M N Z
BRES Bit reset bres byte, #3 M
BSET Bit set bset byte, #3 M
BTJF Jump if bit is false (0) btjf byte, #3, Jmp1 M C
(s)
BTJT Jump if bit is true (1) btjt byte, #3, Jmp1 M C
CALL Call subroutine
c t
CALLR Call subroutine relative
u
od
CLR Clear reg, M 0 1
CP Arithmetic compare tst(Reg - M) reg
Pr
M N
s)
Z C
t(
e uc
CPL One complement A = FFH-A reg, M N Z 1
DEC Decrement
l e t dec Y
d
reg, M N Z
HALT Halt
s o r o 0
IRET
O b
Interrupt routine return
e P
Pop CC, A, X, PC H I N Z C
INC Increment
- l e t inc X reg, M N Z
JP
( s )
Absolute jump
o
jp [TBL.w]
JRA
JRT
c t
Jump relative b s
Jump relative always
JRF
d u
Never jump
- O jrf *
r
JRIH o s )
Jump if ext. interrupt = 1
e P
JRIL
t (
Jump if ext. interrupt = 0
c
l e t JRH
d u
Jump if H = 1 H=1?
s o JRNH
r o Jump if H = 0 H=0?
O b e P
JRM
JRNM
Jump if I = 1
Jump if I = 0
I=1?
I=0?
l e t JRMI Jump if N = 1 (minus) N=1?
s o JRPL Jump if N = 0 (plus) N=0?
O b JREQ
JRNE
Jump if Z = 1 (equal) Z=1?
Jump if Z = 0 (not equal) Z = 0 ?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >
90/124
Table 60. Instruction set overview (continued)

Mnemo Description Function/Example Dst Src H I N Z C
JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No operation
OR OR operation A=A+M A M N Z
POP Pop from the stack pop reg reg M
(s)
pop CC CC M H I N Z C
PUSH Push onto the stack push Y M

reg,
CC
c t
u
od
RCF Reset carry flag C=0 0
RET Subroutine return
Pr s)
RIM Enable interrupts I=0 0
t(
RLC Rotate left true C C <= Dst <= C
t e
reg, M
e uc N Z C
l od
RRC Rotate right true C C => Dst => C reg, M N Z C
RSP Reset stack pointer S = Max allowed
s o r
SBC Subtract with carry A=A-M-C
O b A
e P M N Z C
SCF Set carry flag
-
C=1
le t 1
)
t(s so
SIM Disable Interrupts I=1 1
SLA
SLL
u c
Shift left arithmetic
Shift left logic
Ob
C <= Dst <= 0
C <= Dst <= 0
reg, M
reg, M
N
N
Z
Z
C
C
d -
ro )
SRL Shift right logic 0 => Dst => C reg, M 0 Z C
SRA
P Shift right arithmetic
( s Dst7 => Dst => C reg, M N Z C
e ct
let
SUB Subtraction A=A-M A M N Z C
SWAP
d u
SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z
s o TNZ
r o
Test for neg & zero tnz lbl1 N Z
Ob TRAP
e PS/W trap S/W interrupt 1
l et
WFI Wait for interrupt 0
s o XOR Exclusive OR A = A XOR M A M N Z
O b
91/124
Electrical characteristics ST7LUS5, ST7LU05, ST7LU09
12 Electrical characteristics
12.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.
12.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
( s )
Data based on characterization results, design simulation and/or technology characteristics
c t
are indicated in the table footnotes and are not tested in production. Based on
d u
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3Σ).
r o s )
12.1.2 Typical values
e P c t (
l e t d u
Unless otherwise specified, typical data is based on TA = 25°C, VDD = 5V (for the
4.5V < VDD < 5.5V voltage range) and VDD = 3.3V (for the 3V < VDD < 3.6V voltage range).
o r o
They are given only as design guidelines and are not tested.
s
12.1.3 Typical curves
O b e P
- l e t
not tested.
( s )
Unless otherwise specified, all typical curves are given only as design guidelines and are
o
c t b s
12.1.4
u
Loading capacitor
d - O
o )
The loading conditions used for pin parameter measurement are shown in Figure 44.
r s
P t (
Figure 36. Pin loading conditions
e c
l e t d u
s o r o ST7 pin
O b e P
l e t CL
s o
O b
92/124
ST7LUS5, ST7LU05, ST7LU09 Electrical characteristics
12.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 45.
Figure 37. Pin input voltage
ST7 pin
VIN
( s )
c t
12.2 Absolute maximum ratings
d u
r o s )
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
P t (
to the device. This is a stress rating only and functional operation of the device under these
e c
affect device reliability.
l e t
conditions is not implied. Exposure to maximum rating conditions for extended periods may
d u
Table 61.
s o
Voltage characteristics
r o
Symbol
O b e P
Ratings Maximum value Unit
VDD - VSS
-
Supply voltage
l e t 7.0
( s ) o (1)(2)
V
VIN
c t b s
Input voltage on any pin
Electrostatic discharge voltage
VSS-0.3 to VDD+0.3
VESD(HBM)
d u - O
(Human body model)
see Section 12.7.2 on page 114
r o
VESD(MM)
s )
Electrostatic discharge voltage
(Machine model)
see Section 12.7.2 on page 114
e P c t (
1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O
l e t u
configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this
connection has to be done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins
d
must be tied in the same way to VDD or VSS according to their reset configuration.
s o r o
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
O b e P
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
l e t
s o
O b
93/124
Table 62. Current characteristics

Symbol Ratings Maximum value Unit
IVDD Total current into VDD power lines (source)(1) 75

(1)
IVSS Total current out of VSS ground lines (sink) 150
Output current sunk by any standard I/O and control pin 20
IIO Output current sunk by any high sink I/O pin 40
mA
Output current source by any I/Os and control pin -25
Injected current on RESET pin ±5
IINJ(PIN)(2)(3)
Injected current on any other pin(4) ±5
ΣIINJ(PIN)(2)
( s )
Total injected current (sum of all I/O and control pins)(4) ±20
c t
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
d u
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
r o
injection is induced by VIN>VDD while a negative injection is induced by VIN < VSS.
s )
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
P t (
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
e c
e t
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
u
analog voltage is lower than the specified limits)
l d
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject
s o r o
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
O b e P
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 63. - l e t
Thermal characteristics
( s ) o
Symbol
c
TSTGt b s Ratings
Storage temperature range

Value
-65 to +150
Unit
°C
d uTJ
- OMaximum junction temperature (see Chapter 13: Package characteristics)
r o s )
12.3
e P
Operating
c t (
conditions
l e t d u
s o r o
Table 64. General operating conditions
O b e P
Symbol Parameter Conditions Min Max Unit
l e t VDD Supply voltage

fOSC = 16 MHz max,
TA = -40°C to TA max
3.0 5.5 V
s o fCLKIN
External clock frequency on
VDD > 3V 0 16 MHz
O b TA
CLKIN pin
Ambient temperature range

A Suffix version
-40
+85
°C
C Suffix version +125
94/124
Figure 38. fCLKIN maximum operating frequency versus VDD supply voltage
Functionality
guaranteed
fCLKIN [MHz] in this area
(unless otherwise
stated in the
tables of
16 parametric data)
Functionality
not guaranteed
in this area
0 Supply voltage [V]

2.0 2.7 3.0 3.3 3.5
( s )4.0 4.5 5.0 5.5
Table 65.
c t
Operating conditions with low voltage detector (LVD)(1)
Symbol Parameter
d u Conditions Min Typ Max Unit
VIT+(LVD)
r o
Reset release threshold (VDD rise)
s ) 3.50(2) 4.00 4.50
VIT-(LVD) P
Reset generation threshold (VDD fall)
e c t ( High threshold
3.30 3.80 4.40(2)
V
Vhys
l e t
LVD voltage threshold hysteresis
d u VIT+(LVD)-VIT-(LVD) 150 mV
VtPOR VDD rise time
s o rate(3)(4)
r o 20 - µs/V
O b
IDD(LVD)(2) LVD current consumption
e P VDD = 5V 220 µA
- l e t
1. TA = -40 to 125°C unless otherwise specified.
( s )
2. Not tested in production
o
3. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
c t
reset of the MCU.
b s
and LVD reset release. When the VDD slope is outside these values, the LVD may not release properly the
d u - O
4. Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur in the
application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit
o )
example in Figure 67 on page 124.
r s
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
95/124
12.3.1 Internal RC oscillator

The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).
Note: To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
Table 66. Internal RC oscillator calibrated at 5.0V

Symbol Parameter Conditions Min Typ Max Unit
Internal RC oscillator RCCR = FF (reset value), TA = 25°C, VDD = 5V 4.5

fRC MHz
frequency (1)
RCCR = RCCR0 , TA = 25°C, VDD = 5V 8
RC resolution VDD = 5V(2)
( s ) -2 +2
ACCRC Accuracy of internal RC

c t
TA = -40°C to +125°C, VDD = 5V -7 +7 %
oscillator with
RCCR = RCCR0(1)
d u
TA = -40°C to +125°C, VDD = 4.5 to 5.5V(2) -8 +9
IDD(RC)
RC oscillator current
r o
TA = 25°C, VDD = 5V
s ) 900(3) µA
consumption
e P c t ( 4(3)
tsu(RC) RC oscillator setup time
l e t
TA = 25°C, VDD = 5V
1. See Internal RC oscillator adjustment on page 31
d u
µs
s o r o
2. Data based on characterization results; not tested in production
3. Guaranteed by Design
O b e P
Table 67.
- t
Internal RC oscillator calibrated at 3.3V
l e
Symbol Parameter
( s ) o Conditions Min Typ Max Unit
fRC
c t
Internal RC oscillator
b sRCCR = FF (reset value), TA = 25°C, VDD = 3.3V 4.4
MHz
frequency
d u - O RCCR = RCCR1 (1),

TA = 25°C, VDD = 3.3V 8
r o
RC resolution
s ) VDD = 3.3V(2) -2 +2
e P
oscillator with
c t (
ACCRC Accuracy of internal RC TA = -40°C to +125°C, VDD = 3.3V -7 +7 %
l t
RCCR = RCCR1(1)
e d u TA = -40°C to +125°C, VDD = 3.0 to 3.6V(2) -8 +9
o
IDD(RC)
s o
RC oscillator current
r
consumption
TA = 25°C, VDD = 3.3V 900(3) µA
O btsu(RC) P
RC oscillator setup time
e
TA = 25°C, VDD = 3.3V 4(3) µs
e t
1. See Internal RC oscillator adjustment on page 31
l
s o
2. Data based on characterization results; not tested in production
3. Guaranteed by design
O b
96/124
Figure 39. Internal RC oscillator frequency vs. temperature (RCCR = RCCR0) at

VDD = 5.0V
8.25
fRC (MHz) 8
4.5V
5.0V
7.75
( s ) 5.5V
-60 - 40 -20 0
c t20 40
T A (°C)
60 80 100 120 140
d u
r o )
Figure 40. Internal RC oscillator frequency vs. temperature (RCCR = RCCR1) at
s
VDD = 3.3V
e P c t (
8.25
l e t d u
s o r o
O
8
b e P
t
fRC (MHz)
) - l e
t ( s 7.75
s o
u c O b 3.0V
d
3.3V
r o ) - 3.6V
s
7.5
e P c t ( -60 - 40 -20 0 20 40
T A (°C)
60 80 100 120 140
l e t d u
s o r o
O b e P
l e t
s o
O b
97/124
12.4 Supply current characteristics

The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for halt mode
for which the clock is stopped).
Table 68. Supply current consumption

Symbol Parameter Conditions(1) Typ Max Unit
Supply current in run mode(2) fCPU = 8 MHz 5.0 9.0

mA
(3)
Supply current in wait mode fCPU = 8 MHz 1.5 4.0
Supply current in slow mode(4)
( s ) fCPU/32 = 250 kHz 650 1100

IDD Supply current in slow wait
c t
mode(5) fCPU/32 = 250 kHz 500 900
Supply current in AWUFH mode(6)(7)
d u 40 120(8) µA
r
Supply current in halt mode(9)o
Supply current in active halt mode
s )
100 250
e P
1. TA = -40 to +125 °C unless otherwise specified
c t ( 0.5 3
l e t d u
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all
peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
s o r o
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock
O b e P
input (CLKIN) driven by external square wave, LVD disabled.
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
LVD disabled.
l e t
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave,
-
s ) o
5. Slow wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static
(
wave, LVD disabled.
c b s
value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square
t
d u
and fCPU max.
- O
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max.
r o )
7. This consumption refers to the halt period only and not the associated run period which is software
dependent.
s
P t (
8. Data based on characterization, not tested in production
e c
l e t u
9. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on
characterization results, tested in production at VDD max and fCPU max.
d
s o r o
O b e P
l e t
s o
O b
98/124
Figure 41. Typical IDD in run mode vs. fCPU

6.00
5.00
2MHz
4MHZ
4.00 8MHz
Idd [mA]
3.00
2.00
1.00
( s )
t
0.00
2.4 2.6 2.8 3
u c
3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
Vdd [V]
o d )
Figure 42. Typical IDD in slow mode vs. fCPU
P r ( s
0.80
t e c t
0.70
l e 2MHz
d u
0.60
s o r
4MHZ
o
b
0.50
O e P
8MHz
Idd [mA]
-
0.40
l e t
( s ) 0.30
o
c t b
0.20
s
d u - O
0.10
r o s ) 0.00
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
e P c t ( Vdd [V]
l e t d u
Figure 43. Typical IDD in wait mode vs. fCPU
s o r o 1.80
O b e P 1.60
t
2MHz
1.40
e
4MHZ
o l 1.20 8MHz
s
Idd [mA]
b
1.00
O 0.80
0.60
0.40
0.20
0.00
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
Vdd [V]
99/124
Figure 44. Typical IDD in slow wait mode vs. fCPU
0.70
0.60
2MHz
0.50 4MHZ
8MHz
0.40
Idd [mA]
0.30
0.20
0.10
( s )
0.00
c t
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
d u Vdd [V]
r o s )
Figure 45. Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz
e P 5.00
c t (
l e t 4.50
d u
s o r o
4.00
RUN
O b e P 3.50 WAIT
SLOW
t
3.00
-
Idd [mA]
SLOWWAIT
) o l e 2.50
t ( s s
2.00
u c O b 1.50
d
1.00
r o ) - 0.50
P t ( s 0.00
e c
-45 25 90
l e t d u Vdd [V]
s o r o
Table 69. On-chip peripherals
O b e P
Symbol Parameter Conditions Typ(1) Unit
l e t IDD(AT) 12-bit auto-reload timer supply current(2) fCPU = 8 MHz VDD = 5.0V 30
µA
s o IDD(ADC) ADC supply current when converting(3) fADC = 4 MHz VDD = 5.0V 750
O b 1. Not tested in production, guaranteed by characterization

2. Data based on a differential IDD measurement between reset configuration (timer stopped) and the timer
running in PWM mode at fCPU = 8 MHz
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions with amplifier off
100/124
12.5 Clock and timing characteristics

Subject to general operating conditions for VDD, fOSC, and TA.
Table 70. General timings

Symbol Parameter(1) Conditions Min Typ(2) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time
250 375 1500 ns
fCPU = 8 MHz
Interrupt reaction time(3) 10 22 tCPU
tv(IT)
tv(IT) = ∆tc(INST) + 10 1.25 2.75 µs
1. Data based on characterization, not tested in production
( s )
t
2. Data based on typical application software
u c
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
Table 71. Auto wake-up RC oscillator

o d )
Symbol Parameter
P r ( s
Conditions Min Typ Max Unit
VDD(RCAWU) Supply voltage range

t e c t 3.0 5.0 5.5 V
TA(RCAWU)
l e
Operating temperature range
d u -40 25 125 °C
s o r o Without prescaler 2.0 8.0 14.0

IDD(RCAWU)
O b
Current consumption(1)
e P AWU RC switched off 0

µA
-
fOSC(RCAWU) Output frequency(1)
l e t 20 33 60 kHz
s )
1. Data guaranteed by Design
( o
c t b s
12.6
d u
Memory characteristics
- O
r o s )
RAM and hardware registers(1)
e P
Table 72.
c t (
l e t Symbol
VRM
d u
Parameter
Data retention mode(2)

Conditions
Halt mode (or reset)

Min
1.6
Typ Max Unit
s o r o
1. TA = -40°C to 125°C, unless otherwise specified.
O b e P
2. Minimum VDD supply voltage without losing data stored in RAM (in halt mode or under reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
l e t
Table 73. Flash program memory
s o Symbol Parameter Conditions(1) Min Typ Max Unit
O b VDD
Operating voltage for Flash
write/erase
3.0 5.5 V
Programming time for 1~32

TA = -40 to +125°C 5 10 ms
tprog bytes(2)
Programming time for 1 Kbyte TA = +25°C 0.16 0.32 s
tRET Data retention(3) TA = +55°C(4) 20 years
(5)
NRW Write/erase cycles TA = +25°C 10k cycles
101/124
Table 73. Flash program memory (continued)

Symbol Parameter Conditions(1) Min Typ Max Unit
Read/write/erase modes
2.6 mA
fCPU = 8 MHz, VDD = 5.5V
(6)
IDD Supply current
No read/no write mode 100
µA
Power down mode/halt 0 0.1
2. Up to 32 bytes can be programmed at a time.
3. Data based on reliability test results and monitored in production.
4. The data retention time increases when the TA decreases.
( s )
5. Design target value pending full product characterization.
6. Guaranteed by design. Not tested in production.
c t
Table 74. EEPROM memory (ST7FLU09 only)
d u
Symbol Parameter
r o Conditions(1)
s )
Min Typ Max Unit
VDD
e P
Operating voltage for EEPROM
c t (
Refer to operating range of
VDD with TA, Section 12.3 3.0 5.5 V
write/erase
l e t u
on page 104
d
tprog
bytes
s o
Programming time for 1~32
r o 5 10 ms
tRET(2)
O b
Data retention(3)
e P TA = +55°C 20 years
NRW
-
Write/erase cycles
l e t TA = +25°C 300k cycles
s ) o
(
t s
2. Data based on reliability test results and monitored in production.
c b
u O
3. The data retention time increases when the TA decreases.
d -
12.7 r o
EMC (electromagnetic
s ) compatibilty) characteristics
e P c t (
l e t Susceptibility tests are performed on a sample basis during product characterization.
d u
s o
12.7.1
o
Functional EMS (electromagnetic susceptibility)
r
O b P
Based on a simple running application on the product (toggling two LEDs through I/O ports),
e
l e t the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
s o ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
O b ●
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100pF capacitor until a functional disturbance occurs. This test conforms with
the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results given in Table 77
are based on the EMS levels and classes defined in application note AN1709.
102/124
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore, it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical data corruption (control registers...)
( s )
Prequalification trials
c t
d u
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
r o s )
P t (
To complete these trials, ESD stress can be applied directly on the device, over the range of
e c
l e t d u
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
s o r o
Table 75. EMS test results
O b e P Level/
Symbol
-
Parameter
l e t Conditions
class
( s ) o VDD = 5V, TA = +25°C, fOSC = 8 MHz,

VFESD
c t b s
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
SO8 package,
conforms to IEC 1000-4-2
3B
d u - O
Fast transient voltage burst limits to be VDD = 5V, TA = +25°C, fOSC = 8 MHz,
r o
VFFTB
)
applied through 100pF on VDD and VDD
s
SO8 package, 4A
e P c t (
pins to induce a functional disturbance conforms to IEC 1000-4-4
l e t d u
s o r o
O b e P
l e t
s o
O b
103/124
12.7.2 Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 76. EMI emissions(1)

Max vs.
Monitored [fOSC/fCPU]
Symbol Parameter Conditions Unit
frequency band
-/8 MHz
0.1 MHz to 30 MHz 21
SEMI Peak level

VDD = 5V, TA = +25°C,
SO8 package,
( s ) 30 MHz to 130 MHz 23 dBµV
t
conforming to SAE J 1752/3
c
130 MHz to 1 GHz 10
d u SAE EMI Level 3 -
o )
1. Data based on characterization results, not tested in production.
r s
12.7.3 P
Absolute maximum ratings (electrical sensitivity)
e c t (
e t u
Based on three different tests (ESD and LU) using specific measurement methods, the
l d
o o
product is stressed in order to determine its performance in terms of electrical sensitivity.
s r
b
Electrostatic discharge (ESD)
O e P
- t
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
l e
s )
applied to the pins of each sample according to each pin combination. The sample size
o
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
(
t b s
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
c
d u
application note AN1181.
- O
r o
Table 77.
)
Absolute maximum ratings
s
e P
Symbol
c t ( Ratings Conditions Class
Max
value(1)
Unit
l e t d
VESD(HBM)u Electrostatic discharge voltage TA = +25 °C
H2 4000
s o r o (Human body model) conforming to AEC-Q100-002
O b e P
VESD(MM)
Electrostatic discharge voltage TA = +25 °C
(Machine model) conforming to AEC-Q100-003
M3 400 V
l e t VESD(CDM)
Electrostatic discharge voltage TA = +25 °C
C3A 750
s o (Charged device model) conforming to AEC-Q100-011
O b 1. Data based on characterization results, not tested in production.
104/124
Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin.
● A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD78 IC latch-up standard.
Electrical sensitivities
Table 78. Latch-up results

Symbol Parameter Conditions Class
TA = +125°C
( s )
LU Static latch-up class
c t
conforming to JESD78
II level A
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
105/124
12.8 I/O port pin characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 79. General characteristics

VIL Input low level voltage 0.3VDD

-40°C to 125°C V
VIH Input high level voltage 0.7VDD
Schmitt trigger voltage
Vhys 400 mV
hysteresis(1)
Ilkg Input leakage current VSS < VIN < VDD ±1
Static current consumption
( s ) µA
IS induced by each floating
input pin(2)
c t
Floating input mode 400
d u VDD = 5V 70 120 200

RPU
Weak pull-up equivalent
resistor(3)(4)
r o )
VIN = VSS
s VDD = 3.3V 200(1)

kΩ
CIO I/O pin capacitance

e P c t ( 5 pF
tf(IO)out
time(1) l e t
Output high to low level fall
d u 25
s o r o
CL = 50 pF
Output low to high level rise between 10% and 90%
ns
tr(IO)out
time(1)
O b e P 25
tw(IT)in
- l e t
External interrupt pulse
1 tCPU
( s )
time(5)
o
c t b s
1. Data based on characterization results, not tested in production
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
d u - O
the I/O for example or an external pull-up or pull-down resistor (see Figure 58). Static peak current value
taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in
r o s )
production. This value depends on VDD and temperature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current
e P t (
characteristics described in Figure 56).
c
l e t 4. RPU not applicable on PA3 because it is multiplexed on RESET pin
d u
5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as
s o o
an external interrupt source.
r
O b P
Figure 46. Two typical applications with unused I/O pin
e
l e t VDD ST7XXX
10kΩ
Unused I/O port
s o 10kΩ
Unused I/O port
O b ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled up, internally or externally (external pull-up of 10k mandatory
in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
106/124
Figure 47. Typical IPU vs. VDD with VIN = VSS

90
80 -45°C
70 25°C
60 90°C
IPU [uA]
50
40
30
20
10
0
6
4
6
2.
2.
3.
3.
4.
4.
5.
5.
( s ) VDD [V]
Table 80. Output driving current

c t (1)
Symbol
d u Parameter
Conditions
Min Max Unit
r o s )
P
Output low level voltage for PA3/RESET
e
standard I/O pin (see Figure 58)
c t ( IIO = +5mA 1200
VOL(2)
l e t d u
Output low level voltage for a high sink I/O
IIO = +2mA
IIO = +20mA
400
1300
(see Figure 60)

s o o
pin when 4 pins are sunk at same time
r IIO = +8mA 750 mV
O b e P
Output high level voltage for an I/O pin IIO = -5mA VDD - 1500
-
(see Figure 63)
l e t
VOH(3)(4) when 4 pins are sourced at same time
IIO = -2mA VDD - 800
( s ) o
2.
c b s
1. Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
t
The IIO current sunk must always respect the absolute maximum rating specified in Table 63: Current
d u - O
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The IIO current sourced must always respect the absolute maximum rating specified in Table 63: Current
r o s )
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O
pins do not have VOH.
P t (
4. Not tested in production, based on characterization results.
e c
l e t d u
Figure 48. Typical VOL at VDD = 3.3V (standard pins)
s o r o 1000
O b e P -45°C
25°C
t
800
VOL (mV) at VDD=3 V(STD)
90°C
o l e 600
b s
O 400
200
0
0 2 4 6
ILOAD (mA)
107/124
Figure 49. Typical VOL at VDD = 5V (standard pins)
800
-45°C
25°C
90°C
VOL (mV) at VDD=5V(STD)

600
400
200
( s ) 0
c t 0 2
ILOAD (mA)
4 6
d u
o
Figure 50. Typical VOL at VDD = 3.3V (HS pins)
r s )
1200
e P c t (
l
1000
e t d u
s o 800
r o 25°C
P
-45°C
b 90°C
Vol [mV]
- O t
600
e e
s ) o l 400
c t ( b s 200
d u - O 0
r o s ) 0 2 4 6 8 10 12 14 16 18 20
e P c t ( ILOAD[mA]
l e t u
Figure 51. Typical VOL at VDD = 5V (HS pins)
d
s o r o 1000
O b e P 900
800 25°C
l e t 700
-45°C
90°C
o 600
Vol [mV]
b s 500
400
O 300
200
100
0
0 2 4 6 8 10 12 14 16 18 20
ILOAD[mA]
108/124
Figure 52. Typical VDD - VOH at VDD = 3.3V (HS pins)
1000
900 -45°C
25°C
800 90°C
700
VDD-VOH [mV]
600
500
400
300
200
100
( s )
c t0 -2 -4 -6
Iload [mA]
-8 -10 -12
d u
o
Figure 53. Typical VDD - VOH at VDD = 5V (HS pins)
r s )
e P
600
c t (
l e t 500
d u
-45°C
25°C
90°C
s o 400
r o
b P
VDD-VOH [mV]
- O e t e300
s ) o l 200
c t ( b s 100
d u - O
r o s )
0
0 -2 -4 -6 -8 -10 -12
e P c t ( Iload [mA]
l e t d u
Figure 54. Typical VOL vs. VDD (standard I/Os)
s o r o 500
O b e P 450 -45°C
25°C
t
400
90°C
e
350
VOL [mV] at Iload=2mA
o l 300
b s 250
200
O
150
100
50
0
2.4 3 3.4 4 4.4 5 5.4 6
VDD [V}
109/124
Figure 55. Typical VOL vs. VDD (HS pins)
500 900
-45°C -45°C
450 25°C 800 25°C
90°C 90°C
400
700
Vol [mV] at ILOAD = 12mA

Vol [mV] at ILOAD = 8mA
350
600
300
500
250
400
200
300
150
100 200
50 100
)
0 0
s
2.4 3 3.4 4 4.4 5 5.4 6 2.4 3 3.4 4 4.4 5 5.4 6
c t ( Vdd [V] Vdd [V]
Figure 56. Typical VDD - VOH vs. VDD (HS pins)

d u
180
r o s )
P (
600
t
160
e c t 500
u
140
VDD-VOH [mV] at ILOAD=2 mA
VDD-VOH [mV] at ILOAD = 6mA
o l e 120
o d 400
b s
100
P
80 r 300
- O e t e60
40 -45°C
200
-45°C
l
25°C
)
25°C 100
90°C
s o
20 90°C
c t ( b s 0
2.4 3 3.4 4 4.4 5 5.4 6
0
2.4 3 3.4 4 4.4 5 5.4 6
u
VDD [V]
O
VDD [V]
o d ) -
P r ( s
t e c t
l e d u
s o r o
O b e P
l e t
s o
O b
110/124
12.9 Control pin characteristics

TA = -40°C to 125°C, unless otherwise specified.
Table 81. Asynchronous RESET pin

VIL Input low level voltage VSS - 0.3 0.3VDD

VIH Input high level voltage 0.7VDD VDD + 0.3
V
Schmitt trigger voltage
Vhys 2
hysteresis(1)
VOL Output low level voltage(2) VDD = 5V IIO = +2mA 400 mV
( s )VDD = 5V 10 50 70
RON Pull-up equivalent resistor(3)
c t
VIN = VSS
VDD = 3.3V 90(1)
kΩ
tw(RSTL)out
Generated reset pulse
d u
Internal reset sources 90(1)
duration
r o s ) µs
th(RSTL)in
External reset pulse hold
time(4)
e P c t ( 20
tg(RSTL)in Filtered glitch duration

l e t d u 200 ns
o r o
1. Data based on characterization results, not tested in production
s
b P
2. The IIO current sunk must always respect the absolute maximum rating specified in Table 63: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
O e
-
between VILmax and VDD.
l e t
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin
s ) o
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses
(
t s
applied on RESET pin with a duration below th(RSTL)in can be ignored.
c b
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
111/124
Figure 57. RESET pin protection when LVD is enabled(1)(2)(3)(4)

VDD ST7XXX
Required Optional RON

(note 3) Internal
External reset
reset Filter
0.1µF 1MΩ Watchdog

Pulse
generator Illegal opcode(5)
LVD reset
1. - The reset network protects the device against parasitic resets.
)
- The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
s
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
(
- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
into account internally.

c t
can go below the VIL max. level specified in Table 85 on page 123. Otherwise the reset will not be taken
d u
- Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
IINJ(RESET) in Table 63 on page 104.
r o s )
2. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
P t (
down capacitor is required to filter noise on the reset line.
e c
t
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the
l d
add 5µA to the power consumption of the MCU).u
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
e
4. Tips when using the LVD:
s o r o
A. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in
b
Table 2 on page 15 and notes above)
P
B. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709
O e
e t
and AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
-
C. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up
l
s )
marginality. In most cases, steps A and B above are sufficient for a robust solution. Otherwise: replace
o
10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.
(
t b s
Figure 58. RESET pin protection when LVD is disabled(1)
c
d u - O VDD ST7XXX
r o s )
e P c t ( RON
t
User Internal
l e d u
external
reset Filter
reset
s o r o
circuit
0.01µF
Watchdog
O b e P
Required
Pulse
generator
Illegal opcode(2)
l e t
s o 1. The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
O b Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Table 85 on page 123. Otherwise the reset will not be taken
into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
IINJ(RESET) in Table 63 on page 104.
2. Please refer to Illegal opcode reset on page 99 for more details on illegal opcode reset conditions.
112/124
12.10 10-bit ADC characteristics

Table 82. 10-bit ADC characteristics(1)
Symbol Parameter Conditions Min Typ(2) Max Unit
fADC ADC clock frequency 4 MHz

VAIN Conversion voltage range(3) VSSA VDDA V
VDD = 5V, fADC = 4 MHz (4)
8k
RAIN External input resistor Ω
VDD = 3.3V, fADC = 4 MHz 7k(4)
CADC Internal sample and hold capacitor 3 pF
tSTAB Stabilization time after ADC enable 0(5)
( s ) µs
tADC
Conversion time (sample+hold)
Sample capacitor loading time
fCPU = 8 MHz, fADC = 4 MHz
3.5
4
c t
Hold conversion time
d u
10
1/fADC
1. Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
r o s)
guidelines and are not tested.
t e P
2. Unless otherwise specified, typical data are based on TA = 25°C and VDD - VSS = 5V. They are given only as design
c t(
l e
3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
d u
based on characterization results, not tested in production.
s o r o
4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
valid.
O b e P
5. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always
- le t
Figure 59. Typical application with ADC
( s ) o
c t b s
d u - O
VDD
r o s )
e P ct ( VT
0.6V
let du
RAIN AINx
VAIN 10-bit A/D
conversion
s o r o VT
Ilkg CADC
O b e P 0.6V
l et ST7LUxx
s o
O b
113/124
Table 83. ADC accuracy with VDD = 4.5V to 5.5V

(1)
Symbol Parameter Conditions Typ Max Unit
|ET| Total unadjusted error 2.1 5.0

|EO| Offset error 0.2 2.5
(1)
|EG| Gain error fCPU = 8 MHz, fADC = 4 MHz 0.3 1.5 LSB
|ED| Differential linearity error 1.9 3.5
|EL| Integral linearity error 1.9 4.5
1. Data based on characterization results over the whole temperature range
Table 84. ADC accuracy with VDD = 3.0V to 3.6V

Symbol(1) Parameter Conditions Typ Max
( s ) Unit
t
uc
|ET| Total unadjusted error 2.0 3.0
od
|EO| Offset error 0.1 1.5
|EG| Gain error fCPU = 4 MHz, fADC = 2 MHz(1)
Pr
0.4 1.4
s) LSB
|ED| Differential linearity error
t e
1.8
c t(
2.5
|EL| Integral linearity error
l e d u
1.7 2.5
1. Data based on characterization results over the whole temperature range
s o r o
Figure 60. ADC accuracy characteristics
b e P
-O t
Digital result ADCDR EG (1) Example of an actual transfer curve
1023
) le
(2) The ideal transfer curve
s so
(3) End point correlation line
(
1022 V –V
DD SS
1021
1LSB
IDEAL
= --------------------------------
1024
c t b
ET = Total unadjusted error: maximum deviation
between the actual and the ideal transfer curves.
d u ET
(2)
- O EO = Offset error: deviation between the first actual

transition and the first ideal one.
ro )
(3) EG = Gain error: deviation between the last ideal
7
s
transition and the last actual one.
(1)
6
5
e P ct ( ED = Differential linearity error: maximum deviation
between actual steps and the ideal one.
let
EO
du
EL EL = Integral linearity error: maximum deviation
4
between any actual transition and the end point
so o
3 correlation line.
r
ED
2
O b 1
e P 1 LSBIDEAL
l et 1 2 3 4 5 6 7 1021 1022 1023 1024 Vin (LSBIDEAL)
o
VSS VDD
b s
O
114/124
ST7LUS5, ST7LU05, ST7LU09 Package characteristics
13 Package characteristics
13.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.com.
13.2 Package mechanical data

( s )
c t
u
Figure 61. 8-pin plastic small outline package, 150-mil width
d
r o s )
D
e P c t (
l e t d u
h x 45°
E H
s o A2 A
r o
O b A1
e P
α
C
t
B L
) - l e e
t ( s s o
Table 85.
u c O b
8-pin plastic small outline package, 150-mil width, mechanical data
mm inches(1)
Dim.
o d ) -
P r ( s
Min Typ Max Min Typ Max
t e
A
c t 1.350 1.750 0.0531 0.0689
l e
A1
d u 0.100 0.250 0.0039 0.0098
s o r o
A2 1.100 1.650 0.0433 0.0650
O b e P B
C
0.330
0.190
0.510
0.250
0.0130
0.0075
0.0201
0.0098
l e t D 4.800 5.000 0.1890 0.1969
s o E 3.800 4.000 0.1496 0.1575
O b e
H 5.800
1.270
6.200 0.2283
0.0500
0.2441
h 0.250 0.500 0.0098 0.0197
α 0° 8°
L 0.400 1.270 0.0157 0.0500
1. Values in inches are converted from mm and rounded to 4 decimal digits
115/124
Package characteristics ST7LUS5, ST7LU05, ST7LU09
Figure 62. 16-pin plastic dual in-line package, 300-mil width
A2
A1 A
L c
E1
b2 b eB
D1 b3 e
( s )
c t
d u
r o s )
Table 86. P t (
8-pin plastic small outline package, 150-mil width, mechanical data
e c
Dim.
l e t mm
d u inches(1)(2)
Min
s o r
Typ
o Max Min Typ Max
O b e P 5.330 0.2098
A1
-
0.380
l e t 0.0150
A2
( s ) 2.920
o 3.300 4.950 0.1150 0.1299 0.1949
b
c t b
0.360
s 0.460 0.560 0.0142 0.0181 0.0220
b2
d u - O
1.140 1.520 1.780 0.0449 0.0598 0.0701
r o
b3
s ) 0.760 0.990 1.140 0.0299 0.0390 0.0449
e P c
c t ( 0.200 0.250 0.360 0.0079 0.0098 0.0142
l e t D
D1
d u
18.670
0.130
19.180 19.690 0.7350
0.0051
0.7551 0.7752
s o r oe 2.540 0.1000
O b e P E 7.620 7.870 8.260 0.3000 0.3098 0.3252
l e t E1 6.100 6.350 7.110 0.2402 0.2500 0.2799
s o L 2.920 3.300 3.810 0.1150 0.1299 0.1500
O b 1.
eB 10.920
Values in inches are converted from mm and rounded to 4 decimal digits.
0.4299
2. This package is for development purposes only and is not available in production
116/124
ST7LUS5, ST7LU05, ST7LU09 Package characteristics
13.3 Thermal characteristics

Table 87. Thermal characteristics
Symbol Ratings Package Value Unit
RthJA Package thermal resistance (junction to ambient) 130 °C/W

TJmax Maximum junction temperature(1) SO8 150 °C
PDmax (2)
Power dissipation 180 mW
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD = PINT + PPORT where PINT is the
chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the application.
( s )
13.4 Soldering compatibility
c t
d u
ECOPACK® SO packages are fully compatible with lead (Pb) containing soldering process (see
application note AN2034).
r o s )
Table 88.
e P c t (
Soldering compatibility (wave and reflow soldering process)
Package
l e t
Plating material
d u Pb solder paste Pb-free solder paste
SO
s o r o
NiPdAu (nickel-palladium-gold) Yes Yes
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
117/124
Device configuration and ordering information ST7LUS5, ST7LU05, ST7LU09
14 Device configuration and ordering information
This device is available for production in user programmable versions (Flash). ST7FLUxx XFlash devices
are shipped to customers with a default program memory content (FFh).
14.1 Flash devices
14.1.1 Flash configuration
Table 89. Flash option bytes

Option byte 0
( s ) Option byte 1
7 6 5 4 3 2 1
c0t 7 6 5 4 3 2 1 0
d u
FMP FMP WDG WDG
Reserved SEC0[1:0]
r o
_R _W
s )
CKSEL[1:0] Reserved LVD[1:0]
SW HALT
Default
1 1 1 1 0 0
e P 0
c0
t ( 0 0 1 0 1 1 1 1
value
l e t d u
The two option bytes are used to select the hardware configuration of the microcontroller.
s o r o
The option bytes can be accessed only in programming mode (for example, using a standard ST7
programming tool).
O b e P
Option byte 0
- l e t
( s ) o
Table 90.
t s
Option byte 0 bit description
c b
Bit Name
d u - O Function
OPT7:4
r o -
s
Reserved, must always be 1
)
e P c t ( Sector 0 size definition
These option bits indicate the size of sector 0 as follows:
OPT3:2
l e t d u
SEC0[1:0] 00: 0.5 Kbyte
01: 1 Kbyte
s o r o 1- : 2 Kbytes
O b e P Readout protection
Readout protection, when selected provides a protection against program memory
l e t content extraction and against write access to Flash memory. Erasing the option bytes
when the FMP_R option is selected will cause the whole memory to be erased first,
s o
OPT1 FMP_R
and the device can be reprogrammed. Refer to Section 4.5 and the ST7 Flash
O b Programming Reference Manual for more details.

0: Readout protection off
1: Readout protection on
Flash write protection
This option indicates if the Flash program memory is write protected.
0: Write protection off
OPT0 FMP_W
1: Write protection on
Warning: When this option is selected, the program memory (and the option bit
itself) can never be erased or programmed again
118/124
ST7LUS5, ST7LU05, ST7LU09 Device configuration and ordering information
Option byte 1
Table 91. Option byte 1 bit description

Bit Name Function
Start-up clock selection

These option bits are used to select the startup frequency. By default, the internal RC
is selected.
OPT7:6 CKSEL[1:0] 00: Internal RC as startup clock
01: AWU RC as a startup clock
10: Reserved
11: External clock on pin PA5
OPT5
OPT4
-
-
( s )
Low voltage detection selection
c t
OPT3:2 LVD[1:0]
d u
These option bits enable the LVD block with a selected threshold as follows:
10: Highest voltage threshold
11: LVD off
r o s )
P
Hardware or software watchdog
e c t (
OPT1 WDG SW
l t d u
This option bit selects the watchdog type.
e
0: Hardware (watchdog always enabled)
o r o
1: Software (watchdog to be enabled by software)
s
O b
Watchdog reset on halt
e P
This option bit determines if a reset is generated when entering Halt mode while the
OPT0 WDG HALT
-
Watchdog is active.
l e t
( s )
0: No Reset generation when entering halt mode
o
c t b s
1: Reset generation when entering halt mode
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
119/124
14.1.2 Flash ordering information

The following Table 98 serves as a guide for ordering.
Table 92. Flash user programmable device types

Order code Program memory RAM/EEPROM ADC Temp. range Package Packaging
ST7FLUS5MAE Tube
-40°C to +85°C
ST7FLUS5MATRE Tape and reel
1 Kbyte Flash
ST7FLUS5MCE Tube
-40°C to +125°C
ST7FLUS5MCTRE Tape and reel
128 bytes RAM/ 10-bit SO8
ST7FLU05MAE
no EEPROM
( s ) -40°C to +85°C
Tube
ST7FLU05MATRE
ST7FLU05MCE
c t Tape and reel
Tube
ST7FLU05MCTRE
d u -40°C to +125°C Tape and reel
ST7FLITEU0ICD 2 Kbytes Flash
r o s ) - DIP16(1) Tube
ST7FLU09MAE
e P c t ( Tube
ST7FLU09MATRE
l e t128 bytes
d u
128 bytes RAM/
10-bit
-40°C to +85°C
SO8
Tape and reel
ST7FLU09MCE
s o r
EEPROM
o -40°C to +125°C
Tube
ST7FLU09MCTRE
O b e P Tape and reel
- l e t
1. For development or tool prototyping purposes only. Not orderable in production quantities. Please contact Marketing
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
120/124
ST7LUS5, ST7LU05, ST7LU09 Device configuration and ordering information
14.2 Development tools

Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
14.2.1 Starter kits

ST offers complete, affordable starter kits. Starter kits are complete, affordable
hardware/software tool packages that include features and samples to help you quickly start
developing your application.
14.2.2 Development and debugging tools

( s )
c t
Application development for ST7 is supported by fully optimizing C compilers and the ST7
d u
assembler-linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
r o )
application. The Cosmic C Compiler is available in a free version that outputs up to
s
16 Kbytes of code.
e P c t (
l e t
The range of hardware tools includes full-featured ST7-EMU3 series emulators, cost
d u
effective ST7-DVP3 series emulators and the low-cost RLink in-circuit
s o r o
debugger/programmer. These tools are supported by the ST7 toolset from
STMicroelectronics, which includes the STVD7 integrated development environment (IDE)
b P
with high-level language debugger, editor, project manager and integrated programming
O e
interface.
- l e t
14.2.3 Programming tools
( s ) o
c t b s
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
u O
RLink provide in-circuit programming capability for programming the Flash microcontroller
d -
r o
on your application board.
s )
e P c t (
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 socket boards which provide all the sockets required for programming any of the
l e t d u
devices in a specific ST7 sub-family on a platform that can be used with any tool with in-
circuit programming capability for ST7.
s o r o
For production programming of ST7 devices, ST’s third-party tool partners also provide a
O b P
complete range of gang and automated programming solutions, which are ready to integrate
e
l e t
into your production environment.
s o
14.2.4 Order codes for development and programming tools
O b Table 100 on page 137 lists the ordering codes for the ST7LUxx development and
programming tools. For additional ordering codes for spare parts and accessories, refer to
the online product selector at www.st.com.
121/124
Table 93. Development and programming tool order codes for the ST7LUxx family
In-circuit debugger,
Emulator Programming tool
RLink series(1)
Supported
products Starter kit Starter kit ST socket
In-circuit
without demo with demo EMU series boards and
programmer
board board EPBs
ST7FLUS5
STFLITE- ST7MDT10- STX-RLINK ST7SB10-
ST7FLU05 STX-RLINK(2)
SK/RAIS(2) EMU3 ST7-STICK(3)(4) SU0(3)
ST7FLU09
1. Available from ST or from Raisonance, www.raisonance.com
2. USB connection to PC
s )
3. Add suffix /EU, /UK or /US for the power supply for your region
(
4. Parallel port connection to PC
c t
d u
14.3 ST7 application notes
r o s )
P t (
All relevant ST7 application notes can be found on www.st.com.
e c
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
122/124
ST7LUS5, ST7LU05, ST7LU09 Revision history
15 Revision history
Table 94. Document revision history

Date Revision Changes
25-Jul-2007 1 Initial release

Removed temperature from data retention duration in Memories on page 1
Updated Table 1: Device summary on page 1 for memory and packages
Added note to Section 2: Package pinout and device pin description on page 14
Added MCO to pin 3 in Figure 3 pinout and Table 2 pin descriptions
Added Figure 4: 16-pin DIP package pinout on page 14
( s )
Replaced 25°C with TAmax in Section 6.1 on page 31
Modified conditions and added Note 1 to Table 6 on page 31
c t
Added MCO bit to Section 6.2.1 and to the MCCSR of Table 12 on page 36
Modified Figure 13: Clock management block diagram on page 37
d u
Corrected SICSR reset values for bits 6:5 in Figure 20 and in Table 20 on page 50
r o
Added AWUCSR reset values for bits 2:0 in Table 26 on page 65
s )
Corrected name of bit 2 in Lite timer control/status register (LTCSR) on page 77
P t (
Modified description of CNTR bits in Table 42 on page 83
e c
Corrected CS[2:0] to read CH[2:0] in A/D conversion on page 89
e t u
Modified content of ADC conversion mode on page 89
l d
Added Changing the conversion channel on page 89
s o r o
Modified description of EOC bit in Table 49: ADCCSR register description on page 90
b P
Added ‘direct’ to instruction headings in Section 11.1.4 on page 96
Added Note 2 to Table 67 on page 105
O e
15-Jan-2008 2
l e t
Added Note 2, changed TA from 0°C to -40°C (for ACCRC at VDD = 5V and 3.3V), and
-
( s )
modified min and max values (for ACCRC) in Table 68 and Table 69 on page 106
o
Replaced “JESD22-A114A/A115A standard” with “AEC-Q100-002/-003/-011
c t b s
standard” in Electrostatic discharge (ESD) on page 114
Added the AEC-Q100 standards and ‘class’ column in Table 80 on page 115
d u - O
Updated LU and deleted DLU content in Static and dynamic latch-up (LU) on
page 116
r o )
Updated LU and removed DLU content in Table 82: Latch-up results on page 116
s
e P c t (Modified ‘Ilkg’ symbol and modified min and max values of RPU (VDD = 5V) in Table 83
on page 117
l e t d u Modified min value for RON (VDD = 5V) in Table 85 on page 123
Replaced ‘IL ±1µA’ with ‘Ilkg’ in Figure 69 on page 125
s o r o Inches rounded to four decimal places in Figure 72 on page 128

Added Figure 73: 16-pin plastic dual in-line package, 300-mil width on page 129
O b e P Removed ECOPACK content from Section 13.4 and added updated ECOPACK
l e t content to Section 13.1 on page 128

Removed FASTROM versions from Section 14 on page 131
s o Added DIP16 package to Table 98 on page 133 and modified Note 1

Replaced www.st.com/mcu with www.st.com in Section 14.3.4 on page 136
O b Removed ‘DVP series’ in Table 100 on page 137:

Removed Section 15: Known limitations on page 123
26-Feb-2008 3 Document status promoted from ‘preliminary data’ to ‘datasheet’
123/124
ST7LUS5, ST7LU05, ST7LU09
s )
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
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ST7LUS5, ST7LU05, ST7LU09

8-bit low cost, low pin-count MCU for automotive,

■ 128 bytes RAM

e P c t (■ One 8-bit lite timer with prescaler including:

Clock, reset and supply management

e P c t ( ■ 17 main addressing modes

ST7LUS5 1 Kbyte Lite timer with

February 2008 Rev 3 1/124

2 Package pinout and device pin description . . . . . . . . . . . . . . . . . . . . . 12

3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

s o r o 5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

O b e P 5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

l e t 5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

s o 5.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

O b 5.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 30

O b 8.5 Auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

s o r o 10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

O b e P 10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

s o 10.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

11.1.4 Direct indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 86

14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 118

14.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 49. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 49. Typical VOL at VDD = 5V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

1. Optional on certain devices

2 Package pinout and device pin description

Figure 2. 8-pin SO package pinout

PA5 (HS)/AIN4/CLKIN 2) ei4 ei0 (7 PA0 (HS)/AIN0/ATPWM/ICCDATA

PA4 (HS)/AIN3/MCO 3) ei3 ei1 (6 PA1 (HS)/AIN1/ICCCLK

PA3/RESET 4 ei2 (5 PA2 (HS)/LTIC/AIN2

l t 3 ei0 14 PA0 (HS)/AIN0/ATPWM

e P c t ( PA3 7 ei2 10 PA2 (HS)/LTIC/AIN2

Table 2. Device pin description(1)

1 VDD(7) S Main power supply

d u Analog input 1 or in-circuit

e P c t ( Caution: During normal

O b e Analog input 0 or auto-reload

l e t ei0 X X X Port A0 timer PWM or in-circuit

3 Register and memory map

t 1 Kbyte Flash DEE3h(1)

Figure 5. Memory map (ST7LU05 and ST7LU09)

c t 2 Kbyte Flash DEE3h(2)

Table 3. Hardware register map(1)

0000h PADR Port A data register 00h(2) R/W

e P Reserved area (2 bytes)

l e t ITC EICR2 External interrupt control register 2 00h R/W

Table 3. Hardware register map(1) (continued)

004Bh DMCR DM control register 00h R/W

I/O pins are returned instead of the DR register contents.

4 Flash program memory

s o via cable. ICP is performed in three steps:

4.3.2 In-application programming (IAP)

Figure 6. Typical ICC interface

4.5 Memory protection

4.5.1 Readout protection

Readout protection selection depends on the device type:

4.6 Register description