Design and Implementation of a Frequency
Hopping Hybrid Multiple Access Protocol on FPGA
Hangchao Jiang∗† , Bo Li∗ , Zhongjiang Yan∗ , Mao Yang∗
∗ School
of Electronics and Information, Northwestern Polytechnical University, Xi’an, China
† Science
and Technology on Communication Networks Laboratory, Shijiazhuang, 053200, China
Email:jianghangchao@mail.nwpu.edu.cn, {libo.npu, zhjyan, yangmao}@nwpu.edu.cn
Abstract—The frequency hopping ad hoc network system is
the product of frequency hopping (FH) technology and ad hoc
network technology. Because of its anti-interference, mobility
and invulnerability, the frequency hopping ad hoc network is
widely applied to military and civil communications systems.
To make efficient use of the transmission channel, a frequency
hopping hybrid multiple access (FHMA) protocol is proposed
for frequency hopping ad hoc network. Each hop duration of
the FH is divided into three parts. The first one is the transition
period for frequency synthesis, and the following part is the time
division multiple access (TDMA) period for reservation based
multiple access, and the last part is the carrier sensing multiple
access with collision avoidance (CSMA/CA) period for random
access. Furthermore, an FPGA based implementation design is
given for FHMA, where the transmitter module as well as the
receiver module are designed with the finite state machine (FSM)
method. Finally, the FHMA is implemented in Xilinx Vivado
design suite to show the project is feasible and efficient. This
protocol implementation is done in Verilog HDL language so
that it can be easily transplanted. Behaviour simulation results
verifies the correctness of the implementation.
Index Terms—Frequency hopping ad hoc network, Frequency
hopping hybrid multiple access protocol (FHMA), MAC, FPGA.
I. I NTRODUCTION
Ad hoc network works without fixed infrastructure, where
every mobile has the same data communication function.
Frequency hopping is a kind of technique, which switches
working frequency in a random sequence. Frequency hopping
ad hoc network system combines FH technology with ad hoc
network technology. It gets the anti-interference performance
from FH technology and the performance of network mobility
and invulnerability from ad hoc network technology [1], [2].
FH multiple access control (MAC) protocol plays a key role
in applications which have higher demands of timeliness and
reliability, such as aeronautical ad hoc network (AANET). In
such a network the MAC protocol is desired to be implemented
on field programmable gate arrays (FPGA) due to its advan-
tages, such as high integration, high speed and low power
consumption. FPGA is a kind of semi-custom circuit that
develops on the original hardware-editable device in recent
years. Using FPGA to implement the MAC protocols can make
the design product miniaturized, integrated and reliable, while
the development cycle is greatly shortened. What’s more, it is
convenient for internal debugging and modification.
978-1-5386-7946-3 / 18 / $ 31.00 
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There are two main challenges emerging to implement an
FH MAC protocol on FPGA. Firstly, frequency synthesizer
is the most important part in FH, which can generate a
large number of discrete frequency signals from one or more
standard signals. It usually has two stages when frequency
hopping. One is the transition period (transient time), and
the other is the retention period (stable-state time) [3]. The
transition period is required to be as short as possible in order
to achieve high-speed conversion, but it actually exists and can
be easily ignored in the design of FH MAC protocol. Thus
how to design an FH MAC protocol by taking the transition
period into account, becomes the first challenges. Secondly,
how to accurately describe the sequential working procedures
of the designed MAC protocol on FPGA becomes the other
challenge. Since FPGA, as a hardware platform, is a parallel
working environment, while the designed MAC protocol is
usually a time dimensional sequential working process.
The related works on how to design and implement FH
MAC protocols on FPGA can be classified into two categories,
according to the ‘design’ and/or the ‘implement’ of a MAC
protocol on FPGA.
• A large amount of new MAC protocols combined FH
with other techniques are proposed. In Ref. [4], a protocol
called statistical priority-based media access (SPMA) is
proposed, that is based on contention based CSMA and
asynchronous frequency hopping technique. A virtual full
duplex physical frequency hopping method is employed,
which enables the node overhears all the transmitting
signals while it is sending messages to other nodes. Ref.
[5] analyses the performance of a slow-frequency-hopped
with reservation based TDMA communication system.
In Ref. [6], it shows the combination of CSMA/CA
and TDMA can improve the channel access capacity of
the wireless communication networks. A MAC protocol
that is equipped with the CSMA/CA and the scheduling
method based TDMA is put forward to output a better
throughput in [7]. These paper indicate the capability of
hybrid multiple access protocol is better than one only
multiple access protocol.
• An FPGA based design and implementation of IEEE
802.15.4 MAC protocol is shown in Ref. [8]. And an
efficient method to design time-critical MAC protocol
by using finite state machines (FSM) is given in [9]–
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[11]. In Ref. [9] shows how to make a 802.11MAC
FPGA-based prototype in FSM. Ref. [10] focuses on
designing and implementation of next generation WLAN
MAC prototype. A modified 802.11MAC FPGA-based
prototype is proposed and designed in Ref. [11].
As far as the authors know, there exists no works on FPGA
based design and implementation of FH MAC protocols. This
motivates us to combine FH with hybrid multiple access
protocol to design an FH hybrid multiple access protocol,
and implement it on FPGA. The main contributions are
summarised as follows:
• A frequency hopping hybrid multiple access (FHMA)
protocol is proposed, which combines the FH tech-
nology, reservation based TDMA and contention based
CSMA/CA. It can not only improve anti-interference
performance of the system, but also enhance the channel
utilization.
• A design scheme of FHMA on FPGA is proposed by
using finite state machine (FSM) [12] method. With FSM,
the proposed MAC protocol is designed as a control logic
of a node, which controls the node when to send, to
receive and to backoff/wait according to the state of the
FSM. Both the designed FSMs of the sender module and
the receiver module are given.
• The proposed FHMA is implemented in Xilinx Vivado
design suite. The project is edited in Verilog HDL, which
can be easily transplanted. Behaviour simulation results
verify that the design and implementation is reliable.
The rest of this paper is organized as follows. In Section
II, we provide an integrated framework of FHMA to describe
the overall model of the protocol. In Section III, we provide
a comprehensive introduction to FHMA proposed by us. In
Section IV, we illustrate the the system FPGA design scheme
and the key part design of hybrid multiple access protocol.
Section V describes the simulation results of the FHMA in
Vivado design suite. Section VI concludes this paper.
II. S YSTEM M ODEL
Suppose that there are many nodes deployed in an ad
hoc network, and every one uses an FH system capable of
wireless communication. Fig.1 shows the working process of
the frequency hopping system. The wide frequency band is
divided into N narrow frequency channels, while the time
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is also slotted into time slots. When each time slot starts,
the system will hop into another frequency channel in a
discrete random FH sequence. Let T denote the length of the
timeslot. In each timeslot, there exists an FH unstable period
at the beginning of the timeslot, with length of Tu , named the
transition period of the FH system. And the left part of the
timeslot is the retention period, with length of T − Tu . The
transition period is reserved to make sure that frequency slots
are switched successfully. And the retention period is provided
for transmission of data, where the proposed hybrid multiple
access protocol works.
III. FHMA: FH H YBRID M ULTIPLE ACCESS P ROTOCOL
This section will introduce FHMA in details. The basic
principle of FHMA is to divide the time line into time frames
first, where each time frame consists of M timeslots. Then, for
each time slot the retention period is divided into two parts,
i.e., the reservation based TDMA period Tt , and the contention
based CSMA/CA period Tc , where we have T -Tu =Tt +Tc .
Fig.2 shows the time frame structure of the proposed
FHMA. The length of these three periods is different but fixed.
The length of FH period is determined by the frequency syn-
thesizer, then the length of other two periods can be optimized
by evaluating its performance via network simulation.
In each time frame, the TDMA periods, i.e., Tt , of the
timeslots can be scheduled by a cluster head, or dynamically
reserved in distribute. Because TDMA has the performance
of real-time, some important data that has high real-time and
reliability requirements will send in revised TDMA. During
the contention based CSMA/CA period Tc , the nodes contend
to access into the channel in a CSMA/CA mode, and an
example is shown in Fig.3. The nodes transmitting data in
CSMA/CA mode, can enhance the channel utilization of the
network. Therefore, the proposed FHMA can provide different
traffic quality of service (QoS), and the traffic priorities can
be defined according to its data type.
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Then standard CSMA/CA protocol with CTS and RTS
[13] is employed, when it is in CSMA/CA period. Fig.3
provides an example for the sequential logic of the CSMA/CA
protocol. Firstly, if ST A1 and ST A2 have data to send, the
random number generated from different back-off windows
starts to count down after the duration of the DIFS. Secondly,
when the back-off number of ST A1 earlier gets to zero,
this user is allowed to send data first, at the same time,
ST A2 records the remaining back-off number (six). Thirdly,
RTS/CTS mechanism works in ST A1. ST A1 waits for the
duration of SIFS after confirmation of CTS. Then ST A1 is
allowed to send data of allowed transmission length. Finally,
after the ACK is confirmed, data transmission ends. After that,
new channel contention access starts among the users that need
to send data. ST A2 will restarts to count down the back-off
number from six to zero after the DIFS duration.
IV. FPGA IMPLEMENTATION SCHEME OF FHMA
The FPGA implementation diagram of FHMA is shown in
Fig.4, which consists of two parts, i.e., the sender module and
the receiver module. In the transmitter, data that need to be
sent enters the sender module, and the data frame as well
as the control frame are sent in the corresponding protocol.
After the receiver module receives the frame from PHY, it
will output corresponding information according to different
types of frame. Next we will detail the implementation scheme
of the sender module and the receiver module.
A. FPGA implementation scheme of sender module
The sender module consists of three parts, clock counter
module, TDMA module and CSMA/CA module. The
clock counter module is equivalent to control the sender
module, which outputs signals of tdma f reeze en and
csma f reeze en according to the time periods of Tt and
Tc , to freeze the TDMA and CSMA/CA module periodically.
When the TDMA or CSMA/CA module is frozen, it will stay
in the current process until the freezing signal becomes invalid.
TDMA module and CSMA/CA module send data according
to the TDMA and CSMA/CA protocol respectively.
the fixed time T . When the counter gets to 0, the initial value is
restored and the counter is reset. The fixed time is divided into
three phases. As shown in Fig.2, Tu is the FH period, during
which both tdma f reeze en and csma f reeze en are valid.
Tt is the TDMA period, during which tdma f reeze en
is invalid and csma f reeze en is valid. Tc is the CS-
MA/CA period, during which tdma f reeze en is valid and
csma f reeze en is invalid. The specific output signal values
of various stages can be seen in Fig.7 in Section V.
CSMA/CA system can be considered as an extend finite
state machine (EFSM) [14]. Fig.5 is the extend finite state
machine of CSMS/CA, each circle represents a state, that has
an inner sub-FSM to realize the function. What’s more, the
FSM in Fig.5 is a top-level controller, and each function task
is finished in the sub-FSM. The controller can send a start
signal (or enable signal) to the sub-FSM to enable the sub-
FSM to run, and a busy signals to withdraw when the sub-FSM
completes the task. The sub-FSM plays a co-processing role
in the project, it can make the overall project more readable
and maintainable.
Next, the design of the CSMA/CA EFSM is detailed. Firstly,
a finite set of states should be constructed. According to the
protocol of CSMA/CA, the system is divided into nine states.
{IDLE, DIF S W AIT ER, BACKOF F W AIT ER,
RT S SEN D, CT S W AIT ER, SIF S W AIT ER,
DAT A SEN D, ACK W AIT ER, CT S/ACK SEN D,
BACKOF F CW IN }.
• IDLE: The initial state.
• DIF S W AIT ER: Waiting in the duration of DIFS.
• BACKOF F W AIT ER: Waiting in the duration of
back-off.
• RT S SEN D: Packaging and sending RTS.
• CT S W AIT ER: Waiting for CTS coming.
• SIF S W AIT ER: Waiting in the duration of SIFS
• DAT A SEN D: Packaging and sending DATA frame
• ACK W AIT ER: Waiting ACK coming
• CT S/ACK SEN D: Packaging and sending CTS/ACK
Secondly, the main inputs is {clk, rst, data en,
data in length, sif s waiter1 over, sif s waiter2 over,
nav, cca, cts valid, ack valid}.
• clk: System synchronization clock
• rst: System reset signal
• data en: Data ready to be sent
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• data in length: Length of the input data
• sif s waiter1 over: Signal from receiver module to tell 6,)6B:
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• nav: Signal of Network Allocation Vector
• cca: Signal of Clear Channel Assessment 3 1 '

• cts valid: Signal of right CTS has been received
• ack valid: Signal of right ACK has been received
Thirdly, the main outputs Δ = {csma o en, csma o,
ready data in en, ready data in en1}. The outputs is de-
scribed below.
• csma o en: csma o valid
• csma o: The output of data frame and control frame
• ready data in en: Acknowledge signal from sender
module to tell memory module to send CSMA/CA data
in
• ready data in en1: Acknowledge signal from sender
module to tell memory module to send TDMA data in
Finally, letters of A-P represent all transitions from one
state to another state in Fig.5. Now, we try to describe each
letter in 3-tuple(pt , nt , ct ) [15], where: pt represents the
present state; nt is the next state; and ct is the transition
condition, that returns 1/0 to enable/disable the transition.
• A: (IDLE, CT S/ACK SEN D, The signal of sending
CTS or ACK comes)
• B: (CT S/ACK SEN D, IDLE, CTS/ACK has been
sent over)
• C: (IDLE, DIF S W AIT ER, Data ready to be sent
and channel is free)
• D: (DIF S W AIT ER, IDLE, Channel is busy)
• E: (DIF S W AIT ER, BACKOF F W AIT ER, D-
IFS counts to zero)
• F : (BACKOF F W AIT ER, IDLE, Channel is busy)
• G: (BACKOF F W AIT ER, RT S SEN D, Back-off
number counts to zero)
• H: (BACKOF F W AIT ER, DAT A SEN D, The
length of data is quite small)
• I: (RT S SEN D, CT S W AIT ER, RTS has been sent
over and the length of data is long)
• J: (CT S W AIT ER, IDLE, CTS overtime time out-
numbers maximum time or right ACK arrives)
• K: (CT S W AIT ER, DIF S W AIT ER, CTS over-
time and the time is no larger than maximum time)
• L: (CT S W AIT ER, SIF S W AIT ER, Right CTS
arrives)
• M : (SIF S W AIT ER, DAT A SEN D, SIFS counts
to zero)
• N : (DAT A SEN D, ACK W AIT ER, Data frame has
been sent over)
• O: (ACK W AIT ER, DIF S W AIT ER, ACK over-
time and the time is no larger than maximum time)
• P : (ACK W AIT ER, IDLE, ACK overtime time out-
numbers maximum time or right ACK arrives)
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Fig. 6. Finite state machine of receiver module.
B. FPGA implementation scheme of receiver module
The function of the receiver module is to parse the received
frame and generate a corresponding signal to inform the sender
module to send the corresponding CTS or ACK or DATA
frame.
Fig.6 is the extend finite state machine designed for the
receiver module. Its design follows the same principle of
CSMAM/CA above.
The receiver module can be divided into nine states
according to its function, {IDLE, RECV V ECT OR,
RECV DAT A, RECV CT S/ACK, DAT A W AIT ER
N AV U P DAT E, RECV RT S, SIF S W AIT ER1,
SIF S W AIT ER2}.
• IDLE: The initial state.
• RECV V ECT OR: Receiving vector from PHY, and
analyzing the type of following frame.
• RECV DAT A: Receiving and analyzing Data frame.
• RECV RT S: Receiving and analyzing RTS.
• RECV CT S/ACK: Receiving and analyzing CTS or
ACK.
• N AV U P DAT E: Updating and countdowning NAV.
• SIF S W AIT ER1: Waiting in the duration of SIFS to
tell sender to send CTS.
• SIF S W AIT ER2: Waiting in the duration of SIFS to
tell sender to send ACK.
• DAT A W AIT ER: Waiting data frame coming.
Secondly, the input ports can be just regard as the output
ports of sender module. The main inputs are {clk, rst,
csma in en, csma in}.
• clk: System synchronization clock
• rst: System reset signal
• csma in: Input of data frame and control frame
• csma in en: csma in valid
Thirdly, the outputs Δ = {sif s waiter1 over,
sif s waiter2 over, nav, cts valid, ack valid, data out,
data out en}. The first five outputs is just part of the inputs
of sender module, so these outputs will not be declared again
and the other outputs are described below.
• data out en: data out valid
• data out: Output of valid data from data frame
 Finally, all transitions in Fig.6 are also represented by letters
of A-P again. Here is the description of A-P .
• A: (IDLE, RECV V ECT OR, Data frame coming)
• B: (RECV V ECT OR, RECV DAT A, Following
frame is data frame)
• C: (RECV V ECT OR, RECV RT S, Following
frame is RTS)
• D: (RECV V ECT OR, RECV CT S/ACK, Follow-
ing frame is CTS/ ACK)
• E: (RECV DAT A, SIF S W AIT ER2, CRC check
of DATA frame is correct)
• F : (RECV DAT A, IDLE, Destination address does
not match the local address or CRC check is wrong or
the frame is sent in TDMA)
• G: (SIF S W AIT ER2, IDLE, SIFS counts to zero)
• H: (RECV RT S, SIF S W AIT ER1, Destination ad-
dress matches the local address and CRC check is correct) Fig. 7. Simulation of the sender module.
• I: (RECV RT S, IDLE, CRC check is incorrect)
• J: (RECV RT S, N AV U P DAT E, Destination ad-
dress does not match the local address and CRC check
is correct)
• K: (SIF S W AIT ER1, DAT A W AIT ER, SIFS
counts to zero)
• L: (DAT A W AIT ER, IDLE, Waiting data frame
overtime)
• M : (DAT A W AIT ER, RECV V ECT OR, Data
frame coming)
• N : (RECV CT S/ACK, IDLE, CRC check is incor-
rect or the destination address matches the local address
and the CRC check is correct)
• O: (RECV CT S/ACK, N AV U P DAT E, Destina- Fig. 8. Simulation of the receiver module.
tion address does not match the local address and CRC
check is correct)
• P : (N AV U P DAT E, IDLE, NAV counts to zero) csma o en in Fig.7. Therefore, the functional simulation of
V. S IMULATION R ESULTS this module is equivalent to the overall functional simulation.
As we can see, the data received in Fig.8 is the same as data
We employ Xilinx’s Vivado design suite to implement FH- transmitted in Fig.7. In the Box ,
1 tdma mode en becomes
MA in VC707 Evaluation Platform. The entire design is imple- 1 when the frame comes, it means this frame is sent in TDMA.
mented using Verilog HDL hardware description language. In Box  2 and  3 show that when the receiver receive frame
the test verification process, a testbench is used to complete the transmitted in CSMA/CA, a series of follow-up signals will
verification. The following is the simulation of each module work as the design in Fig.6.
and the whole project. In the overall simulation verification, Fig.9 is the simulation of receiver output. This model
In consideration of no physical layer (PHY), so the sender and extracts the valid data and outputs them from the port of
receiver module interfaces are directly connected without the data out. Port data out en indicates data out data valid
physical layer.

A. Simulation of data sender module

Fig.7 shows the simulation result of the sender module. In
the Box ,
1 the data transmitted in the TDMA mode is sent out
when the user id and tdma f reeze en are both 0. In Box
2 and ,
3 the data and RTS are sent after channel contention.

B. Simulation of data receiver module

The input interfaces of receiver module are directly con-
nected the data output of the sender module, csma o and Fig. 9. Simulation of receiver output.

Fig. 10. resource utilization of FPGA chip.
output. In order to see if the output is right, in the testbench,
the length of effective data in data frame is changed to 3.
Compared to the data in Box  1 and . 2 the csma o valid
data are correctly extracted when the data out en is high.
The simulation of the receiver module is just the simulation
of the overall system. The overall functional simulation tallies
with the design of protocol, so the design of receiver model
is correct.
C. FPGA chip resource utilization
Fig.10 shows the resource utilization of the FPGA chip in
the project including the entire transmission module and the
receiving module. As shown in the figure, the total number
of LUTs and Registers used is small, and the percentage is
very little. It basically meets the requirements of the design to
minimize the use of on-board resources. As we can see, there
are lots of I/O ports being used in the project, because we
employ a large number of inputs that enable some intermediate
variable, like the length of SIFS and DIFS to be changed.
In summary, the data receiving process of the receiving
module is correct and the data is correctly parsed. The success
of the overall joint adjustment between the receiving mod-
ule and the sending module is demonstrated, which further
proves that the design scheme is correct and the utilization
of on-board resources is low. The overall design meets the
requirements and at the same time it proves that the overall
design scheme is feasible.
VI. C ONCLUSION
Nowadays, frequency hopping ad hoc network is widely
applied to military and civil communications network systems.
This paper proposes an FH hybrid multiple access protocol
for frequency hopping ad hoc network, named as FHMA, and
proposes its FPGA based design and implementation using
FSM. The proposed FPGA implementation is given, which
mainly includes the sender module as well as the receiver
module. Both these two modules are designed in the method
of finite state machine. Furthermore, the states, inputs, outputs,
and the state transition conditions are given in detail. The
proposed FPGA implementation method is implemented with
the Xilinx’s Vivado design suits, and behavior simulation
results are given. Simulation results show that the design
scheme is correct. What’s more, this proposed FPGA based
finite state machine design is not only simple and convenient,
but also can be a reference for other frequency hopping ad
hoc network MAC protocol.
ACKNOWLEDGEMENTS
This work was supported in part by the National Nat-
ural Science Foundations of CHINA (Grant No.61771392,
61771390, 61501373 and 61271279), the National Science
and Technology Major Project (Grant No. 2015ZX03002006-
004 and 2016ZX03001018-004), the Fundamental Research
Funds for the Central Universities (Grant No. 3102017ZY018),
and the Science and Technology on Communication Networks
Laboratory Open Projects (Grant No. KX172600027).
R EFERENCES
[1] M. C. Valenti, D. Torrieri, and S. Talarico, “Optimization of a finite
frequency-hopping ad hoc network in nakagami fading,” pp. 1–6, 2012.
[2] C. Jin and S. W. Jin, “Invulnerability assessment for mobile ad hoc
networks,” in Power Electronics and Intelligent Transportation System,
2008. PEITS’08. IEEE Workshop on, 2008, pp. 48–51.
[3] Y. Taki, “Frequency synchronous circuit for reducing transition period
from power on state to stable state,” U.S. Patent 5,461,345, Oct. 24,
1995.
[4] J. C. Herder and J. A. Stevens, “Method and architecture for ttnt symbol
rate scaling modes,” U.S. Patent 7,839,900, Nov. 23, 2010.
[5] S. Chennakeshu, A. A. Hassan, J. B. Anderson, and B. Gudmundson,
“Capacity analysis of a tdma-based slow-frequency-hopped cellular
system,” IEEE Transactions on Vehicular Technology Vt, vol. 45, no. 3,
pp. 531–542, 1996.
[6] B. Shrestha, E. Hossain, and K. W. Choi, “Distributed and centralized
hybrid csma/ca-tdma schemes for single-hop wireless networks,” IEEE
Transactions on Wireless Communications, vol. 13, no. 7, pp. 4050–
4065, 2014.
[7] Y. A. Chau and Y. H. Chen, “Adaptive medium access control with
csma/ca and tdma for overlay networks,” in Signal Processing Advances
in Wireless Communications, 2006. Spawc ’06. IEEE Workshop on,
2007, pp. 1–5.
[8] N. S. Bhat, “Design and implementation of ieee 802.15.4 mac protocol
on fpga,” arXiv preprint arXiv:1203.2167, 2012.
[9] J. Zhang, “Fpga-based mac prototype design and implementation of
wlan,” 2015.
[10] R. Zhang, “An fpga based mac prototype design and implementation for
the next generation wlan,” 2016.
[11] Z. Zhang, “Research and implementatiaon of key technology in the next
generation mac prototype,” 2017.
[12] A. Gill, “Introduction to the theory of finite-state machines,” Mathemat-
ics of Computation, vol. 92, no. 29, pp. 63–74, 1962.
[13] G. Bianchi, L. Fratta, and M. Oliveri, “Performance evaluation and
enhancement of the csma/ca mac protocol for 802.11 wireless lans,” in
IEEE International Symposium on Personal, Indoor and Mobile Radio
Communications, 2002, pp. 392–396 vol.2.
[14] W. E. Wong, A. Restrepo, Y. Qi, and B. Choi, “An efsm-based test gen-
eration for validation of sdl specifications,” in International Workshop
on Automation of Software Test, 2008, pp. 25–32.
[15] C. H. Shih, J. D. Huang, and J. Y. Jou, “Automatic verification stimu-
lus generation for interface protocols modeled with non-deterministic
extended fsm,” IEEE Transactions on Very Large Scale Integration
Systems, vol. 17, no. 5, pp. 723–727, 2009.