PCIM Europe digital days 2020, 7 – 8 July 2020

Combining Time and Frequency Domain Design in Current Control

to Optimize Command and Disturbance Response
Christoph H. van der Broeck1 , Marc S. Petit2 , Bulent Sarlioglu2 , Rik W. De Doncker1
1
ISEA, RWTH Aachen University, Germany
2
WEMPEC, University of Wisconsin–Madison, USA
Corresponding author: Christoph H. van der Broeck , cvb@isea.rwth-aachen.de
The Power Point Presentation will be made available after the conference.
Abstract
This paper presents a model-based design method for current controllers of pulse-width modulated converters. It
demonstrates how the command-tracking and disturbance rejection behavior of current controllers must be designed
separately via appropriate state-feedback and feedforward paths, as well as feasible references to yield an optimized
system behavior. The method features a state-feedback design in the frequency domain that optimizes the load
and disturbance voltage response and illustrates important design limitations. The state-feedback design in the
frequency domain is effectively linked to the time domain to facilitate a physically understanding of all control design
decisions. For optimized, high-bandwidth command tracking, a trajectory filter generates feasible references for the
state-feedback control, as well as for command-feedforward. The trajectory filter takes into account the available
voltage margin and limits the di/dt of the trajectories to prevent saturation of the feedback controller and eliminate any
windup issues. The proposed design method is evaluated based on experiments that validate its wide applicability.

1 Introduction properties of any control design with a given parameter

The high-performance current control of power electronic
systems is critical in many applications, e.g. electrical
drives [1]–[3], grid-integration of renewable energies [4],
[5] and electric vehicles [6], [7]. The most common
control technologies are linear state-feedback controllers
that utilize proportional and integral (PI) feedback paths
and a pulse-width modulation unit. For those designs,
various methods were proposed, e.g. the symmetrical
optimum [8], designs based on phase-margin and cut-
off frequency [9] or the root locus method [10]–[12].
These methods enable designing regulators with well-
behaved dynamics ensured by suitable eigenvalue (EV)
placements. However, they do neither provide insight
in design limits, e.g. limited modulator and sensor
bandwidth or voltage limits, nor reflect command and
disturbance response properties of the closed-loop
system.
In particular, many control designs fail at providing
control systems with PI regulators that achieve
optimized command-tracking and disturbance rejection
characteristics. To overcome this limitation many
advanced control technologies were proposed [13], e.g.
model predictive control, adaptive control, fuzzy control
and sliding-mode control. Although these non-linear
control techniques are suitable to find solutions for one
problem, they fail in providing physical insight into design
trade-offs and limitations. Consequently, computer-
aided control design tools, e.g. the MATLAB PID Tuner,
have been developed [14]. These show time domain
set and allow improving control design in a trial and error
way. However, these computer-aided control design tools
exhibit two substantial limitations: They do not provide
physical insight on why a specific design leads to good
results. They encourage the control designer to develop
a PID feedback controller to optimize both, command
tracking and disturbance response behavior. This design
perspective is conceptually deceptive since considering
both design goals with a PID controller can only yield
mediocre system performance.
This work aims to overcome the indicated limitation by
proposing an insightful, model-based control structure
and design for current control of PWM converters.
The introduced control structure exhibits feedback and
feedforward paths, as well as a command trajectory filter.
This structure supports an optimized design of both,
command tracking and disturbance rejection response:
– A state feedback design method is developed
to generate optimized disturbance response
properties. The method reveals the impact of
the feedback gains on frequency and time domain
behavior and links frequency and time domain.
Thereby, it yields maximum insight to design
limitations and closed-loop system behavior.
– A trajectory filter is introduced that creates a current
reference and command feedforward voltage taking
into account the limitation of the converter, i.e. the
maximal di/dt that is feasible with the available

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 PCIM Europe digital days 2020, 7 – 8 July 2020

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Fig. 2: PWM operation with triangular carrier with illustration diL

L = upwm − Uout − Rp · iL (1)
of double-sampling double-update process dt
converter voltage. Applying the current reference dīL
L = ūpwm − Uout − Rp īL (2)
and command feedforward voltage consistently to dt
the state feedback controller enables command This equation indicates how the average voltage that can
tracking with the maximal bandwidth that is possible. be manipulated via PWM according to ūpwm = Uin · d
The paper starts by introducing and analyzing the results in a change of the averaged current īL . The
physical model that is used for the control design. averaged current is extracted by synchronous sampling,
Consequently, the paper introduces the state-feedback i.e. at the top and the bottom of the carrier, as illustrated
design that optimizes disturbance rejection behavior. in Fig. 2. As the control algorithm requires a minimal
Then, the paper addresses the implementation of high- computation time ΔT > 0 to compute the manipulated
bandwidth command tracking using trajectory filters input voltage for the next sampling interval um (k + 1)
for reference and command feedforward generation. and as the latched duty cycle only allows updates at
Finally, experimental results are shown and discussed to the sampling instant, a delay of one sampling period
evaluate the control performance of the approach. Ts is introduced. This intrinsic limitation illustrated in
2 Converter Modeling and Analysis Fig. 2 does not affect control loops with low bandwidth,
but limits the performance of high-bandwidth control
2.1 Modeling the Converter Behavior systems.
Fig. 1 shows the topology and pulse-width modulation For the control analysis and design, the power converter
unit of a half-bridge converter: The manipulated input is simplified to a linear circuit depicted in Fig. 3. It
voltage um that is calculated by the control algorithm is consists of a controlled voltage source um , an inductance
passed as a reference voltage u∗pwm to the PWM unit. L, the strait resistance of the inductance Rp and the load
The PWM modulation unit first determines the duty cycle voltage uload . Besides the load voltage, a disturbance
for the converter d = u∗pwm /Uin . The duty cycle is latched voltage udist is included that takes into account voltage
over one sampling period Ts to prevent multi switching drops within the circuit that are not measured and thus
events and afterwards compared with a triangular carrier cannot be included in the load voltage, e.g. due to
signal to generate a switching command that is passed blanking time, sensor errors and parameter deviations.
to the power devices S1 and S2 . Thereby, the half-bridge The control algorithm to be developed can use the
converter realizes an average pulse-width-modulated load voltage and current information. It determines
voltage ūpwm that is equal to the manipulated input the manipulated input voltage to realize a commanded
voltage um . This carrier-based generation of the duty reference current with command tracking high bandwidth
cycle and the PWM voltage waveform is shown in Fig. 2. in the presence of load voltage changes, disturbances

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 PCIM Europe digital days 2020, 7 – 8 July 2020


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Fig. 5: Disturbance response (left) and dynamic stiffness (right) showing the disturbance response of a power converter at open
loop control with/without resistance and using proportional feedback control.

voltages and model inaccuracies. The equivalent circuit response transfer function DS(jω) = Gd (jω)−1 and tells
is be mapped to a state block diagram of the power at every excitation frequency how much disturbance
converter depicted in Fig. 4 that allows inspecting the voltage must appear to change the state variable, i.e
dynamic behavior of the power converter and reveals converter current, by 1 A. Equation (5) determines the
cause-effect relations. This insight into the physical magnitude of the DS, as it includes most information on
behavior of the system provided by the state block the system dynamics.
diagram is of great importance for the development   
of effective control algorithms. Furthermore, the state  Udist (jω)  iff < fb
|DS(jω)| =   = |jωL + Rp | = Rp
block diagram allows including a dynamic model for IL (jω)  2πf · L iff > fb
the pulse-width modulation and update delay M (s) =
1 1 1 Rp sEV
Upwm (s)/Um (s) = exp (−sTd ). with fb = · = · =− (5)
2π τb 2π L 2π
2.2 Time and Frequency Domain Analysis
The DS plot is depicted for the same exemplary cases
Before addressing the control design, the dynamic open like the disturbance step response in Fig. 5. It can be
loop behavior of the power converter is examined at constructed based on two asymptotes: One asymptote
an equilibrium, e.g. a constant current of 0 A. This is a constant with the magnitude of the resistance. It
is realized by applying a manipulated input voltage um dominates the DS up to the bandwidth fb The finite
that is equal to the load voltage uload . The disturbance dynamic stiffness of Rp that reaches towards 0 Hz
response of the open-loop system in the time domain reflects that constant disturbance voltages udist,0 cannot
is calculated based on the disturbance transfer function be rejected without steady-state error, but results in a
Gd (s) and the step disturbance Ud (s) according to (3) permanent error of ΔiL = udist,0 /Rp as shown in the
and (4). time domain response. Above the bandwidth fb the
IL (s) 1 udist dynamic stiffness is dominated by an inclining asymptote
Gd (s) = = and Ud (s) = (3) that reflects the inductance according to (5). The green
Udist (s) s · L + Rp s
udist   DS plot in Fig. 5 illustrates that a sinusoidal disturbance
iL (t) = L−1 {Ud (s) · Gd (s)} = 1 − e−t/τb (4) voltage with an amplitude of V̂ = 1 V results in a current
Rp
response with a magnitude of IˆL = 10 A at excitation
The disturbance response in the time domain iL (t) is frequencies below 5 Hz. At higher excitation frequencies
exemplary plotted in Fig. 5 for a relevant and a negligible the current amplitude declines due to the increased
resistance Rp in green and blue. It can be characterized stiffness, e.g. an excitation at 50 Hz with V̂ = 1 V results
by two properties: The time constant τb = L/Rp that in a current response with a magnitude of IˆL = 1 A.
determines the transient of the response and the steady- Utilizing the dynamic stiffness DS(jω) as a disturbance
state error ΔiL = udist /Rp . These properties show that response metric has one key advantage over the
a larger resistance Rp leads to a faster response and a classical disturbance response transfer function Gd (jω).
smaller steady-state error. It provides useful insight into how a change in the
Similarly, the open-loop response characteristics can be physical parameters, i.e. the inductance L and the
analyzed in the frequency domain. This paper utilizes resistance Rp , impacts the disturbance response over
the dynamic stiffness (DS) for analyzing the disturbance the entire frequency range. As an example, an increased
response properties in the frequency domain [15], [16]. resistance Rp can effectively improve the disturbance
The DS is equal to the inverse of the disturbance rejection ability. However, this is not a desirable option as

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 PCIM Europe digital days 2020, 7 – 8 July 2020
 bandwidth fp . Therefore, the proportional feedback
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Fig. 6: Proportional (and integral) state feedback control with
disturbance input decoupling
a larger resistance comes along with additional losses.
3 State Feedback Design for
Optimized Disturbance Rejection
The feedback control of converters has the primary
objective to reject disturbances. This typically requires
to find a compromise between the following goals:
– Fast compensation of disturbances
– Achieve zero steady-state error
– Avoid unwanted system resonances
– Minimize the effect of sensor noise
3.1 Proportional State Feedback Control
To minimize the effect of disturbances, a first measure
is the decoupling of all known load voltage components,
e.g. load voltage and blanking time voltages,
summarized as uload that have an impact on the current
iL . The state block diagram depicted in Fig. 6 illustrates
this load voltage decoupling. It assumes that the
modulator delay is negligible within the bandwidth of
the control loop M (s) = 1. This is a valid assumption up
to a bandwidth of fpwm /10 at which modulator dynamics
must be considered.
To mitigate the effect of disturbance voltages that cannot
be decoupled, the passive feedback that is provided
by the resistance Rp is actively enhanced by adding
a proportional feedback loop with the gain Kp . As
this active feedback loop lies in parallel to the passive
feedback, the sum of both gains determines the dynamic
stiffness at low bandwidth as can be seen in (6) and the
red DS plot in Fig. 5.
   reference without steady-state error, an integral feedback
 Udist (jω)  Kp + Rp if f < fp
 
 IL (jω)  = |jωL + Rp + Kp | ≈ 2πf L if f ≥ fp
Kp
Kp ≈ 2πfp L → fp =
2πL
The intersection of asymptotes that span the dynamic
stiffness allows calculating the proportional feedback
bandwidth fp in which the feedback control loop provides
the dynamic stiffness of the system actively (6). Above
this bandwidth fp the dynamic stiffness is provided
passively as a result of the inductance L. To realize
a feasible closed-loop control, the PWM must be
able to create a manipulated input voltage up to the
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G
 GW L/  L/ frequency fpmax = fPWM /10. Otherwise, resonances
/ V can occur due to the delay between sampling and
5S update and the limited bandwidth of the modulator.
Consequently, control designs with bandwidths above
fpmax need to model these effects via M (s). The
introduced bandwidth limit fpmax ≈ fPWM /10 results
from a maximal gain of Kpmax = L/(3Ts ) that is derived
for state-feedback current controllers in [5]. A further
limitation of the proportional feedback bandwidth exists if
the current sensor does not provide an acceptable signal-
to-noise-ratio above a certain bandwidth fsense . In this
case, the proportional feedback bandwidth must remain
below fsense . Otherwise, the feedback control tries to
compensate sensor noise and thereby adds noise on
the current iL . Consequently, the maximal proportional
feedback gain is limited to Kpmax ≈ 2πfpmax L. This
imposes a limit to the disturbance rejection ability of the
closed-loop control systems that can only be pushed by
operating at higher PWM frequencies and utilizing high-
performance sensors or by installing a larger inductance.
The maximal state feedback gain also limits the
dynamics and steady-state error of the disturbance step-
response in the time domain that is given by (7) and
plotted in Fig. 5.
udist
iL (t) = · (1 − exp (−t/τp )) (7)
Rp + Kp
L L 1 1
τp = ≈ =− = (8)
Rp + Kp Kp sEV 2πfp
The dynamics of the disturbance step response are
reflected by the time constant τp that directly relates
to the control bandwidth fb and Kp . The system time
constant τp and the steady-state error ΔiL = udist /Kp
can be minimized by increasing Kp up to the introduced
limit Kpmax . However, a proportional state-feedback
regulator cannot entirely reject dc-disturbances, such
that a steady-state error always remains.
3.2 Integral State Feedback Path
To compensate dc-disturbances and follow a constant
path is added to the regulator structure, as shown in Fig.
6. The integrator increases the manipulated input voltage
if a current error exists until the error is compensated.
(6)
The integral feedback paths affect the dynamic stiffness
of the closed control loop at low bandwidth, where it adds
a third asymptote to the DS plot. This asymptote can be
identified in (9) and the DS plot in Fig. 7.
⎧
Ki
⎪
⎨ 2πf if f ≤ fi
Udist (jω) Ki
= jωL + Kp + ≈ Kp if fi < f < fp
IL (jω) jω ⎪
⎩
2πf L if f ≥ fp
(9)
534 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Europe digital days 2020, 7 – 8 July 2020



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Fig. 7: Disturbance step response and dynamic stiffness plot of an PI feedback controller assuming Rp = 0.1 Ω and L = 1 mH
Tab. 1: Design of limitation of a PI current regulator
Feedback
Gain Kp,i
Maximal bandwidth fp,i
Kp
fp = and fi =
2πL
The three asymptotes intersect at two points that
represent the proportional and integral state-feedback
bandwidth. Above the proportional state-feedback
bandwidth f > fp , the inductance dominates the DS.
Between the proportional and integral state feedback
bandwidth fi > f > fp , the proportional feedback path
and the resistance Rp , which is neglected in the following,
1 s
Gd (s) ≈ (13)
Proportional Kp Integral Ki L (s + 2πfp ) · (s + 2πfi )
2πfp L 2πfi Kp The approximation of the closed-loop EVs that is derived
fPWM fp
10 5 from (11) to (13) shows that if the fi << fp , the
disturbance response results from the inductance and
the proportional and integral feedback bandwidth. Within
Ki
(10) the discussed limits, these bandwidths fp and fi can
2πKp be selected to design a desired system behavior. The
corresponding disturbance-step response in the time
domain that is derived from (14) to (15) and shown in
Fig. 7 illustrates the asymptotic behavior of the controlled
system that can be manipulated by selection of the
feedback gains. The maximal transient error that results
from a given step excitation can be limited by selecting
an appropriate Kp , whereas the settling time constant τi
can be determined by selecting Ki .
dominate the DS. Below the integral state feedback  
bandwidth f > fi , the integral feedback path dominates udist udist 1 1
IL (s) = Gd (s) = −
the DS. There are two equations that tie the proportional s L(ωP − ωi ) s + ωi s + ωp
and integral feedback bandwidths fp and fi with the udist
iL (t) ≈ (exp (−2πfi t) − exp (−2πfp t)) (14)
inductance L and the proportional and integral feedback Kp

gains Kp and Ki (10). Identifying proportional and udist 1 − exp (−2πfp t) if t < τp
integral state feedback bandwidths allows understanding ≈ · (15)
Kp exp (−2πfi t) if t > τp
the most critical limits in the control design process of the
PI regulator. As discussed in the previous section, the
The discussed limits of the bandwidth fp,i directly
proportional feedback bandwidth must remain at least a
indicate the maximal feasible feedback gains Kp,i and
decade below the PWM frequency. To avoid low damping
consequently the best achievable disturbance response
that occurs if the EVs that are associated with the
in frequency and time domain.
feedback paths form a resonance, the integral bandwidth
must keep a distance of at least half a decade to the
proportional state feedback bandwidth. The maximal 4 Designing Optimized Command
feasible feedback gains that result from this limitation Tracking over High-Bandwidth
can be derived via (10) and are summarized in Tab. 1.
The introduced PI regulator structure and design is
optimized for fast and effective disturbance rejection.
IL (s) 1 s
Gd (s) = = (11) Unfortunately, it exhibits a degraded command tracking
Udist (s) L s2 + Kp s + Ki performance due to substantial current overshoot of
L L

 2
16 %, as it can be seen in the frequency response
Kp Kp Ki ωP ωP ωi
sEV =− ± − =− ± 1−4 function (FRF) and the step response in Fig. 9. The
2L 2L L 2 2 ωP pole-zero plot in Fig. 9 shows that this overshoot is
sEV,1 ≈ −2πfp sEV,2 ≈ −2πfi (12) not a consequence of weakly damped poles, which

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 PCIM Europe digital days 2020, 7 – 8 July 2020

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Fig. 8: State block diagram of the plant, the feedback control and the trajectory filter that applies a reference and a command
feedforward voltage
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optimized for disturbance response with/without low-pass and with trajectory filter and command feedforward

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imaginary axis, which results in a transient overshoot.
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4.1 Mitigating Overshoots of PI Feedback
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There are two options in the state-of-the-art control
design of PI regulators to handle this overshoot. One    
option lies in a reduction of the integral feedback gain )UHTXHQF\LQ+]
Ki and thus, the integral feedback bandwidth fi . This Fig. 10: Experimentally obtained dynamic stiffness plotted
reduces the overshoot during command transients but together with asymptotes that are directly tied to the
also reduces the dynamic stiffness at low bandwidth feedback gains and bandwidths
as well as the settling time during a step disturbance
compensation. A second option is the application of response properties requires identifying the physical
a low-pass filter with one pole at sEV = Ki /Kp that root cause of the overshoot: The integral feedback
compensates the zero of the FRF. This option is the path accumulates any error during transients. After
preferred choice in many control design books, e.g. the current reference changes, it accumulates the
[8], as it does not degrade the disturbance response error between the new reference and the measured
properties of the system. However, the time domain current. If the reference current is reached, the integral
and frequency domain response in Fig. 9 show that this state continuously applies the accumulated voltage and
low pass introduces significant lag and leads to a weak thus causes an over current. During overcurrent, the
command tracking performance. integrator state is reduced until an equilibrium is reached.

4.2 Command Feedforward and Feasible

This paper proposes to use the control topology shown in
Trajectory Generation
Fig. 8 to prevent this overshoot while achieving optimized
An alternative method to achieve high-bandwidth command tracking and disturbance response. It does
command tracking without degrading the disturbance not only apply a current reference to the PI regulator iref
L ,

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Authorized licensed use limited to: University of Minnesota. Downloaded on August 27,2020 at 14:50:56 UTC from IEEE Xplore. Restrictions apply.
 PCIM Europe digital days 2020, 7 – 8 July 2020

 
but additionally applies a command feedforward voltage
ucff that is required to establish the reference current. 
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This voltage can be conceptually computed by inverting

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the open-loop model according to ucff = L · diL /dt. 
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inductor current that is commanded by the reference

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such that the PI regulator does not receive any error 'LPD[
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ΔiL and overshoots do not occur. Thus, the PI regulator v H[SSI W L


only needs to act in the presence of disturbances or 


model deviations. The resulting command tracking FRF
 
for a control loop with command feedforward is shown v H[SSI W S
in Fig. 9. The model inversion ensures that high-  
     
bandwidth command tracking is possible without lag and
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that the command tracking bandwidth is only limited by
Fig. 11: Experimentally obtained disturbance step response
the modulator dynamics M (s), which are not included in
that is directly tied to the feedback gains and
Fig. 9.
bandwidths
However, the concept of command feedforward only
works if a consistent trajectory consisting of a current
reference and a command feedforward voltage are 

applied. This trajectory must not violate system limits, 'L

e.g. the maximal feasible manipulated input voltage 
−uload < ucff < Uin − uload . This imposes a natural LUHI
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limit to the command tracking performance, as the


available voltage limits the maximal diL /dt. Optimized
voltage and current responses that take into account v H[SSI W S

an exemplary voltage limit of 10 V are illustrated in Fig. 

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Fig. 8 provides precisely the fastest references that
are feasible within the voltage limits. It consists of a
low pass that exhibits a model of the plant to generate
consistent voltages and currents. The feedback gain
Kc can be arbitrary chosen up to a Kc = L/Ts , which
realizes deadbeat response. Kc allows limiting the
bandwidth of the trajectory whereas the saturation unit
takes into account the limits of the manipulated input
voltage. The delay of the current reference is essential for
consistency. It ensures that the command feedforward
first realizes the commanded current before the response
is compared to the current reference. This trajectory filter
develops optimized feasible references and enables high
bandwidth command tracking. As it implicitly takes into
account the limits of the plant, there is no need for any
anti-windup schemes of the PI regulator.
5 Experimental Results
The introduced control topology and design have been
experimentally evaluated with a full-bridge converter
and an inductive load with L = 0.5 mH. One converter
half-bridge was operated with the introduced controller,
whereas the second half-bridge was used to apply
disturbance voltages. First, the converter response to
periodic disturbances was experimentally characterized
by applying sinusoidal voltage disturbances at different
frequencies. The magnitude ratio of the excitation
voltage and the current response was plotted in Fig. 10.
ISBN 978-3-8007-5245-4
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Fig. 12: Experimental results of command tracking with
different regulator structures
It nearly exactly matches the underlaid dynamic stiffness
plot that was used for simulations and design and its
asymptotes directly tell what feedback gains have been
used. This underlines that the dynamic stiffness is an
excellent measure not only for frequency domain design
and analysis but also for the control validation. Next,
a disturbance voltage step of 30 V was applied. The
current and voltage response plotted in Fig. 11 show
that the response follows the asymptotes that result from
Kp , fp and fi with good accuracy.
Command tracking has been evaluated in Fig. 12. The
PI regulator design that is optimized for disturbance
rejection, shows the expected overshoot, whereas a PI
regulator with moderate bandwidth shows no overshoot
but a long settling time. The optimized response was
achieved with the control structure shown in Fig. 8
that uses a trajectory filter and command feedforward.
Fig. 13 shows the inductor voltage as well as the PWM
voltage during that transient. As the PWM modulation
applies full voltage during the entire transient, this is
the best command tracking performance that can be
achieved.
537 © VDE VERLAG GMBH · Berlin · Offenbach
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Fig. 13: Experimental results of command tracking using a
trajectory filter with Kc = L/Ts .
6 Conclusions
This work introduces a control topology and design
methodology for current controllers allowing an
independent design of command tracking and
disturbance rejection properties. The design method
combines frequency and time domain analysis to enable
insightful controller design and to take into account the
limits of the modulator and sensor bandwidth. Together
these measures unveil design trade-offs and limitations
to realize an optimized controller for a wide range of
applications.
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