FTS Manual

LAB MANUAL
Fault Tolerant Systems

COURSE CODE: CEN-456
Lab Manual: Fault Tolerant Systems
BAHRIA UNIVERSITY KARACHI CAMPUS

COMPUTER ENGINEERING DEPARTMENT
COURSE TITLE: FAULT TOLERANT SYSTEMS
SN EXPERIMENT TITLES
1 INTRODUCTION TO XILINX WITH RESPECT TO FAULTS, ERRORS & FAILURES
2 FAULT MODELING ON BASIC GATES (AND-OR-NOT)
3 FAULT MODELING USING ADDERS AND DECODERS
4 PERFORMANCE EVALUATIONS (MTTF, MTTR ETC.) OF MULTIPLEXERS AND
DEMULTIPLEXERS
5 APPLYING REDUNDANCY TO COMBINATIONAL & SEQUENTIAL CIRCUITS AND TESTING
THEM
6 APPLYING PATH SENSITIZATION TECHNIQUES ON DIFFERENT CIRCUITS FOR PERMANENT
& TRANSIENT FAULTS
7 TEST PATTERN GENERATION FOR DIFFERENT FAULT MODELS
8 DETECTING & TESTING FAULTS IN 8-BIT ALU & 3 TO 8-BIT DECODER
9 DESIGNING LINEAR FEEDBACK SHIFT REGISTERS (LFSR COUNTERS)
10 IMPLEMENTATION AND TESTING ON MEALY MACHINE & MOORE MACHINE
11 DESIGNING A FAULT DETECTABLE ODD PARITY GENERATOR & PULSE GENERATOR
12 DESIGN OF FAULT DETECTING AND CORRECTING PRIORITY ENCODER & BCD-TO-7
SEGMENT DECODER
13 IMPLEMENTING THE HAMMING CODE AND TESTING IT ON MEALY MACHINE & MOORE
MACHINE
14 DESIGN IMPLICATIONS FAULT MODELS OF MEALY MACHINES
1
Computer Engineering Department
Bahria University (Karachi Campus)
Lab Manual for Fault Tolerant Systems

Lab No. 1
INTRODUCTION TO XILINX WITH RESPECT TO FAULTS,
ERRORS & FAILURES
2
LAB # 01
Introduction to Xilinx With Respect to Faults, Errors & Failures
Objective:
To simulate the AND gate logic through VHDL coding.
Using Xilinx
Create a New Project
Create a new IS project which will target the FPGA device on Spartan-3 start up kit
demo board.
i) Select File –>New Project…. The New Project Wizard appears.
ii) Type Lab1 in the Project Name field.

iii) Enter or Browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically
iv) Verify that HDL is selected from the Top-Level Source Type list.
3
v) Click NEXT to move the device properties page.

vi) Fill in the properties in the table as shown below:
vii) Click NEXT to proceed to create new source window in the New Project Wizard. At
the end of the next section, your new project will be complete.
Create an HDL Source
Create a VHDL source file for the project as follows:
i) Click the New Source button in the New Project Wizard.

ii) Select VHDL Module as the source type.
iii) Type in the file name basicgates.
iv) Verify that the add to project checkbox is selected.
v) Click Next.
4
vi) Declare the ports for the gate design by filling in the port information as shown
below:
vii) Click Next , then Finish in the New Source Wizard – summary dialog box to complete
the New Source file template appears.
5
viii) Click Next , then Next then Finish.
The source file containing the entity/ architecture pair displays in the Workspace,
and the counter displays in the Source tab, as shown below.
The newly created .vhd file has the skeleton code. Add the line Y <= A and B; below
the first begin and the code is complete for AND gate. The complete code is shown
below:
6
Checking the syntax of the New Gate Module
When the source files are complete, check the syntax of the design to find errors and typos.
i) Verify that implementation tab is selected from the Sources Window.

ii) Select the basicgates design source in the Sources Window to display the related
processes in the Processes Window.
iii) Click the ‘+’ next to the Synthesize-XST process to expand the process group.
iv) Double-click the Check Syntax process.
v) Close the HDL file.
7
Verifying Functionality using Behavioural Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
i) Select the basicgates HDL file in the source window.

ii) Create a new test bench source by selecting Project---> New Source.
iii) In the New Source wizard, select VHDL TESTBENCH as a source type and type
basicgates_tbw in the File Name field.
iv) Click Next.
8
v) The associated Source page shows that you are associating the test bench waveform
with the source file basicgates. Click Next.
vi) The summary page shows that the source will be added to the project, and it
displays the source directory, type, and name. Click Finish.
Simulating the design functionality
Verify that the counter design functions as you expect by performing behaviour simulation
as follows:
9
i) Verify that Behavioural Simulation and basicgates_tbw are selected in the Source
Window.
ii) In the Process Window, click the ‘+’ to expand the Xilinx ISim Simulator process and
double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
iii) To view your simulation results, select the Simulation tab.
iv) The simulation waveform results will look like the following.
10
VHDL Program
--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;
--ENTITY DECLARATION: name, inputs, outputs

entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;
--FUNCTIONAL DESCRIPTION: how the AND Gate works

architecture func of andGate is
begin
F <= A and B;
end func;
------------------------------------------------------END
------------------------------------------------------END
Test Bench Code

library ieee;
--ENTITY DECLARATION: no inputs, no outputs

entity andGate_tb is
end andGate_tb;
-- Describe how to test the AND Gate

architecture tb of andGate_tb is
--pass andGate entity to the testbench as component
component andGate is
F : out std_logic);
end component;
signal inA, inB, outF : std_logic;

begin
--map the testbench signals to the ports of the andGate
mapping: andGate port map(inA, inB, outF);
process
--variable to track errors
variable errCnt : integer := 0;
begin
--TEST 1
inA <= '0';
inB <= '0';
wait for 15 ns;
11
assert(outF = '0') report "Error 1" severity error;

if(outF /= '0') then
errCnt := errCnt + 1;
end if;
--TEST 2
inA <= '0';
inB <= '1';
wait for 15 ns;
end if;
--TEST 3
inA <= '1';
inB <= '1';
wait for 15 ns;
end if;
-------------- SUMMARY -------------

if(errCnt = 0) then
assert false report "Good!" severity note;
else
assert true report "Error!" severity error;
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of andGate_tb is
for tb
end for;
end cfg_tb;
---------------------------------------------------------END
---------------------------------------------------------END
12
Objectives/Outcomes
 Understand the Xilinx ISE software.
 Learn to VHDL module for code and testbench.
 Write a basic Xilinx code for AND gate.
Lab Tasks/Practical Work

 Implement another logic gate of your choice on Xilinx ISE.
Time Boxing
Activity Name Activity Time Total Time
Login Systems + Setting up Xilinx ISE 3 mints + 7 mints 10 mints
Walk through Theory & Tasks 60 mints 60 mints
Implement Tasks 80 mints 80 mints
Evaluation Time 30 mints 30 mints
Total Duration 180 mints
Teacher Signature: ________________________
Student Registration No: ________________________
13

Lab No. 2
FAULT MODELING ON BASIC GATES (AND-OR-NOT)
14
LAB # 02
Fault Modelling on Basic Gates (AND-OR-NOT)
Introduction
A logic gate is an idealized or physical device implementing a Boolean function; that is, it
performs a logical operation on one or more binary inputs and produces a single binary output.
Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero
rise time and unlimited fan-out, or it may refer to a non-ideal physical device
Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but
can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic,
pneumatic logic, optics, molecules, or even mechanical elements. With amplification, logic gates can
be cascaded in the same way that Boolean functions can be composed, allowing the construction of
a physical model of all Boolean logic, and therefore, all of the algorithms and mathematics that can
be described with Boolean logic.
And-Gate
The AND gate is a basic digital logic gate that implements logical conjunction - it behaves
according to the truth table shown. A HIGH output (1) results only if all the inputs to the AND gate
are HIGH (1). If none or not all inputs to the AND gate is HIGH, a LOW output results. The function
can be extended to any number of inputs.
INPUT OUTPUT
A B A AND B
0 0 0
0 1 0
1 0 0
1 1 1
VHDL Program
library ieee;

entity andGate is
F : out std_logic);
end andGate;
15
--FUNCTIONAL DESCRIPTION: how the AND Gate works

architecture func of andGate is
begin
F <= A and B;
end func;
------------------------------------------------------END
------------------------------------------------------END
Test Bench Code

library ieee;

entity andGate_tb is
end andGate_tb;
-- Describe how to test the AND Gate

architecture tb of andGate_tb is
--pass andGate entity to the testbench as component
component andGate is
F : out std_logic);
end component;

begin
--map the testbench signals to the ports of the andGate
mapping: andGate port map(inA, inB, outF);
process
begin
--TEST 1
inA <= '0';
inB <= '0';
wait for 15 ns;
end if;
--TEST 2
inA <= '0';
inB <= '1';
wait for 15 ns;
16
end if;
--TEST 3
inA <= '1';
inB <= '1';
wait for 15 ns;
end if;
-------------- SUMMARY -------------

if(errCnt = 0) then
else
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of andGate_tb is
for tb
end for;
end cfg_tb;
---------------------------------------------------------END
---------------------------------------------------------END
Or-Gate
The OR gate is a digital logic gate that implements logical disjunction – it behaves according
to the truth table shown. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1).
If neither input is high, a LOW output (0) results. In another sense, the function of OR effectively finds
the maximum between two binary digits, just as the complementary AND function finds the
minimum.
INPUT OUTPUT
A B A AND B
0 0 0
0 1 1
1 0 1
1 1 1
17
VHDL Program
library ieee;

entity orGate is
F : out std_logic);
end orGate;
--FUNCTIONAL DESCRIPTION: how the OR Gate works

architecture func of orGate is
begin
F <= A or B;
end func;
------------------------------------------------------END
------------------------------------------------------END
Test Bench Code

library ieee;

entity orGate_tb is
end orGate_tb;
-- Describe how to test the OR Gate

architecture tb of orGate_tb is
--pass orGate entity to the testbench as component
component orGate is
F : out std_logic);
end component;

begin
--map the testbench signals to the ports of the orGate
mapping: orGate port map(inA, inB, outF);
process
begin
--TEST 1
inA <= '0';
inB <= '0';
wait for 15 ns;
18

end if;
--TEST 2
inA <= '0';
inB <= '1';
wait for 15 ns;
end if;
--TEST 3
inA <= '1';
inB <= '1';
wait for 15 ns;
end if;
-------------- SUMMARY -------------

if(errCnt = 0) then
else
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of orGate_tb is
for tb
end for;
end cfg_tb;
---------------------------------------------------------END
---------------------------------------------------------END
Not-Gate
In digital logic, an inverter or NOT gate is a logic gate which implements logical negation.
The truth table is shown.
INPUT OUTPUT
A NOT A
0 1
1 0
19
VHDL Program
library ieee;

entity notGate is
port( A : in std_logic;
F : out std_logic);
end notGate;
--FUNCTIONAL DESCRIPTION: how the NOT Gate works

architecture func of notGate is
begin
F <= not A;
end func;
------------------------------------------------------END
------------------------------------------------------END
Test Bench Code

library ieee;

entity notGate_tb is
end notGate_tb;
-- Describe how to test the NOT Gate

architecture tb of notGate_tb is
--pass notGate entity to the testbench as component
component notGate is
port( A : in std_logic;
F : out std_logic);
end component;
signal inA, outF : std_logic;

begin
--map the testbench signals to the ports of the notGate
mapping: notGate port map(inA, outF);
process
begin
--TEST 1
inA <= '0';
20
wait for 15 ns;

end if;
--TEST 2
inA <= '1';
wait for 15 ns;
end if;
-------------- SUMMARY -------------

if(errCnt = 0) then
else
end if;
end process;
end tb;
--------------------------------------------
configuration cfg_tb of notGate_tb is
for tb
end for;
end cfg_tb;
---------------------------------------------------------END
---------------------------------------------------------END
21
Objectives/Outcomes
 Understand logic gates.
 Write basic VHDL codes for implementing gates.
 Simulate each gate and see the result.

 Insert a transient fault into the gates and observe the changes in the output.
Time Boxing
22

Lab No. 3
FAULT MODELING USING ADDERS AND DECODERS
23
LAB # 03
Fault Modelling Using Adders and Decoders
Adders
An adder is a digital circuit that performs addition of numbers. In many computers and other kinds of
processors adders are used in the arithmetic logic units or ALU. They are also utilized in other parts
of the processor, where they are used to calculate addresses, table indices, increment and decrement
operators, and similar operations. Although adders can be constructed for many number
representations, such as binary-coded decimal or excess-3, the most common adders operate on
binary numbers. In cases where two's complement or ones' complement is being used to represent
negative numbers, it is trivial to modify an adder into an adder–subtractor. Other signed number
representations require more logic around the basic adder.
Half Adder
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry
signal represents an overflow into the next digit of a multi-digit addition. The value of the sum in decimal
system is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and
an AND gate for C. The Boolean logic for the sum (in this case S) will be A'B+AB' whereas for carry (C) will
be AB. With the addition of an OR gate to combine their carry outputs, two half adders can be combined
to make a full adder. The half adder adds two input bits and generates a carry and sum, which are the two
outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The
output variables are the sum and carry.
Full Adder
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder
adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit
carried in from the previous less-significant stage. The full adder is usually a component in a cascade
of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output.
24
VHDL Program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;
architecture gate_level of full_adder_vhdl_code is
begin
S <= A XOR B XOR Cin ;

Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;
Test Bench Code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Testbench_full_adder IS
END Testbench_full_adder;
ARCHITECTURE behavior OF Testbench_full_adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT full_adder_vhdl_code
25
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
S : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
--Outputs
signal S : std_logic;
signal Cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: full_adder_vhdl_code PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here

A <= '1';
B <= '0';
Cin <= '0';
wait for 10 ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 10 ns;
A <= '1';
B <= '1';
Cin <= '0';
wait for 10 ns;
A <= '0';
26
B <= '0';
Cin <= '1';
wait for 10 ns;
A <= '1';
B <= '0';
Cin <= '1';
wait for 10 ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 10 ns;
A <= '1';
B <= '1';
Cin <= '1';
wait for 10 ns;
end process;
END;
Decoders
In digital electronics, a binary decoder is a combinational logic circuit that converts binary information
from the n coded inputs to a maximum of 2n unique outputs. They are used in a wide variety of
applications, including data demultiplexing, seven segment displays, and memory address decoding.
There are several types of binary decoders, but in all cases a decoder is an electronic circuit with
multiple input and multiple output signals, which converts every unique combination of input states
to a specific combination of output states. In addition to integer data inputs, some decoders also have
one or more "enable" inputs. When the enable input is negated (disabled), all decoder outputs are
forced to their inactive states.
VHDL Program
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder;
architecture bhv of decoder is
27
begin
process(a)
begin
case a is
when "00" => b <= "0001"; when "01" => b <= "0010"; when "10" => b <= "0100"; when "11" => b <= "1000";
end case;
end process;
end bhv;
Test Bench Code

LIBRARY ieee;
ENTITY tb_decoder IS
END tb_decoder;
ARCHITECTURE behavior OF tb_decoder IS
COMPONENT decoder
PORT(
a : IN std_logic_vector(1 downto 0);
b : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal b : std_logic_vector(3 downto 0);
-- appropriate port name
BEGIN

uut: decoder PORT MAP (
a => a,
b => b
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
a <= "00";
28
wait for 100 ns;
a <= "01";
wait for 100 ns;
a <= "10";
wait for 100 ns;
a <= "11";
wait;
end process;
END;
29
Objectives/Outcomes
 Understand decoders and adders.
 Learn the code for their implementation.
 Observe how faults effect the performance of these devices.

 Investigate how decoders and adders behave under intermittent faults using Xilinx
simulation.
Time Boxing
30

Lab No. 4
PERFORMANCE EVALUATIONS (MTTF, MTTR) OF
MULTIPLEXERS AND DEMULTIPLEXERS
31
LAB # 04
Performance Evaluations (MTTF, MTTR) of Multiplexers and
Demultiplexers
Multiplexer
In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select
lines, which are used to select which input line to send to the output. Multiplexers are mainly used
to increase the amount of data that can be sent over the network within a certain amount of time
and bandwidth. A multiplexer is also called a data selector. Multiplexers can also be used to
implement Boolean functions of multiple variables. An electronic multiplexer makes it possible for
several signals to share one device or resource, for example, one A/D converter or one
communication line, instead of having one device per input signal.
Demultiplexer
A demultiplexer (or demux) is a device taking a single input signal and selecting one of many
data-output-lines, which is connected to the single input. A multiplexer is often used with a
complementary demultiplexer on the receiving end. An electronic multiplexer can be considered as
a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch.
The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side
containing the input pins and the short parallel side containing the output pin. The schematic on the
right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The sel wire
connects the desired input to the output.
VHDL Program
library IEEE;
entity mux_4to1 is
port(
A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;
architecture bhv of mux_4to1 is

begin
process (A,B,C,D,S0,S1) is
32
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
Z <= C;
else
Z <= D;
end if;
end process;
end bhv;
Test Bench Code

LIBRARY ieee;
ENTITY tb_mux IS
END tb_mux;
ARCHITECTURE behavior OF tb_mux IS
COMPONENT mux_4to1
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal S0 : std_logic := '0';
--Outputs
33
signal Z : std_logic;
BEGIN

uut: mux_4to1 PORT MAP (
A => A,
B => B,
C => C,
D => D,
S0 => S0,
S1 => S1,
Z => Z
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
A <= '1';
B <= '0';
C <= '1';
D <= '0';
S0 <= '0'; S1 <= '0';
wait for 100 ns;
S0 <= '1'; S1 <= '0';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;
end process;
END;
34
Objectives/Outcomes
 Studying the multiplexers and demultiplexers.
 Understanding the VHDL coding for MUX and DEMUX.

 Insert transient faults in a MUX or DEMUX by adding delays and observe the changes.
Time Boxing
35

Lab No. 5
APPLYING REDUNDANCY TO COMBINATIONAL &
SEQUENTIAL CIRCUITS AND TESTING
36
LAB # 05
Applying Redundancy to Combinational & Sequential Circuits and
Testing
Description
Redundancy occurs in a digital gate network containing circuitry that does not affect the static
logic function. There are several reasons why logic redundancy may exist. One reason is that it may
have been added deliberately to suppress transient glitches (thus causing a race condition) in the
output signals by having two or more product terms overlap with a third one.
Another reason for logic redundancy is poor design practices which unintentionally result in logically
redundantly terms. This causes an unnecessary increase in network complexity, and possibly
hampering the ability to test manufactured designs using traditional test methods (single stuck-at
fault models).
VHDL Program
library IEEE;
entity demux_1to4 is
port(
F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end demux_1to4;
architecture bhv of demux_1to4 is

begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
B <= F;
C <= F;
else
D <= F;
end if;
end process;
37
end bhv;
Test Bench Code

LIBRARY ieee;
ENTITY tb_demux IS
END tb_demux;
ARCHITECTURE behavior OF tb_demux IS
COMPONENT demux_1to4
PORT(
F : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
A : OUT std_logic;
B : OUT std_logic;
C : OUT std_logic;
D : OUT std_logic
);
END COMPONENT;
--Inputs
signal F : std_logic := '0';
--Outputs
signal A : std_logic;
signal B : std_logic;
signal C : std_logic;
signal D : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN

uut: demux_1to4 PORT MAP (
F => F,
S0 => S0,
S1 => S1,
A => A,
B => B,
C => C,
38
D => D
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
F <= '1';
S0 <= '0'; S1 <= '0';
wait for 100 ns;
S0 <= '1'; S1 <= '0';
wait for 100 ns;
S0 <= '0'; S1 <= '1';
wait for 100 ns;
S0 <= '1'; S1 <= '1';
wait for 100 ns;

-- insert stimulus here
wait;
end process;
END;
39
Objectives/Outcomes
 Studying the PIR HC-SR-501 sensor.
 Learning about the pins, modes, sensitivity controls.
 Understanding the detecting mechanism.

 Write a code that will light an LED connected to a GPIO pin when an object is detected by
the PIR sensor.
Time Boxing
40

Lab No. 6
APPLYING PATH SENSITIZATION TECHNIQUES ON
DIFFERENT CIRCUITS FOR PERMANENT & TRANSIENT
FAULTS
41
LAB # 06
Applying Path Sensitization Techniques on Different Circuits for
Permanent & Transient Faults
Parallel Adder
A single full adder performs the addition of two 1-bit numbers and an input carry. But a
Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary numbers that is
greater than one bit in length by operating on corresponding pairs of bits in parallel. It consists of full
adders connected in a chain where the output carry from each full adder is connected to the carry
input of the next higher order full adder in the chain. A n bit parallel adder requires n full adders to
perform the operation. So, for the two-bit number, two adders are needed while for 4-bit number,
four adders are needed and so on. Parallel adders normally incorporate carry lookahead logic to
ensure that carry propagation between subsequent stages of addition does not limit addition speed.
VHDL Program
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
42
entity pa1 is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
c : out std_logic;
cin : in std_logic);
end pa1;
architecture pa11 of pa1 is
begin
process(a,b,cin)
variable u:std_logic;
begin
u:=cin;
for i in 0 to 3 loop
s(i)<=a(i) xor b(i) xor u;
u:=(a(i) and b(i))or(b(i) and u) or(u and a(i));
end loop;
c<=u;
end process;
end pa11;
Universal Gates
A universal gate is a gate which can implement any Boolean function without need to use any other
gate type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND
and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital
logic families. In fact, an AND gate is typically implemented as a NAND gate followed by an inverter
not the other way around. Likewise, an OR gate is typically implemented as a NOR gate followed by
an inverter not the other way around.
43
Objectives/Outcomes
 Studying the parallel adders and universal gates.
 Understanding about the sequential combination of adders.
 Learning how it can be programmed.

 Implement path sensitization on a 4-bit parallel adder.
Time Boxing
44

Lab No. 7
TEST PATTERN GENERATION FOR DIFFERENT FAULT
MODELS
45
LAB # 07
Test Pattern Generation for Different Fault Models
Description
A fault model is an engineering model of something that could go wrong in the construction
or operation of a piece of equipment. From the model, the designer or user can then predict the
consequences of this fault. Fault models can be used in almost all branches of engineering. Basic fault
models include:
 stuck-at fault
 bridging fault
 transistor faults
 open fault
 delay fault.
Finite State Machine (FSM)

A finite-state machine (FSM) or finite-state automaton, finite automaton, or simply a state machine,
is a mathematical model of computation. It is an abstract machine that can be in exactly one of a
finite number of states at any given time. The FSM can change from one state to another in response
to some external inputs; the change from one state to another is called a transition. An FSM is defined
by a list of its states, its initial state, and the conditions for each transition. Finite state machines are
of two types deterministic finite state machines and non-deterministic finite state machines. A
deterministic finite-state machine can be constructed equivalent to any non-deterministic one.
VHDL Program
-- Architecture definition for the SimpleFSM entity
Architecture RTL of SimpleFSM is
TYPE State_type IS (A, B, C, D); -- Define the states
SIGNAL State : State_Type; -- Create a signal that uses
-- the different states
BEGIN
PROCESS (clock, reset)
BEGIN
If (reset = ‘1’) THEN -- Upon reset, set the state to A
State <= A;
ELSIF rising_edge(clock) THEN -- if there is a rising edge of the

-- clock, then do the stuff below
-- The CASE statement checks the value of the State variable,

-- and based on the value and any other control signals, changes
46
-- to a new state.
CASE State IS
-- If the current state is A and P is set to 1, then the

-- next state is B
WHEN A =>
IF P='1' THEN
State <= B;
END IF;
-- If the current state is B and P is set to 1, then the

-- next state is C
WHEN B =>
IF P='1' THEN
State <= C;
END IF;
-- If the current state is C and P is set to 1, then the

-- next state is D
WHEN C =>
IF P='1' THEN
State <= D;
END IF;
-- If the current state is D and P is set to 1, then the

-- next state is B.
-- If the current state is D and P is set to 0, then the
-- next state is A.
WHEN D=>
IF P='1' THEN
State <= B;
ELSE
State <= A;
END IF;
WHEN others =>
State <= A;
END CASE;
END IF;
END PROCESS;
-- Decode the current state to create the output

-- if the current state is D, R is 1 otherwise R is 0
R <= ‘1’ WHEN State=D ELSE ‘0’;
END rtl;
47
Objectives/Outcomes
 Studying the Finite State Machines.
 Understanding how to code and implement.

 Investigate different fault models using FSMs.
Time Boxing
48

Lab No. 8
DETECTING & TESTING FAULTS IN 8-BIT ALU & 3 TO 8-
BIT DECODER
49
LAB # 08
Detecting & Testing Faults In 8-Bit ALU & 3 To 8-Bit Decoder
Arithmetic Logic Unit (ALU)

An arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs
arithmetic and bitwise operations on integer binary numbers. This contrasts with a floating-point unit
(FPU), which operates on floating point numbers. An ALU is a fundamental building block of many
types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and
graphics processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs. The inputs to
an ALU are the data to be operated on, called operands, and a code indicating the operation to be
performed; the ALU's output is the result of the performed operation. In many designs, the ALU also
has status inputs or outputs, or both, which convey information about a previous operation or the
current operation, respectively, between the ALU and external status registers.
VHDL Program
library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
entity ALU is
generic (
constant N: natural := 1 -- number of shited or rotated bits
);
Port (
A, B : in STD_LOGIC_VECTOR(7 downto 0); -- 2 inputs 8-bit
ALU_Sel : in STD_LOGIC_VECTOR(3 downto 0); -- 1 input 4-bit for selecting function
ALU_Out : out STD_LOGIC_VECTOR(7 downto 0); -- 1 output 8-bit
Carryout : out std_logic -- Carryout flag
);
end ALU;
50
architecture Behavioral of ALU is
signal ALU_Result : std_logic_vector (7 downto 0);
signal tmp: std_logic_vector (8 downto 0);
begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "0000" => -- Addition
ALU_Result <= A + B ;
when "0001" => -- Subtraction
ALU_Result <= A - B ;
when "0010" => -- Multiplication
ALU_Result <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) * to_integer(unsigned(B))),8)) ;
when "0011" => -- Division
ALU_Result <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8)) ;
when "0100" => -- Logical shift left
ALU_Result <= std_logic_vector(unsigned(A) sll N);
when "0101" => -- Logical shift right
ALU_Result <= std_logic_vector(unsigned(A) srl N);
when "0110" => -- Rotate left
ALU_Result <= std_logic_vector(unsigned(A) rol N);
when "0111" => -- Rotate right
ALU_Result <= std_logic_vector(unsigned(A) ror N);
when "1000" => -- Logical and
ALU_Result <= A and B;
when "1001" => -- Logical or
ALU_Result <= A or B;
when "1010" => -- Logical xor
51
ALU_Result <= A xor B;
when "1011" => -- Logical nor
ALU_Result <= A nor B;
when "1100" => -- Logical nand
ALU_Result <= A nand B;
when "1101" => -- Logical xnor
ALU_Result <= A xnor B;
when "1110" => -- Greater comparison
if(A>B) then
ALU_Result <= x"01" ;
else
end if;
when "1111" => -- Equal comparison
if(A=B) then
else
end if;
when others => ALU_Result <= A + B ;
end case;
end process;
ALU_Out <= ALU_Result; -- ALU out
tmp <= ('0' & A) + ('0' & B);
Carryout <= tmp(8); -- Carryout flag
end Behavioral;
52
Test Bench Code

LIBRARY ieee;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_ALU IS
END tb_ALU;
ARCHITECTURE behavior OF tb_ALU IS
COMPONENT ALU
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
ALU_Sel : IN std_logic_vector(3 downto 0);
ALU_Out : OUT std_logic_vector(7 downto 0);
Carryout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal ALU_Sel : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal ALU_Out : std_logic_vector(7 downto 0);
53
signal Carryout : std_logic;
signal i:integer;
BEGIN
uut: ALU PORT MAP (
A => A,
B => B,
ALU_Sel => ALU_Sel,
ALU_Out => ALU_Out,
Carryout => Carryout
);
-- Stimulus process
stim_proc: process
begin
A <= x"0A";
B <= x"02";
ALU_Sel <= x"0";
for i in 0 to 15 loop
ALU_Sel <= ALU_Sel + x"1";
wait for 100 ns;
end loop;
A <= x"F6";
B <= x"0A";
wait;
end process;
END;
54
Objectives/Outcomes
 Studying the 8-bit ALU.
 Understanding about how it works and processes data.
 Learning how to code a ALU and a decoder.

 Test the 8-bit ALU for stutter faults.
Time Boxing
55

Lab No. 9
DESIGNING LINEAR FEEDBACK SHIFT REGISTERS (LFSR
COUNTERS)
56
LAB # 09
Designing Linear Feedback Shift Registers (LFSR Counters)
Introduction
A linear feedback shift register takes a linear function, typically an exclusive OR, as an input. An LSFR,
like other shift registers, is a cascade of flip-flop circuits. The bits that change state for the others in
the cascade are called taps. Two of the major schemes for connecting taps are Fibonacci and Galois.
In the Fibonacci configuration, the taps are cascaded and fed into the leftmost bit. In a Galois
configuration, named after the French mathematician Évariste Galois, each tap is XOR'd to the output
stream. LSFRs are used in cryptography for pseudo-random number generation, pseudo-noise
sequences and whitening sequences. They are also often used for digital counters because they are
so fast.
VHDL Program
library IEEE;
entity lfsr is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
outp : out STD_LOGIC_VECTOR (3 downto 0));
end lfsr;
architecture Behavioral of lfsr is
signal feedback : std_logic;
signal out_reg : std_logic_vector(3 downto 0):="0000";
begin
feedback <= not (out_reg(3) xor out_reg(2));
57
process (clk,rst)
begin
if (rst='1') then
out_reg <= "0000";
elsif (rising_edge(clk)) then
out_reg <= out_reg(2 downto 0) & feedback;
end if;
end process;
outp <= out_reg;
end Behavioral;
Test Bench Code

library IEEE;
entity lfsr_tb is
-- Port ( );
end lfsr_tb;
architecture Behavioral of lfsr_tb is

signal clk_tb : std_logic := '1';
signal rst_tb : std_logic;
signal outp_tb : std_logic_vector(3 downto 0);
constant clk_period : time := 10 ns;
component lfsr is
rst : in STD_LOGIC;
outp : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
process
begin
clk_tb <= not clk_tb;
wait for clk_period/2;
end process;
process
58
begin
rst_tb <= '1';
wait for 6 ns;
rst_tb <= '0';

wait for 200 ns;
end process;
DUT : lfsr port map (clk_tb,rst_tb,outp_tb);
end Behavioral;
59
Objectives/Outcomes
 Studying the force and load sensors.
 Learning about how force changes the resistance of the sensors.
 Basic python coding for the sensor.

 Write a code that will measure the weight of an object using force and load sensors.
Time Boxing
60

Lab No. 10
IMPLEMENTATION AND TESTING ON MEALY
MACHINE & MOORE MACHINE
61
LAB # 10
Implementation and Testing on Mealy Machine & Moore Machine
Mealy Machine
In the theory of computation, a Mealy machine is a finite-state machine whose output values
are determined both by its current state and the current inputs. A Mealy machine is a deterministic
finite-state transducer: for each state and input, at most one transition is possible.
Moore Machine
A Moore machine is a finite-state machine whose output values are determined only by its
current state.
VHDL Program
library IEEE;
entity moore is
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end moore;
architecture Behavioral of moore is
type state is (st0, st1, st2, st3);
signal present_state, next_state : state;
begin
62
synchronous_process: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
output_decoder : process(present_state, din)
begin
next_state <= st0; case (present_state) is when st0 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0; end if; when st1 =>
if (din = '1') then
next_state <= st1;
else
if (din = '1') then
next_state <= st3;
else
if (din = '1') then
next_state <= st1;
else
63
next_state <= st2; end if; when others =>
next_state <= st0; end case; end process; next_state_decoder : process(present_state) begin case (present_state)
is when st0 =>
dout <= '0'; when st1 =>
dout <= '1'; when others =>
dout <= '0';
end case;
end process;
end Behavioral;
Test Bench Code

LIBRARY ieee;
ENTITY tb_moore IS
END tb_moore;
ARCHITECTURE behavior OF tb_moore IS
COMPONENT moore
PORT(
clk : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal din : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal dout : std_logic;
64
-- Clock period definitions

constant clk_period : time := 20 ns;
BEGIN

uut: moore PORT MAP (
clk => clk,
din => din,
rst => rst,
dout => dout
);
-- Clock process definitions

clk_process :process
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
65
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';

end process;
END;
66
Objectives/Outcomes
 Studying the GSM-900A module.
 Learning about Arduino and its interfacing.
 Understanding how to send and receive SMS.

 Write a code that will receive messages from GSM module and Arduino.
Time Boxing
67

Lab No. 11
DESIGNING A FAULT DETECTABLE ODD PARITY
GENERATOR & PULSE GENERATOR
68
LAB # 11
Designing a Fault Detectable Odd Parity Generator & Pulse Generator
Odd Parity Generator
In asynchronous communication systems, odd parity refers to parity checking modes, where
each set of transmitted bits has an odd number of bits. If the total number of ones in the data plus
the parity bit is an odd number of ones, it is called odd parity. A system that generates odd parity is
called an Odd Parity Generator.
Pulse Generator
A pulse generator is either an electronic circuit or a piece of electronic test equipment used
to generate rectangular pulses. Pulse generators are used primarily for working with digital circuits,
related function generators are used primarily for analog circuits.
VHDL Program
package anu is
constant m: integer :=8;
type input is array (0 to m-1) of bit;
end anu;
library ieee;
use ieee.std_logic_1164.all ;
use Work.anu.all;
entity Parity_Generator1 is
port ( input_stream : in input;
clk : in std_logic ;
parity :out bit );
end Parity_Generator1;
69
architecture odd of Parity_Generator1 is
begin
P1: process
variable odd : bit ;
begin
wait until clk'event and clk = '1';
odd := '0';
for I in 0 to m-1 loop
odd := odd xor input_stream (I);
end loop;
parity <= odd;
end process;
end odd;
Test Bench Code

entity ODD_PARITY_TB is
end;
library ieee;
use WORK.anu.all;
architecture OP_TB_ARCH of ODD_PARITY_TB is
component Parity_Generator1
port (input_stream : in input;
clk : in std_logic;
parity : out bit );
end component;
signal input_stream : input;
signal clk :std_logic;
signal parity :bit ;
begin
U1: Parity_Generator1
port map(
input_stream,
clk,
parity => parity
);
input1 : process (clk)
begin
if clk <= 'U' then clk <= '0' after 1 ns;
70
else clk <= not clk after 1 ns;

end if;
end process;
input2: process (input_stream)
begin
input_stream <= "10100110" after 1 ns,
"01111100" after 2 ns;
end process;
end OP_TB_ARCH;
configuration cfg_op of ODD_PARITY_TB is
for OP_TB_ARCH
end for;
end cfg_op;
71
Objectives/Outcomes
 Studying the Parity and Pulse Generator.
 Understanding about its working and specifications.
 Learning how to code an odd parity generator.

 Write a code that will implement a pulse generator.
Time Boxing
72

Lab No. 12
DESIGN OF FAULT DETECTING AND CORRECTING
PRIORITY ENCODER & BCD-TO-7 SEGMENT DECODER
73
LAB # 12
Design of Fault Detecting and Correcting Priority Encoder
Priority Encoder
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a
smaller number of outputs. The output of a priority encoder is the binary representation of the
original number starting from zero of the most significant input bit. They are often used to control
interrupt requests by acting on the highest priority encoder. If two or more inputs are given at the
same time, the input having the highest priority will take precedence. An example of a single bit 4 to
2 encoder is shown, where highest-priority inputs are to the left and "x" indicates an irrelevant value
- i.e. any input value there yields the same output since it is superseded by higher-priority input. The
output V indicates if the input is valid.
Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-
to-4 encoder made from six 4-to-2 priority encoders - four 4-to-2 encoders having the signal source
connected to their inputs, and the two remaining encoders take the output of the first four as input.
The priority encoder is an improvement on a simple encoder circuit, in terms of handling all possible
input configurations.
VHDL Program
entity priority is
port (I : in bit_vector(7 downto 0); --inputs to be prioritised
A : out bit_vector(2 downto 0); --encoded output
GS : out bit); --group signal output
end priority;
architecture v1 of priority is
begin
process (I)
begin
GS <= '1'; --set default outputs
A <= "000";
if I(7) = '1' then
A <= "111";
elsif I(6) = '1' then

74
A <= "110";
A <= "101";
A <= "100";
A <= "011";
A <= "010";
A <= "001";
A <= "000";
else
GS <= '0';
end if;
end process;
end v1;
Test Bench Code

library ieee;
entity enco8x3_seq_tst is
end enco8x3_seq_tst;
architecture beh of enco8x3_seq_tst is
component enco8x3_seq
port (
i: in std_logic_vector(7 downto 0); -- inputs
o: out std_logic_vector(2 downto 0)); -- outputs
end component;
signal i_s : std_logic_vector(7 downto 0); -- signals
signal o_s : std_logic_vector(2 downto 0); -- output signals
75
begin -- beh
u1 : enco8x3_seq port map (

i => i_s,
o => o_s);
tst_p: process
begin
i_s<="00000001";
wait for 100 ns;
i_s<="00000010";
wait for 100 ns;
i_s<="00000100";
wait for 100 ns;
i_s<="00001000";
wait for 100 ns;
i_s<="00010000";
wait for 100 ns;
i_s<="00100000";
wait for 100 ns;
i_s<="01000000";
wait for 100 ns;
i_s<="10000000";
wait for 100 ns;
end process;
end beh;
76
Objectives/Outcomes
 Studying the priority encoder.
 Understanding its functions.
 Learning how to code a priority encoder in VHDL.

 Write a code to design a fault detecting BCD to 7-segment decoder.
Time Boxing
77

Lab No. 13
IMPLEMENTING THE HAMMING CODE AND TESTING
IT ON MEALY MACHINE & MOORE MACHINE
78
LAB # 13
Implementing the Hamming Code and Testing It on Mealy Machine &
Moore Machine
Hamming Code
Hamming codes are a family of linear error-correcting codes. Hamming codes can detect up
to two-bit errors or correct one-bit errors without detection of uncorrected errors. By contrast, the
simple parity code cannot correct errors, and can detect only an odd number of bits in error.
Hamming codes are perfect codes, that is, they achieve the highest possible rate for codes with their
block length and minimum distance of three. Richard Hamming invented Hamming codes in 1950 as
a way of automatically correcting errors introduced by punched card readers. In his original paper,
Hamming elaborated his general idea, but specifically focused on the Hamming (7,4) code which adds
three parity bits to four bits of data.
VHDL Program
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY hamming_encoder IS
PORT(datain : IN BIT_VECTOR(0 TO 3); --d0 d1 d2 d3
hamout : OUT BIT_VECTOR(0 TO 6)); --d0 d1 d2 d3 p0 p1 p2
END hamming_encoder;
ARCHITECTURE beh OF hamming_encoder IS
SIGNAL p0, p1, p2 : BIT; --check bits
BEGIN
--generate check bits
p0 <= (datain(0) XOR datain(1)) XOR datain(3);
79
--connect up outputs
hamout(4 TO 6) <= (p0, p1, p2);
hamout(0 TO 3) <= datain(0 TO 3);
END beh;
80
Objectives/Outcomes
 Studying the Hamming codes.
 Understanding its operation and fault correcting ability.
 Learning how to implement Hamming codes on VHDL.

 Write a code to implement Hamming codes on a Moore Machine.
Time Boxing
81

Lab No. 14
DESIGN IMPLICATIONS FAULT MODELS OF MEALY
MACHINES
82
LAB # 14
Design Implication Fault Models of Mealy Machines
Mealy Machine
A Mealy Machine is an FSM whose output depends on the present state as well as the
present input.
It can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where:
 Q is a finite set of states.

 ∑ is a finite set of symbols, called the input alphabet.
 O is a finite set of symbols, called the output alphabet.
 δ is the input transition function where δ: Q × ∑ → Q
 X is the output transition function where X: Q × ∑ → O
 q0 is the initial state from where any input is processed (q0 ∈ Q).
VHDL Program
-- A Mealy machine has outputs that depend on both the state and
-- the inputs. When the inputs change, the outputs are updated
-- immediately, without waiting for a clock edge. The outputs
-- can be written more than once per state or per clock cycle.
library ieee;
entity mealy_4s is
port
clk : in std_logic;
data_in : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(1 downto 0)
);
83
end entity;
architecture rtl of mealy_4s is
-- Build an enumerated type for the state machine
type state_type is (s0, s1, s2, s3);
-- Register to hold the current state
signal state : state_type;
begin
process (clk, reset)
begin
if reset = '1' then
state <= s0;
elsif (rising_edge(clk)) then
-- Determine the next state synchronously, based on
-- the current state and the input
case state is
when s0=>
if data_in = '1' then
state <= s1;
else
state <= s0;
end if;
when s1=>
state <= s2;
else
84
state <= s1;
end if;
when s2=>
state <= s3;
else
state <= s2;
end if;
when s3=>
state <= s3;
else
state <= s1;
end if;
end case;
end if;
end process;
-- Determine the output based only on the current state
-- and the input (do not wait for a clock edge).
process (state, data_in)
begin
case state is
when s0=>
data_out <= "00";
else
data_out <= "01";
end if;
85
when s1=>
data_out <= "01";
else
data_out <= "11";
end if;
when s2=>
data_out <= "10";
else
data_out <= "10";
end if;
when s3=>
data_out <= "11";
else
data_out <= "10";
end if;
end case;
end process;
end rtl;
86
Objectives/Outcomes
 Studying the fault models of Mealy Machine.
 Learning how to work on FSMs and Mealy Machines together.

 Write a code that will implement a Mealy Machine for a different fault model.
Time Boxing
87

FTS Manual

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FTS Manual

Uploaded by

Copyright:

Available Formats

LAB MANUAL

Fault Tolerant Systems

BAHRIA UNIVERSITY KARACHI CAMPUS

COURSE TITLE: FAULT TOLERANT SYSTEMS

Lab Manual for Fault Tolerant Systems

ii) Type Lab1 in the Project Name field.

v) Click NEXT to move the device properties page.

Create an HDL Source

Create a VHDL source file for the project as follows:

i) Click the New Source button in the New Project Wizard.

viii) Click Next , then Next then Finish.

Checking the syntax of the New Gate Module

i) Verify that implementation tab is selected from the Sources Window.

Verifying Functionality using Behavioural Simulation

i) Select the basicgates HDL file in the source window.

Simulating the design functionality

--ENTITY DECLARATION: name, inputs, outputs

--FUNCTIONAL DESCRIPTION: how the AND Gate works

Test Bench Code

--ENTITY DECLARATION: no inputs, no outputs

-- Describe how to test the AND Gate

signal inA, inB, outF : std_logic;

assert(outF = '0') report "Error 1" severity error;

-------------- SUMMARY -------------

Lab Tasks/Practical Work

Teacher Signature: ________________________

Student Registration No: ________________________

Lab Manual for Fault Tolerant Systems

--ENTITY DECLARATION: name, inputs, outputs

--FUNCTIONAL DESCRIPTION: how the AND Gate works

Test Bench Code

--ENTITY DECLARATION: no inputs, no outputs

-- Describe how to test the AND Gate

signal inA, inB, outF : std_logic;

-------------- SUMMARY -------------

--ENTITY DECLARATION: name, inputs, outputs

--FUNCTIONAL DESCRIPTION: how the OR Gate works

Test Bench Code

--ENTITY DECLARATION: no inputs, no outputs

-- Describe how to test the OR Gate

signal inA, inB, outF : std_logic;

assert(outF = '0') report "Error 1" severity error;

-------------- SUMMARY -------------

--ENTITY DECLARATION: name, inputs, outputs

--FUNCTIONAL DESCRIPTION: how the NOT Gate works

Test Bench Code

--ENTITY DECLARATION: no inputs, no outputs

-- Describe how to test the NOT Gate

signal inA, outF : std_logic;

wait for 15 ns;

-------------- SUMMARY -------------

Lab Tasks/Practical Work

Teacher Signature: ________________________

Student Registration No: ________________________

Lab Manual for Fault Tolerant Systems

architecture gate_level of full_adder_vhdl_code is

S <= A XOR B XOR Cin ;

Test Bench Code

ARCHITECTURE behavior OF Testbench_full_adder IS

-- Component Declaration for the Unit Under Test (UUT)

-- Instantiate the Unit Under Test (UUT)

-- insert stimulus here

Test Bench Code