QuestaSim Workshop

11th September,2015
 Mentor Graphics Enterprise Verification Platform
Investing in Smarter, Stronger, & Faster Verification

 Smarter
Management
 Stimulus Stimulus
& Analysis
Debug

 Metrics
 Debug

 Stronger Verification Infrastructure

 Environment
 Infrastructure

 Faster
Virtual FPGA
 Verification Prototype
Formal Simulation Emulation
Prototype
Engines
 Functional Simulation Solutions
Mentor Graphics
 ModelSim PE -HDL Simulation + code coverage (W,32)

 ModelSim DE -Above + FSM, ABV (WL, 32-64)

 QuestaSim Core -Above + Opti. + Schematic + Multicore (WL, 32-64)

 QuestaSim Prime -Above + SV + OVM + UVM + F. Coverage (WL, 32-64)

 QuestaSim Ultra -Above + Power Aware + Infact Auto TB (WL, 32-64)

 Questa ADMS -Analog mixed Simulation (L, 32-64)

 Questa CodeLink -Processor + RTL Debugging (L, 32-64)

 Questa Formal -Formal checks and Coverage (L, 32-64)

 Questa CDC -CDC Analysis (L, 32-64)

 Questa INFACT -Automated TB for Code + F. Coverage (L, 32-64)

 Questa VIP -UVM based Verification IP solution (L, 32-64)

 Veloce Emulators -Emulation solution (L, 32-64)

 AGENDA

 Module-1 -- Introduction to QuestaSim.

 Module-2 -- Advanced Debugging Features.

 Module-3 -- Introduction to Code-Coverage.

 Module-4 -- Introduction to Assertion Based Verification.

 Module-5 – Advance Verification Questa Support.

 Module -1

 Introduction to QuestaSim

 Language/Standards Support.

 Basic Flow of Working with Questa.

 Questa GUI.
 Core Simulation Technology

 Single kernel, mixed-language with best Native

Support for Standards for Highest Performance
 VHDL 1987/1993/2002/2008

 Verilog 1995/2001, SystemVerilog 2005/2009/2012

 SystemC

 Standard Delay Format (SDF)

 Property Specification Language (PSL)

 SystemVerilog Assertions
 Core Simulation Technology

 Most Comprehensive Support of

Methodologies for Increased Verification
Productivity
 Assertion-Based Verification

 OVM/UVM Supported

 Coverage-Driven Verification

 Verification Management

Functional
Coverage
 Hierarchies Supported
 Single simulation kernel provides total freedom to intermix
VHDL and Verilog design units.
 You cannot place Verilog code constructs inside of VHDL code or
vice versa.
 Requires no additional effort from the designer.

library IEEE; module fee (x, y, z);

VHDL
use IEEE.std_logic_1164.ALL;

Verilog
input x, y;
entity foo is
port (a: in std_logic; output z;
b: in std_logic; wire temp_wire;
c. out std_logic; initial begin
end; temp_wire = 1;

library IEEE;
module fee (x, y, z); use IEEE.std_logic_1164.ALL;

Verilog VHDL
input x, y; entity foo is
output z; port (a: in std_logic;
wire temp_wire; b: in std_logic;
initial begin c. out std_logic;
end;
temp_wire = 1;

library IEEE; module fee (x, y, z);

use IEEE.std_logic_1164.ALL;

VHDL Verilog
input x, y;
entity foo is
port (a: in std_logic; output z;
b: in std_logic; wire temp_wire;
c. out std_logic; initial begin
end; temp_wire = 1;
Design flow with Questa
 Execution Methods
 Graphic User Interface (GUI).
 Can accept menu input and interactive.
 Command line input via transcript window.
 Interactive Command Line Interface (CLI).
 Only interface is a command line console, no Graphical User
Interface.
 Invoke vsim with -c switch.
 Batch Mode.
 Run batch files from DOS or UNIX/Linux prompt.
 Driven from a TCL script “do file” or additional command line
switches.
vsim –c <other switches> -do “log /*; run –all; quit –f”
 Run batch mode for performance, after debugging the design.
 Change the Working Directory
 Before compiling or simulating the design, change the working
directory.
 GUI: File > Change Directory
 Command: cd ../modelsim_labs/modsim_lab1
 Create a New Library
 Create and map the design library:
 GUI: In the Library window, click the right mouse button (RMB),
and select New > Library from the popup menu.
 Command: vlib lib
 vmap work lib
 Compiler Options
 Set global compiler options:
 GUI: Compile > Compile Options
 Command: Various vcom and vlog compiler switches.
– Example: vcom -93 top_level.vhd
 Compile the Design Files
 Compile the design files:
 GUI: Compile > Compile
– Select source files to compile.
– Specify target library for compiled design units.
 Compile button on toolbar.
 Command: vcom or vlog

Set or change compiler options by

clicking the Default Options button.
 Simulation Options
 Set Simulation Options:
 GUI: Simulate > Runtime Options
 Designating a Design to Simulate
 Load and simulate your design:
 GUI: Simulate > Start Simulation > Design tab.
– Expand the work library, select the design to simulate, and click OK.
– May set additional simulation options from this window.
 Command: vsim <design_name>

Set other “Simulate”

options from these tabs.
 Designating a Design to Simulate (Cont.)
 Other methods to load the design for
simulation:
 Double-click on the design unit or
configuration in the Library window.
– Use when you want to do a quick load
with no options.
 Click the RMB on the design unit in
the Library window and select:
– Simulate
– Simulate with Coverage
 Running a Simulation
 There are several ways to run a simulation:
 GUI: Simulate > Run > <Run Options>
 Select one of the Run buttons on the toolbar.
 Command: run <Run Options> Break
– Example: run -all
run -all stop -sync

restart run run -continue

 Restarting the Simulation
 Easy way to reload the design and reset the simulation.
 GUI: Click the Restart button from the Main or Wave window.
 Command: restart
 Commands for Basic Simulation Steps
 Steps to run a basic simulation in Command-Line mode:

1. Change directories to your working directory.

At the command prompt, type:
cd ../projects/my_design

2. Create a working library.

vlib work

3. Define a mapping between a logical library name and a directory.

vmap work work

4. Compile the files in your design.

vcom counter.vhd proc.vhd mem.vhd cpu.vhd top.vhd top_tb.vhd
vlog counter.v proc.v mem.v cpu.v top.v top_tb.v
 Basic Simulation Steps (Cont.)

5. Invoke vsim, the simulator, in command-line mode (-c).

Save the contents of the transcript (-l) to filename result.log.
vsim –c top_tb –l result.log –wlf result.wlf

6. After the design has loaded, run the simulation.

 add log –r /*
 run 500 ns
 quit –f
Questa GUI
 Main Window
 Initial window upon startup
 Displays Library and Transcript windows by default
 Additional windows opened within the Main window

Library window

Transcript window
 Main Window With Design Loaded
Menus and toolbar buttons provide quick
access to simulation commands and functions.

Debug
Windows
Design
Navigation

Command Line Interface

 Basic Window Operations

Windows:
• Placed in any position
• Can be grouped with any
other window
Zoom,
Undock
Drag Handle & Close
buttons
Tab
Groups
 Drag and Drop Feature
 Select HDL items in
one window, drag
and drop into
another window.
 Drag HDL items
from the List,
Locals, Memories,
Objects, Processes, Hold down the left mouse mutton (LMB) to
Source, Structure Drag and Drop from one window to another.

and Wave windows.

 Drop into either the
Dataflow, List,
Schematic, Watch, Use Drag and Drop to rearrange items
or Wave windows. in the Wave and List windows, too.
 Library and Structure Windows

The Structure (sim) window displays the

hierarchy for the design being simulated.

Displays the compiled

design unit name, type,
and source code path.
Files Windows

Displays the source files

for the loaded design.
 Memory Viewer

 The memory viewer (window) is actually two window

 List Window
 Data Window
All memories with
their dimensions –
double click to open
in data window

Address of
data in first
column
 Data Viewer Display Properties

 RMB click in the data window to get the properties dialog

Change radix of
address and/or data

Adjust the number of

columns in the display
 Initializing & Changing Memory Contents

 There are several ways to change memory contents

 Edit individual fields
 Initialize entire memory
 Load data from a file

Left mouse click

directly in field and
type new value

Fill with a selected

value, increment or
decrement or just
Change entire randomly fill
memory or just a
range of
addresses
 Saving Memory Contents to a File

 Once a memory is configured the way you want, simply save it to a file
so it can be loaded whenever you want

Files can be save in standard Verilog

$readmemb/$readmemh format or our proprietary
format for loading with our memory load commands

Name file
 Loading Memories

 Memories can be loaded with saved data or initialized with various fill
values

Select loading
from file, direct, or
both

File name

Direct load
data
 Comparing Two Memories

 A nice way to check results is collect data in a memory and then use
memory compare against a “golden” result

The compare function uses TkDiff

making difference in the memory
easy to see
 Transcript Window
 Running history of commands invoked and messages.
 Provides a command-line interface.
 Automatic Command Help.
 When typing a command at the prompt, a dropdown box appears
listing the available commands matching what has been typed.
 Enable/Disable by selecting Help > Command Completion.

Select command with Tab, LMB,

or up/down arrows to save typing.

 Transcript Menu Items.

 Various items that can be modified.
 Source Window
Language templates pane contain wizards, menus, and
dialogs that help you write VHDL, Verilog, SystemVerilog, Source Annotation.
or SystemC code.
Bookmark buttons.

Language Templates.

Executable lines.

Bookmark – ease navigation by

highlighting certain lines.
RMB > Add/Remove Bookmark

Click in the Ln# column of an executable

 Displays the HDL source code (red) line number to set a breakpoint.
 Many editing and debugging features
 Can drag and drop highlighted objects to the List, Wave, Watch, or Dataflow
windows
 Objects Window GUI: View > Objects
CLI: view objects
 Displays names and current values of the selected design region.
 VHDL signals, constants, generics and shared variables.
 Verilog nets, register variables, named events and module parameters.
 Values do not change dynamically with movement of Wave window cursor.
 Can find/filter by name or by type.
 By name: Type in the Find/Contains field to dynamically display matching objects.
 By type: View > Filter menu selection.
 Toolbar buttons filter display based on mode.
 View any combination of inputs, outputs, inouts, internal signals, or view all.

Port direction.

Double-clicking an item
Value at current
in the Objects window
simulation time.
bookmarks the line and
highlights the item in
the Source window.

Find by Name.
 Processes Window

Selecting a region in the Structure (sim)

window changes the processes displayed
in the Processes (In Region) window.

Selecting a process in the Active, In Region,

Design, or Hierarchy window highlights that
process in the Dataflow window.
 Watch Window GUI: View > Watch
CLI: view watch
 View any object in the
design regardless of the
current context
 VHDL signals, aliases, Object’s address
generics, constants and
variables
 Verilog nets, registers,
variables, named events
and module parameters
 SystemC primitive
channels and ports
 Virtual signals and virtual
functions
 Drag and drop objects from
the Structure, List, Locals,
Objects, Source, and Wave
windows
 add watch <object_name>
 Watch Window (Cont.)

Group objects to display and

move together. Select objects
and click RMB > Group/Ungroup.

RMB > Properties to change radix.

RMB > Save/Load Format to save/reload

contents of Watch window.

Any item that changes value during the

previous run command is marked in RED.
 Wave Window GUI: View > Wave
CLI: view wave

Simulator Control Buttons

Dock/Undock

Message Bar

Pathnames RMB > Radix > Global Signal Radix Waveforms

Port
direction

Values
Cursor

Toolbox
RMB > Cursor Linking
Link and move two or
more cursors together

 VHDL signals, aliases, process variables, and shared variables

 Verilog and SystemVerilog nets, registers, variables, named events,
transactions, classes, assertions, and cover directives
 SystemC, Virtual, and Comparison objects, PSL assertions & cover directives
 Organizing the Wave Window: Dividers

 Dividers provide a “named” separator between signals

 Organizing the Wave Window: Groups

 While dividers only create a “named” separator, groups add the ability
to expand and collapse the separator

Select
signals to Expand &
group collapse
as needed
 Wave Cursors

 Wave cursors have lots ways to control

their behavior
 They have many helpful features useful
during debug Add/Delete Move between
Cursors edges

Values linked to
Lock/Unlock active cursor
Properties Active cursor
Add/Remove highlighted
Gridlines
Leaf names
Time at each
cursor and
distance
between
cursors
 Cursor Properties

RMB click & select

Cursor Properties

Cursor can be uniquely

named and lock in position

Locked cursors
never move
 Cursor Linking

RMB click &

select Cursor
Linking

Link/Unlink all
cursors or select
Configure... to
link only specific
cursors

Both cursors
move together
 Saving the Wave Window Setup

 Once you have the wave window setup the way you like, you can save
it for future reloading
 Signals, zoom, cursors, radix, groups, dividers, etc.

Default file name:

wave.do
 List Window
GUI: View > List
CLI: view list

Drag and drop objects from

the Locals, Objects, Source,
Wave, or Structure windows

Active Marker

Non-active Marker

 Textual representation of waveforms

 VHDL signals, aliases, process variables, and shared variables
 Verilog and SystemVerilog nets, registers, variables, and transactions
 SystemC, Virtual signals and functions, and comparison objects
 FSM Viewer GUI: View > FSM List
CLI: view fsmlist

 Graphical display of Finite State Machines in the design.

 FSMs can be displayed with or without code coverage statistics.

Double-click to display After compiling and loading design.

graphical FSM.

RMB > Add to Wave > Selected FSM

Green: Current state
Yellow: Previous state
Tan: Reset state
Blue: Non-reset state

Dynamically linked to Wave window.

– Moving the Wave window cursor changes the active
(current) state.
– FSM View > Track Wave Cursor menu selection.
 Questa Windows
Processes Window:
VHDL processes and
Structure (sim) Objects Windows: concurrent signal
Window: Current value of data assignments.
Design hierarchy for objects in current region. Verilog initial, always,
current design loaded assign and implicit wire.
in the simulator.

Source Window:
Editable,
color-coded.
Transcript Window:
Tracks simulation
commands and
messages.

Locals Windows:
Dataflow Window: Next executable data.
Interconnect of
processes and
signals.

Wave and List

Windows:
Historical
tracking of
selected data.
 Resetting the Toolbar

 The menu groups

within the toolbar often
get “jumbled”,
especially after the
window is repeatedly
resized
 RMB in menu area and
select “Reset” to tidy
this up
 This will re-pack the
menu groups
 Editing Source Code

 Source Window is “READ ONLY” by default

 Allows interactive usage for breakpoints, single stepping, examining signal
values, etc. without accidentally modifying the source
 Toggle off with Source menu option
 Create Testbench Wizard
 Double-click “Create Testbench” in the Language Templates window.

Select a compiled design unit.

 AGENDA
 Module-1 -- Introduction to QuestaSim.

 Module-2 -- Advanced Debugging Features.

 Module-3 -- Introduction to Code-Coverage.

 Module-4 -- Introduction to Assertion Based Verification.

 Module-5 – Advance Verification Questa Support.

 Module -2

 Advance Debugging Features

 Dataflow Window.

 Schematic Window.

 Waveform Comparison.

 Checkpoint & Restore.

 Dataflow Window
 Explore the physical connectivity of the
design

Hierarchical
boundary

Input on
sensitivity list Verilog primitives
of process automatically
mapped to correct
symbol
Dataflow Viewing Options

 Turning on several options can help keep

information in the dataflow organized

Enabling Hierarchy
adds boarder
showing instance
boundary
 Attached Wave Viewer

 The attached wave viewer is a context sensitive view based on which

instance in the dataflow is selected
 Same functionality as the regular wave window

Toggle attached
wave ON/OFF

All inputs & outputs for

selected instance
displayed

Values in
dataflow linked
to active cursor
 Dataflow Example: Finding X Root Cause

Double click (depends on action set) or RMB menu

to send “rw_out” signal to the dataflow window
Signal of interest
transitions to an
unknown

Chose RMB
menu ChaseX

Double click to
show source
 Schematic Window GUI: View > Schematic
CLI: view schematic

 Provides an implementation view of the design.

 Bit-level RTL view separating sequential elements from combinational logic.
 Explore the “physical” connectivity of the design.
 Trace events that propagate through the design.
 Identify the cause of unexpected outputs.

process or
logic gate

module
or entity
instance
 Schematic Window (Cont.)
 Incremental view
 Logical gate equivalent of the
RTL design
– Understand design intent
 Ideal for design debugging
– Trace signal readers/drivers
 Embedded wave viewer

 Full view
 Structural overview of the
design hierarchy
– Processes and interconnect
 Dynamically linked to
selections in other windows
with the “Follow” selection
 Tracing From the Schematic Window
1. Click time indicator

3. Highlight signal

2. Enter causality
trace start time
4. RMB > Event Traceback
> Show Cause

5. Cause is highlighted in Source window

 Compare Datasets Using Waveform Compare
 Compare the results of simulation:
 The current simulation against a saved waveform file
 A saved waveform file against another saved waveform file
 Two modes of operation:
 Continuous comparison
 Clocked comparison
 Ease of use:
 Scrollbars identify mis-
compared areas
 Search for next/previous
mis-compare
 Annotate comments to
waveform
Continuous: red shaded
region over comparison
differences
 Comparison Wizard

Specify reference dataset name

Use current sim or specify test dataset

Walks you through all the steps to do a compare!

 Comparison Wizard (Cont.)
2

Select signals to compare

Click to run the compare Compare waveforms are

automatically created!
 Waveform Compare Menus
Using the Menus to Define a Comparison
1. Tools > Waveform Compare

2. Add signals, regions, or define

clocks for clocked comparisons

4. End the compare

3. Run the compare

 Compare by Signal Dialog Box

1. Add signal

2. Select signal

3. Specify compare method

 Differences

Compare navigation buttons

The “match” and “diff” in the

Values column relates to the
active cursor.

Pathnames of all compare Difference markers

signals are designated as
yellow triangles. Differences
are marked with red X.
Clocked versus Continuous Differences

Clocked: red diamonds

at the comparison point

Continuous: red shaded region

over comparison differences
 Write Report
 Create a comparison report
 Command: compare info [-write <filename>] ...

View in
Transcript
window

Save to a
text file
 VCD (Value Change Dump)

 IEEE 1364-2005 standard.

 Supported for use in QuestaSim.

 ASCII file that contains information about value changes on

selected variables in the design stored by VCD System Tasks.
 Creating a VCD (Value Change Dump) File
 First, compile and load the design. For example:
 cd <installDir>/examples/tutorials/verilog/basicSimulation
 vlib work
 vlog counter.v tcounter.v
 vsim test_counter

 Next, with the design loaded, specify the VCD file name and
objects to add with the vcd dumpports command:
 vcd dumpports -file myvcdfile.vcd /test_counter/dut/*
 Run
 quit –f
 Using VCD as stimulus
 First, create the VCD file for the single instance using vcd
dumpports:
 cd <installDir>/examples/tutorials/verilog/basicSimulation
 vlib work
 vlog counter.v tcounter.v
 vsim test_counter +dumpports+nocollapse
 vcd dumpports -file counter.vcd /test_counter/dut/*
 Run
 quit -f
 Next, rerun the counter without the test bench, using the -
vcdstim argument:
 vsim counter -vcdstim counter.vcd
 add wave /*
 run 200
 Checkpoint and Restore
 checkpoint saves the simulation kernel state of the design.
 This includes the vsim.wlf file, the list of the HDL items shown in the List and
Wave windows, the file pointer positions for open files, and the state of
foreign architectures.
checkpoint <filename>
 restore restores the “state” of the design saved by checkpoint.
restore <filename>
or
vsim -restore <filename>
 Useful for long simulations.
 Put in periodic checkpoints in anticipation of simulation error.
 Restore back to “state” prior to simulation error.
– Add more signals to monitor for debugging purposes.
– Continue simulation.

Checkpoint files are platform dependent. You cannot

checkpoint on one platform and restore on another.
Checkpoint/Restore must use the same simulator version.
 Signal Spy

 Ability to probe through VHDL hierarchy/Mixed HDL Designs.

 Ability to probe through mixed HDL designs.

 VHDL Procedure (utility):

 init_signal_spy (source, destination, verbose, control_state)
init_signal_driver()
signal_force()
signal_release()
 Verilog System Task:
 $init_signal_spy (source, destination, verbose, control_state)

$init_signal_driver()
$signal_force()
$signal_release()
 Signal Spy (Cont.)
 Signal probing capability.
 Can check any signal
in any other VHDL or VHDL testbench
Verilog module without
having to modify your code. ...
signal s, t, r: std_logic;
...
 Greatly simplifies init_signal_spy(“/top/u1/s”, “s”);
init_signal_spy(“/top/u1/t2/v1/s”, “t”);
testbench development Verilog init_signal_spy(“/top/u1/t2/v2/r”, “r”);

and debug for VHDL

and mixed-language
VHDL Verilog
environments. signal s: std_logic;

Verilog VHDL VHDL

VHDL Verilog Verilog

signal s: std_logic; wire r;
 AGENDA

 Module-1 -- Introduction to QuestaSim.

 Module-2 -- Advanced Debugging Features.

 Module-3 -- Introduction to Code-Coverage.

 Module-4 -- Introduction to Assertion Based Verification.

 Module-5 – Advance Verification Questa Support.

 Module -3

 Introduction to Code Coverage.

 Types of Code Coverage.

 Using Code Coverage in QuestaSim.

 Merging Code Coverage from different tests.

 Generating Code Coverage Reports.

 Code Coverage in QuestaSim
 Tightly integrated with ModelSim
 No learning another tool
 No instrumented code
 VHDL, Verilog and SystemVerilog supported
 Approx. 5-10% performance impact
 Coverage Metrics:
 Branch
 Condition
 Expression
 Statement
 Toggle
 Finite State Machine (FSM)
 Fully Integrated with GUI
 Results displayed in various graphical windows
 Results displayed for each metric — also provides FSM graphics
 Missed Coverage and Objects windows linked to Source window
 View coverage results during current simulation
 Can save coverage data to a Unified Coverage Database (UCDB) for post-process
analysis
 Statement Coverage
 z = 0;
 One countable statement for statement coverage
 if (x == 0) z = 1;
 z = 1 countable statement for statement coverage only if true

always @ (x or y) begin
z = 0;
if (x == 0) z = 1;
end
 Branch Coverage
 Branch Coverage measures the coverage of
expressions and case statements that affect
control flow. if (x == 0)
 Branch Coverage reports if the if x == 0 branch z = 1;
was tested true or false.
else begin
 Case statements z = 0;
 Statement coverage end
– 1,2: z = 1; reports a hit if x was 1 or 2
 Branch Coverage
case (x)
– Reports if x was tested 1, 2 or 3
1,2: z = 1;
– 1,2: z = 1; 1 and 2 will be reported separately
3: z = 0;
– Provides additional information
to Statement coverage endcase
 Expression Coverage
 Analyzes expressions on the right hand side of assignment
statements.
 Counts when these expressions are executed.
 Constructs a truth table and tabulates counts for conditions
involving Boolean expressions.
 Example:
Truth Table for Line 236

counts a b(0) (a xor not(b(0))) (not b(0))

Row 1 1 0 0 1 1

Row 2 0 0 1 0 0

Row 3 2 1 0 0 1

Row 4 0 1 1 1 0

Unknown 0
one of the variables
had an “x” state Line 236: x <= a xor (not b(0));
 Condition Coverage
 Extension of branch coverage
 Evaluates “if”, “if-then-else”, and other ternary statements
 Constructs truth table
 Keeps track of count of each row of truth table
 Example:

Truth Table for Line 180

counts a b (a or b)

Row 1 5 1 - 1

Row 2 0 - 1 1

Row 3 8 0 0 0

Unknown 0

Line 180: IF (a or b) THEN x := 0; else x := 1; endif;

 Toggle Coverage
 Count and collect state changes on specified nodes:
 Verilog and SystemVerilog types
 wire, reg, bit, enum, real, shortreal, shortint, int, longint, byte, integer, and time
 arrays, structs, and packed unions
 VHDL types
 boolean, bit, bit_vector, enum, integer, std_(u)logic, and std_(u)logic_vector
 arrays and records
 Two modes of toggle coverage operation:
 Standard
 Extended

 Standard (2-state) toggle coverage counts the following:

 Low or 0  1 or High
 High or 1  0 or Low
 Extended (3-state) toggle coverage includes standard coverage plus the
following:
 Z  1 or H
 Z  0 or L
 1 or H  Z
 0 or L  Z
 Finite State Machine (FSM) Coverage

 Types of coverage:
 State Coverage Metric.
 Transition Coverage Metric.

 All existing coverage commands line options are available for

FSM coverage.

 FSM recognition and coverage is enabled during compilation.

 Use the vcom | vlog | +cover=f switch.
 Invoking Code Coverage: Two-Step Flow
 Two-step flow:
 Compile vcom or vlog with +cover[=<spec>] argument.
– <spec> indicates one or more of the following:
b — Collect branch statistics.
c — Collect condition statistics.
e — Collect expression statistics.
s — Collect statement statistics.
t — Collect toggle statistics. Overridden if “x” is specified elsewhere.
x — Collect extended toggle statistics. Takes precedence if “t” is
specified elsewhere.
f — Collect finite state machine statistics.
– +cover with no "=<spec>" is equivalent to "+cover=bcesft"
 Simulate the design with vsim -coverage argument.
 Example:
vlog proc.v cache.v top.v +cover=bcesfx –nocoverfec
vsim –coverage top

The two-step process enables coverage statistics collection on all areas of the design.
 Enabling Code Coverage in the GUI, 2-Step Flow
 GUI
 Compile > Compile Options > Coverage Tab
 Simulate > Start Simulation > Others Tab > Enable code coverage
1 2

Use this dialog box to

enable code coverage
when compiling your code
for the 2-step flow.
 Code Coverage in the Structure Window
Default: Coverage statistics displayed in the Structure
window columns are for each design instance only.

Code Coverage compilation options.

View coverage recursively:

Structure > Code Coverage > Enable Recursive Coverage Sums
or RMB > Code Coverage > Enable Recursive Coverage Sums
 Code Coverage Analysis Window
 View covered, uncovered (missed), and/or excluded coverage items.
 Analysis toolbar.
Excluded
items View > Coverage > Code Coverage Analysis
or
Coverage metric view canalysis
Covered Uncovered
(missed)

View > Coverage > Details or view details

Expression Analysis:
– expression has been covered.
XE – one or more expressions were missed.
 Code Coverage Analysis Window (Cont.)

Select a line and see specifics

in Coverage Details window.

Statement Analysis:
– statement has been covered.
XS – one or more statements were missed.

Condition Analysis:
– Condition has been covered.
XC – one or more conditions were missed.
 Code Coverage Analysis Window (Cont.)
Click the state button to open
a state machine view window.

State machine name

State

Transition

FSM Analysis:
The state variable name is listed at the top of the
hierarchy and is also a button.
A green check mark indicates that the state was
covered.
An X indicates that a transition was not taken.
 Viewing Toggle Coverage

Toggle Analysis: Size (width)

– node has been covered (toggled). of the signal.
X – node has not been covered.

Click the state button to open

a state machine view window.
 Code Coverage in the Source Window
Coverage calculation method.

Branch Coverage (“BC”) column indicates whether

a particular branch has executed.

Unexecuted statements and

branches are highlighted in pink.

Click to view in
Coverage Details
window.
– Line has been executed.
X – More than one kind of coverage was missed.
XB – One or more branches were missed.
XC – One or more conditions were missed.
XE – One or more expressions were missed.
XS – One or more statements were missed.
XT – True branch not executed. (BC column)
XF – False branch not executed. (BC column)
 Code Coverage in the Source Window (Cont.)

Hover the mouse over any line of code

to display the coverage numbers.
 Creating Coverage Reports
CLI: coverage report command

Right-click on any item in the Instance Coverage

window to access the Coverage Report menu.

Can also select any item in the Files or Structure

(sim) windows and RMB > Code Coverage > Code
Coverage Reports
 Saving Coverage Data
 Save coverage data using the GUI.

Tools > Coverage Save

Specify coverage types to save, the

hierarchy, output UCDB filename, etc.
 Reloading Coverage Data in the GUI
 Load a UCDB file into the
Verification Management Browser
window:
 First, bring up the Verification
Management Browser window:
View > Verification Management >
Browser
 CLI: view browser
 Reloading Coverage Data in the GUI (Cont.)
 After the Verification Management Browser window loads, add file(s).
 GUI: RMB > Add File in the Verification Management Browser window
 Command: add testbrowser cover1.ucdb cover2.ucdb

 After adding the UCDB file(s) to the Browser window, results for each
UCDB file are available.
 Merging Coverage Data in the GUI

Select the UCDB files to merge, then RMB > Merge.

In the Merge Result File Name

field, type a name or accept
the default (merge.ucdb).

CLI: vcover merge command

 Invoking Coverage View Mode in the GUI
 Select the UCDB file you want to invoke coverage view mode on,
then RMB > Invoke CoverageView Mode.

CLI: vsim –viewcov <filename>.ucdb

or, coverage open <filename>.ucdb
 Coverage View Mode with UCDB Loaded

Invoke coverage view mode through the GUI or with vsim –viewcov <filename>.ucdb or coverage open
<filename>.ucdb. The workspace contains a tab for the .ucdb file, called cover3 in this example.
 Generating HTML Reports

 Can create on-screen, static

coverage reports in HTML.
 From the GUI:
 Select a UCDB file in the
Verification Management
Browser window.
– From the main menu, select
Verification Browser > HTML
Report.
– In the Browser window, select
RMB > HTML Report.
 From the main menu, select
Tools > Coverage Report >
HTML.
 From the CLI:
coverage report –html <options> <input_ucdb>
or
vcover report -html <options> <input_ucdb>
 AGENDA
 Module-1 -- Introduction to QuestaSim.

 Module-2 -- Advanced Debugging Features.

 Module-3 -- Introduction to Code-Coverage.

 Module-4 -- Introduction to Assertion Based Verification.

 Module-5 – Advance Verification Questa Support.

 Module -4

 Introduction to Assertion Based Verification.

 Types of Assertions Languages.

 Simulating Assertions in QuestaSim.

 What is an Assertion?

A concise description of [un]desired behavior

0 1 2 3 4 5
req

ack
Example intended behavior

“After the request signal is asserted, the

acknowledge signal must come 1 to 3 cycles later”
 Concise and Expressive
SVA Assertion
property req_ack;
@(posedge clk) req ##[1:3] $rose(ack);
endproperty
as_req_ack: assert property(req_ack);

always @(posedge req) begin Verilog

0 1 2 3 4 5 repeat (1) @(posedge clk);
fork: pos_pos
req begin
@(posedge ack)
ack $display("Assertion Success",$time);
disable pos_pos;
Example intended behavior
end
begin
repeat (2) @(posedge clk);
$display("Assertion Failure",$time);
disable pos_pos;
end
HDL Assertion join
end
 SystemVerilog Assertions (SVA)

 Part of IEEE 1800-2009 SystemVerilog standard

 First added in the Accellera 3.0 standard
 Evolved over many revisions
 Native to Verilog/SystemVerilog
 Directly embed assertions in the design and/or testbench
 Same syntax as design and/or testbench

property p1;
@(posedge clock) a |-> b == 8’b10010001;
endproperty
assert property (p1);

 Use with dynamic simulation and/or formal property checking

 Property Specification Language (PSL)

 Standardized by IEEE as 1850-2005

 Based on the IBM Sugar donation to Accellera
 Dynamic simulation and formal property checking
 Not native to design or testbench language
 Added as a meta (tagged) comment

// psl property vlog_1 = always {a} |-> {b == 8’b10010001};

// psl assert vlog_1;
-- psl property vhdl_1 is always {a} |-> {b = “10010001”};
-- psl assert vhdl_1;

 Added to the IEEE 1076-2008 VHDL standard

 Provides an embedded (native) assertion language to VHDL
 VHDL 2008 contains a simple subset of PSL
 Assertions Window
 Display a list of PSL or SystemVerilog assert directives
 GUI: View > Coverage > Assertions
 CLI: view assertions

Failure/Pass counts

Assertion header menu accessed by

clicking the RMB on the column
 Assertion Error Reporting

Expression that caused assertion to fail

Assertion error

Start of assertion evaluation

Assertion passed
Assertion failed at this time

Green mid- line indicates

assertion is active. Blue low-line indicates
assertion is inactive.

Drag and Drop from Assertions window to Wave window.

Expand to see associated signals.
 Assertion Error Reporting (Cont.)
Clicking Messages takes you to the next simulation message.
Tab/Shift-Tab to go forward/backward to next/previous message.

A blue square indicates

when a new thread starts.

Double-click any top

triangle loads the
Message Viewer.
 Advanced Assertion Debug
Expanded
assertion
Red dots indicates
expression is false
Green dots indicates
expression is true

Local variable
pane

Design
Objects pane
Yellow dots indicates
additional thread
spawned Redundant failures:
individual spawned thread
failed but other threads
still active

 Automate and Ease Assertion Based Verification

 Create Assertion Reports
RMB > Report

VSIM > coverage report –assert –details –file <filename> -r /

 AGENDA

 Module-1 -- Introduction to QuestaSim.

 Module-2 -- Advanced Debugging Features.

 Module-3 -- Introduction to Code-Coverage.

 Module-4 -- Introduction to Assertion Based Verification.

 Module-5 – Advance Verification Questa Support.

 Module -5

 Module-5 – Advance Verification Questa Support.

 Constraint Randomization in QuestaSim.

 Functional Coverage in QuestaSim.

 Focusing Random Distributions

 While random stimulus can help find bugs

 Focusing the scope of what is generated yields better results
120

100

80

Random
60
Constrained Random

40

20 Distributed,
but focused
0
0 20 40 60 80 100 120
 Defining & Controlling Random Variables

 Constraints are built onto the SV Class system

 SV class random variables identified by special
modifiers
class Bus; Random variable
rand bit [31:0] data;
randc bit [15:0] addr;
endclass Random cyclic variable

 Values generated for random variables are controlled

using constraints

class myBus extends Bus;

constraint word_align {addr[1:0] == 2’b0;}
endclass
 Randomizing Variables

 Object is randomized by calling built-in class method

 Randomize method automatically available in classes using
random variables Both addr & data will
class Bus; be randomized
randc bit [15:0] addr;
rand bit [31:0] data; pkt_number will NOT be randomized
int pkt_number;
constraint word_align {addr[1:0] == 2’b0;}
endclass
Bus busA = new; The randomize method
repeat (50) called just as any other
if ( busA.randomize() == 1 ) class method
$display("addr = %h data = %h",busA.addr,busA.data);
else
$display("Randomization FAILED"); Always test return
value of randomize
 Layered Constraints
 Constraints are inherited from parent class to any subclasses
 Constraints are additive
Base class has two random
class Bus; variables & one constraint
rand bit [15:0] addr;
rand bit [31:0] data;
constraint word_align {addr[1:0] == 2’b0;}
endclass

typedef enum { low, high } AddrType; Extended class adds a new

class MyBus extends Bus; random variable & an
rand AddrType atype; additional constraint
constraint addr_rang {
( atype == low ) -> addr inside { [ 0 : 15] };
( atype == high ) -> addr inside { [128 : 255] };
solve atype before addr;}
endclass Both constraints work together:
(atype == low) => addr = {0, 4, 8, c}
 Enabling & Disabling Random Variables

 SystemVerilog provides a method to enable or disable random

variables
 Can be called as a task or a function
class packet;
rand int eth_src, eth_dest;
...
endclass : packet
int status; Turn off all variables in object
packet eth_pkt = new();
initial begin
eth_pkt.rand_mode(0); Enable only eth_src
eth_pkt.eth_src.rand_mode(1);
status = eth_pkt.eth_dest.rand_mode()
...
end
Get status of eth_dest
 Turning Constraints ON & OFF

 In SystemVerilog, constraints can also be controlled just like

random variables
 Can be called as a task or a function

class Bus;
rand bit [15:0] addr;
rand bit [31:0] data;
constraint word_align {addr[1:0] == 2’b0;} Test whether or
endclass not constraint is
function int toggle_constraint( Bus b ); enabled
if ( b.word_align.constraint_mode() )
b.word_align.constraint_mode(0);
else Turn constraint OFF
b.word_align.constraint_mode(1);
toggle_constraint = b.randomize();
endfunction : toggle_constraint Turn constraint ON
 Module -5

 Module-5 – Advance Verification Questa Support.

 Constraint Randomization in QuestaSim.

 Functional Coverage in QuestaSim.

 What is Coverage?

 The percentage of your verification objectives that

have been met
 Two basic types of coverage
 Coverage that can be automatically extracted by the tool
for the design code: Code Coverage
 Coverage developed by the user to link the testbench to
the design’s functionality: Functional Coverage
 Code and Functional coverage are not the same
 You need both types of coverage
 SystemVerilog Covergroups

 The covergroup encapsulates the coverage model

 Acts like a class – must create an instance & construct it
 A covergroup can be defined in:
 package, module, interface, class or program

enum { Event to cause

IDLE, MEM_ACCESS, SWITCH, RAS_CAS, REF2 covergroup to
} fsm_state; capture values

covergroup dram_ctrl_cg @(posedge sample);

Variable to cover –
fsm_cp: coverpoint fsm_state;
tool creates all
endgroup : dram_ctrl_cg
needed bins
dram_ctrl_cg CG1 = new();
Construct an instance of
dram_ctrl_cg
 covergroup Sampling

 Covergroups can have clocking events for sampling

covergroup dram_ctrl_cg @(posedge sample);
fsm_cp: coverpoint fsm_state;
endgroup : dram_ctrl_cg Pick logical clocking event that
is representative of the data
you are capturing, the clock is
probably not the best choice
 They can also use a procedural sampling method

covergroup dram_ctrl_cg;
fsm_cp: coverpoint fsm_state;
endgroup : dram_ctrl_cg
Sample when there
dram_ctrl_cg cg1 = new();
is known good data
...
always @(posedge xact_write)
cg1.sample();
 Covergroups in Classes

 Covergroups can be declared in a class

 Intuitive & expressive method for creating coverage models
 Some differences when a covergroup is used in a class
 Only one instance of each declared covergroup allowed
 An implicit instance is declared with the name of the covergroup if no
explicit instance is declared
class monitor;
int data;
covergroup cg1 @(posedge sample); Do not need to declare
coverpoint data; an instance but do
endgroup : cg1 need to constuct the
function new(); covergroup
cg1 = new();
endfunction : new
endclass : monitor
 Coverpoints

 A covergroup can contain one or more coverpoint

int a, b;
covergroup cg2 @(posedge sample);
coverpoint a;
coverpoint b;
endgroup : cg2

 A coverpoint can be an integral variable or integral expression

 A coverpoint can be optionally labeled

coverpoint a + b;

covergroup cg3 @(posedge sample);

sum_a_b: coverpoint a + b;
endgroup : cg3
 Auto created coverpoint bins

 Each coverpoint has a set of bins to cover all possible values

 If not defined by the user, bins are automatically created
 Use auto_bin_max coverage option to control auto bins
enum {red, blue, green, yellow} color;
covergroup cg1 @(posedge sample);
color_cp: coverpoint color; When not explicitly
endgroup : cg1 specified, bins are
automatically created for
coverpoint color_cp:
red, blue, green, yellow

Auto created bins

 AGENDA

 Module-1 -- Introduction to QuestaSim.

 Module-2 -- Advanced Debugging Features.

 Module-3 -- Introduction to Code-Coverage.

 Module-4 -- Introduction to Assertion Based Verification.

 Module-5 – Advance Verification Questa Support.

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