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System Verilog Interview Questions and Answers PDF
System Verilog Interview Questions and Answers PDF
1 of 6 6/6/2013 11:00 AM
System Verilog Interview Questions and answers http://asic-verification-questions.blogspot.in/2013/06/systemverilog-impo...
ming explicit. The clocking block is a key element in a cycle-based methodology, which enables
users to write testbenches at a higher level of abstrac on. Rather than focusing on signals and
transi ons in me, the test can be defined in terms of cycles and transac ons. The clocking block
separates the ming and synchroniza on details from the structural, func onal, and procedural
elements of a testbench.
Q. What are the ways to avoid race condi on between testbench and RTL using SystemVerilog?
Program block
Clocking block
Enforcement of design signals being driven in non-blocking fashion from program block
if(My_usb_packet == null) begin.// This loop will get exited if the handle is not holding any object
end else begin// Hurray ... the handle is holding an object
end
2 of 6 6/6/2013 11:00 AM
System Verilog Interview Questions and answers http://asic-verification-questions.blogspot.in/2013/06/systemverilog-impo...
int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i] = i;
UniqVal.shuffle();
· Program blocks get executed in the re-ac ve region of scheduling queue, module blocks
get executed in the ac ve region
· A program can call a task or func on in modules or other programs. But a module can not
call a task or func on in a program.
class Base;
integer a,b;
task always_task();
fork
forever
begin
@(a,b);
$display(" a is %d : b is %d at %t ",a,b,$ me);
end
join_none
endtask
endclass
forever begin
fork
begin : reset_logic
@ (negedge reset_);
data <= '0;
end : reset_logic
begin : clk_logic
@ (posedge clk);
if(!reset_) data <= '0;
else data <= data_next;
end : clk_logic
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System Verilog Interview Questions and answers http://asic-verification-questions.blogspot.in/2013/06/systemverilog-impo...
join_any
disable fork
end
Q. Describe the difference between Code Coverage and Func onal Coverage Which is more
important and Why we need them?
Code Coverage indicates the how much of RTL has been exercised. The Func onal Coverage
indicates which features or func ons has been executed. Both of them are very important. With
only Code Coverage, it may not present the real features coverage. On the other hand, the
func onal coverage may miss some unused RTL coverage.
Q. What is polymorphism?
Polymorphism allows an en ty to take a variety of representa ons. Polymorphism
means the ability to request that the same Opera ons be performed by a wide range of different
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System Verilog Interview Questions and answers http://asic-verification-questions.blogspot.in/2013/06/systemverilog-impo...
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System Verilog Interview Questions and answers http://asic-verification-questions.blogspot.in/2013/06/systemverilog-impo...
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