A Seminar report on

FIELD PROGRAMMABLE GATE ARRAY

A Technical seminar report submitted in partial fulfilment of the requirement for the award
of the degree of

BACHELOR OF TECHNOLOGY

In

ELECTRICAL AND ELEECTRONICS ENGINEERING

By

V.JANARDHAN REDDY (16AT5A0211)

Under the Guidance of

Y.HAZARATHAIYA M.TECH

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

G.PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY

Accredited by NAAC with ‘A’ Grade and NBA Accredited (EEE, CSE & ECE)

Permanently Affiliated to JNTUA, Ananthapuramu, Approved by AICTE, New Delhi.

(Recognized by UGC under 2(f) & 12(B) and ISO 9001:2008 Certified Institution)

Nandikotkur Road, Kurnool, A.P-518452

2016-2019

1
 G.PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY
Accredited by NAAC with ‘A’ Grade and NBA Accredited (EEE, CSE & ECE)

Permanently Affiliated to JNTUA, Ananthapuramu, Approved by AICTE, New Delhi.

(Recognized by UGC under 2(f) & 12(B) and ISO 9001:2008 Certified Institution)

Nandikotkur Road, Kurnool, A.P-518452.

2016-2019

CERTIFICATE
This is to certify that the technical seminar report entitled FIELD PROGRAMMABLE GATE ARRAY
is the bonafied work carried out by V. Janardhan Reddy bearing a Roll Number 16AT5A0211 in
the partial fulfillment of the requirements for the award of the degree of Bachelor of Technology in
Electrical and Electronics Engineering during the academic year 2016-2019.

S eminar Guide: Head of the Department:

Y.HAZARATHAIYA, M.Tech Dr. M. Rama Prasad Reddy, M.Tech ,PhD

Date:

Place: Kurnool EXTERNAL EXAMINER

2
 ACKNOWLEDGMENTS

Our hard work never shines if we do not convey our heartfelt gratitude to those people
from whom we got considerable support and encouragement during this Project.
We would like to express our gratitude to our Guide Y, HAZARATHAIYA, Assistant
Professor of Computer Science & Engineering, G.PULLAIAH COLLEGE OF
ENGINEERING AND TECHNOLOGY, for her constant support and guidance throughout the
project work.
We would like to thank DR.M. Rama Prasad Reddy , Head of the Department,
Electrical & Electronics Engineering, for his valuable suggestions from time to time during this
Project.
We would like to express our deep Gratitude to our beloved Principal DR.C. Srinivasa
Rao G.Pullaiah college of Engineering and technology for his encouragement and cooperation
in carrying out the seminar
We are happy to express our sincere thanks to all teaching and non-teaching staff,
Department of Electrical & Electronics Engineering for their help. Finally, we are thankful to all
those who helped directly or indirectly in making endeavor a success.

3
 CONTENTS
LIST OF FIGURES……………………………………………………………1
ABSTRACT…………………………………………………………………2

Chapter-1 INTRODUCTION
1. Introduction……………………………………………………………3
Chapter -2
2.1 Defination …………………………………………………………………5
2.2 History…………………………………………………………………..6

Chapter-3 METHADOLOGY
3.1 Working……………………………………………………………………7
3.2 Block diagram………………………………………………………………8
3.3 Block diagram description………………………………………………….9

Chapter-4 ADVANTAGES
Advantages & disadvantages…………………………………………………10
Applications…………………………………………………………………..11

Chapter-5 CONCLUSION
Conclusion…………………………………………………………………………………12
Reffrences…………………………………………………………………………………...13

4
 LIST OF FIGURES
Fig
………………………………………………………………………………………………………
…………….11
Fig
………………………………………………………………………………………………………
…………….12
Fig
………………………………………………………………………………………………………
…………….13

Fig…………………………………………………………………………………………………
…………………..14
Fig
………………………………………………………………………………………………………
…………….15

5
 ABSTRACT

Modern high-end FPGAs have not only millions of configurable gate

equivalents and interconnects, but also large numbers of hard-wired components. The
latter may include several hundred independent caches and ALUs, and 1 or more
complete microprocessors. The former can be configured various ways, including
10,000-bit wide processors, pipelines with hundreds of stages, collections of cellular,
associative or SIMD processors, systolic arrays, and many other alternatives. In
addition, FPGAs have several hundred of conventional I/O pins typically used for
access to memory or I/O devices, and up to 30 8Gb/s transceivers for high-speed
network interconnect. FPGAs represent a mature and flourishing area of technology
development, and together with graphics processors, are the driving application in
new generations of silicon process technology.
This computational capability makes them attractive for computing numerous
types of applications. Ideal candidate applications involve heavy computation and
significant re-use of input data or intermediate results. Applications may combine
high initiation latency with very high memory bandwidth, as in typical vector
operations. But unlike clusters, the massive on chip interconnect means that
algorithms with heavy use of fine-grained communication are especially appropriate.
Furthermore, the greatest advantage of MPPs, the large number of “memory pipes” is
replicated in the many on-chip RAM blocks. This allows complex interaction among
the data-fetch streams, including the kind we presented at BARC04. FPGAs tend not
to work well when large amounts of precision are required over wide dynamic ranges,
as vendors have as yet not emphasized incorporated floating-point support into the
FPGA fabric. Although FPGAs typically process more payload data per cycle by
eliminating loop overhead and access delays, they work well only when applications
contain enough parallelism to compensate for their relatively low clock.

6
 CHAPTER-1
INTRODUCTION
An FPGA is a device that contains a matrix of reconfigurable gate array
logic circuitry. When a FPGA is configured, the internal circuitry is
connected in a way that creates a hardware implementation of the software
application. Unlike processors, FPGAs use dedicated hardware for
processing logic and do not have an operating system. FPGAs are truly
parallel in nature so different processing operations do not have to
compete for the same resources. As a result, the performance of one part
of the application is not affected when additional processing is added.
Also, multiple control loops can run on a single FPGA device at different
rates. FPGA-based control systems can enforce critical interlock logic and
can be designed to prevent I/O forcing by an operator. However, unlike
hard-wired printed circuit board (PCB) designs which have fixed hardware
resources, FPGA-based systems can literally rewire their internal circuitry
to allow reconfiguration after the control system is deployed to the field.
FPGA devices deliver the performance and reliability of dedicated
hardware circuitry.

A single FPGA can replace thousands of discrete components by

incorporating millions of logic gates in a single integrated circuit (IC)
chip. The internal resources of an FPGA chip consist of a matrix of
configurable logic blocks (CLBs) surrounded by a periphery of I/O blocks
shown in Fig. 20.1. Signals are routed within the FPGA matrix by
programmable interconnect switches and wire routes.

7
 CHAPTER-2
DEFINATION:
An FPGA is a type of integrated circuit (IC) that can be programmed
for different algorithms after fabrication. Modern FPGA devices consist of up to
two million logic cells that can be configured to implement a variety of software
algorithms. Although the traditional FPGA design flow is more similar to a
regular IC than a processor, an FPGA provides significant cost advantages in
comparison to an IC development effort and offers the same level of performance
in most cases. Another advantage of the FPGA when compared to the IC is its ability
to be dynamically reconfigured. This process, which is the same as loading a
program in a processor, can affect part or all of the resources available in the FPGA
fabric.

HISTORY:
The first FPGA was invented by Ross Freeman (cofounder of Xilinx)
in 1985 and since then their logic capacity has enhanced greatly and they have
become a popular choice because FPGA system can be reprogrammed after
manufacturing to implement the user’s final desired application .Some FPGAs can
be reprogrammed infinite times and some limited times.

In general terms, FPGAs are programmable silicon chips with a

collection of programmable logic blocks surrounded by input/output blocks that are
put together through programmable interconnect resource to become any kind of
digital circuit or system. FPGAs developed from programmable read-only memory
(PROM) and programmable logic devices (PLDs)

An FPGA is a type of integrated circuit (IC) that can be programmed

for different algorithms after fabrication. Modern FPGA devices consist of up to
two million logic cells that can be configured to implement a variety of software
algorithms. Although the traditional FPGA design flow is more similar to a
regular IC than a processor, an FPGA provides significant cost advantages in
comparison to an IC development effort and offers the same level of performance
in most cases.
8
 Another advantage of the FPGA when compared to the IC is its ability to
be dynamically reconfigured. This process, which is the same as loading a program in
a processor, can affect part or all of the resources available in the FPGA fabric.

When using the Vivado® HLS compiler, it is important to have a basic

understanding of the available resources in the FPGA fabric and how they interact to
execute a target application. This chapter presents fundamental information about
FPGAs, which is required to guide Vivado HLS to the best computational architecture
for any algorithm.

FPGA Architecture
The basic structure of an FPGA is composed of the following elements:
Look-up table (LUT): This element performs logic operations.

Flip-Flop (FF): This register element stores the result of the LUT.

Wires: These elements connect elements to one another.

Input/Output (I/O) pads: These physically available ports get data in and
out of the FPGA.

The combination of these elements results in the basic FPGA architecture

shown in Figure 2-1. Although this structure is sufficient for the implementation of
any algorithm, the efficiency of the resulting implementation is limited in terms of
computational throughput, required resources, and achievable clock frequency.

9
Basic FPGA Architecture

Contemporary FPGA architectures incorporate the basic elements along with additional
computational and data storage blocks that increase the computational density and efficiency of
the device. These additional elements, which are discussed in the following sections, are:

• Embedded memories for distributed data storage

• Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates

• High-speed serial transceivers

• Off-chip memory controllers

• Multiply-accumulate blocks

The combination of these elements provides the FPGA with the flexibility to implement any
software algorithm running on a processor and results in the contemporary FPGA

Architecture shown in Figure 2-2

10
 CHAPTER-3
METHADOLOGY
WORKING

FPGA provide the next generation in the programmable logic devices. The word Field
in the name refers to the ability of the gate arrays to be programmed for a specific function by
the user instead of by the manufacturer of the device. The word Array is used to indicate a
series of columns and rows of gates that can be programmed by the end user.

As compared to standard gate arrays, the field programmable gate arrays are larger
devices. The basic cell structure for FPGA is some what complicated than the basic cell
structure of standard gate array. The programmable logic blocks of FPGA are called
Configurable Logic Block (CLB).

The FPGA architecture consists of three types of configurable elements-

(i) IOBs – a perimeter of input/output blocks

(ii) CLBs- a core array of configurable logic blocks

(iii) Resources for interconnection

The IOBs provide a programmable interface between the internal; array of logic blocks
(CLBs) and the device’s external package pins. CLBs perform user-specified logic functions, and
the interconnect resources carry signals among the blocks.

A configurable program stored in internal static memory cells determines the logic
functions and the interconnections. The configurable data is loaded into the device during power-
up reprogramming function.

FPGA devices are customized by loading configuration data into internal memory cells. The
FPGA device can either actively read its configuration data out of an external serial or byte-wide
parallel PROM (master modes), or the configuration data can be written to the FPGA devices
(slave and peripheral modes).

11
Architecture of FPGA:

Architecture of FPGA
The fig .1 shows the general structure of FPGA chip. It consists of a large number of
programmable logic blocks surrounded by programmable I/O block. The programmable logic
blocks of FPGA are smaller and less capable than a PLD, but an FPGA chip contains a lot more
logic blocks to make it more capable. As shown in fig.1 the logic blocks are distributed across
the entire chip. These logic blocks can be interconnected with programmable inter connections.

Xilinx, Inc inverted FPGAs, and in this section we will see the FPGA architecture used
by Xilinx. The programmable logic blocks in the Xilinx family of FPGAs are called
Configurable Logic Blocks (CLBs).The Xilinx architecture uses, CLBs, I/O blocks switch matrix
and an external memory chip to realize a logic function. It uses external memory to store the
interconnection information. Therefore, the device can be reprogrammed by simply changing the
configuration data stored in the memory.

12
BLOCK DIAGRAM

CMOS:
Complementary metal-oxide-semiconductor is a technology for constructing integrated
circuits. CMOS technology is used in microprocessors ,microcontrollers ,static RAM and other
digital logical circuits. CMOS technology is also used for several (CMOS sensor) ,data
converters , and highly integrated transceivers for many types of communication.

PROGRAM COUNTER (PC)

PC is a register in a computer processor that contains the address (location) of the
instruction being executed at the current time. As each instruction gets fetched the pc increase its
stored value by 1.

13
BLOCK DIAGRAM DESCRIPTION

Configurable Logic Block:

The above figure the logic functions contained within the Xilinx 3000 series
configurable logic block. It consists of a combinational logic array, program controlled data
multiplexers, and flip-flops.

The CLB contains RAM memory cells and can be programmed to realize any function
of five variables or any two functions of four variables. The functions are stored in the truth
table form, so the number of gates required to realize the functions is not important. In the
above fig each trapezoidal block represents a multiplexer, which can be programmed to
select one of its inputs.

14
The following fig shows the three different modes of operation for this block:

(i)FG mode,(ii)F mode,(iii)FGM mode

15
FG Mode:

The FG mode generates two functions of four variables each. One variable (A) must be
common to both functions. The next two variables can be chosen from B, C, QX and QY.
The remaining variable can be either D or E.

F Mode:

The F mode can generate one function of five variables (A, D, E, and two variables
chosen from B, C, QX and QY).

FGM Mode:

The FGM mode uses a multiplexer with E as a control input to select one of two four-
variable functions. Each function inputs A, D and two of the inputs B, C, QX, QY. The FGM
mode can realize the functions of six or seven variables.

Cascading of CLBs

When we have to implement Boolean function of more than five variables using Xilinx
3000 series then we have to cascade CLBs. The above fig shows the cascading of CLBs.
Here two CLBs are used to gate the two intermediate functions of five variables each, then a
third CLB is used to gate the two intermediate outputs plus an additional three input
variables. Therefore, there are in all 13 variables.

16
 Programmable Interconnect:

The programmable interconnections between the configurable logic blocks and

I/O blocks can be made in several ways

(i)General purpose interconnects

(ii)Direct interconnect

(iii)Vertical & Horizontal Long Line interconnect

(iv)General purposes interconnect:

In general purposes interconnect system, the signals between CLBs or between CLBs and
IOBs can be routed through switch matrices as they travel along the horizontal and vertical lines

17
 CHAPTER-4
ADVANTAGES

 The FPGA is one of the most popular logic circuit components and have
revolutionized.

 Some FPGA advantages include:

 Low-Cost

 Fast turnaround prototype implementation

 Supported by CAD/EDA tools

 High-Density

 High-Speed

 Programmable and Versatile

 Flexible

 Reusable

 Large amounts of logic gates, registers, RAM and routing resources

 Quick time to market

DISADVANTAGES

 Controlling the spin for long distance.

 Combining techniques between the semiconductor and magnetic recording

industry.

 Difficult to inject and measure spin in silicon.

 Silicon causes electrons to loose their spin state.

18
APPLICATIONS

 1 .Security system
 2 .Consumer electronics
 3 .Medical electronics
 4 .Wireless communications
 5 .Aerospace & defence
 6 .Video & image Processing

19
 CHAPTER-5
CONCLUSION

We gained lot of experience implementing the GBT protocol on the ML421

platform (Xilinx virtex 4 FX)

The full data path has been tested.

The embedded transceivers are compatible with the GBT protocol

BER testing can be performed using either the chipScope or the UART

We need to develop the user interface for the second method (eg;Labview)

20
REFFERENCES

 http://www.xilinx.com

 “Optimization Techniques for Efficient Implementation of DSP in

FPGAs”, by J.Wang

 “Reconfigurable Computing for DSP:A Survey” by R.Tessier and

W.Burleson,2001

 “Reconfigurable Computing: The Theory and Practice of FPGA Based

Computing.

21