Design and simulation of 32 bit Floating Point ALU using Verilog

Aravinth R Balachandar V and Edwin Gerald A

Department of Electronics and Communication Engineering, BCET, Karaikal, India

Abstract

The Arithmetic Logic Unit is one of the essential component of a computer. It performs
arithmetic operations such as addition, subtraction, multiplication, division and various logical
functions. The Aim of this paper is to simulate an ALU and to analyze the various parameters
such as speed, power and number of logical blocks used by that ALU. The Floating point
numbers in this paper are represented according to the IEEE standard 754. The Arithmetic
operations such a s addition, subtraction, multiplication, division and the logical operations are
realized using Verilog HDL. Xilinx 7.1i software is used for writing the verilog codes and the
simulation is carried out with ModelSim 5.5f simulator.

1. INTRODUCTION

For the efficient way of representing real
numbers the floating point numbers are
used. It is used when there is a need of
representing a number which is very large or
very small but representation of such
numbers are cannot be done without paying
a price for it like as power, speed, accuracy,
ease of implementation and the memory of
the system.
In the various fields of science such as
physics and biology etc. the need of
measuring the dimensions of objects are
essential for analyzing its characteristics. In
physics measuring the distance between
stars or the size of an electron cannot be
done with the range of fixed numbers hence
we are in need of floating point numbers.
The Arithmetic Logic Unit is the basic
building block of a CPU which does various
arithmetic operations like addition,
subtraction, multiplication and division etc.
1.1 Single Precision IEEE 754 Format
All the floating point numbers are composed
by three components:
 Sign: it indicates the sign of the number (0
positive and 1 negative)
 Mantissa: it sets the value of the number
 Exponent: it contains the value of the base
power (biased)
If a Simple Precision format is used the bits
will be divided in that way:
 The first bit (31st bit) is set the sign (S) of the
number (0 positive and 1 negative)
 Next w bits (from 30th to 23rd bit) represent
the exponent (E)
 The rest of the string, t, (from 22nd to 0) is
reserved to save the mantissa.
Figure 1.1 Floating point number format
Standard IEEE 754 specifies formats and
methods in order to operate with floating
point arithmetic. These methods for
computational with floating point numbers
will yield the same result regardless the
processing is done in hardware, software or
a combination for the two or the
implementation.
The standard specifies:
 Formats for binary and decimal floating
point data for computation and data
interchange
 Different operations as addition,
subtraction, multiplication and
operations
 Conversion between integer-floating
point formats and the other way around
 Different properties to be satisfied when
rounding numbers during arithmetic and
conversions
 Floating point exceptions and their
handling (NaN, ±∞ or zero).
1.2 Conversion of Decimal to Floating Point
Conversion of Decimal to Floating point 32
bit format is explained with an example.
Suppose the decimal number considered is
129.85. Before converting into floating
format this number is converted into binary
value which is 10000001.110111. After
conversion the radix point is moved to the
left such that there will be only one bit
towards the left of the radix point and this
bit must be 1. This bit is known as “hidden
bit”.
The binary value now can be represented
as 1.00000011101110000000000. The
number which is after the radix point is
called the mantissa which is of 23 bits and
the whole number is called significand
which is of 24 bits(including the hidden bit).
Now the number of times the radix point is
shifted (say x) is counted. In above case
there is 7 times shifting of radix point to the
left. This value must be added to 127 to get
the exponent value i.e. original exponent
value is 127 + “x”. Thus the exponent
becomes 127 + 7 = 134 which is 10000110.
Sign bit i.e. MSB is “0” because number is +
ve. Now the result is assembled into 32 bit
other
format which is sign, exponent, mantissa:
01000011000000011101110000000000.
2. LITERATURE SURVEY
In recent years, Floating-point numbers are
widely adopted in many applications due to
its high dynamic range and good robustness
against quantization errors, capabilities.
Floating-point representation is able to
retain its resolution and accuracy.
IEEE specified standard for floating-point provides a high performance. With
representation is known as IEEE 754 pipelining concept ALU execute multiple
standard. This standard specifies interchange instructions simultaneously (Suchita Pare et.
and arithmetic formats and methods for al, 2012) .
binary and decimal floating-point arithmetic
3. METHODOLOGY
in computer programming environments.
(IEEE 754-2008) The entire design is implemented by the
following steps in progression.
The main objective of implementation of
 Conversion of the Floating Point
floating point operation on reconfigurable
Number into a novel integral
hardware is to utilize less chip area with less representation.
combinational delay (Karan Gumber et.al,
 Conversion of the binary integer to its
May 2012) which means less latency i.e.
IEEE754 format.
faster speed. A parameterizable floating
point adder and multiplier implemented  Pre-normalization of the operands
using the software-like language Handel-C,
using the Xilinx XCV1000 FPGA, a five  Performing the selected operation.

stages pipelined multiplier achieved

 Post-normalize the output obtained.
28MFlops (A. Jaenicke et. Al, 2001). The
hardware needed for the parallel 32-bit  Detecting and handling the exceptions
multiplier is approximately 3 times that of encountered.

serial.

A single precision floating point multiplier

that doesn’t support rounding modes can be
implemented using a digit serial multiplier
(L.Louca et. al, 1996). The ALU is a
fundamental building block of the central
processing unit of a computer, and even the
simplest microprocessors contain one for
purposes such as maintaining timers. By
using pipeline with ALU design, ALU
Figure 3.1 Flow diagram of Arithmetic Logic Unit

Figure 3.2 Block diagram of adder/subtractor
Figure 3.3 Block diagram of multiplier
Figure 3.4 Block diagram of divider
Unpack: The sign, exponent and mantissa
of both operands are separated. A flag,
aequalb flag, is set if both inputs are equal.
The aequalb flag will be used if the effective
operation, determined in the adder/subtracter
module, was subtraction to set a flag
indicating a zero output. This prevents
unnecessary addition/subtraction and pre
normalization operations from taking place.
Swap: Inputs are swapped if necessary such
that operand A carries the larger floating
point number and operand B is the smaller
operand to be pre-normalized. A swap flag is
set if the operands were swapped to be used
in determining the effective operation in the
adder/subtracter module.
Pre-normalize: The smaller mantissa, of
operand B, is pre-normalized, that is it's
shifted by the difference between the two
input exponents. Three extra bits the guard
bit, the round bit, and the sticky bit are
added to both mantissas to increase the
accuracy of the performed operation
(addition or subtraction) and to be used in
the rounding process. Sticky bit is the
logical "Or"ing of any bits that are dropped
during the pre-normalization of operand B.
Post Normalize: The resultant mantissa is
normalized after the leading one is detected
using the LOD method. The resultant
exponent is adjusted accordingly.
Rounding: The resultant mantissa is
rounded using the REN technique. The final
output is given in IEEE format.
Adder/Subtracter: The effective operation
to be performed is calculated according to
the signs of operands A & B, the input
operation and the swap flag. The effective
operation is performed and the zero flag is
updated if the effective operation is
subtraction and the aequalb flag is set.
Block Multiplier: Multiplies the two 24 bit
mantissa of operands A and B. the bottle
neck of the design is the 24*24 bit multiplier
used to calculate the resulting 48 bit
mantissa. To increase the maximum
operating speed of the multiplier, the
proposed design breaks up the 24*24 bit
multiplication of operands A and B into nine
8*8 bit multiplications where each mantissa
is sliced into three 8-bit slices such that INPUT B:
A=A2A1A0, B=B2B1B0. Then, B0 is 00000100000001000100001100000011
multiplied in A2, A1 and A0. Each of these RESULT:
three 8*8 bit multiplications gives a 16 bit 00001000000001100100011101000110
result. The three 16 bit results are properly
manipulated to give a 32 bit result Ro of the
24*8 bits multiplication operation (i.e.
A*B0). In a similar manner B1 and B2 are
multiplied in A2, A1 and A0 to give R1 and
R2. R1 and R2 are properly shifted to be
added to R0 thus giving the 48 bit result
mantissa. The result sign is determined
Figure 4.1 Result of Floating point addition
through a simple XOR operation.
Divider:
4.2 Subtraction
 First shift left the dividend by 1. INPUT A:
 Subtract the divisor. If the carry is 1 do 00001000000001100100001100000011
not restore. If carry is 0 i.e. answer is INPUT B:
negative then restore by adding back to 00000100000001000100001100000011
the divisor. RESULT:

 Place the carry as the LSB of the 00001000000001100011111011000000

intermediate answer.

 Do this procedure up to n –iterations,

where n is number of bits in the divisor.
Here n is 24 bits for single precision and
53 bit for double precision.
4. SIMULATION RESULTS
4.1 Addition
INPUT A:
00001000000001100100001100000011 Figure 4.2 Result of Floating point subtraction
4.3 Multiplication
INPUT A:
00001000000001100100001100000011
INPUT B:
00000100000001000100001100000011
RESULT:
000011000000000000110101010111110101 Figure 4.4 Result of Floating point division

0001001001000001001

Figure 4.5 FPGA Spartan 6 kit

5. CONCLUSION

Figure 4.3 Result of Floating point Multiplication

Thus the 32 bit Floating point Arithmetic
Logic Unit was designed to perform the

4.4 Divider operations like addition, subtraction,

INPUT A: multiplication and division . IEEE 754

00001000000001100100001100000011 standard based floating point representation

INPUT B: is used. The programs are coded in Verilog

00000100000001000100001100000011 HDL. The simulation is done with

RESULT: Modelsim 5.5f and the programming is done

00000100000000000000000000000001 using Xilinx 7.1i.

Table5.1: Device Utilization Summary: Comparison with Booth Algorithm (Radix-
2) ” Research India Publications,2013.
Number of Slice Registers 123
Number of Slice LUTs 304
[4] Geetanjali and Nishant Tripathi, "VHDL
Number used as Logic 304
Number of LUT Flip Flop pairs 102 Implementation of 32-Bit Arithmetic Logic
used Unit (ALU)“, International Journal of
Number with an unused Flip 223
Computer Science and Communication
Flop
Number with an unused LUT 5416 Engineering,2012 .
Number of fully used LUT-FF 102
[5] D. Jackuline moni and P. Eben Sophia,”
pairs
Number of IOs 100 Design of low power and high speed
Number of bonded IOBs 98% configurable booth multiplier”, IEEE, 2011.
[6] Kiseon cho and Minkyu song, “Design
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