Mixed Signal Design Lab 3(EC2061)

Experiment No: 04
Santosh Kumar Ramisetty kishore
18EC4215 18EC4216
Microelectronics & VLSI Microelectronics & VLSI
National Institute of Technology National Institute of Technology
Durgapur, India - 713209 Durgapur, India - 713209
Email: gangalasantoshkumar75@gmail.com Email:ramisettykishore16@gmail.com

Abstract
To design a Miller op-amp by using cellview of differential amplifier and

a. Perform DC analysis to verify all transistors in saturation.

b. Perform AC analysis to measure
◦ DC gain
◦ Phase Margin
◦ Bandwidth
◦ Unity Gain Frequency.
c. Perform transient analysis to verify the gain showing input and output waveforms.
d. Using Miller op-amp measure ICMR and slew rate.

I. B RIEF D ESCRIPTION OF THE W ORK

The following specifications are to be acquired:-
◦ Input/output common mode level at 600mV
◦ Length of all transistors = 480m
◦ Load capacitance at 500f F
◦ Tail current = 15uA
◦ DC gain > 35db
◦ Phase Margin > 60◦
◦ Second stage should carry 30uA current.
II. S IMULATION S TEPS AND RESULTS
A. Introduction
◦ In some applications, the gain and/or output swings provided by single stage op-amps are not adequate.

◦ In such cases, we use 2 stage op-amp with the first stage providing a high gain and the second stage, the high swing.
◦ 2 stage amplifier have non dominant pole which gives rise to instability.Hence in order to compensate the effect of non
dominant pole,a miller capacitance is added in 2nd stage of amplifier.
◦ Miller compensation moves dominant pole towards the origin and output pole away from the origin,allowing a much
greater bandwidth.
B. DC analysis of 2 stage amplifier
1) Copy the cellview of differential amplifier and connect a PMOS common source amplifier at 2nd stage.
2) Schematic diagram of 2 stage amplifier is shown in Fig 1.
 Fig. 1. 2 Stage Amplifier

3) Determine width of PMOS and NMOS of 2nd stage to achieve output voltage at 600mV and output current at 30uA
and fix it in schematic.
4) Plot between Id vs wp and Id vs wn is shown in Fig 2 and 3 respectively.

Fig. 2. Id vs wp
 Fig. 3. Id vs wn

C. AC analysis of 2 stage amplifier

1) Schematic diagram of 2 stage amplifier for AC analysis is shown in Fig 4.

Fig. 4. Schematic of AC analysis of 2 stage amplifier

3) AC analysis is performed to plot gain and Phase plot with respect to frequency as shown in Fig 5.
 Fig. 5. Frequency response of 2 stage amplifier

4) DC Gain, Unity Gain Bandwidth, Phase Margin, 3-dB bandwidth is determined from the plot.
D. AC analysis of 2 stage amplifier with Miller capacitance
1) 2 stage amplifier designed above have non dominant pole which gives rise to instability.Hence in order to compensate
effect of non dominant pole a miller capacitance is added in 2nd stage of amplifier.
2) Schematic diagram of 2 stage amplifier with Miller capacitance is shown in Fig 6.

Fig. 6. 2 stage amplifier with Miller compensation

3) AC analysis is performed to plot gain and Phase plot of Miller op-amp with respect to frequency as shown in Fig 7.
 Fig. 7. Frequency response of 2 stage amplifier with Miller compensation

4) DC Gain, Unity Gain Bandwidth, Phase Margin, 3-dB bandwidth is determined from the plot.
E. AC analysis of 2 stage amplifier with Miller capacitance and nulling resistor
1) In a two stage Miller compensation a nearby zero appears in circuit.A resistor in series with compensation capacitor
is added to modify zero frequency.
2) Schematic diagram of 2 stage amplifier with Miller capacitance and nulling resistor is shown in Fig 8.

Fig. 8. 2 stage amplifier with Miller compensation and nulling resistor

3) AC analysis is performed to plot gain and phase plot of Miller op-amp with nulling resistor with respect to frequency
is shown in Fig 9.
 Fig. 9. Frequency response of 2 stage amplifier with Miller compensation and nulling resistor

4) DC Gain, Unity Gain Bandwidth, Phase Margin, 3-dB bandwidth is determined from the plot.
F. ICMR and Slew Rate Calculation
1) Input Common Mode Range(ICMR)
ICMR is the allowable input common mode voltage range for which all the transistors are in saturation region shown in
Fig 10.
 Fig. 10. ICMR Calculation

2) Slew Rate
It is defined as the maximum rate of change of output voltage caused by a step change in input.
3) Schematic diagram for calculation of Slew rate is shown in Fig 11 and 12.

Fig. 11. schematic for Slew rate calculation

 Fig. 12. Slew rate calculation

III. O BSERVATION AND R ESULTS

The following results are obtained from Miller op-amp:-

(1) Results without miller capacitance and nulling resistor

◦ DC Gain = 48.68 dB
◦ UGF = 158 MHz
◦ Phase Margin = -5.737 degrees
◦ 3 dB BW = 34.7 MHz
(2) Results with miller capacitance but without nulling resistor

◦ DC Gain = 63.4 dB
◦ UGF = 102.542 MHz
◦ Phase Margin = 3.5 degrees
◦ 3 dB BW = 898 KHz
(3) Results with miller capacitance and nulling resistor

◦ DC Gain = 63 dB
◦ UGF = 292.32 MHz
◦ Phase Margin = 53.72 degrees
◦ 3 dB BW = 163.78 MHz
◦ ICMR = 0.552 to 1.16
◦ Slew Rate = 37.85 V/usec
IV. ACKNOWLEDGMENT
We express our profound gratitude and deep regards to Dr. Ashis Kumar Mal sir and Dr.Rishi Todani sir for his cordial
support, valuable information and guidance. We express our heartful thanks to our seniors for their guidance, monitoring
and constant encouragement throughout the lab.