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t is not possible to adjust the static noise margin separately. The new structure uses a separate reading path, so
storage node will be not influenced by voltage of bit-line and external noise, which greatly increases the read noise
margin. High static noise margin gets better stability. Figure3. Current path from VDD to GND. When '0' is stored in
cell, M3 is on, M4 is off, Qbar node is connected to VDD. Thus Qbar node is charged to the logic '1' and M2 is turned
off.. With the sub- threshold voltage VIDLE, sub-threshold current of M1 helps to retain the value of Q node. In order
to maintain the value of the Q node, the bit-line bar must be pulled down to GND at idle mode. In this way this
design eliminates the need of refresh cycle and makes use of leakage current to maintain the data at node. Based
on these 3.2 Leakage current SRAM power consumption comprises dynamic and static power consumption..
According to the technology scaling, the supply voltage is reduced and the SRAM operates in subthreshold where
the leakage current increases drastically. This makes static power dissipation significant. . However the new 6T-
SRAM can stores value using leakage current in idle mode. In the new proposed cell leakage current is quite less as
compared to the conventional leakage current under the same condition. Hence it possesses better stability and a
lower power consumption. 3.3 Power consumption In cache, bit-lines, word-lines, sense amplifiers, decoders, and
output drivers are the most power consuming elements’ lines tops the list. They consume power during both the
read and write operations. In the conventional 6T SRAM,we require two bit lines. Each of these bitlines are to be
charged to vdd during read operation, which results in huge power consumption. But in this new design, since only
one bit line ins used for both read and write operation, power consumption in drastically reduced. Also the power
consumption in both write / read of '0' and '1' are the same. 4. Conclusions In this paper, a new highly stable 6T-
SRAM is presented in 65nm technology. This new design makes use of separate write and read operation mode, and
needs only one bit line for read and write operations. So the new cell has lower power consumption which is an
important need in cache. During idle mode of cell, word-line voltage maintained at VIDLE. The cell stores data with
the help of leakage current and positive feedback without refresh cycle. Meanwhile, the new structure improves the
static noise margin by separate read and write operation. References [1] Vijaykrishnan N., Kandemir M., Irwin M.J.,
et al, Proceedings of the 27th International Symposium on Computer Architecture, p.95-106(2000). [2] Takeda K.,
Hagihara Y., Aimoto Y., et al, IEEE Journal of Solid-State Circuits, 41, p.113- 121(2006). [3] Chen Wu, Li-Jun Zhang, et
al, Microelectronics, 40, p.551-560(2010). [4] Azizi N., Najm F.N., Moshovos A., IEEE Transactions on VLSI Systems,
11, p.701-715(2003). [5] Moshovos A., Falsafi B., Najm F.N., et al, IEEE Transactions on VLSI Systems, 13,
p.877-881(2005). [6] Seevinck E., List F.J., Lohstroh J., IEEE Journal of Solid-State Circuits, 22, p.748- 754(1987). [7]
Lohstroh J., Seevinck E., de Groot J., IEEE Journal of Solid-State Circuits, 18, p.803-807(1983). [8] Yen-Jen Chang,
Feipei Lai, Chia-Lin Yang, IEEE Transactions on VLSI Systems, 12, p.827-836(2004).
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