1.

Optimal ratio f for a chain of inverters

We expressed every given data in V, m, and F. Dimensions are expressed in nm unless
specified otherwise.

Our goal is to drive a capacitance of 200fF through a chain of inverters. The number of
inverters in this chain will greatly influence delay characteristics as seen in this section.

1.1.Three stage inverter chain

1.1.1. Determining f

f is the ratio that will let us calculate the width of the NMOS and PMOS transistors of our
chain. It is given by the following:
C 1
f = ( Load ) N where N is the number of inverters driving the load.
C in
(1)
⇒ f = 5.84

The first inverter’s NMOS dimensions will be of minimum size s, the PMOS dimensions
being evaluated through simulation below. The second inverter will be sized k2s, the 3rd
inverter k3s etc.

1.1.2. Size of the PMOS transistor in the first inverter

We do not know a priori what the size of the PMOS transistors of the chain should be.
To find out, we simulated a chain of 3 inverters driving a load of 200fF with Cadence.
Appendices 1 and 1bis give the schematic used for this simulation.
The results of the simulation appear in appendices 2 and 3. The rise and fall times, as
well as the propagation delays were measured on the output of the minimum size
inverter, id est the first inverter of the chain. We were looking for a W / L ratio that
would yield a symmetric design (VM around 0.9V and equivalent trise and tfall) while
keeping the propagation delay within reasonable bounds.

A ratio of 4 to 1 gives the better result in terms of the problem just formulated.
Out of curiosity, we also plotted the transient response at the output of the whole chain of
inverters. This is given by appendix 4. Note that the tfall and trise are almost equal and
around 260ps.

In the light of the simulation, we decided to take a ratio of 4 to 1. The f ratio is 5.84.

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1.1.3. Chain of inverters for first layout

880 5139 30012

180 180 180

220 1284 7503

180 180 180

1.1.4. Propagation delay

Now that we have our ratios f and Wp to Wn we can evaluate the propagation delay from
one end of the chain to the other end.
First, let us evaluate the propagation delay of one inverter. We computed tp like in the
first homework assignment using a Wp of 880nm and a minimum size NMOS. Our
calculations yielded tpHL and tpLH of 2ps and 7.5ps respectively. 7.5ps is the delay created
by the critical path in the inverter.

t pchain = N ⋅ t inv ⋅ ( f + γ ) ≈ 142 ps

(2)

1.2. Optimal number of inverters in the chain

1.2.1. Determining f

The optimum case for the number of inverters in a chain driving a load is given in
consideration of γ.

γ=0 fopt = e
γ = 1 (closer to reality) fopt ≈ 3.6

Our γ being 0.5, we will keep in mind that fopt may not be exactly 3.6.

C Load
ln( )
C in
We have N = ≈ 4.136 . We now need to choose how to round this number (up
ln f
or down). We could take 4 or 5 inverters. Given that the real γ is between 0 and 1, we
chose a chain of 5 inverters (which actually brings a f of 2.88). Relationship (1) also tends
to show that a smaller f would let us with a faster design. Using (1):

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 N=4 f ≈ 3.8 tpchain ≈ 129ps
N=5 f ≈ 2.88 tpchain ≈ 127ps

Our choice for N may not be the wiser but it makes sense in terms of propagation delay.

1.2.2. Size of the PMOS transistor in the first inverter

We used the same method as in 1.1.2.: we simulated a chain of 5 inverters and

determined which width ratio would yield the most symmetric device. We found that a
ratio of 4 to 1 yet again was giving a better result.

1.2.3. Chain of 5 inverters

880 2.539µm 7.324µm 21.136µm 60.996µm

220 634 1.831µm 5.284µm 15.249µm

1.2.4. Propagation delay

As seen above, the total propagation delay in the chain is approximately 127ps.

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2. Layout and simulation
2.1. Layout of the two chains of inverters

The layouts of the 3-stage and 5-stage inverters are shown in appendices 10, 11, and 12.
The size L of the gate was put to 180nm in every case. When the W of the transistors
exceeded 3µm, we decided to rearrange the design so that the gates meanders within the
active drawing as suggested below:

In this case, the total width of the gate is 3W.

Note: We tried to avoid angles when drawing metal lines.

2.2. Test and simulation of the design

Once the layout was finished, we extracted it to a schematic, displaying only the pins of
the new instance. We then created a new cellview from this cellview.
Appendix 13 shows the schematic used to test and measure some of the characteristics of
our chains of inverters.

2.2.1. Propagation delays of the chain of 3 and 5 inverters

These characteristics are given by appendices 14 and 15.

We have the following:

3 inverter chain 5 inverter chain

tpLH 265ps 336ps
tpHL 251ps 273ps
tp 258ps 304ps
tfall 341ps 276ps
trise 340ps 395ps
VM 0.83V 0.83V

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For this section of the assignment, we did a transient and DC-sweep 0-to-1.8V simulation
to obtain the output voltage as a function of time and the VTC curve.

2.2.2. Power consumptions

The power consumptions were calculated for both chain of inverters and are given in
appendices 16 and 17.
We have the following:

3 inverter chain 5 inverter chain

P average 293µW 507µW

To calculate the average power consumption, we ran the simulation over a period of 5ns
with a 2ns periodic pulse input voltage. The input voltages were rigorously the same
when simulating the 1st or 2nd chain of inverters. We decided to plot the input current
(taken at the plus end of the input voltage). We then used the calculator to multiply this
current by Vdd (1.8V). Finally, with the special function Average, we re-plotted the
curve.

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3. Comparison of the analytical and simulated results
When simulating the two chains of inverters, we were expecting to find a much better
propagation delay in the “optimal” case (5 inverters in the chain) compared to the 3
inverter case. The simulation of our layouts gave much different results than what was
expected.
First, the propagation delay in each case was between 2 and 2.5 bigger than the one
calculated analytically. But the 5 inverter chain did not even turn out to have a smaller
delay than the 3 inverter chain.
Likewise, the power consumptions for the two cases were the opposite of what we
expected.

Of course, some of those differences with the analytical calculation may be due to our
layout itself: this layout was a first time trial, with inherent flaws.

But two main reasons are probably responsible for this surprising result. The main one is
that Cin was chosen to be 1fF. In reality it may be closer to 5 times this value. If we had
taken a bigger Cin, our optimal f would have been smaller than the one we picked (and
probably around 3, even though it is hard to assess). This also would explain why we
observed such a difference between the calculated propagation delay and the simulated
value for the shortest chain.
The second reason may be the value of γ we picked. We may have chosen a γ much too
close to 0, which had a repercussion on the value of f and the optimal number of inverters
in the chain.

With time, we would have tried a solution with 4 inverters only (our second choice for
N).

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