Dept.

of Electronics and Electrical Communication Engineering Indian

Institute of Technology Kharagpur

VLSI LABORATORY (EC39002)

Experiment - 7
Date of submission: 11-03-2024

Instructor: Group Members:

Prof. Gourab Dutta Name: Akash Ganeriwal
Roll Number: 21EC30063
Name: Aditya Varshney
Roll Number: 21EC10089
Objective-1:
To design a CMOS inverter chain to get optimum delay for specified input and output capacitance.

Circuit Diagram:

a) Circuit for estimating intrinsic delay:

b) Circuit for estimating Cin:

c) Circuit of inverter chain with sizes optimized for minimum delay:

Plots and Observations:
a) Plot for estimating intrinsic delay:

è Here, PMOS Width = 1u and NMOS Width = 0.5u

è We know, tpo = (tPLH + tPHL) / 2 = ((30.173 – 30.15) + (10.062 – 10.05)) / 2 = 0.018ns = 18ps

b) Plots for estimation of Cin:

 è Here, PMOS Width = 1u and NMOS Width = 0.5u
è We know, tp = (tPLH + tPHL) / 2 = ((30.529 – 30.15) + (10.352 – 10.05)) / 2 = 0.681ns = 681ps
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è We know that, tp = tpo (1 + g!%& ), where g = 1 because of submicron device
è Implies that, Cin = 0.0027 pF

c) Plotting the output with optimized sizes for minimum delay:

è For the first inverter stage, PMOS Width = 1um, NMOS Width = 0.5um.
è The input capacitance of the first inverter stage is 0.0027 pF as computed above.
è Hence, F = Cext / Cin = 10 fF / 0.0027pF = 3.7
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è Implies f = √𝐹 = √3.7 = 1.3
è The minimized propagation delay = (tPLH + tPHL) / 2 = ((50.167 – 50) + (0.162 – 0)) / 2 = 0.1645ns = 164.5ps

Objective-2:
To design a ring oscillator using single-ended inverter stages.

Circuit Diagrams:
a) Circuit of the Ring Oscillator:

Plots and Observations:

a) Plots for estimating the frequency of Ring Oscillator:

è Here, we have taken PMOS width = 1u and NMOS width = 0.5u for each inverter stage.
è Frequency of Oscillation = 1 / Time Period = 1 / (1.323ns – 1.041ns) = 3.5461 GHz

Objective-3:
To observe the dependence of supply voltage on the oscillation frequency.

Circuit Diagrams:
a) Circuit of the Ring Oscillator:
b) Circuit of the Ring Oscillatior with temperature sweep:

Plots and Observations:

a) Plots of Ring Oscillator with Vdd sweep:

è Here we observe that the frequency of the oscillation decreases as we decrease Vdd.

b) Plots of the Ring Oscillator with temperature sweep:

è Here, we observe that as we decrease the temperature the Oscillation frequency increases.

Objective-4:
To design a ring oscillator using single-ended inverter stages and frequency 400 MHz.

Circuit Diagrams:
a) Circuit of the Ring Oscillator with 400 MHz frequency:

Plots and Observations:

b) Plots of output of the Ring Oscillator:

è We know that the Oscillation frequency of a ring oscillator is inversely proportional to the length of transistor.
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è Therefore, ideally for 400 MHz frequency we should have L = 0.18 * ) um = 0.536 um.
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è But, we have made an assumption that the gamma value is 1 for the transistor which is not exactly true.
Hence, we have to sweep the length for desired frequency.
è In the above plot we have taken the length to be 0.725 um.
è Frequency of Oscillation = 1 / Time Period = 1 / (9.826ns – 7.33ns) = 400.64 MHz

Questions Asked:
1. Can a ring oscillator be formed using even number of stages?

A Ring Oscillator can be formed using an even number of stages but in that case the last stage would be
simply a latch (instead of inverter). Because for even number of inverter stages the phase difference
between the input and the output becomes 0, which disobeys the Barkhousen Criteria for oscillation.

2. What are the effects of temperature on the frequency?

As we have seen above from the plots that the Oscillation frequency decreases as we increase the
temperature.

3. Is it possible to make a single-stage ring oscillator?

No, we cannot make a ring oscillator using only one stage of the inverter because it would not likely
provide sufficient gain and phase difference to maintain oscillation due to ambiguity of the signal present at
one port.

4. Is BARKHOUSEN CRITERIAN satisfied here ? How ?

Yes, it is satisfies in the above experiment because the there are odd number of stages each providing a
phase shift of 180 degrees and hence the total phase difference is also 180 degrees. Also the loop gain is -1
whose modulus is equal to 1. Therefore it satisfies both the criteria of the Barkhousen.

Discussion:

Objective – 1:

1. We systematically designed a CMOS inverter chain by first defining specifications

and selecting appropriate technology parameters. We then sized the transistors and
 calculated load capacitances for each inverter in the chain. Using SPICE
simulations, we verified the performance, ensuring that the delay met requirements.
The designed circuit demonstrated effective delay optimization while fulfilling
capacitance constraints.

Objective – 2:

1. Technology Parameters Selection: We began by selecting appropriate CMOS

technology parameters, including transistor sizes, threshold voltages, and channel
lengths. These parameters significantly influenced the performance of the ring
oscillator.
2. Inverter Sizing: Next, we determined the sizes of the NMOS and PMOS transistors
for the single-ended inverters. Through equations and simulation tools, we
optimized the sizing to achieve the desired oscillation frequency while minimizing
power consumption.
3. Cascade Inverters: We connected multiple single-ended inverters in a ring
configuration, ensuring an odd number of inverters to provide a total phase shift of
360 degrees around the loop, enabling oscillation.
4. Power Supply and Biasing: Proper power supply and biasing conditions were
provided to the inverters to ensure their operation within the desired voltage range.
5. Simulation and Optimization: Using circuit simulation tools like SPICE, we
simulated the designed ring oscillator. We verified that the oscillation frequency met
the specified requirements and optimized the design parameters as necessary to
enhance performance.

Objective – 3:

1. Setup Configuration: We constructed a ring oscillator circuit using CMOS

inverters arranged in a ring topology. The inverters were designed to operate within
a specified range of supply voltages.

2. Oscillation Frequency Measurement: With the circuit powered on, we measured

the oscillation frequency using a frequency counter or oscilloscope. This frequency
represents the rate at which the output signal oscillates in the circuit.

3. Supply Voltage Variation: We systematically adjusted the supply voltage across a

predefined range while monitoring the corresponding changes in the oscillation
frequency. For each voltage level, we recorded the observed frequency.

4. Data Collection and Analysis: The data collected from varying the supply voltage
and measuring the corresponding oscillation frequency were analyzed. By plotting this
data, we were able to visually discern the relationship between supply voltage and
oscillation frequency.

5. Analysis of Results: Upon analysis, we observed a clear relationship between supply

voltage and oscillation frequency. Generally, an increase in supply voltage led to an
increase in the oscillation frequency, while a decrease in supply voltage resulted in a
decrease in frequency. This relationship is consistent with the behavior expected in ring
oscillator circuits.

Objective – 4:

The designed single-ended ring oscillator successfully achieved the target frequency of
400 MHz through careful sizing and optimization of inverter stages. This experiment
provided valuable insights into the design considerations and challenges associated with
high-frequency oscillator circuits.