Heaven’s Light is Our Guide

Rajshahi University of Engineering &

Technology
(RUET), Rajshahi

Department of Electrical and Electronic Engineering (EEE)

Experiment no.: 05
Name of the experiment: Experimental study of digital logic gate design using
PLC ladder diagram.

Course title: Embedded System Design Submitted by-

Sessional Name: MD. NAEEM HOSSAIN
Roll no.: 141004
Course no.: EEE-4210 Section: A
Class: 4th Year Even Semester
Date of experiment: 08-04-19
Session: 2014-15
Date of submission: 23-04-19

Year: 2019

Experiment no.: 05
Name of the experiment: Experimental study of digital logic gate design using
PLC ladder diagram.

Objectives: The objectives of this experiment are-

1. To design digital logic gates, i.e., AND, OR, NOT etc. using PLC ladder
diagrams.
2. To design counter/timer in WinProladder.
3. To implement a 4×1 multiplexer using PLC.

Required apparatus: Winproladder software

Introduction: A PLC is an industrial controlling device that continuously monitors

the state of input devices and make decisions based upon accustom program to
control the state of output devices.
Power

Input Module Output

CPU Module

Fig. 1: PLC block diagram.

Ladder diagram is a type of graphic language for automatic control systems. It had
been used for a long period since World War II. Until today, it is the oldest and
most popular language for automatic control systems. Originally there are only few
basic elements available such as A contact (Normally ON), B contact (Normally
OFF), output coil, timers and counters. Not until the appearance of microprocessor
based PLC, more elements for ladder diagram, such as differential contact,
retentive coil and other instructions that a conventional system can’t provide
became available.
The basic operating principle for both conventional and PLC ladder diagram is the
same. The main difference between the two systems is that the appearance of the
symbols for conventional ladder diagram are closer to the real devices, while for
PLC system, symbols are simplified for computer display. There are two types of
logic system available for ladder diagram logic namely combination logic and
sequential logic.
Buffer:

Input Outpu
t
0 0
1 1

AND:

Inputs Outpu
t
0 0 0
0 1 0
1 0 0
1 1 1

We can observe the other cases by the same procedure as previous one given.
OR:
Inputs Outpu
t
0 0 0
0 1 1
1 0 1
1 1 1

We can observe the other cases by the same procedure as previous one given.
NOT:
Input Outpu
t
0 1
1 0
NAND:
Inputs Outpu
t
0 0 1
0 1 1
1 0 1
1 1 0

We can observe the other cases by the same procedure as previous one given.

NOR:
Inputs Outpu
t
0 0 1
0 1 0
1 0 0
1 1 0
We can observe the other cases by the same procedure as previous one given.

XOR:
Inputs Outpu
t
0 0 0
0 1 1
1 0 1
1 1 0

We can observe the other cases by the same procedure as previous one given.

XNOR:
Inputs Outpu
t
0 0 1
0 1 0
1 0 0
1 1 1
We can observe the other cases by the same procedure as previous one given.

COUNTER:
TIMER:

4×1 multiplexer :
Discussion: In this experiment, a few digital logic gates were designed using
ladder diagrams in WinProladder. After that, the operation of counter/timer were
also observed in PLC. Finally, a 4×1 multiplexer was implemented using PLC
ladder diagram.