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Acer Compal La 5912p r1 Schematics
Acer Compal La 5912p r1 Schematics
1 1
Compal Confidential
2 2
3
2010-06-17 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 1 of 45
A B C D E
A B C D E
Danube
Compal Confidential AMD S1G4 Processor
Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2
Model Name : NEWX5 / PEW56 uPGA-638 Package Dual Channel BANK 0, 1, 2, 3 page 10,11
File Name : LA-5912P Champlain page 6,7,8,9 1.5V DDRIII 1066~1333MHz
1
P/N : DA60000FZ10 1
Hyper Transport Link
16 x 16
LVDS
page 16 Thermal Sensor Clock Generator
ATI RS880M
ADM1032 ICS9LPRS488
page 8 page 15
CRT uFCBGA-528
page 18
page 12,13,14 page 28 page 16 page 28 page 27 page 28 page 28
HDMI Conn. A link Express2 USB CMOS Bluetooth Mini 3G/GPS Card
page 17
Gen1 conn Camera Conn card WWAN Reader
X3 <Option>
(WL)X1 <Option>
USB port 0,1,2 USB port 5 USB port 12 USB port 8 USB port 9 USB port 6
2
ATI SB820M 3.3V 48MHz USB
2
Power Circuit
page 35,36,37,38,39,40,
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/06 Deciphered Date 2010/03/12 Title
41,42,43
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 2 of 45
A B C D E
5 4 3 2 1
D D
14.31818MHz
CLK_SBLINK_BCLK
MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N 100MHz
C
A_SODIMM
1066MHz
AMD CLK_NBGFX
AMD C
100MHz ATI
MEM_MB_CLK1_P/N S1G4 CPU_CLKP/N EXTERNAL
MEM_MB_CLK7_P/N
CPU SOCKET 200MHz CLK GEN. CLK_NBHT
NB
B_SODIMM
1066MHz SLG8SP626 / ICS9LPRS488 RS880M
100MHz
CLK_NB_14.318M
14.318MHZ
CLK_SBSRC_BCLK
CLK_48M_USB
CLK_48M_SD
48MHz
100MHz
48MHz
CLK_PCIE_WWAN
100MHz
CLK_PCIE_MINI1
100MHz
CLK_PCIE_LAN
B B
100MHz
GbE LAN
WWAN WLAN
CardReader BCM
Mini PCI Socket Mini PCI Socket
57780 AMD
ATI
SB
SB820M
RTC SATA
A A
32.768K Hz 25MHz
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU (1.375-1.5V) ON OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V)ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_VDDR 1.05V switched power rail ON OFF OFF
+0.75V 0.75V switched power rail for DDR terminator ON ON OFF Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Vcc 3.3V +/- 5%
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for MINI Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW 3.3V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+RTCVCC RTC power ON ON ON
2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 4 of 45
A B C D E
5 4 3 2 1
D D
VDDA18 0.64A
1.8V_S0 VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A
VDDG33 0.06A
PU6 +1.1VALW +1.1VALW 3.3V_S0 AVDD 0.125A
RT8209BGQW U36 VDDLT33 0A
SI4800BDY
No Use VDD18_MEM 1.8V 0.005A
+1.1VS VDD_MEM 1.8V 0.23A
C +1.5V +1.5VS C
PU19 U35
TSP51117RGYR SI4800BDY
+1VSG PCIE_VDDC 2 A
PU10 1.0V DP[F:A]_VDD10 230 mA VRAM 1GB
+1.8VS APL5913 DPLL_VDDC 125 mA
SPV10 100 mA 64Mx16 (K4B1G1646E) * 8
PU14 PU11
APL5913 MP2121DQ +1.5VS
1.5V VDDR1 TBD A 1.5V 2.4 A
PCIE_PVDD 40 mA
+1.8VSP2 +1.8VSP1 PCIE_VDDR 400 mA
TSVDD 5 mA
+3VALW VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
+INVPWR_B+ PU4 1.8V DP[F:A]_VDD18 330 mA
SN0806081 RHBR AVDD 70 mA
VDD1DI 45 mA
+5VALW U37 +3VS A2VDDQ 1.5 mA
SI1800BDY VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA
B LCD panel B
Delay +3VS_DELAY 3.3V VDDR3 60 mA
15.6" A2VDD 130 mA
U34
SI4800BDY +5VS
B+ 300mA
+3.3 350mA SouthBridge AMD SB820M
VDDIO_33_S
+3VALW VDDPL_33_USB_S
U25/U40 VDDAN_33_USB_S 0.2A
TPS2061DRG4 +USB_VCCA 3.3V_S5 VDDAN_33_S
VDDXL_33_S
+USB_VCCB
VDDIO_AZ_S
VDDCR_11_GBE_S
A Audio AMP Audio Codec Realtek EC LAN VDDRF_GBE_S A
USB X3 SATA ICS9LPRS488B Mini Card No Use VDDIO_33_GBE_S
TPA6017A2 ALC272 RTS5159 ENE KB926 BCM 57780 RTC VDDIO_GBE_S
VDDIO_18_FC
+5V Bettary
Dual+1 +5V 25mA +5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 500mA +3.3V 400mA +1.5VS 500mA
+3.3VS 300mA +3.3VS 3mA +3.3VS 1A 2.5~3.6V VDDBT_RTC_G
2.5A +3.3V +3.3VS 25mA +1.1V +3.3VALW 330mA BAT
1 1
+1.1VS
VLDT CAP.
250 mil
2 2 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
[12] H_CADIP[0..15] H_CADOP[0..15] [12]
10U_0805_10V4Z 10U_0805_10V4Z
H_CADIN[0..15] H_CADON[0..15] 1 1 2 2 2 2
[12] H_CADIN[0..15] H_CADON[0..15] [12]
FOX_PZ63823-284S-41F_Champlian
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 6 of 45
A B C D E
A B C D E
C8
FOX_PZ63823-284S-41F_Champlian FOX_PZ63823-284S-41F_Champlian
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 7 of 45
A B C D E
A B C D E
Champlain: C1E
C1E: LDT_REQ# no connect
+2.5VDDA
CLMC: LDT_REQ# connect to NB +1.5V
L1 VDDA=0.25A
+2.5VS 1 2 3300P_0402_50V7K
1
+ no support in S1g4
C11 4.7U_0805_10V4Z C12 C13 C14 R6
2
0.22U_0603_16V4Z 10K_0402_5%
220U_6.3V_M 2 2 2 R7 <BOM Structure>
2 2
1K_0402_5%
JCPU1D
B
1 1
1
Q1
E
F8 M11 CPU_THERMTRIP#_R 3 1 1 2
VDDA1 VSS H_THERMTRIP# [20]
C
F9 W18 R8 0_0402_5%
VDDA2 RSVD11 MMBT3904_NL_SOT23-3
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC 1 2
[15] CLK_CPU_BCLK CLKIN_H SVC CPU_SVC [43] MAINPWON [36,37,41]
C16 CPU_CLKIN_SC_N A8 A4 CPU_SVD R9 @ 0_0402_5%
CLKIN_L SVD CPU_SVD [43]
1
LDT_RST# B7 +1.5V 1 2
R10 H_PWRGD RESET_L R11 300_0402_5%
A7 PWROK
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R
LDTSTOP_L THERMTRIP_L H_PROCHOT#
C6 AC7
2
T2 PAD LDTREQ_L PROCHOT_L
[15] CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 PAD T3
C15 3900P_0402_50V7K +1.5V 1 2 CPU_SIC AF4 H_PROCHOT# 1 2
SIC H_PROCHOT_R# [19]
+1.5V R12 1 2 1K_0402_5% CPU_SID AF5 R13 0_0402_5%
R14 1K_0402_5% SID THERMDC_CPU
AE6 ALERT_L THERMDC W7
+1.5VS THERMDA_CPU
THERMDA W8 PROCHOT:
R15 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
+1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 Input: For HTC Function
HT_REF1
2
R17 CPU_VDD0_FB_H
Output: Over Temperature Condition
[43] CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 PAD T4
300_0402_5% [43] CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L PAD T11
1 FOX_PZ63823-284S-41F_Champlian
220_0402_5% R36
220_0402_5% R37
220_0402_5% R38
300_0402_5% R39
300_0402_5% R40
CPU_TEST22 1 2
R34 1K_0402_5%
1
2
CPU internal thermal sensor CPU_TEST24 1 2
R35 1K_0402_5%
CPU_TEST23 1 2
1 2 FDV301N, the Vgs is: R265 1K_0402_5%
PEW56@ JP2
min = 0.65V
2
1
C22 0.1U_0402_16V4Z
Typ = 0.85V @ @ @ @ 1 2
R41 R42 3 4
Max = 1.5V 5 6
+3VS 2 1 2 1 CPU_DBREQ# 1 R43 2
PEW56@ PEW56@ CPU_DBRDY 7 8 @ 0_0402_5%
31.6K_0402_1% 30K_0402_5% CPU_TCK
9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
15 16 @
2.09V for Gate CPU_TRST#
17 18
2
5
G
CPU_TDO U2
@ 19 20 LDT_RST#
2
P
CPU_SID 3 EC_SMB_DA SB_SID 21 22 HDT_RST# B
1 1 2 SB_SID [20] T0 SB 23 24 4 Y
R44 0_0402_5%
S
26 A 1 SB_PWRGD [13,20,29]
G
4 PEW56@ EC_SMB_DA2 4
1 2 TO EC
Q2 FDV301N_NL_SOT23-3 R45 0_0402_5% NC7SZ08P5X_NL_SC70-5
3
PEW56@ CONN@ SAMTEC_ASP-68200-07
2
G
@
CPU_SIC 3 EC_SMB_CK SB_SIC T0 SB
1 1
R46
2
0_0402_5%
SB_SIC [20] Security Classification Compal Secret Data Compal Electronics, Inc.
S
JCPU1F
+1.5V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
+CPU_CORE_NB F19 V11
VSS57 VSS122
F21 VSS58 VSS123 V13
1 1 1 1 1 1 F23 VSS59 VSS124 V15
C44 C45 C46 C47 C48 C50 1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C42 C43 C49 VSS60 VSS125
H7 VSS61 VSS126 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 VSS63 VSS128 Y23
2 2 2
H23 VSS64 VSS129 N6
J4 VSS65
FOX_PZ63823-284S-41F_Champlian
Under CPU Socket Athlon 64 S1
Processor Socket
+1.5V
C97
C98
C99
C100 0.1U_0402_16V7K
C101 0.1U_0402_16V7K
C96
Between CPU Socket and DIMM
+1.5V +CPU_VDDR 2 2 2 2 2 2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
3 @ @ @ @ @ @ 3
Near Power Supply
1 1 1 1 1 1
VDDR decoupling. 1
1
C51 C52 C53 C54 C354 C355 C55 1 1 1 1 1 1
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z C56 + 220U_6.3V_M 22U_0805_6.3V6M
2 2 2 2 2 2 2
2
For PVT Change as SF000002N00(H4.4)
180PF Qt'y follow the distance between
+1.5V +1.5V CPU socket and DIMM0. <2.5inch> +CPU_VDDR Reserve for EMI
1 1 2 2 1 1
C64 C65 C66 C67 C68 C69 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J C57 C58 C59 C60 C61 C62 C63 C70
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 1 1 2 2
2 2 2 2 2 2 2 2
+1.5V
Near CPU Socket Right side.
Change as SGA19331D10 (ESR9 ohm) for PVT +CPU_VDDR
1
1 1 1 1
+
C71 C72 C73 C74 C75 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 330U_D2_2V_Y C76 C77 C78 C79 C80 C81 C82 C83
2 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 9 of 45
A B C D E
A B C D E
JDIMM1
1 VREF_DQ VSS1 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS2 DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8
DQ1 VSS3 DDRA_SDQS0#
9 VSS4 DQS#0 10 DDRA_SDQS0# [7]
DDRA_SDM0 11 12 DDRA_SDQS0
DM0 DQS0 DDRA_SDQS0 [7] DDRA_SDQ[0..63]
13 VSS5 VSS6 14 DDRA_SDQ[0..63] [7]
DDRA_SDQ2 15 16 DDRA_SDQ6
DDRA_SDQ3 DQ2 DQ6 DDRA_SDQ7 DDRA_SDM[0..7]
17 DQ3 DQ7 18 DDRA_SDM[0..7] [7]
19 VSS7 VSS8 20
1 DDRA_SDQ8 DDRA_SDQ12 1
21 DQ8 DQ12 22
DDRA_SDQ9 23 24 DDRA_SDQ13
DQ9 DQ13 DDRA_SMA[0..15]
25 VSS9 VSS10 26 DDRA_SMA[0..15] [7]
DDRA_SDQS1# 27 28 DDRA_SDM1
[7] DDRA_SDQS1# DQS#1 DM1
DDRA_SDQS1 29 30 MEM_MA_RST#
[7] DDRA_SDQS1 DQS1 RESET# MEM_MA_RST# [7]
31 VSS11 VSS12 32
DDRA_SDQ10 33 34 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRA_SDQ16 39 40 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRA_SDQS2# 45 46 DDRA_SDM2
[7] DDRA_SDQS2# DQS#2 DM2
DDRA_SDQS2 47 48
[7] DDRA_SDQS2 DQS2 VSS17
49 50 DDRA_SDQ22
DDRA_SDQ18 VSS18 DQ22 DDRA_SDQ23
51 DQ18 DQ23 52
DDRA_SDQ19 53 54
DQ19 VSS19 DDRA_SDQ28
55 VSS20 DQ28 56
DDRA_SDQ24 57 58 DDRA_SDQ29 +VREF_CA +1.5V
DDRA_SDQ25 DQ24 DQ29 +VREF_DQ +1.5V
59 DQ25 VSS21 60
61 62 DDRA_SDQS3#
VSS22 DQS#3 DDRA_SDQS3# [7]
2
DDRA_SDM3 63 64 DDRA_SDQS3
DM3 DQS3 DDRA_SDQS3 [7]
2
65 66 R310
DDRA_SDQ26 VSS23 VSS24 DDRA_SDQ30 R48 1K_0402_1%
67 DQ26 DQ30 68
DDRA_SDQ27 69 70 DDRA_SDQ31 1K_0402_1%
DQ27 DQ31
71 72
1
VSS25 VSS26 +VREF_CA
1
+VREF_DQ
1000P_0402_50V7K
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDRA_CKE0 73 74 DDRA_CKE1
[7] DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 [7]
1000P_0402_50V7K
0.01U_0402_25V7K
4.7U_0805_10V4Z
75 VDD1 VDD2 76 1 2 1
2
77 78 DDRA_SMA15 1 2 1 C235 C351 C680
NC1 A15
2
2 DDRA_SBS2# DDRA_SMA14 C84 C85 C10 @ R315 2
[7] DDRA_SBS2# 79 BA2 A14 80
81 82 @ R49 1K_0402_1%
DDRA_SMA12 VDD3 VDD4 DDRA_SMA11 1K_0402_1% 2 1 2
83 A12/BC# A11 84
DDRA_SMA9 DDRA_SMA7 2 1 2
85 86
1
A9 A7
87 88
1
DDRA_SMA8 VDD5 VDD6 DDRA_SMA6
89 A8 A6 90
DDRA_SMA5 91 92 DDRA_SMA4
A5 A4
93 VDD7 VDD8 94
DDRA_SMA3 95 96 DDRA_SMA2
DDRA_SMA1 A3 A2 DDRA_SMA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRA_CLK0 101 102 DDRA_CLK1
[7] DDRA_CLK0 CK0 CK1 DDRA_CLK1 [7]
DDRA_CLK0# 103 104 DDRA_CLK1#
[7] DDRA_CLK0# CK0# CK1# DDRA_CLK1# [7]
105 VDD11 VDD12 106
DDRA_SMA10 107 108 DDRA_SBS1#
A10/AP BA1 DDRA_SBS1# [7]
DDRA_SBS0# 109 110 DDRA_SRAS#
[7] DDRA_SBS0# BA0 RAS# DDRA_SRAS# [7]
111 VDD13 VDD14 112
DDRA_SWE# 113 114 DDRA_SCS0#
[7] DDRA_SWE# WE# S0# DDRA_SCS0# [7]
DDRA_SCAS# 115 116 DDRA_ODT0
[7] DDRA_SCAS# CAS# ODT0 DDRA_ODT0 [7]
117 VDD15 VDD16 118
DDRA_SMA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 [7]
DDRA_SCS1# 121 122
[7] DDRA_SCS1# S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CA +1.5V
NCTEST VREF_CA
127 VSS27 VSS28 128
1000P_0402_50V7K
DDRA_SDQ32 129 130 DDRA_SDQ36 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
131 DQ33 DQ37 132 1 2 2 2 2 2 2 2 2 2 2
C89
0.01U_0402_16V7K
4 R51 0.01U_0402_16V7K 4
205 G1 G2 206
+3VS
10K_0402_5% FOX_AS0A626-U8SN-7F 0.01U_0402_16V7K
CONN@
2
1 1
C90 C91
Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/10/06 2010/03/12 Title
2
2.2U_0805_10V6K 2 Issued Date Deciphered Date
DIMM_A STD H:8mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
<Address: 00> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 10 of 45
A B C D E
A B C D E
JDIMM2
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5
5 DQ0 DQ5 6
DDRB_SDQ1 7 8
DQ1 VSS3 DDRB_SDQS0#
9 VSS4 DQS#0 10 DDRB_SDQS0# [7]
DDRB_SDM0 11 12 DDRB_SDQS0
DM0 DQS0 DDRB_SDQS0 [7] DDRB_SDQ[0..63]
13 VSS5 VSS6 14 DDRB_SDQ[0..63] [7]
DDRB_SDQ2 15 16 DDRB_SDQ6
DDRB_SDQ3 DQ2 DQ6 DDRB_SDQ7 DDRB_SDM[0..7]
17 DQ3 DQ7 18 DDRB_SDM[0..7] [7]
19 VSS7 VSS8 20
1 DDRB_SDQ8 DDRB_SDQ12 1
21 DQ8 DQ12 22
DDRB_SDQ9 23 24 DDRB_SDQ13
DQ9 DQ13 DDRB_SMA[0..15]
25 VSS9 VSS10 26 DDRB_SMA[0..15] [7]
DDRB_SDQS1# 27 28 DDRB_SDM1
[7] DDRB_SDQS1# DQS#1 DM1
DDRB_SDQS1 29 30 MEM_MB_RST#
[7] DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# [7]
31 VSS11 VSS12 32
DDRB_SDQ10 33 34 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRB_SDQ16 39 40 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRB_SDQS2# 45 46 DDRB_SDM2
[7] DDRB_SDQS2# DQS#2 DM2
DDRB_SDQS2 47 48
[7] DDRB_SDQS2 DQS2 VSS17
49 50 DDRB_SDQ22
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
DDRB_SDQ19 53 54
DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56
DDRB_SDQ24 57 58 DDRB_SDQ29
DDRB_SDQ25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDRB_SDQS3#
VSS22 DQS#3 DDRB_SDQS3# [7]
DDRB_SDM3 63 64 DDRB_SDQS3
DM3 DQS3 DDRB_SDQS3 [7]
65 VSS23 VSS24 66
DDRB_SDQ26 67 68 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDRB_CKE0 73 74 DDRB_CKE1
[7] DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 [7]
75 VDD1 VDD2 76
77 78 DDRB_SMA15
2 DDRB_SBS2# NC1 A15 DDRB_SMA14 2
[7] DDRB_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 A12/BC# A11 DDRB_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6 +VREF_DQ +VREF_CA
DDRB_SMA5 A8 A6 DDRB_SMA4
91 A5 A4 92
93 VDD7 VDD8 94
DDRB_SMA3 95 96 DDRB_SMA2 +VREF_DQ +VREF_CA
DDRB_SMA1 A3 A2 DDRB_SMA0
97 A1 A0 98
1000P_0402_50V7K
1000P_0402_50V7K
99 VDD9 VDD10 100
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
DDRB_CLK0 101 102 DDRB_CLK1
[7] DDRB_CLK0 CK0 CK1 DDRB_CLK1 [7]
DDRB_CLK0# 103 104 DDRB_CLK1# 1 1 1 1 1 1
[7] DDRB_CLK0# CK0# CK1# DDRB_CLK1# [7]
105 106 C92 C93 C682 C352 C353 C683
DDRB_SMA10 VDD11 VDD12 DDRB_SBS1#
107 A10/AP BA1 108 DDRB_SBS1# [7]
DDRB_SBS0# 109 110 DDRB_SRAS#
[7] DDRB_SBS0# BA0 RAS# DDRB_SRAS# [7] 2 2 2 2 2 2
111 VDD13 VDD14 112
DDRB_SWE# 113 114 DDRB_SCS0#
[7] DDRB_SWE# WE# S0# DDRB_SCS0# [7]
DDRB_SCAS# 115 116 DDRB_ODT0
[7] DDRB_SCAS# CAS# ODT0 DDRB_ODT0 [7]
117 VDD15 VDD16 118
DDRB_SMA13 119 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 [7]
DDRB_SCS1# 121 122
[7] DDRB_SCS1# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_50V7K
DDRB_SDQ32 129 130 DDRB_SDQ36
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
131 DQ33 DQ37 132 1
133 134 C94
DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4
[7] DDRB_SDQS4# 135 DQS#4 DM4 136
DDRB_SDQS4 137 138
[7] DDRB_SDQS4 DQS4 VSS31 2
139 140 DDRB_SDQ38
DDRB_SDQ34 VSS32 DQ38 DDRB_SDQ39
141 DQ34 DQ39 142
3 DDRB_SDQ35 3
143 DQ35 VSS33 144
145 146 DDRB_SDQ44
DDRB_SDQ40 VSS34 DQ44 DDRB_SDQ45
147 DQ40 DQ45 148
DDRB_SDQ41 149 150
DQ41 VSS35 DDRB_SDQS5#
151 VSS36 DQS#5 152 DDRB_SDQS5# [7]
DDRB_SDM5 153 154 DDRB_SDQS5 +1.5V
DM5 DQS5 DDRB_SDQS5 [7]
155 VSS37 VSS38 156
DDRB_SDQ42 157 158 DDRB_SDQ46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
159 DQ43 DQ47 160 2 2 2 2 2 2 2 2 2 2
161 VSS39 VSS40 162
DDRB_SDQ48 163 164 DDRB_SDQ52 C677 C670 C666 C671 C667 C672 C668 C673 C669 C674
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 DQ49 DQ53 166
1 1 1 1 1 1 1 1 1 1
167 VSS41 VSS42 168
DDRB_SDQS6# 169 170 DDRB_SDM6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
[7] DDRB_SDQS6# DQS#6 DM6
DDRB_SDQS6 171 172
[7] DDRB_SDQS6 DQS6 VSS43
173 174 DDRB_SDQ54
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 DQ50 DQ55 176
DDRB_SDQ51 177 178
DQ51 VSS45 DDRB_SDQ60 +1.5V
179 VSS46 DQ60 180
DDRB_SDQ56 181 182 DDRB_SDQ61 +0.75VS
DDRB_SDQ57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDRB_SDQS7# 0.1U_0402_16V4Z
VSS48 DQS#7 DDRB_SDQS7# [7]
DDRB_SDM7 187 188 DDRB_SDQS7 2 2 1 1
DM7 DQS7 DDRB_SDQS7 [7]
189 VSS49 VSS50 190
DDRB_SDQ58 191 192 DDRB_SDQ62 C676 C675 C925 + C86
DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63 @ 330U_X_2VM_R6M
193 DQ59 DQ63 194
R52 10K_0402_5% 1 1 2
195 VSS51 VSS52 196
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2
1 2 197 SA0 EVENT# 198 PAD T10
+3VS 199 VDDSPD SDA 200 SB_SMDAT0 [10,15,20,27]
201 SA1 SCL 202 SB_SMCLK0 [10,15,20,27] Place near DIMM2
203 VTT1 VTT2 204 +0.75VS
1
4 R53 4
205 G1 G2 206
10K_0402_5% FOX_AS0A626-U4SN-7F
CONN@
2
DIMM_B STD H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 11 of 45
A B C D E
A B C D E
U3B
D4 GFX_RX0P GFX_TX0P A5 GMCH_HDMI_TXD2+ [17]
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 GMCH_HDMI_TXD2- [17]
A3 GFX_RX1P GFX_TX1P A4 GMCH_HDMI_TXD1+ [17]
B3 GFX_RX1N GFX_TX1N B4 GMCH_HDMI_TXD1- [17]
1 1
C2 GFX_RX2P GFX_TX2P C3 GMCH_HDMI_TXD0+ [17]
C1 GFX_RX2N GFX_TX2N B2 GMCH_HDMI_TXD0- [17]
E5 GFX_RX3P GFX_TX3P D1 GMCH_HDMI_TXC+ [17]
F5 GFX_RX3N GFX_TX3N D2 GMCH_HDMI_TXC- [17]
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 GFX_RX6P GFX_TX6P F1
J5 GFX_RX6N GFX_TX6N F2
J7 GFX_RX7P GFX_TX7P H4
J8 GFX_RX7N GFX_TX7N H3
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 GFX_RX9N GFX_TX9N J1
[25] PCIE_PTX_C_IRX_P0 1 2 GPP0P AE3 GPP_RX0P GPP_TX0P AC1 PCIE_ITX_PRX_P0 C127 1 2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_P0 [25]
[25] PCIE_PTX_C_IRX_N0 2 GPP0N AD4
R54 1 0_0402_5%
GPP_RX0N GPP_TX0N AC2 PCIE_ITX_PRX_N0 C128 1 2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_N0 [25] GLAN
R55 0_0402_5% AE2 AB4 PCIE_ITX_PRX_P1 C129 1 2 0.1U_0402_16V7K
2 [27] PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 [27] 2
AD3 AB3 PCIE_ITX_PRX_N1 C130 1 2 0.1U_0402_16V7K WLAN
[27] PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 [27]
AD1 GPP_RX2P GPP_TX2P AA2
PCIE_PTX_C_IRX_P0 1 @
AD2
PCIE_PTX_C_IRX_P3V5 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1
PCIE_ITX_PRX_P3 C131 1@ 0.1U_0402_16V7K PCIE_ITX_C_PRX_P0
2
PCIE_PTX_C_IRX_N0 1R56 @ 0_0402_5% PCIE_PTX_C_IRX_N3 GPP_RX3P GPP_TX3P Y1
PCIE_ITX_PRX_N3 C132 @1
2 Reserve for LAN debug
2 W6 GPP_RX3N GPP_TX3N Y2 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_N0
R57 0_0402_5% U5 Y4
GPP_RX4P GPP_TX4P H_CADOP[0..15] H_CADIP[0..15]
R56,R57 close to R54,R55 U6 GPP_RX4N GPP_TX4N Y3 C131,C132 close to C127,C128 [6] H_CADOP[0..15] H_CADIP[0..15] [6]
U8 GPP_RX5P GPP_TX5P V1
U7 V2 H_CADON[0..15] H_CADIN[0..15]
GPP_RX5N GPP_TX5N [6] H_CADON[0..15] H_CADIN[0..15] [6]
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 12 of 45
A B C D E
A B C D E
0.1U_0402_16V4Z +1.8VS
2
1 2
R417 R63 U4
5
+1.1VS +NB_PLLVDD @ C684 2.2K_0402_5% NC7SZ08P5X_NL_SC70-5
5
L2 C696 C679 300_0402_5% NB_PWRGD 2
P
B
1 2 2 4NB_PWRGD_R
P
1
1
+3VS 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K B NB_LDTSTOP# Y
1 1 Y 4 [8,20,29] SB_PWRGD 1 A
G
FBMA-L11-160808-221LMT 0603 L3 1 @
[8,19] LDT_STOP# A
G
C141 C142 1 2 C144 C143 U8
3
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z
+AVDD1
1 1 1 1
3
1 2 2 FBMA-L11-160808-221LMT 0603 NC7SZ08P5X_NL_SC70-5 1
@
2.2U_0603_6.3V4Z
2 2 2 2
1U_0402_6.3V4Z R64
1
@
2
0_0402_5%
For PVT 0118
+1.8VS
L4 AMD suggest
+1.8VS +NB_HTPVDD 1 2 +AVDDDI
L5 1
125mA
1 2 FBMA-L11-160808-221LMT 0603
1 1 C145
FBMA-L11-160808-221LMT 0603 0.1U_0402_16V4Z
C146 C147 2 U3C
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F12 A22 TXOUT0+ [16]
2 2 +1.8VS AVDD1(NC) TXOUT_L0P(NC)
20mA E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 TXOUT0- [16]
F14 AVDDDI(NC) TXOUT_L1P(NC) A21 TXOUT1+ [16]
L6 4mA G15 B21 TXOUT1- [16]
+AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
1 2 H15 AVDDQ(NC) TXOUT_L2P(NC) B20 TXOUT2+ [16]
1 1 H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 TXOUT2- [16]
FBMA-L11-160808-221LMT 0603 A19
C148 C149 TXOUT_L3P(NC)
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
+1.8VS +VDDA18HTPLL 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z
CRT/TVOUT
F17 Y(DFT_GPIO2)
L7 2 2
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 TZOUT0+ [16]
1 2 TXOUT_U0N(NC) A18 TZOUT0- [16]
1 1 GMCH_CRT_R G18 A17 TZOUT1+ [16]
[18] GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
FBMA-L11-160808-221LMT 0603 G17 B17 TZOUT1- [16] L8
C150 C151 GMCH_CRT_G REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) +VDDLTP18
[18] GMCH_CRT_G E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20 TZOUT2+ [16] 1 2 +1.8VS
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F18 D21 TZOUT2- [16] 1 1
2 2 GMCH_CRT_B GREENb(NC) TXOUT_U2N(NC) FBMA-L11-160808-221LMT 0603
[18] GMCH_CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 D19 C152 C153
BLUEb(NC) TXOUT_U3N(NC) 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
GMCH_CRT_HSYNC 2 2
[14,18] GMCH_CRT_HSYNC A11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) B16 TXCLK+ [16]
2 GMCH_CRT_VSYNC 2
[14,18] GMCH_CRT_VSYNC B11 DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 TXCLK- [16]
GMCH_CRT_CLK F8 D16 TZCLK+ [16]
+1.8VS +VDDA18PCIEPLL [18] GMCH_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
GMCH_CRT_DATA E8 D17 TZCLK- [16]
[18] GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
L9
1 2 1 2 DAC_RSET G14 15mA L10
R65 715_0402_1% DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLT18
FBMA-L11-160808-221LMT 0603
1 1
+NB_PLLVDD
65mA VDDLTP18(NC) A13 1 2
BLM18AG601SN1D_2P
+1.8VS
+NB_PLLVDD A12 PLLVDD(NC) VSSLTP18(NC) B13 1 1
C154 C155 +NB_HTPVDD +NB_HTPVDD 20mAD14 300mA C156
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z PLLVDD18(NC) +VDDLT18 0.1U_0402_16V4Z C157
B12 A15
LVTM
2 2 PLLVSS(NC) VDDLT18_1(NC) 4.7U_0805_10V4Z
20mA B15
PLL PWR
VDDLT18_2(NC) 2 2
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
120mA VDDLT33_2(NC) B14
+VDDA18PCIEPLL D7 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
R66 0_0402_5% D15
NB_RESET# VSSLT2(VSS)
[14,19,29] A_RST# 1 2 D8 SYSRESETb VSSLT3(VSS) C16
1 2 NB_PWRGD_R A10 C18
[20] NB_PWRGD POWERGOOD VSSLT4(VSS)
R67 0_0402_5% NB_LDTSTOP# C10 C20
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
For PVT 0118 C12 E20
PM
ALLOW_LDTSTOP VSSLT6(VSS)
close NB +1.8VS
R68
2 1
300_0402_5% VSSLT7(VSS) C22
[15] CLK_NBHT C25 HT_REFCLKP
[15] CLK_NBHT# C24 HT_REFCLKN
CLK_NB_14.318M 1 2
[15] CLK_NB_14.318M
[19] NB_DISP_CLKP R8401 EXT@ 2 0_0402_5% NB_DISP_CLKP_R E11 REFCLK_P/OSCIN(OSCIN)
CLOCKs
[19] NB_DISP_CLKN R1101 INT@ 2 0_0402_5% NB_DISP_CLKN_R F11 E9 GMCH_ENVDD [16]
R107 INT@ 0_0402_5% REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP) F7
CLK_NBGFX T2 G12 VARY_ENBKL R71 1 UNVB@ 2 0_0402_5% ENBKL [29]
[15] CLK_NBGFX GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2)
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1 2 1 2 CLK_NBGFX# T1
[15] CLK_NBGFX# GFX_REFCLKN
1
+1.1VS R69 EXT@ R70 EXT@ R72 1 VB@ 2 0_0402_5% GMCH_INVT_PWM [16]
4.7K_0402_5% 4.7K_0402_5% R83 1 2 4.7K_0402_5% U1
+3VS R106 1 INT@ 4.7K_0402_5% GPP_REFCLKP R76 1 VB@
2 U2 GPP_REFCLKN 2 0_0402_5%
INT@ close NB
3 If support VB, pop VB@ and reserve R71 3
[15] CLK_SBLINK_BCLK V4
2
R77 GMCH_LCD_CLK GPPSB_REFCLKP(SB_REFCLKP)
1 2 4.7K_0402_5% [15] CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN) R73 R74 R75
R78 1 2 4.7K_0402_5% GMCH_LCD_DATA [16] GMCH_LCD_CLK
GMCH_LCD_CLK B9 I2C_CLK
GMCH_LCD_DATA
R79 1 2 4.7K_0402_5% GMCH_CRT_CLK
[16] GMCH_LCD_DATA
GMCH_HDMI_DATA
A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
GMCH_HDMI_DET [17]
[17] GMCH_HDMI_DATA DDC_DATA0/AUX0N(NC) HPD(NC)
@ GMCH_HDMI_CLK A8 @
[17] GMCH_HDMI_CLK DDC_CLK0/AUX0P(NC)
R80 1 2 4.7K_0402_5% GMCH_CRT_DATA B7 D12 1 2 SUS_STAT# [20] To SB
@ DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) R81 0_0402_5%
1 2 A7 DDC_DATA1/AUX1N(NC)
R82 2K_0402_5% AE8 SUS_STAT_R# [14] Strap pin
POWER_SEL THERMALDIODE_P
[40] POWER_SEL B10 STRP_DATA THERMALDIODE_N AD8
4 4
+1.8VS
1
R90
1K_0402_5%
R91 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 NB_ALLOW_LDTSTOP 2009/10/06 2010/03/12 Title
[19] ALLOW_LDTSTOP Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 13 of 45
A B C D E
A B C D E
600mA
L12 D23 PART 6/6 B1
C165 C166 C159 C167 C200 VSSAHT2 VSSAPCIE2
1 2 +1.1VS E22 VSSAHT3 VSSAPCIE3 D3
FBMA-L11-201209-221LMA30T_0805 G22 D5
2 2 2 2 2 U3E VSSAHT4 VSSAPCIE4
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2.5A +VDDA11PCIE C160
G24 VSSAHT5 VSSAPCIE5 E4
J17 VDDHT_1 VDDPCIE_1 A6 1 2 10U_0805_10V4Z G25 VSSAHT6 VSSAPCIE6 G1
1 C162 1
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1 2 10U_0805_10V4Z H19 VSSAHT7 VSSAPCIE7 G2
L16 VDDHT_3 VDDPCIE_3 C6 J22 VSSAHT8 VSSAPCIE8 G4
L13 1U_0402_6.3V4Z M16 D6 L17 H7
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C163 VSSAHT9 VSSAPCIE9
2 1 P16 VDDHT_5 VDDPCIE_5 E6 1 2 4.7U_0805_10V4Z L22 VSSAHT10 VSSAPCIE10 J4
R16 VDDHT_6 VDDPCIE_6 F6 L24 VSSAHT11 VSSAPCIE11 R7
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 T16 G7 C168 1 2 1U_0402_6.3V4Z L25 L1
VDDHT_7 VDDPCIE_7 C171 VSSAHT12 VSSAPCIE12
700mA VDDPCIE_8 H8 1 2 1U_0402_6.3V4Z M20 VSSAHT13 VSSAPCIE13 L2
C164 C169 C170 C161 C201 H18 J9 N22 L4
VDDHTRX_1 VDDPCIE_9 VSSAHT14 VSSAPCIE14
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 P20 VSSAHT15 VSSAPCIE15 L7
2 2 2 2 2 C172
F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z R19 VSSAHT16 VSSAPCIE16 M6
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 L9 C173 0.1U_0402_16V4Z R22 N4
VDDHTRX_4 VDDPCIE_12 VSSAHT17 VSSAPCIE17
D22 VDDHTRX_5 VDDPCIE_13 P9 R24 VSSAHT18 VSSAPCIE18 P6
B23 VDDHTRX_6 VDDPCIE_14 R9 R25 VSSAHT19 VSSAPCIE19 R1
A23 VDDHTRX_7 VDDPCIE_15 T9 H20 VSSAHT20 VSSAPCIE20 R2
L14 680mA V9 U22 R4
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSSAHT21 VSSAPCIE21
+1.1VS 2 1 AE25 VDDHTTX_1 VDDPCIE_17 U9 V19 VSSAHT22 VSSAPCIE22 V7
GROUND
AD24 VDDHTTX_2 W22 VSSAHT23 VSSAPCIE23 U4
FBMA-L11-201209-221LMA30T_0805 2 1 1 1 1 1 1 AC23 K12 W24 V8
C261 C174 VDDHTTX_3 VDDC_1 VSSAHT24 VSSAPCIE24
AB22 VDDHTTX_4 VDDC_2 J14 W25 VSSAHT25 VSSAPCIE25 V6
@ C175 C176 C177 C178 C202 AA21 U16 Y21 W1
10U_0805_10V4Z VDDHTTX_5 VDDC_3 VSSAHT26 VSSAPCIE26
Y20 VDDHTTX_6 VDDC_4 J11 AD25 VSSAHT27 VSSAPCIE27 W2
1 2 2 2 2 2 2 +NB_CORE
W19 VDDHTTX_7 VDDC_5 K15 VSSAPCIE28 W4
POWER
0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 L12 W7
4.7U_0603_6.3V6K 0.1U_0402_16V4Z VDDHTTX_8 VDDC_6 VSS11 VSSAPCIE29
U17 VDDHTTX_9 VDDC_7 L14 10A M14 VSS12 VSSAPCIE30 W8
T17 VDDHTTX_10 VDDC_8 L11 N13 VSS13 VSSAPCIE31 Y6
C189
R17 VDDHTTX_11 VDDC_9 M13 P12 VSS14 VSSAPCIE32 AA4
P17 VDDHTTX_12 VDDC_10 M15 P15 VSS15 VSSAPCIE33 AB5
M17 VDDHTTX_13 VDDC_11 N12 R11 VSS16 VSSAPCIE34 AB1
C191
C182
C187
C193
C194
C180
C188
C183
C195
C184
C196
L15 700mA N14 1 R14 AB7
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS17 VSSAPCIE35
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 T12 VSS18 VSSAPCIE36 AC3
FBMA-L11-201209-221LMA30T_0805 P10 P13 + U14 AC4
VDDA18PCIE_2 VDDC_14 VSS19 VSSAPCIE37
220U_C6_6.3V_M_R15
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 U11 VSS20 VSSAPCIE38 AE1
10U_0805_10V4Z
10U_0805_10V4Z
2 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 U15 VSS21 VSSAPCIE39 AE4
C181 C179 C192 C185 C190 C186 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 V12 VSS22 VSSAPCIE40 AB2
W9 VDDA18PCIE_6 VDDC_18 T11 W11 VSS23
4.7U_0603_6.3V6K 2 2 2 2 2 2
H9 VDDA18PCIE_7 VDDC_19 T15 W15 VSS24
0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 AC12 AE14
4.7U_0603_6.3V6K VDDA18PCIE_8 VDDC_20 VSS25 VSS1
R10 VDDA18PCIE_9 VDDC_21 T14 AA14 VSS26 VSS2 D11
Y9 VDDA18PCIE_10 VDDC_22 J16 Y18 VSS27 VSS3 G8
AA9 VDDA18PCIE_11 23mA AB11 VSS28 VSS4 E14
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 AB15 VSS29 VSS5 E15
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11 AB17 VSS30 VSS6 J15
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11 AB19 VSS31 VSS7 J12
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10 AE20 VSS32 VSS8 K14
10mA VDD_MEM5(NC) AB10 AB21 VSS33 VSS9 M11
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10 K11 VSS34 VSS10 L15
G9 VDD18_2 60mA RS780M_FCBGA528
AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 +3VS
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12
5mA RS780M_FCBGA528
1 1 RS880 A11(SA000032710)
1
C197 C198 C199
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RS880 A11(SA000032710) 2 2
2
3 U3D 3
PAR 4 OF 6
Side port and Strap setting AB12
AE16
V11
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
AA18
AA20
AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
Debug Mode AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
[13,18] GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC) AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
R92 3K_0402_5% AD15 AD19
1 : Disable MEM_A9(NC) MEM_DQ9/DVO_D5(NC)
SBD_MEM/DVO_I/F
2 1 AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
R93 @ 3K_0402_5% 0 : Enable AE13 AC18
MEM_A11(NC) MEM_DQ11/DVO_D7(NC)
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
DFT_GPIO1: LOAD_EEPROM_STRAPS AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
Load EEPROM Strap AE17 MEM_BA1(NC)
Selects Loading of STRAPS from EPROM AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
D1 @ W18
CH751H-40_SC76
1 : Bypass the loading of EEPROM straps and use Hardware Default Values MEM_DQS0N/DVO_IDCKN(NC)
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
2 1 0 : I2C Master can load strap values from EEPROM if connected, or use Y12 AE21
[13] SUS_STAT_R# A_RST# [13,19,29] MEM_CASb(NC) MEM_DQS1N(NC)
default values if not connected AD18 MEM_WEb(NC)
2 1 AB13 MEM_CSb(NC) MEM_DM0(NC) W17
R264 @ 3K_0402_5% AB18 AE19
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
V14 MEM_ODT(NC) 15mA
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
Enable Side Port Memory W14 MEM_CKN(NC) 26mA
Enable Side Port Memory IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
4 RS880: HSYNC# 4
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
[13,18] GMCH_CRT_HSYNC 2 1 +3VS 0: Enable Register Readback of strap:
R94 3K_0402_5% RS780M_FCBGA528
@ 1 : Disable NB_CLKCFG:CLK_TOP_SPARE_D[1]
2
R95
1
3K_0402_5% RS880 A11(SA000032710)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 14 of 45
A B C D E
5 4 3 2 1
+VDDCLK_IO +3VS_CLK
EXT@ L54 EXT@ L55
+1.1VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 C515 C516 C517 C518 C519 C520 C521 FBMA-L11-201209-221LMA30T_0805 C522 C523 C524 C525 C526 C527 C528 C529 C530 C531 C532
EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@
D 1U_0402_6.3V4Z D
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U CLOSE PIN 69
L56 EXT@
+3VS 1 2 +3VS_CLKVDDA
FBMA-L11-201209-221LMA30T_0805 +3VS_CLK
1 1 U17
C533 EXT@
1
EXT@ C534
22U_0805_6.3V6M
2 2
0.1U_0402_16V4Z ICS 9LPRS488 R236
49 1 EXT@ 8.2K_0402_5%
VDDA SMBCLK SB_SMCLK0 [10,11,20,27]
48 GNDA SMBDAT 2 SB_SMDAT0 [10,11,20,27]
2
+3VS_CLK 62 41 SRC_SLOW SRC_SLOW
VDDREF SB_SRC_SLOW# R98
66 GNDREF 1 INT@ 2 0_0402_5%
CPU_HT_CLKP [19]
EXT@ 2 1 R108 1 2 0_0402_5%
CPU_HT_CLKN [19]
1
C535 0.1U_0402_16V4Z INT@
+VDDCLK_IO 12 56 R237
VDDSRC_IO CPUKG0T_LPRS CLK_CPU_BCLK [8]
18 55 CPU INT@ 8.2K_0402_5%
VDDSRC_IO CPUKG0C_LPRS CLK_CPU_BCLK# [8]
28 VDDATIG_IO
37
2
VDDSB_SRC_IO
53 VDDCPU_IO HTT0T_LPRS / 66 M 60 CLK_NBHT [13]
+3VS_CLK HTT0C_LPRS / 66 M 59 CLK_NBHT# [13] NB HT
C R96 C
+3VS_CLK 3 VDDDOT 1 INT@ 2 0_0402_5%
NB_HT_CLKP [19]
17 40 R97 1 2 0_0402_5%
VDDSRC SB_SRC0T_LPRS NB_HT_CLKN [19]
29 39 INT@
VDDATIG SB_SRC0C_LPRS +3VS_CLK
R238 8.2K_0402_5%
R239 8.2K_0402_5%
38 VDDSB_SRC
44 VDDSATA
2
54 VDDCPU SB_SRC1T_LPRS 35
L57 61 34
EXT@ EXT@ VDDHTT SB_SRC1C_LPRS
1 2 69 VDD48
BLM18AG601SN1D_2P
2
EXT@ 33 CLK_NBGFX [13]
1
1
ATIG1T_LPRS
Mini Card1 [27] MINI1_CLKREQ# 51 CLKREQ1# ATIG1C_LPRS 30
SEL_SATA
R111 50 CLKREQ2#
[20] LAN_CLKREQ#_I 1 INT@ 2 0_0402_5%
ATIG2T_LPRS 26 R100 1 INT@ 2 0_0402_5%
GPP_CLK1P [19]
27M_SEL
2
43 25 R101 1 2 0_0402_5%
CLKREQ3# ATIG2C_LPRS GPP_CLK1N [19]
[20] MINI1_CLKREQ#_I 1 INT@ 2 0_0402_5% INT@ R242
42 CLKREQ4# 8.2K_0402_5%
R112 23 EXT@
SRC0T_LPRS CLK_PCIE_LAN [25]
22 CLK_PCIE_LAN# [25] GLAN
1
SRC0C_LPRS
27M_SEL 63 21
REF2/SEL_27 SRC1T_LPRS CLK_PCIE_MINI1 [27]
1 2 SRC1C_LPRS 20 CLK_PCIE_MINI1# [27] MiniCard_1
R243 90.9_0402_1% SEL_SATA 64
EXT@ REF1/SEL_SATA CLK_XTAL_OUT
1 2 CLK_14.318M 65 16 R102 1 INT@ 2 0_0402_5%
[13] CLK_NB_14.318M REF0/SEL_HTT66 SRC2T_LPRS GPP_CLK3P [19]
R244 EXT@ 158_0402_1% 15 R103 1 2 0_0402_5% CLK_XTAL_IN
SRC2C_LPRS GPP_CLK3N [19]
INT@
B B
71 48MHz_0 SRC3T_LPRS 14 change to SJ100009R00
SRC3C_LPRS 13
2 1 CLK_48M 70
[20] CLK_48M_USB 48MHz_1 Y2
R246 EXT@ 33_0402_5%
SRC4T_LPRS 10 CLK_SBLINK_BCLK [13] 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 15 of 45
5 4 3 2 1
5 4 3 2 1
1
W=60mils 43 4 +LCDVDD_L 2 @ 1 +LCDVDD
R250 G3 4
44 G4 5 5 +LCDVDD R841 0_0603_5%
300_0603_5% 45 6
G5 6
1
1 46 G6 7 7 +3VS
R251 C538 8 INVT_PWM
2
8 DISPOFF#
100K_0402_5% 9 9
4.7U_0805_10V4Z 10 GMCH_LCD_CLK
2 10 GMCH_LCD_CLK [13]
11 GMCH_LCD_DATA
GMCH_LCD_DATA [13]
2
11
12 12 DAC_BRIG [29]
3
D D S
TXOUT0- D
13 13 TXOUT0- [13]
AO3413_SOT23-3
G
Q11 2 2 1 2 14 TXOUT0+
Q13 14 TXOUT0+ [13]
G R252 1K_0402_5% 15
15 TXOUT1-
S 1
D 16 TXOUT1- [13]
1
2N7002_SOT23 C539 +LCDVDD 16 TXOUT1+
17 17 TXOUT1+ [13]
W=60mils 18 18
1
D Q23 0.047U_0402_16V7K TXOUT2-
19 19 TXOUT2- [13]
GMCH_ENVDD 2 TXOUT2+
[13] GMCH_ENVDD 2
G
<NCQD0 use> 20 20 TXOUT2+ [13]
1 1 21 21
1 R507 2 S 2N7002_SOT23 C540 C541 22 TXCLK-
TXCLK- [13]
3
100K_0402_5% 22 TXCLK+
23 23 TXCLK+ [13]
4.7U_0805_10V4Z 0.1U_0402_16V4Z 24
2 2 24 TZOUT0-
25 25 TZOUT0- [13]
26 TZOUT0+
26 TZOUT0+ [13]
27 R842 2 @ 1 0_0402_5%
27 LOCAL_DIM [29]
28 TZOUT1-
28 TZOUT1- [13]
29 TZOUT1+
29 TZOUT1+ [13]
30 R843 2 @ 1 0_0402_5%
30 COLOY_ENG_EN [29]
31 TZOUT2-
31 TZOUT2- [13]
32 TZOUT2+
32 TZOUT2+ [13]
33 33
+3VS 34 TZCLK-
+LCDVDD 34 TZCLK- [13]
35 TZCLK+
+INVPWR_B+ B+ 35 TZCLK+ [13]
36 36
1
37 37 +3VS
L58 2 1 R121 38 USB20_CMOS_N5 R256 2 1 0_0402_5%
38 USB20_N5 [20]
W=40mils FBMA-L11-201209-221LMA30T_0805 D9 @ 39 USB20_CMOS_P5 R257 2 1 0_0402_5%
39 USB20_P5 [20]
CH751H-40PT_SOD323-2 4.7K_0402_5% 1 1 40
L59 2 @ C546 C547 40
1
2
FBMA-L11-201209-221LMA30T_0805 BKOFF# 1 2 DISPOFF# IPEX_20143-040E-20F
[29] BKOFF#
1 1 10U_0805_10V4Z 0.1U_0402_16V4Z CONN@
C544 C545 R172 1 2 2
2 0_0402_5%
C C
680P_0402_50V7K 68P_0402_50V8J R171 1 2 10K_0402_5% D14 @
2 2 USB20_CMOS_N5
6 CH3 CH2 3
+3VS 5 Vp Vn 2
@
DAC_BRIG 1 2 USB20_CMOS_P54 1
C542 220P_0402_50V7K CH4 CH1
INVT_PWM 1 2 CM1293-04SO_SOT23-6
C543 220P_0402_50V7K
DISPOFF# 1 2
EC_INVT_PWM 1 UNVB@ 2 INVT_PWM C548 220P_0402_50V7K
[29] EC_INVT_PWM
R260 0_0402_5%
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 16 of 45
5 4 3 2 1
5 4 3 2 1
D3 F1
W=40mils
2
10K_0402_5%
10K_0402_5%
+5VS 2 1+HDMI_5V_OUT_1 1 2
1
1
4.7K_0402_5%
R274
R275
HDMI@ HDMI@ RB491D_SC59-3 1.1A_6VDC_FUSE C549
R276 R277 HDMI@ HDMI@ 0.1U_0402_16V4Z
4.7K_0402_5% HDMI@
2
2
G
@ @
JHDMI1
2
D HDMI_SCLK HDMI_HPD D
3 1 19 HP_DET
[13] GMCH_HDMI_CLK @
D
+HDMI_5V_OUT 18 +5V
Q16 17 DDC/CEC_GND
2
G
<5V tolerant> BSH111 1N_SOT23-3 HDMI_SDATA 16
HDMI_SCLK SDA
15 SCL
3 1 HDMI_SDATA 14
[13] GMCH_HDMI_DATA @ Reserved
D
13 CEC
Q17 HDMI_R_CK- 12 20
BSH111 1N_SOT23-3 CK- GND
11 CK_shield GND 21
HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
2 HDMI@ 1 9 D0- GND 23
R278 0_0402_5% 8
HDMI_R_D0+ D0_shield
7 D0+
2 HDMI@ 1 HDMI_R_D1- 6 D1-
R279 0_0402_5% 5
HDMI_R_D1+ D1_shield
4 D1+
Check 5V tolerant HDMI_R_D2- 3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
Place closed to JHDMI1 SUYIN_100042MR019S153ZL
CONN@
<NAV70 use>
+3VS
2
HDMI@
+HDMI_5V_OUT R280
C 0_0402_5% C
HDMI_HPD
1
1 1
2
C681 @ 1 C687
@ 1 R304 2 R411 0.1U_0402_16V7K C HDMI@
+3VS
100K_0402_5% @ 2 1 2 HDMI_HPD
5
1
1
2 4 2 1 GMCH_HDMI_DET [13] GMCH_HDMI_DET GMCH_HDMI_DET 2 1 Q18 HDMI@
A Y R303 0_0402_5% R282 0_0402_5% MMBT3904_NL_SOT23-3 R283
G
1
U40 HDMI@ 365K_0402_1%
@ @
3
R284
2
10K_0402_5%
HDMI@
2
SN74AHCT1G125GW_SOT353-5
Reserve
HDMI@
HDMI_C_CLK- R285 1 2 0_0402_5% HDMI_R_CK-
WCM-2012-900T_0805
@ 4 3
C550 HDMI@2 HDMI_C_TX2- 4 3
[12] GMCH_HDMI_TXD2- 1 0.1U_0402_16V7K R286 1 HDMI@ 2 715_0402_1%
C551 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX2+ R287 1 HDMI@ 2 715_0402_1% HDMI_C_CLK+ R288 1 2 0_0402_5% HDMI_R_CK+
B [12] GMCH_HDMI_TXD2+ B
HDMI@
C552 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX1- R289 1 HDMI@ 2 715_0402_1%
[12] GMCH_HDMI_TXD1-
C553 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX1+ R290 1 HDMI@ 2 715_0402_1% HDMI_C_TX0- R291 1 HDMI@ 2 0_0402_5% HDMI_R_D0-
[12] GMCH_HDMI_TXD1+
C554 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX0- R292 1 HDMI@ 2 715_0402_1% 1 2
[12] GMCH_HDMI_TXD0- 1 2
C555 HDMI@2 1 0.1U_0402_16V7K HDMI_C_TX0+ R293 1 HDMI@ 2 715_0402_1% 10mil L61
[12] GMCH_HDMI_TXD0+
WCM-2012-900T_0805
C556 HDMI@2 1 0.1U_0402_16V7K HDMI_C_CLK- R294 1 HDMI@ 2 715_0402_1% @ 4 3
[12] GMCH_HDMI_TXC- 4 3
C557 HDMI@2 1 0.1U_0402_16V7K HDMI_C_CLK+ R295 1 HDMI@ 2 715_0402_1%
[12] GMCH_HDMI_TXC+
HDMI_C_TX0+ R296 1 2 0_0402_5% HDMI_R_D0+
HDMI@
1
R298 WCM-2012-900T_0805
HDMI@ @ 4 3
100K_0402_5% 4 3
10mil HDMI_C_TX1+ R299 0_0402_5% HDMI_R_D1+
1 2
2
HDMI@
1 1 2 2
L63
WCM-2012-900T_0805
@
Place closed to JHDMI1 4 4 3 3
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 17 of 45
5 4 3 2 1
A B C D E
2
D7 F2 W=40mils
2 1 1 2
RB491D_SC59-3 1.1A_6VDC_FUSE
1
D4 D5
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C558
@ @ 0.1U_0402_16V4Z
2
1
1 1
1
1 1 1 1 1 1 3
R305 R307 R308 C559 C560 C561 C562 C563 C564 9
14 G 16
150_0402_1% 4 17
2 2 2 2 2 2 G
10
2
140_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
10P_0402_50V8J 1 5
150_0402_1% 10P_0402_50V8J C565
C-H_13-12201513CP
100P_0402_50V8J CONN@
2
+CRT_VCC
CRT_DET# [20]
L67 1 2 CRT_HSYNC_2
C569 1 2 0.1U_0402_16V4Z R312 2 1 10K_0402_5% FCM2012CF-800T06_2P DSUB_12
2
L68 1 2 CRT_VSYNC_2 1 R311
1
U18 FCM2012CF-800T06_2P 1 1 100K_0402_5%
OE#
GMCH_CRT_HSYNC 2 4 CRT_HSYNC_1 C566 C567 DSUB_15
[13,14] GMCH_CRT_HSYNC
1
A Y 10P_0402_50V8J 10P_0402_50V8J C568 2
2 G 2 2 68P_0402_50V8J 1 2
74AHCT1G125GW_SOT353-5
3
C570 +CRT_VCC
+CRT_VCC 68P_0402_50V8J
2
C571 1 2 0.1U_0402_16V4Z
1
U19
OE#
GMCH_CRT_VSYNC 2 4 CRT_VSYNC_1
[13,14] GMCH_CRT_VSYNC A Y
G
74AHCT1G125GW_SOT353-5
+3VS
3 3
1
R317 1 R318
4.7K_0402_5% 4.7K_0402_5%
2
2
G
@
DSUB_12 1 3 GMCH_CRT_DATA
GMCH_CRT_DATA [13]
S
Q53
2
BSH111 1N_SOT23-3
G
@
DSUB_15 1 3 GMCH_CRT_CLK
GMCH_CRT_CLK [13]
S
Q65
BSH111 1N_SOT23-3
2 1
R321 0_0402_5%
2 1
R323 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 18 of 45
A B C D E
A B C D E
R370
C572 1 2 150P_0402_50V8J U20A
@ 33_0402_5%
2 1 P1
SB800 Part 1 of 5
W2
A_RST# PCIE_RST# PCICLK0
[13,14,29] A_RST# 2 1 33_0402_5%L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 [23]
PCI CLKS
R325 W3 PCI_CLK2 [23]
C579 0.1U_0402_16V7K SB_RX0P_C PCICLK2/GPO37
[12] SB_RX0P 1 2 AD26 A_TX0P PCICLK3/GPO38 W4 PCI_CLK3 [23]
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1 PCI_CLK4 [23]
[12] SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28
[12] SB_RX1P A_TX1P
C575 1 2 0.1U_0402_16V7K SB_RX1N_C AC29 V2 PAD T26
[12] SB_RX1N A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K SB_RX2P_C AB29
[12] SB_RX2P A_TX2P
C580 1 2 0.1U_0402_16V7K SB_RX2N_C AB28
[12] SB_RX2N A_TX2N
C577 1 2 0.1U_0402_16V7K SB_RX3P_C AB26 AA1
[12] SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4
1 [12] SB_RX3N A_TX3N AD1/GPIO1 +3VALW 1
AD2/GPIO2 AA3
[12] SB_TX0P AE24 AB1 C581
A_RX0P AD3/GPIO3
[12] SB_TX0N AE23 A_RX0N AD4/GPIO4 AA5 1 2
[12] SB_TX1P AD25 AB2 AMD suggest add GPIO control gate
5
[12] SB_TX2N AC25 AA6 R427 @ 0_0402_5% U21
A_RX2N AD8/GPIO8
[12] SB_TX3P AB25 AC2 1 2 2
P
A_RX3P AD9/GPIO9 R425 0_0402_5% B PLT_RST#
[12] SB_TX3N AB24 A_RX3N AD10/GPIO10 AC3 Y 4 PLT_RST# [25,27]
AC4 A_RST# 1
AD11/GPIO11 A
G
R326 2 1 590_0402_1% AD29 AC1 NC7SZ08P5X_NL_SC70-5
PCIE_CALRP AD12/GPIO12
1
+1.1VS_PCIE R327 2 1 2K_0402_1% AD28 AD1
3
PCIE_CALRN AD13/GPIO13 R328
AD14/GPIO14 AD2
AA28 AC6 8.2K_0402_5%
GPP_TX0P AD15/GPIO15 @
AA29 GPP_TX0N AD16/GPIO16 AE2
Y29 AE1
2
GPP_TX1P AD17/GPIO17
Y28 GPP_TX1N AD18/GPIO18 AF8
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1
+3VS W28 AG1
+1.5VS GPP_TX3P AD21/GPIO21
W29 GPP_TX3N AD22/GPIO22 AF2
AE9 PCI_AD23 PCI_AD23 [23]
AD23/GPIO23
2
PCI INTERFACE
CBE1# AD5
2 2
CBE2# AD8
level shift to ISL6265 CBE3# AA10
FRAME# AE8
DEVSEL# AB9
[15] CLK_SBSRC_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
[15] CLK_SBSRC_BCLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
[13] NB_DISP_CLKP U29 NB_DISP_CLKP STOP# AF5
[13] NB_DISP_CLKN U28 NB_DISP_CLKN PERR# AE6
ISL6265 PWROK input, TTL level: 0.8V~2.0V SERR# AE4
[15] NB_HT_CLKP T26 NB_HT_CLKP REQ0# AE11
When this pin is high, the SVI interface is [15] NB_HT_CLKN T27 NB_HT_CLKN REQ1#/GPIO40 AH5
REQ2#/CLK_REQ8#/GPIO41 AH4
active and I2C protocol is running. While this [15] CPU_HT_CLKP V21 AC12
CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42
pin is low, the SVC, SVD, and VFIXEN input [15] CPU_HT_CLKN T21 CPU_HT_CLKN GNT0# AD12
GNT1#/GPO44 AJ5
states determine the pre-PWROK metal VID or V23 AH6
SLT_GFX_CLKP GNT2#/GPO45
VFIX mode voltage. This pin must be low prior T23 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB12
CLKRUN# AB11 CLKRUN# [29]
to the ISL6265 PGOOD output going high L29 GPP_CLK0P LOCK# AD7
L28 GPP_CLK0N
INTE#/GPIO32 AJ6
[15] GPP_CLK1P N29 GPP_CLK1P INTF#/GPIO33 AG6
LAN [15] GPP_CLK1N N28 GPP_CLK1N INTG#/GPIO34 AG4
INTH#/GPIO35 AJ4
M29 GPP_CLK2P
M28 GPP_CLK2N
T25
CLOCK GENERATOR
[15] GPP_CLK3P GPP_CLK3P
MINI [15] GPP_CLK3N V25 H24 LPCCLK0 1 2 LPC_CLK0_EC
GPP_CLK3N LPCCLK0 LPC_CLK0_EC [23,29]
H25 R330 22_0402_5% LPC_CLK1 [23]
LPCCLK1
L24 GPP_CLK4P LAD0 J27 LPC_AD0 [29]
3 3
L23 GPP_CLK4N LAD1 J26 LPC_AD1 [29]
LPC LAD2 H29 LPC_AD2 [29]
P25 GPP_CLK5P LAD3 H28 LPC_AD3 [29]
1 2 25M_CLK_X1 M25 G28
GPP_CLK5N LFRAME# LPC_FRAME# [29]
C689 J25
LDRQ0#
1
GPP_CLK7P
N27 GPP_CLK7N
1 2 25M_CLK_X2 G21 ALLOW_LDTSTOP [13]
C688 ALLOW_LDTSTP/DMA_ACTIVE#
T29 GPP_CLK8P PROCHOT# H21 H_PROCHOT_R# [8]
27P_0402_50V8J T28 K19 H_PWRGD [8]
GPP_CLK8N LDT_PG
CPU
1
D2 R331
RTC
2
@ R332 20M_0402_5%
@R332
D8
1 2 SB820M_FCBGA605
1 2 3
R333 510_0402_5%
C582
0.1U_0402_16V4Z
C584 1 1 C585 W=20mils 1
2
0.1U_0402_16V4Z
1 2 SB_32KHI 1U_0402_6.3V4Z 1
R334 C583 2
4 Y3 4
18P_0402_50V8J @
1
2 2 0_0603_5%
1 OSC NC 2 for Clear CMOS 2 BAS40-04_SOT23-3
R335 Close to SB
1
20M_0603_5% 4 3
OSC NC +CHGRTC
C586
2
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 2009/10/06 2010/03/12 Title
Issued Date Deciphered Date
11/10 for DVT SCHEMATICS, MB A5912
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 19 of 45
A B C D E
A B C D E
+3VALW
2
@ @
R336 1 2 C587 1 2 100P_0402_25V8K
100K_0402_5% R337 100_0402_5%
U20D
[29] EC_SWI# J2 A10 CLK_48M_USB [15]
1
CRT_DET PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
K1 RI#/GEVENT22#
CRT_DET D3 G19 USB_RCOMP 1 2
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
1
D 11.8K_0402_1% R338
[29] PM_SLP_S3# F1 SLP_S3#
[18] CRT_DET# 2 [29] PM_SLP_S5# H1 SLP_S5#
USB 2.0
0-> VB Disable * SB_SMDAT0 AE22 G14 USB20_N7 For China WWAN Port7 and Port9 is disable for
[10,11,15,27] SB_SMDAT0 SDA0/GPIO47 USB_HSD7N USB20_N7 [28]
R588 1 UNVB@ 2 100K_0402_5% SB_SMCLK1 F5
Cinfigure to output or Internal PU/PD SB_SMDAT1 SCL1/GPIO227 USB20_P6
2009 AMD platform
F4 SDA1/GPIO228 USB_HSD6P G16 USB20_P6 [28]
Check SW: VB_EN AH21 G18 USB20_N6 CardReader
LAY_SEL: 1-> 6L* CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USB20_N6 [28]
R402 1 2 2.2K_0402_5% CLK_MODE [15] LAN_CLKREQ#_I AB18
0-> 8L CLK_REQ1#/FANOUT4/GPIO61 USB20_P5
E1 D16
GPIO
IR_LED#/LLB#/GPIO184 USB_HSD5P USB20_P5 [16]
2 @ 1 100K_0402_5% AJ21 C16 USB20_N5 Camera
2 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N USB20_N5 [16] 2
R406 H4 DDR3_RST#/GEVENT7#
D5 GBE_LED0/GPIO183 USB_HSD4P B14
R846 1 @ 2 2.2K_0402_5% MUXLESS_SEL MUXLESS SEL: 1->PX with Muxless D7 A14
0->PX with Mux GBE_LED1/GEVENT9# USB_HSD4N
G5 GBE_LED2/GEVENT10#
2 1 K3 GBE_STAT0/GEVENT11# USB_HSD3P E18
R847 100K_0402_5% AA20 E16
CLK_REQG#/GPIO65/OSCIN USB_HSD3N
EHCI1 / OHCI1
J16 USB20_P2
USB_HSD2P USB20_P2 [28]
H3 J18 USB20_N2 Ext USB3 <Wake Up support>
BLINK/USB_OC7#/GEVENT18# USB_HSD2N USB20_N2 [28]
EC_LID_OUT# D1
[29] EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6#
E4 B17 USB20_P1
USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USB20_P1 [28]
USB OC
T27 PAD D4 A17 USB20_N1 Ext USB2
USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USB20_N1 [28]
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC#2 F7 A16 USB20_P0
[28] USB_OC#2 USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_P0 [28]
USB_OC#1 E7 B16 USB20_N0 Ext USB1
[28] USB_OC#1 USB_OC1#/TDI/GEVENT13# USB_HSD0N USB20_N0 [28]
USB_OC#0 F8
[28] USB_OC#0 USB_OC0#/TRST#/GEVENT12#
R345 1 2 33_0402_5%
[31] HDA_BITCLK_AUDIO
[23] HDA_SDOUT
HDA_BITCLK M3 D25 Check SW:
R346 1 HDA_SDOUT AZ_BITCLK SCL2/GPIO193
[31] HDA_SDOUT_AUDIO 2 33_0402_5% N1 AZ_SDOUT SDA2/GPIO194 F23 Cinfigure to output or Internal PU/PD
HDA_SDIN0 L2 B26
[31] HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SB_SIC [8]
HDA_SDIN1 M2 E26
HD AUDIO
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 SB_SID [8]
M1 AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197 F25
M4 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 E22
R347 1 2 33_0402_5% HDA_SYNC N2 F22
[31] HDA_SYNC_AUDIO AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 GPIO199 [23]
R348 1
P2 AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 E21 GPIO200 [23] STRAP PIN
[31] HDA_RST_AUDIO# 2 33_0402_5% HDA_RST#
KSI_0/GPIO201 G24
GBE_COL T1 G25
GBE_CRS GBE_COL KSI_1/GPIO202
T4 GBE_CRS KSI_2/GPIO203 E28
L6 GBE_MDCK KSI_3/GPIO204 E29
3 GBE_MDIO 3
L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 GBE_RXD3 KSI_6/GPIO207 C29
U3 GBE_RXD2 KSI_7/GPIO208 C28
T2 GBE_RXD1
GBE LAN
U2 GBE_RXD0 KSO_0/GPIO209 B28
+3VS T5 A27
GBE_RXCTL/RXDV KSO_1/GPIO210
EMBEDDED CTRL
GBE_RXERR V5 B27
@ HDA_BITCLK GBE_RXERR KSO_2/GPIO211
1 2 P5 GBE_TXCLK KSO_3/GPIO212 D26
R349 10K_0402_5% R342 1 2 2.2K_0402_5% SB_SMCLK0 M5 A26
@ HDA_SDIN0 GBE_TXD3 KSO_4/GPIO213
1 2 P9 GBE_TXD2 KSO_5/GPIO214 C26
R350 10K_0402_5% R343 1 2 2.2K_0402_5% SB_SMDAT0 T7 GBE_TXD1 KSO_6/GPIO215 A24
1 @ 2 HDA_SDIN1 P7 B25
R351 10K_0402_5% R344 1 SUS_STAT# GBE_TXD0 KSO_7/GPIO216
2 4.7K_0402_5% M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25
P4 GBE_PHY_PD KSO_9/GPIO218 D24
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
GBE_PHY_INTR V7 C24
GBE_PHY_INTR KSO_11/GPIO220
KSO_12/GPIO221 B23
T28 PAD E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
T29 PAD E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22
EMBEDDED CTRL
U20B
AH9
SB800 AH28
1 [24] SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
[24] SATA_STX_DRX_N0 AJ9 SATA_TX0N Part 2 of 5 FC_FBCLKOUT AG28
HDD AJ8
FC_FBCLKIN AF26
[24] SATA_DTX_C_SRX_N0 SATA_RX0N
[24] SATA_DTX_C_SRX_P0 AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
[24] SATA_STX_DRX_P1 AH10 SATA_TX1P FC_WE#/GPIOD148 AG26
[24] SATA_STX_DRX_N1 AJ10 SATA_TX1N FC_CE1#/GPIOD149 AF27
ODD AG10
FC_CE2#/GPIOD150 AE29
AF29
[24] SATA_DTX_C_SRX_N1 SATA_RX1N FC_INT1/GPIOD144
[24] SATA_DTX_C_SRX_P1 AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
FLASH
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17
SERIAL ATA
SATA_RX4P
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
2 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
R364 1K_0402_1% V9
SATA_CALRP FANIN1/GPIO57
2 1 AB14 SATA_CALRP FANIN2/GPIO58 W8
+1.1VS_SATA 2 1 SATA_CALRN AA14
R365 931_0402_1% SATA_CALRN
TEMPIN0/GPIO171 B6
TEMPIN1/GPIO172 A6
AD11 A5 @R366
@ R366
[30] SATA_LED# SATA_ACT#/GPIO67 TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174 B5 1 2 EC_THERM# [29]
C7 0_0402_5%
R367 1 TEMP_COMM
+3VS 2 10K_0402_5% Check SW:
A3 Cinfigure to output or Internal PU/PD
SATA_X1 VIN0/GPIO175
HW MONITOR
AD16 SATA_X1 VIN1/GPIO176 B4
VIN2/GPIO177 A4
VIN3/GPIO178 C5
A7 MEM_1V5
VIN4/GPIO179
VIN5/GPIO180 B7
VIN6/GBE_STAT3/GPIO181 B8
SATA_X2 AC16 A8
SATA_X2 VIN7/GBE_LED3/GPIO182
SPI ROM
SPI_DO/GPIO163 NC2
K4 SPI_CLK/GPIO162
K9 SPI_CS1#/GPIO165
@ G2 ROM_RST#/GPIO161
1 2 SATA_X1
C588
1
27P_0402_50V8J @ SB820M_FCBGA605
3 @ 3
Y4 R368
25MHZ_20PF_7A25000012 10M_0402_5% SB820 A12(SA00003IW10)
2
@
2
1 2 SATA_X2
C589
27P_0402_50V8J
5
U22
MEM_1V5 2
P
B
Y 4 1 2 VDDR_SW [40]
1 2 1 R424 33_0402_5%
[19,23] PCI_AD24 A
G
R422 0_0402_5% 2
NC7SZ08P5X_NL_SC70-5
3
C686
150P_0402_50V8J
1
1 @ 2
PCI_AD24 R423 0_0402_5%
1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 21 of 45
A B C D E
A B C D E
+1.1VS_VDDC U20E
510mA
1 2 +1.1VS
U20C R369 0_0805_5%
Part 3 of 5
SB800
131mA SB800 10U_0805_10V4Z C590
Y14 VSSIO_SATA_1 VSS_1 AJ2
+3VS AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 1 2 Y16 VSSIO_SATA_2 VSS_2 A28
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 AB16 VSSIO_SATA_3 VSS_3 A2
1 2 Y19 N17 1U_0402_6.3V4Z 2 1 C596 AC14 E5
VDDIO_33_PCIGP_3 VDDCR_11_3 VSSIO_SATA_4 VSS_4
CORE S0
C591 22U_0805_6.3V6M AE5 U13 1U_0402_6.3V4Z 2 1 C594 AE12 D23
1 C592 0.1U_0402_16V4Z VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U_0402_16V4Z C597 VSSIO_SATA_5 VSS_5 1
1 2 AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 2 1 AE14 VSSIO_SATA_6 VSS_6 E25
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF9 E6
VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_7 VSS_7
PCI/GPIO I/O
C599 1 2 0.1U_0402_16V4Z AB4 V18 AF11 F24
VDDIO_33_PCIGP_7 VDDCR_11_7 VSSIO_SATA_8 VSS_8
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 AF13 VSSIO_SATA_9 VSS_9 N15
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18 AF16 VSSIO_SATA_10 VSS_10 R13
AA9 VDDIO_33_PCIGP_10 AG8 VSSIO_SATA_11 VSS_11 R17
+1.1VS_CKVDD L69
AF7 VDDIO_33_PCIGP_11 400mA AH7 VSSIO_SATA_12 VSS_12 T10
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 2 1 +1.1VS AH11 VSSIO_SATA_13 VSS_13 P10
K29 FBMA-L11-201209-221LMA30T_0805 AH13 V11
VDDAN_11_CLK_2 VSSIO_SATA_14 VSS_14
VDDAN_11_CLK_3 J28
22U_0805_6.3V6M C595
External Clock, connect to +1.1VS AH16 VSSIO_SATA_15 VSS_15 U15
VDDAN_11_CLK_4 K26 1 2 AJ7 VSSIO_SATA_16 VSS_16 M18
71mA J21 directly, no need thick trace AJ11 V19
CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_17 VSS_17
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 AJ13 VSSIO_SATA_18 VSS_18 M11
FLASH I/O
AE25 K21 1U_0402_6.3V4Z 2 1 C601 check can be removed? AJ16 L12
VDDIO_18_FC_2 VDDAN_11_CLK_7 0.1U_0402_16V4Z C602 VSSIO_SATA_19 VSS_19
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 2 1 VSS_20 L18
1 2 AC22 0.1U_0402_16V4Z 2 1 C603 A9 J7
R371 0_0402_5% VDDIO_18_FC_4 VSSIO_USB_1 VSS_21
B10 VSSIO_USB_2 VSS_22 P3
VDDRF_GBE_S V1 1 2 K11 VSSIO_USB_3 VSS_23 V4
R372 0_0402_5% B9 AD6
POWER VDDIO_33_GBE_S M10 1 2 D10
VSSIO_USB_4
VSSIO_USB_5
VSS_24
VSS_25 AD4
43mA R373 0_0402_5% D12 AB7
VSSIO_USB_6 VSS_26
+VDDPL_3V_PCIE AE28 VDDPL_33_PCIE D14 VSSIO_USB_7 VSS_27 AC9
GBE LAN
D17 VSSIO_USB_8 VSS_28 V8
L70 +1.1VS_PCIE
600mA E9 VSSIO_USB_9 VSS_29 W9
PCI EXPRESS
+1.1VS 2 1 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 1 2 F9 VSSIO_USB_10 VSS_30 W10
FBMA-L11-201209-221LMA30T_0805 V22 L9 R374 0_0402_5% F12 AJ28
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_11 VSS_31
V26 VDDAN_11_PCIE_3 F14 VSSIO_USB_12 VSS_32 B29
C604 1 2 22U_0805_6.3V6M V27 F16 U4
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 VSSIO_USB_13 VSS_33
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 1 2 C9 VSSIO_USB_14 VSS_34 Y18
C606 1 2 0.1U_0402_16V4Z V29 P8 R375 0_0402_5% G11 Y10
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_15 VSS_35
GROUND
1 2 W22 VDDAN_11_PCIE_7 F18 VSSIO_USB_16 VSS_36 Y12
W26 VDDAN_11_PCIE_8 D9 VSSIO_USB_17 VSS_37 Y11
2 2
H12 VSSIO_USB_18 VSS_38 AA11
+VDDPL_3V_SATA H14 VSSIO_USB_19 VSS_39 AA12
+3VALW
93mA H16 VSSIO_USB_20 VSS_40 G4
L71 +1.1VS_SATA
AD14 VDDPL_33_SATA 32mA H18 VSSIO_USB_21 VSS_41 J4
VDDIO_33_S_1 A21 J11 VSSIO_USB_22 VSS_42 G8
+1.1VS 2 1 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 J19 VSSIO_USB_23 VSS_43 G9
FBMA-L11-201209-221LMA30T_0805 567mA AF18 B21 2.2U_0603_6.3V4Z 1 2 C608 K12 M12
SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 2.2U_0603_6.3V4Z C609 VSSIO_USB_24 VSS_44
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 1 2 K14 VSSIO_USB_25 VSS_45 AF25
3.3V_S5 I/O
C610 1 2 22U_0805_6.3V6M AG19 L10 K16 H7
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_26 VSS_46
1 2 AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 K18 VSSIO_USB_27 VSS_47 AH29
C612 1 2 1U_0402_6.3V4Z AD18 T6 +1.1VALW H19 V10
C613 0.1U_0402_16V4Z VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_28 VSS_48
1 2 AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 VSS_49 P6
C614 1 2 0.1U_0402_16V4Z N4
VSS_50
Y4 EFUSE VSS_51 L4
check 220ohm bead 113mA C615 2 1 1U_0402_6.3V4Z L8
+AVDD_USB VSS_52
CORE S5
L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5%
1 1 1
C636
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/06 Deciphered Date 2010/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 22 of 45
A B C D E
A B C D E
PULL LOW POWER ALLOW PCIE WATCHDOG USE Inter CLK EC CLOCKGEN
HIGH MODE GEN2 TIMER DEBUG Gen Mode ENABLE ENABLE H,H = Reserved
ENABLE STRAP Enable
1 H,L = SPI ROM 1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R385
R377
R378
R379
R380
R381
R382
R383
R384
2
2
@ @ @ @ INT@ @ INT@ @
[20] HDA_SDOUT
[19] PCI_CLK1
[19] PCI_CLK2
[19] PCI_CLK3
[19] PCI_CLK4
[19,29] LPC_CLK0_EC
[19] LPC_CLK1
[20] GPIO200
2 [20] GPIO199 2
2.2K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R393
R394
R386
R387
R388
R389
R390
R391
R392
@
2
2
EXT@ EXT@
+3VS +3VS
DEBUG STRAPS
10K_0402_5%
10K_0402_5%
1
1
R395
R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI [19] PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT [19] PCI_AD28
HIGH [19] PCI_AD27
[19] PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
[19] PCI_AD25
[19,21] PCI_AD24
[19] PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R397
R398
R399
R400
R401
2
2
Check AD29,AD28 strap function @ @ @ @ @
check default
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 23 of 45
A B C D E
A B C D E F G H
1
SATA HDD Conn. 1
JHDD1
1 GND
C656 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P0 2
[21] SATA_STX_DRX_P0 A+
C658 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_N0 3
[21] SATA_STX_DRX_N0 A-
4 GND
[21] SATA_DTX_C_SRX_N0 C657 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N0 5
C659 1 SATA_DTX_SRX_P0 B-
[21] SATA_DTX_C_SRX_P0 2 0.01U_0402_16V7K 6 B+
7 GND
+3VS
+3VS 8 V33
1 9 V33
C639 10 V33
11 GND
0.1U_0402_16V4Z 12
2 GND
13 GND
14 V5
15 V5
R405 1 2 0_0805_5% +5VS_HDD 16
+5VS V5
17 GND
18 Reserved
10U_0805_10V4Z 0.1U_0402_16V4Z 19 GND
20 V12
1 1 1 1 21 V12 GND 24
C660 C661 C662 C663 22 23
V12 GND
2 2 2 2 SANTA_192301-1
2 CONN@ 2
1U_0402_6.3V4Z 1000P_0402_50V7K
<NAV70 use>
1 GND
[21] SATA_STX_DRX_P1 C648 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P1 2
C649 1 SATA_STX_C_DRX_N1 A+
[21] SATA_STX_DRX_N1 2 0.01U_0402_16V7K 3 A-
4 GND
C650 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N1 5
[21] SATA_DTX_C_SRX_N1 B-
C651 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P1 6
[21] SATA_DTX_C_SRX_P1 B+
7 GND
3 R403 1 @ 3
2 1K_0402_1% 8 DP
9 +5V
+5VS R404 1 2 0_0805_5% +5VS_ODD 10 17
+5V GND
11 MD GND 16
12 GND NC 15
13 GND NC 14
2 2 2 2
1U_0402_6.3V4Z 1000P_0402_50V7K
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 24 of 45
A B C D E F G H
A B C D
+3V_LAN
R800
60mil
+3VALW 1 2
0_1206_5%
2 1
C902
C901
4.7U_0805_10V4Z
U70 1 2
0.1U_0402_16V4Z
+3V_LAN 42 25 +LAN_BIASVDDH
VDDC BIASVDDH
1 1
35 LAN_MIDI2-
TRD2_N LAN_MIDI2- [26] +3V_LAN
34 LAN_MIDI2+
TRD2_P LAN_MIDI2+ [26]
+LAN_GPHYPLLVDDL 24 C906 1 2 0.1U_0402_16V4Z
GPHY_PLLVDDL
31 LAN_MIDI1- @
TRD1_N LAN_MIDI1- [26]
2
32 LAN_MIDI1+ R802 R803
TRD1_P LAN_MIDI1+ [26]
1K_0402_1% 1K_0402_1%
+LAN_PCIEPLLVDD 18 @
PCIE_PLLVDDL LAN_MIDI0- U71 @
29 LAN_MIDI0- [26]
1
TRD0_N
21 PCIE_PLLVDDL 8 VCC A0 1
28 LAN_MIDI0+ 7 2
TRD0_P LAN_MIDI0+ [26] WP A1
SPROM_CLK 6 3
SPROM_DOUT SCL NC
5 SDA GND 4
AT24C02_SO8
2
2 2
1
PCIE_TXD_N SPD1000LED#
[12] PCIE_ITX_C_PRX_P0 22 PCIE_RXD_P
[12] PCIE_ITX_C_PRX_N0 23 PCIE_RXD_N TRAFFICLED# 45 2 1 LAN_ACTIVITY# [26]
LAN_PME# 4 R805
WAKE# 0_0402_5%
LAN_RESET# 2 REST#
20 PCIE_REFCLK_P
R806 1 @ 2 0_0402_5% 19
[20,27] SB_PCIE_WAKE# PCIE_REFCLK_N
[29] EC_PME# R807 1 2 0_0402_5%
+3V_LAN R808 1 2 4.7K_0402_5%
R809 1
20mil
[19,27] PLT_RST# 2 0_0402_5% L100
5 +LAN_XTALVDDH 1 1 2 +3V_LAN
MODE C909 BLM18AG601SN1D_2P
[15] CLK_PCIE_LAN
0.1U_0402_16V4Z
[15] CLK_PCIE_LAN#
2
20mil L101
43 SPROM_DOUT +LAN_BIASVDDH 1 1 2
EEDATA C910 BLM18AG601SN1D_2P
44 SPROM_CLK
R810 1 EECLK
+3VS 2 1K_0402_5% 40 VMAIN_PRSINT
0.1U_0402_16V4Z
2
R813 1
20mil
2 10K_0402_5% 1 LOW_PWR
L102
+LAN_AVDDH
1 1 1 2
L103
C911 C912 BLM18AG601SN1D_2P
11 +1.2V_LAN_OUT 1 2 +1.2V_LAN
SR_LX 4.7UH_PG031B-4R7MS_1.1A_20% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
LAN_XTALO_R 2 2
3
T12 PAD 13 XTALO SR_VFB 8 1 1 3
C913
LAN_XTALI 12 C914 20mil
T13 PAD XTALI 0.1U_0402_16V4Z 10U_0805_10V4Z L104
2 2 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
1 2 BLM18AG601SN1D_2P
R814
C915
1 2 LAN_RDAC 26 C916
RDAC 0.1U_0402_16V4Z 4.7U_0805_10V4Z
SR_VDDP 10 +3V_LAN 2 1
1.24K_0402_1% 1 1
9 C917 C918
SR_VDD
2 2 20mil L105
[15] LAN_CLKREQ# 3 CLKREQ# 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
7 1 2 BLM18AG601SN1D_2P
NC C919
C920
PAD
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 1
49
4
R815 4
200_0402_1%
Y5
2
1 2 LAN_XTALO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
TXC suggest change SE071330J80 For DVT
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 25 of 45
A B C D
5 4 3 2 1
D D
BH GS5009-D <SP050006B00>
LAN Connector
JRJ45
T25 12
[25] LAN_ACTIVITY# Yellow LED-
1 TCT1 MCT1 24 +3V_LAN 2 1 11 Yellow LED+
[25] LAN_MIDI0+ LAN_MIDI0+ 2 23 RJ45_MIDI0+ R823 1K_0402_5%
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0- RJ45_MIDI3-
[25] LAN_MIDI0- 3 TD1- MX1- 22 1 2 8 PR4-
C938 220P_0402_50V7K
4 21 RJ45_MIDI3+ 7
LAN_MIDI1+ TCT2 MCT2 RJ45_MIDI1+ PR4+
[25] LAN_MIDI1+ 5 TD2+ MX2+ 20
[25] LAN_MIDI1- LAN_MIDI1- 6 19 RJ45_MIDI1- RJ45_MIDI1- 6
TD2- MX2- PR2-
7 18 RJ45_MIDI2- 5
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ PR3-
[25] LAN_MIDI2+ 8 TD3+ MX3+ 17
[25] LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2- RJ45_MIDI2+ 4
TD3- MX3- PR3+
10 15 RJ45_MIDI1+ 3
LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+ PR2+ @
[25] LAN_MIDI3+ 11 TD4+ MX4+ 14
[25] LAN_MIDI3- LAN_MIDI3- 12 13 RJ45_MIDI3- RJ45_MIDI0- 2 R413 0_0805_5%
TD4- MX4- PR1-
SHLD2 13 2 1
RJ45_MIDI0+ 1 14
C
PR1+ SHLD1 C
2
350UH_IH-037-2 10
[25] LAN_LINK# Green LED- R412
1 1 1 1 R819 R820 +3V_LAN 2 1 9 0_0805_5%
C928 C929 C930 C931 75_0402_1% 75_0402_1% R824 1K_0402_5% Green LED+
@
1 2 SANTA_130451-K
1
1
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z C942 220P_0402_50V7K CONN@
2 2 2 2
R821 R822
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1%
RJ45_GND 1 2 LANGND 40mil
2
1 2
RJ45_GND C940
Place close to TCT pin 1000P_1206_2KV7K C941 C939
40mil 4.7U_0805_10V4Z
2 1
LAN_ACTIVITY# 0.1U_0402_16V4Z
LAN_LINK#
2
D40
LAN_ACTIVITY# 1 2
PJDLC05_SOT23-3 C943 220P_0402_50V7K
@
LAN_LINK# 1 2
C944 220P_0402_50V7K
B B
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 26 of 45
5 4 3 2 1
A B C D E
1 1
1 1 1 1 1 1
C705 C706 C707 C708 C709 C710
JMINI1
SB_PCIE_WAKE# R440 1 @ 2 0_0402_5% 1 2 +3VS
[20,25] SB_PCIE_WAKE# 1 2
3 3 4 4
5 5 6 6 +1.5VS
[15] MINI1_CLKREQ# 7 7 8 8 Mini Card Power Rating
9 9 10 10
[15] CLK_PCIE_MINI1# 11 11 12 12 Power Primary Power (mA) Auxiliary Power (mA)
[15] CLK_PCIE_MINI1 13 13 14 14
15 15 16 16 Peak Normal Normal
+3VS 1000 750
17 17 18 18
19 20 WL_OFF# +3V 330 250 250 (wake enable)
19 20 WL_OFF# [29]
21 22 PLT_RST#
21 22 PLT_RST# [19,25]
23 24 +3V_WLAN 1 2 +3VS +1.5VS 500 375 5 (Not wake enable)
2 [12] PCIE_PTX_C_IRX_N1 23 24 2
25 26 R441 1 2 0_0603_5% +3VALW
[12] PCIE_PTX_C_IRX_P1 25 26
27 28 R442 @ 0_0603_5%
27 28 MINI1_SMBCLK @
29 29 30 30 1 2 SB_SMDAT0 [10,11,15,20]
[12] PCIE_ITX_C_PRX_N1 31 32 MINI1_SMBDAT R443
1 @ 0_0603_5%
2
31 32 SB_SMCLK0 [10,11,15,20]
[12] PCIE_ITX_C_PRX_P1 33 34 R444 0_0603_5%
33 34
35 35 36 36 USB20_N8 [20]
37 37 38 38 USB20_P8 [20]
+3VS 39 39 40 40
41 42 (MINI1_LED#) WIMAX_LED#
41 42 WLAN_LED#_L
43 43 44 44
45 45 46 46
0_0402_5% 47 48
R445 1 E51TXD_P80DATA_R 47 48
[29] E51TXD_P80DATA 2 49 49 50 50
E51RXD_P80CLK 51 52
[29] E51RXD_P80CLK 51 52
G1
G2
G3
G3
2
ACES_88910-5204
53
54
55
56
R492 CONN@
100K_0402_5%
@
<NAV70 use>
1
1
0_0402_5%
R835 1 2 R848
+3VS 100K_0402_5%
2
3 3
WIMAX_LED# 2
1 MINI1_LED# [29]
1 @ 2 WLAN_LED#_L 3
R836 10K_0402_5%
CHP202UPT_SOT323-3
(9~16mA)
D44 @
1 2
R837 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 27 of 45
A B C D E
A B C D E
+3VALW +USB_VCCA
USB PW switch Change P/N SA00002XX00 For DVT
1
1
+ C711
+5VALW
1
+USB_VCCA C712
U24 80mil R446 220U_6.3V_M
2
100K_0402_5% 2
1 GND VOUT 8
2 7 470P_0402_50V7K
VIN VOUT
W=80mils
3 6
2
1 VIN VOUT R447 1 1
1 4 EN FLG 5 2 10K_0402_5% USB_OC#0 [20]
C713
RT9715BGS_SO8 1 2
4.7U_0805_10V4Z 1 R448 @ 0_0402_5%
2 C714
0.1U_0402_16V4Z
L83 JUSB1
2 USB20_N0
[34] SYSON# [20] USB20_N0 1 1 2 2 1 1
USB20_N0_R 2
USB20_P0_R 2
3 3
+3VALW USB20_P0
[20] USB20_P0 4 4 3 3 4 4 <NAL00 use>
5 GND
WCM2012F2S-900T04_0805 6
+5VALW GND
1
+USB_VCCB R449 7
U25 0_0402_5% GND
80mil R450
8 GND
1 GND VOUT 8 1 2 USB_OC#2 [20] 1 2
2 7 100K_0402_5% R451 @ 0_0402_5% SUYIN_020133MB004S580ZL-C
VIN VOUT CONN@
3 6
2
VIN VOUT
1 4 EN FLG 5 1 2 USB_OC#1 [20]
C715 R452
RT9715BGS_SO8 10K_0402_5% 1
4.7U_0805_10V4Z C716
2
0.1U_0402_16V4Z
2 D10
SYSON# USB20_N0_R 4 3 USB20_P0_R
+USB_VCCA 5 2
2 2
6 1
(Port 1,2)
JUSB2 JCR1 +3VS
1 10 C717
1 GND 4.7U_0805_10V4Z
2 2 GND 9
3 3 8 8 1 2
4 7
4
5 5
6 USB20_N1
7
6 6
5 CLK_CR_48M
5IN1_LED# [30] Bluetooth Conn.
6 USB20_N1 [20] 5
7 USB20_P1 4
7 USB20_P1 [20] 4
8 3 USB20_N6
8 3 USB20_N6 [20]
9 USB20_N2 2 USB20_P6
9 USB20_N2 [20] 2 USB20_P6 [20]
10 USB20_P2 1
10 USB20_P2 [20] 1
13 GND 11 11
14 12 +3VALW +3VS
GND 12 ACES_85201-08051
CONN@
ACES_85201-1205N
CONN@ <NEW70 use> 1 BT@
@ R504 @ C782 C718 C719
<NAL00 use> CLK_CR_48M 2 1 BT@
0.1U_0402_16V4Z BT@ 1U_0402_6.3V4Z
3
2
S
0_0402_5% 33P_0402_50V8K G Q24
3 BT@ 2 3
[29] BT_ON# 1 2
R453 10K_0402_5%
D AO3413_SOT23-3
1
Reserve for EMI C720
BT@
W=40mils
+BT_VCC
0.1U_0402_16V4Z
1
To 3G Module Connect
1
C721 BT@ C722 BT@ BT@
R454
+BT_VCC 4.7U_0805_10V4Z 300_0603_5%
2 0.1U_0402_16V4Z
+3VS_WWAN +3VS +3VS_WWAN JBT1
2
Peak: 2.75A 10 GND 8 8
BT@
7 7
Normal: 1.1A
2
1
+3VS_WWAN 3G@ 2 D
(Port 9) R457
1
R455 0_1206_5% 6 6
5
USB20_P14 [20]
2 Q25
5 USB20_N14 [20]
JP4 100K_0402_5% 4 G 2N7002_SOT23
4
1 3 S
3
1 3
2 1 2
1
2 WWAN_OFF# C723 2
3 3 WWAN_OFF# [29] 9 GND 1 1
4 +
4 WWAN_LED# [29]
5 ACES_87213-0800G
5 CONN@
6 6 USB20_N9 [20]
220U_C6_6.3V_M_R15 2
7 7 USB20_P9 [20]
8 3G@ Close to WWAN CONN <NAL00 use>
8
9 9 USB20_N7 [20]
10 10 USB20_P7 [20]
GND 11
GND 12
ACES_87036-1001-CP
4 4
CONN@
<NAV70 use>
11/25 for DVT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 28 of 45
A B C D E
5 4 3 2 1
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2+EC_VCCA +3VALW
1 1 C725 1 1 2 2
1
BLM18AG601SN1D_2P R109 JP7 Place on MiniCard door
C724 1 0_0402_5% 1
C726 C727 C728 C729 1 E51RXD_P80CLK
@ 2 2 E51RXD_P80CLK [27]
1000P_0402_50V7K 1000P_0402_50V7K C730 3 E51TXD_P80DATA
E51TXD_P80DATA [27]
1
KSO[0..17] 2 2 2 2 1 1 MB_SL 3
KSO[0..17] [30] 4 4
2
ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
KSI[0..7] ACES_85205-0400
KSI[0..7] [30]
@
D R491 D
+3VALW
111
125
4.7K_0402_5%
22
33
96
67
1
9
U26 NEWX5@ 65W/90W# 2 1
R458 100K_0402_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
VR_ON 2 1
R459 100K_0402_5%
3S/4S# 1 2
EC_GA20 1 21 R460 4.7K_0402_5%
[20] EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
[20] EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# [31]
SERIRQ 3 26
[19] SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
[19] LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF [38,41]
C732 LPC_AD3 5 2 1 ECAGND
[19] LPC_AD3 LAD3
@ 22P_0402_50V8J @ LPC_AD2 7 PWM Output C731 0.01U_0402_16V7K
[19] LPC_AD2 LAD2
2 1 2 1 LPC_AD1 8 63 BATT_TEMP
[19] LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP [36]
R461 33_0402_5% LPC_AD0 BATT_OVP
[19] LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP [38] Analog Project ID definition
ADP_I/AD2/GPIO3A 65 ADP_I [38]
LPC_CLK0_EC 12 AD Input 66 AD_BID0 +3VALW
[19,23] LPC_CLK0_EC PCICLK AD3/GPIO3B
13 75 AD_PID0
[13,14,19] A_RST# PCIRST#/GPIO05 AD4/GPIO42 Project_ID : 0-> NEW75/85/95
37 76 MB_SL
ECRST# SELIO2#/AD5/GPIO43
2
EC_SCI# 20 1-> PEW76/86/96
[20] EC_SCI# SCI#/GPIO0E 2-> PEW56(BA51)
+3VALW 2 1 1 2 38 R463
[19] CLKRUN# CLKRUN#/GPIO1D
R462 47K_0402_5% @ 68 DAC_BRIG Ra PEW56@
DAC_BRIG/DA0/GPIO3C DAC_BRIG [16]
2 1 R99 0_0402_5% 70 EN_DFAN1 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 [33]
C733 0.1U_0402_16V4Z DA Output 71 IREF
IREF [38]
1
IREF/DA2/GPIO3E
2
+5VS KSI0 55 72 CALIBRATE# AD_PID0
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# [38]
KSI1 56 KSI1/GPIO31
2
@ KSI2 57 1
TP_CLK R489 KSI3 KSI2/GPIO32 EC_MUTE# R464 C734
1 2 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# [32] Rb
C R465 4.7K_0402_5% 4.7K_0402_5% KSI4 59 84 C
1
1
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK [30]
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA [30]
KSO1 40
+3VALW +3VS KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 3S/4S#
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# [38]
KSO4 43 98 65W/90W# Analog Board ID definition
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# [38]
KSO5 VLDT_EN
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 VLDT_EN [34,40]
2
2
PEW56@ NEWX5@ KSO9 48 119 0_0402_5% 1-> wo/ pach code
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO [30]
KSO10 49 120 R469
EC_SO_SPI_SI [30]
1
1
R468 2.2K_0402_5% KSO14 KSO13/GPIO2D C783 AD_BID0
53 KSO14/GPIO2E
KSO15 54 73 WWAN_OFF# 33P_0402_50V8K
KSO15/GPIO2F CIR_RX/GPIO40 WWAN_OFF# [28]
1
+3VALW KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 @ 1
KSO17 82 89 R470 C735
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG [38]
1 2 EC_SMB_CK1
BATT_CHGI_LED#/GPIO52 90 BATT_BLUE_LED#
BATT_BLUE_LED# [30]
Rb
R471 2.2K_0402_5% 91 8.2K_0402_5% 0.1U_0402_16V4Z
EC_SMB_DA1 EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_AMB_LED# 2
1 2 [36] EC_SMB_CK1 77 GPIO 92
2
R472 2.2K_0402_5% EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 PWR_LED BATT_AMB_LED# [30]
[36] EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 PWR_LED [30]
1 2 KSO1 EC_SMB_CK2 79 SM Bus 95 SYSON Reserve for EMI, close to EC
[8] EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON [34,39]
R473 47K_0402_5% EC_SMB_DA2 80 121 VR_ON
[8] EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON [40,43]
1 2 KSO2 127 ACIN 12/03 for DVT
B R474 47K_0402_5% AC_IN/GPIO59 ACIN [30,34,35] B
2 1 LID_SW#
R475 100K_0402_5% PM_SLP_S3# 6 100 EC_RSMRST# +3VS EC_REV : 1-> D3
[20] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# [20] 0-> E0
1 @ 2 EC_PME# PM_SLP_S5# 14 101 EC_LID_OUT#
[20] PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# [20]
R476 10K_0402_5% EC_SMI# 15 102 EC_ON
[20] EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON [33]
2 1 PBTN_OUT# LOCAL_DIM 16 103 EC_SWI# EC_REV 2 PEW56@1
[16] LOCAL_DIM LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# [20]
R497 100K_0402_5% MINI1_LED# 17 104 EC_PWROK R838 100K_0402_5%
[27] MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF#
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# [16] 2 1
COLOY_ENG_EN 19 GPIO 106 WL_OFF# R839NEWX5@100K_0402_5%
[16] COLOY_ENG_EN EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# [27]
For LED INV_PWM freq to 1K EC_INVT_PWM 25 107 EC_REV
[16] EC_INVT_PWM EC_THERM#/GPIO11 GPXO10
FAN_SPEED1 28 108 VGA_ON [34,42] Delay SUSP# 10ms
ENBKL [33] FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11
2 1 [28] BT_ON# 29 FANFB2/GPIO15
R488 100K_0402_5% E51TXD_P80DATA 30
LOCAL_DIM E51RXD_P80CLK EC_TX/GPIO16 VGATE
2
R844
1
100K_0402_5% ON/OFF
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110
ENBKL
VGATE [43] 11/25 for DVT EC suggest
[33] ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL [13]
2 1 COLOY_ENG_EN [30] PWR_SUSP_LED PWR_SUSP_LED 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD [31]
R845 100K_0402_5% WLAN_LED# 36 GPI 115 EC_THERM# EC_PWROK 1 2
[30] WLAN_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# [21] SB_PWRGD [8,13,20]
116 SUSP# R254 0_0402_5%
GPXID5 SUSP# [34,38]
For Low PWR panel use 117 PBTN_OUT#
GPXID6 EC_PME# PBTN_OUT# [20]
GPXID7 118 EC_PME# [25]
EC_CRY1 122 U26
EC_CRY2 XCLK1
123 XCLK0 V18R 124
1
AGND
C736
GND
GND
GND
GND
GND
69
OSC
15P_0402_50V8J 1 1
BLM18AG601SN1D_2P KB926 Rev:E0(SA00001J5A0)
<BOM Structure>
NC
NC
32.768KHZ_12.5PF_Q13MC14610002
Security Classification Compal Secret Data Compal Electronics, Inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 29 of 45
5 4 3 2 1
To TP/B Conn. +5VS
JTP1
1 1
2 +5VS
2 TP_CLK [29]
+3VALW 1 2 C742 1 2 0.1U_0402_16V4Z 3
3 TP_DATA [29]
R479 0_0603_5% 4 LEFT_BTN#
4 RIGHT_BTN# C745
5 5
+SPI_VCC 6
6 0.1U_0402_16V4Z
7 GND
U27 8
[29] EC_SPICS#/FSEL# GND
EC_SPICS#/FSEL# 1 8
R480 1 CS# VCC
2 4.7K_0402_5% SPI_WP# 3 WP# SCLK 6 EC_SPICLK_R R481 1 2 0_0402_5% EC_SPICLK [29]
ACES_85201-0605N
+3VALW R482 1 2 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI_R R483 1 2 0_0402_5% CONN@
HOLD# SI EC_SO_SPI_SI [29]
4 2 EC_SI_SPI_SO_R R484 1 2 0_0402_5%
GND SO EC_SI_SPI_SO [29]
MX25L1605DM2I-12G SOP 8P RIGHT_BTN# TP_CLK
SA00002TO00 SW1 SW2
SMT1-05-A_4P SMT1-05-A_4P LEFT_BTN# TP_DATA
LEFT_BTN# 3 1 RIGHT_BTN# 3 1
2
4 2 4 2 D11 D13
U28 @
5
6
5
6
EC_SPICS#/FSEL# 1 8 +SPI_VCC PJDLC05C_SOT23-3
SPI_WP# CE# VDD EC_SPICLK_R PJDLC05C_SOT23-3
3 WP# SCK 6
SPI_HOLD# 7 5 EC_SO_SPI_SI_R
HOLD# SI EC_SI_SPI_SO_R
4 VSS SO 2
1
MX25L1005AMC-12G_SOP8
@
0_0402_5% R485
1
@
C746
33P_0402_50V8K
Left side Right side
For NEW75 NEW85 For NEW95
JLED2 JLED1
1 1 +3VALW 1 1 +3VALW
2 LID_SW# 2 LID_SW#
JKB1
INT_KBD Conn. 2
3 3
4
ACIN_LED#
3G_LED#
LID_SW# [29] 2
3 3
4
ACIN_LED#
3G_LED#
4 3G_LED# [29] 4
5 WLAN_LED# 5 WLAN_LED#
5 WLAN_LED# [29] 5
KSO0 26 28 6 MEDIA_LED# 6 MEDIA_LED#
KSO1 KSO0 G2 6 6
25 KSO1 G1 27 7 7 +3VS 7 7 +3VS
KSO2 24 8 PWR_LED# 8 PWR_LED#
KSO3 KSO2 KSI[0..7] 8 ON/OFFBTN# 8 ON/OFFBTN#
23 KSO3 KSI[0..7] [29] 9 9 ON/OFFBTN# [33] 9 9
KSO4 22 10 10
KSO5 KSO4 KSO[0..17] 10 10
21 KSO5 KSO[0..17] [29] GND 11 GND 11
KSO6 20 12 12
KSO7 KSO6 GND GND
19 KSO7
KSO8 18 ACES_85201-1005N ACES_85201-1005N
KSO9 KSO8 CONN@ CONN@
17 KSO9
KSO10 16
KSO11 KSO10
15 KSO11
KSO12 14 PIN define modify for 01/22
KSO13 KSO12
13 KSO13
KSO14 12 ACIN_LED#
KSO15 KSO14 +3VS
11 KSO15
KSO16 10
KSO17 KSO16
9 KSO17
2
KSI0 D @ +3VS
8 KSI0
KSI1 7 [29,34,35] ACIN 2 Q73 R486
KSI2 KSI1 G
6 KSI2
KSI3 5 S 100K_0402_5%
3
KSI3
5
KSI4 4 2N7002_SOT23 U29
1
KSI5 KSI4
3 2
P
KSI5 B 5IN1_LED# [28]
KSI6 2 For MP Add @ MEDIA_LED# 4
KSI7 KSI6 Y
1 KSI7 A 1 SATA_LED# [21]
G
KSO16 C747 1 2 100P_0402_50V8J NC7SZ08P5X_NL_SC70-5
3
ACES_88747-2601
CONN@ KSO17 C748 1 2 100P_0402_50V8J
PWR_LED#
KSO15 C749 1 2 100P_0402_50V8J KSO7 C750 1 2 100P_0402_50V8J
6
LED1
KSO14 C751 1 2 100P_0402_50V8J KSO6 C752 1 2 100P_0402_50V8J HT-191NB5_BLUE
KSO13 C753 1 2 100P_0402_50V8J KSO5 C754 1 2 100P_0402_50V8J [29] PWR_LED 2 DMN66D0LDW-7_SOT363-6 +3VS 1 7585@ 2 2 1 PWR_LED#
Q26A R477 2.2K_0402_5% B
2
KSO12 C755 1 2 100P_0402_50V8J KSO4 C756 1 2 100P_0402_50V8J
1
R487
100K_0402_5% LED2
KSI0 C757 1 2 100P_0402_50V8J KSO3 C758 1 2 100P_0402_50V8J HT-191UD5_AMBER
1
KSO11 C759 1 2 100P_0402_50V8J KSI4 C760 1 2 100P_0402_50V8J +3VALW 1 7585@ 2 2 1 PWR_SUSP_LED#
R478 3.9K_0402_5% A
KSO10 C761 1 2 100P_0402_50V8J KSO2 C762 1 2 100P_0402_50V8J
Change Q26 as SB00000DH00
KSI1 C763 1 2 100P_0402_50V8J KSO1 C764 1 2 100P_0402_50V8J NEW95 / PEW56 LED Option 20100120 LED3
HT-191NB5_BLUE
2 9556@1 PWR_SUSP_LED#
KSI2 C765 1 2 100P_0402_50V8J KSO0 C766 1 2 100P_0402_50V8J R477 680_0402_5% +3VALW 1 7585@ 2 2 1 BATT_BLUE_LED# BATT_BLUE_LED# [29]
3
R499 2.2K_0402_5% B
KSO9 C767 1 2 100P_0402_50V8J KSI5 C768 1 2 100P_0402_50V8J 2 9556@1
R478 680_0402_5%
KSI3 C769 1 2 100P_0402_50V8J KSI6 C770 1 2 100P_0402_50V8J [29] PWR_SUSP_LED 5 DMN66D0LDW-7_SOT363-6 LED4
2 9556@1 Q26B HT-191UD5_AMBER
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 30 of 45
A B C D E F G H
1 2
R784 0_0805_5%
+3VS +VDDA
+5VAMP
U81
60mil 40mil
1
+5VS L87 1 2 1 IN
1
R783 5 +VDDA 4.75V
OUT
C678
C899
C947
D38 20K_0402_1% FBMA-L11-201209-221LMA30T_0805 2
R789 L88 1 GND
2 1 1 1
CH751H-40PT_SOD323-2 10K_0402_5% 3 4 1 2
2
1 C936 FBMA-L11-201209-221LMA30T_0805 SHDN BYP C949 1
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2 MONO_IN @ @ G9191-475T1U_SOT23-5 0.01U_0402_25V7K
1U_0402_6.3V4Z 2 2 2
1
R786
2 HD Audio Codec (output = 300 mA)
1
C 2.4K_0402_1%
C952 1 R787 Q72
[29] BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E
3
2SC2411KT146_SOT23-3
C946 1 R788
[20] SB_SPKR 2 1 2
1U_0402_6.3V4Z
1
560_0402_5%
D37
CH751H-40PT_SOD323-2
L82
2 10mil BLM18AG601SN1D_2P
0.1U_0402_16V4Z +3VS_DVDD 1 2 +3VS MIC2_VREFO
1 1 1
C933 C953 C926
+AVDD_HDA
1
10U_0805_10V4Z
L86 2 2 2 R585
1 2 0.1U_0402_16V4Z 40mil 2.2K_0402_5%
+VDDA
BLM18AG601SN1D_2P 1 1 1 0.1U_0402_16V4Z
C935 C945
2
C950 Close to Conn
2 10U_0805_10V4Z INT_MIC 2
25
38
9
2 2 2 U82
0.1U_0402_16V4Z 1
DVDD
AVDD1
AVDD2
DVDD_IO
C808
220P_0402_50V7K
AMP_LEFT 2
14 LINE2_L LOUT1_L 35 AMP_LEFT [32]
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT [32]
C794 4.7U_0805_10V4Z
1 2 MIC2_C_L 16 39
INT_MIC MIC2_L LOUT2_L
2 1INT_MIC_2 0_0603_5% R849 JP1
R523 1K_0402_1% 1 2 MIC2_C_R 17 41 INT_MIC 1 2 1
C797 4.7U_0805_10V4Z MIC2_R LOUT2_R 1
15mil 1 2 2 2
23 45 0_0603_5% R850
LINE1_L SPDIFO2
1 1
24 46 220P_0402_50V7K 220P_0402_50V7K 3
LINE1_R DMIC_CLK1/2 G1
4 G2
2
18 43 C979 C980
LINE1_VREFO NC 2 2 ACES_88266-02001
20 LINE2_VREFO DMIC_CLK3/4 44 1 2 1 2 C948 CONN@
R792 0_0402_5% 22P_0402_50V8J For EMI
MIC2_VREFO 19 MIC2_VREFO
4.7U_0805_10V4Z 6 EMI For PVT
BITCLK HDA_BITCLK_AUDIO [20]
MIC1_L C934 1 2 MIC1_C_L 21
[32] MIC1_L MIC1_L
MIC1_R 1 2 MIC1_C_R 22 8 1 2 HDA_SDIN0 [20] D27 @
[32] MIC1_R
1
C932 4.7U_0805_10V4Z MIC1_R SDATA_IN R793 33_0402_5% PJDLC05C_SOT23-3
MONO_IN 12 37
PCBEEP_IN MONO_OUT
CBP 29
11 C951 2.2U_0805_10V6K
3 [20] HDA_RST_AUDIO# RESET# 3
CPVEE 31 1 2
[20] HDA_SYNC_AUDIO 10 SYNC 10mil 2
MIC1_VREFO 28 MIC1_VREFO
[20] HDA_SDOUT_AUDIO 5 C954 HP_RIGHT
SDATA_OUT HP_RIGHT [32]
32 HP_RIGHT 2.2U_0805_10V6K
HPOUT_R 1 HP_LEFT
2 GPIO0/DMIC_DATA1/2 HP_LEFT [32]
3 GPIO1/DMIC_DATA3/4 CBN 30
R794 2 1 20K_0402_1% SENSE_A 13 10mil
[32] MIC_PLUG# SENSE A
R795 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF
[32] HP_PLUG# SENSE B VREF
1 1
10U_0805_10V4Z
0.1U_0402_16V4Z
[29] EAPD 1 2 47 EAPD JDREF 40
20K_0402_1%
C927
C937
R796 0_0402_5%
1
48 33 HP_LEFT
SPDIFO1 HPOUT_L 2 2
R797
4 DVSS1 AVSS1 26
7 DVSS2 AVSS2 42
2
ALC272-VA2-GR_LQFP48_7X7 1 2 1 2
Change to ALC272X R798 0_0805_5% R799 0_0805_5%
DGND AGND
1 2 1 2
R804 0_0805_5% R816 0_0805_5%
ALC272X
Sense Pin Impedance Codec Signals Function 1 2 1 2
R818 0_0805_5% R817 0_0805_5%
39.2K PORT-A (PIN 39, 41) LOUT2
20K PORT-B (PIN 21, 22) MIC1
SENSE A
10K PORT-C (PIN 23, 24) LINE1 GND GNDA GND GNDA
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 31 of 45
A B C D E F G H
A B C D E
2
1
1
D39
16
15
3 G1
6
U83 R827 @ R829 4
100K_0402_5% 100K_0402_5% G2
VDD
PVDD1
PVDD2
PJDLC05C_SOT23-3 ACES_88266-02001
CONN@
2
C958 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
1
3 GAIN1
GAIN1
1
1 2 1 2 AMP_C_RIGHT 17
[31] AMP_RIGHT C957 0.47U_0603_10V7K R830 0_0603_5% RIN- SPKR+ @ R825 R826
ROUT+ 18
100K_0402_5% 100K_0402_5% JSPK1
SPKR+ R831 1 2 0_0603_5% SPK_R+ 1
SPKR- SPKR- R832 1 1
14 2 0_0603_5% SPK_R- 2
2
C955 1 ROUT- 2
2 0.47U_0603_10V7K 9 20mil
LIN+ Right
2
4 SPKL+ D41 3
LOUT+ G1
4 G2
1 2 1 2 AMP_C_LEFT 5
[31] AMP_LEFT C971 0.47U_0603_10V7K R828 0_0603_5% LIN- SPKL- PJDLC05C_SOT23-3 ACES_88266-02001
LOUT- 8
CONN@
For PVT
1
NC 12
2 2
EC_MUTE# BYPASS 10 Keep 10 mil width
[29] EC_MUTE# 19 SHUTDOWN
2
GND5
GND1
GND2
GND3
GND4
C956
0.47U_0603_10V7K
1
21
20
13
11
1 TPA6017A2_TSSOP20
2 2
C779 C774
330P_0402_50V7K 330P_0402_50V7K
Headphone Out
1 1 JHP1
1
[31] HP_LEFT R686 1 2 56.2_0603_1% HPOUT_L_1 1 2 HPOUT_L_2 2
L94 FBMA-L11-160808-700LMT_2P
[31] HP_RIGHT R685 1 2 56.2_0603_1% HPOUT_R_1 1 2 HPOUT_R_2 3
L93 FBMA-L11-160808-700LMT_2P
4
HP_PLUG# 5
[31] HP_PLUG#
SINGA_2SJ-0960-C01
3 CONN@ 3
MIC_PLUG# <NAL00 use>
HP_PLUG#
2
MIC1_VREFO MIC1_VREFO @
D24
PJDLC05C_SOT23-3
2
D43 D42
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
1 1
1 1
1
R692 R693
MIC JACK
4.7K_0402_5%
4.7K_0402_5% JMIC1
2
1
R694 1 2 MIC1_L_1 L89 1 2 MIC1_L_R 2
[31] MIC1_L
1K_0603_1% FBMA-L11-160808-700LMT_2P
R695 1 2 MIC1_R_1 L90 1 2 MIC1_R_R 3
[31] MIC1_R
1K_0603_1% FBMA-L11-160808-700LMT_2P
2
1 1 @ 4
D29
C780 C781 MIC_PLUG# 5
[31] MIC_PLUG#
220P_0402_50V7K 220P_0402_50V7K
2 2
PJDLC05C_SOT23-3
6
4 4
SINGA_2SJ-A960-C01
1
CONN@
<NAL00 use>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 32 of 45
A B C D E
ON/OFF switch Power Button
FAN1 Conn +3VALW
TOP Side
+5VS 1 2
+5VS R493 @ 10K_0603_5%
2
C821 10U_0805_10V4Z
1
1 2 1 2 R495
2 D25 R494 @ 10K_0603_5%
@ 1SS355_SOD323-2 100K_0402_5%
R566
Bottom Side
1
0_0603_5% @ SW3 D12
2
@ U35 @ D26 BAS16_SOT23-3 SMT1-05-A_4P 2 ON/OFF [29]
1 8 1 2 1 3 ON/OFFBTN# 1
1
EN GND
2 VIN GND 7 3 51ON# [35]
+VCC_FAN1 3 6 2 4
VOUT GND C823 DAN202UT106_SC70-3
[29] EN_DFAN1 1 2 4 VSET GND 5
R567 0_0402_5% 1 10U_0805_10V4Z
6
5
C822 APL5607KI-TRG_SO8 1 2 For MP 2
@ C773
+3VS ON/OFFBTN# [30]
0.01U_0402_25V4Z C824
2 1000P_0402_50V7K 1000P_0402_50V7K
1
1 2
1
R568
1
10K_0402_5% D
40mil EC_ON 2 Q27
[29] EC_ON
JFAN1 G
2
+VCC_FAN1 S 2N7002_SOT23
3
1 R496
[29] FAN_SPEED1 2
3 10K_0402_5%
1
C825 CONN@
1
1000P_0402_50V7K ACES_85205-03001
2
LDO FAN
H1 H2 H4 H5 H6 H7 H8 H9 H10
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
1
H11 H12 H19 H24 H20 H21 H22 H23
H_3P0 H_3P0 H_3P0 H_3P0 H_4P2 H_4P2 H_4P2 H_4P2
1
H18 H17 H13
H_3P4 H_3P0X3P5N H_3P0N
1
FD1 FD2 FD3 FD4
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 33 of 45
A B C D E
+5VALW +5VS
+1.1VALW TO +1.1VS
2
+1.1VALW +1.1VS
U36 R570
8 1 U38 100K_0402_5%
D S
7 D S 2 8 D S 1
2
6 3 1 1 7 2
1
D S D S
2
1 1 5 4 C827 R571 6 3 1 1
D G D S
1
C826 C828 470_0603_5% 1 5 4 C838 R578 SYSON#
D G [28] SYSON#
SI4800BDY_SO8 10U_0805_10V4Z C829 R577 C837
1
10U_0805_10V4Z 2 2 1K_0402_5% SI4800BDY_SO8 10U_0805_10V4Z C839 470_0603_5% D
1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 Q30
[29,39] SYSON 2
1
2 1U_0402_6.3V4Z G 2N7002_SOT23
2
1
1
D 10U_0805_10V4Z S
3
1
1 D 1
2 SUSP R573
G 2 VLDT_EN# 100K_0402_5%
+VSB 1 2 5VS_GATE S Q31 G
3
R574 100K_0402_5% 2N7002_SOT23 +VSB 1 2 1.1VS_GATE S Q37
2
1 R581 47K_0402_5% 2N7002_SOT23
1
D C834
+5VALW
510K_0402_5%
SUSP 2 1
1
Q33G 0.1U_0603_25V7K D C844
2
R595
2N7002_SOT23 S VLDT_EN# 2
3
2
Q39G 0.1U_0603_25V7K
2N7002_SOT23 S @ 2 R576
3
100K_0402_5%
1 2
D
1
ACIN 2 Q48 SUSP
+3VALW TO +3VS
+3VS
[29,30,35] ACIN
G @
2N7002_SOT23
[41] SUSP
S
1
+3VALW D
1
8 1 S
3
D S
7 D S 2
2
6 3 R580
C840
1
C841
1 5
D
D
S
G 4 C842
1 1
R579
470_0603_5%
+1.5V to +1.5VS 10K_0402_5%
2
SI4800BDY_SO8 10U_0805_10V4Z C836 +1.5V +1.5VS
10U_0805_10V4Z 2 2
1 1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z
D
U37
2 SUSP 8 D S 1
G 7 2
D S
2
2 1 3VS_GATE S Q36 6 3 +5VALW
+VSB 1 1
3
2 R582 200K_0402_5% 2N7002_SOT23 D S C832 C833 R572 2
1 1 5 D G 4
C830 C831
1
2
D SI4800BDY_SO8 10U_0805_10V4Z 470_0603_5%
1 2 2
SUSP 2 C843 1U_0402_6.3V4Z R583
1
Q38G 2 2 100K_0402_5%
2N7002_SOT23 S 0.1U_0603_25V7K 10U_0805_10V4Z 10U_0805_10V4Z
3
1
2 D
1
2 VGA_ON# VLDT_EN#
G
+VSB 1 2 1.5VSG_GATE S Q32
1
R575 100K_0402_5% 2N7002_SOT23 D
510K_0402_5%
1 G 2N7002_SOT23
1
D C835 S
3
R596
VGA_ON# 2 1 2
R503 47K_0402_5% G 0.1U_0603_25V7K R584
Q34 S @ 2 10K_0402_5%
3
1 2N7002_SOT23
2
C848
1
D
0.22U_0603_16V4Z2 ACIN 2 Q49
G @
S 2N7002_SOT23
3
+5VALW
2
R587
100K_0402_5%
3 3
1
VGA_ON#
1
D
[29,42] VGA_ON 2 Q42
G 2N7002_SOT23
1
S
3
R586
+2.5VS +0.75VS +CPU_VDDR +NB_CORE +1.8VS +1.5V 10K_0402_5%
2
2
+5VS
1
D D D D D D
2 SUSP 2 SUSP 2 VLDT_EN# 2 VLDT_EN# 2 VGA_ON# 2 SYSON#
G G G G G G
S Q44 S 2N7002_SOT23 S Q56 S Q69 S Q46 S Q57
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 34 of 45
A B C D E
A B C D
PR1
1M_0402_1%
1 2
VIN VIN
VS
1
1 1
VIN PR2
10K_0402_5%
PR3
84.5K_0402_1%
PR4
SP02000GC00
8
ACES_50305-00441-001 PL1 PR5 PU1A 22K_0402_5%
2
SMB3025500YA_2P 10K_0402_1% 3 1 2
P
DC_IN_S1 PACIN +
1 1 1 2 1 2 1 O
[29,30,34] ACIN
1
2 2 - 2
1
G
3 <BOM Structure> PC1
3
1
4 PD1 LM393DR_SO8 PR7 1000P_0402_50V7K
4
4 PC2 20K_0402_1%
5
2
GND
1
6 PR8 0.1U_0603_25V7K
2
GND PC3 PC4 PC5 PC6 10K_0402_5% GLZ4.3B_LL34-2
PJP1 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
PR9
10K_0402_5%
1 2
RTCVREF
[38,41] PACIN
Vin Dectector
Min. Typ Max.
H-->L 16.976V 17.525V 17.728V
2
L-->H 17.430V 17.901V 18.384V 2
PJ29
2 1
- PBJ1 + +1.8VSP2 2 1 +1.8VS
2
@ PC130
@PC130 JUMP_43X118
2 1 +RTCBATT 0.1U_0402_16V7K (3A,120mils ,Via NO.=6)
+RTCBATT
1
ML1220T13RE PJ1 PJ22
45@ +3VALWP 2 2 1 1 +3VALW +1.8VSP1 2 2 1 1 +1.8VS
2
@ PC7
@PC7 JUMP_43X118 @ PC71
@PC71 JUMP_43X118
0.1U_0402_16V7K (3.9A,160mils ,Via NO.= 8) 0.1U_0402_16V7K (3A,120mils ,Via NO.=6)
1
VIN 2
PJ3
1 2
PJ26
1
+5VALWP 2 1 +5VALW +1.1VALWP 2 1 +1.1VALW
2
@ PC9
@PC9 JUMP_43X118 @ PC8
@PC8 JUMP_43X118
2
1
PD2
LL4148_LL34-2
PJ11
PJ5
1
PD3 2 1
+0.75VSP 2 1 +0.75VS
BATT+ 2 1 +VSBP 2 2 1 1 +VSB
1
2
3 3
@ PC10
@PC10 JUMP_43X118
2
LL4148_LL34-2 PR10 PR11 PC11 JUMP_43X39 0.1U_0402_16V7K (3A,120mils ,Via NO.=6)
68_1206_5% 68_1206_5% 0.1U_0402_25V6 (120mA,40mils ,Via NO.= 2)
1
1
PR12 PQ1
2
200_0603_5% PJ6
CHGRTCP 1 2 N1 3 1 PJ8 +1.5VP 2 1 +1.5V
VS +NB_COREP 2 2 1 1 +NB_CORE
2 1
2
@PC12
@ PC12 JUMP_43X118
1
2
@ PC15
@PC15 JUMP_43X118 0.1U_0402_16V7K
1
1
100K_0402_1% 0.22U_0603_25V7K PC14 2 1
1
0.1U_0603_25V7K 2 1
2
2
@PC16
@ PC16 JUMP_43X39
RTCVREF 0.1U_0402_16V7K
1
1
PR15
200_0603_5%
PJ21
PR16 PR17 PU2
560_0603_5% 560_0603_5% 3.3V +CPU_VDDRP 2 1 +CPU_VDDR
2
N2 2 1
1 2 1 2 3 OUT IN 2
2
+CHGRTC @PC70
@ PC70 JUMP_43X39
0.1U_0402_16V7K (1.5A,40mils ,Via NO.= 3)
1
GND PC18
1
4
PC17 G920AT24U_SOT89-3 1U_0805_25V4Z 4
10U_0805_10V4Z 1
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 35 of 45
A B C D
A B C D
VL
GND 10
1
GND 9 1
8 VL
8
7 7
21K_0402_1%
6 EC_SMDA
6
1
5 EC_SMCA
5
2
PR28
4 TH PR29 PC21 PR27
4 PI 100_0402_1% 0.1U_0603_25V7K 26.7K_0402_1% PR21 @
3
2
3 100K_0402_1%
2 2
1 <40,41>
2
1 PU3
1
2
PJP2
VMB 1 VCC TMSNS1 8
2
SUYIN_200275GR008G13GZR PR32
100_0402_1% 2 7 PR30
CONN@ EC_SMB_DA1 [29] GND RHYST1
PL2 9.53K_0402_1%
SMB3025500YA_2P
<40,41> 3 6
1
OT1 TMSNS2
2
BATT_S1 1 2 BATT+
1
1
1
4 5 PR169
OT2 RHYST2
13.7K_0402_1%
PH1
EC_SMB_CK1 [29]
1
1
G718TM1U_SOT23-8
PC20 PC19 PR261 100K_0402_1%_NCP15WF104F03RC
1
1000P_0402_50V7K 0.01U_0402_25V7K 1K_0402_5%
2
2
PR24
6.49K_0402_1%
2 1 +3VALWP MAINPWON [8,37,41]
1
PH2
1
PR33 100K_0402_1%_NCP15WF104F03RC
1K_0402_1%
2
2
2 2
BATT_TEMP [29]
PQ3
B+ 3 1 +VSBP
0.22U_0603_25V7K
0.1U_0603_25V7K
1
1
PC24
PC25
PR34
100K_0402_1% @ @
2
3 3
TP0610K-T1-E3_SOT23-3
2
VL
1 2
PR36
22K_0402_1%
2
PR38
100K_0402_1%
PR39
1
0_0402_5% D
1 2 2 PQ4
[37,39] SPOK G 2N7002W-T/R7_SOT323-3
S
3
1
PC27
0.1U_0402_16V7K
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 36 of 45
A B C D
5 4 3 2 1
TPS51427_B+
TPS51427_B+
PR50
PL26
0_0805_5%
1 2 1 2
B+
2200P_0402_50V7K
2200P_0402_50V7K
HCB4532KF-800T90_1812
10U_1206_25V6M
1
2200P_0402_25V7K
2200P_0402_25V7K
10U_1206_25V6M
5
6
7
8
PC31
PC45
D D
2
8
7
6
5
1
PC122
PC28
PC30
VL
2
PC120
1U_0603_10V6K
PQ6
1
2
2
PQ5 PC40 AO4466_SO8
4.7U_0603_6.3V6M
AO4466_SO8 0.1U_0603_25V7K 4
1
PC41
4
PC29
1
+5VALWP
3
2
1
PL4
1
2
3
PL3 4.7UH_SIL1045R-4R7PF_6.3A_30%
7
4.7UH_SIL1045R-4R7PF_6.3A_30% PU4 PC36 2 1
1 2 1U_0603_10V6K
VIN
V5FILT
LDO
+3VALWP 33 19 1 2
TP V5DRV
5
6
7
8
1
4.7_1206_5%
1
8
7
6
5
PR43
DH3 26 15 DH5
PR41 PR40 DRVH2 DRVH1 PR47 2.2_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 VBST2 VBST1 17 BST5A 2 1 AO4712_SO8
1
63.4K_0402_1%
1 AO4712_SO8 2.2_0603_5%
2
2
2
PR42 PC42 4
PR49
PC39 + 0_0402_5% 4 PC43 0.1U_0603_25V7K
2
680P_0402_50V7K
220U_6.3V_M 0.1U_0603_25V7K
1
1
LX3 25 16 LX5 1
2
2 LL2 LL1
PC34
PC37
3
2
1
2
680P_0402_50V7K + PC35
1
2
3
DL3 23 18 DL5 220U_6.3V_M
1
DRVL2 DRVL1
2
2
10K_0402_1%
PGND 22
2
FB3 30 VOUT2
PR48
@ PR44
@PR44
C 10K_0402_1% C
VOUT1 10
VL 32
1
REFIN2
1
11 FB5
2VREF_TPS51427 FB1
1 2 1 VREF2
PC47 0.22U_0603_10V7K
VSW 9
8 LDOREFIN @PR59
@ PR59 0_0402_5%
SKIPSEL 29 2 1 VL
+3.3VALWP Ipeak=5.9A ; Imax=4.1A;Iocp=6.6A
PR45 0_0402_5%
Choke DCRmax=23m ohm, 1 2
Rds(on)=18m ohm(max) ; Rds(on)=15m 20 NC PGOOD2 28
PD17 PR46
ohm(typical) GLZ5.1B_LL34-2 100K_0402_1%
Vlimit=(5E-06 * 294K)/10=147mV 1 2 1 2 4 13 SPOK [36,39]
VS EN_LDO PGOOD1 PR60
Ilimit=147mV/18m ~ 147mV/15m
2
200K_0402_5%
330K_0402_1%
2
=8.17A ~ 9.8A
PR58
14 EN1 TRIP1 12 2 1
PC44
Delta I=1.94A (Freq=300KHz) 0.22U_0603_25V7K
TONSE
VREF3
1
GND
1
EN2 TRIP2
1
=9.14A ~ 10.77A
0_0402_5%
PD16 PR57
VL
2
1SS355_SOD323-2 @ PR56
@PR56 SN0806081RHBR_QFN32_5X5 294K_0402_1%
21
PR51
0_0402_5%
2
2
B PR52 B
1
1
1U_0603_10V6K
806K_0603_1% 2VREF_TPS514271 +5VALWP Ipeak=7A ; Imax=5A;Iocp=8.4A
PR54 @ PR55
@PR55 PR53 Choke DCRmax=23m ohm
1
2
PC143
0_0402_5% 47K_0402_5% 0_0402_5% Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
2 1 1 2
Vlimit=(5E-06 * 330K)/10=165mV
2VREF_TPS514272
[8,36,41] MAINPWON
1
0.047U_0402_16V7-K
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
1
PC38
=9.729A ~ 11.562A
@ PC46
@PC46
3
0.047U_0402_16V7K
2
2 PQ37
TP0610K-T1-E3_SOT23-3
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 37 of 45
5 4 3 2 1
A B C D
Iada=0~4.74A(90W/19V=4.736A) B+
CP = 85%*Iada ; CP = 4.03A
5 5 5
2200P_0402_25V7K
10U_1206_25V6M
10U_1206_25V6M
0.1U_0603_25V7K
5600P_0402_25V7K
CSIP PR63
4
1
1
PC50
PC51
47K_0402_1%
VIN
PC48
PC61
PQ17 TP0610K-T1-E3_SOT23-3 1 2
PC56
2
1
3 1 DCIN
1
P3
2
PR62 PD8
1
100K_0402_1%
0.1U_0603_25V7K
47K_0402_1% PR65 1 2 ACOFF
1
PR94 PQ18 10K_0402_1%
1
PC62
PR64
200K_0402_1% PDTC115EU_SOT323 1SS355_SOD323-2
2
PR67
2
1 1
PD9 200K_0402_1%
2
PR66 2 FSTCHG 1 2 VIN
FSTCHG [29]
2
3
2 1 2 1
47K PQ19 PD10 3 SUSP#
PDTA144EU_SOT323-3 1 2 6251VDD 100K_0402_1% SUSP# [29,34] PQ20 PD11
2.2U_0603_6.3V6K
2 47K BAS40CW_SOT323-3 PDTC115EU_SOT323 2 1 2
PC49
1SS355_SOD323-2
3
1
PR68 10K_0402_5% wrong Value 1SS355_SOD323-2
FSTCHG 2 1 PU5 PC127
1
0.1U_0603_25V7K
0.1U_0603_25V7K
1
PQ21 1 2 1 24 DCIN 2 1 PQ23D
1
VDD DCIN
1
1
100K_0402_1%
PC52
PDTC115EU_SOT323 PR70 47K_0402_5% PC67 2 PACIN
6251VDD 1 2 .1U_0402_16V7K 2N7002W-T/R7_SOT323-3
G
PR71
2 PR69 2 23 S
3
ACSET ACPRN
1
150K_0402_1% PR72
PQ24 20_0402_5%
2
2
1
2
2 PC53
3
5
6
7
8
G 2N7002W-T/R7_SOT323-3 2 0.047U_0603_16V7K
[29] 3S/4S#
2
S 4 21 1 2 CSOP PQ55 2
3
1
CELLS CSOP PR73 AO4466_SO8
PC54 6800P_0402_25V7K 20_0402_5%
1 2 5 20 2 1
3
ICOMP CSIN
1
2
PQ56 D PR74 4
PC129 20_0402_5%
2
G 2N7002W-T/R7_SOT323-3 1 2 1 PR75 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2
<40,41>
1
PR77 VCOMP CSIP PR76 PL5
S
3
3
2
1
ACON 0.01U_0402_25V7K PC57 1 2 7 18 LX_CHG 1 2 CHG 1 4
[41] ACON ICM PHASE
4.7_1206_5%
@ 100P_0402_50V8J
5
6
7
8
1
[29] ADP_I 2 3
PR80
PR79 PC58 6251VREF 8 17 DH_CHG
22K_0402_5% PR81 VREF UGATE PR82 PC59 0.02_1206_1%
1 2
10U_1206_25V6M
10U_1206_25V6M
PACIN 1 2 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K
[35,41] PACIN
2 1 .1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ57 @
2
[29] IREF CHLIM BOOT
1
0.01U_0402_25V7K
PD12 4 AO4466_SO8
1
1
PC68
PC63
PQ53 PR84
680P_0402_50V7K
PC60
PC128
100K_0402_1% RB751V-40_SOD323-2
2
2
1
2.55K_0402_1%
PR85
3
2
1
2
ACOFF 2 PR87 11 14 DL_CHG
[29,41] ACOFF
2
VADJ LGATE
1
2
PR86 @
4.7_0603_5%
12 13 PC64
2
1
GND PGND 4.7U_0805_6.3V6K
3
2
1
PQ54 D ISL6251AHAZ-T_QSOP24
2
[29] 65W/90W# G 2N7002W-T/R7_SOT323-3
S
3
3 3
VMB
<40,41>
PR88
15.4K_0402_1%
1
Iada=0~4.74A(90W) CP= 85%*Iada; CP=4.03A [29] CALIBRATE#
1 2
2
2
0.01U_0402_25V7K
BATT-OVP=0.1112*VMB
1
PC65
1
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
PR91
2
where Vaclm=1.464V (90W), Iinput=4.03A 499K_0402_1%
PR84=12.1K;PR87=20K
where Vaclm=0.391(65W), Iinput=2.91A
2
8
PR92 PU18B
PR84=12.1K;PR85=2.55K 10K_0402_1% LM358DT_SO8 5
P
+
CC=0.6~4.48A [29] BATT_OVP
1 2 7 0
- 6
0.01U_0402_25V7K
IREF=1.016*Icharge
1
PR93
PC66
105K_0402_1%
ADP_I = 19.9*3.42*0.95*0.02=1.29V IREF=0.43V~3.24V
2
2
4 4
Charging Voltage
BATT Type (0x15) CV mode
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number Rev
- AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 38 of 45
A B C D
A B C D
PL31
FBMA-L11-322513-151LMA50T_1210
1.1VALW_B+ 2 1 B+
2200P_0402_50V7K
10U_1206_25V6M
1
1
PC139
PC72
5
6
7
8
2
1 1
PQ25
PR96
255K_0402_1% 4
1 2
PR97 PR98
0_0402_5% 2.2_0603_5%
1 2 BST_1.1VALW
1 2 AO4466_SO8
3
2
1
[36,37] SPOK
DCR= 7.5 mohm
1
PR99 PL6
15
14
1
30K_0402_5% PC74 PU6 PC75 1UH_FDUE1040D-1R0M-P3_21.3A_20%
@ @0.1U_0402_16V7K BST_1.1VALW-11 2 1 2
BOOT
NC
EN/DEM
+1.1VALWP
2
2
2 13 DH_1.1VALW 0.1U_0603_25V7K
TON UGATE
1
PR101 3 12 LX_1.1VALW
VOUT PHASE
5
6
7
8
100_0603_1% PQ26 PR100 1
+5VALW 1 2 4 11 1 2 +5VALW 4.7_1206_5%
VDD CS PR102 + PC76
2
5 10 7.32K_0402_1% 330U_6.3V_M
FB VDDP
1
DL_1.1VALW 2
6 PGOOD LGATE 9 4
PGND
PC77 PC78
GND
4.7U_0603_6.3V6K PC79 680P_0603_50V7K
2
1
@ 47P_0402_50V8J
<Vo=1.1V> VFB=0.75V 1 2 RT8209BGQW_WQFN14_3P5X3P5 PC80
3
2
1
4.7U_0805_10V6K AO4456_SO8
2
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
2
PR103 2
1
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A PR104
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V 8.87K_0402_1%
Rcs=Vtrip/9uA=0.065V/9uA=7.2K 2
choose Rcs=7.32K PL32
FBMA-L11-322513-151LMA50T_1210
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A 1.5V_B+ 2 1 B+
Iocp=10A~19A
2200P_0402_50V7K
10U_1206_25V6M
1
1
PC82
PC83
5
6
7
8
PQ27
2
PR105 0_0402_5% PR106
1 2 226K_0402_1% 4
[29,34] SYSON
1 2
PR108
2.2_0603_5%
BST_1.5V 1 2 AO4466_SO8
3
2
1
1
3 3
@ PR109
@PR109 PC84 PL7
15
14
1
30K_0402_5% @PC85
@PC85 PU7 0.1U_0603_25V7K 1UH_MMD-10DZ-1R0M-X1A_18A_20%
0.1U_0402_16V7K BOOT BST_1.5V-1 1 2 1
<BOM Structure> 2
NC
EN/DEM
+1.5VP
2
2
2 13 DH_1.5V
TON UGATE
1
PR111 3 12 LX_1.5V PR110
VOUT PHASE
5
6
7
8
100_0603_1% PQ28 4.7_1206_5% 1
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS PR112 + PC86
2
5 10 13K_0402_1% 330U_2.5V_M
FB VDDP
1
1
DL_1.5V PC88 2
6 PGOOD LGATE 9 4
PGND
PC87 680P_0603_50V7K
GND
4.7U_0603_6.3V6K PC89
2
2
1
@ 47P_0402_50V8J
1 2 RT8209BGQW_WQFN14_3P5X3P5 PC90
7
3
2
1
4.7U_0805_10V6K AO4456_SO8
2
<Vo=1.5V> VFB=0.75V PR113
10K_0402_1%
Vo=0.75*(1+10K/10K)=1.5V 1 2
Fsw=335KHz
1
=>1/2Delta I=1.95A
4
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V 4
Rcs=Vtrip/9uA=0.118V/9uA=13.1K
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A Security Classification Compal Secret Data Compal Electronics, Inc.
Iocp=18A~32A Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 39 of 45
A B C D
A B C D
FB1_NB_COREP
POWER_SEL +5VALW
2
HIGH 0.95V
PR158
1
11.8K_0402_1% PL33
LOW 1.1V PR131 FBMA-L11-322513-151LMA50T_1210
1
10K_0402_1%
10K_0402_5% NB_CORE_B+ 2 1 B+
1
PR159 D
2200P_0402_50V7K
10U_1206_25V6M
1
SSM3K7002F_SC59-3 1 2 2 1
PQ43 G
1
D
S
1
PC140
PC91
1 2 2 PQ44
[13] POWER_SEL
100U_25V_M
PR157 G SSM3K7002F_SC59-3 1
5
6
7
8
0_0402_5% S PQ29
2
1
PC218
PC125 +
2
PC126 0.1U_0402_25V6
0.01U_0402_25V7K
2
PR115 2
255K_0402_1% 4
1 2
PR116 PR117
100K_0402_5% 2.2_0603_5%
1 2 BST_NB_CORE
1 2 AO4466_SO8
3
2
1
[29,34] VLDT_EN
DCR= 7.5 mohm
1
@ PR118
@PR118 PL8
15
14
1
30K_0402_5% PC94 PU8 PC93 1UH_FDUE1040D-1R0M-P3_21.3A_20%
.1U_0402_16V7K BST_NB_CORE-1
1 2 1 2
BOOT
NC
EN/DEM
+NB_COREP
2
2
2 13 DH_NB_CORE 0.1U_0603_25V7K
TON UGATE
1
PR120 3 12 LX_NB_CORE
VOUT PHASE
5
6
7
8
100_0603_1% PQ30 PR119 1
1 2 4 11 1 2 +5VALW 4.7_1206_5%
+5VALW VDD CS PR121 + PC95
2
FB1_NB_COREP 5 10 7.5K_0402_1% 330U_6.3V_M
FB VDDP
1
DL_NB_CORE 2
6 PGOOD LGATE 9 4
PGND
<Vo=1.1V> VFB=0.75V PC96 PC97
GND
4.7U_0603_6.3V6K PC98 680P_0603_50V7K
2
V=0.75*(1+4.7K/10K)=1.1V
1
2
@ 47P_0402_50V8J 2
3
2
1
4.7U_0805_10V6K AO4456_SO8
2
Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m
Ipeak=7.6A, Imax=5.4A, Iocp=9.2A PR122
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A 2.37K_0402_1%
1 2
=>1/2Delta I=1.03A
1
Vtripmax=Iocp*Rdson=9.2*5.6*1.3=0.067V
Rcs=Vtrip/9uA=0.067V/9uA=7.44K PR123
choose Rcs=7.5K 8.87K_0402_1%
Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A
2
Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A
Iocp=10.3A~19.36A
+1.5V
PU16
+5VALW APL5508-25DC-TRL_SOT89-3
1
3 3
+3VS 2 3
PJ24 IN OUT
+2.5VSP
1
@ JUMP_43X79
1
GND
1
1
2
PC115 PC114
1
4.7U_0805_6.3V6K
PC113
1U_0402_6.3V6K 1U_0402_6.3V6K @ PR153
@PR153
2
PR162 150_1206_5%
2
2
[29,43] VR_ON 10K_0402_1%
6
1 2 PU12
1
5 PC116
VCNTL
VIN 4.7U_0805_6.3V6K
7 POK
4
2
@PR155
@ PR155 VOUT
3
10K_0402_1% VOUT +CPU_VDDRP
1
22U_0805_6.3V6M
VLDT_EN 1 2 8 2
EN FB
1
PC119
GND
1
9 PR154 PC118
2
VIN
1
.1U_0402_16V7K
2
HIGH 1.05V
1
@PR152
@ PR152 SSM3K7002F_SC59-3
4
10K_0402_1% PQ58 LOW 0.9V 4
1
D
2
2
[21] VDDR_SW G
S
3
1
PR160
10K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title
SCHEMATICS, MB A5912
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 40 of 45
A B C D
5 4 3 2 1
PR124
+1.5V 1K_1206_5%
1 2
PQ31
PR125 TP0610K-T1-E3_SOT23-3
B+
1
VIN PD13 1K_1206_5%
2 1 1 2 3 1
1
PJ17
JUMP_43X79 LL4148_LL34-2 PR126
2
1K_1206_5%
PU9 1 2
2
D D
100K_0402_5%
100K_0402_5%
1 8
VIN NC
+3VALW
1
PR128
PR127
PR129
2 7 1K_1206_5%
2
GND NC
1
PC101 1 2
1
PC100 3 6 1U_0603_6.3V6M
4.7U_0805_6.3V6K PR130 VREF VCNTL
2
1K_0402_1% 4 5
VOUT NC
9
2
TP
APL5336KAI-TRL_SOP8P8
1
.1U_0402_16V7K
PR133 PR132
+0.75VSP
1
300K_0402_5% PQ32 D 100K_0402_5%
PC102
1 2 2 PR134 PQ33
[34] SUSP
1
G 1K_0402_1% DTC115EUA_SC70-3
1 2
1
S PC103
3
PC104 2N7002W-T/R7_SOT323-3 22U_0805_6.3V6M [29,38] ACOFF 2
2
0.22U_0402_10V4Z PQ34
2
DTC115EUA_SC70-3
3
Change 300K / 0.22u delay
3
Ipeak=1A, Imax=0.7A
C C
PR135 B+
VL 2.2M_0402_5%
2 1
1
VS PR136
499K_0402_1%
1
PR137
2
100K_0402_1%
8
[8,36,37] MAINPWON PD14 PU1B
2 5
P
+
1 7 O
0.01U_0402_25V7K
[38] ACON 3 - 6
1
G
1
1000P_0402_50V7K
32.4
PC107
B BAS40CW_SOT323-3 LM393DR_SO8 PR138 B
4
1
1
191K_0402_1%
PC106
PC105 PR139
2
0.1U_0603_25V7K
PRG++ 2
2
499K_0402_1%
1
34K_0402_1% D 47K_0402_5%
2 1 2 2 1
RTCVREF G PACIN [35,38]
1
S
SSM3K7002FU_SC70-3
PQ36
ACIN
1
DTC115EUA_SC70-3
@ PR142
@PR142
Precharge detector 66.5K_0402_1% 2 +5VALW
Min. typ. Max.
2
H-->L 14.589V 14.84V 15.243V
3
L-->H 15.562V 15.97V 16.388V
BATT ONLY
Precharge detector
Min. typ. Max.
A
H-->L 6.138V 6.214V 6.359V A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401829 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 30, 2010 Sheet 41 of 45
5 4 3 2 1
5 4 3 2 1
D
PR144 D
200K_0402_1%
1 2 VGA_ON [29,34]
1
316K_0402_1% PC156
PR145 0.22U_0402_10V4Z
2
PR147
402K_0402_1% PU11
1
+1.8VSP1 2 1 1 FB EN/SYNC 10
PC153 2 9 PL9
.1U_0402_16V7K GND GND 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
PJ28 1 2 3 SW SW 8 1 2 +1.8VSP1
+5VALW
1 1 2 2 4 IN IN 7
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_25V6
10U_0805_10V4Z
10U_0805_10V4Z
JUMP_43X79 1 2 5 BS POK 6
B340A_SMA2
PR148 PR143
1
PC157
PC123
PC154
PD15
PC117
PC124
0_0402_5% 11 4.7_1206_5%
TP
2
MP2121DQ-LF-Z_QFN10_3X3
2
@
1
PC155
680P_0603_50V7K
2
C C
+5VALW
1
+3VALW PC109 @
1U_0402_6.3V6K
2
1
1
@PJ18
@ PJ18
JUMP_43X79
PU14
2
6 VCNTL
5 3 +1.8VSP2
2
VIN VOUT
9 VIN VOUT 4
1
8 @ PR149
@PR149
EN
1
@PC112
@ PC112 7 2 15K_0402_1% PC108 @ PC111 @
GND
4.7U_0603_6.3V6K POK FB 0.01U_0402_25V7K 22U_0805_6.3V6M
2
2
2
APL5913-KAC-TRL_SO8
1
@
1
B B
PR150 @
12K_0402_1%
2
@ PR151
200K_0402_1%
VGA_ON 1 2
1
@
PR146
1
@PC150
@ PC150 47K_0402_5%
0.1U_0402_10V7K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 42 of 45
5 4 3 2 1
A B C D E F G H
CPU_B+ PL15
LGATE_NB HCB4532KF-800T90_1812
PC183 1 2 B+
10U_1206_25V6M
2200P_0402_50V7K
33P_0402_50V8K
0.01U_0402_25V7K
100U_25V_M
2200P_0402_50V7K
2200P_0402_50V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
2 1 1
1
+
220U_25V_M
PC185
PC186
PC187
PC188
PQ50 1
1
1 1
PC219
PC220
PC221
PC222
2 1 2 1 UGATE_NB 8 1
G2 D2 +
PC343
7 2
2
PR214 PC184 S2/D1 D2 2
6 3
2
44.2K_0402_1% 1200P_0402_50V7K S2/D1 G1
5 S2/D1 S1 4
PR215 2
2_0603_5% AO4932_SO8
+5VS 1 2 PC189 PL16
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB
2 1 PHASE_NB 1 2
PR230
1
PC190 PR216 2.2_0603_5%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 PR217
2 1 4.7_1206_5% 1
2
PR218 PC191
10_0402_5% 0.22U_0603_10V7K + PC192
1 2
1 2 +CPU_CORE_NB 220U_D2_4VM
CPU_B+ 1 2 PC193
680P_0603_50V7K 2
PR219 +VDDNB
CPU_VDDNB_FB_H [8]
2
2_0603_5% PR221
+3VS +5VS +3VS 13.7K_0402_1%
Design Current: 2.8A
1
2 1 PHASE_NB Max current: 4A
PR220
0_0402_5% LGATE_NB OCP_min:5A
1
PC194 CPU_B+
0.1U_0603_16V7K PHASE_NB
2
1
2200P_0402_50V7K
PR222 PR223 UGATE_NB
0.01U_0402_25V7K
10U_1206_25V6M
10U_1206_25V6M
0_0402_5% @ 105K_0402_1%
5
2 1 CPU_VDDNB_FB_L [8]
PR224 PQ46
2
2
1
1
PC195
PC196
PC197
PC198
0_0402_5%
PR225
1
2
105K_0402_1% PR228 10_0402_5% UGATE0 4
@ 105K_0402_1% 48
47
46
45
44
43
42
41
40
39
38
37
2
1
PU15
2 PHASE0 2
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
VIN
VCC
2
3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
[29] VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +CPU_CORE
PR237 0_0402_5% OFS/VFIXEN BOOT_NB
2
1 2 2 35 BOOT0 PC199
TPCA8028-H_SOP-ADVANCE8-5
PGOOD BOOT0
5
[19] H_PWRGD_L 1 2 0.22U_0603_10V7K PR232
1
PR231 0_0402_5% @ 3 34 UGATE0 PQ48 PQ47@ 16.2K_0402_1%
PWROK UGATE0 PR233
2 1 4 33 PHASE0 4.7_1206_5%
TPCA8028-H_SOP-ADVANCE8-5
1
[8] CPU_SVD PR234 0_0402_5% SVD PHASE0
1 PR235 2
5 32 4 4 4.02K_0402_1%
1 2
SVC PGND0 +5VS
2 1
[8] CPU_SVC PR236 0_0402_5% 6 31 LGATE0 PC200 PC201
ENABLE ISL6265AHRTZ-T_TQFN48_6X6 LGATE0 680P_0603_50V7K 2 1
7 30
3
2
1
3
2
1
2
RBIAS PVCC .1U_0402_16V7K
[29,40] VR_ON 8 29 LGATE1
OCSET LGATE1
1
PR238 PR239 PC202
2 1 2 1 9 28 1U_0603_16V6K LGATE0
21.5K_0402_1% 95.3K_0402_1% VDIFF0 PGND1
ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE_0
VW0 BOOT1
Design Current: 25A
COMP1
VDIFF1
VSEN0
VSEN1
RTN0
RTN1
2200P_0402_50V7K
0.01U_0402_25V7K
ISN0
ISN1
VW1
ISP0
ISP1
FB1
10U_1206_25V6M
10U_1206_25V6M
Max current: 35A
TP
5
TPCA8030-H_SOP-ADV8-5
PQ51 OCP_min:42A
13
14
15
16
17
18
19
20
21
22
23
24
49
1
PC203
PC204
PC205
PC206
PR242 0_0402_5%
ISP0
ISN0
2
1
ISN1
ISP1
UGATE1 4
[8] CPU_VDD0_FB_H
0_0402_5%
VSEN0 0_0402_5%
2 PR244 1
2 PR250 1
0_0402_5%
PR241 PR240
+CPU_CORE 2 1 1 2 PHASE1
3 3
10_0402_5% PR243 PL18
2
3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
[8] CPU_VDD0_FB_L RTN0 BOOT1 1<BOM Structure>
2 1 2 1 2 +CPU_CORE
PR245 10_0402_5%
2
2 1 PC207
5
0.22U_0603_10V7K PR247
1
RTN1 PQ49 PQ52 @ 16.2K_0402_1%
[8] CPU_VDD1_FB_L PR246 10K_0402_1% PR248
2 1 TPCA8028-H_SOP-ADVANCE8-5 4.7_1206_5%
TPCA8028-H_SOP-ADVANCE8-5
1
1 PR249 2
@ PR252 1K_0402_1% 4 4 4.02K_0402_1%
1 2
+1.5VS 2 1
PC208 PC209
[8] CPU_VDD1_FB_H VSEN1 680P_0603_50V7K 2 1
PR251
3
2
1
3
2
1
2
+CPU_CORE 2 10_0402_5%
1 .1U_0402_16V7K
ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1
PR262 @ PR263 @
1K_0402_5% 1K_0402_5%
2
4 4
Cause GPU have GCORE_SEN and FB_GND pin ADD GCORE_SEN and FB_GND net, also add
3 Add GPU voltagr sence net so power add receive net. 0.1 51 PR296(0_0402_1%), PR297(10_0402_5%) and 2009/09/04 EVT_NEW75
PR298(0_0402_5%)
4 change DC-IN connector part number to meet pin definition 0.1 43 change part number is SP020908120 2009/09/10 EVT_NEW75
Add snubber and boost resistance Add 4.7 ohm to PR100, add cap. 680p to PC78 and
10 of 1.1Valw and 1.5V Cause follow EMI request 0.2 39 add 2.2 ohm toPR98. Add 4.7 ohm to PR110, add 2009/11/23 EVT_NEW75_6L
cap. 680p to PC88 and add 2.2 ohm toPR108
B B
12 Change chock Cause A phase put wrong chock 0.2 37,39,40 Change PL9 from SH00000FK00 to SH000009Q00 2009/11/23 EVT_NEW75_6L
Cause Hw request 1.1Valw need to set to 1.15V, so Change PR104 from SD000000680 (S RES 1/16W
13 Change resistance value change divider resistance PR104 0.2 39 8.45K +-1% 0402 ) to SD034887180 (S RES 2009/12/01 EVT_NEW75_6L
1/16W 8.87K +-1% 0402)
A A
ADD PR40, PR47,PR117 and PR230 from SD013000080
16 ADD Boost resistance Cause EMI request 0.2 37-43 (S RES 1/10W 0 +-5% 0603) to SD013220B80 (S RES 2009/12/01 EVT_NEW75_6L
1/10W 2.2 +-5% 0603 )
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 44 of 45
5 4 3 2 1
5 4 3 2 1
11/20
1. P.21 unstuff Y4, C588, C589, R368 for AMD suggest
2. P.19 Modify Y3 net connect
3. P.25 Change C923, C924 as 33pF for Y5
11/24
D D
1. P.13, P.15, P.20, P.23 Add Ext@ & Int@ option ; Modify CLK_SBLINK_BCLK net connect
2. P.13, P.16, P.20 Add VB@ & UNVB@ option
3. P.34 Change U38 as 4430(SB000007O10)
4. P.27 Add R835, R837 unstuff D44, R836 for WiMax/Wlan LED request ; change R492 as 100Komh for EC request
5. P.30 Change R477, R499 as 680ohm ; R478, R498 as 3.9kohm for LED brightness
11/25
1. P.19, P20 update SB GPIO PIN
2. P.29 Add R838, R839 for EC RevD3, E0
3. P.34 Add C972, C973, C974, C975, C976, C977, C978 for EMI Request
4. P.15 Remove R245, R247 for unSD CLK
5. P.13 Add R840 for CLK_NB_14.318
11/28
C C
1. P.30 JLED1, JLED2 Pin define modify; Add Q73
2. P.23 Add R841, R842, R843 ; P.29 Add R844, R845 for Panel Low Power
3. P.28 Change D10 P/N as SC300000B00 ; Stuff D41, D27, D39, D11, D13, D29, D24 For ESD Request
01/25
1. P.30 Change Q26 as SB00000DH00
2. P.29 Define U26 Pin 36, Pin 17, Pin 85, Pin86 for WWAN & WLAN
3. P.31 Reserve C979, C980, R849, R850 for EMI solution
4. P.9 Change C23, C24, C25, C26, C75 as SGA19331D10 (ESR 9 ohm)
03/02
1. P.29 Add R851, unstuff R852
A
03/30 For MP A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401829
Date: Wednesday, June 30, 2010 Sheet 45 of 45
5 4 3 2 1