A B C D E

1 1

2
Compal Confidential 2

G470/G570 DIS+UMA+Muxless M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
ATI Robson/PX3.0,PX4.0

3
2010-10-22 3

LA-6751P / LA-6753P
REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 1 of 59
A B C D E
 A B C D E

Compal confidential For 14"(Page 4x) For 15"(Page 4x+1)

File Name : G470/G570 LS6753P PWR/B LS6753P PWR/B
LS6751P CardReader/B LS6751P CardReader/B
WĂŐĞϮϯͲϯϬ LS6754P LED/B
AMD LS6755P ODD/B
Intel
1
Robson XT Sandy Bridge 1

VRAM 64*16 PCI-E x16 DDR3 SO-DIMM *2

DDR3*4 Socket-rPGA988B BANK 0, 1, 2, 3 WĂŐĞϭϮͲϭϯ
37.5mm*37.5mm
Dual Channel Up to 8GB
WĂŐĞϯϯ WĂŐĞϱͲϭϭ DDR3 1066MHz(1.5V)
HDMI
DDR3 1333MHz(1.5V)
Connector
100MHz
WĂŐĞϯϮ 2.7GT/s FDI *8 DMI *4
CRT
Connector Audio Codec 2 channel speaker
Intel
AZALIA Conexant
LVDS WĂŐĞϯϭ Cougar Point CX20671
Int. MIC
2 Connector FCBGA 989 2

WĂŐĞϯϵ
Audio Jacks
25mm*25mm
WĂŐĞϯϱ PCI-E x1 *6 USB2.0 *14
LAN
Athros Camera Conn.
AR8151-B(GLAN)
AR8152-B(10/100) SATA *6 BlueTooth Conn.
WĂŐĞϰϮ
WĂŐĞϭϰͲϮϮ
RJ-45 WĂŐĞϯϲ
SPIROM Mini Card Slot *1
WĂŐĞϯϰ
Connector BIOS
LPC BUS Card Reader
PCI Express PCI-E(WLAN)
WĂŐĞϰϬ Reltek
Mini Card Slot *1
EC RTS5139
3 USB(WiMAX) ENE KB930 SDXC/MMC/MS/xD 3

WLAN ENE KB9012

WiMAX WĂŐĞϯϰ USB2.0 *1(Right)
USB2.0 *2(Left)
Touch Pad Int. KBD

Thermal Sensor SPI ROM

WĂŐĞϰϭ
eSATA+USB(Left) WĂŐĞϰϮ
EMC1403 WĂŐĞϯϳ
SATA3 HDD (Port 0/Port 1 support SATA3)
WĂŐĞϯϴ

SATA ODD WĂŐĞϯϴ

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 2 of 59
A B C D E
 A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
1
+VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

+5VALW +1.5V +CPU_CORE

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +GFX_CORE
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
+1.05VS
Board ID PCB Revision
Ra/Rc/Re 100K +/- 5%
0 0.1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1
0 0 0 V 0 V 0 V EVT
2
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
3
2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
4
3 33K +/- 5% 0.712 V 0.819 V 0.875 V MP
S0
5
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
6
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
7
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
S3 7 NC 2.500 V 3.300 V 3.300 V
O O O X
2 2

S5 S4/AC
O O X X
USB Port Table BOM Structure Table
S5 S4/ Battery only
O X X X 3 External BTO Item BOM Structure
USB 2.0 USB 1.1 Port USB Port
S5 S4/AC & Battery
UMA and PX bus PX@
don't exist X X X X 0 USB/B (Right Side) Discrete Only DIS@
UHCI0 PX3.0 only, not for BACO
Address 1 USB Port (Left Side) PX3@
EC SM Bus1 address EC SM Bus2 address 2 USB Port (Left Side) BACO BACO@
UHCI1
3 USB Port (Left Side) COMMON HDMI HDMI@
Device Device Address EHCI1
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb
4 UMA HDMI UMA_HDMI@
UHCI2
Thermal Sensor EMC1402-1 100_1100 b
5 Camera Discrete HDMI VGA_HDMI@
6 eSATA ESATA@
UHCI3
7 Blue Tooth BT@
PCH SM Bus address 8 Mini Card(WLAN) Connector ME@
UHCI4
9 45 LEVEL 45@
Device Address
DDR DIMM0 1001 000Xb
10 10/100 LAN 8152@
3 EHCI2 UHCI5 3
DDR DIMM2 1001 010Xb
11 Card Reader GIGA LAN GIGA@
12 Cameara CMOS@
UHCI6
13 Blue Tooth

SMBUS Control Table

Unpop @
Thermal
WLAN Sensor
SOURCE VGA BATT KE930 SODIMM WWAN PCH

SMB_EC_CK1
SMB_EC_DA1
KB930 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB930 X X X X X X V
+3VS
+3VALW
SMBCLK
SMBDATA
PCH X X X V
+3VS +3VS
V X X
+3VALW
SML0CLK
SML0DATA
PCH X X X X X X X
+3VALW
4 4
SML1CLK
SML1DATA
PCH
+3VS
V X V
+3VS
X X V
+3VS
X
+3VALW

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 3 of 59
A B C D E
 5 4 3 2 1

tŝƚŚŽƵƚKŽƉƚŝŽŶ͗
Power-Up/Down Sequence Wͺ'W/KϬ͗>ŽǁͲхZĞƐĞƚĚ'Wh͖,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up Wͺ'W/Kϭ͗>ŽǁͲхĚ'WhWŽǁĞƌK&&͖,ŝŐŚͲхĚ'WhWŽǁĞƌKE
sequence, though a shorter ramp-up duration is preferred.
KŽƉƚŝŽŶ͗
2. VDDR3 should ramp-up before or simultaneously with VDDC. Wͺ'W/KϬ͗,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ;Ě'WhŝƐŶŽƚƌĞƐĞƚŽŶKŵŽĚĞͿ
Wͺ'W/Kϭ͗>ŽǁͲхĚ'WhWŽǁĞƌK&&͖,ŝŐŚͲхĚ'WhWŽǁĞƌKE;ĂůǁĂLJƐ,ŝŐŚͿ
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. Ě'WhWŽǁĞƌWŝŶƐ sŽůƚĂŐĞ Wyϯ͘Ϭ KDŽĚĞ DĂdžĐƵƌƌĞŶƚ
D

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and W/ͺWs͕W/ͺsZ͕d^s͕sZϰ͕sͺd͕ ϭ͘ϴs K&& KE ϭϲϳϵŵ
VDD_CT have ramped up. WͺWs͕W΀&͗΁ͺsϭϴ͕W΀͗΁ͺWs͕
W΀͗΁ͺsϭϴ͕s͕sϭ/͕ϮsY͕sϮ/͕
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
W>>ͺWs͕DWsϭϴ͕ĂŶĚ^Wsϭϴ
ramp-up (or vice versa).)
W΀&͗΁ͺsϭϬ͕W΀͗΁ͺsϭϬ͕W>>ͺs͕ĂŶĚ ϭ͘Ϭs K&& KE ϱϳϱŵ
^WsϭϬ
W/ͺs ϭ͘Ϭs K&& KE Ϯ
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
sZϯ͕ĂŶĚϮs ϯ͘ϯs K&& KE ϭϵϬŵ
/&ͺs;ĐƵƌƌĞŶƚĐŽŶƐƵŵƉƚŝŽŶсϱϱŵΛϭ͘Ϭs͕ŝŶ ^ĂŵĞĂƐ K&& KE ϳϬŵ
PCIE_VDDC(1.0V) KŵŽĚĞͿ s ^ĂŵĞĂƐ
W/ͺs
sZϭ ϭ͘ϱs K&& K&& Ϯ͘ϴ
C
VDDR1(1.5VGS) sͬs/ ϭ͘ϭϮs K&& K&& ϭϮ͘ϵ C

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)
PE_GPIO0 PE_EN K^ǁŝƚĐŚ
ŝ'Wh Ě'Wh
PERSTb BIF_VDDC

PE_GPIO1

REFCLK PX_mode

B нϯ͘ϯs>t MOS
нϯ͘ϯs'^ B

Straps Reset ϭ
нϭ͘ϱs SI4800
нϭ͘ϱs'^
Straps Valid нϭ͘Ϭs нϭ͘Ϭs'^
Regulator
Ϯ ϯ

Global ASIC Reset

н Regulator
нs'ͺKZ
нϭ͘ϴs нϭ͘ϴs'^
T4+16clock
SI4800
ϱ ϰ
PWRGOOD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 4 of 59
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
24.9_0402_1% - typical impedance = 14.5 mohms
JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 PCIE_CRX_GTX_N[0..15] <23>
DMI_RX#[2] PCIE_CRX_GTX_N15
<16> DMI_CRX_PTX_N3 B24 K33
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14
PEG_RX#[1] M35
<16> DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 B26
DMI_RX[1] PEG_RX#[3]
J35 PEG Static Lane Reversal - CFG2 is for the 16x

DMI
A24 J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
B23 H34 PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
PEG_RX#[6] PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 G21
DMI_TX#[0] PEG_RX#[7]
G33 CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9] PCIE_CRX_GTX_N5
D21 E34 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
C <16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N1 C

PCI EXPRESS* - GRAPHICS

<16> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
L35
PEG_RX[1] PCIE_CRX_GTX_P13
PEG_RX[2] K34
A21 H35 PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] PCIE_CRX_GTX_P11
<16> FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32
E19 G34 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] PCIE_CRX_GTX_P9
F18 G31

Intel(R) FDI
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P8
DISCRETE ONLY <16> FDI_CTX_PRX_N4 B21
FDI1_TX#[0] PEG_RX[7]
F33
C20 F30 PCIE_CRX_GTX_P7
FDI_FSYNC0 <16> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] PCIE_CRX_GTX_P6
1K_0402_5% 2 DIS@ 1 R2 D18 E35
<16> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PCIE_CRX_GTX_P5
FDI_FSYNC1 <16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] PCIE_CRX_GTX_P4
1K_0402_5% 2 DIS@ 1 R3 F32
PEG_RX[11] PCIE_CRX_GTX_P3
D34
1K_0402_5% 2 DIS@ FDI_INT PEG_RX[12] PCIE_CRX_GTX_P2
1 R4 <16> FDI_CTX_PRX_P0 A22 FDI0_TX[0] PEG_RX[13] E31
G19 C33 PCIE_CRX_GTX_P1
<16> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
1K_0402_5% 2 DIS@ 1 R5 FDI_LSYNC0 E20 B32 PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 G18 PCIE_CTX_GRX_N[0..15] <23>
1K_0402_5% 2 DIS@ FDI_LSYNC1 FDI0_TX[3] PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_N15
1 R6 <16> FDI_CTX_PRX_P4 B20 M29 C1 1 2 0.1U_0402_10V6K
FDI1_TX[0] PEG_TX#[0] PCIE_CTX_GRX_C_N14 C2 0.1U_0402_10V6K PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 C19 FDI1_TX[1] PEG_TX#[1] M32 1 2
D19 M31 PCIE_CTX_GRX_C_N13 C3 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N13
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N12 C4 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N12
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_N11
L29 C5 1 2 0.1U_0402_10V6K
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 0.1U_0402_10V6K PCIE_CTX_GRX_N10
<16> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
+1.05VS FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N9 C7 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N9
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
J30 PCIE_CTX_GRX_C_N8 C8 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N8
FDI_INT PEG_TX#[7] PCIE_CTX_GRX_C_N7 C9 0.1U_0402_10V6K PCIE_CTX_GRX_N7
<16> FDI_INT H20 FDI_INT PEG_TX#[8] J28 1 2
H29 PCIE_CTX_GRX_C_N6 C10 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N6
PEG_TX#[9]
1

FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5

<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R7 <16> FDI_LSYNC1 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N4 C12 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N4
B 24.9_0402_1% FDI1_LSYNC PEG_TX#[11] PCIE_CTX_GRX_C_N3 C13 0.1U_0402_10V6K PCIE_CTX_GRX_N3 B
PEG_TX#[12] F27 1 2
D28 PCIE_CTX_GRX_C_N2 C14 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N2
PEG_TX#[13] PCIE_CTX_GRX_C_N1 C15 0.1U_0402_10V6K PCIE_CTX_GRX_N1
F26 1 2
2

PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 0.1U_0402_10V6K PCIE_CTX_GRX_N0

PEG_TX#[15] E25 1 2
EDP_COMP A18
eDP_COMPIO PCIE_CTX_GRX_P[0..15] <23>
eDP_COMPIO and ICOMPO signals A17 M28 PCIE_CTX_GRX_C_P15 C17 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P15
eDP_HPD eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_C_P14 C18 0.1U_0402_10V6K PCIE_CTX_GRX_P14
B16 M33 1 2
should be shorted near balls eDP_HPD PEG_TX[1]
M30 PCIE_CTX_GRX_C_P13 C19 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P13
PEG_TX[2] PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_P12
and routed with typical PEG_TX[3]
L31 C20 1 2 0.1U_0402_10V6K
C15 L28 PCIE_CTX_GRX_C_P11 C21 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P11
impedance <25 mohms D15
eDP_AUX PEG_TX[4]
K30 PCIE_CTX_GRX_C_P10 C22 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5]
eDP

K27 PCIE_CTX_GRX_C_P9 C23 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P9

PEG_TX[6] PCIE_CTX_GRX_C_P8 C24 0.1U_0402_10V6K PCIE_CTX_GRX_P8
PEG_TX[7] J29 1 2
C17 J27 PCIE_CTX_GRX_C_P7 C25 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P7
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P6 C26 0.1U_0402_10V6K PCIE_CTX_GRX_P6
F16 eDP_TX[1] PEG_TX[9] H28 1 2
C16 G28 PCIE_CTX_GRX_C_P5 C27 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P5
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P4 C28 0.1U_0402_10V6K PCIE_CTX_GRX_P4
G15 eDP_TX[3] PEG_TX[11] E28 1 2
F28 PCIE_CTX_GRX_C_P3 C29 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P3
PEG_TX[12] PCIE_CTX_GRX_C_P2 C30 0.1U_0402_10V6K PCIE_CTX_GRX_P2
C18 eDP_TX#[0] PEG_TX[13] D27 1 2
E16 E26 PCIE_CTX_GRX_C_P1 C31 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P1
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_C_P0 C32 0.1U_0402_10V6K PCIE_CTX_GRX_P0
D16 eDP_TX#[2] PEG_TX[15] D25 1 2
F15
eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 5 of 59
5 4 3 2 1
 5 4 3 2 1

JCPU1B
D D
R10 0_0402_5% DG1.0
A28 CLK_CPU_DMI_R 1 2
BCLK CLK_CPU_DMI <15>

MISC

CLOCKS
C26 A27 CLK_CPU_DMII#_R R11 1 2
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
0_0402_5%
AN34
SKTOCC# R12
A16 2 1 1K_0402_5% DG1.0
DPLL_REF_CLK R13
DPLL_REF_CLK#
A15 2 1 1K_0402_5% +1.05VS
+1.05VS
closs to EC 250~750mils H_CATERR# AL33 CATERR#
R9 1

THERMAL
62_0402_5%
H_PECI AN33 R8 H_DRAMRST#
<19,40> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

DDR3
MISC
R15
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R16 2 1 140_0402_1%
<40> H_PROCHOT# PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP1 R17 2 1 25.5_0402_1% DDR3 Compensation Signals
SM_RCOMP[1] SM_RCOMP2 R18
SM_RCOMP[2]
A4 2 1 200_0402_1%

H_THRMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#

AP29 XDP_PRDY# +1.05VS

PRDY# XDP_PREQ#
PREQ# AP27

R22 AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5%

TCK

PWR MANAGEMENT
C 0_0402_5% XDP_TMS XDP_TDI R21 C
AR27 2 1 51_0402_5% PU/PD for JTAG signals

JTAG & BPM

H_PM_SYNC_R TMS XDP_TRST# XDP_TDO R23 @
<16> H_PM_SYNC 1 2 AM34 AP30 2 1 51_0402_5%
PM_SYNC TRST#
AR28 XDP_TDI XDP_TCK R24 2 1 51_0402_5%
R26 TDI XDP_TDO XDP_TRST# R25
AP26 2 1 51_0402_5%
0_0402_5%1 H_CPUPWRGD_R TDO
<19> H_CPUPWRGD 2 AP33 UNCOREPWRGOOD
2

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS

DBR#
R27 1 2 PM_DRAM_PWRGD_R V8
130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0
BPM#[0] XDP_BPM#1
AR29
1

BPM#[1] XDP_BPM#2
AR30
BUF_CPU_RST# BPM#[2] XDP_BPM#3
AR33 AT30
RESET# BPM#[3] XDP_BPM#4
AP32
BPM#[4] XDP_BPM#5
BPM#[5] AR31
AT31 XDP_BPM#6
BPM#[6] XDP_BPM#7
AR32
+3VALW BPM#[7]

1
C33 Sandy Bridge_rPGA_Rev1p0
0.1U_0402_16V4Z ME@
2
Buffered reset to CPU
10/12 reserve R880 / R882
+1.5V_CPU_VDDQ
0_0402_5% R882 +3VS
B @ B
<16,40> PCH_POK 1 2
1

0_0402_5% R880 R30

1 @ 2 U1 200_0402_5% +1.05VS
<16> SYS_PWROK 1
C34
5

R161 100K_0402_5% 0.1U_0402_16V4Z

2

1 2 1
P

+3VS B 2
4 PM_SYS_PWRGD_BUF R32
O 75_0402_5%
<16> PM_DRAM_PWRGD 2
A
G

5
74AHC1G09GW_TSSOP5 R34 U2
3

@ 43_0402_1% 1 3V

P
R33 BUF_CPU_RST# BUFO_CPU_RST# 4 NC
1 2 Y
39_0402_5% 2 PLT_RST#
A PLT_RST# <18>

G
1

SN74LVC1G07DCKR_SC70-5
1 2

3
D @ R35 @
SUSP 2 Q1 0_0402_5%
<10,44,51> SUSP
G 2N7002H_SOT23-3
2

S Change footprint
3

20100814

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 6 of 59
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D

<12> DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 <13>
AA6 M_CLK_DDR#0 <12> AD2 M_CLK_DDR#2 <13>
DDR_A_D0 SA_CLK#[0] DDR_B_D0 SB_CLK#[0]
C5 SA_DQ[0] SA_CKE[0] V9 DDR_CKE0_DIMMA <12> C9 SB_DQ[0] SB_CKE[0] R9 DDR_CKE2_DIMMB <13>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
D6 AA5 M_CLK_DDR1 <12> A9 AE1 M_CLK_DDR3 <13>
D DDR_A_D5 SA_DQ[4] SA_CLK[1] DDR_B_D5 SB_DQ[4] SB_CLK[1] D
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 <12> A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 <13>
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
C3 SA_DQ[7] D8 SB_DQ[7]
DDR_A_D8 F10 DDR_B_D8 G4
DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
F8 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 F2
DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
G7 SA_DQ[15] G2 SB_DQ[15]
DDR_A_D16 K4 AB3 DDR_B_D16 J7 AA1
DDR_A_D17 SA_DQ[16] RSVD_TP[4] DDR_B_D17 SB_DQ[16] RSVD_TP[14]
K5 AA3 J8 AB1
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K1 W10 K10 T10
DDR_A_D19 SA_DQ[18] RSVD_TP[6] DDR_B_D19 SB_DQ[18] RSVD_TP[16]
J1 SA_DQ[19] K9 SB_DQ[19]
DDR_A_D20 J5 DDR_B_D20 J9
DDR_A_D21 SA_DQ[20] DDR_B_D21 SB_DQ[20]
J4 SA_DQ[21] J10 SB_DQ[21]
DDR_A_D22 J2 AK3 DDR_B_D22 K8 AD3
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# <12> DDR_B_D23 SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# <13>
K2 AL3 DDR_CS1_DIMMA# <12> K7 AE3 DDR_CS3_DIMMB# <13>
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_B_D24 SB_DQ[23] SB_CS#[1]
M8 SA_DQ[24] RSVD_TP[7] AG1 M5 SB_DQ[24] RSVD_TP[17] AD6
DDR_A_D25 N10 AH1 DDR_B_D25 N4 AE6
DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D26 SB_DQ[25] RSVD_TP[18]
N8 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 N1
DDR_A_D28 SA_DQ[27] DDR_B_D28 SB_DQ[27]
M10 SA_DQ[28] M4 SB_DQ[28]
DDR_A_D29 M9 AH3 DDR_B_D29 N5 AE4
SA_DQ[29] SA_ODT[0] M_ODT0 <12> SB_DQ[29] SB_ODT[0] M_ODT2 <13>

DDR SYSTEM MEMORY B

DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4

DDR SYSTEM MEMORY A

DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 <12> DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 <13>
M7 AG2 M1 AD5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AG6 AH2 AM5 AE5
DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D33 SB_DQ[32] RSVD_TP[20]
AG5 SA_DQ[33] AM6 SB_DQ[33]
DDR_A_D34 AK6 DDR_B_D34 AR3
DDR_A_D35 SA_DQ[34] DDR_B_D35 SB_DQ[34]
AK5 SA_DQ[35] AP3 SB_DQ[35]
DDR_A_D36 AH5 DDR_B_D36 AN3
C DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 J3 AP2 K6
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D43 AT6 AK12 DDR_B_DQS#6
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AH8 SA_DQ[44] SA_DQS#[7] AM15 AP6 SB_DQ[44] SB_DQS#[7] AP15
DDR_A_D45 AH9 DDR_B_D45 AN8
DDR_A_D46 SA_DQ[45] DDR_B_D46 SB_DQ[45]
AL9 SA_DQ[46] AR6 SB_DQ[46]
DDR_A_D47 AL8 DDR_B_D47 AR5
DDR_A_D48 SA_DQ[47] DDR_B_D48 SB_DQ[47]
AP11 DDR_A_DQS[0..7] <12> AR9 DDR_B_DQS[0..7] <13>
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AN11 SA_DQ[49] SA_DQS[0] D4 AJ11 SB_DQ[49] SB_DQS[0] C7
DDR_A_D50 AL12 F6 DDR_A_DQS1 DDR_B_D50 AT8 G3 DDR_B_DQS1
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AM12 SA_DQ[51] SA_DQS[2] K3 AT9 SB_DQ[51] SB_DQS[2] J6
DDR_A_D52 AM11 N6 DDR_A_DQS3 DDR_B_D52 AH11 M3 DDR_B_DQS3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AL11 SA_DQ[53] SA_DQS[4] AL5 AR8 SB_DQ[53] SB_DQS[4] AN6
DDR_A_D54 AP12 AM9 DDR_A_DQS5 DDR_B_D54 AJ12 AP8 DDR_B_DQS5
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AN12 AR11 AH12 AK11
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 AM14 AT11 AP14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AH14 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 SA_DQ[60] DDR_A_MA[0..15] <12> AT12 SB_DQ[60] DDR_B_MA[0..15] <13>
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
W7 T6
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
SA_MA[4] V3 SB_MA[4] T2
V2 DDR_A_MA5 T4 DDR_B_MA5
SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
SA_MA[6] W3 SB_MA[6] T3
AE10 W6 DDR_A_MA7 AA9 R2 DDR_B_MA7
B <12> DDR_A_BS0 SA_BS[0] SA_MA[7] <13> DDR_B_BS0 SB_BS[0] SB_MA[7] B
AF10 V1 DDR_A_MA8 AA7 T5 DDR_B_MA8
<12> DDR_A_BS1 SA_BS[1] SA_MA[8] DDR_A_MA9 <13> DDR_B_BS1 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS2 V6 SA_BS[2] SA_MA[9] W5 <13> DDR_B_BS2 R6 SB_BS[2] SB_MA[9] R3
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_RAS# AB8 R5
SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_WE# AF9 SA_WE# SA_MA[15] V7 <13> DDR_B_WE# AB9 SB_WE# SB_MA[15] R4

Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0

ME@ ME@

+1.5V

@ R36
1

0_0402_5%
1 2 R37
1K_0402_5%

R38
2

1K_0402_5%
S

<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# <12,13>

2

Q2
R39 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
1

A R40 A
0_0402_5%
<15> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

1
C35
Eiffel used 0.01u Security Classification Compal Secret Data Compal Electronics, Inc.
Module design used 0.047u Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
0.047U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6751P
WWW.AliSaler.Com 5 4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 2
Date: Friday, November 26, 2010

1
Sheet 7 of 59
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x

RSVD28
L7 1: Normal Operation; Lane # definition matches
RSVD29
AG7 CFG2 socket pin map definition
AK28 CFG[0] RSVD30 AE7
AK29 AK2
CFG2 CFG[1] RSVD31
AL26 W8 0:Lane Reversed
CFG4
AL27
AK26
CFG[2]
CFG[3]
CFG[4]
RSVD32
*
CFG5 AL29 AT26 CFG4
CFG6 CFG[5] RSVD33
AL30 AM33
CFG[6] RSVD34

1
CFG7 AM31 AJ27
CFG[7] RSVD35
AM32 CFG[8]
AM30 @ R42
CFG[9] 1K_0402_1%
AM28
CFG[10]
AM26

2
CFG[11]
AN28 CFG[12]
AN31 T8
CFG[13] RSVD37
AN26 J16
CFG[14] RSVD38
AM27 H16
CFG[15] RSVD39
AK31 G16
CFG[16] RSVD40
AN29 CFG[17]
Display Port Presence Strap

C C
AR35 1 : Disabled; No Physical Display Port
T9
T10
PAD
PAD
AJ31
AH31
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD41
RSVD42
RSVD43
AT34
AT33
CFG4 * attached to Embedded Display Port
T11 PAD AJ33 AP35
VCC_VAL_SENSE RSVD44
T12 PAD AH33
VSS_VAL_SENSE RSVD45 AR34 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ26
RSVD5

RESERVED
B34 CFG6
RSVD46
B4 A33
RSVD6 RSVD47 CFG5
D1 A34
RSVD7 RSVD48
B35
RSVD49

1
C35
RSVD50
1

@ R43 @ R44
R64 R353 F25 1K_0402_1% 1K_0402_1%
1K_0402_1% 1K_0402_1% RSVD8
F24
RSVD9
F23

2
RSVD10
D24 AJ32
2

RSVD11 RSVD51
G25 AK32
RSVD12 RSVD52
G24
RSVD13
8/5 Check E23
RSVD14
D23
RSVD15 PAD T13
C30 AH27
RSVD16 VCC_DIE_SENSE
A31
RSVD17
B30
RSVD18
B29
RSVD19 PCIE Port Bifurcation Straps
D30 AN35
RSVD20 RSVD54
B31 AM35
RSVD21 RSVD55
A30 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
C29
RSVD22
RSVD23
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

J20
disabled
RSVD24
B18
RSVD25 RSVD56
AT2 01: Reserved - (Device 1 function 1 disabled ; function
A19 AT1 2 enabled)
VCCIO_SEL RSVD57
AR1
RSVD58
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
J15
RSVD27

B1
KEY CFG7

1
@R45
@ R45
1K_0402_1%

Sandy Bridge_rPGA_Rev1p0

2
ME@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 8 of 59
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+CPU_CORE Cap quantity follow HR_PDDG_Rev07
(6/16 change 10uF_0603_6.3V)*5 22uF*7 NO-STUFF
QC=94A +1.05VS
18A
DC=53A AG35
OSCAN(22uF_0805_6.3V)*13
VCC1 +1.05VS
1 1 1 1 1 AG34 VCC2 VCCIO1
AH13

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AG33 AH10 1 1 1 1 1 1 1 1 1 1
VCC3 VCCIO2

C36

C37

C38

C39

C40

22U_0805_6.3V6M
C41

22U_0805_6.3V6M
C42

22U_0805_6.3V6M
C43

22U_0805_6.3V6M
C44

22U_0805_6.3V6M
C54

22U_0805_6.3V6M
C45

22U_0805_6.3V6M
C46

22U_0805_6.3V6M
C55

22U_0805_6.3V6M
C56

22U_0805_6.3V6M
C47
AG32 AG10
VCC4 VCCIO3
AG31 AC10
D 2 2 2 2 2 VCC5 VCCIO4 D
AG30 Y10
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
1 1 1 1 1 1 AF34 J12
10U_0603_6.3V6M VCC12 VCCIO11
C48

10U_0603_6.3V6M
C49

10U_0603_6.3V6M
C50

10U_0603_6.3V6M
C51

10U_0603_6.3V6M
C52

10U_0603_6.3V6M
C53
AF33 J11 1 1 1 1 1 1 1 1 1
VCC13 VCCIO12

22U_0805_6.3V6M
C57

22U_0805_6.3V6M
C58

22U_0805_6.3V6M
C59

22U_0805_6.3V6M
C60

22U_0805_6.3V6M
C61

22U_0805_6.3V6M
C62

22U_0805_6.3V6M
C63

22U_0805_6.3V6M
C64

22U_0805_6.3V6M
C65
AF32 H14
VCC14 VCCIO13 @ @ @ @ @ @ @
AF31 H12
2 2 2 2 2 2 VCC15 VCCIO14
AF30 H11
VCC16 VCCIO15 2 2 2 2 2 2 2 2 2
AF29 VCC17 VCCIO16 G14
@ AF28 G13
VCC18 VCCIO17

PEG AND DDR

AF27 VCC19 VCCIO18
G12
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20
F13
AD34 F12
+CPU_CORE (22uF_0805_6.3V)*16 AD33
VCC22 VCCIO21
F11
VCC23 VCCIO22
AD32 VCC24 VCCIO23
E14

330U_D2_2.5VY_R9M
AD31 VCC25 VCCIO24 E12 1 1 1

C73
AD30 VCC26
AD29 E11 + C69 + C72 +
1 1 1 1 1 VCC27 VCCIO25
22U_0805_6.3V6M
C66

22U_0805_6.3V6M
C67

22U_0805_6.3V6M
C68

22U_0805_6.3V6M
C70

22U_0805_6.3V6M
C71
AD28 D14 220U_6.3V_M 220U_6.3V_M @
VCC28 VCCIO26
AD27 VCC29 VCCIO27 D13
2 2 2
AD26 VCC30 VCCIO28
D12
@ 2 2 2 2 2
AC35 D11
AC34
VCC31 VCCIO29
C14
OSCAN
VCC32 VCCIO30
AC33 C13
AC32
VCC33 VCCIO31
C12
(220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00)
VCC34 VCCIO32
AC31 VCC35 VCCIO33
C11
AC30 VCC36 VCCIO34 B14
1 1 1 1 1 AC29 VCC37 VCCIO35
B12
22U_0805_6.3V6M
C74

22U_0805_6.3V6M
C75

22U_0805_6.3V6M
C76

22U_0805_6.3V6M
C77

22U_0805_6.3V6M
C78
C C
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37
A13
AC26 VCC40 VCCIO38
A12
2 2 2 2 2 AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31
VCC45
AA30
VCC46
1 1 1 1 1 AA29
VCC47
22U_0805_6.3V6M
C79

22U_0805_6.3V6M
C80

22U_0805_6.3V6M
C81

22U_0805_6.3V6M
C82

22U_0805_6.3V6M
C83

AA28
VCC48
AA27
@ @ VCC49
AA26
2 2 2 2 2 VCC50

CORE SUPPLY
Y35 +1.05VS
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54

1
Y31 VCC55
Y30 R46
VCC56
1 1 1 1 Y29 75_0402_5%
VCC57
22U_0805_6.3V6M
C84

22U_0805_6.3V6M
C85

22U_0805_6.3V6M
C86

22U_0805_6.3V6M
C87

Y28
VCC58
Y27 VR_SVID_CLK series-resistors close to VR

2
VCC59
Y26
2 2 2 2 VCC60
V35
VCC61

SVID
V34 AJ29 H_CPU_SVIDALRT# R47 1 2 43_0402_5%
VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# <53>
V33 AJ30 R48 1 2 0_0402_5%
VCC63 VIDSCLK H_CPU_SVIDDAT VR_SVID_CLK <53>
V32 AJ28 R49 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT <53>
V31
+CPU_CORE VCC65
V30
VCC66 R50
V29 2 1 130_0402_5% +1.05VS
VCC67
V28
VCC68
V27
B VCC69 B
V26
VCC70
330U_X_2VM_R6M

330U_X_2VM_R6M

330U_X_2VM_R6M

330U_X_2VM_R6M

1 1 1 1 1 1 1 U35
VCC71
330U_X_2VM_R6M

330U_X_2VM_R6M

330U_X_2VM_R6M

C394 C397 C400 U34

VCC72
C88

C89

C90

C91

+ + + + + + + U33
VCC73
U32
(330uF)*4 U31
VCC74
2 2 2 2 2 2 2 U30
VCC75 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
VCC76
U29
VCC77
U28
@ @ @ VCC78
U27
VCC79
U26
VCC80 +CPU_CORE
R35
VCC81
R34
VCC82
R33
VCC83

1
R32
VCC84 R51
10/21 modify R31
VCC85
R30 100_0402_1%
VCC86
R29
VCC87
SENSE LINES

R28

2
VCC88
R27 AJ35 VCCSENSE_R R52 1 2 0_0402_5%
VCCSENSE <53>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R R53 1 2 0_0402_5%
VSSSENSE <53>
VCC90 VSS_SENSE
P35
VCC91
P34
VCC92

1
P33
VCC93 R54
P32 B10 VCCIO_SENSE <51>
VCC94 VCCIO_SENSE
P31 A10 1 2 100_0402_1%
VCC95 VSSIO_SENSE R74
P30
VCC96 0_0402_5% VSSIO_SENSE
P29 1 2

2
VCC97 @ R75
P28
VCC98 0_0402_5%
P27
VCC99 @
P26
VCC100
A VSS_SENCE 100ohm +-1% pull-down to GND near processor A

8/12 Modify, need follow diffential routing

R74 close CPU,R75 close PWR

Sandy Bridge_rPGA_Rev1p0
ME@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 9 of 59
5 4 3 2 1
 5 4 3 2 1

+1.5V @ J1 +1.5V_CPU_VDDQ
1 2
8/27 change to stuff +1.5V
PAD-OPEN 4x4m 1

1
1 2 R55 @ C92
<6,44,51> SUSP 0_0402_5% R668 220_0402_5% 0.1U_0402_10V6K
2 @ @

12
U3 D

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C95

C96

C129

C396
+3VALW +VSB DMN3030LSS-13_SOP8L-8 Q3 2 RUN_ON_CPU1.5VS3# 1 1 1 1
8 1 2N7002H_SOT23-3 G
D Change footprint D
8/27 change to @ 7 2 S

3
1
6 3 20100814

1
R56 5 +1.5V_CPU_VDDQ 2 2 2 2
R667
100K_0402_5% @ 15K_0402_1%

4
2
2
R885 11/18 add for sequence
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 2

1
@ 1

1
D D 0_0402_5%
1 @ 2 2 Q7 2 Q4 R57 C97
<40> CPU1.5V_S3_GATE
0_0402_5% R58 G 2N7002H_SOT23-3 G 2N7002H_SOT23-3 330K_0402_5% 0.1U_0603_25V7K
S Change footprint S @ 2

2
1 @ 2 20100814
<26,40,44,49,51,52> SUSP#
0_0402_5% R59

Change footprint
20100814

+VGFX_CORE
8/27 change to @
JCPU1G
POWER

SENSE
LINES
AT24 VAXG1 VAXG_SENSE
AK35 VCC_AXG_SENSE <53>
AT23 VAXG2 VSSAXG_SENSE
AK34 VSS_AXG_SENSE <53>
1

1 1 1 1 1 1 1 1 1 1 AT21 VAXG3
22U_0805_6.3V6M
C98

22U_0805_6.3V6M
C99

22U_0805_6.3V6M
C100

22U_0805_6.3V6M
C101

22U_0805_6.3V6M
C102

22U_0805_6.3V6M
C103

22U_0805_6.3V6M
C104

22U_0805_6.3V6M
C105

22U_0805_6.3V6M
C106

22U_0805_6.3V6M
C107
AT20 VAXG4
0_0402_5% +1.5V_CPU_VDDQ
AT18 VAXG5
R60 AT17 R61
DIS@ 2 2 2 2 2 2 2 2 2 2 VAXG6 0_0402_5%
AR24
2

VAXG7

1
AR23 VAXG8 2 1
C PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ C
AR21 VAXG9
AR20 R62
VAXG10

VREF
AR18 1K_0402_1%
VAXG11
AR17

2
VAXG12 +V_SM_VREF_CNT +V_SM_VREF
AP24 AL1 3 1
VAXG13 SM_VREF
AP23 VAXG14

1
AP21 1 100K_0402_5% Q5 @
VAXG15 C114 R666 AP2302GN-HF_SOT23-3
1 1 1 1 1 1 AP20 VAXG16
22U_0805_6.3V6M
C108

22U_0805_6.3V6M
C109

22U_0805_6.3V6M
C110

22U_0805_6.3V6M
C111

22U_0805_6.3V6M
C112

22U_0805_6.3V6M
C113 AP18 0.1U_0402_16V4Z @ R63
VAXG17 2 1K_0402_1%
AP17 VAXG18
AN24 2 RUN_ON_CPU1.5VS3

2
2 2 2 2 2 2 VAXG19
AN23
VAXG20
AN21 VAXG21
PX@ PX@ @ @ PX@ PX@ AN20
VAXG22

DDR3 -1.5V RAILS

AN18
AN17
VAXG23 +1.5V_CPU_VDDQ 10/5 change to 1K
VAXG24

GRAPHICS
AM24 VAXG25 VDDQ1
AF7
10/21 Change AM23
AM21
VAXG26 VDDQ2 AF4
AF1
VAXG27 VDDQ3 1
330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

1 1 AM20 AC7 1 1 1 1 1 1
VAXG28 VDDQ4
C115

C116

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 + C123
+ + @ VAXG29 VDDQ5 330U_2.5V_M
AM17 VAXG30 VDDQ6
AC1
PX@ AL24 Y7
VAXG31 VDDQ7 2 2 2 2 2 2 2
AL23 VAXG32 VDDQ8
Y4
2 2 AL21 Y1
VAXG33 VDDQ9
AL20 VAXG34 VDDQ10 U7
AL18 VAXG35 VDDQ11 U4
AL17 U1
VAXG36 VDDQ12
AK24 VAXG37 VDDQ13 P7
AK23 P4
VAXG38 VDDQ14
AK21 VAXG39 VDDQ15 P1
AK20
B VAXG40 B
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21
VAXG45
AJ20 VAXG46
AJ18
VAXG47
AJ17 VAXG48
AH24 +VCCSA

SA RAIL
VAXG49
AH23 VAXG50
AH21 M27 +VCCSA
VAXG51 VCCSA1
AH20 VAXG52 VCCSA2
M26
AH18 L26 @
VAXG53 VCCSA3 R65 VCCSA_SENSE
AH17 J26 1 1 1 1 1 2 0_0402_5% VCCSA_SENSE <50>
VAXG54 VCCSA4

10U_0805_6.3V6M
C124

10U_0805_6.3V6M
C125

10U_0805_6.3V6M
C126

10U_0805_6.3V6M
C127

330U_D2_2.5VY_R9M
J25 1
VCCSA5

C128
Sandy Bridge_rPGA_Rev1p0 J24
ME@ VCCSA6 +
H26
VCCSA7 2 2 2 2 @
H25
VCCSA8
2 R66
1.8V RAIL

1 2 0_0402_5% VSSSA_SENSE <50>

+1.8VS R67
0_0805_5% 9/27 update C128 to D2 and @
1 2 +1.8VS_VCCPLL B6 H23 VCCSA_SENSE
VCCPLL1 VCCSA_SENSE
MISC

A6
VCCPLL2
10U_0805_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

1 1 1 1 A2 @
VCCPLL3
22U_0805_6.3V6M
C154

22U_0805_6.3V6M
C345

1 R68 1 2 0_0402_5%
FC_C22 C22 H_FC_C22
C24
2 @ 2 @ 2 2 VCCSA_VID1
2 R69 1 2 10K_0402_5%
A A

VCCSA_SEL <50>

6/9 change 330U to 22U X2

Security Classification Compal Secret Data
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 10 of 59
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I
D D
AT35 AJ22
VSS1 VSS81
AT32 AJ19
VSS2 VSS82
AT29 AJ16 T35 F22
VSS3 VSS83 VSS161 VSS234
AT27 AJ13 T34 F19
VSS4 VSS84 VSS162 VSS235
AT25 AJ10 T33 E30
VSS5 VSS85 VSS163 VSS236
AT22 AJ7 T32 E27
VSS6 VSS86 VSS164 VSS237
AT19 AJ4 T31 E24
VSS7 VSS87 VSS165 VSS238
AT16 AJ3 T30 E21
VSS8 VSS88 VSS166 VSS239
AT13 AJ2 T29 E18
VSS9 VSS89 VSS167 VSS240
AT10 AJ1 T28 E15
VSS10 VSS90 VSS168 VSS241
AT7 AH35 T27 E13
VSS11 VSS91 VSS169 VSS242
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9
VSS171 VSS244
E9
AR25 VSS14 VSS94 AH30 P8
VSS172 VSS245
E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5
VSS174 VSS247
E6
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5
AR13 VSS18 VSS98 AH25 P2
VSS176 VSS249
E4
AR10 VSS19 VSS99 AH22 N35
VSS177 VSS250
E3
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2
AR4 VSS21 VSS101
AH16 N33
VSS179 VSS252
E1
AR2 VSS22 VSS102
AH7 N32
VSS180 VSS253
D35
AP34 VSS23 VSS103
AH4 N31
VSS181 VSS254
D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105
AG8 N29
VSS183 VSS256
D26
AP25 VSS26 VSS106
AG4 N28
VSS184 VSS257
D20
AP22 VSS27 VSS107
AF6 N27
VSS185 VSS258
D17
AP19 VSS28 VSS108
AF5 N26
VSS186 VSS259
C34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 VSS30 VSS110
AF2 L33
VSS188 VSS261
C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112
AE34 L27
VSS190 VSS263
C25
C C
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114
AE32 L8
VSS192 VSS265
C10
AN30 VSS35 VSS115
AE31 L6
VSS193 VSS266
C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
AN25 AE29 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE26 L1 B13
VSS40 VSS120 VSS198 VSS271
AN13 AE9 K35 B11
VSS41 VSS121 VSS199 VSS272
AN10 AD7 K32 B9
VSS42 VSS122 VSS200 VSS273
AN7 AC9 K29 B8
VSS43 VSS123 VSS201 VSS274
AN4 AC8 K26 B7
VSS44 VSS124 VSS202 VSS275
AM29 AC6 J34 B5
VSS45 VSS125 VSS203 VSS276
AM25 AC5 J31 B3
VSS46 VSS126 VSS204 VSS277
AM22 AC3 H33 B2
VSS47 VSS127 VSS205 VSS278
AM19 AC2 H30 A35
VSS48 VSS128 VSS206 VSS279
AM16 AB35 H27 A32
VSS49 VSS129 VSS207 VSS280
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29
AM10 AB33 H21 A26
VSS51 VSS131 VSS209 VSS282
AM7 AB32 H18 A23
VSS52 VSS132 VSS210 VSS283
AM4 AB31 H15 A20
VSS53 VSS133 VSS211 VSS284
AM3 AB30 H13 A3
VSS54 VSS134 VSS212 VSS285
AM2 AB29 H10
VSS55 VSS135 VSS213
AM1 AB28 H9
VSS56 VSS136 VSS214
AL34 AB27 H8
VSS57 VSS137 VSS215
AL31 AB26 H7
VSS58 VSS138 VSS216
AL28 Y9 H6
VSS59 VSS139 VSS217
AL25 Y8 H5
VSS60 VSS140 VSS218
AL22 Y6 H4
VSS61 VSS141 VSS219
AL19 Y5 H3
VSS62 VSS142 VSS220
AL16 Y3 H2
VSS63 VSS143 VSS221
AL13 Y2 H1
B VSS64 VSS144 VSS222 B
AL10 W35 G35
VSS65 VSS145 VSS223
AL7 W34 G32
VSS66 VSS146 VSS224
AL4 W33 G29
VSS67 VSS147 VSS225
AL2 W32 G26
VSS68 VSS148 VSS226
AK33 W31 G23
VSS69 VSS149 VSS227
AK30 W30 G20
VSS70 VSS150 VSS228
AK27 W29 G17
VSS71 VSS151 VSS229
AK25 W28 G11
VSS72 VSS152 VSS230
AK22 W27 F34
VSS73 VSS153 VSS231
AK19 W26 F31
VSS74 VSS154 VSS232
AK16 U9 F29
VSS75 VSS155 VSS233
AK13 U8
VSS76 VSS156
AK10 U6
VSS77 VSS157
AK7 U5
VSS78 VSS158
AK4 U3
VSS79 VSS159
AJ25 U2
VSS80 VSS160

Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0

ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 11 of 59
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMA +1.5V +1.5V +1.5V

4BA2/6W
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A

1
<7> DDR_A_DQS[0..7]
R70
JDIMM1 1K_0402_1%
<7> DDR_A_DQS#[0..7] +VREF_DQ_DIMMA
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D4
3 4 <7> DDR_A_MA[0..15]

2
VSS2 DQ4

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C133

C134
1 1 DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10

1
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6 R71
15 DQ2 DQ6 16
D DDR_A_D3 17 18 DDR_A_D7 1K_0402_1% D
DQ3 DQ7
19 20

2
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 DQ8 DQ12 22
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# <7,13>
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

C CKE0 CKE1 DDR_CKE1_DIMMA <7> C
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
<7> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
M_CLK_DDR0 101 102 M_CLK_DDR1
<7> M_CLK_DDR0
<7> M_CLK_DDR#0 M_CLK_DDR#0 103
CK0 CK1
104 M_CLK_DDR#1
M_CLK_DDR1 <7> OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0# CK1# M_CLK_DDR#1 <7>
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1 Layout Note:
<7> DDR_A_BS0 DDR_A_BS0 109
A10/AP BA1
110 DDR_A_RAS#
DDR_A_BS1 <7> +1.5V (10uF_0603_6.3V)*8
BA0 RAS# DDR_A_RAS# <7>
111 112 Place near DIMM
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
113 114
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7> (0.1uF_402_10V)*4

1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118 R72
DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
119 A13 ODT1 120 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CA +1.5V
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C135

C136

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
133 VSS29 VSS30 134 1

C137

C138

C139

C140

C141

C142

C143

C144

C145

C146

C147

C148
DDR_A_DQS#4 135 136 DDR_A_DM4 R73 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS4 DQS#4 DM4 1K_0402_1% + C149
137 DQS4 VSS31 138
B DDR_A_D38 2 2 220U_6.3V_M B
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 @ @
141 DQ34 DQ39 142
DDR_A_D35 2 2 2 2 2 2 2 2 2 2 2 2 2
143 DQ35 VSS33 144
145 146 DDR_A_D44
DDR_A_D40 VSS34 DQ44 DDR_A_D45 @
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5
151 VSS36 DQS#5 152
DDR_A_DM5 153 154 DDR_A_DQS5
DM5 DQS5
155 VSS37 VSS38 156 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR)
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166 Layout Note:
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 VTT(0.75V) = Place near DIMM
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54 3*0805 10uf 4*0402 1uf 7/28 Update connect GND directly
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 VREF =
DQ51 VSS45 DDR_A_D60 +0.75VS
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf DDR_A_DM0
DDR_A_D57 DQ56 DQ61 DDR_A_DM1
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 VDDSPD (3.3V)= DDR_A_DM2
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7 DDR_A_DM3
187 DM7 DQS7 188

C150

1U_0402_6.3V6K
C151

1U_0402_6.3V6K
C152

1U_0402_6.3V6K
C153

1U_0402_6.3V6K
189 190 1*0402 0.1uf 1*0402 2.2uf DDR_A_DM4
DDR_A_D58 VSS49 VSS50 DDR_A_D62 DDR_A_DM5
191 DQ58 DQ62 192 1 1 1 1
DDR_A_D59 193 194 DDR_A_D63 DDR_A_DM6
DQ59 DQ63
1 R81 2 195 VSS51 VSS52 196 DDR_A_DM7
10K_0402_5% 197 198
SA0 EVENT# SMB_DATA_S3 2 2 2 2
+3VS 199 VDDSPD SDA 200 SMB_DATA_S3 <13,15,34>
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

201 202 SMB_CLK_S3 Layout Note:

SA1 SCL SMB_CLK_S3 <13,15,34>
C155

C156

A 203 204 @ @ A
1 1 VTT1 VTT2 +0.75VS
1

Place near DIMM

10K_0402_5%
R83

205 206 1/76BA1/86W

G1 G2
2 2 FOX_AS0A626-U4SN-7F
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 12 of 59
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+VREF_DQ_DIMMB 4BA2/6W
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
JDIMM2 +1.5V
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS1 DDR_B_D4
3 VSS2 DQ4 4 <7> DDR_B_MA[0..15]

1
2.2U_0603_6.3V4Z

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5 R84
1 1 7 DQ1 VSS3 8
9 10 DDR_B_DQS#0 1K_0402_1%
C158 VSS4 DQS#0 +VREF_DQ_DIMMB

C157
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 14

2
2 2 DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7
D DQ3 DQ7 D
19 VSS7 VSS8 20

1
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 26 R85
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1 1K_0402_1%
27 DQS#1 DM1 28
DDR_B_DQS1 29 30 DDR3_DRAMRST#
DDR3_DRAMRST# <7,12>

2
DQS1 RESET#
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42 For Arranale only +VREF_DQ_DIMMB
43 VSS15 VSS16 44
DDR_B_DQS#2 45 DQS#2 DM2 46 DDR_B_DM2 supply from a external 1.5V voltage divide
DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
circuit.
49 VSS18 DQ22 50
DDR_B_D18 51 DQ18 DQ23 52 DDR_B_D23 07/17/2009
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD1 VDD2 76
C 77 78 DDR_B_MA15 C
DDR_B_BS2 NC1 A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<7> M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7> +1.5V
DDR_B_BS0 109 110 DDR_B_RAS# Layout Note:
<7> DDR_B_BS0
111
BA0 RAS#
112
DDR_B_RAS# <7> (10uF_0603_6.3V)*8
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB# Place near DIMM
<7> DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB# <7>

1
DDR_B_CAS# 115 116 M_ODT2
<7> DDR_B_CAS#
117
CAS# ODT0
118
M_ODT2 <7>
R86 (0.1uF_402_10V)*4
DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1%
119 A13 ODT1 120 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CB
125 NCTEST VREF_CA 126
+1.5V
0.1U_0402_10V6K

2.2U_0603_6.3V4Z
127 VSS27 VSS28 128
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
C159

C160
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
133 VSS29 VSS30 134

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_B_DQS#4 135 136 DDR_B_DM4 R87
DQS#4 DM4

C161

C162

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
DDR_B_DQS4 137 138 1K_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS31 DDR_B_D38 2 2
139 140

2
B DDR_B_D34 VSS32 DQ38 DDR_B_D39 B
141 DQ34 DQ39 142
DDR_B_D35 143 144 @ @
DQ35 VSS33 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 DM5 DQS5 154 VDDQ(1.5V) =
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166 Layout Note:
167 VSS41 VSS42 168 VTT(0.75V) =
DDR_B_DQS#6 169 DQS#6 DM6 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174 7/28 Update connect GND directly
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
DDR_B_D60 +0.75VS
179 VSS46 DQ60 180 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61 DDR_B_DM0
183 DQ57 VSS47 184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7 DDR_B_DM1
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7 DDR_B_DM2
187 DM7 DQS7 188 1*0402 0.1uf 1*0402 2.2uf

C173

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C175

1U_0402_6.3V6K
C176

1U_0402_6.3V6K
189 190 DDR_B_DM3
DDR_B_D58 VSS49 VSS50 DDR_B_D62 DDR_B_DM4
191 DQ58 DQ62 192 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
DQ59 DQ63 DDR_B_DM6
195 VSS51 VSS52 196
1 R95 2 197 SA0 EVENT# 198 DDR_B_DM7
10K_0402_5% SMB_DATA_S3 2 2 2 2
199 VDDSPD SDA 200 SMB_DATA_S3 <12,15,34>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,34>
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

R97 10K_0402_5% 203 204 +0.75VS @ @

VTT1 VTT2 1/76BA1/86W
C177

C178

A A
1 1 Layout Note:
205 G1 G2 206
Place near DIMM
FOX_AS0A626-U8SN-7F
2 2 ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 13 of 59
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

PCH_RTCX1 1 @ 2 R663 0_0402_5% PCH_RTCX1_OUT <40>

W=20mils W=20mils 1 2 PCH_RTCX2 1 @ 2 R670 0_0402_5% PCH_RTCX2_OUT <40>
R98 10M_0402_5%
+RTCVCC +RTCBATT

R99 6/24 Update R663,R670 must be close Y1

1K_0402_5%

32.768KHZ_12.5PF_9H03200413
1 2

4
1
1 Y1

OSC

OSC
C179 CLRP1 1 1
1U_0603_10V4Z SHORT PADS

2
C180 C181
2

NC

NC
15P_0402_50V8J
D 2 2 15P_0402_50V8J D

3
CMOS

U4A

SHORT PADS
CLRP2
+RTCVCC
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <34,40>

1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1

LPC
PCH_RTCX2 FWH1 / LAD1 LPC_AD2 LPC_AD1 <34,40>
C183 C20 B37 EC and Mini card debug port
PCH_INTVRMEN RTCX2 FWH2 / LAD2 LPC_AD3 LPC_AD2 <34,40>
R102 1 2 330K_0402_5% 1U_0603_10V4Z C37

2
2 PCH_RTCRST# FWH3 / LAD3 LPC_AD3 <34,40>
1 2 D20
RTCRST#
R103 20K_0402_5% LPC_FRAME#
INTVRMEN FWH4 / LFRAME# D36 LPC_FRAME# <34,40>
ΚIntegrated 1 2 PCH_SRTCRST# G22 SRTCRST#
* HLΚ Integrated VRM enable R100 20K_0402_5% E36 +3VS
1

RTC
LDRQ0#

1
SHORT PADS
CLRP3
VRM disable SM_INTRUDER# K22 K36 R104 2 1 10K_0402_5%
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <40>

2
2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <38>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 <38>
HDA_BCLK SATA0RXP

SATA 6G
AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0 HDD
SATA0TXN SATA_ITX_DRX_N0 <38>
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <38>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10
<39> HDA_SPKR SPKR SATA1RXN
LOW= Disable (Default) AM8
* HDA_RST# K34 HDA_RST#
SATA1RXP
SATA1TXN AP11
SATA1TXP AP10
C +3VALW HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<39> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <56,57>
AD5 SATA_DTX_C_IRX_P2 ODD
SATA2RXP SATA_DTX_C_IRX_P2 <56,57>
R106 2 @ 1 1K_0402_5% HDA_SDOUT G34 AH5 SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 1 C186 SATA_ITX_DRX_N2_CONN
HDA_SDIN1 SATA2TXN SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2 SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_N2_CONN <56,57>
SATA2TXP AH4 1 C187 SATA_ITX_DRX_P2_CONN <56,57>
Low = Disabled (Default) C34
*

IHDA
HDA_SDIN2
High = Enabled [Flash Descriptor Security Overide] SATA3RXN AB8
A34 AB10
HDA_SDIN3 SATA3RXP
AF3
R109 SATA3TXN
AF1
ME_FLASH HDA_SDOUT SATA3TXP
1 2 A36

SATA
+3VALW <40> ME_FLASH HDA_SDO SATA_DTX_C_IRX_N4
0_0402_5% Y7 SATA_DTX_C_IRX_N4 <42>
SATA4RXN ESATA@ SATA_DTX_C_IRX_P4
SATA4RXP
Y5 SATA_DTX_C_IRX_P4 <42> ESATA
R108 2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 AD3 SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C188 SATA_ITX_DRX_N4
HDA_DOCK_EN# / GPIO33 SATA4TXN SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 SATA_ITX_DRX_P4 SATA_ITX_DRX_N4 <42>
AD1 1 C189 SATA_ITX_DRX_P4 <42>
Kill_SW# SATA4TXP ESATA@
This signal has a weak internal pull-down <56,57> Kill_SW# N32 HDA_DOCK_RST# / GPIO13
Y3
R110 SATA5RXN
Y1
On Die PLL VR Select is supplied by 51_0402_5% SATA5RXP
AB3 7/28 change from port 5 to port 4
1.5V when smapled high PCH_JTAG_TCK SATA5TXN
2 1 J3 AB1
* 1.8V when sampled low
JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11 R111
Needs to be pulled High for Huron River platfrom

JTAG
JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
R112 PCH_JTAG_TDO H1
33_0402_5% +3VS JTAG_TDO R113 +1.05VS_SATA3
SATA3RCOMPO AB12
1 2 HDA_BIT_CLK 49.9_0402_1%
<39> HDA_BITCLK_AUDIO
2
G

R114 Q10 AB13 SATA3_COMP 1 2

33_0402_5% BSS138_NL_SOT23-3 SATA3COMPI
1 2 HDA_SYNC_R 3 1 HDA_SYNC
<39> HDA_SYNC_AUDIO
R116 SPI_CLK_PCH_R RBIAS_SATA3 R115 1 2 750_0402_1%
S

T3 SPI_CLK SATA3RBIAS AH1

33_0402_5%
2

B HDA_RST# SPI_SB_CS0# B
<39> HDA_RST_AUDIO# 1 2 Y14
R118 R878 SPI_CS0# R117
1 2 2 1 10K_0402_5% +3VS
33_0402_5% 1M_0402_5% T1
SPI

HDA_SDOUT @ R325 SPI_CS1# HDD_LED#

<39> HDA_SDOUT_AUDIO 1 2 P3 HDD_LED# <56,57>
0_0402_5% SATALED#
1

SPI_SI V4 V14 PCH_GPIO21 2 R119 1 10K_0402_5%

SPI_MOSI SATA0GP / GPIO21 +3VS

+3VALW +3VALW +3VALW

SPI_SO_R U3 SPI_MISO SATA1GP / GPIO19 P1 PCH_GPIO19 2 R187 1 10K_0402_5% +3VS 4MB SPI ROM FOR ME SPI_CLK_PCH

9/27 reserve R878 for DG1.5 COUGARPOINT_FCBGA989

@ & Non-share ROM.
1

1
8/16 reserved for MOW
R121 R122 R123 R124
@ 200_0402_5% 200_0402_5% 200_0402_5% 33_0402_5%
+3VS @
2

2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI
1

R127 1 2 SPI_WP# C190

R125 R126 R128 3.3K_0402_5% 22P_0402_50V8J
@ 100_0402_1% 100_0402_1% 100_0402_1% @
R129 1 2 SPI_HOLD# +3VS
3.3K_0402_5%
2

C191
DPDG1.1 1 2
R130
6/30 update R121, R122, R123 0_0402_5% U5 0.1U_0402_16V4Z
SPI_SB_CS0# 1 2 1 8
SPI_SO_R SPI_SO_L CS# VCC SPI_HOLD# 0_0402_5% R132
1 2 2
SO HOLD#
7
SPI_WP# 3 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
33_0402_5% WP# SCLK SPI_SI_R
4 5 1 2 SPI_SI
R131 GND SI
A S IC FL 32M W25Q32BVSSIG SOIC 8P 33_0402_5% A
R133

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC, XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 14 of 59
5 4 3 2 1
 5 4 3 2 1

10K_0402_5%
U4B Q60A
2 1 +3VALW 2N7002DW-T/R7_SOT363-6
<35> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 R134 6 1 SMB_CLK_S3
PCIE_PRX_DTX_P1 PERN1 EC_LID_OUT# SMB_CLK_S3 <12,13,34>
LAN <35> PCIE_PRX_DTX_P1 BJ34 PERP1 SMBALERT# / GPIO11 E12 EC_LID_OUT# <40>
C192 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 2.2K_0402_5% 2.2K_0402_5%
<35> PCIE_PTX_C_DRX_N1
C193 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32
PETN1
H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1

2
<35> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK

<34> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA
+3VALW
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 BF34 R135 R138
WLAN
<34> PCIE_PRX_DTX_P2
<34> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3

SMBUS
<34> PCIE_PTX_C_DRX_P2 PETP2 DRAMRST_CNTRL_PCH SMB_DATA_S3 <12,13,34>
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH <7>
BG36 2N7002DW-T/R7_SOT363-6 8/14 change P/N to
PERN3 PCH_SML0CLK
BJ36 C8 Q60B
D
AV34
PERP3 SML0CLK
2 R139 1
2N7002KDW(SB00000EO10) D
PETN3 +3VALW
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 7/28 reserved 7/5 change to 1K 2N7002DW-T/R7_SOT363-6
PERN4 10K_0402_5% EC_SMB_CK2
BE36 6 1 EC_SMB_CK2 <24,37,40>
PERP4 PCH_GPIO74
AY34 C13 2 1 +3VALW
PETN4 SML1ALERT# / PCHHOT# / GPIO74 2.2K_0402_5%
BB34
PETP4
E14 PCH_SML1CLK R140 1 R141 2 VGA

PCI-E*

2
SML1CLK / GPIO58
BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75
M16 PCH_SML1DATA
+3VALW
1 2
+3VS EC

5
AY36 R142
BB36
PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 <24,37,40>
BJ38 PERN6
BG38 2N7002DW-T/R7_SOT363-6

Controller
PERP6
AU36 PETN6 CL_CLK1
M7 Q61B
AV36 +3VALW
PETP6 +3VALW

Link
BG40 PERN7 CL_DATA1
T11

2
BJ40 PERP7
AY40 R143
PETN7

2
BB40 PETP7 CL_RST1#
P10 10K_0402_5%
@ R544 R545
BE38 R144 2.2K_0402_5% 2.2K_0402_5%

1
PERN8 0_0402_5%
BC38 PERP8
AW38 @ 1 2

1
PETN8 PEG_CLKREQ# <24> PCH_SML0CLK
AY38 PETP8 10K_0402_5% R145
PEG_A_CLKRQ# / GPIO47 M10 PEG_CLKREQ#_R 1 2 PCH_SML0DATA
Y40
Desktop Only Y39
CLKOUT_PCIE0N
CLKOUT_PCIE0P CLK_PCIE_VGA#_R R146 1 CLK_PCIE_VGA#
CLKOUT_PEG_A_N
AB37 2 0_0402_5% CLK_PCIE_VGA# <23> 7/28 reserved

CLOCKS
C R147 PCH_GPIO73 CLK_PCIE_VGA_R CLK_PCIE_VGA C
+3VALW 2 1 10K_0402_5% J2 AB38 R148 1 2 0_0402_5% CLK_PCIE_VGA <23>
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
@
<34> CLK_PCIE_WLAN1#
R149 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 CLK_CPU_DMI#
CLK_CPU_DMI# <6>
CLK_CPU_DMI# R349 1 2 10K_0402_5%
<34> CLK_PCIE_WLAN1
R150 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
CLK_CPU_DMI <6>
CLK_CPU_DMI R347 1 2 10K_0402_5%
CLKOUT_PCIE1P CLKOUT_DMI_P
WLAN
<34> WLAN_CLKREQ1# R156 1 2 0_0402_5% WLAN_CLKREQ1#_R M1 @
R158 PCIECLKRQ1# / GPIO18
+3VS 2 1 10K_0402_5% AM12
CLKOUT_DP_N / CLKOUT_BCLK1_N
AA48
CLKOUT_DP_P / CLKOUT_BCLK1_P AM13 6/30 Update to @
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P CLK_BUF_CPU_DMI# R155 1 10K_0402_5%
BF18 2
R301 CLKIN_DMI_N CLK_BUF_CPU_DMI
+3VS 2 1 10K_0402_5% V10 BE18 R157 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

<35> CLK_PCIE_LAN# CLK_PCIE_LAN_R CLKOUT_PCIE3N CLKIN_DMI2_N CLKIN_DMI2
LAN R154 1 2 0_0402_5% Y36 BG30 R160 1 2 10K_0402_5%
<35> CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_DMI2_P
R151 1 2 0_0402_5% PCH_GPIO25 A8
<35> CLKREQ_LAN# PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M#
+3VALW R152 2 1 10K_0402_5% G24 R162 1 2 10K_0402_5%
CLKIN_DOT_96N CLK_BUF_DREF_96M R163 1 10K_0402_5%
E24 2
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R164 1 10K_0402_5%
CLKIN_SATA_N / CKSSCD_N AK7 2
R165 2 1 10K_0402_5% PCH_GPIO26 L12 AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
+3VALW PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
R168 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
+3VALW PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B XTAL25_IN B
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 1 2
R169 1M_0402_5%
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
+3VALW PEG_B_CLKRQ# / GPIO56 90.9_0402_1% Y2
Y47 XCLK_RCOMP 1 2 2 1
XCLK_RCOMP
V40 CLKOUT_PCIE6N 1 1
@ 1 R520 2 100K_0402_5% V42 25MHZ_20PF_7A25000012
CLKOUT_PCIE6P C196 C197
2 R172 1 10K_0402_5% PCH_GPIO45 T13 27P_0402_50V8J 27P_0402_50V8J
+3VALW PCIECLKRQ6# / GPIO45 2 2
PE_GPIO0 1 @ 2 V38 K43
<18> PE_GPIO0 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
R700 0_0402_5% R173
FLEX CLOCKS

V37
CLKOUT_PCIE7P CLK_PCI_DB_R
F47 1 2 22_0402_5% CLK_PCI_DB <34>
CLKOUTFLEX1 / GPIO65
+3VALW R174 2 1 10K_0402_5% PCH_GPIO46 K12 @
PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47
PE_GPIO1 1 2 PCIE_CLK_8N AK14
<18,25,26,52> PE_GPIO1 PCIE_CLK_8P CLKOUT_BCLK0_N / CLKOUT_PCIE8N
R701 0_0402_5% AK13 K49
@ CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 @ R175 @ C198
33_0402_5% 22P_0402_50V8J
COUGARPOINT_FCBGA989 CLK_BUF_ICH_14M 2 1 1 2

6/23 for GPU Reserve for EMI please close to PCH

@ R176 @ C199
33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2
A A

Reserve for EMI please close to PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 15 of 59
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
3

<5> DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2

DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
VGATE 1 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
G

A <5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>

4 SYS_PWROK BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4
Y SYS_PWROK <6> FDI_RXN4 <5>
PCH_POK 2 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
B <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
P

DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6

<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
U6 <5> DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI_CTX_PRX_P2 FDI_CTX_PRX_N7 <5>
5

DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7

<5> DMI_CTX_PRX_P3 BJ20 DMI3RXP
7/28 Defult use AND Gate BG14 FDI_CTX_PRX_P0
* <5> DMI_CRX_PTX_N0
DMI_CRX_PTX_N0 AW24 DMI0TXN
FDI_RXP0
FDI_RXP1 BB14 FDI_CTX_PRX_P1
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
<5>
<5>
+3VS DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5>
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
R180 2 1 100K_0402_1% SYS_PWROK DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4

DMI
FDI
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5>
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 DMI1TXP FDI_RXP7
<5> DMI_CRX_PTX_P2 AY18 DMI2TXP
DMI_CRX_PTX_P3 AU18
<5> DMI_CRX_PTX_P3 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT <5> +RTCVCC
R743
PCH_POK_R 1 2 @ SYS_PWROK +1.05VS_PCH BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
0_0402_5%

1
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R742 R177 49.9_0402_1% R179
1 2 @ 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 330K_0402_5%
C <40> SYS_PWROK_EC DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
0_0402_5% R178 750_0402_1%
4mil width and place BB10 FDI_LSYNC1

2
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
7/22 modify SUSACK# is only used on platform A18 DSWODVREN
DSWVRMEN

1
that support the Deep Sx state. 0_0402_5% 1 R181 2 @ PCH_RSMRST#_R

System Power Management

R183
T72 PAD SUSACK# C12 E22 PCH_DPWROK_R 0_0402_5% 1 R182 2 330K_0402_5%
SUSACK# DPWROK PCH_DPWROK <40>
R185 @
0_0402_5% 7/28 Update

2
+3VS 2 1 SYS_RST# K3 B9 WAKE# 1 2 PCIE_WAKE# <34,35>
R184 10K_0402_5% SYS_RESET# WAKE#
1 2 10K_0402_5% +3VALW
R186
SYS_PWROK P12 N3 PM_CLKRUN# PAD T73

Κ
R188 1 @ SYS_PWROK CLKRUN# / GPIO32 DSWODVREN - On Die DSW VR Enable
2 0_0402_5% 1 R189 2
<53> VGATE +3VS *
Κ
8.2K_0402_5% H Enable
AEPWROK can be connect to R190 1 2 0_0402_5% PCH_POK_R L22 G8 SUS_STAT# L Disable
<6,40> PCH_POK PWROK SUS_STAT# / GPIO61
PWROK if iAMT disable
R191 R302 1 2 0_0402_5% APWROK L10 N14 SUSCLK
<40> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK <40>
PCH_POK_R 1 2 APWROK

0_0402_5% @ PM_DRAM_PWRGD B13 SLP_S5#

7/22 modify <6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 D10 SLP_S5# <40>

1 2 PCH_RSMRST#_R C21 H4 SLP_S4#

+3VALW <40> EC_RSMRST# RSMRST# SLP_S4# SLP_S4# <40>
R193 0_0402_5%

1 2 SUSWARN#_R K16 F4 SLP_S3#

<40> SUSWARN# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# SLP_S3# <40>
@ R196 0_0402_5%
R192 2 1 200_0402_5% PM_DRAM_PWRGD Can be left NC
B PBTN_OUT#_R B
<40> PBTN_OUT# 1 2 E20 G10 when IAMT is not
R194 SUSWARN# PWRBTN# SLP_A#
2 1 10K_0402_5% R198 0_0402_5% support on the
R195
ACIN_R ACIN_R PM_SLP_SUS# platfrom
2 1 <24,40,47> ACIN 1 2 D29 H20 G16 PAD T71
200K_0402_1% CH751H-40PT_SOD323-2 ACPRESENT / GPIO31 SLP_SUS#
1 2
R197 2 1 10K_0402_5% PCH_RSMRST#_R R199 @ 0_0402_5%
1 R200 2 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
8.2K_0402_5%
R201 Can be left NC if no use
+3VALW 2 1 RI# A10 K14 @ T66 PAD integrated LAN.
10K_0402_5% RI# SLP_LAN# / GPIO29

7/28 modify COUGARPOINT_FCBGA989

+3VS

R546 2 1 200_0402_5% PM_DRAM_PWRGD

7/28 Modify follow CRB & ORB

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 16 of 59
5 4 3 2 1
 5 4 3 2 1

D D
+3VS

1
R234 R523
2.2K_0402_5% 2.2K_0402_5%
PX@ PX@ U4D
PCH_ENBKL J47 AP43

2
<31> PCH_ENBKL L_BKLTEN SDVO_TVCLKINN +3VS
PCH_ENVDD M45 AP45
EDID_CLK <31> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
EDID_DATA P45 AM42
<31> PCH_PWM L_BKLTCTL SDVO_STALLN
AM40
SDVO_STALLP

1
EDID_CLK T40
<31> EDID_CLK EDID_DATA L_DDC_CLK
Pull up R for Chipset SIDE K47 AP39 R202 R203
<31> EDID_DATA L_DDC_DATA SDVO_INTN
AP40 2.2K_0402_5% 2.2K_0402_5%
R204 1 CTRL_CLK SDVO_INTP
+3VS 2 2.2K_0402_5% T45 UMA_HDMI@ UMA_HDMI@
R205 1 CTRL_DATA L_CTRL_CLK
2 2.2K_0402_5% P39

2
2.37K_0402_1% L_CTRL_DATA
R206 2 1 LVDS_IBG AF37 P38 HDMICLK_NB HDMICLK_NB <33>
PX@ LVD_IBG SDVO_CTRLCLK HDMIDAT_NB
AF36 M39 HDMIDAT_NB <33>
LVD_VBG SDVO_CTRLDATA
0_0402_5% LVD_VREF AE48
R207 LVD_VREFH
2 1 AE47 AT49
PX@ LVD_VREFL DDPB_AUXN
DDPB_AUXP AT47
DDPB_HPD AT40 TMDS_B_HPD# <33>
AK39

LVDS
<31> LVDS_ACLK# LVDSA_CLK#
<31> LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCH UMA_HDMI@ C200 1 2 0.1U_0402_10V6K
HDMI_TX2-_CK <33>
AV40 TMDS_B_DATA2_PCH UMA_HDMI@ C201 1 2 0.1U_0402_10V6K
HDMI_TX2+_CK <33>
DDPB_0P
<31> LVDS_A0# AN48 LVDSA_DATA#0 DDPB_1N AV45 TMDS_B_DATA1#_PCH UMA_HDMI@ C202 1 2 0.1U_0402_10V6K
HDMI_TX1-_CK <33>
AM47 AV46 TMDS_B_DATA1_PCH UMA_HDMI@ C203 1 2 0.1U_0402_10V6K

Digital Display Interface

C <31> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <33> C
<31> LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCH UMA_HDMI@ C204 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK <33> HDMI
AJ48 AU47 TMDS_B_DATA0_PCH UMA_HDMI@ C205 1 2 0.1U_0402_10V6K
HDMI_TX0+_CK <33>
LVDSA_DATA#3 DDPB_2P
AV47 TMDS_B_CLK#_PCH UMA_HDMI@ C206 1 2 0.1U_0402_10V6K
HDMI_CLK-_CK <33>
DDPB_3N
<31> LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH UMA_HDMI@ C207 1 2 0.1U_0402_10V6K
HDMI_CLK+_CK <33>
<31> LVDS_A1 AM49
LVDSA_DATA1
<31> LVDS_A2 AK49 LVDSA_DATA2 UMA_HDMI@
AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA P42

AF40 LVDSB_CLK#
AF39 AP47
LVDSB_CLK DDPC_AUXN
AP49
DDPC_AUXP
AH45 LVDSB_DATA#0 DDPC_HPD
AT38
AH47
LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 AY49
LVDSB_DATA#3 DDPC_0P
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 BA47
LVDSB_DATA1 DDPC_2N
AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 BB47
DAC_BLU LVDSB_DATA3 DDPC_3N
<32> DAC_BLU DDPC_3P BB49
R208 2 1 150_0402_1%
PX@ DAC_GRN
<32> DAC_GRN
R209 2 1 150_0402_1% N48 M43
PX@ DAC_RED CRT_BLUE DDPD_CTRLCLK
<32> DAC_RED P49 CRT_GREEN DDPD_CTRLDATA M36
R210 2 1 150_0402_1% T49
PX@ CRT_RED
AT45

CRT
+3VS CRT_DDC_CLK DDPD_AUXN
<32> CRT_DDC_CLK T39 AT43
CRT_DDC_DATA CRT_DDC_CLK DDPD_AUXP
Pull up R for Chipset SIDE <32> CRT_DDC_DATA M40 CRT_DDC_DATA DDPD_HPD
BH41
B B
DDPD_0N BB43
1

<32> CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45

R524 R559 M49 BF44
<32> CRT_VSYNC CRT_VSYNC DDPD_1N
2.2K_0402_5% 2.2K_0402_5% BE44
PX@ PX@ DDPD_1P
BF42
CRT_IREF DDPD_2N
T43 BE42
2

DAC_IREF DDPD_2P
T42 BJ42
CRT_DDC_CLK CRT_IRTN DDPD_3N
DDPD_3P BG42
1

CRT_DDC_DATA
COUGARPOINT_FCBGA989
R211
1K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 17 of 59
5 4 3 2 1
 5 4 3 2 1

+3VS

R551 1 @ 2 8.2K_0402_5% PCH_GPIO53

U4E
RP2 8/17 reserved AY7
PCI_PIRQA# NV_CE#0
8 1 NV_CE#1
AV7
7 2 PCI_PIRQD# BG26 AU3
PCI_PIRQC# TP1 NV_CE#2
6 3 BJ26 TP2 NV_CE#3 BG4
5 4 PCI_PIRQB# BH25 TP3
BJ16 TP4 NV_DQS0 AT10
8.2K_0804_8P4R_5% BG16 BC8
TP5 NV_DQS1
AH38
RP1 TP6
AH37 AU2
PCH_GPIO2 TP7 NV_DQ0 / NV_IO0
8 1 AK43
TP8 NV_DQ1 / NV_IO1
AT4
D PCH_GPIO54 D
7 2 AK45 AT3
PCH_GPIO4 TP9 NV_DQ2 / NV_IO2
6 3 C18
TP10 NV_DQ3 / NV_IO3
AT1
5 4 PCH_GPIO3 N30 AY3
TP11 NV_DQ4 / NV_IO4
H3 AT5
8.2K_0804_8P4R_5% TP12 NV_DQ5 / NV_IO5
AH12 AV3

NVRAM
TP13 NV_DQ6 / NV_IO6
AM4 AV1
R225 WL_OFF# TP14 NV_DQ7 / NV_IO7
1 2 8.2K_0402_5% AM5 BB1
TP15 NV_DQ8 / NV_IO8
Y13 BA3
TP16 NV_DQ9 / NV_IO9
K24 BB5
R212 PCH_GPIO52 TP17 NV_DQ10 / NV_IO10
1 2 8.2K_0402_5% L24
TP18 NV_DQ11 / NV_IO11
BB3
AB46 BB7
R213 PCH_GPIO5 TP19 NV_DQ12 / NV_IO12
1 2 8.2K_0402_5% AB45 BE8

RSVD
TP20 NV_DQ13 / NV_IO13
BD4
NV_DQ14 / NV_IO14
BF6
R214 PCH_GPIO50 NV_DQ15 / NV_IO15
1 2 8.2K_0402_5%
B21 TP21 NV_ALE
AV5
@ M20 AY1 NV_CLE
TP22 NV_CLE
AY16 TP23
BG46 TP24 NV_RCOMP
AV10

GPIO55 NV_RB# AT8

PCH_GPIO51 R221 1 @ 2 1K_0402_5% DMI Termination Voltage
WL_OFF# R215 1 @ 2 1K_0402_5% BE28 AY5
TP25 NV_RE#_WRB0
BC30 TP26 NV_RE#_WRB1 BA2 Set to Vcc when HIGH
BE32 TP27
NV_CLE
BJ32 TP28 NV_WE#_CK0
AT12 Set to Vss when LOW
Boot BIOS Strap bit1 BBS1 A16 swap overide Strap/Top-Block BC28 TP29 NV_WE#_CK1
BF3
Swap Override jumper BE30 TP30 USB DEBUG=PORT1 AND PORT9
Boot BIOS BF32 +1.8VS
TP31 USB20_N0
Destination Low=A16 swap BG32 TP32 USBP0N C24 USB20_N0 <56,57>
Bit11 Bit10 override/Top-Block AV26 A24 USB20_P0 RIGHT USB
TP33 USBP0P USB20_P0 <56,57>

1
PCI_GNT3# Swap Override enabled BB26 C25 USB20_N1 6/24 change to 1K
C TP34 USBP1N USB20_P1 USB20_N1 <38> C
0 1 Reserved High=Default * AU28 TP35 USBP1P B25 USB20_P1 <38> LEFT USB USB charger R216
GNT1#/ AY30 C26 USB20_N2 1K_0402_5%
TP36 USBP2N USB20_P2 USB20_N2 <42>
GPIO51 1 0 Reserved AU26 TP37 USBP2P A26 USB20_P2 <42> LEFT USB
AY26 K28 USB20_N3

2
TP38 USBP3N USB20_P3 USB20_N3 <42> NV_CLE
1 1 * SPI (Default) AV28 TP39 USBP3P H28 USB20_P3 <42> LEFT USB (COMBO) 2 1 H_SNB_IVB# <6>
AW30 E28 R217 4.7K_0402_5%
TP40 USBP4N
0 0 LPC USBP4P D28
C28 USB20_N5 CLOSE TO THE BRANCHING POINT
USBP5N USB20_N5 <31>
A28 USB20_P5 USB Camera
USBP5P USB20_P5 <31>
C29
USBP6N
B29
PCI_PIRQA# USBP6P
K40 N28
PCI_PIRQB# PIRQA# USBP7N
10/5 change to PX@ K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P USB20_N8
H38 L30
PCI_PIRQD# PIRQC# USBP8N USB20_P8
PX@
G38 PIRQD# USBP8P
K30
USB20_N9
8/6 WLAN change
G30 USB20_N9 <34>
USBP9N
PE_GPIO0 1 2 PCH_GPIO50 C46 E30 USB20_P9 WLAN to port 9 +3VALW

USB
<15> PE_GPIO0 PCH_GPIO52 REQ1# / GPIO50 USBP9P USB20_N10
USB20_P9 <34>
R553 0_0402_5% C44 C30
PE_GPIO1 PCH_GPIO54 REQ2# / GPIO52 USBP10N USB20_P10 RP3
<15,25,26,52> PE_GPIO1 1 2 E40 A30
R691 0_0402_5% REQ3# / GPIO54 USBP10P USB20_N11 USB_OC0#
PX@ PCH_GPIO51 USBP11N
L32
USB20_P11 USB20_N11 <43> CARD READER USB_OC2#
4 5
D47 K32 USB20_P11 <43> 3 6
PCH_GPIO53 GNT1# / GPIO51 USBP11P USB_OC7#
E42 GNT2# / GPIO53 USBP12N G32 2 7
WL_OFF# F46 E32 USB_OC5# 1 8
<34> WL_OFF# GNT3# / GPIO55 USBP12P
C32 USB20_N13
USBP13N USB20_P13 USB20_N13 <42>
GPIO53=This Signal has a weak internal pull-up. A32 Bluetooth 10K_1206_8P4R_5%
PCH_GPIO2 USBP13P USB20_P13 <42>
G42 PIRQE# / GPIO2
NOTE: The internal pull-up is disabled after <40,56,57> ODD_DA#
ODD_DA# 1 @ 2 PCH_GPIO3 G40 Within 500 mils
0_0402_5% R715 PCH_GPIO4 PIRQF# / GPIO3 USBRBIAS
PLTRST# deasserts. C42 C33 1 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R218 22.6_0402_1% RP4
D44 PIRQH# / GPIO5 USB_OC1# 4 5
B33 USB_OC4# 3 6
USBRBIAS USB_OC3#
<40> PCI_PME# K10 2 7
B PME# USB_OC6# B
1 8
PLT_RST# C6 A14 USB_OC0#
<6> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <38,56,57>
K20 10K_1206_8P4R_5%
OC1# / GPIO40 USB_OC2# USB_OC1# <42>
R219 22_0402_5% B17
CLK_PCI_LPBACK_R H49 OC2# / GPIO41 USB_OC3#
<15> CLK_PCI_LPBACK 1 2 C16
CLK_PCI_LPC_R CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#
<40> CLK_PCI_LPC 1 2 H43 CLKOUT_PCI1 OC4# / GPIO43 L16
R220 22_0402_5% J48 A16 USB_OC5#
CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
K42 CLKOUT_PCI3 OC6# / GPIO10 D14
H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14

COUGARPOINT_FCBGA989

7/12 For DIS only

1 2
R690 2 DIS@ 1 R222 0_0402_5%
0_0402_5%
1 R487 2 +3VGS
10K_0402_5% +3VGS
@
@ MC74VHC1G08DFT2G SC70 5P
D27

3
R693 @ @
5

PE_GPIO0 1 2 2 1 VGA_RST# U12 1 PLT_RST#

G
PLT_RST# PX@ R682 A
2 4
P

B <34,35,40> BUF_PLT_RST# Y
CH751H-40PT_SOD323-2 0_0402_5% 4 VGA_RST#_R 2 1 2
Y VGA_RST# <23> B

P
PE_GPIO0 1 0_0402_5%
A
G

1
7/12 Reserve for BACO suggestion 1 U7

5
NC7SZ08P5X_NL_SC70-5 PX@ PX@ R684 1U_0402_6.3V4Z
3

100K_0402_5% C208 R223

@ 100K_0402_5%
A 2 +3VS A
2

2
R741 @
PE_GPIO0 2 1 VGA_RST#
10/5 change to PX@
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
7/12 Reserve for PX3.0 Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 18 of 59
5 4 3 2 1
 5 4 3 2 1

+3VS
PCH_GPIO69 PCH_GPIO70 PCH_GPIO71 Function

R702 R703 R704

0 0 0 UMA

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
1 0 0 DIS

1
PCH_GPIO69
0 1 0 PX3.0 PX@ @
PCH_GPIO70
D D
1 1 0 PX4.0 * PCH_GPIO71 R707 R705 R706

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
R233 1 2 10K_0402_5% PCH_GPIO0
+3VS
@ U4F
ICC_EN# ESATA_DET# 1 2
Integrated Clock Chip Enable 0_0402_5% R303 T7 C40 PCH_GPIO68

1
BMBUSY# / GPIO0 TACH4 / GPIO68
H ; Disable 7/22 update to reserve only R227 1 2 10K_0402_5% A42 B41 PCH_GPIO69 @ DIS@
L ; Enable TACH1 / GPIO1 TACH5 / GPIO69
* +3VS R228 1 2 10K_0402_5% PCH_GPIO6 H36 TACH2 / GPIO6 TACH6 / GPIO70 C41 PCH_GPIO70 +3VS
@ 6/23 update for MB ID
R235 1 2 1K_0402_5% EC_SMI# <40> EC_SCI# EC_SCI# E38 A40 PCH_GPIO71
TACH3 / GPIO7 TACH7 / GPIO71

2
EC_SMI# C10 R236
<40> EC_SMI# GPIO8
Weak internal pull-high 10K_0402_5%
R229 1 @ 2 10K_0402_5% CPUSB# C4
+3VALW LAN_PHY_PWR_CTRL / GPIO12

1
R230 1 2 1K_0402_5% PCH_GPIO15 G2 P4
GPIO15 A20GATE GATEA20 <40> +3VS
GPIO28 AU16 PCH_PECI_R 1 @ 2

CPU/MISC
PCH_GPIO16 PECI H_PECI <6,40> PCH_GPIO68 R224
On-Die PLL Voltage Regulator +3VS R231 1 2 10K_0402_5% U2
SATA4GP / GPIO16
0_0402_5% R237 1 2 10K_0402_5%
This signal has a weak internal pull up P5 KB_RST#

Κ
RCIN# KB_RST# <40>
R542 1 @ 2 0_0402_5% KB_RST# R226 1 2 10K_0402_5%

ΚOn-Die

GPIO
<42> ESATA_DET#
H voltage regulator enable R232 1 2 10K_0402_1% GPIO17 D40 AY11
* L On-Die PLL Voltage Regulator disable
+3VS TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>
R238 1 2 10K_0402_5% PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R240 1 @ 2 1K_0402_5% PCH_GPIO28 R239 390_0402_5%
7/22 update to used ODD_EN E8 T14
+3VALW <38> ODD_EN GPIO24 / MEM_LED INIT3_3V#
intel function INIT3_3V
PCH_GPIO27 E16
C GPIO27 C
R241 This signal has weak internal
1 2 10K_0402_5% PCH_GPIO28 P8 PU, can't pull low
GPIO28
<42> BT_OFF# NC_1 AH8
+3VS 1 @ 2 10K_0402_5% BT_OFF# K1
R242 STP_PCI# / GPIO34
NC_2 AK11
PCH_GPIO27 (Have internal Pull-High) R243 1 2 10K_0402_5% PCH_GPIO35 K4 GPIO35
AH10
*High: VCCVRM VR Enable
Low: VCCVRM VR Disable
PCH_GPIO36 V8 SATA2GP / GPIO36
NC_3

NC_4
AK10 Intel schematic reviwe recommand.
R244 1 @ 2 10K_0402_5% PCH_GPIO37 M5
+3VS SATA3GP / GPIO37
P37
R245 @ PCH_GPIO27 PCH_GPIO38 NC_5
1 2 10K_0402_5% R246 1 2 10K_0402_5% N2
SLOAD / GPIO38
R247 1 2 10K_0402_5% PCH_GPIO39 M3
SDATAOUT0 / GPIO39
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2 @ T15 PAD
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% ESATA_DET#_R V3 BG48 @ T16 PAD
+3VS SATA5GP / GPIO49 VSS_NCTF_16
PCH_GPIO57 D6 BH3 @ T17 PAD
R250 @ PCH_GPIO36 GPIO57 VSS_NCTF_17
+3VS 1 2 10K_0402_5%
BH47 @ T18 PAD
R251 VSS_NCTF_18
+3VALW 1 2 10K_0402_5%
R547 1 2 10K_0402_5% PAD T19 @ A4 BJ4 @ T20 PAD
VSS_NCTF_1 VSS_NCTF_19
PAD T21 @ A44 BJ44 @ T22 PAD
VSS_NCTF_2 VSS_NCTF_20
8/5 update to pull down PAD T23 @ A45
VSS_NCTF_3 VSS_NCTF_21
BJ45 @ T24 PAD

NCTF
PAD T25 @ A46 BJ46 @ T26 PAD
VSS_NCTF_4 VSS_NCTF_22
PAD T27 @ A5 BJ5 @ T28 PAD
B VSS_NCTF_5 VSS_NCTF_23 B
PAD T29 @ A6 BJ6 @ T30 PAD
R881 PCH_GPIO37 VSS_NCTF_6 VSS_NCTF_24
1 2 10K_0402_5%
PAD T31 @ B3 C2 @ T32 PAD
VSS_NCTF_7 VSS_NCTF_25
PAD T33 @ B47 C48 @ T34 PAD
VSS_NCTF_8 VSS_NCTF_26
PAD T35 @ BD1 D1 @ T36 PAD
VSS_NCTF_9 VSS_NCTF_27
10/8 update to pull down for checklist Rev1.2
PAD T37 @ BD49 D49 @ T38 PAD
VSS_NCTF_10 VSS_NCTF_28
PAD T39 @ BE1 E1 @ T40 PAD
VSS_NCTF_11 VSS_NCTF_29
PAD T41 @ BE49 E49 @ T42 PAD
VSS_NCTF_12 VSS_NCTF_30
PAD T43 @ BF1 F1 @ T44 PAD
VSS_NCTF_13 VSS_NCTF_31
PAD T45 @ BF49 F49 @ T46 PAD
VSS_NCTF_14 VSS_NCTF_32

COUGARPOINT_FCBGA989

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 19 of 59
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

+1.05VS U4G POWER +3VS S0 Iccmax
L1 Voltage Rail Voltage Current (A)
@ PJP1 1300mA MBK1608221YZF_2P
2 1 +1.05VS_PCH AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212

0.01U_0402_16V7K
C213

0.1U_0402_10V7K
C214
CRT
AD21 C215
PAD-OPEN 4x4m 1 1 1 1 VCCCORE[3] 1

10U_0603_6.3V6M
C209
AD23 U47 10U_0805_6.3V6M C395
VCCCORE[4] VSSADAC

VCC CORE
AF21 10U_0805_6.3V6M V5REF 5 0.001
VCCCORE[5] 2 2 2
AF23
D 2 2 2 2 VCCCORE[6] R252 +3VS 2 @ D
AG21 VCCCORE[7]
AG23 0.022_0805_1% V5REF_Sus 5 0.001
VCCCORE[8] +VCCA_LVDS
AG24 VCCCORE[9] 1mA VCCALVDS AK36 1 2
AG26 PX@
VCCCORE[10]

1
AG27
VCCCORE[11] VSSALVDS
AK37 8/5 Reserved Vcc3_3 3.3 0.266
AG29 DIS@
VCCCORE[12] R253
AJ23

LVDS
VCCCORE[13] 0_0402_5%
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VccADAC 3.3 0.001
AJ27 +1.8VS

2
VCCCORE[15] L2 PX@
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2] 0.1UH_MLF1608DR10KT_10%_1608
AJ31 VCCCORE[17]
VccADPLLA 1.05 0.08
+1.05VS_PCH AP36 +VCCTX_LVDS 2 1
60mA VCCTX_LVDS[3] 0.1uH inductor, 200mA
1 1 1

1
22U_0805_6.3V6M
C218
VCCTX_LVDS[4]
AP37 VccADPLLB 1.05 0.08
R254 2 1 0_0603_5% +1.05VS_VCCDPLLEXP AN19 C216 C217 DIS@
VCCIO[28] 0.01U_0402_16V7K 0.01U_0402_16V7K PX@ R255
2 PX@ 2 PX@ 2 0_0402_5% VccCore 1.05 1.3
PAD T47 @ +VCCAPLLEXP BJ22 R256 +3VS

2
VCCAPLLEXP 0_0805_5%
This pin can be left as no connect in V33 +3VS_VCC3_3_6 1 2 VccDMI 1.05 0.042

HVCMOS
VCC3_3[6]
AN16
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16]
VccIO 1.05 2.925
V34 C219
VCC3_3[7]
0.1U_0402_10V7K
AN21 2 VccASW 1.05 1.01
@ J12 VCCIO[17]
2 1 AN26
VCCIO[18]
VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
PAD-OPEN 4x4m VCCIO[19] VCCVRM[3]
+1.05VS_PCH AP21 +VCCP_VCCDMI +1.05VS VccDSW 3.3 0.003
C VCCIO[20] R258 C
@
1 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VccpNAND 1.8 0.19

DMI
+1.05VS_PCH
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

R257 0_0805_5% 1 1 1 1 1 AP24 0_0805_5%

VCCIO
VCCIO[22]
10U_0805_6.3V6M
C221

@ C220
AP26 VCCIO[23] 20mA VCCIO[1] AB36 +1.05VS_VCC_DMI_CCI 0_0805_5% 1 R259 2 1U_0402_6.3V6K VccRTC 3.3 6 uA
2
2 2 2 2 2 1 1
AT24 C917 L75
VCCIO[24] C226 10UH_LBR2012T100M_20% VccSus3_3 3.3 0.119
1U_0402_6.3V6K @ 1 2
AN33 2 2
VCCIO[25] 10U_0603_6.3V6M 8/11 update for PDGD 1.2 VccSusHDA 3.3 / 1.5 0.01
AN34 AG16
+3VS R260 VCCIO[26] VCCPNAND[1] 8/27 update L75 symbol
0_0805_5% VccVRM 1.8 / 1.5 0.16

NAND / SPI
1 2 +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS
VCC3_3[3] 190mA VCCPNAND[2] R261
1
C227 0_0805_5% VccCLKDMI 1.05 0.02
0.1U_0402_10V7K AJ16 1 2
VCCPNAND[3]
2 1
+VCCAFDI_VRM AP16 C228 VccSSC 1.05 0.095
+1.05VS_PCH @ R262 VCCVRM[2] 0.1U_0402_10V7K
VCCPNAND[4] AJ17
0_0603_5% Place CH53 Near BG6 pin
2 1 +1.05VS_VCCAPLL_FDI 2 VccDIFFCLKN 1.05 0.055
BG6 VCCFDIPLL
+1.05VS_PCH R263
1
1 2 +1.05VS_VCCDPLL_FDI AP17 VCCIO[27]
VccALVDS 3.3 0.001
FDI

@C229
@ C229 0_0805_5% V1 +3V_VCCPSPI 1 R399 2
20mA VCCSPI +3VS
1U_0402_6.3V6K
2 AU20 0_0805_5% VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI VCCDMI[2] 1
C230
B COUGARPOINT_FCBGA989 1U_0402_6.3V6K B
2

6/30 update

+VCCAFDI_VRM
+1.5VS

R265 2 1 0_0603_5% +VCCAFDI_VRM

+1.8VS

R266 2 @ 1 0_0603_5%

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 20 of 59
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS @ R267 +1.05VS_PCH @ R268 VCC3_3 = 266mA detal waiting for newest spec
0_0805_5% 0_0603_5%
1 2 2 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
L3
10UH_LBR2012T100M_20%
1 2 +3VS_VCC_CLKF33 +3VALW R269
1 1 0_0603_5% U4J POWER R270 +1.05VS_PCH

10U_0805_10V4Z
C231

1U_0402_6.3V6K
C232
1 2 +VCCPDSW 0_0603_5%
1 AD49 N26 +1.05VS_VCCUSBCORE 2 1
VCCACLK VCCIO[29]
2 2
7/1 update to @ 1
C234 P26
0.1U_0402_10V7K VCCIO[30] C233
T16 3mA
D @ C235 2 VCCDSW3_3 1U_0402_6.3V6K D
VCCIO[31] P28
0.1U_0402_10V7K 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
T29
+3VS_VCC_CLKF33 VCCIO[33] R272 +3VALW
T38 VCC3_3[5]
+1.05VS_PCH @ R271 @ L4 0_0603_5%
0_0603_5% 10UH_LBR2012T100M_20% T23 +3V_VCCPUSB 2 1
1 2 +VCCAPLL_CPY 1 2 +VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3VALW

0.1U_0402_10V7K
C236
T24 1 R273
R274 +VCCDPLL_CPY VCCSUS3_3[8] +5VALW +3VALW
1 +1.05VS_PCH 1 2 0_0603_5% AL29 VCCIO[14]
0_0603_5%
V23 +3V_VCCAUBG 2 1

USB
VCCSUS3_3[9]

C237
10U_0805_6.3V6M
1

2
@ +VCCSUS1 AL24 V24 2 C238
2 DCPSUS[3] VCCSUS3_3[10] 0.1U_0402_10V7K R275 D1
1
P24 100_0402_5% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 R276 +1.05VS_PCH
1U_0402_6.3V6K AA19 0_0603_5%

1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
T26 2 1
+1.05VS_PCH R277 VCCIO[34]
AA21 VCCASW[2]
1010mA 1
0_0805_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242

Clock and Miscellaneous

AA26 @
VCCASW[4] +VCCA_USBSUS C243
AN23 1 2 1U_0402_6.3V6K
DCPSUS[4]
AA27
2 2 VCCASW[5] +3V_VCCPSUS
AN24
VCCSUS3_3[1]
AA29
VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN R278 +3VALW
VCCASW[8] 1mA V5REF

2
C 0_0603_5% C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27 2 1 R279 D2
VCCASW[9] +3V_VCCPSUS 100_0402_5% CH751H-40PT_SOD323-2
N20 1

PCI/GPIO/LPC
VCCSUS3_3[2] C247
AC29 VCCASW[10]
2 2 2 N22 1U_0402_6.3V

1
+1.05VS_PCH VCCSUS3_3[3] +PCH_V5REF_RUN
AC31 VCCASW[11]
L5 P20 2 R281 +3VS
VCCSUS3_3[4] 1
10UH_LB2012T100MR_20% AD29 0_0805_5%
+VCCA_DPLL_L +1.05VS_VCCA_A_DPL VCCASW[12] C248
1 2 VCCSUS3_3[5] P22 2 1
AD31 1 1U_0603_10V6K
VCCASW[13] C249 2
1 2 +1.05VS_VCCA_B_DPL W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
L6 VCCASW[14] VCC3_3[1]
2 +3VS
220U_B2_2.5VM_R35
C250

1U_0402_6.3V6K
C251

220U_B2_2.5VM_R35
C252

1U_0402_6.3V6K
C253

10UH_LB2012T100MR_20% 1 1 W23 W16 R282

VCCASW[15] VCC3_3[8] 0_0603_5%
1 1
+ + W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
1
W26 C254
2 2 2 2 VCCASW[17] 0.1U_0402_10V7K
W29 R283 +3VS
VCCASW[18] 0_0603_5% 2
W31 AJ2 +VCC3_3_2 2 1
R284 VCCASW[19] VCC3_3[2] +1.05VS_SATA3 R285 +1.05VS_PCH
1
0_0603_5% W33 0_0805_5%
+VCCDIFFCLK VCCASW[20] C255
+1.05VS_PCH 2 1 AF13 2 1
VCCIO[5] 0.1U_0402_10V7K
2 1
1 +VCCRTCEXT N16
C256 DCPRTC C257
1 AH13
1U_0402_6.3V6K C258 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
R286 2 VCCVRM[4] VCCIO[13]
0_0603_5% +1.05VS_VCCDIFFCLKN 2
B
2 1 +1.05VS_VCCDIFFCLKN AF14 L7 @ @ R287 +1.05VS_PCH B
+1.05VS_PCH VCCIO[6]
1 +1.05VS_VCCA_A_DPL BD47 10UH_LB2012T100MR_20% 0_0805_5%

SATA
VCCADPLLA 80mA +VCCSATAPLL +VCCSATAPLL_R2
VCCAPLLSATA AK1 1 2 1
C259 +1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM
1U_0402_6.3V6K VCCADPLLB 80mA
2 1
AF11 +VCCAFDI_VRM @ C260
R288 +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA R289 +1.05VS_PCH 10U_0805_6.3V6M
AF17
VCCIO[7]
0_0603_5% AF33 VCCIO[8]
0_0805_5% Place CH80 Near AK1 pin
2 1 +1.05VS_SSCVCC AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2
+1.05VS_PCH VCCIO[9] VCCIO[2]
1 +1.05VS_VCCDIFFCLKN AG34 VCCIO[11]
AC17 1
C262 VCCIO[3] C261
1U_0402_6.3V6K +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
2 VCCIO[10] 95mA VCCIO[4]
@ R290 2
0_0603_5% +VCCSST V16 +1.05VS_PCH
+1.05VM_VCCSUS DCPSST
+1.05VS_PCH 2 1 1

1 C263 +1.05VM_VCCSUS T17 T21 +VCCME_22 R291 2 1 0_0603_5%

0.1U_0402_10V7K DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC

@ C264 2
1U_0402_6.3V6K +1.05VS R293 V21 +VCCME_23 R292 2 1 0_0603_5%
2 0_0603_5% VCCASW[23]
CPU

1 2 +V_CPU_IO BJ8 V_PROC_IO 1mA +VCCME_21 R294

T19 2 1 0_0603_5%
VCCASW[21]
1 1 1
+RTCVCC +3VALW
4.7U_0603_6.3V6K
C265

0.1U_0402_10V7K
C266

0.1U_0402_10V7K
C267

RTC

A22 P32 +VCCSUSHDA R295 2 1 0_0603_5%

HDA

2 2 2 VCCRTC 10mA VCCSUSHDA

1U_0402_6.3V6K
C268

0.1U_0402_10V7K
C269

0.1U_0402_10V7K
C270

1 1 1 1
COUGARPOINT_FCBGA989 C271
A @ 0.1U_0402_16V4Z A

2 2 2 2

@
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/07/12 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 21 of 59
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 K46
D U4H VSS[163] VSS[263] D
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] VSS[165] VSS[265]
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
VSS[2] VSS[81] VSS[168] VSS[268]
AA3 VSS[3] VSS[82] AK42 B35
VSS[169] VSS[269]
L28
AA33 VSS[4] VSS[83] AK46 B39
VSS[170] VSS[270]
L36
AA34 VSS[5] VSS[84] AK8 B7
VSS[171] VSS[271]
L48
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 VSS[8] VSS[87] AL19 BB16
VSS[174] VSS[274]
M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 AL21 BB22 M24
VSS[10] VSS[89] VSS[176] VSS[276]
AB5 AL23 BB24 M30
VSS[11] VSS[90] VSS[177] VSS[277]
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 AL27 BB30 M34
VSS[13] VSS[92] VSS[179] VSS[279]
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 AL33 BB4 M4
VSS[15] VSS[94] VSS[181] VSS[281]
AC24 AL34 BB46 M42
VSS[16] VSS[95] VSS[182] VSS[282]
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 AM11 BC18 M8
VSS[18] VSS[97] VSS[184] VSS[284]
AC48 AM14 BC2 N18
VSS[19] VSS[98] VSS[185] VSS[285]
AD10 AM36 BC22 P30
VSS[20] VSS[99] VSS[186] VSS[286]
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 AM43 BC32 P11
VSS[22] VSS[101] VSS[188] VSS[288]
AD13 AM45 BC34 P18
VSS[23] VSS[102] VSS[189] VSS[289]
AD19 AM46 BC36 T33
VSS[24] VSS[103] VSS[190] VSS[290]
AD24 AM7 BC40 P40
VSS[25] VSS[104] VSS[191] VSS[291]
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 AN29 BC48 P47
VSS[27] VSS[106] VSS[193] VSS[293]
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 AN31 BD5 R2
C VSS[29] VSS[108] VSS[195] VSS[295] C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 AP19 BE26 T12
VSS[31] VSS[110] VSS[197] VSS[297]
AD38 AP28 BE40 T31
VSS[32] VSS[111] VSS[198] VSS[298]
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 AP32 BF12 T4
VSS[34] VSS[113] VSS[200] VSS[300]
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 AP4 BF20 T46
VSS[36] VSS[115] VSS[202] VSS[302]
AD43 VSS[37] VSS[116]
AP42 BF22
VSS[203] VSS[303]
T47
AD45 VSS[38] VSS[117]
AP46 BF24
VSS[204] VSS[304]
T8
AD46 VSS[39] VSS[118]
AP8 BF26
VSS[205] VSS[305]
V11
AD8 AR2 BF28 V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 AR48 BD3 V26
VSS[41] VSS[120] VSS[207] VSS[307]
AE3 VSS[42] VSS[121]
AT11 BF30
VSS[208] VSS[308]
V27
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 VSS[44] VSS[123]
AT18 BF40
VSS[210] VSS[310]
V31
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 VSS[46] VSS[125]
AT26 BG17
VSS[212] VSS[312]
V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 VSS[51] VSS[130]
AT39 BH11
VSS[217] VSS[317]
W2
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 VSS[53] VSS[132]
AT46 BH17
VSS[219] VSS[319]
W48
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 VSS[55] VSS[134]
AU24 H10
VSS[221] VSS[321]
Y38
AF42 VSS[56] VSS[135]
AU30 BH27
VSS[222] VSS[322]
Y4
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 VSS[58] VSS[137]
AV20 BH33
VSS[224] VSS[324]
Y46
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 VSS[60] VSS[139]
AV30 BH39
VSS[226] VSS[328]
BG29
AG19 AV38 BH43 N24
B VSS[61] VSS[140] VSS[227] VSS[329] B
AG2 VSS[62] VSS[141]
AV4 BH7
VSS[228] VSS[330]
AJ3
AG31 VSS[63] VSS[142]
AV43 D3
VSS[229] VSS[331]
AD47
AG48 VSS[64] VSS[143]
AV8 D12
VSS[230] VSS[333]
B43
AH11 VSS[65] VSS[144]
AW14 D16
VSS[231] VSS[334]
BE10
AH3 AW18 D18 BG41
VSS[66] VSS[145] VSS[232] VSS[335]
AH36 VSS[67] VSS[146]
AW2 D22
VSS[233] VSS[337]
G14
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 VSS[69] VSS[148]
AW26 D26
VSS[235] VSS[340]
T36
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 VSS[71] VSS[150]
AW32 D32
VSS[237] VSS[343]
BG24
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 VSS[73] VSS[152]
AW36 D38
VSS[239] VSS[345]
AP13
AJ21 VSS[74] VSS[153]
AW40 D42
VSS[240] VSS[346]
M14
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 VSS[76] VSS[155]
AV11 E18
VSS[242] VSS[348]
AP1
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 VSS[78] VSS[157]
AY22 G18
VSS[244] VSS[350]
BC16
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
COUGARPOINT_FCBGA989 VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A

COUGARPOINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 22 of 59
5 4 3 2 1
 5 4 3 2 1

PCIE_CTX_GRX_P[15..0] U8A PCIE_CRX_GTX_P[15..0]

<5> PCIE_CTX_GRX_P[15..0] PCIE_CRX_GTX_P[15..0] <5>
U8F
PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] R296
<5> PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] <5>
1 2
10K_0402_5%
LVDS CONTROL AB11
VARY_BL VGA_ENVDD
DIGON AB12 VGA_ENVDD <31>
PCIE_CTX_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 0.1U_0402_10V7K
2 C273
1 PCIE_CRX_GTX_P0
PCIE_CTX_GRX_N0 PCIE_RX0P PCIE_TX0P
AE31 PCIE_RX0N PCIE_TX0N AG31 PCIE_CRX_C_GTX_N0 2 1 PCIE_CRX_GTX_N0 1 2
0.1U_0402_10V7K C272 R297
D 10K_0402_5% D
PCIE_CTX_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.1U_0402_10V7K
2 C274
1 PCIE_CRX_GTX_P1 AH20
PCIE_CTX_GRX_N1 PCIE_RX1P PCIE_TX1P TXCLK_UP_DPF3P
AD28 PCIE_RX1N PCIE_TX1N AF28 PCIE_CRX_C_GTX_N1 2 1 PCIE_CRX_GTX_N1
TXCLK_UN_DPF3N AJ19
0.1U_0402_10V7K C275
TXOUT_U0P_DPF2P AL21
PCIE_CTX_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_10V7K
2 C276
1 PCIE_CRX_GTX_P2 AK20
PCIE_CTX_GRX_N2 PCIE_RX2P PCIE_TX2P TXOUT_U0N_DPF2N
AC31 PCIE_RX2N PCIE_TX2N AF26 PCIE_CRX_C_GTX_N2 2 1 PCIE_CRX_GTX_N2
0.1U_0402_10V7K C277 AH22
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N AJ21
PCIE_CTX_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.1U_0402_10V7K
2 C278
1 PCIE_CRX_GTX_P3
PCIE_CTX_GRX_N3 PCIE_RX3P PCIE_TX3P
AB28 PCIE_RX3N PCIE_TX3N AD26 PCIE_CRX_C_GTX_N3 2 1 PCIE_CRX_GTX_N3
TXOUT_U2P_DPF0P AL23
0.1U_0402_10V7K C279 AK22
TXOUT_U2N_DPF0N

PCI EXPRESS INTERFACE

PCIE_CTX_GRX_P4 AB30 AC25 PCIE_CRX_C_GTX_P4 0.1U_0402_10V7K
2 C280
1 PCIE_CRX_GTX_P4 AK24
PCIE_CTX_GRX_N4 PCIE_RX4P PCIE_TX4P TXOUT_U3P
AA31 PCIE_RX4N PCIE_TX4N AB25 PCIE_CRX_C_GTX_N4 2 1 PCIE_CRX_GTX_N4
TXOUT_U3N AJ23
0.1U_0402_10V7K C281

PCIE_CTX_GRX_P5 AA29 Y23 PCIE_CRX_C_GTX_P5 0.1U_0402_10V7K

2 C282
1 PCIE_CRX_GTX_P5 LVTMDP
PCIE_CTX_GRX_N5 PCIE_RX5P PCIE_TX5P PCIE_CRX_C_GTX_N5 PCIE_CRX_GTX_N5
Y28 PCIE_RX5N PCIE_TX5N Y24 2 1
0.1U_0402_10V7K C283 AL15
TXCLK_LP_DPE3P VGA_LVDS_ACLK <31>
TXCLK_LN_DPE3N AK14 VGA_LVDS_ACLK# <31>
PCIE_CTX_GRX_P6 Y30 AB27 PCIE_CRX_C_GTX_P6 0.1U_0402_10V7K
2 C284
1 PCIE_CRX_GTX_P6
PCIE_CTX_GRX_N6 PCIE_RX6P PCIE_TX6P
W31 PCIE_RX6N PCIE_TX6N AB26 PCIE_CRX_C_GTX_N6 2 1 PCIE_CRX_GTX_N6
TXOUT_L0P_DPE2P AH16 VGA_LVDS_A0 <31>
0.1U_0402_10V7K C285 AJ15
C TXOUT_L0N_DPE2N VGA_LVDS_A0# <31> C

PCIE_CTX_GRX_P7 W29 Y27 PCIE_CRX_C_GTX_P7 0.1U_0402_10V7K

2 C286
1 PCIE_CRX_GTX_P7 AL17
PCIE_RX7P PCIE_TX7P TXOUT_L1P_DPE1P VGA_LVDS_A1 <31>
PCIE_CTX_GRX_N7 V28 Y26 PCIE_CRX_C_GTX_N7 2 1 PCIE_CRX_GTX_N7 AK16
PCIE_RX7N PCIE_TX7N TXOUT_L1N_DPE1N VGA_LVDS_A1# <31>
0.1U_0402_10V7K C287
TXOUT_L2P_DPE0P AH18 VGA_LVDS_A2 <31>
PCIE_CTX_GRX_P8 V30 W24 PCIE_CRX_C_GTX_P8 0.1U_0402_10V7K
2 C288
1 PCIE_CRX_GTX_P8 AJ17
PCIE_RX8P PCIE_TX8P TXOUT_L2N_DPE0N VGA_LVDS_A2# <31>
PCIE_CTX_GRX_N8 U31 W23 PCIE_CRX_C_GTX_N8 2 1 PCIE_CRX_GTX_N8
PCIE_RX8N PCIE_TX8N 0.1U_0402_10V7K C289
TXOUT_L3P AL19
TXOUT_L3N AK18
PCIE_CTX_GRX_P9 U29 V27 PCIE_CRX_C_GTX_P9 0.1U_0402_10V7K
2 C290
1 PCIE_CRX_GTX_P9
PCIE_CTX_GRX_N9 PCIE_RX9P PCIE_TX9P
T28 PCIE_RX9N PCIE_TX9N U26 PCIE_CRX_C_GTX_N9 2 1 PCIE_CRX_GTX_N9
0.1U_0402_10V7K C291

PCIE_CTX_GRX_P10 T30 U24 PCIE_CRX_C_GTX_P10 0.1U_0402_10V7K

2 C292
1 PCIE_CRX_GTX_P10 216-0774207-A11ROB_FCBGA631
PCIE_CTX_GRX_N10 PCIE_RX10P PCIE_TX10P
R31 PCIE_RX10N PCIE_TX10N U23 PCIE_CRX_C_GTX_N10 2 1 PCIE_CRX_GTX_N10
0.1U_0402_10V7K C293

PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
R29
P28
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
T26
T27
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
0.1U_0402_10V7K
2
2
C294
1
1
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11 LVDS
0.1U_0402_10V7K C295

PCIE_CTX_GRX_P12 P30 T24 PCIE_CRX_C_GTX_P12 0.1U_0402_10V7K

2 C296
1 PCIE_CRX_GTX_P12
PCIE_CTX_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_CRX_C_GTX_N12 PCIE_CRX_GTX_N12
N31 PCIE_RX12N PCIE_TX12N T23 2 1
B 0.1U_0402_10V7K C297 B

PCIE_CTX_GRX_P13 N29 P27 PCIE_CRX_C_GTX_P13 0.1U_0402_10V7K

2 C298
1 PCIE_CRX_GTX_P13
PCIE_CTX_GRX_N13 PCIE_RX13P PCIE_TX13P PCIE_CRX_C_GTX_N13 PCIE_CRX_GTX_N13
M28 PCIE_RX13N PCIE_TX13N P26 2 1
0.1U_0402_10V7K C299

PCIE_CTX_GRX_P14 M30 P24 PCIE_CRX_C_GTX_P14 0.1U_0402_10V7K

2 C300
1 PCIE_CRX_GTX_P14
PCIE_CTX_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_CRX_C_GTX_N14 PCIE_CRX_GTX_N14
L31 PCIE_RX14N PCIE_TX14N P23 2 1
0.1U_0402_10V7K C301

PCIE_CTX_GRX_P15 L29 M27 PCIE_CRX_C_GTX_P15 0.1U_0402_10V7K

2 C302
1 PCIE_CRX_GTX_P15
PCIE_CTX_GRX_N15 PCIE_RX15P PCIE_TX15P
K30 PCIE_RX15N PCIE_TX15N N26 PCIE_CRX_C_GTX_N15 2 1 PCIE_CRX_GTX_N15
0.1U_0402_10V7K C303

CLOCK
T48 PAD
CLK_PCIE_VGA
<15> CLK_PCIE_VGA AK30 PCIE_REFCLKP
CLK_PCIE_VGA# AK32
<15> CLK_PCIE_VGA# PCIE_REFCLKN
T49 PAD
CALIBRATION
VGA_PWRGD Y22 1.27K_0402_1% 1 2 R298
<25> VGA_PWRGD PCIE_CALRP
2 R299 1 N10 PWRGOOD PCIE_CALRN AA22 2K_0402_5% 1 2 R300 +1.0VGS
A 10K_0402_5% A

<18> VGA_RST# AL27 PERSTB

Security Classification Compal Secret Data Compal Electronics, Inc.
216-0774207-A11ROB_FCBGA631 Issued Date 2010/07/12 2012/07/11 Title
Deciphered Date
RobsonXT-S3 PCIE/LVDS
PCIE LANE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
B
Document Number Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 23 of 59
5 4 3 2 1

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 5 4 3 2 1

Transmitter Power Saving Enable U8B CONFIGURATION STRAPS RECOMMENDED SETTINGS

TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1: full Tx output swing (Default setting for Desktop) 1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
PCI Express Transmitter De-emphasis Enable TXCAP_DPA3P
AF2 VGA_HDMI_CLK+ <33> NA = NOT APPLICABLE
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode TXCAM_DPA3N
AF4 VGA_HDMI_CLK- <33>
1: Tx de-emphasis enabled (Defailt setting for desktop) T52 Y11
T53 DVCLK RECOMMENDED
AE9 AG3 VGA_HDMI_TX0+ <33>
T54 DVCNTL_0 TX0P_DPA2P STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
L9 AG5 VGA_HDMI_TX0- <33> SETTINGS
T55 DVCNTL_1 DVO DPA TX0M_DPA2N
N9
DVCNTL_2
AH3 VGA_HDMI_TX1+ <33>
T50 TX1P_DPA1P TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING X
AE8 AH1 VGA_HDMI_TX1- <33>
T56 DVDATA_12 TX1M_DPA1N
AD9
T57 DVDATA_11
AC10 AK3 VGA_HDMI_TX2+ <33>
+1.8VGS +DPC_VDD18 T51 DVDATA_10 TX2P_DPA0P TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED X
AD7 AK1 VGA_HDMI_TX2- <33>
L8 T58 DVDATA_9 TX2M_DPA0N
150mA +DPC_VDD18 T59
AC8
DVDATA_8
2 1 AC7 AK5
BLM15BD121SN1D_0402 T60 DVDATA_7 TXCBP_DPB3P RSVD GPIO2 RESERVED 0
AB9 AM3
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K
D DVDATA_6 TXCBM_DPB3N D
C304

C305

C306
1 1 1 T61 AB8
T62 DVDATA_5
Change to 0 ohm AB7
DVDATA_4 TX3P_DPB2P
AK6
T70 AB4 AM5 RSVD GPIO8 RESERVED 0
P/N VRAM_ID2 DVDATA_3 DPB TX3M_DPB2N
<29> VRAM_ID2 AB2
2 2 2 VRAM_ID1 DVDATA_2
<29> VRAM_ID1 Y8 AJ7
VRAM_ID0 DVDATA_1 TX4P_DPB1P BIF_VGA DIS GPIO9 VGA ENABLED 0
<29> VRAM_ID0 Y7 AH6
DVDATA_0 TX4M_DPB1N
AK8
TX5P_DPB0P RSVD GPIO21 RESERVED 0
AL7
TX5M_DPB0N

+DPC_VDD18 +DPC_VDD18 W6 DPC BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM X

DPC_PVDD
V6
+1.0VGS +DPC_VDD10 DPC_PVSS
V4
L9 +DPC_VDD18 TXCCP_DPC3P ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
110mA +DPC_VDD10 +DPC_VDD18 AC6
DPC_VDD18#1 TXCCM_DPC3N
U5
2 1 AC5
BLM15BD121SN1D_0402 DPC_VDD18#2
W3
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

+DPC_VDD10 TX0P_DPC2P VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0

C307

C308

C309

1 1 1 +DPC_VDD10 AA5 V2
DPC_VDD10#1 TX0M_DPC2N
Change to 0 ohm AA6
DPC_VDD10#2
Y4
P/N TX1P_DPC1P RSVD H2SYNC 0
W5
2 2 2 TX1M_DPC1N
U1 AA3
DPC_VSSR#1 TX2P_DPC0P RSVD GENERICC 0
W1 Y2
DPC_VSSR#2 TX2M_DPC0N
U3
DPC_VSSR#3
Y6 J8 1 R305 2 AUD[1] AUD[0]
DPC_VSSR#4 DPC_CALR 150_0402_1% VGA_CRT_R AUD[1] HSYNC 11
AA1 0 0 No audio function
DPC_VSSR#5
0 1 Audio for DisplayPort and HDMI if dongle is detected
VGA_CRT_G AUD[0] VSYNC 1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
VGA_CRT_B

R318 1

R320 1

R541 1
+3VGS I2C
AMD RESERVED CONFIGURATION STRAPS

150_0402_1%

150_0402_1%

150_0402_1%
@ 1R306 4.7K_0402_5%
2 VGA_SMB_CK2_R VGA_SMB_CK2_R R1 ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
@ SCL
1R307 4.7K_0402_5%
2 VGA_SMB_DA2_R VGA_SMB_DA2_R R3
SDA RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND

2
AM26 VGA_CRT_R
GENERAL PURPOSE I/O R VGA_CRT_R <32> NOT CONFLICT DURING RESET
C AK26 C
GPU_GPIO0 RB
U6
GPU_GPIO1 GPIO_0 VGA_CRT_G GPIO21 H2SYNC GENERICC GPIO2 GPIO8
8/13 update to @ U10
GPIO_1 G
AL25 VGA_CRT_G <32>
GPU_GPIO2 T10 AJ25
GPIO_2 GB
D3 U8
CH751H-40PT_SOD323-2 @ GPIO_3_SMBDATA VGA_CRT_B
U7 AH24 VGA_CRT_B <32>
GPU_GPIO5 GPIO_4_SMBCLK B +AVDD +1.8VGS
1 2 T9 AG25
<16,40,47> ACIN
T8
GPIO_5_AC_BATT
GPIO_6
DAC1 BB
65mA L10 STRAPS +3VGS
1 R662 2 VGA_ENBKL VGA_ENBKL T7 AH26 VGA_HSYNC +AVDD 1 2
<31> VGA_ENBKL GPIO_7_BLON HSYNC VGA_HSYNC <32>
10K_0402_5% GPU_GPIO8 P10 AJ27 VGA_VSYNC BLM15BD121SN1D_0402 GPU_GPIO0 R309 2 @ 1 10K_0402_5%

10U_0603_6.3V6M
0.1U_0402_10V6K

1U_0402_6.3V4Z
GPIO_8_ROMSO VSYNC VGA_VSYNC <32>
GPU_GPIO9 GPU_GPIO1 R310 10K_0402_5%

C310

C311

C312
@ P4 1 1 1 2 1
GPIO_9_ROMSI GPU_GPIO2 R311 10K_0402_5%
P2
GPIO_10_ROMSCK Change to 0 ohm 2 1
GPU_GPIO11 N6 AD22 1 R312 2 GPU_GPIO5 R308 2 @ 1 10K_0402_5%
GPU_GPIO12 GPIO_11 RSET 499_0402_1% P/N
N5
GPU_GPIO13 GPIO_12 +AVDD +AVDD 2 2 2 GPU_GPIO8 R313 @
N3 AG24 2 1 10K_0402_5%
GPIO_13 AVDD GPU_GPIO9 R314 @
Y9 AE22 2 1 10K_0402_5%
GPU_VID0 GPIO_14_HPD2 AVSSQ
<52> GPU_VID0 N1
T63 GPIO_15_PWRCNTL_0
M4 AE23 +VDD1DI +VDD1DI GPU_GPIO11 R315 2 1 10K_0402_5%
THM_ALERT# GPIO_16_SSIN VDD1DI GPU_GPIO12 R316 @
R6 AD23 2 1 10K_0402_5%
GPIO_17_THERMAL_INT VSS1DI GPU_GPIO13 R317 @
W10 2 1 10K_0402_5%
R319 1 10K_0402_5% GPIO_18_HPD3 +VDD1DI +1.8VGS
2 M2
GPU_VID1 GPIO_19_CTF L11 VGA_HSYNC R548
<52> GPU_VID1 P8 AM12 110mA 1 DIS@ 2 10K_0402_5%
GPIO_20_PWRCNTL_1 R2 +VDD1DI VGA_VSYNC R549
P7 AK12 1 2 1 DIS@ 2 10K_0402_5%
GPIO_21_BB_EN R2B BLM15BD121SN1D_0402
N8

10U_0603_6.3V6M
0.1U_0402_10V6K

1U_0402_6.3V4Z
PEG_CLKREQ# GPIO_22_ROMCSB

C313

C314

C315
+3VGS <15> PEG_CLKREQ# N7
GPIO_23_CLKREQB G2
AL11 1 1 1 8/5 Add For DIS HDMI audio strap
G2B
AJ11 Change to 0 ohm
GPIO24_TRSTB L6
R321 10K_0402_5% GPIO24_TRSTB GPIO25_TDI JTAG_TRSTB P/N +3VGS
1 2 L5 AK10
R322 10K_0402_5% GPIO25_TDI GPIO26_TCK JTAG_TDI B2 2 2 2
1 2 L3 AL9
R323 10K_0402_5% GPIO27_TMS GPIO27_TMS JTAG_TCK B2B VGA_HDMI_SCL R714 DIS_HDMI@
1 2 L1 2 1 10K_0402_5%
R324 10K_0402_5% GPIO26_TCK T64 GPIO28_TDO JTAG_TMS VGA_HDMI_SDA R713 DIS_HDMI@
1 2 K4 2 1 10K_0402_5%
TEST_EN K7 JTAG_TDO VGA_LVDS_SCL R712 DIS@
2 1 AH12 2 1 10K_0402_5%
R326 T65 TESTEN C VGA_LVDS_SDA R711 DIS@
AF24 AM10 2 1 10K_0402_5%
10K_0402_5% TESTEN_LEGACY Y VGA_DDCCLK R621 DIS@
AJ9 2 1 10K_0402_5%
COMP +VDD2DI +1.8VGS VGA_DDCDATA R426 DIS@
2 1 10K_0402_5%
DAC2 L12
AB13
GENERICA +VDD2DI
2mA
W8 AL13 1 2
+1.8VGS +DPLL_PVDD GENERICB H2SYNC BLM15BD121SN1D_0402
W9 AJ13

10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
B GENERICC V2SYNC +3VGS B

C316

C317

C318
L14 75mA W7 1 1 1
+DPLL_PVDD GENERICD
2 1 AD10
GENERICE_HPD4 Change to 0 ohm
BLM15BD121SN1D_0402 AD19 +VDD2DI +VDD2DI
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

VDD2DI P/N
C323

C324

C325

1 1 1 <33> HDMI_DETECT_VGA AC14 AC19

PX_EN HPD1 VSS2DI 2 2 2 +3VGS
<25> PX_EN AB16

1
PX_EN
1 2 R613 AE20 +A2VDD +A2VDD R327 R328 8/14 change P/N to
2 2 2 4.7K_0402_5% A2VDD 10K_0402_5% 10K_0402_5%
0.60 V level, Please AE17 +A2VDDQ +A2VDDQ
DMN66D0LDW-7_SOT363-6
A2VDDQ

2
VREFG Divider ans (SB00000DH00)

2
+1.8VGS AE19 +A2VDD +3VGS
cap close to ASIC A2VSSQ L13 VGA_SMB_CK2_R
100mA 1 6 EC_SMB_CK2 <15,37,40>
2 R329 1499_0402_1% +VREFG_GPU AC16 +A2VDD 1 2

5
+1.0VGS +DPLL_VDDC VREFG
AG13 1 R330 2 BLM15BD121SN1D_0402 Q64A

10U_0603_6.3V6M
0.1U_0402_10V6K

1U_0402_6.3V4Z
R2SET

C319

C320

C321
L16 125mA +DPLL_VDDC 2 R331 1249_0402_1% 715_0402_1% 1 1 1 2N7002DW-T/R7_SOT363-6
2 1 Change to 0 ohm VGA_SMB_DA2_R 4 3 EC_SMB_DA2 <15,37,40>
BLM15BD121SN1D_0402 2 1
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

C322 0.1U_0402_10V6K DDC/AUX VGA_HDMI_SCL P/N Q64B

C330

C331

C332

1 1 1 AE6 VGA_HDMI_SCL <33>

PLL/CLOCK DDC1CLK VGA_HDMI_SDA 2 2 2 2N7002DW-T/R7_SOT363-6
AE5
+DPLL_PVDD DDC1DATA VGA_HDMI_SDA <33>
+DPLL_PVDD AF14
DPLL_PVDD
AE14 AD2
2 2 2 DPLL_PVSS AUX1P
AD4
AUX1N +3VGS
+DPLL_VDDC +DPLL_VDDC AD14 AC11 VGA_LVDS_SCL
DPLL_VDDC DDC2CLK VGA_LVDS_SCL <31> +A2VDDQ +1.8VGS
AC13 VGA_LVDS_SDA

XTALIN XTALIN AM28

DDC2DATA
AD13
VGA_LVDS_SDA <31>
130mA
+A2VDDQ 1
L15
2 C329
2 VGA Thermal Sensor
+1.8VGS @ +TSVDD XTALOUT XTALIN AUX2P BLM15BD121SN1D_0402 0.1U_0402_16V4Z
Voltage Swing: 1.8 V AK28 AD11
EMC1402-1 Closed to GPU

10U_0603_6.3V6M
0.1U_0402_10V6K

1U_0402_6.3V4Z
XTALOUT AUX2N

C326

C327

C328
L17 20mA 1 1 1
+TSVDD 2 R332 10_0402_5% 1
2 1 AC22
XO_IN DDCCLK_AUX3P
AD20 Change to 0 ohm
BLM18AG121SN1D_0603 2 R333 10_0402_5% AB22 AC20 U9
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_16V4Z

XO_IN2 DDCDATA_AUX3N P/N VGA_SMB_CK2_R

C334

C335

C336

1 1 1 1 8
2 2 2 VDD SCLK
AE16
DDCCLK_AUX5P GPU_THERMAL_D+ VGA_SMB_DA2_R
AD16 2 7
DDCDATA_AUX5N D+ SDATA
2 2 2 AC1 VGA_DDCCLK 1 2 3 6
DDC6CLK VGA_DDCCLK <32> D- ALERT#
@

GPU_THERMAL_D+ T4 THERMAL AC3 VGA_DDCDATA C333

L17 GPU_THERMAL_D- DPLUS DDC6DATA VGA_DDCDATA <32> 2200P_0402_50V7K THM_ALERT#
A T2 4 5 A
DMINUS GPU_THERMAL_D- THERM# GND
R334 2.61K_0402_5%
+3VGS 1 2 R5 +3VGS 1 R335 2 EMC1402-2-ACZL-TR MSOP 8P 2 R336 1 +3VGS
+TSVDD TS_FDO 4.7K_0402_5%
+TSVDD AD17
XTALOUT R337 XTALIN TSVDD 4.7K_0402_5%
AC17
1M_0603_5% TSVSS EMC1412-A (SA00003YA00)
0_0603 5% @
Address 1111_100xb
SD013000080 Y3 S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
2 1 216-0774207-A11ROB_FCBGA631

27MHZ_16PF_X5H027000FG1H
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
C337 C338
18P_0402_50V8J 18P_0402_50V8J RobsonXT-S3 Main Generic/MSIC

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 24 of 59
5 4 3 2 1
 5 4 3 2 1

@ 0_0402_5%
<52> VGA_CORE_PG 1 2 VGA_PWRGD VGA_PWRGD <23>
R689

VGA_CORE_PG +3VGS +5VS +5VS

D D

1
0.1U_0402_10V6K
R338

1
@
10K_0402_5%

C339
1 R339 BACO@
10K_0402_5%

2
BACO@ VDDC_ON#

2
2 1.0V_ON#

5
+3VGS 1 R612 2 U10

1
10K_0402_5% BACO@ D D
2

P
R692 B 2N7002H_SOT23-3 2N7002H_SOT23-3
BACO@ @
PX_MODE Y 4 2
Q66
2
Q67
+3VS 1 R340 2 1 2 1 A
G G

G
S Change footprint S Change footprint

3
@ 10K_0402_5% 0_0402_5% MC74VHC1G08DFT2G SC70 5P 20100814 20100814

3
BACO@
BACO@
1

1
D
2N7002H_SOT23-3 C382 C386
<24> PX_EN 1 2 2
R341 G Q68 0.1U_0402_10V6K @ 0.1U_0402_10V6K
0_0402_5% S Change footprint 1 2 2 @
+3VGS
3

BACO@ 20100814 Q69 Q70

C U37 C
AO3414_SOT23-3 AO3414_SOT23-3

5
BACO@ +1.0VGS +BIF_VDDC +VGA_CORE

S
2 3 1 1 3

P
B PX_MODE
Y 4 PX_MODE <26,52>
+3VGS 1 BACO@ BACO@
A

G
C731

G
1 2

G
2

0.1U_0402_10V6K
1 2 BACO@ 1.0V_ON# R342

BACO@ C343
@ MC74VHC1G08DFT2G SC70 5P 1 0_0402_5%
1

BACO@ 0.1U_0402_10V6K DIS@

R872 Q71 Q72
20K_0402_5% AO3414_SOT23-3 AO3414_SOT23-3
5

@ +VGA_CORE 2

S
1 3 1 1 3
P
2

NC RUNPWROK
Y 4
PE_GPIO1 1 2 2 BACO@ BACO@
<15,18,26,52> PE_GPIO1 A
G

D28 U40

G
2

2
CH751H-40PT_SOD323-2 SN74LVC1G07DCKR_SC70-5 VDDC_ON#
3

BACO@ 1
Add when verify BACO
C732
1U_0603_10V4Z
2 2 1
@
R873
B 0_0402_5% BACO@ 9/28 modify to AO3414 B

D28 with leakage need to check

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 Main Generic/MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 25 of 59
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

Short J2 for control sequence at PWM

+VGA_PCIE TO +1.0VGS
+VGA_PCIE +1.0VGS +1.8VS @ +1.8VGS
@
+1.8VS TO +1.8VGS 2 1
2 1
2MM J5
D 2MM J2 D
U14 @ U13
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8
8 1 10U_0805_10V4Z 1U_0603_10V4Z 8 1
1 7 2 1 7 2 1 1

1
6 3 1 1 6 3
C346 5 C375 C368 R664 C348 5 C349 C350
10U_0805_10V4Z 470_0603_5% 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R348
2 2 2 2 470_0603_5%

4
2 2 @ @

1 2

1 2
@
+VSB D +VSB D
0_0402_5% 2N7002H_SOT23-3 2N7002H_SOT23-3
2 2
R640 1 2 Q75 G Q76 G

1
R687 @ S Change footprint @ S Change footprint

3
@ @ 20100814 20100814
20K_0402_5% 330K_0402_5%
R350

1
D
2N7002H_SOT23-3 1 C730

2
PE_GPIO1# 2 1 R352 2
G Q85 0.1U_0603_25V7K 0_0402_5% PE_GPIO1#

2
S@ 1
3

1
Change footprint @ 2 PE_GPIO1# D R354 C352
20100814 PE_GPIO1# 2 0_0402_5% 0.1U_0603_25V7K
G Q78 @
S 2

1
Change footprint 2N7002H_SOT23-3
20100814

C C

+1.5VS TO +1.5VGS

+1.5V +1.5VGS

2 1

2MM J3 @
U11
+3.3VS TO +3.3VGS +3VS +3VGS DMN3030LSS-13_SOP8L-8
@ 8 1
2 1 10U_0805_10V4Z 1U_0603_10V4Z 1 7 2 1 1

1
6 3 C341 C342
1

2MM J4 1 1 C340 5 10U_0805_10V4Z 1U_0603_10V4Z R343

C376 C377 R686 10U_0805_10V4Z 470_0603_5%
470_0603_5% 2 2 2 @
3 1

4
@

1 2
Change footprint 2 2
2

+5VALW 20100814 Q65 +VSB D

AP2301GN-HF_SOT23-3 2N7002H_SOT23-3
2
2

D Q73 G
2N7002H_SOT23-3 R344 @ Change footprint
2 S

3
Q77 G 20K_0402_5% 20100814
R641 R688 @ S Change footprint
3

20100814 DIS@ 0_0402_5% R345

20K_0402_5% 20K_0402_5% PE_GPIO1# 1 2 1 2 @ 0_0402_5%

2
R674 200K_0402_1% 1 PE_GPIO1# 1 2

1
0_0402_5% D R346 R680
1
1

D C351 PE_GPIO1# PX_MODE# 0_0402_5% C344 @ 0_0402_5%

1 2 2
B PE_GPIO1 2 0.1U_0603_25V7K R677 G Q74 @ 0.1U_0603_25V7K PX_MODE# 1 2 B
G Q86 BACO@ S 2 R681

1
S 2 2N7002H_SOT23-3
3

Change footprint 2N7002H_SOT23-3 Add when verify BACO

20100814 Change footprint
20100814
DIS@

0_0402_5%
1 2 PE_GPIO1
<10,40,44,49,51,52> SUSP#
R744
+3VALW
+3VALW
1
1

R676
R718 100K_0402_5%
100K_0402_5%
2
2

PX_MODE# PE_GPIO1#

Q121
1

D DTC124EKAT146_SC59-3
PX_MODE 2N7002H_SOT23-3
2
OUT

<25,52> PX_MODE Q87

G
1

S Change footprint
3

20100814 PE_GPIO1 2
<15,18,25,52> PE_GPIO1 IN
R719
GND

100K_0402_5%
2

A A
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 Main Generic/MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 26 of 59
5 4 3 2 1
 5 4 3 2 1

+1.8VGS +DPEF_VDD18 +DPAB_VDD18 +1.8VGS

L18 total:440mA@LVDS L19
total:300mA@DP total:300mA
2 1 2 1

10U_0603_6.3V6M

10U_0603_6.3V6M
C353

C354

C355

C357

C358

C359
0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
D
1 1 1 1 1 1 D
MBK1608121YZF_0603 U8G MBK1608121YZF_0603
Change to 0 ohm 2 2 2 2 2 2
Change to 0 ohm
DP E/F POWER DP A/B POWER
P/N 130mA P/N
+1.0VGS AG15 AE11 +DPAB_VDD18
DPE_VDD18#1 DPA_VDD18#1
AG16 DPE_VDD18#2 DPA_VDD18#2 AF11
+DPEF_VDD10 +DPAB_VDD10 +1.0VGS
L20 total:240mA@LVDS L21
total:220mA@DP 110mA total:220mA
2 1 AG20 DPE_VDD10#1 DPA_VDD10#1 AF6 1 2

10U_0603_6.3V6M

10U_0603_6.3V6M
C356

C360

C361

C362

C363

C364
0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 1 1 AG21 DPE_VDD10#2 DPA_VDD10#2 AF7 1 1 1
MBK1608121YZF_0603 MBK1608121YZF_0603
Change to 0 ohm
P/N 2 2 2
AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
2 2 2
Change to 0 ohm
AH14 AE3
AM14
DPE_VSSR#2 DPA_VSSR#2
AG1 P/N
DPE_VSSR#3 DPA_VSSR#3
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5

+DPEF_VDD18 +DPAB_VDD18
130mA
AF16 AE13 +DPAB_VDD18
DPF_VDD18#1 DPB_VDD18#1
C AG17 DPF_VDD18#2 DPB_VDD18#2 AF13 C

+DPEF_VDD10 +DPAB_VDD10
110mA
AF22 AF8 +DPAB_VDD10
DPF_VDD10#1 DPB_VDD10#1
AG22 DPF_VDD10#2 DPB_VDD10#2 AF9

AF23 DPF_VSSR#1 DPB_VSSR#1 AF10

AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8

R355
2 1 AF17 DPEF_CALR DPAB_CALR AE10 1 R356 2
150_0402_1% 150_0402_1%
+DPEF_VDD18 +DPAB_VDD18
20mA 20mA
+DPEF_VDD18 AG18 DP PLL POWER AG8 +DPAB_VDD18
DPE_PVDD DPA_PVDD
AF19 DPE_PVSS DPA_PVSS AG7

B +DPEF_VDD18 +DPAB_VDD18 B
20mA 20mA
+DPEF_VDD18 AG19 AG10 +DPAB_VDD18
DPF_PVDD DPB_PVDD
AF20 DPF_PVSS DPB_PVSS AG11

216-0774207-A11ROB_FCBGA631

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 DP PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 27 of 59
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+1.5VGS

2.3A(RMS)/2.8A(Peak)

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
C365

C366

C369

C370

C371

C372

C373

C374

C389

C390

C391

C381

C392
1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2
+PCIE_VDDR +1.8VGS
9/28 Reserved for VGA_CORE
504mA L22
U8D +PCIE_VDDR 2 1
10/8 change to B2 size U8E

10U_0603_6.3V6M
0.1U_0402_10V6K

1U_0402_6.3V4Z

1U_0402_6.3V4Z
MEM I/O

C385

C387

C388

C380
1 1 1 1 MBK1608121YZF_0603
D D
PCIE Change to 0 ohm
H13 AB23 +VGA_CORE AA27 A3
VDDR1#1 PCIE_VDDR#1 P/N PCIE_VSS#1 GND#1
H16 AC23 AB24 A30
VDDR1#2 PCIE_VDDR#2 2 2 2 2 PCIE_VSS#2 GND#2
H19 AD24 AB32 AA13
VDDR1#3 PCIE_VDDR#3 PCIE_VSS#3 GND#3

220U_B2_2.5VM_R35
C736
J10 AE24 1 AC24 AA16
VDDR1#4 PCIE_VDDR#4 PCIE_VSS#4 GND#4
J23 AE25 AC26 AB10
VDDR1#5 PCIE_VDDR#5 + PCIE_VSS#5 GND#5
J24 AE26 AC27 AB15
VDDR1#6 PCIE_VDDR#6 @ PCIE_VSS#6 GND#6
J9 AF25 AD25 AB6
VDDR1#7 PCIE_VDDR#7 +1.0VGS PCIE_VSS#7 GND#7
K10 AG26 AD32 AC9
VDDR1#8 PCIE_VDDR#8 2 PCIE_VSS#8 GND#8
K23 AE27 AD6
VDDR1#9 PCIE_VSS#9 GND#9
K24 1920mA AF32 AD8
VDDR1#10 PCIE_VSS#10 GND#10
K9 L23 AG27 AE7
VDDR1#11 PCIE_VDDC#1 PCIE_VSS#11 GND#11
L11 L24 AH32 AG12

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12

C398

C399

C383

C403

C384
L12 L25 1 1 1 1 1 K28 AH10
+1.8VGS +VDDC_CT VDDR1#13 PCIE_VDDC#3 PCIE_VSS#13 GND#13
L13 L26 K32 AH28
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#14 GND#14
L20 M22 L27 B10
L23 VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
110mA L21
VDDR1#16 PCIE_VDDC#6
N22
2 2 2 2 2
M32
PCIE_VSS#16 GND#16
B12
1 2 L22 N23 N25 B14
BLM15BD121SN1D_0402 VDDR1#17 PCIE_VDDC#7 PCIE_VSS#17 GND#17
N24 N27 B16
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

+3VGS PCIE_VDDC#8 PCIE_VSS#18 GND#18

C404

C405

C408

1 1 1 R22 P25 B18

PCIE_VDDC#9 PCIE_VSS#19 GND#19
Change to 0 ohm LEVEL PCIE_VDDC#10
T22 P32
PCIE_VSS#20 GND#20
B20
U22 R27 B22
P/N TRANSLATION PCIE_VDDC#11 +VGA_CORE PCIE_VSS#21 GND#21
V22 T25 B24
10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 PCIE_VDDC#12 PCIE_VSS#22 GND#22
C409

C410

C411
1 1 1 17mA AA20
VDD_CT#1
T32
PCIE_VSS#23 GND#23
B26

@
AA21
AB20
VDD_CT#2
AA15
11.8A(RMS)/12.9A(Peak) U25
U27
PCIE_VSS#24 GND#24
B6
B8
VDD_CT#3 CORE VDDC#1 PCIE_VSS#25 GND#25
AB21 N15 V32 C1

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 VDD_CT#4 VDDC#2 PCIE_VSS#26 GND#26

C413

C414

C415

C416

C417

C418

C419

C420

C423

C424

C425

C426
N17 1 1 1 1 1 1 1 1 1 1 1 1 W25 C32
VDDC#3 PCIE_VSS#27 GND#27
R13 W26 E28
I/O VDDC#4 PCIE_VSS#28 GND#28
R16 W27 F10
VDDC#5 PCIE_VSS#29 GND#29
60mA AA17
VDDR3#1 VDDC#6
R18 Y25
PCIE_VSS#30 GND#30
F12
AA18 Y21 2 2 2 2 2 2 2 2 2 2 2 2 Y32 F14
VDDR3#2 VDDC#7 PCIE_VSS#31 GND#31
AB17 T12 F16
VDDR3#3 VDDC#8 GND#32
AB18 T15 F18
L24 VDDR3#4 VDDC#9 GND#33
T17 F2
VDDC#10 GND#34
1 2 170mA V12
VDDR4#1 VDDC#11
T20
GND#35
F20
BLM15BD121SN1D_0402 Y12 U13 M6 F22
0.1U_0402_10V6K
1U_0402_6.3V4Z

VDDR4#2 VDDC#12 GND#56 GND#36

C U12 U16 N11 F24 C
VDDR4#3 VDDC#13 GND#57 GND#37

POWER
C429

C430

Change to 0 ohm 1 1 VDDC#14

U18 7/22 modify N12
GND#58 GND#38
F26
AA11 V21 N13 F6
P/N NC#1 VDDC#15 GND#59 GND#39
AA12 V15 N16 F8
2 2 V11
NC#2

NC#3
VDDC#16
VDDC#17
VDDC#18
V17
V20
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
U11 Y13 P6 G31
NC#4 VDDC#19 GND#63 GND#43
Y16 P9 G8
VDDC#20 GND#64 GND#44
Y18 R12 H14
VDDC#21 GND#65 GND#45
M11 R15 H17
L25 VDDC#22 GND#66 GND#46
M12 R17 H2
MEM CLK VDDC#23 GND#67 GND#47
1 2 R20 H20
BLM15BD121SN1D_0402 GND#68 GND#48
L17 T13 H6
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K

NC_VDDRHA GND#69 GND#49

C446

C447

C449

1 1 1 T16 J27
+BIF_VDDC GND#70 GND#50
L16 T18 J31
+1.8VGS NC_VSSRHA GND#71 GND#51
T21 K11
GND#72 GND#52
T6 K2

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 PLL GND#73 GND#53

C451

C452
For Seymour, PCIE_PVDD is PCIE_VDDR. 1 1 U15 K22
GND#74 GND#54
AM30 U17 K6
PCIE_PVDD GND#75 GND#55
R21 U20
BIF_VDDC#1 GND#76
U21 U9
+MPV18 BIF_VDDC#2 2 2 GND#77
75mA L8 NC_MPV18
V13
GND#78
V16
L26 GND#79
V18
+SPV18 GND#80
1 2 75mA H7 SPV18
Y10
GND#81
BLM15BD121SN1D_0402 ISOLATED Y15
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

+SPV10 CORE I/O GND#82

C453

C454

C455

1 1 1 120mAH8 SPV10 VDDCI#1

M13 Y17
GND#83 VSS_MECH#1
A32
M15 +VDDCI R745 +VGA_CORE Y20 AM1
+1.0VGS VDDCI#2 0_0603_5% GND#84 VSS_MECH#2
J7 M16 R11 AM32
L28 SPVSS VDDCI#3 GND#85 VSS_MECH#3
M17 1 2 T11
2 2 2 VDDCI#4 GND#86
1 2 M18

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDCI#5

C459

C460

C461

C466
BLM15BD121SN1D_0402 M20 1 1 1 1
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

VDDCI#6
C456

C457

C458

1 1 1 M21
VDDCI#7
N20
VDDCI#8 216-0774207-A11ROB_FCBGA631
2 2 2 2
2 2 2

B B
216-0774207-A11ROB_FCBGA631

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
RobsonXT-S3 PWR/GND

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 28 of 59
5 4 3 2 1
 5 4 3 2 1

U8C +1.8VGS
M_DA[63..0]
<30> M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3 R357 1 X76@ 2 10K_0402_5% VRAM_ID0
M_MA[13..0] VRAM_ID0 <24>
M_DA0 K27 K17 M_MA0 R358 1 X76@ 2 10K_0402_5%
<30> M_MA[13..0] DQA0_0/DQA_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1 R359 1 X76@ 2 10K_0402_5% VRAM_ID1
M_DQM[7..0] DQA0_1/DQA_1 MAA0_1/MAA_1 VRAM_ID1 <24>
M_DA2 H30 H23 M_MA2 R360 1 X76@ 2 10K_0402_5%
<30> M_DQM[7..0] DQA0_2/DQA_2 MAA0_2/MAA_2
M_DA3 H32 G23 M_MA3 R361 1 X76@ 2 10K_0402_5% VRAM_ID2
M_DQS[7..0] DQA0_3/DQA_3 MAA0_3/MAA_3 VRAM_ID2 <24>
M_DA4 G29 G24 M_MA4 R362 1 X76@ 2 10K_0402_5%
<30> M_DQS[7..0] DQA0_4/DQA_4 MAA0_4/MAA_4

MEMORY INTERFACE
M_DA5 F28 H24 M_MA5
M_DQS#[7..0] M_DA6 DQA0_5/DQA_5 MAA0_5/MAA_5 M_MA6
<30> M_DQS#[7..0] F32 DQA0_6/DQA_6 MAA0_6/MAA0_6 J19
M_DA7 F30 K19 M_MA7
D M_DA8 DQA0_7/DQA_7 MAA0_7/MAA0_7 M_MA8 D
C30 DQA0_8/DQA_8 MAA1_0/MAA_8 J14
M_DA9 F27 K14 M_MA9
M_DA10 DQA0_9/DQA_9 MAA1_1/MAA_9 M_MA10
A28 DQA0_10/DQA_10 MAA1_2/MAA_10 J11
M_DA11 C28 J13 M_MA11 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
M_DA12 DQA0_11/DQA_11 MAA1_3/MAA_11 M_MA12
E27 DQA0_12/DQA_12 MAA1_4/MAA_12 H11
M_DA13 G26 G11 M_BA2
DQA0_13/DQA_13 MAA1_5/MAA_13/BA2 M_BA2 <30>
M_DA14 D26 J16 M_BA0 Hynix 512MB
DQA0_14/DQA_14 MAA1_6/MAA_14/BA0 M_BA0 <30>
M_DA15 F25 L15 M_BA1 R357 R360 R362
DQA0_15/DQA_15 MAA1_7/MAA_15/BA1 M_BA1 <30> PN:SA000032460
M_DA16 A25
M_DA17 DQA0_16/DQA_16 M_DQM0
C25 DQA0_17/DQA_17 WCKA0_0/DQMA_0 E32
M_DA18 E25 E30 M_DQM1 Samsung 512MB
M_DA19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 M_DQM2
M_DA20
D24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 A21
M_DQM3 PN:SA000035700 R358 R359 R362
E23 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C21
M_DA21 F23 E13 M_DQM4
M_DA22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 M_DQM5
M_DA23
D22 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 D12
M_DQM6
Hynix 1GB
M_DA24
F21 DQA0_23/DQA_23 WCKA1_1/DQMA_6 E3
M_DQM7 PN:SA00003VS20 R357 R360 R361
E21 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 F4
M_DA25 D20
M_DA26 DQA0_25/DQA_25 M_DQS0
M_DA27
F19 DQA0_26/DQA_26 EDCA0_0/RDQSA_0 H28
M_DQS1
Samsung 1GB
M_DA28
A19 DQA0_27/DQA_27 EDCA0_1/RDQSA_1 C27
M_DQS2 PN:SA00003MQ20 R358 R359 R361
D18 DQA0_28/DQA_28 EDCA0_2/RDQSA_2 A23
M_DA29 F17 E19 M_DQS3
M_DA30 DQA0_29/DQA_29 EDCA0_3/RDQSA_3 M_DQS4
A17 DQA0_30/DQA_30 EDCA1_0/RDQSA_4 E15
C
M_DA31 C17 D10 M_DQS5 C
+1.5VGS M_DA32 DQA0_31/DQA_31 EDCA1_1/RDQSA_5 M_DQS6
E17 DQA1_0/DQA_32 EDCA1_2/RDQSA_6 D6
+1.5VGS M_DA33 D16 G5 M_DQS7
M_DA34 DQA1_1/DQA_33 EDCA1_3/RDQSA_7
F15 DQA1_2/DQA_34
1

M_DA35 A15 H27 M_DQS#0

DQA1_3/DQA_35 DDBIA0_0/WDQSA_0
1

R365 M_DA36 D14 A27 M_DQS#1

R363 40.2_0402_1% M_DA37 DQA1_4/DQA_36 DDBIA0_1/WDQSA_1 M_DQS#2
F13 DQA1_5/DQA_37 DDBIA0_2/WDQSA_2 C23
40.2_0402_1% M_DA38 A13 C19 M_DQS#3
M_DA39 DQA1_6/DQA_38 DDBIA0_3/WDQSA_3 M_DQS#4
C13 C15
2

M_DA40 DQA1_7/DQA_39 DDBIA1_0/WDQSA_4 M_DQS#5

E11 E9
2

MVREFDA MVREFSA M_DA41 DQA1_8/DQA_40 DDBIA1_1/WDQSA_5 M_DQS#6

A11 DQA1_9/DQA_41 DDBIA1_2/WDQSA_6 C5
M_DA42 C11 H4 M_DQS#7
DQA1_10/DQA_42 DDBIA1_3/WDQSA_7
1

1 1 M_DA43 F11
R364 C467 R367 C468 M_DA44 DQA1_11/DQA_43 VRAM_ODT0
A9 DQA1_12/DQA_44 ADBIA0/ODTA0 L18 VRAM_ODT0 <30>
100_0402_1% 0.1U_0402_16V4Z 100_0402_1% 0.1U_0402_16V4Z M_DA45 C9 K16 VRAM_ODT1
DQA1_13/DQA_45 ADBIA1/ODTA1 VRAM_ODT1 <30>
M_DA46 F9
2 2 M_DA47 DQA1_14/DQA_46 M_CLK0
D8 H26 M_CLK0 <30>
2

M_DA48 DQA1_15/DQA_47 CLKA0 M_CLK#0

E7 DQA1_16/DQA_48 CLKA0B H25 M_CLK#0 <30>
M_DA49 A7
M_DA50 DQA1_17/DQA_49 M_CLK1
C7 DQA1_18/DQA_50 CLKA1 G9 M_CLK1 <30>
M_DA51 F7 H9 M_CLK#1
DQA1_19/DQA_51 CLKA1B M_CLK#1 <30>
M_DA52 A5
M_DA53 DQA1_20/DQA_52 M_RAS#0
PARK SCL has different M_DA54
E5 DQA1_21/DQA_53 RASA0B G22
M_RAS#1
M_RAS#0 <30>
C3 DQA1_22/DQA_54 RASA1B G17 M_RAS#1 <30>
B recommand 9/28 change P/N to SD034100A80 M_DA55 E1 B
M_DA56 DQA1_23/DQA_55 M_CAS#0
G7 DQA1_24/DQA_56 CASA0B G19 M_CAS#0 <30>
R369 M_DA57 G6 G16 M_CAS#1
DQA1_25/DQA_57 CASA1B M_CAS#1 <30>
R366 10_0402_1% M_DA58 G1
DRAM_RST M_DA59 DQA1_26/DQA_58 M_CS#0
<30> DRAM_RST# 2 1 2 1 G3 DQA1_27/DQA_59 CSA0B_0 H22 M_CS#0 <30>
M_DA60 J6 J22
49.9_0402_1% M_DA61 DQA1_28/DQA_60 CSA0B_1
J1 DQA1_29/DQA_61
1

1 M_DA62 J3 G13 M_CS#1

DQA1_30/DQA_62 CSA1B_0 M_CS#1 <30>
C469 R371 M_DA63 J5 K13
120P_0402_50V8J 4.99K_0402_1% DQA1_31/DQA_63 CSA1B_1
MVREFDA K26 K20 M_CKE0
2 +1.5VGS MVREFDA CKEA0 M_CKE0 <30>
MVREFSA J26 J17 M_CKE1
M_CKE1 <30>
2

R368 MVREFSA CKEA1

1 243_0402_1%
2 J25 G25 M_WE#0
MEM_CALRN0 WEA0B M_WE#0 <30>
1 2 K25 H10 M_WE#1
MEM_CALRP0 WEA1B M_WE#1 <30>
R370
243_0402_1%
MAA1_8 G14
GDDR5 G20 M_MA13
DRAM_RST L10 MAA0_8
DRAM_RST
1R372@ 51.1_0402_1%
2 1C470@20.1U_0402_16V4Z K8 CLKTESTA
1 2 1 2 L7 CLKTESTB
R373@ 51.1_0402_1% C471@ 0.1U_0402_16V4Z
A A

Route 50ohms single-ended/100ohm diff and keep short 216-0774207-A11ROB_FCBGA631

debug only, for clock observation,if not need, Security Classification Compal Secret Data Compal Electronics, Inc.
DNI. Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 29 of 59
5 4 3 2 1

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 5 4 3 2 1

M_DA[63..0]
<29> M_DA[63..0]
M_MA[13..0]
<29> M_MA[13..0]
M_DQM[7..0]
<29> M_DQM[7..0]
M_DQS[7..0]
<29> M_DQS[7..0]
M_DQS#[7..0]
<29> M_DQS#[7..0]

U19 U20 U18 U21

VREFC_A1 M9 E4 M_DA22 VREFC_A2 M9 E4 M_DA25 VREFC_A3 M9 E4 M_DA35 VREFC_A4 M9 E4 M_DA52

VREFD_Q1 VREFCA DQL0 M_DA20 VREFD_Q2 VREFCA DQL0 M_DA28 VREFD_Q3 VREFCA DQL0 M_DA34 VREFD_Q4 VREFCA DQL0 M_DA48
H2 F8 H2 F8 H2 F8 H2 F8
ZZZ ZZZ VREFDQ DQL1 M_DA19 VREFDQ DQL1 M_DA27 VREFDQ DQL1 M_DA36 VREFDQ DQL1 M_DA54
F3 F3 F3 F3
D
M_MA0 DQL2 M_DA18 M_MA0 DQL2 M_DA31 M_MA0 DQL2 M_DA37 M_MA0 DQL2 M_DA50 D
N4 F9 N4 F9 N4 F9 N4 F9
M_MA1 A0 DQL3 M_DA21 M_MA1 A0 DQL3 M_DA24 M_MA1 A0 DQL3 M_DA32 M_MA1 A0 DQL3 M_DA53
P8 H4 P8 H4 P8 H4 P8 H4
M_MA2 A1 DQL4 M_DA17 M_MA2 A1 DQL4 M_DA29 M_MA2 A1 DQL4 M_DA38 M_MA2 A1 DQL4 M_DA49
P4 H9 P4 H9 P4 H9 P4 H9
M_MA3 A2 DQL5 M_DA23 M_MA3 A2 DQL5 M_DA26 M_MA3 A2 DQL5 M_DA33 M_MA3 A2 DQL5 M_DA55
N3 G3 N3 G3 N3 G3 N3 G3
M_MA4 A3 DQL6 M_DA16 M_MA4 A3 DQL6 M_DA30 M_MA4 A3 DQL6 M_DA39 M_MA4 A3 DQL6 M_DA51
P9 H8 P9 H8 P9 H8 P9 H8
M_MA5 A4 DQL7 M_MA5 A4 DQL7 M_MA5 A4 DQL7 M_MA5 A4 DQL7
Hynix Samsung P3
A5
P3
A5
P3
A5
P3
A5
H1G@ S1G@ M_MA6 R9 M_MA6 R9 M_MA6 R9 M_MA6 R9
X7624938L01 X7624938L02 M_MA7 A6 M_DA3 M_MA7 A6 M_DA14 M_MA7 A6 M_DA47 M_MA7 A6 M_DA60
R3 D8 R3 D8 R3 D8 R3 D8
M_MA8 A7 DQU0 M_DA1 M_MA8 A7 DQU0 M_DA10 M_MA8 A7 DQU0 M_DA42 M_MA8 A7 DQU0 M_DA58
T9 C4 T9 C4 T9 C4 T9 C4
M_MA9 A8 DQU1 M_DA0 M_MA9 A8 DQU1 M_DA15 M_MA9 A8 DQU1 M_DA45 M_MA9 A8 DQU1 M_DA56
0706 update M_MA10
R4
A9 DQU2
C9
M_DA5 M_MA10
R4
A9 DQU2
C9
M_DA11 M_MA10
R4
A9 DQU2
C9
M_DA41 M_MA10
R4
A9 DQU2
C9
M_DA61
L8 C3 L8 C3 L8 C3 L8 C3
M_MA11 A10/AP DQU3 M_DA6 M_MA11 A10/AP DQU3 M_DA12 M_MA11 A10/AP DQU3 M_DA43 M_MA11 A10/AP DQU3 M_DA63
update X76 PN M_MA12
R8
A11 DQU4
A8
M_DA7 M_MA12
R8
A11 DQU4
A8
M_DA8 M_MA12
R8
A11 DQU4
A8
M_DA40 M_MA12
R8
A11 DQU4
A8
M_DA62
N8 A3 N8 A3 N8 A3 N8 A3
M_MA13 A12 DQU5 M_DA2 M_MA13 A12 DQU5 M_DA13 M_MA13 A12 DQU5 M_DA46 M_MA13 A12 DQU5 M_DA57
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 M_DA4 A13 DQU6 M_DA9 A13 DQU6 M_DA44 A13 DQU6 M_DA59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
ZZZ ZZZ A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS

M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3

<29> M_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10
<29> M_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8
<29> M_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
Hynix Samsung VDD
K9
VDD
K9
VDD
K9
VDD
K9
H512@ S512@ N2 N2 N2 N2
X7624938L03 X7624938L04 M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
<29> M_CLK0 J8 N10 J8 N10 <29> M_CLK1 J8 N10 J8 N10
M_CLK#0 K8 CK VDD M_CLK#0 CK VDD M_CLK#1 K8 CK VDD M_CLK#1 CK VDD
<29> M_CLK#0 R2 K8 R2 <29> M_CLK#1 R2 K8 R2
M_CKE0 K10 CK VDD M_CKE0 CK VDD M_CKE1 K10 CK VDD M_CKE1 CK VDD
<29> M_CKE0 R10 K10 R10 <29> M_CKE1 R10 K10 R10
CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS

VRAM_ODT0K2 A2 VRAM_ODT0 K2 A2 VRAM_ODT1K2 A2 VRAM_ODT1 K2 A2

<29> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <29> VRAM_ODT1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L3 A9 M_CS#0 L3 A9 M_CS#1 L3 A9 M_CS#1 L3 A9
<29> M_CS#0 CS VDDQ CS VDDQ <29> M_CS#1 CS VDDQ CS VDDQ
M_RAS#0 J4 C2 M_RAS#0 J4 C2 M_RAS#1 J4 C2 M_RAS#1 J4 C2
<29> M_RAS#0 RAS VDDQ RAS VDDQ <29> M_RAS#1 RAS VDDQ RAS VDDQ
M_CAS#0 K4 C10 M_CAS#0 K4 C10 M_CAS#1 K4 C10 M_CAS#1 K4 C10
<29> M_CAS#0 CAS VDDQ CAS VDDQ <29> M_CAS#1 CAS VDDQ CAS VDDQ
M_WE#0 L4 D3 M_WE#0 L4 D3 M_WE#1 L4 D3 M_WE#1 L4 D3
<29> M_WE#0 WE VDDQ WE VDDQ <29> M_WE#1 WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
M_DQS2 VDDQ M_DQS3 VDDQ M_DQS4 VDDQ M_DQS6 VDDQ
F4 H3 F4 H3 F4 H3 F4 H3
M_DQS0 DQSL VDDQ M_DQS1 DQSL VDDQ M_DQS5 DQSL VDDQ M_DQS7 DQSL VDDQ
C C8 H10 C8 H10 C8 H10 C8 H10 C
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

M_DQM2 E8 A10 M_DQM3 E8 A10 M_DQM4 E8 A10 M_DQM6 E8 A10

M_DQM0 DML VSS M_DQM1 DML VSS M_DQM5 DML VSS M_DQM7 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
DMU VSS DMU VSS DMU VSS DMU VSS
E2 E2 E2 E2
VSS VSS VSS VSS
G9 G9 G9 G9
M_DQS#2 VSS M_DQS#3 VSS M_DQS#4 VSS M_DQS#6 VSS
G4 J3 G4 J3 G4 J3 G4 J3
M_DQS#0 DQSL VSS M_DQS#1 DQSL VSS M_DQS#5 DQSL VSS M_DQS#7 DQSL VSS
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS
<29> DRAM_RST# T3 P10 P10 P10 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 B2 J2 B2 J2 B2 J2 B2
R374 NC/ODT1 VSSQ R375 NC/ODT1 VSSQ R376 NC/ODT1 VSSQ R377 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J10 D2 J10 D2 J10 D2 J10 D2
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA
X76@ X76@ X76@ X76@

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

B B
1

1
R378 R379 R380 R381 R382 R383 R384 R385
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2

2
VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1

1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C472

C473

C474

C475

C476

C477

C478

C479
1 1 1 1 1 1 1 1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R386 R387 R388 R389 R390 R391 R392 R393
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 2 2 2
2

2
M_CLK0 1 2
R394 56_0402_1%

M_CLK#0 1 2 +1.5VGS
R396 56_0402_1% +1.5VGS
1 1U_0402_6.3V4Z 1U_0402_6.3V4Z
C506 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
0.01U_0402_16V7K +1.5VGS 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C500

C501

C484

C485

C486

C502

C503

C504

C505

C487
1 1 1 1 1 1 1 1 1 1
C492

C482

C483

C493

C494

C495

C496

C497

C498

C499
C488 C489 C490 C480 C491 C481
2 2 2 2 2 2 @ 2 2 2 2 2 2 2 2 @ 2 2 @
10U_0603_6.3V6M 10U_0603_6.3V6M10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
M_CLK1 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R395 56_0402_1%
A A

M_CLK#1 1 2
R397 56_0402_1% 1
C507
0.01U_0402_16V7K
2
ref 139-02 recommand VRAM P/N :
add off page Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! ) Security Classification Compal Secret Data Compal Electronics, Inc.
Park SCL recommand pu 60.4 ohm to Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! ) Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

1.5VGS
0619 update update VRAM PN 0619 update RobsonXT-S3 VRAM

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 30 of 59
5 4 3 2 1
 5 4 3 2 1

INVPWM
+LEDVDD B+

1 R398 2 0_0805_5%

470P_0402_50V7K

470P_0402_50V7K
DISPOFF# 1 1
C508
C509 680P_0402_50V7K C512
1 1 @ 4.7U_0805_25V6-K
C511 2 2
LCD POWER CIRCUIT JLVDS1
+3VS_CMOS
2 2 2
2 1 1 USB20_N5
+LCDVDD +5VALW
4
4 3 3 USB20_P5
USB20_N5 <18> CMOS
D
For EMI +LCDVDD_CONN
(60 MIL) 6
6 5 5 USB20_P5 <18>
D
8
8 7 7 CONN_LVDS_A0#
10
+3VS 10 9 9 CONN_LVDS_A0
W=60mils 12
12 11 11
14
+3VS 14 13 13

1
R400 R401 16 CONN_LVDS_A1#
150_0603_1% 100K_0402_5% Change footprint
1
C513 @ <40> CE_EN INVPWM 16 15 15 CONN_LVDS_A1
1 2 18
20100814 4.7U_0603_6.3V6K 680P_0402_50V7K 1 <40> INVT_PWM
0_0402_5% DIS@ DISPOFF# 18 17 17
20
C514 R402 20 19 19 CONN_LVDS_A2#
22
2 Change footprint 22 21 21 CONN_LVDS_A2
24
23 23

2
24

3
D R403 220K_0402_5% Q80 20100814 2 @ 26
2N7002H_SOT23-3 R404 2.2K_0402_5% CONN_LVDS_SCL 26 25 25 CONN_LVDS_ACLK#
2 1 2 2 +3VS 28
28 27 27
Q79 G R405 2.2K_0402_5% CONN_LVDS_SDA 30 CONN_LVDS_ACLK
@ 30 29 29
S 1

1
Change footprint DTC124EK C515 AP2301GN-HF_SOT23-3 32 31
20100814 GNDGND
W=60mils Pull high at chipset/VGA side

OUT

1
0.1U_0402_16V4Z ACES_87142-3041-BS
2 +LCDVDD +LCDVDD_CONN ME@
L29
<17> PCH_ENVDD R406 2 1 0_0402_5% LCD_ENVDD 2
PX@ IN
1 2

GND
Q81 FBMA-L11-201209-221LMA30T_0805
1

<23> VGA_ENVDD R407 2 1 0_0402_5% DTC124EKAT146_SC59-3 C516 1 1

3
DIS@ C517
R408 @ 4.7U_0603_6.3V6K <24> VGA_LVDS_SCL VGA_LVDS_SCL 0_0402_5% 2 DIS@ 1 R409 CONN_LVDS_SCL
100K_0402_5% 0.1U_0402_16V4Z <24> VGA_LVDS_SDA VGA_LVDS_SDA 0_0402_5% 2 DIS@ 1 R410 CONN_LVDS_SDA
2 2
2

Change footprint VGA_LVDS_A0 0_0402_5% 2 DIS@ 1 R411 CONN_LVDS_A0

20100814 <23> VGA_LVDS_A0 VGA_LVDS_A0# 0_0402_5% CONN_LVDS_A0#
<23> VGA_LVDS_A0# 2 DIS@ 1 R412

VGA_LVDS_A1 0_0402_5% 2 DIS@ 1 R413 CONN_LVDS_A1

<23> VGA_LVDS_A1 VGA_LVDS_A1# 0_0402_5% CONN_LVDS_A1#
<23> VGA_LVDS_A1# 2 DIS@ 1 R414
C VGA_LVDS_A2 0_0402_5% CONN_LVDS_A2 C
<23> VGA_LVDS_A2 2 DIS@ 1 R415
VGA_LVDS_A2# 0_0402_5% 2 DIS@ 1 R416 CONN_LVDS_A2#
<23> VGA_LVDS_A2#
VGA_LVDS_ACLK 0_0402_5% 2 DIS@ 1 R417 CONN_LVDS_ACLK
<23> VGA_LVDS_ACLK VGA_LVDS_ACLK#0_0402_5% CONN_LVDS_ACLK#
<23> VGA_LVDS_ACLK# 2 DIS@ 1 R418

<17> EDID_CLK EDID_CLK 0_0402_5% 2 PX@ 1 R419 CONN_LVDS_SCL

<17> EDID_DATA EDID_DATA 0_0402_5% 2 PX@ 1 R420 CONN_LVDS_SDA

LVDS_A0 0_0402_5% 2 PX@ 1 R421 CONN_LVDS_A0

+3VS <17> LVDS_A0 LVDS_A0# CONN_LVDS_A0#
0_0402_5% 2 PX@ 1 R422
<17> LVDS_A0#
LVDS_A1 0_0402_5% 2 PX@ 1 R423 CONN_LVDS_A1
<17> LVDS_A1 LVDS_A1# CONN_LVDS_A1#
0_0402_5% 2 PX@ 1 R424
U22 <17> LVDS_A1#
5

1 LVDS_A2 0_0402_5% 2 PX@ 1 R425 CONN_LVDS_A2

P

NC <17> LVDS_A2
2 4 INVPWM LVDS_A2# 0_0402_5% 2 PX@ 1 R427 CONN_LVDS_A2#
<17> PCH_PWM A Y <17> LVDS_A2#
G

LVDS_ACLK 0_0402_5% 2 PX@ 1 R428 CONN_LVDS_ACLK

<17> LVDS_ACLK LVDS_ACLK# CONN_LVDS_ACLK#
TC7SZ14FU_SSOP5 0_0402_5% 2 PX@ 1 R429
3

<17> LVDS_ACLK#
@

PX@
1 R430 2
2
G

0_0402_5%

3 1 INVPWM 2 R431 1 +3VS

10K_0402_5% @
S

B B
2N7002H_SOT23-3 Change footprint
@ Q82 20100814

For GMCH DPST

(20 MIL)
R539
CMOS Camera Conn (20 MIL)
0_0603_5%
@ 1 2 Change footprint
+5VS
R596 20100814 +CMOS_PW +3VS_CMOS
0_0603_5%
+3VS 1 2 3 1
+3VS
1 1
CMOS@ Q83 CMOS@ CMOS@
1

R717 0_0402_5% C518 C519

1 2 R433 @ +5VALW AP2301GN-HF_SOT23-3 0.1U_0402_16V4Z 10U_0805_10V4Z

2
R434 100K_0402_5% 2 2
4.7K_0402_5% 4.7V
D4
1
2

BKOFF# 1 2 DISPOFF# CMOS@ R435 CMOS@

<40> BKOFF#

1
150K_0402_5% C520
@ CH751H-40PT_SOD323-2 R543 CMOS@ 0.1U_0402_16V4Z
1

2
0_0402_5%

1
R716 @
10K_0402_5%

OUT
2
2

<40> CMOS_OFF# 2
IN

GND
Q84
A DTC124EKAT146_SC59-3 A

3
R436 DIS@ 0_0402_5% CMOS@
<24> VGA_ENBKL 1 2 ENBKL <40>
PX@
<17> PCH_ENBKL R437 1 2 0_0402_5%
2

R438
100K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
LVDS/CAMERA
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 31 of 59
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS +5VS +5VS

3 3 3 3 3

1 BLUE 1 GREEN 1 RED 1 JVGA_HS 1 JVGA_VS

2 2 2 BAT54S-7-F_SOT23-3 2 2
@ @ @ @ @
D5 D6 D7 D8 D9
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

1 UMA only +5VS

D10
+CRT_VCC
CRT Connector
F1
1

2 1 1 2
1
DAC_RED 1 2 CRT_R RB491D_SC59-3
<17> DAC_RED
R439 PX@ 0_0402_5% 1.1A_6V_SMD1812P110TF C521
DAC_GRN 1 2 CRT_G
<17> DAC_GRN
R440 PX@ 0_0402_5% FCM1608CF-121T03 0603 W=40mils 2
0.1U_0402_16V4Z

DAC_BLU 1 2 CRT_B CRT_R 1 2 RED

<17> DAC_BLU
R441 PX@ 0_0402_5% L30
FCM1608CF-121T03 0603
CRT_G 1 2 GREEN
L31
DIS only FCM1608CF-121T03 0603 JCRT1
CRT_B 1 2 BLUE T67 PAD 6
L32 @ 11

1
VGA_CRT_R 1 2 CRT_R 1 1 1 1 1 1 RED 1
<24> VGA_CRT_R
R442 DIS@ 0_0402_5% 7
VGA_CRT_G 1 2 CRT_G R445 R443 R446 C522 C523 C524 C525 C526 C527 CRT_DDC_DAT_CONN 12
<24> VGA_CRT_G
R444 DIS@ 0_0402_5% 150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J GREEN 2
VGA_CRT_B CRT_B 2 2 2 2 2 2
<24> VGA_CRT_B 1 2 8 G 16

2
R447 DIS@ 0_0402_5% JVGA_HS 13 17
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J BLUE G
3
CLOSE TO CONN 9
JVGA_VS 14
4
10
CRT_DDC_CLK_CONN 15
2 5 2
+CRT_VCC 1
R448
C528 CONTE_80431-5K1-152
1 2
1 100P_0402_50V8J ME@
2
C529 1K_0402_5%
0.1U_0402_16V4Z
2

1
PX@ FCM1608CF-121T03 0603

OE#
P
R449 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC A Y L33
Check CRT footprint 7/20_OTIS

G
DIS@ U23
R450 1 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5 1
<24> VGA_HSYNC

3
@
C530
10P_0402_50V8J
+CRT_VCC 2
R451
1 2
1
C531 1K_0402_5%
0.1U_0402_16V4Z
2
5

1
PX@ FCM1608CF-121T03 0603
OE#
P
R4521 2 0_0402_5% VSYNC_G 2 4 CRT_VSYNC_1 1 2 JVGA_VS
3 <17> CRT_VSYNC A Y 3
L34
G

DIS@ U24 1
R4531 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5
<24> VGA_VSYNC
3

@ C532
10P_0402_50V8J
2

+3VS +3VGS
7/21 modify
2

R736 R735
+3VS 0_0402_5% 0_0402_5% +CRT_VCC
Pull high at chipset/VGA side PX@ DIS@
1

1
1

1
@ @
R454 R455
2.2K_0402_5% 2.2K_0402_5% R456 R457
5

2.2K_0402_5% 2.2K_0402_5%
2

<17> CRT_DDC_DATA CRT_DDC_DATA 2 PX@ 1 CRT_DDC_DATA_R 4 3 CRT_DDC_DAT_CONN

R458 0_0402_5%
<24> VGA_DDCDATA VGA_DDCDATA 2 DIS@ 1 2N7002DW -T/R7_SOT363-6
2

R459 0_0402_5% Q62B

<17> CRT_DDC_CLK CRT_DDC_CLK 2 PX@ 1 CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN

R460 0_0402_5% 1 1
4 <24> VGA_DDCCLK VGA_DDCCLK 2 DIS@ 1 2N7002DW -T/R7_SOT363-6 @ 4
R461 0_0402_5% Q62A C533 C534
100P_0402_50V8J 68P_0402_50V8K
2 2

8/14 change P/N to

DMN66D0LDW-7_SOT363-6
(SB00000DH00)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 32 of 59
A B C D E
 5 4 3 2 1

HDMI_CLK+_CONN 1 2 @ L35
R462 UMA_HDMI@ 680_0402_1% HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN
HDMI_CLK-_CONN 1 2
1 2
R463 UMA_HDMI@ 680_0402_1% <17> HDMI_CLK+_CK HDMI_CLK+_CK HDMI@ R464 1 2 0_0402_5% HDMI_CLK+_CONN
<17> HDMI_CLK-_CK HDMI_CLK-_CK HDMI@ R465 1 2 0_0402_5% HDMI_CLK-_CONN HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN
HDMI_TX0+_CONN HDMI_TX0+_CK HDMI@ R466 0_0402_5% HDMI_TX0+_CONN 4 3
1 2 <17> HDMI_TX0+_CK 1 2
R472 UMA_HDMI@ 680_0402_1% <17> HDMI_TX0-_CK HDMI_TX0-_CK HDMI@ R467 1 2 0_0402_5% HDMI_TX0-_CONN W CM-2012-900T_4P
HDMI_TX0-_CONN 1 2 <17> HDMI_TX1+_CK HDMI_TX1+_CK HDMI@ R468 1 2 0_0402_5% HDMI_TX1+_CONN
R473 UMA_HDMI@ 680_0402_1% <17> HDMI_TX1-_CK HDMI_TX1-_CK HDMI@ R469 1 2 0_0402_5% HDMI_TX1-_CONN @ L36
D <17> HDMI_TX2+_CK HDMI_TX2+_CK HDMI@ R470 1 2 0_0402_5% HDMI_TX2+_CONN HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN D
HDMI_TX1+_CONN HDMI_TX2-_CK HDMI@ R471 0_0402_5% HDMI_TX2-_CONN 1 2
1 2 <17> HDMI_TX2-_CK 1 2
R474 UMA_HDMI@ 680_0402_1%
HDMI_TX1-_CONN 1 2 HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN
R475 UMA_HDMI@ 680_0402_1% C535 DIS_HDMI@ 0.1U_0402_16V7K HDMI_CLK+_CK 4 3
<24> VGA_HDMI_CLK+ 1 2
C536 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_CLK-_CK W CM-2012-900T_4P
<24> VGA_HDMI_CLK-
HDMI_TX2+_CONN 1 2 C537 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX0+_CK
<24> VGA_HDMI_TX0+
R476 UMA_HDMI@ 680_0402_1% C538 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX0-_CK @ L37
<24> VGA_HDMI_TX0-
HDMI_TX2-_CONN 1 2 C539 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN
<24> VGA_HDMI_TX1+ 1 2
R477 UMA_HDMI@ 680_0402_1% C540 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX1-_CK
<24> VGA_HDMI_TX1-
2N7002H_SOT23-3 C541 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX2+_CK
<24> VGA_HDMI_TX2+

1
D UMA_HDMI@ C542 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX2-_CK HDMI_TX1-_CK HDMI_TX1-_CONN
<24> VGA_HDMI_TX2- 1 2 4 4 3 3
2 +3VS
Q95 G W CM-2012-900T_4P
S Change footprint

3
20100814 @ L38
+3VS +3VGS HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN
1 2
8/6 Modify
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN
4 3

2
R738 R739 W CM-2012-900T_4P
0_0402_5% 0_0402_5%
UMA_HDMI@ DIS_HDMI@

1
C +5VS +5VS C
Pull up R for PCH OR VGA SIDE

2
HDMI@ 3 3

<17> HDMICLK_NB R478 1 2 0_0402_5% 1 6 HDMICLK_R 1 HDMIDAT_R 1 HDMICLK_R

UMA_HDMI@

5
<24> VGA_HDMI_SCL R479 1 2 0_0402_5% HDMI@ 2N7002DW -T/R7_SOT363-6 2 @ 2 @
DIS_HDMI@ Q63A D11 D12
<17> HDMIDAT_NB R480 1 2 0_0402_5% 4 3 HDMIDAT_R BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
UMA_HDMI@
<24> VGA_HDMI_SDA R481 1 2 0_0402_5% Q63B 2N7002DW -T/R7_SOT363-6
DIS_HDMI@
RB491D_SC59-3 D13 F2
+5VS 2 1 +5VS_HDMI_F 1 2
8/14 change P/N to
1.1A_6V_SMD1812P110TF
DMN66D0LDW-7_SOT363-6 HDMI@ HDMI@
(SB00000DH00)
R482 9/27 add F2 for safty
0_0805_5%
@

+5VS_HDMI
+3VS
1 C543
+5VS 0.1U_0402_16V4Z

2
B HDMI@ B
2

2
R485 R483 R484 2
1M_0402_5% 2.2K_0402_5% 2.2K_0402_5%
UMA_HDMI@ HDMI@ HDMI@

1
2
G
1

TMDS_B_HPD# 3 1 R486 1 2 0_0402_5% @

<17> TMDS_B_HPD#

1
UMA_HDMI@ D14
S

Change footprint BAT54S-7-F_SOT23-3 JHDMI1

2N7002H_SOT23-3 20100814 HDMI_DET 19 HP_DET
Q93 18 +5V
2

UMA_HDMI@ 17
R696 +3VS HDMIDAT_R DDC/CEC_GND
16 SDA
0_0402_5% HDMICLK_R 15 SCL

2
@ 14 Reserved
R697 DIS_HDMI@ 13
1

CEC
1

C 150K_0402_5% R488 HDMI_CLK-_CONN 12 20

Q28 DIS_HDMI@ 100K_0402_5% CK- G1
2 1 2 11 CK_shield G2 21
MMBT3904_G_SOT23-3 B 1 HDMI_CLK+_CONN 10 22
E HDMI@ HDMI_TX0-_CONN CK+ G3
9 23
3

D0- G4
<24> HDMI_DETECT_VGA 8 D0_shield
HDMI_CLK+_CONN 1 2 HDMI_TX0+_CONN 7 D0+
1

R489 DIS_HDMI@
499_0402_1% HDMI_TX1-_CONN 6
HDMI_CLK-_CONN R698 DIS_HDMI@ D1-
1 2 5 D1_shield
R490 DIS_HDMI@
499_0402_1% 10K_0402_5% HDMI_TX1+_CONN 4
HDMI_TX0+_CONN HDMI_TX2-_CONN D1+
1 2 3 D2-
R491 DIS_HDMI@
499_0402_1% Q94 2
2

D2_shield
1

HDMI_TX0-_CONN D 2N7002H_SOT23-3 HDMI_TX2+_CONN

A 1 2 1 D2+ A
R492 DIS_HDMI@
499_0402_1% 2 DIS_HDMI@ +5VS
HDMI_TX1+_CONN 1 2 G SUYIN_100042GR019M23DZL
R493 DIS_HDMI@
499_0402_1% S Change footprint
3

HDMI_TX1-_CONN 1 2 20100814
R494 DIS_HDMI@
499_0402_1% R874
HDMI_TX2+_CONN 1 2 100K_0402_5%
R495 DIS_HDMI@
499_0402_1% DIS_HDMI@ Security Classification Compal Secret Data Compal Electronics,Ltd.
HDMI_TX2-_CONN 1 2 2010/07/12 2012/07/11 Title
Issued Date Deciphered Date
2

R496 DIS_HDMI@
499_0402_1%
HDMI CONN
NEAR CONNECT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Custom
Document Number Rev
0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 33 of 59
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half)

1 1

+1.5VS
+3VALW +1.5VS_CONN
+3VS +3VS_WLAN
J6

1
Mini-Express Card(WLAN/WiMAX) 1 2 J7
1
@
1
@
1

1
1 2

@
JUMP_43X79 C544 C545 C546
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

@
JUMP_43X79 2 2 2

2
@
JWLN1

2
<16,35> PCIE_WAKE# PCIE_WAKE# R514 1 2 0_0402_5% 1 2
BT_ACTIVE R497 1 WAKE# 3.3V
<42> BT_ACTIVE 2 @ 0_0402_5% 3 NC GND 4
5 6 +1.5VS_CONN
WLAN_CLKREQ1# NC 1.5V LPC_FRAME#_R
<15> WLAN_CLKREQ1# 7 CLKREQ# NC 8
9 10 LPC_AD3_R
GND NC LPC_AD2_R
<15> CLK_PCIE_WLAN1# 11 REFCLK- NC 12
13 14 LPC_AD1_R
<15> CLK_PCIE_WLAN1 REFCLK+ NC
15 16 LPC_AD0_R
PCI_RST#_R GND NC
17 NC GND 18
CLK_PCI_DB 19 20 R498 1 2 0_0402_5%
NC NC WL_OFF# <18>
21 GND PERST# 22 BUF_PLT_RST# <18,35,40>
23 24 R499 1 2 @ 0_0402_5% +3VALW
2 <15> PCIE_PRX_DTX_N2 PERn0 +3.3Vaux 2
25 26 R500 1 2 0_0402_5% +3VS
<15> PCIE_PRX_DTX_P2 PERp0 GND
27 GND +1.5V 28
29 30 R501 1 2 @ 0_0402_5% SMB_CLK_S3 <12,13,15>
GND SMB_CLK R502 1
<15> PCIE_PTX_C_DRX_N2 31 PETn0 SMB_DATA 32 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15>
<15> PCIE_PTX_C_DRX_P2 33 PETp0 GND 34
35 GND USB_D- 36 USB20_N9 <18>
+3VS_WLAN 37 38
NC USB_D+ USB20_P9 <18>
39 NC GND 40
41 42 0_0402_5% 2 @ 1 R503
NC LED_WWAN# 0_0402_5% WLAN_LED#
43 NC LED_WLAN# 44 2 1 R504 WLAN_LED# <56,57>
100_0402_1% 45 46 @
R505 NC LED_WPAN#
47 NC +1.5V 48
EC_TX_P80_DATA 1 2 49 50
<40,41> EC_TX_P80_DATA NC GND
EC_RX_P80_CLK 1 2 51 52
<40,41> EC_RX_P80_CLK NC +3.3V
R506
100_0402_1% 53 54
GND GND

TAITW_PFPET0-AFGLBG1ZZ4N0

2
For EC to detect ME@
R507
debug card insert. 100K_0402_5%

3 3

Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
LPC_FRAME#_R R508 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,40>
LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <14,40>
LPC_AD2_R R510 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <14,40>
LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <14,40>
LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,40>
PCI_RST#_R R513 1 @ 2 0_0402_5% BUF_PLT_RST#
CLK_PCI_DB CLK_PCI_DB <15>
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/NEW Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 34 of 59
A B C D E

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 5 4 3 2 1

Power On strapping
+3VALW +3V_LAN +1.7_VDDCT +1.7_LX Pin Description Chip Default
Close together
H:Over Clock Enable
Layout Notice : Place as close LED0 H
J8 chip as possible. L39 L:Over Clock Disable *
+1.7_VDDCT 1 2 +1.7_LX

1000P_0402_50V7K

10U_0805_10V4Z
4.7UH_SIA4012-4R7M_20% H:SWR Switch mode regulator Select

0.1U_0402_16V4Z
1 2
1 2 *

@ C549

C548

C547
1 1 LED2 --
JUMP_43X79
AR8151 Pin23=LED2.
@ Note: Place Close to LAN chip
2 2 L39 DCR< 0.15 ohm AR8152, Pin23 is CLKREQ
D Atheros request can't disable LAN power Rate current > 1A D

Close to
Pin40

U26 8152@

S IC AR8152-AL1E QFN 40P E-LAN CTRL

no overclocking
PD 5.1K
U26 LED0,1,2 intel Pull UP
Place Close to Chip 1 2
R515 5.1K_0402_5%
C C5531 20.1U_0402_16V7K PCIE_PRX_C_DTX_N129 38 ACTIVITY
Place Close to LAN chip C
<15> PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY <36>
LAN_LINK# 49.9_0402_1%
C5521 20.1U_0402_16V7K PCIE_PRX_C_DTX_P130
Atheros LED_1 39
23 1 8152@ 2
LAN_LINK# <36>
CLKREQ_LAN# MDI0+ R526 1 2 1@ 2 C574 1000P_0402_50V7K
<15> PCIE_PRX_DTX_P1 TX_P LED_2
8151-AL1A R516 0_0402_5% 49.9_0402_1%
36 MDI0- R527 1 2 1 2 C575 0.1U_0402_16V4Z
<15> PCIE_PTX_C_DRX_N1 RX_N
12 MDI0- 49.9_0402_1%
TRXN0 MDI0+ MDI0- <36> MDI1+
35 11 R528 1 2 1@ 2 C576 1000P_0402_50V7K
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ <36>
15 MDI1- 49.9_0402_1%
CLK_PCIE_LAN#_C32 TRXN1 MDI1+ MDI1- <36>
MDI1-
<15> CLK_PCIE_LAN# 2R517 0_0402_5%
1 REFCLK_N TRXP1 14 MDI1+ <36>
R529 1 2 1 2 C577 0.1U_0402_16V4Z
2R518 0_0402_5%
1 CLK_PCIE_LAN_C 33 18 MDI2- 49.9_0402_1%
<15> CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- <36>
17 MDI2+ MDI2+ R530 1 2 1@ 2 C580 1000P_0402_50V7K
BUF_PLT_RST# TRXP2 MDI3- MDI2+ <36>
2 21 GIGA@49.9_0402_1%
<18,34,40> BUF_PLT_RST# PERST# TRXN3 MDI3- <36>
20 MDI3+ MDI2- R531 1 2 1 2 C581 0.1U_0402_16V4Z
TRXP3 MDI3+ <36>
1R519 @ 0_0402_5%
2 PCIE_WAKE#_R 3 GIGA@ 49.9_0402_1% GIGA@
<16,34> PCIE_WAKE# W AKE#
<40> LAN_WAKE# 1R521 0_0402_5%
2 Close Pin 10 MDI3+ R532 1 2 1@ 2 C582 1000P_0402_50V7K
25 10 LAN_RBIAS 1 2 +3V_LAN GIGA@ 49.9_0402_1%
SMCLK RBIAS MDI3-
26 SMDATA
R522 2.37K_0402_1% C554 & C555 Close pin1 < 200mil R533 1 2 1 2 C583 0.1U_0402_16V4Z
GIGA@ GIGA@
+3V_LAN
C557 & C558 Close pin < 400mil
28 TEST_RST VDD33 1

C554

C555

C557

@ C558
10U_0805_10V4Z

10U_0805_10V4Z
Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+

0.1U_0402_16V4Z

1U_0402_6.3V4Z
27 TESTMODE 1 1 1 1
+1.7_LX
resister and cap
LX 40 +1.7_LX
1 2 8152@ LAN_XTALO 7
LAN_XTALI XTLO 2 2 2 2
C559 0.1U_0402_16V4Z 8 XTLI Note 2 : C574, C576, C580, C582, reserved for EMI.
5 +1.7_VDDCT
VDDCT +1.7_VDDCT
R525 GIGA@ 1 2C561
CLKREQ_LAN# 1 2 CLKREQ_LAN#_R 4 0.1U_0402_16V4Z
<15> CLKREQ_LAN# CLKREQ#
0_0402_5% 24 +1.1_DVDDL
DVDDL +1.1_DVDDL
DVDDL_REG 37
+1.1_AVDDL 13
B
+1.1_AVDDL AVDDL B
19 AVDDL
+1.1_AVDDL 31 16 +2.7_AVDDH
+1.1_AVDDL AVDDL AVDDH +2.7_AVDDH
34 AVDDL AVDDH 22
+1.1_AVDDL 6 9 +2.7_AVDDH
AVDDL_REG AVDDH_REG
C564

C565

C566

C567

C568

C569
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1
C571

C570

C572

GIGA@ C573

C563

C562

C560
1U_0402_6.3V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
41 GND 1 1 1 1 1 1 2
AR8151-AL1A_QFN40_5X5
2 2 2 2 2 2
GIGA@

GIGA@

GIGA@
LAN_XTALI 2 2 2 2 2 2 1

LAN_XTALO
Y4
1 2
Near Near Near Near Near Near Near Near Near Near
27P_0402_50V8J

25MHZ_20PF_7A25000012
Pin13 Pin19 Pin31 Pin34 Pin6 Pin9 Pin22 Pin16 Pin37 Pin24
27P_0402_50V8J

1 1
C578

C579

2 2

A A

Configure Configure
Pin4 R525 C559 Pin23 R516
Security Classification Compal Secret Data Compal Electronics, Inc.
AR8152 VDDCT_REG * CLKREQn * Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8151/8152
AR8151 CLKREQn * LED[2] AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6751P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 35 of 59
5 4 3 2 1

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 5 4 3 2 1

8/23 Change T1,T2 P/N to SP050006E00

+1.7_VDDCT T1
D D
2
C435 GIGA@ MDI3+ 1 16 MDO3+
<35> MDI3+ TD+ TX+
R304 0.1U_0402_16V4Z MDI3- 2 15 MDO3-
<35> MDI3- TD- TX-
2 1 3 14 MCT3 2 R534 1 GIGA@
0_0603_5% 1 CT CT 75_0402_5%
4 NC NC 13
1 5 NC NC 12
@C427
@ C427 1 6 11 MCT2 2 R535 1 GIGA@
MDI2+ CT CT MDO2+ 75_0402_5%
<35> MDI2+ 7 RD+ RX+ 10
C436 GIGA@ MDI2- 8 9 MDO2-
2 <35> MDI2- RD- RX-
1U_0402_6.3V4Z 0.1U_0402_16V4Z
2
BOTHHAND_NS0013LF
GIGA@
6/23 update
1 2

T2 C585
2 1000P_1206_2KV7K
Place Close to T2 C438 MDI0+ 1 16 MDO0+
<35> MDI0+ TD+ TX+
0.1U_0402_16V4Z MDI0- 2 15 MDO0-
<35> MDI0- TD- TX-
3 14 MCT0 2 R536 1
1 CT CT 75_0402_5%
4 NC NC 13
MDI1- 5 12
NC NC MCT1
C 1 6 CT CT 11 2 R537 1 C
MDI1+ 7 10 MDO1+ 75_0402_5%
<35> MDI1+ RD+ RX+
MDI1+ C440 MDI1- 8 9 MDO1- 1 1
<35> MDI1- RD- RX-
D31 0.1U_0402_16V4Z
2 C643 C644
TCLAMP3302N.TCT_SLP2626P10-10 BOTHHAND_NS0013LF 22U_1206_10V7K 22U_1206_10V7K
2 2
10
6
7
8
9

@ @
6
7
8
9
10

11 R02
GND
Reserve gas tube for EMI go rural solution
5
4
3
2
1

20101006
JRJ2
5
4
3
2
1

LAN_LINK# 12
<35> LAN_LINK# Green LED-
1 220_0402_5%
@ +3V_LAN 2 1 11
MDI0- C378 R699 Green LED+
SHLD2 16
470P_0402_50V7K MDO3- 8
MDI0+ 2 PR4-
SHLD1 15
MDO3+ 7 PR4+
@ MDO1- 6 PR2-
B Reserve D1 for EMI go rural solution MDO2- 5 B
PR3-
20101006
MDO2+ 4 PR3+
MDO1+ 3 PR2+
MDO0- 2 PR1-
SHLD2 14
MDO0+ 1 PR1+
SHLD1 13
10 Yellow LED-
ACTIVITY R538 2 1 220_0402_5% 9
<35> ACTIVITY Yellow LED+
1 LIYO_101007-08203-033
@
C379 ME@
470P_0402_50V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-6751P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 36 of 59
5 4 3 2 1

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 5 4 3 2 1

D D

+3VS REMOTE1+
Close to DDR
Close U20 SMSC thermal sensor 1

1
@ C

1
1
REMOTE1+
+3VS placed near by VRAM R540
C586
100P_0402_50V8J
2
B
Q97
MMST3904-7-F_SOT323-3
2 E
10K_0402_5%

3
C587 @ REMOTE1-
2200P_0402_50V7K U27

2
2 REMOTE1-

1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <15,24,40>
REMOTE1+ 2 9 EC_SMB_DA2
REMOTE2+ 2
DP1 SMDATA EC_SMB_DA2 <15,24,40>
REMOTE2+
Under WWAN
1 REMOTE1- 3 8 1
DN1 ALERT#

1
C590 @ C @
C588 @ 0.1U_0402_16V4Z REMOTE2+ 4 7 C589 2 Q98
2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 2 E
5 6

3
DN2 GND REMOTE2-

EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil C

10/5 change P/N to SA000046C00 Trace length:<8"

B B

FAN1 Conn
+5VS

JFAN1
1 1
<40> EC_TACH 2 2
<40> EC_FAN_PW M 3 3
4 4
2 5 G5
6 G6
C591
10U_0805_10V4Z ACES_85205-04001
1 ME@

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
EMC1403_Thermal sensor/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 37 of 59
5 4 3 2 1
 A B C D E F G H

Left USB Conn.

+USB_VCCB
W=80mils
JUSB1
1 VCC
1 USB20_N1 1 @ 2 USB20_N1_C 2
<18> USB20_N1 USB20_P1 USB20_P1_C D-
1 R660 1 @ 2 0_0402_5% 3
+ <18> USB20_P1 D+
C592 R661 0_0402_5% 4 GND
220U_6.3V_M C593 8/27 change to @

PJDLC05_SOT23-3
470P_0402_50V7K 5
2 2 D16 GND1
6
WCM-2012-900T_4P @ GND2
7
1 USB20_N1 USB20_N1_C GND3 1
4 3 8
4 3 GND4
9/27 change C592 to SUYIN_020173GR004M58BZL
USB20_P1 1 2 USB20_P1_C
4.2H SF000002Y00 1 2
L65 ME@

1
8/27 change to stuff

+5VALW +USB_VCCB
E-SATA COMBO
U29
1 8
RIGHT USB PORT
C594 0.1U_0402_16V4Z GND OUT
2 IN OUT 7
2 1 3 IN OUT 6
USB_ON# 4 5 USB_OC0#
<40,42,56,57> USB_ON# EN OC# USB_OC0# <18,56,57>
APL3510BKI_SO8
Low Active
1
C595
@ 1000P_0402_50V7K
2

SATA HDD Conn.

2 JHDD1 2
1 GND
<14> SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 2
SATA_ITX_DRX_N0 RX+
<14> SATA_ITX_DRX_N0 3 RX-
4 GND
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5
<14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 SATA_DTX_IRX_P0 TX-
2 0.01U_0402_16V7K 6 TX+
<14> SATA_DTX_C_IRX_P0
7
GND

8
3.3V
+3VS 9
3.3V
10
3.3V
11
GND
12
GND
13 GND
14
5V
+5VS 15
5V
16
5V
17
GND
18
Reserved
19
+5VS +3VS GND
20 23
12V GND
21 24
12V GND
22
12V
1 1 1 1 1 1
@ SUYIN_127043FB022G278ZR
C598 C599 C600 C601 C602 C603
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
3 3
@ @

ODD Power Control

@ J9
1 2
1 2

+5VS JUMP_43X79 +5V_ODD

3 1
1

1
Change footprint Q99
20100814 C604
R552 AP2301GN-HF_SOT23-3 0.1U_0402_16V4Z

2
10K_0402_5% 2
C607
0.01U_0402_16V7K 1

2
1 R675 2 1 2
100K_0402_5% C608

1
10U_0805_10V4Z
2

OUT
<19> ODD_EN 2
IN
4 GND 4
Q100
DTC124EKAT146_SC59-3
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 38 of 59
A B C D E F G H
 5 4 3 2 1

CX20671
High Definition Audio Codec SoC HDA_RST_AUDIO#
With Integrated Class-D Stereo
HDA_SYNC_AUDIO
EMI
Amplifier.
HDA_SDOUT_AUDIO_R
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO). 1
33_0402_5%
2
R556
HDA_BITCLK_AUDIO

An integrated 3.3 V to 1.8V Low-dropout @

voltage regulator (LDO). 9/27 Update U30 P/N to SA00003K410 1 1 1 1

C609

C610

C611

C612
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
2 2 2 2
D D
@ @ @ @

+3VS

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1

C613

C614

C615
+LDO_OUT_3.3V
+3VS 2 1 +VAUX_3.3
0_0402_5% R557 2 2 2

1U_0603_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VALW 2 @ 1 @ 1 1 1 1 AVDD_3.3 pinis output of

10U_0805_10V4Z

0.1U_0402_16V4Z

C618

C619

C620

C621
0_0402_5% R558 1 1 internal LDO. NOT connect

C616

C617
6/24 change +3VS To support Wake-on-Jack or Wake-on-Ring, the CODEC
VAUX_3.3 & VDD_IO pins must be powerd by a rail that to external supply.
is not removed unless AC power is removed. 2 2 2 2
*DSH page42 has more detail. 2 2

9/28 Change to R879 for 21Z

2 1 +CLASSD_5VS
+3VS
0_0402_5% R560 1 R879 2
+3VALW 2 @ 1 +5VS 0_0805_5%

1U_0603_10V4Z

0.1U_0402_16V4Z
0_0402_5% R561 1 1 10K only needed if supply to VAUX_3.3

C622

C623
is removed during system re-start. 1 R562 2 @ +5VS

10U_0805_10V4Z

0.1U_0402_16V4Z
1 1

C624

C625
0.1_1206_1%

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2
1 1 1 1

C626

C627

C628

C629
Layout Note:Path from +5VS to LPW R_5.0

10U_0805_10V4Z

0.1U_0402_16V4Z
1
2 2

10K_0402_5%
1 1 RPW R_5.0 must be very low

C630

C631
R563 2 2 2 2 resistance (<0.01 ohms)
HDA_RST_AUDIO#

0.1U_0402_16V4Z
<14> HDA_RST_AUDIO# 2 2

18

29

27
28
26
C 1 C

3
7
2
HDA_BITCLK_AUDIO

C632
U30
<14> HDA_BITCLK_AUDIO

FILT_1.8

VAUX_3.3
DVDD_3.3

FILT_1.65

AVDD_3.3
VDD_IO

AVDD_5V
AVDD_HP
Please bypass caps very close to device.
HDA_SYNC_AUDIO 2
<14> HDA_SYNC_AUDIO 8/10 update LPWR_5.0
12
15
+3VS RPWR_5.0
9 17
RESET# CLASS-D_REF R564 1 2 5.11K_0402_1% +VAUX_3.3
0_0402_5% 2 R578 1 HDA_BITCLK_AUDIO_R 5 Sense resistors must be
2

BIT_CLK R565 2 10K_0402_1% Port C

G

8 36 1 MIC_JD <43> connected same power

SYNC SENSE_A
<14> HDA_SDIN0 1 R566 2 33_0402_5% 6 R567 1 2 39.2K_0402_1% PLUG_IN <43> Port A
HDA_SDOUT_AUDIO 1 3 HDA_SDOUT_AUDIO_R 4
SDATA_IN that is used for VAUX_3.3
<14> HDA_SDOUT_AUDIO Change footprint SDATA_OUT
35 MIC_INR Internal MIC
D

20100814 PORTB_R MIC_INL

34
2N7002H_SOT23-3 PORTB_L
33 +MICBIASB
PC_BEEP B_BIAS R568 2.2K_0402_5%
Q9 10 +MICBIASC
PC_BEEP R569 2.2K_0402_5%
1R669 @ 2 32 +MICBIASC
C_BIAS C633 1
31 2 2.2U_0603_6.3V4Z R570 100_0402_1%
EXT_MIC_R <43>
0_0402_5% PORTC_R C634 1
30 2 2.2U_0603_6.3V4Z EXT_MIC_L <43> External MIC
0_0402_5% PORTC_L
<40> EAPD 1 2 R572 38 R571 100_0402_1%
EC_MUTE# GPIO0/EAPD#
<40> EC_MUTE# 2 1 37
0_0402_5% R573 GPIO1/SPK_MUTE# HP_OUTR_R R575 15_0402_5%
23 1 2 HP_OUTR <43>
PORTA_R HP_OUTL_R R574 15_0402_5%
PORTA_L
22 1 2 HP_OUTL <43> Headphone
40
DMIC_CLK
1
DMIC_1/2 NC
24 Changed from 5.1ohm to 15ohm
25 for "zi zi"noise.
NC
39
SPK_L2+ NC
11
SPK_L1- LEFT+
EAPD active low 13
LEFT-
C637 @ 0=power down ex AMP Internal SPEAKER AVEE
21
19
SPK_R2+ FLY_P
1 2 1=power up ex AMP 16 20 1 2

10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z SPK_R1- RIGHT+ FLY_N C638 1U_0603_10V4Z
14 1 1
RIGHT-

C639

C641
GND

C640 @ +3VS
1 2
1

B 2 2 B
0.1U_0402_16V4Z CX20671-21Z_QFN40_6X6
41

R576 @ R351
1 2 @ 4.7K_0402_5%
0_0402_5% +MICBIASB
R577 @
2

1 2

1
0_0402_5% HDA_RST_AUDIO#
R579 @ R580
1 2 1 4.7K_0402_5%
0_0402_5% C584
@

2
100P_0402_50V8J MIC1 C642
2 1 1 2 2.2U_0603_6.3V4Z MIC_INR
2 GNDA
GND GNDA MIC_INL
WM-64PCY_2P
8/10 update 45@
8/10 update for vendor suggestion
R720

0_0402_5%
R598
2 1 @
FBMA-L11-160808-121LMA30T
R721
wide 20MIL
EC Beep <40> BEEP# 2 1

D17 RB751V_SOD323 JSPK1

R582 SPK_R1- R720 2 @ 1 0_0603_5% SPK_R1-_CONN 1
1
ICH Beep <14> HDA_SPKR 2 1PC_BEEP1 1 2 1 2 PC_BEEP SPK_R2+ R721 2 @ 1 0_0603_5% SPK_R2+_CONN 2
33_0402_5% C645 0.1U_0402_16V4Z SPK_L1- R722 @ 0_0603_5% SPK_L1-_CONN 2
FBMA-L11-160808-121LMA30T 2 1 3
3
D30 RB751V_SOD323 SPK_L2+ R723 2 @ 1 0_0603_5% SPK_L2+_CONN 4
4
1

R722
5
R585 GND1
6
PC Beep

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
10K_0402_5% GND2
A 1 1 1 1 A

C649

C650

C647

C651
ACES_88231-04001
2

ME@
FBMA-L11-160808-121LMA30T 8/24 update 2 2 2 2
R723

10/08 update

FBMA-L11-160808-121LMA30T
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
CX20671 Codec

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 39 of 59
5 4 3 2 1
 +3VALW 3.3V +/- 5%
+EC_AVCC Vcc
1 1 1 1 1 1 R694 100K +/- 5%

0.1U_0402_16V4Z
C653

0.1U_0402_16V4Z
C654

0.1U_0402_16V4Z
C662

0.1U_0402_16V4Z
C655

1000P_0402_50V7K
C657

1000P_0402_50V7K
C658
L44 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 Board ID R695 VAD_BID min V AD_BID typ
2 1 VAD_BID max
C656 2 2 2 2 2 2
0.1U_0402_16V4Z C659 0 0 0 V 0 V 0 V MP

111
125
1000P_0402_50V7K

22
33
96

67
9
1 2 1 ECAGND 2 U31 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
L45 FBM-11-160808-601-T_0603

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
Change to 0 ohm P/N
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
1 21 CPU1.5V_S3_GATE
<19> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F CPU1.5V_S3_GATE <10>
KB_RST# 2 23 BEEP#
<19> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 PCH_DPWROK BEEP# <39>
3 26 +3VALW
<14> SERIRQ SERIRQ# FANPWM1/GPIO12 ACOFF PCH_DPWROK <16>
4 27 +3VS
<14,34> LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <45,47>
<14,34> LPC_AD3 5
LAD3

2
LPC_AD2 7 PWM Output
<14,34> LPC_AD2 LAD2

1
LPC_AD1 8 63 BATT_TEMP
<14,34> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <46> 100K_0402_1%
LPC_AD0 @
LAD0 LPC & MISC
<14,34> LPC_AD0 10 64
BATT_OVP/AD1/GPIO39 R588 R694
2 1 2 1 65 ADP_I <46,47>
@ C660 22P_0402_50V8J @ R589 10_0402_5% ADP_I/AD2/GPIO3A 10K_0402_5%
12 AD Input 66

1
<18> CLK_PCI_LPC PCICLK AD3/GPIO3B BRDID IMVP_IMON <53> BRDID
13 75 @ 10/6 Modify

2
<18,34,35> BUF_PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
1 2 EC_RST# 37 76 EC_FAN_PWM
+3VALW ECRST# SELIO2#/AD5/GPIO43

2
R590 47K_0402_5% EC_SCI# 20
<19> EC_SCI# BATT_LEN# SCI#/GPIO0E
2 38 R695
<46> BATT_LEN# CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68 8.2K_0402_5%
C661 70 CHG_ON# +5VALW
EN_DFAN1/DA1/GPIO3D IREF CHG_ON#
0.1U_0402_16V4Z 11/16 Modify DA Output 71

1
1 IREF/DA2/GPIO3E IREF <47>
KSI0 55 72 +3VALW
KSI1 KSI0/GPIO30 DA3/GPIO3F CHGVADJ <47>
56 KSI1/GPIO31
KSI2 57 EC_MUTE# R593 1 2 10K_0402_5%
KSO[0..15] KSI3 KSI2/GPIO32
<56,57> KSO[0..15] <56,57> KSI3 58
KSI3/GPIO33 PSCLK1/GPIO4A
83 EC_MUTE# <39> 6/19 Add BRDID
KSI4 59 84 USB_ON# USB_ON# R594 1 2 10K_0402_5%
KSI[0..7] <56,57> KSI4 KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# <38,42,56,57> +5VS
60 KSI5/GPIO35 PSCLK2/GPIO4C 85
<56,57> KSI[0..7] KSI6 61 PS2 Interface 86
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK CMOS_OFF# <31> TP_CLK
62 87 R591 1 2 4.7K_0402_5%
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <56,57>
+3VALW 39 88
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <56,57>
R595 1 2 47K_0402_5% KSO1 KSO1 40 KSO1/GPIO21 7/23 Modify TP_DATA R592 1 2 4.7K_0402_5%
KSO2 41
KSO2/GPIO22
R597 1 2 47K_0402_5% KSO2 KSO3 42 KSO3/GPIO23 SDICS#/GPXOA00 97 SYS_PWROK_EC <16>
KSO4 43 98 CE_EN_EC 2 1 @
KSO5 KSO4/GPIO24 SDICLK/GPXOA01 CE_EN <31>
BATT_TEMP
0_0402_5% R746 +3VALW
KSO5/GPIO25 Int. K/B
44 99 1 2
ENE UPDATE 08/10/21 KSO6 45 KSO6/GPIO26 Matrix
SDIDO/GPXOA02
SDIDI/GPXID0 109 LID_SW#
ME_FLASH <14>
LID_SW# <56,57>
C663 100P_0402_50V8J
KSO7 46 SPI Device Interface FRD#SPI_SO 2 1 ACIN 1 2
+3VS +3VALW KSO8 KSO7/GPIO27 100K_0402_1%@ R599 C664 100P_0402_50V8J
47
KSO9 KSO8/GPIO28 FRD#SPI_SO
48 119 FRD#SPI_SO <41>
R600 EC_SMB_CK1 KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI FSEL#SPICS#
49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI <41> 2 1
2.2K_0402_5% KSO11 50 SPI Flash ROM 126 SPI_CLK 100K_0402_1%@ R603
KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# SPI_CLK <41>
51 128 FSEL#SPICS# <41>
R601 R602 R604 EC_SMB_DA1 KSO13 KSO12/GPIO2C SPICS#
52
2.2K_0402_5% KSO14 KSO13/GPIO2D R737
2.2K_0402_5% 2.2K_0402_5% 53
KSO15 KSO14/GPIO2E H_PROCHOT#_EC 0_0402_5%
54 KSO15/GPIO2F CIR_RX/GPIO40 73
KSO16 81 74 H_PECI_R R665 1 2 43_0402_1% VR_HOT# 2 1 H_PROCHOT# <6>
<57> KSO16 KSO16/GPIO48 CIR_RLC_TX/GPIO41 H_PECI <6,19> <46,53> VR_HOT#
EC_SMB_CK2 KSO17 82 89
EC_SMB_DA2 <57> KSO17 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0# FSTCHG <47>
90 CHARGE_LED0# <56,57>
BATT_CHGI_LED#/GPIO52

1
CAPS_LED# D
1 1 CAPS_LED#/GPIO53 91 CAPS_LED# <43>
@ @ EC_SMB_CK1 77 GPIO 92 H_PROCHOT#_EC 2 Q37
<46> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 PWR_LED# <43,56,57>
C665 C666 EC_SMB_DA1 78 93 CHARGE_LED1# G 2N7002H_SOT23-3
<46> EC_SMB_DA1 EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON CHARGE_LED1# <56,57> Change footprint
100P_0402_50V8J 100P_0402_50V8J 79 SM Bus 95 S

3
2 2 <15,24,37> EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 SYSON <44,49> 20100814
<15,24,37> EC_SMB_DA2 80 121 VR_ON <53>
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN
AC_IN/GPIO59 127 ACIN <16,24,47>
0_0402_5% R747
<16> SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# <16> 2 1
+3VS 14 101 EC_LID_OUT# 7/23 Modify @ 7/28 Modify
<16> SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON EC_LID_OUT# <15>
15 102 @
<19> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <43,48>
16 103 D18 RB751V_SOD323
LID_SW#/GPIO0A EC_SWI#/GPXO06 BATT_SEL_EC <47>
1

17 104 PCH_POK_EC 1 2 PCH_POK

SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PCH_POK <6,16>
18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF# <31>
R605 SUSWARN# 19 GPIO 106 RF_LED# 1 2 1 2
<16> SUSWARN# EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_LED# <56,57> +3VS
10K_0402_5% INVT_PWM 25 107 PCH_APWROK <16> R607 0_0402_5% R608 10K_0402_5%
<31> INVT_PWM EC_TACH EC_THERM#/GPIO11 GPXO10
28 108 SA_PGOOD <50> @
2

EC_TACH <37> EC_TACH ODD_DA# FAN_SPEED1/FANFB1/GPIO14 GPXO11

<18,56,57> ODD_DA# 29 FANFB2/GPIO15
EC_TX_P80_DATA 30
<34,41> EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16
<34,41> EC_RX_P80_CLK 31 110 SLP_S4# <16>
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 +3VALW
<43> ON/OFF# 32 112 ENBKL <31>
EC_FAN_PWM ON_OFF/GPIO18 ENBKL/GPXID2
<37> EC_FAN_PWM 34 PWR_LED#/GPIO19 GPXID3 114 EAPD <39>
36 GPI 115 NOVO#
<43> NUM_LED# NUMLED#/GPIO1A GPXID4 NOVO# <43>

2
116 SUSP#
GPXID5 PBTN_OUT# SUSP# <10,26,44,49,51,52>
117 R606
GPXID6 PBTN_OUT# <16>
118 10K_0402_5%
EC_RTCX1 122 GPXID7
SUSCLK_R 123 XCLK1
2 1 124

1
<16> SUSCLK XCLK0 V18R
0_0402_5% R611 1 C667
AGND

4.7U_0603_6.3V6K
GND
GND
GND
GND
GND
1

2 1
R740 C93 KB930QF A0 LQFP 128P 2 0_0402_5% R609 LAN_WAKE# <35>
11
24
35
94
113

69

100K_0402_5% 20P_0402_50V8
2

2 1
2

ECAGND

0_0402_5%@ R610

8/23 modify EC_PME#

S
1 3
2N7002H_SOT23-3 @ PCI_PME# <18>

Q102

G
2
Change footprint +3VALW
20100814
EC_RTCX1 1 @ 2 R708 0_0402_5% PCH_RTCX1_OUT <14>
1 2 SUSCLK_R 1 @ 2 R709 0_0402_5% PCH_RTCX2_OUT <14>
R120 10M_0402_5%
@
6/24 Update R708,R709 must be close Y5
32.768KHZ_12.5PF_9H03200413
1

4
18P_0402_50V8J

Y5
OSC

OSC

1 1
C367
C347 18P_0402_50V8J
NC

NC

2 2 @
@
2

@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
8/23 change to reserved DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-6751P 0.2

WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 40 of 59
 FOR EC 128KB SPI ROM
(150mil PACKAGE)
SA00003FL10
SA00003JD00
+3VALW
20mils R619 8/27 R619 change to Bead
1

1
C699
0.1U_0402_16V4Z R617
2 10K_0402_5% S SUPPRE_ KC FBMA-10-100505-101T 0402

2
U33
<40> FSEL#SPICS# FSEL#SPICS# 1 8
FRD#SPI_SO R618 1 SPI_SO CS# VCC HOLD#
<40> FRD#SPI_SO 2 15_0402_5% 2
DO HOLD#
7 R619 @ 0_0402_5%
3 6 SPI_CLK_R 1 2 SPI_CLK
WP# CLK SPI_CLK <40>
4 5
GND DIO
MX25L2005CMI-12G SOP SPI_SI_EC 1 2 15_0402_5% FWR#SPI_SI SPI_CLK_R
FWR#SPI_SI <40>
R620

Colse to EC
1
@
C700
EC DEBUG PORT 10P_0402_50V8J
2

1
JP3 EMI
+3VALW 1
EC_TX_P80_DATA 2
<34,40> EC_TX_P80_DATA EC_RX_P80_CLK 2
<34,40> EC_RX_P80_CLK 3 3
4 4
ACES_85205-0400
ME@

FD1 FD2 FD3 FD4

1 1 1 1

H_3P8
H1 H2 H3 H4
HOLEA HOLEA HOLEA HOLEA

1
H_3P3 H_3P0x4P5N H_3P0N H_6P0
H6 H5
HOLEA H15 H16 HOLEA H17
HOLEA HOLEA HOLEA

1
1

1
H_2P8
H12 H11 H10 H9 H13 H8 H7
H_5P5N
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H14
HOLEA

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6751P
WWW.AliSaler.Com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 41 of 59
 A B C D E

8/27 change to stuff

1 1

WCM-2012-900T_4P
USB20_N2 4 3 USB20_N2_C
4 3

USB20_P2 1 2 USB20_P2_C
1 2
L63
(220uF_6.3V_5.9L_ESR17m)*2=(SF000001500) Left USB Conn.
+USB_VCCC
W=80mils JUSB2
1 VCC
USB20_N2 2 R862 @1 0_0402_5% USB20_N2_C 2
+5VALW <18> USB20_N2 D-
1 USB20_P2 2 R863 @1 0_0402_5% USB20_P2_C 3
<18> USB20_P2 D+
4 GND
C702 8/27 change to @

PJDLC05_SOT23-3
470P_0402_50V7K 5
+USB_VCCC 2 D21 GND1
E-SATA COMBO 6 GND2
U34 @ 7
1 8
RIGHT USB PORT 8
GND3
C703 0.1U_0402_16V4Z GND OUT GND4
2 IN OUT 7
2 1 3 6 SUYIN_020173GR004M58BZL
USB_ON# 4 IN OUT
<38,40,56,57> USB_ON# EN OC# 5 USB_OC1# <18>
APL3510BKI_SO8 ESATA and USB Conn. ME@

1
2 Low Active 2
1
C704 +USB_VCCC
@ 1000P_0402_50V7K W=80mils
+USB_VCCC
2
1
USB20_N3_C 8/27 change to stuff 1 8/27 change to @
+ C706 C705 0_0402_5% JESAT1
USB20_P3_C
WCM-2012-900T_4P
220U_6.3V_M 470P_0402_50V7K
USB20_N3 2 R865
@ 1 VBUS
USB USB
<18> USB20_N3 1USB20_N3_C 2 D-
3

2 2
PJDLC05_SOT23-3

USB20_N3 4 3 USB20_N3_C USB20_P3 2 @ 1USB20_P3_C 3

D22
@
4 3 <18> USB20_P3
0_0402_5% R864 4
D+
GND
A+ = RXP
USB20_P3 1 2 USB20_P3_C 5
1
L64
2
<14> SATA_ITX_DRX_P4 SATA_ITX_DRX_P4
SATA_ITX_DRX_N4
R627
R628
1 ESATA@2 0_0402_5% SATA_ITX_DRX_P4_R
0_0402_5% SATA_ITX_DRX_N4_R
6
GND
A+ ESATA
A- = RXN
<14> SATA_ITX_DRX_N4 1 2 7 A-
ESATA@ ESATA@ ESATA_DET#_CONN 8 12
SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 GND SHIELD
<14> SATA_DTX_C_IRX_N4 1 C707 SATA_DTX_IRX_N4 R629 1 ESATA@2 0_0402_5% SATA_DTX_IRX_N4_R 9 B- SHIELD 13
SATA_DTX_C_IRX_P4 2 1 C708 SATA_DTX_IRX_P4 R630 1 2 0_0402_5% SATA_DTX_IRX_P4_R 10 14
1

<14> SATA_DTX_C_IRX_P4 0.01U_0402_16V7K ESATA@ ESATA@ B+ SHIELD

11 15
GND SHIELD
FOX_3Q38111-RB1C3-7HC
B- = TXN
+5VALW 0_0402_5% 2 R866 1 ESATA_DET#_CONN
<19> ESATA_DET#
1 ESATA@ B+ = TXP
1

BT@ R631
BT MODULE CONN C735
0.1U_0402_16V4Z
2 R867 1

100K_0402_5% 2 @ @ 0_0402_5%
3 C709 3
0.1U_0402_16V4Z
2

1 R632 2 1 2 7/31 Add

100K_0402_5% +3VS +3VS
1

BT@ BT@
@ R877
1

2
0_0402_5% +3VS_BT 1 2
OUT

2
R633
2

@ 4.7K_0402_5% C710 C711 R634 R635

2 +3VS BT@ 0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7K_0402_5% 4.7K_0402_5%
<19> BT_OFF# IN 2 @ 1 @
Q103 30mils @ @
GND

1
DTC124EKAT146_SC59-3 3 1 U35

1
BT@ 1 7 6
Change footprint Q104 0.1U_0402_16V4Z EN VCC
10
3

20100814 C712 SATA_ITX_DRX_P4 VCC

1 RX_0P VCC 16
AP2301GN-HF_SOT23-3 BT@ SATA_ITX_DRX_N4 2 20
2

2 RX_0N VCC
<56,57> BT_LED#
Q105 JBT1 SATA_DTX_IRX_P4 5 9
TX_1P D0
1

DTC124EKAT146_SC59-3 1 SATA_DTX_IRX_N4 4 8
@ 1 TX_1N D1
2
OUT

2
<18> USB20_P13 USB20_P13 3 3 15 SATA_ITX_DRX_P4_R
USB20_N13 3 GND TX_0P SATA_ITX_DRX_N4_R R636 R637
<18> USB20_N13 4 4 13 GND TX_0N 14
BTON_LED
IN 2 BT_ACTIVE
5 5 G1 7 17 GND SATA_DTX_IRX_N4_R
0_0402_5%
@
0_0402_5%
@
<34> BT_ACTIVE 6 8 18 12
GND

6 G2 GND RX_1N SATA_DTX_IRX_P4_R

19 11

1
ACES_87213-0600G GND RX_1P
21 PAD
4 ME@ 4
3

SN75LVCP412RTJR_QFN20_4X4
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ports/BT/E-SATA
Size Document Number Rev

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 42 of 59
A B C D E
ON/OFF switchSW 3 @
1 3
Power Button Power Bottom Board Conn. 8pin
2 4
SMT1-05_4P

6
5
+3VALW

TOP Side J11 +5VALW

2
1 2

SHORT PADS R638 JPW RB1

Bottom Side 100K_0402_5% 1
D23 1
<40> NUM_LED# 2

1
ON/OFF# 2
3 3
ON/OFFBTN# 1
51_ON#
ON/OFF# <40> <40> CAPS_LED#
<40,56,57> PW R_LED# 4
3
4
Card Reader/Audio Jack SB CONN
2 51_ON# <45> 5 5
NOVO_BTN# 6 8/5 modify
DAN202UT106_SC70-3 ON/OFFBTN# 6
7 7
8 8 JCR1
9 HP_OUTL 1
GND <39> HP_OUTL 1
10 HP_OUTR 2
GND <39> HP_OUTR 2
<39> PLUG_IN PLUG_IN 3 3
4 4

1
D EXT_MIC_L
2N7002H_SOT23-3 <39> EXT_MIC_L 5 5
EC_ON 2 EXT_MIC_R 6
<40,48> EC_ON <39> EXT_MIC_R 6
G Q106 ACES_88058-080N <39> MIC_JD MIC_JD 7
0_0402_5% 7
S 8

3
8
2

Change footprint +3VS USB20_P11 2 R871 1 USB20_P11_C 9

20100814 ME@ <18> USB20_P11 9
R639 USB20_N11 2 R870 1 USB20_N11_C10
<18> USB20_N11 10
10K_0402_5% 0_0402_5% 11 11
12 12
13

1000P_0603_50V7K
1

GND
14 GND

1
W CM-2012-900T_4P

C635
USB20_N11 4 3 USB20_N11_C ACES_88058-120N
4 3

2
USB20_P11 1 2 USB20_P11_C
1 2
NOVO_BTN# ON/OFFBTN# L67 @
+3VALW

2
D24
2

PJSOT24C 3P C/A SOT-23

R642 @
100K_0402_5%

1
D26
1

NOVO# 2
<40> NOVO#
1 NOVO_BTN#
51_ON# 3

DAN202UT106_SC70-3
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
other IO connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6751P
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 43 of 59
 A B C D E

Change footprint Change footprint +1.5V to +1.5VS Change footprint

+5VALW TO +5VS 20100814 +3VALW TO +3VS 20100814 20100814
+1.5V +1.5VS

+5VALW U38 +5VS +3VALW U39 +3VS 3 1

DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8 1 1 1

1
8 1 8 1 Q8
1 7 2 1 1 1 7 2 1 1 C717 C718 C719

1
6 3 6 3 10U_0805_10V4Z AP2301GN-HF_SOT23-3
10U_0805_10V4Z 1U_0603_10V4Z R643

2
C720 C721 C722 C723 C724 C725 2 2 2 470_0603_5%
5 5
10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R644 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R645 @

2
1 2 2 2 2 2 2 1
470_0603_5% 470_0603_5%

4
@ @

1 2

1 2

1
+3VALW D
+VSB D +VSB D 2N7002H_SOT23-3 SUSP
2
2N7002H_SOT23-3 2N7002H_SOT23-3 Q109
2 SUSP 2 SUSP G

1
Q107 G Q108 G Change footprint @ S

3
@ S Change footprint @ S Change footprint 20100814

3
R646 20100814 R647 20100814 100K_0402_5%
20K_0402_5% 47K_0402_5% R648

2
5VS_GATE2 R649 15VS_GATE_R 2 R651 1 1.5VS_GATE

2
1 1 1 1
1

1
D 10K_0402_5% D R650 D
SUSP C726 SUSP C727 SUSP# 2 0_0402_5% C728 C729
2 2 0_0402_5%
G Q110 0.1U_0603_25V7K G Q111 0.1U_0603_25V7K G Q112 0.1U_0603_25V7K
S 2N7002H_SOT23-3 2 S 2N7002H_SOT23-3 @ 2 S 2N7002H_SOT23-3 2 2
3

3
Change footprint Change footprint Change footprint
0.1U_0603_25V7K
20100814 20100814 20100814

2 2

+RTCVCC +5VALW
+5VALW

1
+1.8VS +1.5V +0.75VS +1.05VS @
R652 R653 @
100K_0402_5% 100K_0402_5% R654
1

1
100K_0402_5%

2
SUSP

2
<6,10,51> SUSP
R655 R656 R658 R659 SYSON#
470_0603_5% 470_0603_5% 22_0603_5% 470_0603_5% Q117 Q119

1
@ @ @ DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
1 2

1 2

1 2

1 2
@

OUT

OUT
D D D D
2N7002H_SOT23-3
3
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 3
Q113 G Q114 G Q115 G Q116 G 2 SYSON 2
Change footprint @ Change footprint Change footprint <10,26,40,49,51,52> SUSP# IN <40,49> SYSON IN
@ S S S @ S 2N7002H_SOT23-3

GND

GND
3

20100814 20100814 20100814 3 Change footprint

2N7002H_SOT23-3 20100814
2N7002H_SOT23-3

3
For Intel S3 Power Reduction.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 44 of 59
A B C D E

WWW.AliSaler.Com
 5 4 3 2 1

DC030006J00 VIN
Precharge detector
PF101 PL101 15.97V/14.84V FOR
4 APDIN
7A_24VDC_429007.WRML
1 2 APDIN1
SMB3025500YA_2P
1 2
ADAPTOR
4

3 3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2
2

1
D D
1
1 PreCHG PQ102
@ TP0610K-T1-E3_SOT23-3

2
@ 4602-Q04C-09R 4P P2.5

PC101

PC102

PC103

PC104
PR102
JDCIN1 @ 1K_1206_5% PD102
1 2 2 1 3 1
VIN
PR103 @ LL4148_LL34-2
@ 1K_1206_5%
1 2

@ 100K_0402_1%
1

1
@ 100K_0402_1%
PR104

PR105

PR106
@ 1K_1206_5%

2
1 2

PR107

2
@ 1K_1206_5%
1 2
VIN

@ 100K_0402_1%
1
PD103 PQ103

PR108
LL4148_LL34-2 @ DDTC115EUA-7-F_SOT323-3

1
1

@ DDTC115EUA-7-F_SOT323-3
PD101 PD104

1 2
LL4148_LL34-2 2
2 1 <40,47> ACOFF 1 2
BATT+

1
3
PR109 PR110 <48> +5VALWP

PQ104
68_1206_5% 68_1206_5% @ RB715F_SOT323-3
PQ101 VS 2

3
C TP0610K-T1-E3_SOT23-3 C
2

2
N1 3 1
0.22U_0603_25V7K

3
1

PR101 PC106
PC105

100K_0402_5% 0.1U_0603_25V7K
B+
2

PR111
2

22K_0402_5% PR112
1 2 @ 2.2M_0402_5%
<43> 51_ON#
2 1

VL
VS

@ 499K_0402_1%
@ 0.01U_0402_25V7K

1
@ 100K_0402_1%

PR113
1
PR114

1
PC107
PD105

2
2
PU101A

8
@ RB715F_SOT323-3 LM393DG_SO8
2 3

P
<46,48> MAINPWON +
1 1
O

@ 205K_0402_1%

@ 499K_0402_1%

@ 0.01U_0402_25V7K
3 2
-

1
<47> ACON

@ 0.1U_0603_25V7K
+RTCBATT
- +

1
@1000P_0402_50V7K

PR115

PR116

PC110
JRTC1 PR117 PR118

4
1

1
560_0603_5% 560_0603_5%

PC108

PC109
2 1 +RTCBATT 1 2 1 2 +CHGRTC

2
B B

PRG++ 2

2
@2N7002W-T/R7_SOT323-3
ML1220T13RE
45@

1 2 PR119 PR120
+3VLP <47> PACIN

1
@ 34K_0402_1% D @ 47K_0402_5%

PQ105
2 1 2 2 1
PD106 6251VREF G

1
RB751V-40_SOD323-2 S

@ DTC115EUA_SC70-3
2
@ 66.5K_0402_1%

PQ106
PR121
2

+5VALWP

3
ACIN BATT ONLY
Precharge detector Precharge detector
Min. typ. Max. Min. typ. Max.
L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
A A
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/01/25 2010/12/31 Title
Issued Date Deciphered Date PWR DCIN / Vin Detector /Pre-charge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 45 of 54
5 4 3 2 1
 5 4 3 2 1

PH201 under CPU botten side :

VMB2 VMB
CPU thermal protection at 92 degree C
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
Recovery at 56 degree C
1 BATT+
2
D 2 EC_SMCA D
3
3 EC_SMDA
4
4
5
5

1
6
6

1
7 PC201 PC202
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K VL

2
GND
9 ADP_I <40,47>
GND
VL

PR201

PR202
TYCO_1775789-1
2

2
@

1
3.48K_0402_1%

2
PR222
PC203 PR203 PR204
0.1U_0603_25V7K @ 10K_0402_1% 21.5K_0402_1% PR205

2
VL @ 100K_0402_1%

2
100K_0402_1%
PU201

1
1
EC_SMB_CK1 <40> 1 VCC TMSNS1 8

PR221

2
<40,53> VR_HOT#

2N7002KW_SOT323-3
2 GND RHYST1 7
PR206
EC_SMB_DA1 <40>
3 6 9.76K_0402_1%

2
OT1 TMSNS2

1
D

PQ204

43.2K_0402_1%
1 2 +3VALW 2 4 5

1
OT2 RHYST2

2
PR207 G

1
PR208
6.49K_0402_1% S G718TM1U_SOT23-8

3
PR223 PH201
@ 0_0402_5% 100K_0402_1%_TSM0B104F4251RZ
1 2 A/D

1
BATT_TEMP <40>
PR209

2
10K_0402_5% MAINPWON <45,48>

1
C C
PH202
100K_0402_1%

2
VS

+3VALW +3VS
0.01U_0402_25V7K
1

PC204

VMB2
PR210 PR211
2

100K_0402_1% 10K_0402_1%
PR212 PR213
2

649K_0402_1% 5.1M_0402_5%
1

1 2 BATT_OUT <47>
2N7002KW_SOT323-3

PQ202
PR214 TP0610K-T1-E3_SOT23-3
8

10K_0402_1%
1

D
PQ201

1 2 5
P

+
7 2 B+ 3 1 +VSBP
O G
6
-
G
2

100K_0402_1%

0.22U_0603_25V7K
B PU101B B
S
3

1
PR215 LM393DG_SO8
4

1
PR216

PC205
232K_0402_1% PC206
0.1U_0603_25V7K
1

2
2N7002KW_SOT323-3

2
2 1 PR218
6251VREF
1

D VL 22K_0402_1%
PQ205

PR217 2 1 2
<40> BATT_LEN#
10K_0402_1% G
2

S
3

PR219
100K_0402_1%

PR220
1

1
1K_0402_5% D PJ201
1 2 2 PQ203 @ JUMP_43X39
<48> SPOK
G 2N7002W-T/R7_SOT323-3 1 1
1U_0402_6.3V6K
+VSBP 2 2 +VSB
S

3
1

PC207
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 46 of 54
5 4 3 2 1
 5 4 3 2 1

P3
B+
P2 65W:0.020
PQ301 PQ302 90W:0.015
AO4407A_SO8 SI4459_SO8
PR302 PL302
VIN 8
7
1
2
1
2
8
7 0.020_1206_1% 1.2UH_1231AS-H-1R2N=P3_2.9A_30% CHG_B+
6 3 3 6
PQ303

@ 10U_0805_25V6K
5 5 1 4 1 2
AO4407A_SO8
PC325 2 3 1 8
VIN

1
PC324
1 2 2 7
3 6

2200P_0402_50V7K
PQ304 5600P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5

2
D D

2
47K_0402_1%

@ 0.1U_0603_25V7K
1

2
200K_0402_1%
PR303

0.1U_0603_25V7K

PC306

4
1
PR301

PC303

PC304

PC305
DTA144EUA_SC70-3 @47K_0402_1% CSIN DISCHG_G

PC301

PR304

PC302
CSIP

1
PR305

1
PQ317B 47K_0402_1%
VIN PreCHG
2

2
2 @ 2N7002KDW -2N_SOT363-6 1 2

3
VIN

@ 191K_0402_1%

2ACOFF-1
191K_0402_1%

2
1

1
2 5 BATT_OUT <46> PR308

1DISCHG_G-1
PR306

PR307
10K_0402_1%
1

2
PD302

4
1SS355_SOD323-2 PR309

1
BATT_ON 2 P2-1 PQ317A PD301 200K_0402_1%

2
PQ305 @ 2N7002KDW -2N_SOT363-6 6251_VDD RB751V-40_SOD323-2 ACSETIN PQ306
DTC115EUA_SC70-3

1 1

1
1
DTC115EUA_SC70-3 PR310

1
0_0402_5% PR312 PD303
3

FSTCHG
2 1 PR311 14.3K_0402_1% PC307 1SS355_SOD323-2

2.2U_0603_6.3V6K
1 <40> FSTCHG 10_1206_5% 1000P_0402_25V8J 2 1 2

2
6

2
PC308

2
1

150K_0402_1%

PR313

2200P_0402_50V7K
2

2
PR314

@ 100K_0402_5%
PQ307A 10K_0402_1% PU301 PC309 PQ309

1
PC322
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K
12

1
D D

PR316
6251_DCIN 2N7002W -T/R7_SOT323-3

0.1U_0603_25V7K
1 VDD DCIN 24 2 1

1
2 PACIN

100K_0402_1%
2

@2N7002W-T/R7_SOT323-3
1

BATT_OUT <46>

1
PC310
G G

1
PR315
ACSETIN

BATT_ON
S 2 23 S
3

ACPRN <48>

3
PQ308 ACSET ACPRN PR317

2
P2-2

2N7002KW _SOT323-3 20_0402_5%

5
6
7
8
C 6251_EN 6251_CSON CSON C
3 EN CSON 22 1 2

1
D

PQ310
PC311

AO4466L_SO8
3

PQ311
0.047U_0402_16V7K ACPRN 2
PR319 CELLS 4 21 6251_CSOP 1 2 CSOP G

2
47K_0402_1% PQ307B CELLS CSOP PR318 S

3
PACIN 1 2 5 2N7002KDW -2N_SOT363-6 PC312 6800P_0402_25V7K 20_0402_5% 4
<45> PACIN
1 2 6251_ICOMP 5 20 6251_CSIN 2 1
ICOMP CSIN

2
PC313 PR320
<45> ACON
4

PC314 PR321 10K_0402_1% 0.1U_0402_16V7K 20_0402_5%

1 26251_VCOMP-1
1 2 6251_VCOMP 6 19 6251_CSIP 1 2 PL301 PR324

3
2
1
VCOMP CSIP
1

PQ312 PR322 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%

DTC115EUA_SC70-3 0.01U_0402_25V7K 2_0402_5% BATT+
1 26251_ICM 7 ICM PHASE 18 LX_CHG 1 2 CHG
1 4
PR325 PR323

5
6
7
8
<40,45> ACOFF 1 2ACOFF-1 2 <40,46> ADP_I 100_0402_1% 2 3

1
PQ313
10K_0402_5% DH_CHG

AO4466L_SO8

4.7_1206_5%
8 VREF UGATE 17

PR326
PR327 1 2 6251VREF PR328 PC316
1

154K_0402_1% PC315 0_0603_5% 0.1U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
16251_SN
PR343 2 1 0.1U_0402_16V7K 6251_CHLIM 9 16 BST_CHG 1 2 BST_CHGA 2 1
3

<40> IREF CHLIM BOOT

1
0_0402_5% PR329 4

1
PC317

PC323

PC318
21K_0402_1% PD304
0.01U_0402_25V7K

2 6251_ACLIM 6251_VDDP
2N7002KW_SOT323-3

1 10 15 RB751V-40_SOD323-2
2

ACLIM VDDP
1

6251VREF

2
1
PC319

PQ314 PR330

680P_0603_50V7K
1 2 6251_VDD

3
2
1
1

PC320
100K_0402_1% 6251_VADJ
11 14 DL_CHG

2
VADJ LGATE

1
2 PR332 PR331
<46> BATT_OUT
2

G 2.2K_0402_1% 4.7_0402_5%
2

S 12 13 PC321
3

2
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24
B PR333 B
Connect to EC A/D Pin. 15.4K_0402_1%
1 2
<40> CHGVADJ
1

PR334
CHGVADJ=(Vcell-4)/0.10627 31.6K_0402_1%
3cell : GND
6251_VDD 6251_VDD
Vcell CHGVADJ CP mode for 65W adapter 4cell : VDD
2

4V 0V Vaclim=2.39*(2.2K/(2.2K+21K))=0.2515V 6251_VDD

2
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) PR339 PR335 PR336
4.2V 1.882V
where Vaclim=0.2515V, Iinput=2.76A 10K_0402_1% @ 100K_0402_1%@ 100K_0402_1%
1

4.35V 3.2935V 1 2 ACIN <16,24,40>

PR338

1
PR337 10K_0402_1% CELLS
CP mode for 90W adapter 47K_0402_1%

3
CC=0.25A~3A PACIN
2

1 2

Vaclim=2.39*(3.9K/(3.9K+25.5K))=0.0.3544V
IREF=1.016*Icharge PR340
Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05)
1

0_0402_5% 2 5 2 1
IREF=0.254V~3.048V where Vaclim=0.3544V, Iinput=3.827A PR341

2
PR342 @ 0_0402_5%

4
<48> ACPRN
VCHLIM need over 95mV 2 <40> BATT_SEL_EC
14.3K_0402_1%
2

PQ316
PQ315A PQ315B
DTC115EUA_SC70-3 @ 2N7002KDW -2N_SOT363-6 @ 2N7002KDW -2N_SOT363-6
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 47 of 54

5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ401
+3VALW P 2 2 1 1 +3VALW
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ402

PC402
+5VALW P 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2

PR403 PR404
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ403 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
@ JUMP_43X118 PR405 PR406
PC401

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

110K_0402_1% 154K_0402_1%
PC403

PC411
1 2 1 2

4.7U_0805_10V6K
1

1
PC404

PC405

PC406

PC408

PC409

PC410
2

8
7
6
5

5
6
7
8
PU401 PQ402
2

2
AO4466L_SO8

PC407

TONSEL
ENTRIP2

FB2

FB1

ENTRIP1
REF
1
C PQ401 C
25 P PAD
AO4466L_SO8

2
4 4
7 VO2 VO1 24
SPOK <46>
8 23 PR408 PC413
PR407 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
0_0603_5% BOOT2 BOOT1
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH +-20% PCMC063T-4R7MN 5.5A
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V LG_5V
4.7_1206_5%

4.7_1206_5%
12 LGATE2 LGATE1 19

5
6
7
8
PQ403
PR409

PR410
SKIPSEL
AO4712_SO8 PR411 @

VREG5
0_0402_5%

GND

VIN

NC
MAINPW ON 2 RT8205EGQW _W QFN24_4X4

EN
1 1 1
2

2
4
PC414 + 4 PC416 +

13

14

15

16

17

18
1

1
PR412
680P_0603_50V7K

150U_B2_6.3VM_R45M 499K_0402_1% AO4712_SO8

PC415

680P_0603_50V7K
2 PQ404 150U_B2_6.3VM_R45M 2

PC417
1 2
2

1
2
3

2
B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC418

1
PR413

PC419
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
RT8205_B+
6

1
PQ405B
PQ405A 2N7002KDW -2N_SOT363-6

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A

2
PC420
+5VALWP OCP(min)=8.44A
<45,46> MAINPWON
1

PR414
0_0402_5%
2 1

PR415
100K_0402_1%
VL 2 1
1
2N7002W-T/R7_SOT323-3

PR418
1

200K_0402_1% D
ACPRN
PQ406

2 1 2 1 2 2 PQ407
G VS DTC115EUA_SC70-3
S PR416
40.2K_0402_1%

2.2U_0603_10V7K
3

A A
1

100K_0402_1%
1

1
PR417

PC421

3
2

<40,43> EC_ON
2

2
PQ408
DTC115EUA_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

3VALWP/5VALWP
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1

WWW.AliSaler.Com PIWG1/G2(LA-6751P/LA-6753P)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 48 of 54
5 4 3 2 1
 A B C D

1 1

PJ505
1.5_51117_B+ 2 1
2 1 B+

5
6
7
8
@ JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC502

PC503
@ PC504
PQ501 680P_0402_50V7K
AO4406AL 1N SO8

2
PR503
267K_0402_1% 4
PR501 1 2
0_0402_5%
1 2
<40,44> SYSON

3
2
1
2
47K_0402_5%

PR504 PC505 PL502

PR505

0_0603_5% 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%

15

14
+1.5VP
1

1
PU501 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PC501 @

EN/DEM

NC

BOOT
.1U_0402_16V7K
1

2 13 DH_1.5V
TON UGATE

1
3 12 LX_1.5V 1
VOUT PHASE

5
6
7
8
PR506
VFB=0.75V PQ502 4.7_1206_5% + PC506
4 VDD CS 11 +5VALW AO4456_SO8 220U_6.3V_M
2 2
5 10

2
FB VDDP 2
DL_1.5V

1000P_0603_50V7K
6 PGOOD LGATE 9 4

PGND
PR507

GND

PC508
100_0603_5%

9.76K_0402_1%
PR508
1 2 @ PC509 PC507
+5VALW 47P_0402_50V8J RT8209BGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K

3
2
1

2
1 2
1

2
PC510
4.7U_0603_6.3V6K
2

PR509
+1.5VP OCP(min)=15.6A
1 2
1.8VSP max current=4A
10K_0402_1%
1

PR510
10K_0402_1%
2

PJ501
2 2 1 1

@ JUMP_43X118

PJ502 +1.5V
+1.5VP 2 1
2 1
@ JUMP_43X118
3 3

PU502 PL503 PJ504

4

PJ503 1UH_PCMC063T-1R0MN_11A_20% +1.8VSP 2 1 +1.8VS

LX_1.8V 2 1
+5VALW 2 1 10 2 1 2
PG

2 1 PVIN LX +1.8VSP @ JUMP_43X118

@ JUMP_43X118

68P_0402_50V8J
9 PVIN LX 3
1

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC512
PC511 8 SVIN
PR511

22U_0805_6.3VAM PR512
6 30K_0402_1%
2

2
FB

22U_0805_6.3VAM

22U_0805_6.3VAM
5
1 2

EN 2

1
NC

NC
TP

PC514

PC515
FB=0.6Volt
<10,26,40,44,51,52> SUSP#
PC513
11

2
1 2 EN_1.8V
2

PR513 100K_0402_1%
0.1U_0402_10V7K
2

PC516

SY8033BDBC_DFN10_3X3
1

PR514
1M_0402_5%
FB_1.8V
2
1

4
PR515 4

14.7K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title
PWR-+1.5VP/+1.8VSP
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 49 of 54
A B C D
 5 4 3 2 1

D D

B+
@ PJ601
51117_VCCSAP_B+ 2 1
2 1
JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC602

PC603
1

1
5
6
7
8
PQ601

2
AO4466L_SO8

C PR602 4 C
280K_0402_1%
1 2
+VCCSAP OCP(min)=6.28A

3
2
1
EN_VCCSAP BST_VCCSAP

PR601 PR603 PC604 PL601

15

14
1

0_0402_5% PU601 0_0603_5% 0.1U_0603_25V7K 2.2UH_PCMC063T-2R2MN_8A_20%

<51> VCCPPWRGOOD 1 2 1 2 BST_VCCSAP-1
1 2 1 2
NC

BOOT
EN/DEM

+VCCSAP
1

@ PR604 2 13 UG_VCCSAP
TON UGATE

1
47K_0402_5% PC601 1
@ 0.1U_0402_16V7K 3 12 LX_VCCSAP
2

5
6
7
8
VOUT PHASE PR605 + PC605
2

4 11 +5VALW 4.7_1206_5% 220U_6.3V_M

VDD CS PQ602

2
5 10 AO4712_SO8 2

2
PR606 FB VDDP PJ602

1
100_0603_1% +3VS 6 9 LG_VCCSAP 4 PR607 +VCCSAP 2 1 +VCCSA
PGOOD LGATE 2 1
PGND

1 2 PC606 0_0402_5% PR608

GND

+5VALW
470P_0603_50V8J 1 2 VSSSA_SENSE <10> @ JUMP_43X118

2
2

1
PR610 0_0402_5%
10K_0402_5%

13K_0402_1%

1
1

RT8209BGQW_WQFN14_3P5X3P5 PC607
7

3
2
1
1

4.7U_0805_10V6K
PR609

2
PC608 0_0402_5%
2

4.7U_0603_6.3V6K PR611
2

2 1 SA_PGOOD <40>

PR612
PR613
2K_0402_1%
1 2 1 2 VCCSA_SENSE <10>
VFB=0.75V
10_0402_5%

B B
+3VS
1

PR615
1

PR614 15K_0402_1%
30K_0402_1% PR616
10K_0402_5%
2

PQ603 PR617
2
1

D 2N7002W-T/R7_SOT323-3 10K_0402_5% PMBT2222A_SOT23-3

2 2 1
G PQ604 PR619
1

S 0_0402_5%
3

2 2 1
PC609 PR618 @ VCCSA_SEL <10>
1

@ 4700P_0402_25V7K 100K_0402_5%
2

PR620
2

@ 10K_0402_5%
2

VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required

0 0 0.9 V Yes/Yes
0 1 0.8 V Yes/Yes
1 1 0.725V No/Yes
1 1 0.675V No/Yes
A A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title
PWR +VCCSAP

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 50 of 54
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
PJ701

1
D JUMP_43X118 D
@

2
2
PU701
1 VIN VCNTL 6 +3VALW PJ702
+0.75VSP 2 2 1 1 +0.75VS
PC701 2 5
GND NC

1
4.7U_0805_6.3V6K @ JUMP_43X118

1
3 7 PC702
PR701 VREF NC

2
1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
9

2
PQ701 TP PJ703
2N7002W -T/R7_SOT323-3 G2992F1U_SO8 2 1
2 1
PR702 @ JUMP_43X118

0.1U_0402_16V7K
+0.75VSP

1
20K_0402_1% D +1.05VS_VCCPP PJ704 +1.05VS

10U_0603_6.3V6M
<6,10,44> SUSP

PC703
1K_0402_1%
1 2 2 2 2 1 1

10U_0603_6.3V6M
1

1
PC705

PC716
G

2
1
S PR703 @ JUMP_43X118

3
PC704

2
0.1U_0402_16V7K

2
C C

+1.05VS_VCCPP OCP(min)=20.75A

PJ705
1.05VS_B+ 2 1 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1 B+
@ JUMP_43X118

1
@ PC708

PC706

PC707

100U_25V_M
1

5
6
7
8
680P_0402_50V7K
PR704 +

PC717
2

2
267K_0402_1% PQ702
1 2 AO4406AL 1N SO8
PR705 2
120K_0402_1% 4
1 2
6,40,44,49,52> SUSP#
1

PR706 PC710
@ 10K_0402_1%

15

14
2

PC709 PU702 0_0603_5% 0.1U_0603_25V7K PL702

3
2
1
.1U_0402_16V7K BST_1.05VS_VCCP 1.0UH +-20% PCMC104T-1R0MN 20A
PR716

1 2 1 2
EN/DEM

NC

BOOT
2

2 1 +1.05VS_VCCPP
B DH_1.05VS_VCCP B
2 TON UGATE 13
1

1
3 12 LX_1.05VS_VCCP
VOUT PHASE

5
6
7
8
PR707
4 11 +5VALW PQ703 4.7_1206_5% 1
VDD CS AO4456_SO8

330U_X_2VM_R6M
5 VFB=0.75V 10 +

1000P_0603_50V7K
1 2
FB VDDP

PC711
PR709 DL_1.05VS_VCCP

PC712
6 PGOOD LGATE 9 4
PGND

100_0603_5% PR708 2
GND

1 2 0_0603_5%
+5VALW

1
1

1
RT8209BGQW _W QFN14_3P5X3P5
13.7K_0402_1%
7

3
2
1
1

@ PC715 PC714
PR710

PC713 47P_0402_50V8J 4.7U_0805_10V6K

2

4.7U_0603_6.3V6K 1 2
2

PR711
4.02K_0402_1%
1 2

PR714
1

10_0402_5%
<50> VCCPPW RGOOD PR713 2 1 VCCIO_SENSE <9>
PR712 1 2 +3VS
10K_0402_1%
A A
10K_0402_1%
2

PR715 @
10K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +1.05VS_VCCPP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1

WWW.AliSaler.Com PIWG1/G2(LA-6751P/LA-6753P)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 51 of 54
5 4 3 2 1
 5 4 3 2 1

PD804
RB751V-40_SOD323-2
1 2
+3VS
PR801
@ 0_0402_5%
D <25,26> PX_MODE 2 1 D

2
PR803
PD805 PR802 205K_0402_1% PJ801
RB751V-40_SOD323-2 @ 10K_0402_5% VGA_TON 1 2 VGA_IN 2 1 B+
2 1

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 2
PD801 @ JUMP_43X118

5
PR804 1SS355_SOD323-2

TPCA8065-H 1N PPAK56

1
PC802

PC803
1 2 VGA_EN 1 2 +5VALW
<15,18,25,26> PE_GPIO1

PQ801
120K_0402_1%

2
1

@ 10K_0402_1%
PC801 PR805
PC804

PR832
2 1 0.1U_0402_16V7K 0_0603_5% 4

2
<10,26,40,44,49,51> SUSP# BST_VGA 1 2BST_VGA-1
1 2
PR831
@ 120K_0402_1% 0.1U_0603_25V7K

2
PX4.0 PL801

15

14

3
2
1
1
PU801 0.88UH +-20% PCMC104T-R88MN 20A
PR801 120K 1 2

EN/DEM

NC

BOOT
+VGA_CORE
PR804 @
2 13 UG_VGA
TON UGATE

680P_0603_50V7K @ 4.7_1206_5%
PR807 3 12 SW _VGA
VOUT PHASE

PR806
100_0603_1%

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
1

330U_D2_2.5VY_R15M
1 2 VGA_V5FILT 4 11 VGA_TRIP
1 2 +5VALW

TPCA8059-H 1N PPAK56-8
+5VALW VDD CS

1
+

PC806

PC807

PC808

PC809
PR808

1VGA_SNB
2
VGA_FB 5 10 9.1K_0402_1%
FB VDDP

PQ802
1 2 PR834

2
LG_VGA 2
+3VS 2 1 6 PGOOD LGATE 9 4

PGND
PC805 10K_0402_1%

GND

PC811
4.7U_0603_6.3V6K

1
2 PR829 1
<25> VGA_CORE_PG 0_0402_5% RT8209BGQW _W QFN14_3P5X3P5 PC810

3
2
1

2
2
C 4.7U_0805_6.3V6K C

2
PR830
PC812 @ 10K_0402_1%
@ 47P_0402_50V8J @
1 2

1
1 2
PR809
2K_0402_1%
1 2
+3VALW PR810
10K_0402_1%
PR811
30K_0402_1%
1

10K_0402_1%

1 2
PR812

GVID1-2
6

PR813
10K_0402_1%
2

VGA_PWRSEL0 VGA_PWRSEL1 Robson XT

2 1GVID1-1 2 PQ803A
1

PQ803B 2N7002KDW -2N_SOT363-6

3

2N7002KDW -2N_SOT363-6 PR814 PR815 GPU_VID0 GPU_VID1 Core Voltage Level

1

@ 10K_0402_5% 8.66K_0402_1%
PC813
2

2 1 5 0.022U_0402_16V7K 1 1 0.9V
2

<24> GPU_VID1 PR816 +3VALW

2
1

10K_0402_1% GVID0-2
4

PR817 1 0 0.95V PJ804

1

10K_0402_1%

3K_0402_5% 2 1
+VGA_PCIEP 2 1 +VGA_PCIE
PR818

B 0 0 1.12 V @ JUMP_43X118 B
2

+1.5V
2

2 1GVID0-1 2 PQ804A
PR819 PC814 2N7002KDW -2N_SOT363-6 +5VALW
3

1
PQ804B 10K_0402_1% 0.022U_0402_16V7K
1

2N7002KDW -2N_SOT363-6 PR820 PJ805

1
@ 10K_0402_5% JUMP_43X79
2

2 1 5 +5VALW
<24> GPU_VID0 @

2
PR821 PC815
2
1

10K_0402_1% PD802 1U_0402_6.3V6K

4

2
PR822

2
3K_0402_5% RB751V-40_SOD323-2

1
1 2

1
PR823 PC816
2

@ 0_0402_5% 4.7U_0805_6.3V6K

6
PR824 PU802

2
47K_0402_5% 5

VCNTL
2

PE_GPIO1 VIN
<15,18,25,26> PE_GPIO1 1 2 7 POK
VOUT 4 +VGA_PCIEP
PR825 3
VOUT

1
@ 0_0402_5%

22U_0805_6.3V6M
PC818
SUSP# 1 2 8 2
EN FB
1

<10,26,40,44,49,51> SUSP# PR826

0.1U_0603_25V7K

GND

2
1
PC819

9 1.15K_0402_1%
PD803 PR827 VIN

2
1 2 @ 47K_0402_5% APL5912-KAC-TRL_SO8 VGA_PCIE 1.0V 1.1 V
2

1
2

@ RB751V-40_SOD323-2 PC817

1
0.01U_0402_25V7K
A PR828 4.53K 3K A
PR828
4.53K_0402_1%

2
Security Classification Compal Secret Data Compal Electronics, Inc.
2009/01/06 2010/01/06 Title
Issued Date Deciphered Date PWR +VGA_CORE/PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 52 of 54
5 4 3 2 1
 5 4 3 2 1

Alert# PU resister need close CPU, PC902 @ 470P_0402_50V7K CPU_B+ 1 2 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
so the PU resister in HW schematic. 2 1 NTCG PL901
B+ HCB4532KF-800T90_1812
but DAT and CLK need close PWM-IC,

5
PC917 PR915 PR902 PQ901

TPCA8065-H 1N PPAK56

1
so the PU resister in POWER schematic.

PC903

PC904
2 1 2 1 3.83K_0402_1% PH901

100U_25V_M

100U_25V_M
2 1 2 1 1 1
@ 470P_0402_50V7K @ 4.99K_0402_1%

2
1000P_0402_50V7K
8.06K_0402_1%

PC914

PC905
470KB_0402_5%_ERTJ0EV474J + +
UGATEG 4

1
1 2

1
2 2

PR903
PR904

PC901
27.4K_0402_1%
PL902

3
2
1
+VGFX_CORE .36UH 20% PCMC104T-R36MN1R105 30A +VGFX_CORE

2
PR905 PHASEG 4 1
2 1 PC907 1

5
330P_0402_50V7K

10K_0402_1%
TPCA8057-H 1N PPAK56-8

@ TPCA8057-H 1N PPAK56-8
D PC906 10_0402_1% BOOTG 2 PR906 1 2 1 PQ902 PQ903 3 2 D

470U_X_2VM_R4.5M
4.7_1206_5%
1 2 2.2_0603_5% +
1

PC910
PC911 PC912 0.22U_0603_10V7K
VCC_AXG_SENSE <10>

1 2PR907
PR901 @ 39P_0402_50V7K PR909 680P_0402_50V7K 330P_0402_50V7K @ PR908
2

PC908

PR910
499K_0402_1% 2 1 2 1 2 1 PC909 1_0402_5%
VSS_AXG_SENSE <10>

680P_0603_50V7K
422_0402_1% 2 1 LGATEG 4 4

2
PC913 PH902
2

2
PC915
150P_0402_50V8J 1000P_0402_50V7K PR913 10K_0402_5% ERTJ0ER103J
2 1 2 1 2 1 2 1 1 PR914 21 2
PR911 PR912 10_0402_1% 7.5K_0402_1%

3
2
1

3
2
1

2
475K_0402_1% 2.55K_0402_1%
1 PR917 2 .1U_0402_16V7K

ISNG
ISPG
GFXVR_IMON
1

2
PR919 11K_0402_1% PC919
18.2K_0402_1%

+1.05VS_VCCPP
0.047U_0603_16V7K
@ 16.5K_0402_1% @ 1 2 1 2
1

@.1U_0402_16V7K
PC916

PC918 .1U_0402_16V7K

UGATEG

PHASEG

LGATEG
100_0402_1%

BOOTG

470P_0402_50V7K
PR918

PC920

PC921 @ PR922

NTCG
2

1
2

2 PR920 1

1
130_0402_1%

54.9_0402_1%
1 2 1 2

@ 43_0402_1%

PC922
<10> VSS_AXG_SENSE

2 PR924 1
590_0402_1%
PR967

PR921
@ 0.01U_0402_16V7K

ISPG
1

1
Parallel and tune length For shortage changed +3VS

2
+5VS

49

48

47

46

45

44

43

42

41

40

39

38

37
2

2
@
1.91K_0402_1%
2 PR925 1ISNG

GND

COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

PROG2

BOOTG

UGG

PHG

LGG
<9> VR_SVID_DAT

1
@ 0_0402_5%
1 36 BOOT2
<9> VR_SVID_ALRT# VWG BOOT2
PR926
2 35 UGATE2
<9> VR_SVID_CLK 2 IMONG UG2
PR927 3 34 PHASE2 PR928
PGOODG PH2
+3VS 1 2 1 2 +5VS
SVID_SDA 4 33
1.91K_0402_1% GFX_CORE_PWRGD SDA VSSP2 0_0402_5%
SVID_ALERT# 5 32 LGATE2
C ALERT# LG2 PR931 C

SVID_SCLK 6 31 1 2
<9> VSSSENSE VGATE <16> SCLK VDDP

<40> VR_ON 1 PR933 2 7 30 PWM3 0_0402_5%

VR_ON PWM3
0.047U_0603_16V7K

0_0402_5% 8 29 LGATE1
IMVP_IMON PGOOD LG1
29.4K_0402_1%

ISL95831CRZ-T_TQFN48_6X6
1

2.2U_0603_10V6K
PC927
9 28
IMON VSSP1
1

PC926

1
PR936

10 27 PHASE1
VR_HOT# PH1
2

11 26 UGATE1
2

2
ISEN3/ FB2

For shortage changed NTC UG1

12 25 BOOT1

PROG1
ISUMN

ISUMP
VW BOOT1
COMP

ISEN2

ISEN1

VSEN

VDD
RTN
<40,46> VR_HOT#

VIN
PC929 @ CPU_B+
FB
1

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PR938 2 470P_0402_50V7K
1

5
PQ907

TPCA8065-H 1N PPAK56
1 2 PU901
13

14

15

16

17

18

19

20

21

22

23

24
499_0402_1% PR939 PH903
2

1
PC930

PC931
+1.05VS_VCCPP @ 1 2 1 2
3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J

2
UGATE2 4
PC928 2 1

1
47P_0402_50V8J PR940 27.4K_0402_1%
PR941
PR942
1000P_0402_50V7K
8.06K_0402_1%

change from 43P to 47P 1 2 1.69K_0402_1% PL904

CPU_B+

3
2
1
1

(Ipeak=54A) .36UH 20% PCMC104T-R36MN1R105 30A

for shortage problem

4.7_1206_5%
PR943

PC932

PHASE2 4 1 +CPU_CORE

2
2010-03-15 PC933 0_0603_5%
2

22P_0402_50V8J PR945 2.2_0603_5% 3 2

1
0.22U_0603_25V7K

PR944 PQ908 PQ909

@ TPCA8059-H 1N PPAK56-8

TPCA8059-H 1N PPAK56-8
2 1 +5VS
2

PC935

PR946
2 1 BOOT2 2 1 2 1
1U_0603_10V6K

1_0603_5%
ISEN2

ISEN1

PC934 @ 10K_0402_1% 10K_0402_1%

ISEN3

B B

680P_0603_50V7K
PC936

0.22U_0402_6.3V6K PC937 @ 0.22U_0603_10V7K PR947 PR948

1 2
2 1 LGATE2 4 4 ISEN2 2 1 2 1ISEN1
2

PC939
PC938
10P_0402_50V8J PC941
PR950
PR949 PC940 VSUM- 2 1 VSUM+ 3.65K_0402_1% 1_0402_5%

2
1 2 2 1 2 1 2 1 0.22U_0402_6.3V6K PR951 PR952

3
2
1

3
2
1
1
2.61K_0402_1%
499_0402_1% PC942 VSUM+ 2 1 2 1 VSUM-
0.068U_0402_16V7K

@ 0.068U_0402_16V7K

PR953

@ 499K_0402_1% 470P_0402_50V7K 2 1
PC943 PR954 PR955 0.22U_0402_6.3V6K @
0.22U 10V K X7R 0603

2 1 2 1 2 1
3.32K_0402_1%
1 2
1

1
11K_0402_1%
PC944

PC945

PC955

150P_0402_50V8J 316K_0402_1% CPU_B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PR957

PR956

TPCA8065-H 1N PPAK56
2 1 2 1

5
+CPU_CORE 2 1 PH904 PQ910
2

PC923 PR916 @ 10_0402_1% 10K_0402_5% ERTJ0ER103J

1
330P_0402_50V7K

PC948

PC949
@ 680P_0402_50V7K @ 2K_0402_1% PC947
2
1

2 1 PR958
2
PC946

330P_0402_50V7K 2 1 VSUM-

2
<9> VCCSENSE 1.47K_0402_1% UGATE1 4
2

.1U_0402_16V7K

2 1 PC951 PR959
<9> VSSSENSE
PC952

PC950 2 1 2 1
PR960 1000P_0402_50V7K @ 100_0402_1%
2

2 1 @ 330P_0402_50V7K PL905

3
2
1
@ 10_0402_1% .36UH 20% PCMC104T-R36MN1R105 30A
PHASE1 4 1 +CPU_CORE

4.7_1206_5%
5

5
PR961 PQ911 PQ912 10K_0402_1% 10K_0402_1%

@ TPCA8059-H 1N PPAK56-8
3 2

1
PR962
TPCA8059-H 1N PPAK56-8
2.2_0603_5% PC953 PR963 PR964
BOOT1 2 1 2 1 ISEN1 2 1 2 1 ISEN2
*Iccmax in Turbo Mode for SV (35W) is 53A
0.22U_0603_10V7K

680P_0603_50V7K
LGATE1 4 4 @ 3.65K_0402_1% 1_0402_5%

1 2
+CPU_CORE +VGFX_COREP PR965 PR966

PC954
VSUM+ 2 1 2 1 VSUM-
A A
Icc-max=53A Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A
3
2
1

3
2
1

2
Rdson=3.6~4.5m ohm Rdson=3.6~4.5m ohm
DCR=1.1m ohm DCR=1.1m ohm
HW output cap: HW output cap: @
(1)10U_0805_4V *10 (1)22U_0805_6.3V *12
(2)22U_0805_6.3V *15 (2)470U_D2_2V *2(ESR=4.5m ohm)
(3)470U_D2_2V *4(ESR=4.5m ohm) Security Classification
2010/01/25
Compal Secret Data
2010/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date PWR +CPU_CORE/+VGFX_CORE

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
*OCP setting value=71.5A *OCP setting value=37A Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2(LA-6751P/LA-6753P)
Date: Friday, November 26, 2010 Sheet 53 of 54
5 4 3 2 1
 5 4 3 2 1

9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

IRU3:5
,WHP 5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH

To reduce charger ripple 47 Add PC323 DVT

 2010.08.15
D D
Change +VGA_PCIE enable signal from PX_MODE to PE_GPIO1
 51
PR804:120K
2010.08.15
HW request for power sequence PR831,PR801,PR825 UN-POP DVT
PR824:47K
PC819:0.2uF

 Change Vboot setting 52 Change PR942 as 4.32K 2010.08.15 DVT

 Change OCP setting 52 Change PR958 as 1.47K 2010.08.15 DVT

 Add PC955 for loadline adjust 52 Add PC955 2010.08.15 DVT

 Reserve pull low resistor 51 Add PR718,PR832 2010.09.29 PVT

 Remove jump 51 Remove PJ802,PJ803 2010.09.29 PVT

C C

Pop PR222,PR208,PH202,PR221,PQ204 2010.09.29 PVT

 Adapter protect circuit 46 Un-Pop PR223,PR203
Remove PJ301
 EMI Request
47 Add PL302 and reserve PC324 2010.09.29 PVT




B B












A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)

WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIWG1/G2
Date: Friday, November 26, 2010 Sheet 54 of 54
5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN# 2
U14,+3VALW_PCH

V
AC A1
MODE VIN QH4,+5VALW_PCH

V V
A2 A3 B5

VV
PU2 A5 2

V
PU3

V
B+ +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE
B1
B2
B+ B4 V

V
V 4 SYS_PWROK
EC
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#

V
V
ON/OFF V
SYSON 7 SYSON# +1.5V

V
PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU

V
Q6 11
SUSP#,SUSP 8
U49

V
VGATE
+5VS

V
+1.5VSDGPU
U40

V
U20

V
+3VS +1.8VSDGPU VGA
U37
B B

V
U13

V
+1.5VS +1.0VSDGPU
PU28

V
PU8

V
+0.75V +VGA_CORE
VCCPPWRGOOD
PU998
V

V
PU9 PU7
+1.05VS_VCCP +VCCSA 8b (DIS)
VGA_PWROK

U47
CK505
VR_ON 9 PU1000
V
10
V

+CPU_CORE

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
Date: Friday, November 26, 2010 Sheet 55 of 59
5 4 3 2 1
 5 4 3 2 1

INT_KBD Conn. ME@ +3VALW 1

R614
2
0_0402_5%
+VCC_LID R615 1 2 100K_0402_5% Kill
KSI[0..7] STATUS
KSI[0..7] <40,57> ACES_88514-2401
KSO[0..15] 26
1,2(LOW) OFF
KSO[0..15] <40,57> GND2

2
S-5711ACDL-M3T1S_SOT23-3
25 GND1
1
2,3(HI) ON

VDD
KSI1 24
KSO2 C668 1 24
2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSI7 23 23
C694
KSI6 22 0.1U_0402_16V4Z 3
22 2 OUTPUT LID_SW # <40,57>
KSO15 C670 1 2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSO9 21
KSI4 21
20
Lid Switch

GND
D
KSO6 C672 1 2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSI5
KSO0
19
20
19 2
+3VALW
Kill Switch D

18 18
KSO8 C674 1 2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSI2 17 U32 C695 100K_0402_5% LSSM12-P-V-T-R_3P

1
KSI3 17 10P_0402_50V8J
16 16 2 R616 1 3 3
KSO13 C676 1 1
2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J KSO5 15 15
KSO1 14 2
KSO12 C678 1 14 <14,57> KILL_SW # 2
2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSI0 13 13 KILL_SW#
KSO2 12
KSO11 C680 1 12
2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO4 11 11 1 1
KSO7 10
KSO10 C682 1 10
2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J KSO8 9 9 8/23 Change LED1/LED3/LED4 P/N to SC50000A300
KSO6 8
KSO3 C684 1 8
2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J KSO3 7 SW 2

KSO4 C686 1 2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J

KSO12
KSO13
6
5
7
6 LED White
LED1

KSO14 5
4 4 <40,43,57> PW R_LED# 1 2 2 1 +5VALW
KSI0 C688 1 2 @ 100P_0402_50V8J KSO9 C689 1 2 @ 100P_0402_50V8J KSO11 3 300_0402_5% R622
KSO10 3
2 2
KSO0 C690 1 2 @ 100P_0402_50V8J KSI1 C691 1 2 @ 100P_0402_50V8J KSO15 1 19-213A-T1D-CP2Q2HY-3T_W HITE
1
Reserve for ESD. Orange LED2
JKB1
BATT_LOW_LED# 1 2 2 1
<40,57> CHARGE_LED1# +3VALW
CONN PIN define need double check 470_0402_5% R764
ZZZ
Left --> White HT-191UD5_AMBER
+5VS Right --> Orange Change design to two LED
LED5 20101005
C C
1 2 2 1
To TP/B Conn. C696 ACES_88058-060N
DAZ0GL00100
<40,57> CHARGE_LED0#
BATT_CHG_LED# 300_0402_5% R765
+5VALW

White 19-213A-T1D-CP2Q2HY-3T_W HITE

8 GND
0.1U_0402_16V4Z 7 ZZZ1 ZZZ2 ZZZ3
GND
6 6
TP_CLK 5 LED3
<40,57> TP_CLK 5 D19
TP_DATA 4 @ White
<40,57> TP_DATA 4
1 1 SW /L 3 <34,57> W LAN_LED# 1 2 1 2 2 1 +5VS
@ @ SW /R 3 300_0402_5% R625
2 2 PCB PCB PCB
C697 C698 1 RB751V_SOD323
100P_0402_50V8J 100P_0402_50V8J 1 DA80000KF10 DA40000VV10 DA40000VS10 19-213A-T1D-CP2Q2HY-3T_W HITE
2 2 D20
JTP1 @
DA8@ DA4@ DA4@ <42,57> BT_LED# 1 2

RB751V_SOD323

<40,57> RF_LED# 1 2
+5VALW R679 0_0402_5%
6
5

SMT1-05_4P TP_CLK LED4

2 4 TP_DATA White
SW /L <14,57> HDD_LED# 1 2 2 1 +5VS
1 3 +USB_VCCA 300_0402_5% R626
3

U36
D15 1 8 RIGHT USB PORT X1 19-213A-T1D-CP2Q2HY-3T_W HITE
SW 4 C713 0.1U_0402_16V4Z GND OUT
PSOT24C_SOT23-3 2 IN OUT 7
@ 2 1 3 IN OUT 6
B USB_ON# 4 B
<38,40,42,57> USB_ON# EN OC# 5 USB_OC0# <18,38,57>
Right USB Conn.
1
6
5

SMT1-05_4P APL3510BKI_SO8
2 4 1
SW /R C716 +USB_VCCA 8/27 change to @
@ 1000P_0402_50V7K
W=80mils JUSB3
1 3
+USB_VCCA 1
2 USB20_N0 1
SW 5 CONN PIN define need double check <18,57> USB20_N0 2 R868 @1 0_0402_5% USB20_N0_C 2 2
1 1 USB20_P0 2 R869 @1 0_0402_5% USB20_P0_C 3
<18,57> USB20_P0 3
4 4
C714 + C715 5
JODD1 470P_0402_50V7K G5
6 G6
150U_B2_6.3VM_R35M 2
2 ACES_85205-04001
1 GND
SATA_ITX_DRX_P2_CONN 2 ME@
SATA ODD Conn. <14,57> SATA_ITX_DRX_P2_CONN
<14,57> SATA_ITX_DRX_N2_CONN SATA_ITX_DRX_N2_CONN 3
A+
A-
4 GND 8/27 change to stuff
SATA_DTX_C_IRX_N2 C605 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2 5
<14,57> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C606 1 B-
<14,57> SATA_DTX_C_IRX_P2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 6 B+ 8/23 change C714 P/N to SGA00002N80 USB20_N0_C
7 W CM-2012-900T_4P
GND USB20_N0 USB20_N0_C USB20_P0_C
4 4 3 3

2
ODD_DETECT# R710 1 2 0_0402_5% 8

PJDLC05_SOT23-3
DP USB20_P0 USB20_P0_C D25
+5V_ODD 9 +5V 1 1 2 2
10 @
ODD_DA# +5V L66
<18,40,57> ODD_DA# 1 2 11 MD
R554 0_0402_5% 12 15
R555 GND GND
13 GND GND 14
A +3VS 1 2 A
10K_0402_5%
ALLTO_C18518-11305-L

1
8/13 update JODD1 symbol ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 56 of 59
5 4 3 2 1
 5 4 3 2 1

JKB1 ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5

KSI1 1
KSI7 1
2 2
KSI[0..7]
INT_KBD
KSI[0..7]
<40,56> Conn. KSI6
KSO9
3
4
3
4
KSO[0..17] KSO16 C693 1 2 @ 100P_0402_50V8J KSI4 5
KSO[0..17] <40,56> 5
KSI5 6 DAZ0GM00100 PCB PCB PCB PCB PCB
KSO17 C692 1 6
2 @ 100P_0402_50V8J KSO0 7 7
KSI2 8 DA80000KG10 DA40000VV10 DA40000VS10 DA40000VT10 DA40000VU10
KSO2 C668 1 8
2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSI3 9 9
KSO5 10 DA8@ DA4@ DA4@ DA4@ DA4@
KSO15 C670 1 10
2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSO1 11 11
D KSI0 12 D
KSO6 C672 1 12
2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSO2 13 13
KSO4 14
KSO8 C674 1 14
2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO7 15 15
KSO8 16
KSO13 C676 1 16
2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J KSO6 17 17
KSO3 18
KSO12 C678 1 18 +5VALW
2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSO12 19 19
KSO13 20
KSO11 C680 1 20
2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO14 21 21
KSO11 22
KSO10 C682 1 22 +USB_VCCA
2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J KSO10 23 23
KSO15 24 U36
KSO3 C684 1 24
2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J <40> KSO16
KSO16 25 25 1 GND OUT 8 RIGHT USB PORT X1
KSO17 26 C713 0.1U_0402_16V4Z 2 7
<40> KSO17 26 IN OUT
KSO4 C686 1 2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J 27 2 1 3 6
27 USB_ON# 4 IN OUT
28 28 <38,40,42,56> USB_ON# EN OC# 5 USB_OC0# <18,38,56>
KSI0 C688 1 2 @ 100P_0402_50V8J KSO9 C689 1 2 @ 100P_0402_50V8J 29 31
29 GND APL3510BKI_SO8
30 30 GND 32
KSO0 C690 1 2 @ 100P_0402_50V8J KSI1 C691 1 2 @ 100P_0402_50V8J 1
ACES_88514-3001 C716
@ 1000P_0402_50V7K
CONN PIN define need double check Reserve for ESD. ME@ 2

+5VS

C Right USB Conn. C

To TP/B Conn. C696 +USB_VCCA

W=80mils 8/27 change to @
JUSB3
0.1U_0402_16V4Z +USB_VCCA 1
JTP1 USB20_N0 1
<18,56> USB20_N0 2 R868 @1 0_0402_5% USB20_N0_C 2 2
1 1 1 USB20_P0 2 R869 @1 0_0402_5% USB20_P0_C 3
1 <18,56> USB20_P0 3
TP_CLK 2 4
<40,56> TP_CLK 2 + 4
TP_DATA 3 C714 C715 5
<40,56> TP_DATA 3 G5
1 1 SW /L 4 470P_0402_50V7K 6
@ @ SW /R 4 220U_6.3V_M 2 G6
5 5
C697 C698 2 ACES_85205-04001
6 6
100P_0402_50V8J 100P_0402_50V8J ME@
2 2
7 GND
8 GND 8/14 change to OSCAN 220U 8/27 change to stuff
ACES_88058-060N USB20_N0_C
W CM-2012-900T_4P
(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00) USB20_N0 4 3 USB20_N0_C USB20_P0_C
ME@ 4 3
6
5

2
SMT1-05_4P TP_CLK

PJDLC05_SOT23-3
2 4 TP_DATA USB20_P0 1 2 USB20_P0_C D25
SW /L 1 2 @
1 3 L66
3

D15
SW 4
PSOT24C_SOT23-3
@

1
B B
1
6
5

SMT1-05_4P
2 4
SW /R
1 3
JP13
SW 5 CONN PIN define need double check @
D19
White RF_LED#_R
+5VALW 1 1
<34,56> W LAN_LED# 1 2 +3VALW 2 2
+5VS 3 3
RB751V_SOD323 4
<40,56> LID_SW # 4
5
SATA ODD FFC Conn. JP2
@
D20
<40,43,56> PW R_LED# 6
5
6
<42,56> BT_LED# 1 2 <40,56> CHARGE_LED1# 7 7
<14,56> SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_P2_CONN 1 <40,56> CHARGE_LED0# 8
SATA_ITX_DRX_N2_CONN 1 RB751V_SOD323 RF_LED#_R 8
<14,56> SATA_ITX_DRX_N2_CONN 2 2 9 9
3 3 <14,56> HDD_LED# 10 10
SATA_DTX_C_IRX_N2 C605 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2 4 <40,56> RF_LED# 1 2 11
<14,56> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C606 1 4 11
<14,56> SATA_DTX_C_IRX_P2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 5 5
R679 0_0402_5%
<14,56> KILL_SW # 12 12
ODD_DETECT# R710 1 2 0_0402_5% 6 6
+5V_ODD 7 7
8 8
ODD_DA# 1 2 9
<18,40,56> ODD_DA#
R555
R554 0_0402_5% 10
9
10 For 15" M/B to LED/B 13
14
GND1
GND2
+3VS 1 2 11 GND
10K_0402_5% 12 KILL_SW # R884 1 @ 2 100K_0402_5% +3VALW R615 1 2 100K_0402_5%
GND ACES_88514-01201-071
LID_SW #
A
ACES_87056-01001-001
11/16modify 7/22 modify A
ME@

ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 57 of 59
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE Modification list PURPOSE

0.2 P31 Change CRT Symbol For CRT footprint issue
0.2 P31 Del C510 For Non-used part
0.2 P39 change C610 pin 1 net name change C610 pin 1 net name to correct
0.2 P35 U25 change to U26 For co-lay 10/100 and GIGA
0.2 P32 Add R735,R736 For DIS only SMBus pull high
0.2 P33 Add R738,R739 For DIS only SMBus pull high
D D
0.2 P33 Change Q63 BOM structure to HDMI@ For DIS HDMI function
0.2 P40 Add R740, C93 For EC request
0.2 P18 Change R215 pin1 net name Change R215 pin1 net name to correct
0.2 P18 Add R741 Add R741 for Reserved PE_GPIO0
0.2 P16 Add R742, R743 For PCH power sequence
0.2 P38 Del U28, R542~R551 , J12 Del USB charger circuit
0.2 P40 Add EC pin 97,98,103 Add EC pin 97 for SYS_PWROK_EC , pin 98 for CE_EN , pin 103 for BATT_SEL_EC
0.2 P24 Change R662 pin 2 net name Change R662 pin 2 net name to correct
0.2 P28 Del C421,C422,C431,C432,C433, L27, Add R745, U8 pin N11,N12 change to NC For AMD new document suggestion
0.2 P26 Add R744 Add R744 for control PE_GPIO1 from SUSP#
0.2 P39 Change J10 footprint and Add J13 Change J10 footprint by DFx request and Add J13 by vendor suggestion
0.2 P39 Change PC_Beep circuit Change PC_Beep circuit
0.2 P6 Add R161, R182, R192 BOM structure hange to @ Follow ORB circuit
0.2 P58/59 Add R615 in 15" and 17" page Pull high LID_SW# at M/B side
C 0.2 P31 Add Q83 pin 1 power net name +CMOS_PW For power trace net C

0.2 P56/57/58 Change JP21 to JKB1 Change connector to standard name

0.2 P56/57/58 Change JP4 to JTP1 Change connector to standard name
0.2 P43/60 Change JP6 to JPWRB1 Change connector to standard name
0.2 P34 Change JP1 to JWLN1 Change connector to standard name
0.2 P42 Change JP5 to JBT1 Change connector to standard name
0.2 P43/60 Change JP7 to JCR1 Change connector to standard name
0.2 P19 Add R542 For ESATA detect function
0.2 P42 Add R886, R887 , C735 For ESATA detect function
0.2 P31 Add R543 For reserve EC control directly
0.2 P39 Change J10 footprint, Del C635, C636 Change J10 for DFx and Del component for layout
0.2 P42 Add R877 For reserve EC control directly
0.2 P42 SW3 BOM structure change to @ For ME ASSY concern
0.2 P24 R324 BOM structure change, del @ For AMD update
B
0.2 P25 Change Q69,Q70,Q71,Q72 to BSS138, change Q66,Q67 pin 1 net name, D28 change to @ For Change BACO part follow AMD reference DATA ,D28 change to @ for leakage B

0.2 P42 Change ESATA from port 5 to port 4 For intel risk
0.2 P15 Add R544,R545 For Pull high SMBus
0.2 P12/13 Del R74~R80,R82 R88~R94,R96 For DDR3 DM Bus to GND
0.2 P16 Add R182,R546 Add 186 for reserve sequence, Add R546 for follow CRB & ORB
0.2 P20 Del Add J12, R257 change to @ For voltage drop
0.2 P26 R161 Change Q6 to U14 Change SI2301 to SI4800 for loading current
0.2 P6 R161 change to 100K Follow CRB
0.2 P19 Add R547 , R250 change to @ Follow Module and CRB
0.2 P18 WLAN USB port for port8 to port9 For debug port
0.2 P25 AND Gate power change to +3VGS For VGA circuit
0.2 P24 Add R548, R549 For DIS HDMI audio strap
0.2 P39 Del J13 For layout space
0.2 P20,39,42 Add C395 , R581 , R583 , R584 , R586 , R587 For customer request reserved
0.2 P20 Add C129, C396 , Del R264 For reserved
A A
0.2 P40 Add PIN 66 , R740,C93 change to @ Add IMVP_IMON
0.2 P9 Add R74 For VCCIO_SENSE / VSSIO_SENSE differential routing

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 58 of 59
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE Modification list PURPOSE

0.2 P33 Del RQ51 ~ Q54 Add Q95 For DIS HDMI
0.2 P39 Del J10, C637,C640,R576,R577,R579 change to @ , L40~L43 change to R720~R723 For Vendor suggestion and EMI
Del C643, R578 , MIC_INR connect MIC_INL , Add R578 Del C653, R578 connect MIC_INR/L for vendor suggestion , Add R578 for EMI
0.2 P20 Add L75 , R264 , C917, R259 C226 change to @ For intel PDDG update
0.2 P20 Change JCR1 pin define , MIC change with HP For correct ID
0.2 P9 Add C394, C397 ,C400 ,Add R75 For CPU_CORE power reserved at Bottom side, Add R75 for reserved at cpu side and pwr side
D D
0.2 P26 Add R688 change to 20k, R345 change to 200k , R350 change to 330k , Q65 stuff For VGA power sequence
0.2 P42 Change C706 P/N to SF000001500 Change to H=6 OSCAN
0.2 P10 Change C128 to @ For Reserved
0.2 P26 Change D3 change to @ For VGA leakage
0.2 P25 Change BIF_VDDC control pin net name For correct behavior
0.2 P56 Update JODD1 symbol For ME update drawing
0.2 P16 D29 change to @ For AC detect issue
0.2 P24 R548,R549 change to DIS@ For AC detect issue
0.2 P10 C128 change to stuff For test on DVT
0.2 P44 Del Q118, R657 For not need
0.2 P57 Change 15" C714 to OSCAN For ME Space ok
0.2 Change R513, R516 ,R667 P/N and from 0805 to 0603 For common part
0.2 Change C633, C634 , C642 For common part
0.2 Change D3, D29 P/N and symbol For common part
C 0.2 Change U3,U11,U13,U14,U38,U39 P/N and symbol For common part C

0.2 Change U3,U11,U13,U14,U38,U39 P/N and symbol For common part

0.2 Change Q8,Q65,Q80,Q83,Q99,Q104 P/N and symbol For common part
0.2 Change Q1,Q37,Q93 P/N and symbol For common part
0.2 Change Q94, Q95 P/N and symbol For common part
0.2 Change Q3,Q4,Q7,Q9,Q66,Q67,Q68,Q73,Q74,Q75,Q76,Q77,Q78, For common part
Q79,Q82,Q85,Q86,Q87,Q102,Q106,Q107,Q108,Q109,Q110,Q111,Q112,Q113,Q114,Q115,Q116
P/N and symbol

0.2 P43 Change C635 part and change to @ For EMI

0.2 P18 Reserved R551 Reserved
0.2 P9 Change C53,C85,C86,C87 ,C394,C397,C400 to stuff and For CPU_CORE
change C48,C80,C81,C82,C89,C90,C91 to @
0.2 P10 Change C110,C111,C112,C113 to stuff For VGFX_CORE
0.2 P56 Change LED1/LED3/LED4 P/N to SC50000A300 Change P/N
0.2 P36 Change T1,T2 P/N to SP050003N00 For test pass part
B B
0.2 P40 Change R611,R740,C93 to stuff and change Y5,C347,C367 to @ For SUS_CLK
Change R695 to 18K, Q37 change to @, R747 change to stuff, R695 for Board ID, Q37, R747 for VR_HOT
0.2 P41 Change U33 P/N to SA00003FL10 For BIOS ROM
0.2 Change C509,C511,C635 to stuff For EMI request
0.2 P56 Change 14" C714 P/N to SGA00002N80 For Sourcer request
0.2 P39 Change R720,R721,R722,R723 P/N to SM01000BZ00(Bead), and For EMI request
Change C647,C649,C650,C651 to Stuff
0.2 P19 Change R303 to Stuff, and change R542 to @ For BIOS ESATA detect function
0.2 P56 Change U32 P/N to SA000031C00 For common part
0.2 P36 Change T1,T2 P/N to SP050006E00 For correct part
0.2 P10 R688 change to stuff , R687 ,Q7 change to @ For S3 power reduction
0.2 Change R660,R661,R862,R863,R864,R865,R868,R869 to @ , change For EMI
L63,L64,L65,L66 to stuff , change R619 to Bead (SM01000DI00)
0.2 P20 Change L75 symbol For common part

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 59 of 59
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE Modification list PURPOSE

0.3 P10 Update Q5 symbol For update symbol
0.3 P33 Add F2 For safty request
0.3 P39 Update U30 P/N to SA00003K410 and Add R879 For Audio update to 21Z
0.3 P10 Change C128 to D2 size and @ Change size for M/E issue
0.3 P14 Add reserve R878 For Intel DG 1.5
D 0.3 P37 C592 change P/N to SF000001500 (H=6) For ME Z high ok D

0.3 P25 Update Q69~Q72 to AO3414 ,D28 R873 change to BACO@ , U40 change to @ For PX4.0
0.3 P28 Add reserve C94 For reserve VGA_CORE
0.3 P29 R369 P/N change to SD034100A80 For GP part
0.3 P18 R553,R691,R684,R682,U12 change to PX@ For PX 4.0
0.3 P6 Reserved R880 to SYS_PWROK Follow ORB
0.3 P10 R62,R63 change to 1K Follow CRB
0.3 P19 R303 change to @, Change M/B ID to PX4.0 For ESATA and PX4.0
0.3 P25 Q69~Q72 change to BACO @ For PX4.0
0.3 P26 R719 change to stuff, R744 change to @ , R677 change to BACO@ For PX4.0
0.3 P33 R483,R484 change connect to +5V_HDMI_F For Add F2
0.3 P37 Change U27 P/N to SA000046C00 For Fintek
0.3 P40 Change R594 pull high to +5VALW For leakage issue
0.3 P19 R881 change to Dtuff, R244 change to @ For intel MRC Rev0.9
0.3 P14 R878 change to stuff For intel DG 1.5
C C
0.3 P31 Del R432 For non-used part
0.3 P36 Reserved D31 , C643 , C644 For reserved EMI parts
0.3 P37 Del R581 For non-used part
0.3 P38 Del R550 For non-used part
0.3 P38 Change C592 P/N to SF000002Y00 For M/E Z high limlt
0.3 P39 Del R584, R586 , R587 For non-used part
0.3 P40 Change R600, R604 to 2.2K Change R695 to 8.2k Change R600, R604 for Battery SMBus, R695 for Board ID
0.3 P42 Del R583 For non-used part
0.3 P6 Reserved R882 connect to PCH_PWROK Reserved for intel
0.3 P56 R765 change to 300 ohm For LED
0.3 P25 R324, R744 , R674 change DIS@ For DIS only sku

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2

WWW.AliSaler.Com LA-6751P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 26, 2010 Sheet 60 of 60
5 4 3 2 1