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ZZZ1 ZZZ3 ZZZ4 ZZZ5

LA5972P_LS5971P_LS5083P LA5972P LS5971P LS5083P

DAZ@ DAZ@ DAZ@
1 1

Compal Confidential
2 2

NAWA2 Schematics Document

AMD Tigris: Caspian Processor with RS880M/SB710/Park-S3 & M93-S3

3
2009-11-26 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 1 of 49
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 A B C D E

Compal Confidential
VRAM 512MB
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Tigris
AMD S1G3 Processor
Model Name : NAWA1 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
64M16 x 4 Fan Control uPGA-638 Package
page 19 page 37 Dual Channel BANK 0, 1, 2, 3 page 8,9
Caspian page 4,5,6,7 1.8V DDRII 667 (800)
1
DDR3 800MHz 1
Hyper Transport Link 5 in 1 socket
LCD (LED BL) ATI PARK-S3 & M93-S3 16 x 16 page 29

uFCBGA-631 PCI-Express 16x

page 21
Page 14,15,16,17,18
Gen2 Thermal Sensor Clock Generator
ATI RS880M Card Reader
CRT ADM1032 SLG8SP626VTR
WINBOND page 6 page 20 RTS5138
page 22
uFCBGA-528 page 29

PCI-Express 1x
page 10,11,12,13 page 32 page 32 page 31 page 32 page 31

USB CMOS Bluetooth USB Mini

MINI Card x1 LAN(10/100)/1000 A link Express2 conn conn card
Camera Conn
WLAN AR8131/AR8132 X2 X1 (WL)X1
page 31 page 30 USB port 0,1 USB port 7 USB port 8 USB port 3 USB port 5 USB port 2
port 2 port 3
2
ATI SB710 3.3V 48MHz USB
2

RJ45 3.3V 24.576MHz/48Mhz HD Audio

page 30 uFCBGA-528
page 23,24,25,26,27 S-ATA

HDA Codec MIC

CX20671
page 36 page 36

LPC BUS SATA HDD CDROM

Conn. page 28 Conn.
page 28
port 0 port 1 Phone Jack x2
page 36

ENE KB926
3 page 33 3

Touch Pad Int.KBD

page 34 page 34

Power Board
BIOS
page 35
page 34

DC/DC Interface.
page 38

Power Circuit
4
page 39,40,41,42,43, 4
44,45,46,47,48

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 2 of 49
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 A B C D E

Voltage Rails
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BTO Option Table
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
BTO Item BOM Structure
VIN Adapter power supply (19V) N/A N/A N/A Discrete VGA@ Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A PARK PARK@ S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF M93 M93@
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF HDT debug HDT@ S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF UMA UMA@ S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF 1
OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF Wireless LAN WLAN@
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Blue Tooth BT@ S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF Camera CMOS@
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF New Card New Card@
NAWA1_UMA : UMA@/WLAN@/BT@/CMOS@/NEW CARD@
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF VRAM X76@
NAWA1_DIS : VGA@/M93@/WLAN@/BT@/NEW CARD@/CMOS@/X76@
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF UNPON @
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V for CPU_VDDA ON OFF OFF
PARK-S3 power on sequence
+3VALW 3.3V always on power rail ON ON ON*
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+3VS_VGA
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON* +VGA_CPRE
+RTCVCC RTC power ON ON ON
+1.1VS_VGA
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+1.8VS_VGA

External PCI Devices RS880M power on sequence

Device IDSEL# REQ#/GNT# Interrupts

+3VS
(AVDD, VDD33)

+1.8VS
+1.1VS PLL Rails
(PLLVDD, IOPLLVDD)
+NB_CORE

EC SM Bus1 address EC SM Bus2 address

3 3

Device Address HEX Device Address HEX

Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H
GMT G781-1 (GPU) 1001 101X b 9AH
SB-Temp Sensor 9CH

SB710 SB710
SM Bus 0 address SM Bus 1 address
Device Address HEX Device Address
New card
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626)
DDR DIMM1 1001 000Xb 90
DDR DIMM2 1001 010Xb 94
Mini card

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 3 of 49
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 A B C D E

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1 1

+1.2V_HT
VLDT CAP.
250 mil

1 1 1 1 1 1 1
C755 C727 C666 C725 C726 C722 C668
H_CADIP[0..15] H_CADOP[0..15] 10U_0805_6.3V4Z 10U_0805_6.3V4Z 10U_0805_6.3V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
(10) H_CADIP[0..15] H_CADOP[0..15] (10)
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2 2
(10) H_CADIN[0..15] H_CADON[0..15] (10)

Near CPU Socket

+1.2V_HT +1.2V_HT
JCPU1A
2 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
C664 10U_0805_6.3V4Z
VLDT=1.5A D2
D3
VLDT_A1 VLDT_B1
AE3
AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 W3
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 V1
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 U2
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 AD4
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 AD3
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 AD5
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 AC5
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 AB4
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 V4
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15

(10) H_CLKIP0 J3 Y1 H_CLKOP0 (10)

L0_CLKIN_H0 L0_CLKOUT_H0
(10) H_CLKIN0 J2 W1 H_CLKON0 (10)
L0_CLKIN_L0 L0_CLKOUT_L0
(10) H_CLKIP1 J5 Y4 H_CLKOP1 (10)
L0_CLKIN_H1 L0_CLKOUT_H1
(10) H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 (10)

(10) H_CTLIP0 N1 R2 H_CTLOP0 (10)

L0_CTLIN_H0 L0_CTLOUT_H0
(10) H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 (10)
(10) H_CTLIP1 P3 T5 H_CTLOP1 (10)
L0_CTLIN_H1 L0_CTLOUT_H1
(10) H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 (10)

6090022100G_B ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G3 HT I/F
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 4 of 49
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PLACE CLOSE TO PROCESSOR
Processor DDR2 Memory Interface
WITHIN 1.2 INCH
JCPU1C
(9) DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] (8)
DDRA_CLK0 DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
C888 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2

1.5P_0402_50V9C DDRB_SDQ4 G11 H11 DDRA_SDQ4

R78 DDRA_CLK0# 2 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 H12
1K_0402_1% DDRB_SDQ6 MB_DATA5 MA_DATA5 DDRA_SDQ6
D12 MB_DATA6 MA_DATA6 C13
DDRA_CLK1 DDRB_SDQ7 A13 E13 DDRA_SDQ7
DDRB_SDQ8 MB_DATA7 MA_DATA7 DDRA_SDQ8
1 A15 H15
1

+MCH_REF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9

A16 MB_DATA9 MA_DATA9 E15
1000P_0402_25V8J
0.1U_0402_16V4Z

C891 DDRB_SDQ10 A19 E17 DDRA_SDQ10

MB_DATA10 MA_DATA10
2

1 1 1.5P_0402_50V9C DDRB_SDQ11 A20 H17 DDRA_SDQ11

2 MB_DATA11 MA_DATA11
C178

C177

R79 DDRA_CLK1# DDRB_SDQ12 C14 E14 DDRA_SDQ12

1K_0402_1% DDRB_SDQ13 MB_DATA12 MA_DATA12 DDRA_SDQ13
D14 MB_DATA13 MA_DATA13 F14
DDRB_SDQ14 C18 C17 DDRA_SDQ14
2 2 DDRB_CLK0 DDRB_SDQ15 MB_DATA14 MA_DATA14 DDRA_SDQ15
D18 G17
1

DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16

1 D20 G18
DDRB_SDQ17 MB_DATA16 MA_DATA16 DDRA_SDQ17
A21 MB_DATA17 MA_DATA17 C19
C890 DDRB_SDQ18 D24 D22 DDRA_SDQ18
1.5P_0402_50V9C DDRB_SDQ19 MB_DATA18 MA_DATA18 DDRA_SDQ19
C25 MB_DATA19 MA_DATA19 E20
DDRB_CLK0# 2 DDRB_SDQ20 B20 E18 DDRA_SDQ20
DDRB_SDQ21 MB_DATA20 MA_DATA20 DDRA_SDQ21
C20 F18
DDRB_CLK1 DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 B22
DDRB_SDQ23 MB_DATA22 MA_DATA22 DDRA_SDQ23
1 C24 MB_DATA23 MA_DATA23 C23
DDRB_SDQ24 E23 F20 DDRA_SDQ24
C889 DDRB_SDQ25 MB_DATA24 MA_DATA24 DDRA_SDQ25
E24 F22
1.5P_0402_50V9C DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
G25 MB_DATA26 MA_DATA26 H24
DDRB_CLK1# 2 DDRB_SDQ27 G26 J19 DDRA_SDQ27
DDRB_SDQ28 MB_DATA27 MA_DATA27 DDRA_SDQ28
C26 E21
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+0.9V +0.9V DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
G24 H22
JCPU1B DDRB_SDQ32 MB_DATA31 MA_DATA31 DDRA_SDQ32
AA24 Y24
2 DDRB_SDQ33 MB_DATA32 MA_DATA32 DDRA_SDQ33 2
VTT=0.75A DDRB_SDQ34
AA23 MB_DATA33 MA_DATA33 AB24
DDRA_SDQ34
D10 W10 AD24 AB22
VTT1 MEM:CMD/CTRL/CLK VTT5 DDRB_SDQ35 MB_DATA34 MA_DATA34 DDRA_SDQ35
Place them close to CPU within 1" C10
VTT2 VTT6
AC10 AE24
MB_DATA35 MA_DATA35
AA21
B10 AB10 DDRB_SDQ36 AA26 W22 DDRA_SDQ36
VTT3 VTT7 DDRB_SDQ37 MB_DATA36 MA_DATA36 DDRA_SDQ37
AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21
R77 39.2_0402_1% A10 DDRB_SDQ38 AD26 Y22 DDRA_SDQ38
VTT9 DDRB_SDQ39 MB_DATA38 MA_DATA38 DDRA_SDQ39
1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
1 2 AE10 Y10 VTT_SENSE DDRB_SDQ40 AC22 Y20 DDRA_SDQ40
+1.8V MEMZN VTT_SENSE PAD T4 MB_DATA40 MA_DATA40
R76 39.2_0402_1% DDRB_SDQ41 AD22 AA20 DDRA_SDQ41
+MCH_REF DDRB_SDQ42 MB_DATA41 MA_DATA41 DDRA_SDQ42
H16 W17 AE20 AA18
RSVD_M1 MEMVREF DDRB_SDQ43 MB_DATA42 MA_DATA42 DDRA_SDQ43
AF20 MB_DATA43 MA_DATA43 AB18
DDRA_ODT0 T19 B18 DDRB_SDQ44 AF24 AB21 DDRA_SDQ44
(8) DDRA_ODT0 MA0_ODT0 RSVD_M2 MB_DATA44 MA_DATA44
DDRA_ODT1 V22 DDRB_SDQ45 AF23 AD21 DDRA_SDQ45
(8) DDRA_ODT1 MA0_ODT1 DDRB_ODT0 DDRB_SDQ46 MB_DATA45 MA_DATA45 DDRA_SDQ46
U21 W26 DDRB_ODT0 (9) AC20 AD19
MA1_ODT0 MB0_ODT0 DDRB_ODT1 DDRB_SDQ47 MB_DATA46 MA_DATA46 DDRA_SDQ47
V19 W23 DDRB_ODT1 (9) AD20 Y18
MA1_ODT1 MB0_ODT1 DDRB_SDQ48 MB_DATA47 MA_DATA47 DDRA_SDQ48
Y26 AD18 AD17
DDRA_SCS0# MB1_ODT0 DDRB_SDQ49 MB_DATA48 MA_DATA48 DDRA_SDQ49
(8) DDRA_SCS0# T20 AE18 W16
DDRA_SCS1# MA0_CS_L0 DDRB_SCS0# DDRB_SDQ50 MB_DATA49 MA_DATA49 DDRA_SDQ50
(8) DDRA_SCS1# U19 V26 DDRB_SCS0# (9) AC14 W14
MA0_CS_L1 MB0_CS_L0 DDRB_SCS1# DDRB_SDQ51 MB_DATA50 MA_DATA50 DDRA_SDQ51
U20 W25 DDRB_SCS1# (9) AD14 Y14
MA1_CS_L0 MB0_CS_L1 DDRB_SDQ52 MB_DATA51 MA_DATA51 DDRA_SDQ52
V20 MA1_CS_L1 MB1_CS_L0 U22 AF19 MB_DATA52 MA_DATA52 Y17
DDRB_SDQ53 AC18 AB17 DDRA_SDQ53
DDRA_CKE0 DDRB_CKE0 DDRB_SDQ54 MB_DATA53 MA_DATA53 DDRA_SDQ54
(8) DDRA_CKE0 J22 J25 DDRB_CKE0 (9) AF16 AB15
DDRA_CKE1 MA_CKE0 MB_CKE0 DDRB_CKE1 DDRB_SDQ55 MB_DATA54 MA_DATA54 DDRA_SDQ55
(8) DDRA_CKE1 J20 H26 DDRB_CKE1 (9) AF15 AD15
MA_CKE1 MB_CKE1 DDRB_SDQ56 MB_DATA55 MA_DATA55 DDRA_SDQ56
AF13 AB13
DDRB_SDQ57 MB_DATA56 MA_DATA56 DDRA_SDQ57
N19 P22 AC12 AD13
MA_CLK_H0 MB_CLK_H0 DDRB_SDQ58 MB_DATA57 MA_DATA57 DDRA_SDQ58
N20 R22 AB11 Y12
DDRA_CLK0 MA_CLK_L0 MB_CLK_L0 DDRB_CLK0 DDRB_SDQ59 MB_DATA58 MA_DATA58 DDRA_SDQ59
(8) DDRA_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDRB_CLK0 (9) Y11 MB_DATA59 MA_DATA59 W11
DDRA_CLK0# F16 A18 DDRB_CLK0# DDRB_SDQ60 AE14 AB14 DDRA_SDQ60
(8) DDRA_CLK0# DDRA_CLK1 MA_CLK_L1 MB_CLK_L1 DDRB_CLK1 DDRB_CLK0# (9) DDRB_SDQ61 MB_DATA60 MA_DATA60 DDRA_SDQ61
(8) DDRA_CLK1 Y16 AF18 DDRB_CLK1 (9) AF14 AA14
DDRA_CLK1# MA_CLK_H2 MB_CLK_H2 DDRB_CLK1# DDRB_SDQ62 MB_DATA61 MA_DATA61 DDRA_SDQ62
(8) DDRA_CLK1# AA16 AF17 DDRB_CLK1# (9) AF11 AB12
MA_CLK_L2 MB_CLK_L2 DDRB_SDQ63 MB_DATA62 MA_DATA62 DDRA_SDQ63
P19 R26 AD11 AA12
MA_CLK_H3 MB_CLK_H3 MB_DATA63 MA_DATA63
P20 R25 (9) DDRB_SDM[7..0] DDRA_SDM[7..0] (8)
3 MA_CLK_L3 MB_CLK_L3 DDRB_SDM0 DDRA_SDM0 3
(8) DDRA_SMA[15..0] DDRB_SMA[15..0] (9) A12 MB_DM0 MA_DM0 E12
DDRA_SMA0 N21 P24 DDRB_SMA0 DDRB_SDM1 B16 C15 DDRA_SDM1
DDRA_SMA1 MA_ADD0 MB_ADD0 DDRB_SMA1 DDRB_SDM2 MB_DM1 MA_DM1 DDRA_SDM2
M20 N24 A22 E19
DDRA_SMA2 MA_ADD1 MB_ADD1 DDRB_SMA2 DDRB_SDM3 MB_DM2 MA_DM2 DDRA_SDM3
N22 MA_ADD2 MB_ADD2 P26 E25 MB_DM3 MA_DM3 F24
DDRA_SMA3 M19 N23 DDRB_SMA3 DDRB_SDM4 AB26 AC24 DDRA_SDM4
DDRA_SMA4 MA_ADD3 MB_ADD3 DDRB_SMA4 DDRB_SDM5 MB_DM4 MA_DM4 DDRA_SDM5
M22 N26 AE22 Y19
DDRA_SMA5 MA_ADD4 MB_ADD4 DDRB_SMA5 DDRB_SDM6 MB_DM5 MA_DM5 DDRA_SDM6
L20 L23 AC16 AB16
DDRA_SMA6 MA_ADD5 MB_ADD5 DDRB_SMA6 DDRB_SDM7 MB_DM6 MA_DM6 DDRA_SDM7
M24 N25 AD12 Y13
DDRA_SMA7 MA_ADD6 MB_ADD6 DDRB_SMA7 MB_DM7 MA_DM7
L21 L24
DDRA_SMA8 MA_ADD7 MB_ADD7 DDRB_SMA8 DDRB_SDQS0 DDRA_SDQS0
L19 MA_ADD8 MB_ADD8 M26 (9) DDRB_SDQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDRA_SDQS0 (8)
DDRA_SMA9 K22 K26 DDRB_SMA9 DDRB_SDQS0# B12 H13 DDRA_SDQS0#
MA_ADD9 MB_ADD9 (9) DDRB_SDQS0# MB_DQS_L0 MA_DQS_L0 DDRA_SDQS0# (8)
DDRA_SMA10 R21 T26 DDRB_SMA10 DDRB_SDQS1 D16 G16 DDRA_SDQS1
DDRA_SMA11 MA_ADD10 MB_ADD10 DDRB_SMA11 (9) DDRB_SDQS1 DDRB_SDQS1# MB_DQS_H1 MA_DQS_H1 DDRA_SDQS1# DDRA_SDQS1 (8)
L22 MA_ADD11 MB_ADD11 L26 (9) DDRB_SDQS1# C16 MB_DQS_L1 MA_DQS_L1 G15 DDRA_SDQS1# (8)
DDRA_SMA12 K20 L25 DDRB_SMA12 DDRB_SDQS2 A24 C22 DDRA_SDQS2
MA_ADD12 MB_ADD12 (9) DDRB_SDQS2 MB_DQS_H2 MA_DQS_H2 DDRA_SDQS2 (8)
DDRA_SMA13 V24 W24 DDRB_SMA13 DDRB_SDQS2# A23 C21 DDRA_SDQS2#
DDRA_SMA14 MA_ADD13 MB_ADD13 DDRB_SMA14 (9) DDRB_SDQS2# DDRB_SDQS3 MB_DQS_L2 MA_DQS_L2 DDRA_SDQS3 DDRA_SDQS2# (8)
K24 J23 (9) DDRB_SDQS3 F26 G22 DDRA_SDQS3 (8)
DDRA_SMA15 MA_ADD14 MB_ADD14 DDRB_SMA15 DDRB_SDQS3# MB_DQS_H3 MA_DQS_H3 DDRA_SDQS3#
K19 J24 (9) DDRB_SDQS3# E26 G21 DDRA_SDQS3# (8)
MA_ADD15 MB_ADD15 DDRB_SDQS4 MB_DQS_L3 MA_DQS_L3 DDRA_SDQS4
(9) DDRB_SDQS4 AC25 AD23 DDRA_SDQS4 (8)
DDRA_SBS0# DDRB_SBS0# DDRB_SDQS4# MB_DQS_H4 MA_DQS_H4 DDRA_SDQS4#
(8) DDRA_SBS0# R20 R24 DDRB_SBS0# (9) (9) DDRB_SDQS4# AC26 AC23 DDRA_SDQS4# (8)
DDRA_SBS1# MA_BANK0 MB_BANK0 DDRB_SBS1# DDRB_SDQS5 MB_DQS_L4 MA_DQS_L4 DDRA_SDQS5
(8) DDRA_SBS1# R23 U26 DDRB_SBS1# (9) (9) DDRB_SDQS5 AF21 AB19 DDRA_SDQS5 (8)
DDRA_SBS2# MA_BANK1 MB_BANK1 DDRB_SBS2# DDRB_SDQS5# MB_DQS_H5 MA_DQS_H5 DDRA_SDQS5#
(8) DDRA_SBS2# J21 J26 DDRB_SBS2# (9) (9) DDRB_SDQS5# AF22 AB20 DDRA_SDQS5# (8)
MA_BANK2 MB_BANK2 DDRB_SDQS6 MB_DQS_L5 MA_DQS_L5 DDRA_SDQS6
(9) DDRB_SDQS6 AE16 MB_DQS_H6 MA_DQS_H6 Y15 DDRA_SDQS6 (8)
DDRA_SRAS# R19 U25 DDRB_SRAS# DDRB_SDQS6# AD16 W15 DDRA_SDQS6#
(8) DDRA_SRAS# DDRA_SCAS# MA_RAS_L MB_RAS_L DDRB_SCAS# DDRB_SRAS# (9) (9) DDRB_SDQS6# DDRB_SDQS7 MB_DQS_L6 MA_DQS_L6 DDRA_SDQS7 DDRA_SDQS6# (8)
(8) DDRA_SCAS# T22 MA_CAS_L MB_CAS_L U24 DDRB_SCAS# (9) (9) DDRB_SDQS7 AF12 MB_DQS_H7 MA_DQS_H7 W12 DDRA_SDQS7 (8)
DDRA_SWE# T24 U23 DDRB_SWE# DDRB_SDQS7# AE12 W13 DDRA_SDQS7#
(8) DDRA_SWE# MA_WE_L MB_WE_L DDRB_SWE# (9) (9) DDRB_SDQS7# MB_DQS_L7 MA_DQS_L7 DDRA_SDQS7# (8)

6090022100G_B 6090022100G_B
ME@ ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G3 DDRII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 5 of 49
A B C D E
 A B C D E

+2.5VS 1
L63
2
+2.5VDDA

3300P_0402_50V7K
www.bufanxiu.com
VDDA=0.25A
MBK1608221YZF_0603
1 1 1 1 1 +1.8V 1 2
R66 10K_0402_5%
C918 + 4.7U_0805_10V4Z C941 C938 C880 1 2
150U_B2_6.3VM_R35M C296 0.22U_0603_16V4Z R67 300_0402_5%
2 180P_0402_50V8J 2 2 2

2
2

B
close to L35 Q9
JCPU1D

E
1 CPU_THERMTRIP#_R R65 1
3 1 1 2 H_THERMTRIP# (24)

C
0_0402_5%
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 KEY1
F9 W18
VDDA2 KEY2
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC
(20) CLK_CPU_BCLK CPU_CLKIN_SC_N CLKIN_H SVC CPU_SVD CPU_SVC (47)
C723 A8 A4
CLKIN_L SVD CPU_SVD (47)

1
+1.8V 1 2
LDT_RST# B7 R69 300_0402_5%
R455 H_PWRGD RESET_L
A7
169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R
F10 LDTSTOP_L THERMTRIP_L AF6
C6 AC7 H_PROCHOT#

2
LDTREQ_L PROCHOT_L H_PROCHOT# R68
(20) CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 1 2 H_PROCHOT_R# (23,33)
C724 3900P_0402_50V7K 2 1 CPU_SIC AF4 0_0402_5%
+1.8V SIC
R70 2 1 390_0402_5% CPU_SID AF5
+1.8VS +1.8V SID
R71 @ 390_0402_5% AE6 W7 THERMDC_CPU
ALERT_L THERMDC THERMDA_CPU
THERMDA W8
R82 1 2 44.2_0402_1% CPU_HTREF0 R6
HT_REF0
2

+1.2V_HT R89 1 2 44.2_0402_1% CPU_HTREF1 P6

R557 HT_REF1
300_0402_5% CPU_VDD0_FB_H F6 W9
(47) CPU_VDD0_FB_H VDD0_FB_H VDDIO_FB_H VDDIO (43)
CPU_VDD0_FB_L E6 Y9
(47) CPU_VDD0_FB_L VDD0_FB_L VDDIO_FB_L PAD T5
1

LDT_RST# CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H

(23) LDT_RST# (47) CPU_VDD1_FB_H VDD1_FB_H VDDNB_FB_H CPU_VDDNB_FB_H (47)
CPU_VDD1_FB_L AB6 G6 CPU_VDDNB_FB_L
(47) CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L (47)
1
C721 CPU_DBRDY G10
0.01U_0402_16V7K CPU_TMS DBRDY CPU_DBREQ#
AA9 E10
@ CPU_TCK TMS DBREQ_L
AC9 TCK
2 CPU_TRST# AD9 AE9 CPU_TDO
CPU_TDI TRST_L TDO
AF9
TDI
2 T44 PAD CPU_TEST23 CPU_TEST28_H_PLLCHRZ_P 2
AD7 TEST23 TEST28_H J7 PAD T24
H8 CPU_TEST28_L_PLLCHRZ_N
+1.8VS CPU_TEST18 TEST28_L PAD T21
T25 PAD H10
T26 PAD CPU_TEST19 TEST18 CPU_TEST17
G9 TEST19 TEST17 D7 PAD T34
E7 CPU_TEST16
TEST16 PAD T36
2

T37 PAD CPU_TEST25H E9 F7 CPU_TEST15 +1.8V

TEST25_H TEST15 PAD T32
R558 T33 PAD CPU_TEST25L E8 C7 CPU_TEST14
TEST25_L TEST14 PAD T38
300_0402_5%
CPU_TEST21 AB8 C3 CPU_TEST7 CPU_SVC R456 1 2 1K_0402_5%
CPU_TEST20 TEST21 TEST7 CPU_TEST10 PAD T31 CPU_SVD
T43 PAD AF7 K8 1 2
PAD T18
1

H_PWRGD CPU_TEST24 TEST20 TEST10 R549 1K_0402_5%

(23) H_PWRGD AE7 TEST24
T42 PAD CPU_TEST22 AE8 C4 CPU_TEST8
TEST22 TEST8 PAD T67
1 T3 PAD CPU_TEST12 AC8
C720 T41 PAD CPU_TEST27 TEST12
AF8
0.01U_0402_16V7K TEST27 CPU_TEST29_H_FBCLKOUT_P
C9 PAD T39
@ R227 2 0_0402_5% TEST29_H CPU_TEST29_L_FBCLKOUT_N +1.8V
1 C2 C8 PAD T35
2 T2 PAD CPU_TEST6 TEST9 TEST29_L @
AA6
TEST6 CPU_TEST25H 1 2
A3 H18 R144 510_0402_5%
RSVD1 RSVD10 CPU_TEST25L 1
A5 RSVD2 RSVD9 H19 2
B3 AA7 R143 510_0402_5%
+1.8VS RSVD3 RSVD8 CPU_TEST10
B5 D5 1 2
RSVD4 RSVD7 R101@ 0_0603_5%
C1 C5
RSVD5 RSVD6 CPU_TEST18 1 2
2

R950@ 0_0603_5%
R556 CPU_TEST19 1 2
6090022100G_B
300_0402_5% R951@ 0_0603_5%
ME@ CPU_TEST22 1 2
R952@ 0_0603_5%
1

LDT_STOP# CPU_TEST21 1 2
(11,23) LDT_STOP#
R75 300_0402_5%
1 CPU_TEST24 1 2
3 C719 R74 300_0402_5% 3
0.01U_0402_16V7K CPU_TEST20 1 2
@ R73 300_0402_5%
2 CPU_TEST23 1 2
R72 300_0402_5%
CPU_TEST25H 1 2
R136 510_0402_5%
CPU_TEST25L 1 2
R135 510_0402_5%
@
+1.8V

+1.8V

220_0402_5%R117

220_0402_5%R118

220_0402_5%R119

300_0402_5%R120

300_0402_5%R555
1

2
JP1
1 2

1
3 4
CPU_DBREQ# @ @ 5 6 R140 2
1
+3VS CPU_DBRDY @ @ 7 8 @ 0_0402_5%
CPU_TCK 9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
15 16 MP(Remove)
0.1U_0402_16V4Z

1 CPU_TRST#
17 18

5
CPU_TDO U15
C206 19 20 LDT_RST#
2

P
21 22 HDT_RST# B
2 MP(Remove) 23 24
4
Y
U10 1
26 A SB_PWRGD (11,24,33)4

G
4 EC_SMB_CK2
1 8 EC_SMB_CK2 (33)
VDD SCLK NC7SZ08P5X_NL_SC70-5

3
THERMDA_CPU 2 7 EC_SMB_DA2 @ SAMTEC_ASP-68200-07 @
D+ SDATA EC_SMB_DA2 (33)
C194 THERMDC_CPU 3 6 MP(mask)
D- ALERT#
1 2
3300P_0402_50V7K 4 5
<BOM Structure> THERM# GND
Security Classification Compal Secret Data Compal Electronics, Inc.
ADM1032ARMZ_MSOP8 Issued Date 2008/10/06 2009/10/06 Title
Deciphered Date
Address 1001 100X b THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G3 CTRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 6 of 49
A B C D E
 A B C D E

VDD(+CPU_CORE) decoupling. www.bufanxiu.com VDD0 = 18A

+CPU_CORE_0

G4
JCPU1E
VDD1 =18A

P8
+CPU_CORE_1
AA4
AA11
AA13
AA15
JCPU1F

VSS1
VSS2
VSS3
VSS66
VSS67
VSS68
J6
J8
J10
J12
VDD0_1 VDD1_1 VSS4 VSS69
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 R7 AB2 J18
VDD0_4 VDD1_4 VSS7 VSS72
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 R11 AB9 K7
VDD0_6 VDD1_6 VSS9 VSS74
1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 T6 AB25 K11
+ C939 + C661 + C96 + C643 VDD0_8 VDD1_8 VSS11 VSS76
K12 VDD0_9 VDD1_9 T8 AC11 VSS12 VSS77 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2 L7 T14 AC17 L6
VDD0_12 VDD1_12 VSS15 VSS80
L9 U7 AC19 L8
VDD0_13 VDD1_13 VSS16 VSS81
Near CPU Socket L11
L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15
U9
U11
AC21
AD6
VSS17
VSS18
VSS82
VSS83
L10
L12
VDDNB=4A L15
VDD0_16 VDD1_16
U13 AD8
VSS19 VSS84
L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
(For Tigris) M6 V6 AE11 L18
VDD0_18 VDD1_18 VSS21 VSS86
M8 V8 AE13 M7
+CPU_CORE_0 VDD0_19 VDD1_19 VSS22 VSS87
+CPU_CORE_1
VDDNB=3A M10 VDD0_20 VDD1_20 V10 AE15 VSS23 VSS88 M9
N7 V12 AE17 AC6
VDD0_21 VDD1_21 VSS24 VSS89
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 Y2 AE23 N8
C914 C911 C273 C915 VDD1_24 VSS27 VSS92
1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C214 C238 C227 C215 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 V25 B11 P7
VDDNB_5 VDDIO26 VSS32 VSS97
V23 B13 P9
+CPU_CORE_0 VDDIO25 VSS33 VSS98
H25 V21 B15 P11
+CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
VDDIO=3A K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 T25 B21 R10
VDDIO4 VDDIO21 VSS37 VSS102
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C887 C276 C921 C882 C9 C230 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_16V7K 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_16V7K 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 T18 D6 T7
VDDIO7 VDDIO18 VSS40 VSS105
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2 M21 P25 D9 T11
VDDIO9 VDDIO16 VSS42 VSS107
Under CPU Socket M23
M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14
P23
P21
D11
D13
VSS43
VSS44
VSS108
VSS109
T13
T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 U4
VSS46 VSS111
D19 U6
6090022100G_B VSS47 VSS112
D21 VSS48 VSS113 U8
Athlon 64 S1 D23 U10
VDDIO decoupling. Processor Socket
ME@
D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 U16

+1.8V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 V9
+CPU_CORE_NB VSS56 VSS121
F19 VSS57 VSS122 V11
F21 V13
VSS58 VSS123
1 1 1 1 1 1 F23 V15
C195 C228 C222 C886 C919 C274 VSS59 VSS124
1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C207 C910 C913 VSS60 VSS125
H7 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VSS61 VSS126
H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 Y23
2 2 2 VSS63 VSS128
H23 VSS64 VSS129 N6
J4
VSS65
6090022100G_B
Under CPU Socket Athlon 64 S1
Processor Socket
ME@

Between CPU Socket and DIMM

+1.8V +0.9V
3 3
Near Power Supply
1
C301
1
C302
1
C303
1
C300
VTT decoupling. C937
1
+
C: Change to NPO CAP
1
C912
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 220U_D2_4VM_R15 22U_0805_6.3V6M
2 2 2 2 2 2

180PF Qt'y follow the distance between

+1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V

1 1 1 1 1 1
C309 C307 C218 C308 C310 C219 1 1 1 1 1 1 1 1
0.01U_0402_16V7K 0.01U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C943 C945 C883 C885 C893 C892 C920 C922
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
2 2 2 2 2 2 2 2

+1.8V
Near CPU Socket Right side.
+0.9V

1 1 1 1 1
C211 C209 C208 C210 + C226
1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 330U_X_2VM_R6M C942 C944 C884 C881 C718 C717 C716 C715
2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2
2 2 2 2 2 2 2 2
4 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G3 PWR & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 7 of 49
A B C D E
 A B C D E

+1.8V +1.8V
www.bufanxiu.com
JDIMM1
+V_DDR_MCH_REF 1 VREF VSS 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 DDRA_SDQ[0..63]
DQ1 VSS DDRA_SDM0 DDRA_SDQ[0..63] (5)
9 VSS DM0 10
DDRA_SDQS0# 11 12 DDRA_SDM[0..7]
(5) DDRA_SDQS0# DQS0# VSS DDRA_SDM[0..7] (5)
DDRA_SDQS0 13 14 DDRA_SDQ6
1 (5) DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7 1
15 VSS DQ7 16
DDRA_SDQ2 17 18
DDRA_SDQ3 DQ2 VSS DDRA_SDQ12 DDRA_SMA[0..15]
19 DQ3 DQ12 20 DDRA_SMA[0..15] (5)
21 22 DDRA_SDQ13
DDRA_SDQ8 VSS DQ13
23 24
DDRA_SDQ9 DQ8 VSS DDRA_SDM1
25 DQ9 DM1 26
27 28 +0.9V +1.8V
DDRA_SDQS1# VSS VSS RP10
29 DQS1# CK0 30 DDRA_CLK0 (5)
(5) DDRA_SDQS1# DDRA_SDQS1 DDRA_SMA6
31 DQS1 CK0# 32 DDRA_CLK0# (5) 1 8 1 2
(5) DDRA_SDQS1 DDRA_SMA7 C16 0.1U_0402_16V4Z
33 34 2 7
DDRA_SDQ10 VSS VSS DDRA_SDQ14 DDRA_SMA15
35 DQ10 DQ14 36 3 6 1 2
DDRA_SDQ11 37 38 DDRA_SDQ15 DDRA_SMA11 4 5 C198 0.1U_0402_16V4Z
DQ11 DQ15
39 VSS VSS 40
+1.8V 47_0804_8P4R_5%
RP13
41 42 8 1 1 2
VSS VSS

2
DDRA_SDQ16 43 44 DDRA_SDQ20 7 2 C225 0.1U_0402_16V4Z
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 R147 DDRA_CKE0
45 46 6 3 1 2
DQ17 DQ21 1K_0402_1% DDRA_SBS2# C223 0.1U_0402_16V4Z
47 VSS VSS 48 5 4
DDRA_SDQS2# 49 50
(5) DDRA_SDQS2# DDRA_SDQS2 DQS2# NC DDRA_SDM2 47_0804_8P4R_5%
51 52

1
(5) DDRA_SDQS2 DQS2 DM2 +V_DDR_MCH_REF RP8
53 54 +V_DDR_MCH_REF
DDRA_SDQ18 VSS VSS DDRA_SDQ22 DDRA_SBS1#
55 DQ18 DQ22 56 1 8 1 2

1000P_0402_25V8J

1U_0402_6.3V4Z
DDRA_SDQ19 57 58 DDRA_SDQ23 1 1 DDRA_SMA0 2 7 C159 0.1U_0402_16V4Z
DQ19 DQ23

2
59 60 DDRA_SMA2 3 6 1 2
VSS VSS

C894

C923
DDRA_SDQ24 61 62 DDRA_SDQ28 R148 DDRA_SMA4 4 5 C167 0.1U_0402_16V4Z
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29 1K_0402_1%
63 64
DQ25 DQ29 2 2 47_0804_8P4R_5%
65 66
DDRA_SDM3 VSS VSS DDRA_SDQS3# RP9
67 68

1
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# (5) DDRA_SMA12
69 NC DQS3 70 8 1 1 2
DDRA_SDQS3 (5) DDRA_SMA9 C179 0.1U_0402_16V4Z
71 72 7 2
DDRA_SDQ26 VSS VSS DDRA_SDQ30 DDRA_SMA8
73 74 6 3 1 2
2 DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 DDRA_SMA5 C17 0.1U_0402_16V4Z 2
75 DQ27 DQ31 76 5 4
77 78
DDRA_CKE0 VSS VSS DDRA_CKE1 47_0804_8P4R_5%
(5) DDRA_CKE0 79 80 DDRA_CKE1 (5)
CKE0 NC/CKE1 RP7
81 VDD VDD 82
83 84 DDRA_SMA15 Check layout place DDRA_SMA3 8 1 1 2
DDRA_SBS2# NC NC/A15 DDRA_SMA14 DDRA_SMA1 C169 0.1U_0402_16V4Z
(5) DDRA_SBS2# 85 86 7 2
BA2 NC/A14 DDRA_SMA10
87 VDD VDD 88 6 3 1 2
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SBS0# 5 4 C15 0.1U_0402_16V4Z
DDRA_SMA9 A12 A11 DDRA_SMA7
91 A9 A7 92
DDRA_SMA8 93 94 DDRA_SMA6 47_0804_8P4R_5%
A8 A6 RP4
95 VDD VDD 96
DDRA_SMA5 97 98 DDRA_SMA4 DDRA_SWE# 8 1 1 2
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_SCAS# C157 0.1U_0402_16V4Z
99 A3 A2 100 7 2
DDRA_SMA1 101 102 DDRA_SMA0 DDRA_SCS1# 6 3 1 2
A1 A0 DDRA_ODT1 C142 0.1U_0402_16V4Z
103 104 5 4
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 106 DDRA_SBS1# (5)
DDRA_SBS0# A10/AP BA1 DDRA_SRAS# 47_0804_8P4R_5%
(5) DDRA_SBS0# 107 108 DDRA_SRAS# (5)
DDRA_SWE# BA0 RAS# DDRA_SCS0# RP3
(5) DDRA_SWE# 109 110 DDRA_SCS0# (5)
WE# S0# DDRA_SMA13
111 112 1 8 1 2
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_ODT0 C145 0.1U_0402_16V4Z
(5) DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 (5) 2 7
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SCS0# 3 6 1 2
(5) DDRA_SCS1# NC/S1# NC/A13
117 118 DDRA_SRAS# 4 5 C18 0.1U_0402_16V4Z
DDRA_ODT1 VDD VDD
(5) DDRA_ODT1 119 120
NC/ODT1 NC 47_0804_8P4R_5%
121 122
DDRA_SDQ32 VSS VSS DDRA_SDQ36
123 124
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
125 126
DQ33 DQ37 DDRA_CKE1 R987 1
127 VSS VSS 128 2 47_0402_5%
DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_SMA14 R988 1 2 47_0402_5%
(5) DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4
131 132
(5) DDRA_SDQS4 DQS4 VSS DDRA_SDQ38
133 134
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 136
DDRA_SDQ35 DQ34 DQ39
137 138
3 DQ35 VSS DDRA_SDQ44 3
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
143 144
DQ41 VSS DDRA_SDQS5#
145 VSS DQS5# 146
DDRA_SDM5 DDRA_SDQS5 DDRA_SDQS5# (5)
147 148
DM5 DQS5 DDRA_SDQS5 (5)
149 150
DDRA_SDQ42 VSS VSS DDRA_SDQ46
151 152
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
153 154
DQ43 DQ47
155 156
DDRA_SDQ48 VSS VSS DDRA_SDQ52
157 DQ48 DQ52 158
DDRA_SDQ49 159 160 DDRA_SDQ53 EMI
DQ49 DQ53
161 162
VSS VSS +1.8V
163 NC,TEST CK1 164 DDRA_CLK1 (5)
165 166 DDRA_CLK1# (5)
DDRA_SDQS6# VSS CK1#
167 DQS6# VSS 168
(5) DDRA_SDQS6# DDRA_SDQS6 DDRA_SDM6
169 170 1 2
(5) DDRA_SDQS6 DQS6 DM6 C13 0.1U_0402_16V4Z
171 172
DDRA_SDQ50 VSS VSS DDRA_SDQ54
173 174 @
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55
175 176 1 2
DQ51 DQ55 C175 0.1U_0402_16V4Z
177 178
DDRA_SDQ56 VSS VSS DDRA_SDQ60
179 180 @
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61
181 DQ57 DQ61 182 1 2
183 184 C176 0.1U_0402_16V4Z
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 DM7 DQS7# 186 @
DDRA_SDQS7 DDRA_SDQS7# (5)
187 188
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 (5)
189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
SB_SMBDATA VSS DQ63
(9,20,24,31) SB_SMBDATA 195 196
SB_SMBCLK SDA VSS R39
(9,20,24,31) SB_SMBCLK 197 198 1 2 10K_0402_5%
SCL SAO R36
+3VS 199 200 1 2 10K_0402_5%
VDDSPD SA1
201 GND GND 202
4 4
TYCO_292527-4
+3VS ME@

C936
1
C14
1
DIMM1 REV H:5.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z Issued Date 2008/10/06 2009/10/06 Title
2
2.2U_0805_10V6K 2 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 8 of 49
A B C D E
 A B C D E

+V_DDR_MCH_REF

+1.8V
+1.8V
www.bufanxiu.com
2.2U_0603_6.3V4Z
1
C933 JDIMM2 DDRB_SDQ[0..63]
DDRB_SDQ[0..63] (5)
1 2
2 VREF VSS DDRB_SDQ4 DDRB_SDM[0..7]
3 VSS DQ4 4 DDRB_SDM[0..7] (5)
DDRB_SDQ0 5 6 DDRB_SDQ5
DDRB_SDQ1 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDRB_SDM0
DDRB_SDQS0# VSS DM0 DDRB_SMA[0..15]
11 DQS0# VSS 12 DDRB_SMA[0..15] (5)
1 (5) DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ6 1
(5) DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 22
DDRB_SDQ8 VSS DQ13
23 DQ8 VSS 24
DDRB_SDQ9 25 26 DDRB_SDM1
DQ9 DM1
27 VSS VSS 28
DDRB_SDQS1# 29 30
(5) DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 (5)
DDRB_SDQS1 31 32
(5) DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# (5) +1.8V
33 34 +0.9V
DDRB_SDQ10 VSS VSS DDRB_SDQ14 RP6
35 36
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15 DDRB_SMA4
37 DQ11 DQ15 38 1 8 2 1
39 40 DDRB_SMA2 2 7 C171 0.1U_0402_16V4Z
VSS VSS DDRB_SMA0 3 6 1 2
DDRB_SBS1# 4 5 C201 0.1U_0402_16V4Z
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20 47_0804_8P4R_5%
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 48 RP12
DDRB_SDQS2# VSS VSS DDRB_SMA14
49 50 1 8 2 1
(5) DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2 DDRB_SMA11 C180 0.1U_0402_16V4Z
51 52 2 7
(5) DDRB_SDQS2 DQS2 DM2 DDRB_SMA7
53 VSS VSS 54 3 6 1 2
DDRB_SDQ18 55 56 DDRB_SDQ22 DDRB_SMA6 4 5 C20 0.1U_0402_16V4Z
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 58
DQ19 DQ23 47_0804_8P4R_5%
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29 RP14
63 64
DQ25 DQ29 DDRB_SMA15
65 VSS VSS 66 8 1 2 1
DDRB_SDM3 67 68 DDRB_SDQS3# DDRB_CKE1 7 2 C200 0.1U_0402_16V4Z
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# (5)
69 70 6 3 1 2
NC DQS3 DDRB_SDQS3 (5) C231 0.1U_0402_16V4Z
71 72 5 4
2 DDRB_SDQ26 VSS VSS DDRB_SDQ30 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 47_0804_8P4R_5%
DQ27 DQ31
77 78
DDRB_CKE0 VSS VSS DDRB_CKE1 RP11
(5) DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 (5)
81 82 DDRB_SMA12 8 1 2 1
VDD VDD DDRB_SMA15 DDRB_SMA9 C21 0.1U_0402_16V4Z
83 84 7 2
DDRB_SBS2# NC NC/A15 DDRB_SMA14 DDRB_SMA5
(5) DDRB_SBS2# 85 BA2 NC/A14 86 6 3 1 2
87 88 DDRB_SMA8 5 4 C197 0.1U_0402_16V4Z
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 47_0804_8P4R_5%
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 RP5
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SBS0#
97 A5 A4 98 8 1 2 1
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA10 7 2 C146 0.1U_0402_16V4Z
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA3
101 102 6 3 1 2
A1 A0 DDRB_SMA1 C19 0.1U_0402_16V4Z
103 104 5 4
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 106 DDRB_SBS1# (5)
DDRB_SBS0# A10/AP BA1 DDRB_SRAS# 47_0804_8P4R_5%
(5) DDRB_SBS0# 107 108 DDRB_SRAS# (5)
DDRB_SWE# BA0 RAS# DDRB_SCS0#
(5) DDRB_SWE# 109 110 DDRB_SCS0# (5)
WE# S0# RP1
111 VDD VDD 112
DDRB_SCAS# 113 114 DDRB_ODT0 DDRB_ODT1 8 1 2 1
(5) DDRB_SCAS# CAS# ODT0 DDRB_ODT0 (5)
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SCS1# 7 2 C122 0.1U_0402_16V4Z
(5) DDRB_SCS1# NC/S1# NC/A13 DDRB_SWE#
117 118 6 3 1 2
DDRB_ODT1 VDD VDD DDRB_SCAS# C117 0.1U_0402_16V4Z
(5) DDRB_ODT1 119 120 5 4
NC/ODT1 NC
121 122
DDRB_SDQ32 VSS VSS DDRB_SDQ36 47_0804_8P4R_5%
123 124
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
125 DQ33 DQ37 126
127 128 RP2
DDRB_SDQS4# VSS VSS DDRB_SDM4 DDRB_SRAS#
129 130 1 8 2 1
(5) DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4 DDRB_SCS0# C147 0.1U_0402_16V4Z
131 132 2 7
(5) DDRB_SDQS4 DQS4 VSS DDRB_SDQ38 DDRB_ODT0
133 134 3 6 1 2
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39 DDRB_SMA13 C118 0.1U_0402_16V4Z
135 136 4 5
3 DDRB_SDQ35 DQ34 DQ39 3
137 DQ35 VSS 138
139 140 DDRB_SDQ44 47_0804_8P4R_5%
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 142
DDRB_SDQ41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDRB_SDQS5#
DDRB_SDM5 VSS DQS5# DDRB_SDQS5 DDRB_SDQS5# (5) DDRB_SBS2# R989 1
147 148 2 47_0402_5%
DM5 DQS5 DDRB_SDQS5 (5) DDRB_CKE0 R990 1
149 150 2 47_0402_5%
DDRB_SDQ42 VSS VSS DDRB_SDQ46
151 152
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
153 154
DQ43 DQ47
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 160
DQ49 DQ53
161 VSS VSS 162
163 164 DDRB_CLK1 (5)
NC,TEST CK1
165 VSS CK1# 166 DDRB_CLK1# (5)
DDRB_SDQS6# 167 168
(5) DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6
169 170
(5) DDRB_SDQS6 DQS6 DM6
171 172
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 174
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55
175 176
DQ51 DQ55
177 178
DDRB_SDQ56 VSS VSS DDRB_SDQ60
179 DQ56 DQ60 180
DDRB_SDQ57 181 182 DDRB_SDQ61
DQ57 DQ61
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7#
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# (5)
187 188
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 (5)
189 DQ58 VSS 190
DDRB_SDQ59 191 192 DDRB_SDQ62
DQ59 DQ62 DDRB_SDQ63
193 194
SB_SMBDATA VSS DQ63
(8,20,24,31) SB_SMBDATA 195 196
SB_SMBCLK SDA VSS R37
(8,20,24,31) SB_SMBCLK 197 198 1 2 10K_0402_5% +3VS
SCL SAO R35
+3VS 199 VDDSPD SA1 200 1 2 10K_0402_5%
4 4

FOX_AS0A426-NARN-7F~N
ME@

DIMM2 REV H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 9 of 49
A B C D E
 A B C D E

(14) PCIE_GTX_C_MRX_P[0..15]

(14) PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
www.bufanxiu.com
PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15] (14)

PCIE_MTX_C_GRX_N[0..15] (14)

U20B
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C358 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C646 1 PCIE_MTX_C_GRX_N0
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 2 VGA@ 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P1 A3 A4 PCIE_MTX_GRX_P1 C649 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_N1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C648 1 PCIE_MTX_C_GRX_N1
B3 GFX_RX1N GFX_TX1N B4 2 VGA@ 0.1U_0402_10V7K
1 PCIE_GTX_C_MRX_P2 PCIE_MTX_GRX_P2 1
C2 GFX_RX2P GFX_TX2P C3 C651 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C650 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 C653 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C652 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4
G5 E2 C366 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_N4 GFX_RX4P GFX_TX4P PCIE_MTX_GRX_N4 C356 1 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
G6 GFX_RX4N GFX_TX4N E1 2
PCIE_GTX_C_MRX_P5 H5 F4 PCIE_MTX_GRX_P5 C876 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 GFX_RX5P GFX_TX5P PCIE_MTX_GRX_N5 C657 1 PCIE_MTX_C_GRX_N5
H6 GFX_RX5N GFX_TX5N F3 2 VGA@ 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P6 J6 F1 PCIE_MTX_GRX_P6 C658 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 GFX_RX6P GFX_TX6P PCIE_MTX_GRX_N6 C365 1 PCIE_MTX_C_GRX_N6
J5 F2 2 VGA@ 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P7 GFX_RX6N GFX_TX6N PCIE_MTX_GRX_P7
J7 GFX_RX7P GFX_TX7P H4 C364 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 J8 H3 PCIE_MTX_GRX_N7 C641 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N7
PCIE_GTX_C_MRX_P8 GFX_RX7N GFX_TX7N PCIE_MTX_GRX_P8
L5 GFX_RX8P GFX_TX8P H1 C638 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
PCIE_GTX_C_MRX_N8 L6 H2 PCIE_MTX_GRX_N8 C636 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8
PCIE_GTX_C_MRX_P9 GFX_RX8N GFX_TX8N PCIE_MTX_GRX_P9
M8 J2 C637 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C635 1 PCIE_MTX_C_GRX_N9
L8 J1 2 VGA@ 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P10 GFX_RX9N GFX_TX9N PCIE_MTX_GRX_P10 C634 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10

PCIE I/F GFX

P7 GFX_RX10P GFX_TX10P K4
PCIE_GTX_C_MRX_N10 M7 K3 PCIE_MTX_GRX_N10 C632 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10
PCIE_GTX_C_MRX_P11 GFX_RX10N GFX_TX10N PCIE_MTX_GRX_P11
P5 GFX_RX11P GFX_TX11P K1 C631 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 M5 K2 PCIE_MTX_GRX_N11 C360 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
PCIE_GTX_C_MRX_P12 GFX_RX11N GFX_TX11N PCIE_MTX_GRX_P12 C629 1 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12
R8 M4 2
PCIE_GTX_C_MRX_N12 GFX_RX12P GFX_TX12P PCIE_MTX_GRX_N12 C627 1 PCIE_MTX_C_GRX_N12
P8 M3 2 VGA@ 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13
R6 GFX_RX13P GFX_TX13P M1 C363 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
PCIE_GTX_C_MRX_N13 R5 M2 PCIE_MTX_GRX_N13 C623 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14
P4 N2 C359 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_N14 GFX_RX14P GFX_TX14P PCIE_MTX_GRX_N14 C624 1 PCIE_MTX_C_GRX_N14
P3 GFX_RX14N GFX_TX14N N1 2 VGA@ 0.1U_0402_10V7K
PCIE_GTX_C_MRX_P15 T4 P1 PCIE_MTX_GRX_P15 C621 1 2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
PCIE_GTX_C_MRX_N15 GFX_RX15P GFX_TX15P PCIE_MTX_GRX_N15 C361 1 PCIE_MTX_C_GRX_N15
T3 P2 2 VGA@ 0.1U_0402_10V7K
GFX_RX15N GFX_TX15N
AE3 AC1 WLAN@
GPP_RX0P GPP_TX0P WLAN@
AD4 AC2
GPP_RX0N GPP_TX0N PCIE_ITX_PRX_P1 C614 1 0.1U_0402_10V7K
(31) PCIE_PTX_C_IRX_P1 AE2 AB4 2 PCIE_ITX_C_PRX_P1 (31)
2 GPP_RX1P GPP_TX1P PCIE_ITX_PRX_N1 2
(31) PCIE_PTX_C_IRX_N1 AD3 GPP_RX1N GPP_TX1N AB3 C362 1 2 0.1U_0402_10V7K
PCIE_ITX_C_PRX_N1 (31) WLAN
AD1 AA2 PCIE_ITX_PRX_P2 C357 1 2 0.1U_0402_10V7K
(30) PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_PRX_N2 PCIE_ITX_C_PRX_P2 (30)
(30) PCIE_PTX_C_IRX_N2 AD2
GPP_RX2N PCIE I/F GPP GPP_TX2N
AA1 C618 1 2 0.1U_0402_10V7K
PCIE_ITX_C_PRX_N2 (30) LAN
V5 GPP_RX3P GPP_TX3P Y1
W6 GPP_RX3N GPP_TX3N Y2
U5 Y4 PCIE_ITX_PRX_P4 C964 1 2 0.1U_0402_10V7K
(31) PCIE_PTX_C_IRX_P4 GPP_RX4P GPP_TX4P PCIE_ITX_C_PRX_P4 (31) H_CADOP[0..15] H_CADIP[0..15]
U6 Y3 PCIE_ITX_PRX_N4 C965 1 2 0.1U_0402_10V7K New Card
(31) PCIE_PTX_C_IRX_N4 GPP_RX4N GPP_TX4N PCIE_ITX_C_PRX_N4 (31) (4) H_CADOP[0..15] H_CADIP[0..15] (4)
U8 V1 NEWCARD@
GPP_RX5P GPP_TX5P NEWCARD@ H_CADON[0..15] H_CADIN[0..15]
U7 GPP_RX5N GPP_TX5N V2 (4) H_CADON[0..15] H_CADIN[0..15] (4)
(23) SB_RX0P AA8 AD7 SB_TX0P_C C352 1 2 0.1U_0402_10V7K
SB_RX0P SB_TX0P SB_TX0P (23)
(23) SB_RX0N Y8 AE7 SB_TX0N_C C609 1 2 0.1U_0402_10V7K
SB_RX0N SB_TX0N SB_TX0N (23)
(23) SB_RX1P AA7 AE6 SB_TX1P_C C38 1 2 0.1U_0402_10V7K
SB_RX1P SB_TX1P SB_TX1N_C SB_TX1P (23)
(23) SB_RX1N Y7 AD6 C33 1 2 0.1U_0402_10V7K U20A
SB_RX1N SB_TX1N SB_TX2P_C SB_TX1N (23) H_CADOP0 H_CADIP0
(23) SB_RX2P AA5 PCIE I/F SB AB6 C37 1 2 0.1U_0402_10V7K Y25 D24
SB_RX2P SB_TX2P SB_TX2N_C SB_TX2P (23) H_CADON0 HT_RXCAD0P HT_TXCAD0P H_CADIN0
(23) SB_RX2N AA6 AC6 C32 1 2 0.1U_0402_10V7K Y24 PART 1 OF 6 D25
SB_RX2N SB_TX2N SB_TX2N (23) HT_RXCAD0N HT_TXCAD0N
(23) SB_RX3P W5 AD5 SB_TX3P_C C610 1 2 0.1U_0402_10V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P (23) HT_RXCAD1P HT_TXCAD1P
(23) SB_RX3N Y5 AE5 SB_TX3N_C C616 1 2 0.1U_0402_10V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N (23) HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R32 1 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R267 1 2 2K_0402_1% H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) +1.1VS HT_RXCAD3P HT_TXCAD3P
H_CADON3 U25 F22 H_CADIN3
H_CADOP4 HT_RXCAD3N HT_TXCAD3N H_CADIP4
RS880M_FCBGA528 H_CADON4
T25
HT_RXCAD4P HT_TXCAD4P
H23
H_CADIN4
T24 H22
H_CADOP5 HT_RXCAD4N HT_TXCAD4N H_CADIP5
RS780M Display Port Support (muxed on GFX) P22
HT_RXCAD5P HT_TXCAD5P
J25
H_CADON5 H_CADIN5

HYPER TRANSPORT CPU I/F

P23 J24
H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6
P25 HT_RXCAD6P HT_TXCAD6P K24
GFX_TX0,TX1,TX2 and TX3 H_CADON6 P24 K25 H_CADIN6
DP0 H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
N24 K23
AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
N25 K22
HT_RXCAD7N HT_TXCAD7N
H_CADOP8 AC24 F21 H_CADIP8
3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 H21
H_CADOP10 HT_RXCAD9N HT_TXCAD9N H_CADIP10
AA24 HT_RXCAD10P HT_TXCAD10P J20
H_CADON10 AA25 J21 H_CADIN10
H_CADOP11 HT_RXCAD10N HT_TXCAD10N H_CADIP11
Y22 J18
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 K17
H_CADOP12 HT_RXCAD11N HT_TXCAD11N H_CADIP12
W21 L19
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 J19
H_CADOP13 HT_RXCAD12N HT_TXCAD12N H_CADIP13
V21 HT_RXCAD13P HT_TXCAD13P M19
H_CADON13 V20 L18 H_CADIN13
H_CADOP14 HT_RXCAD13N HT_TXCAD13N H_CADIP14
U20 M21
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

(4) H_CLKOP0 T22 H24 H_CLKIP0 (4)

HT_RXCLK0P HT_TXCLK0P
(4) H_CLKON0 T23 H25 H_CLKIN0 (4)
HT_RXCLK0N HT_TXCLK0N
(4) H_CLKOP1 AB23 L21 H_CLKIP1 (4)
HT_RXCLK1P HT_TXCLK1P
(4) H_CLKON1 AA22 L20 H_CLKIN1 (4)
HT_RXCLK1N HT_TXCLK1N
H_CTLOP0 M22 M24 H_CTLIP0
(4) H_CTLOP0 H_CTLON0 HT_RXCTL0P HT_TXCTL0P H_CTLIN0 H_CTLIP0 (4)
(4) H_CTLON0 M23 M25 H_CTLIN0 (4)
H_CTLOP1 HT_RXCTL0N HT_TXCTL0N H_CTLIP1
(4) H_CTLOP1 R21 HT_RXCTL1P HT_TXCTL1P P19 H_CTLIP1 (4)
H_CTLON1 R20 R18 H_CTLIN1
(4) H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 (4)
1 R56 2 C23 B24 1 R51 2
HT_RXCALP HT_TXCALP
A24 B25
301_0402_1% HT_RXCALN HT_TXCALN 301_0402_1%
0718 Place within 1" RS880M_FCBGA528 0718 Place within 1"
layout 1:2 layout 1:2
4 4
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA
SA000032710 S IC 216-0752001 A11 RS880M FCBGA528 0FA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880-HT/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 10 of 49
A B C D E
 A B C D E

For RS780M A13

RED: Connected to GND through two separate 140ohm 1% resistor
www.bufanxiu.com
UMA@ 1 2 GMCH_CRT_R
R45 140_0402_1%
UMA@ 1 2 GMCH_CRT_G
R49 150_0402_1%
UMA@ 1 2 GMCH_CRT_B
R50 150_0402_1%
1 1

+3VS
AVDD=0.11A
PLLVDD=65mA
L15
+1.1VS +NB_PLLVDD 2 1 +AVDD1
L59 FBMA-L11-160808-221LMT_0603
1 1
2 1 AVDDDI=20mA C94
FBMA-L11-160808-221LMT_0603 +1.8VS C874 2.2U_0603_6.3V4Z
1 1
L10 1U_0402_6.3V4Z@
C645 C663 +AVDD2 2 2
2 1
2.2U_0603_6.3V4Z @ 1U_0402_6.3V4Z FBMA-L11-160808-221LMT_0603
1
2 2 U20C
C22 F12 A22 GMCH_TXOUT0+ (21)
+1.8VS 0.1U_0402_16V4Z AVDD1(NC) TXOUT_L0P(NC)
PLLVDD18=20mA 2
E12
AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC)
B22 GMCH_TXOUT0- (21)
+1.8VS +NB_HTPVDD
AVDDQ=4mA F14
AVDDDI(NC) TXOUT_L1P(NC)
A21 GMCH_TXOUT1+ (21)
L8 G15 B21 GMCH_TXOUT1- (21)
L13 +AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
2 1 H15 B20 GMCH_TXOUT2+ (21)
FBMA-L11-160808-221LMT_0603 AVDDQ(NC) TXOUT_L2P(NC)
2 1 1 1 H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 GMCH_TXOUT2- (21)
FBMA-L11-160808-221LMT_0603
1 1 A19
C935 C875 TXOUT_L3P(NC)
E17 B19
C93 C84 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
F17

CRT/TVOUT
2.2U_0603_6.3V4Z @ 1U_0402_6.3V4Z 2 2 @ Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
2 2
TXOUT_U0N(NC) A18
GMCH_CRT_R G18 A17
(22) GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
VDDA18HTPLL=20mA GMCH_CRT_G E18 D20
(22) GMCH_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 D21
+1.8VS +VDDA18HTPLL GMCH_CRT_B GREENb(NC) TXOUT_U2N(NC)
(22) GMCH_CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
L9 F19 D19
BLUEb(NC) TXOUT_U3N(NC)
2 1
GMCH_CRT_HSYNC A11
VDDLTP18=15mA
FBMA-L11-160808-221LMT_0603
1 1 B16 GMCH_TXCLK+ (21) L56
2 (13,22) GMCH_CRT_HSYNC GMCH_CRT_VSYNC B11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) +VDDLTP18 2
(13,22) GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 GMCH_TXCLK- (21) 1 2 +1.8VS
C934 C924 GMCH_CRT_CLK F8 D16 1 1 MBC1608121YZF_0603
(22) GMCH_CRT_CLK GMCH_CRT_DATA E8 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
2.2U_0603_6.3V4Z @ 1U_0402_6.3V4Z D17
2 2 (22) GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) C665 C644
R42 1 2 715_0402_1% G14 1U_0402_6.3V4Z@ 2.2U_0603_6.3V4Z
+1.8VS DAC_RSET(PWM_GPIO1) +VDDLTP18 2 2
VDDA18PCIEPLL=0.12A +NB_PLLVDD VDDLTP18(NC)
A13
U42 +NB_PLLVDD A12 B13
PLLVDD(NC) VSSLTP18(NC)
5

+1.8VS +VDDA18PCIEPLL NC7SZ08P5X_NL_SC70-5 +NB_HTPVDD D14

+NB_HTPVDD PLLVDD18(NC)
L14 NB_PWRGD 2 B12 A15 +VDDLT18

LVTM
P

B PLLVSS(NC) VDDLT18_1(NC)
2 1 4 B15 VDDLT18=0.3A

PLL PWR
FBMA-L11-160808-221LMT_0603 Y VDDLT18_2(NC) L12
1 1 (6,24,33) SB_PWRGD 1 A +VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
G

B14 +VDDLT18 1 2
VDDLT33_2(NC) +1.8VS
C87 C86 +VDDA18PCIEPLL D7 1 1 MBK1608221YZF_0603
3

2.2U_0603_6.3V4Z @ 1U_0402_6.3V4Z VDDA18PCIEPLL1 C90

E7 C14
2 2 R107 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS) 0.1U_0402_16V4Z C95
D15
NB_RESET# VSSLT2(VSS) 4.7U_0805_10V4Z
(13,14,23,30,31,33) PLT_RST# 1 2 D8 C16
NB_PWRGD_R A10 SYSRESETb VSSLT3(VSS) 2 2
(24) NB_PWRGD 1 2 C18
R511 @ 0_0402_5% NB_LDTSTOP# POWERGOOD VSSLT4(VSS)
C10 C20
NB_ALLOW_LDTSTOP C12 LDTSTOPb VSSLT5(VSS)
2 1 E20

PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R283 300_0402_5% C22
VSSLT7(VSS)
(20) CLK_NBHT C25
HT_REFCLKP
(20) CLK_NBHT# C24
CLK_NB_14.318M HT_REFCLKN
CLK_NB_14.318M E11 R744 0_0402_5%
(20) CLK_NB_14.318M REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 E9 1 2 UMA_ENVDD_R (21)
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
F7 UMA_VARIBL (21,33)
LVDS_BLON(PCE_RCALRP)
1

+1.1VS 1 2 1 2 (20) CLK_NBGFX T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 ENBKL (33)

1.27K_0402_1%

1.27K_0402_1%
R477 R564 R566 T1
(20) CLK_NBGFX# GFX_REFCLKN

2
@
100_0402_5% 4.7K_0402_5% 4.7K_0402_5%
@ U1 R469
GPP_REFCLKP

1 R441

1 R29
U2 4.7K_0402_5%
2

GPP_REFCLKN

@
3 3
1 (20) CLK_SBLINK_BCLK V4

2
GPPSB_REFCLKP(SB_REFCLKP)
(20) CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
C854
100P_0402_50V8J GMCH_LCD_CLK B9
2 (21) GMCH_LCD_CLK I2C_CLK
GMCH_LCD_DATA
@ (21) GMCH_LCD_DATA
GMCH_HDMI_DATA_R2
A9
B8
I2C_DATA MIS. TMDS_HPD(NC)
D9
D10
GMCH_HDMI_CLK_R2 DDC_DATA0/AUX0N(NC) HPD(NC)
A8
GMCH_HDMI_CLK DDC_CLK0/AUX0P(NC)
B7 D12 1 2 SUS_STAT# (24)
GMCH_HDMI_DATA DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5)
A7
DDC_DATA1/AUX1N(NC)
R106 0_0402_5% SUS_STAT_R# (13) Strap pin
THERMALDIODE_P AE8
POWER_SEL B10 AD8
(45) POWER_SEL STRP_DATA THERMALDIODE_N
G11 RSVD TESTMODE D13 1 2
R279
C8 1.8K_0402_5%
(13) AUX_CAL AUX_CAL(NC)

+3VS
Strap pin RS880M_FCBGA528
UMA@ POWER_SEL
R563 1 2 4.7K_0402_5% GMCH_LCD_CLK
R565 1 2 4.7K_0402_5% GMCH_LCD_DATA
HIGH 1.0V
UMA@
+3VS
LOW 1.1V
1

R460 +1.8VS
10K_0402_5%
@
2

4 4
2

0_0402_5%
POWER_SEL 1 2 NB_LDTSTOP#
(6,23) LDT_STOP#
R60 R280
1K_0402_5%
1

R1008
R59 0_0402_5%
2K_0402_5%
(23) ALLOW_LDTSTOP 1 2 NB_ALLOW_LDTSTOP Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 VEDIO/CLK GEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 11 of 49
A B C D E
 A B C D E

www.bufanxiu.com
U20F
A25 A2
VSSAHT1 VSSAPCIE1
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 D3
VSSAHT3 VSSAPCIE3
G22 VSSAHT4 VSSAPCIE4 D5
VDDHTRX+VDDHT=1.3A G24
VSSAHT5 VSSAPCIE5
E4
G25 VSSAHT6 VSSAPCIE6 G1
1 L71 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
+VDDHT
VDDHT=0.6A H19 VSSAHT7 VSSAPCIE7 G2
+1.1VS 2 1 J22 VSSAHT8 VSSAPCIE8 G4
L17 VSSAHT9 VSSAPCIE9 H7
MBK2012221YZF_0805 1 1 1 1 L22 J4
L3 VSSAHT10 VSSAPCIE10
L24 R7
C612 C344 C341 C928 VSSAHT11 VSSAPCIE11
1 2 +1.1VS L25 VSSAHT12 VSSAPCIE12 L1
VDDPCIE=2.5A FBMA-L11-201209-221LMA30T_0805 M20 L2
2 2 2 2 U20E VSSAHT13 VSSAPCIE13
N22 VSSAHT14 VSSAPCIE14 L4
4.7U_0805_10V4Z 0.1U_0402_16V4Z J17 A6 +VDDA11PCIE C30 1 2 10U_0805_10V4Z P20 L7
VDDHT_1 VDDPCIE_1 C28 VSSAHT15 VSSAPCIE15
VDDHTRX=0.7A K16 PART 5/6 B6 1 2 10U_0805_10V4Z R19 M6
VDDHT_2 VDDPCIE_2 VSSAHT16 VSSAPCIE16
L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
L11 0.1U_0402_16V4Z M16 D6 R24 P6
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C29 VSSAHT18 VSSAPCIE18
2 1 P16 VDDHT_5 VDDPCIE_5 E6 1 2 4.7U_0805_10V4Z R25 VSSAHT19 VSSAPCIE19 R1
R16 F6 H20 R2
MBK2012221YZF_0805 VDDHT_6 VDDPCIE_6 C930 VSSAHT20 VSSAPCIE20
1 1 1 1 T16 G7 1 2 1U_0402_6.3V4Z U22 R4
VDDHT_7 VDDPCIE_7 C929 VSSAHT21 VSSAPCIE21
H8 1 2 1U_0402_6.3V4Z V19 V7
C940 C336 C85 C931 VDDPCIE_8 VSSAHT22 VSSAPCIE22
H18 J9 W22 U4

GROUND
VDDHTRX_1 VDDPCIE_9 VSSAHT23 VSSAPCIE23
G19 K9 1 2 W24 V8
2 2 2 2 VDDHTRX_2 VDDPCIE_10 C88 VSSAHT24 VSSAPCIE24
F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z W25 VSSAHT25 VSSAPCIE25 V6
4.7U_0805_10V4Z 0.1U_0402_16V4Z E21 L9 C339 0.1U_0402_16V4Z Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 P9 AD25 W2
VDDHTRX_5 VDDPCIE_13 VSSAHT27 VSSAPCIE27
B23 R9 W4
VDDHTRX_6 VDDPCIE_14 VSSAPCIE28
VDDHTTX=0.68A A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L4 V9 M14 W8
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
+1.2V_HT 2 1 AE25 U9 N13 Y6
VDDHTTX_1 VDDPCIE_17 VSS13 VSSAPCIE31
AD24 VDDHTTX_2 P12 VSS14 VSSAPCIE32 AA4
MBK2012221YZF_0805 1 1 1 1 1 AC23 K12 +NB_CORE P15 AB5
VDDHTTX_3 VDDC_1 VSS15 VSSAPCIE33
AB22 J14 R11 AB1
C31 C49 C50 C342 C925 VDDHTTX_4 VDDC_2 VSS16 VSSAPCIE34
AA21 VDDHTTX_5 VDDC_3 U16 R14 VSS17 VSSAPCIE35 AB7
Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3
2 2 2 2 2
W19 K15 U14 AC4
VDDHTTX_7 VDDC_5 VSS19 VSSAPCIE37

POWER
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z V18 M12 NB_CORE=10A U11 AE1
2 VDDHTTX_8 VDDC_6 VSS20 VSSAPCIE38 2
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
FOR Version A11 pop 1.35VS A12 T17
VDDHTTX_10 VDDC_8
L11 V12
VSS22 VSSAPCIE40
AB2
use 1.2V_HT R17 M13 W11
VDDHTTX_11 VDDC_9 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
VDDA18PCIE=0.7A M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14

C27
C35

C23

C34

C343

C43

C337

C26

C340

C25

C36

C44
L5 N14 1 AA14 D11
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS26 VSS2
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8
P10 P13 + AB11 E14
MBK2012221YZF_0805 VDDA18PCIE_2 VDDC_14 VSS28 VSS4
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15

330U_D2E_2.5VM
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 R12 AB17 J15
C45 C47 C40 C51 C48 C345 VDDA18PCIE_4 VDDC_16 2 2 2 2 2 2 2 2 2 2 2 2 VSS30 VSS6
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
4.7U_0805_10V4Z W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 K11 L15
VDDA18PCIE_8 VDDC_20 VSS34 VSS10
R10 T14
VDDA18PCIE_9 VDDC_21 RS780M_FCBGA528
Y9 J16
VDDA18PCIE_10 VDDC_22
AA9
VDDA18PCIE_11
AB9 AE10
VDDA18PCIE_12 VDD_MEM1(NC)
AD9 AA11
VDDA18PCIE_13 VDD_MEM2(NC)
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 AD10
VDDA18PCIE_15 VDD_MEM4(NC)
VDD18=10mA VDD_MEM5(NC)
AB10
+1.8VS F9 AC10
VDD18_1 VDD_MEM6(NC)
G9
VDD18_2 VDD33=60mA
AE11 H11 +3VS
VDD18_MEM1(NC) VDD33_1(NC)
AD11 H12
VDD18_MEM2(NC) VDD33_2(NC)
1 1
1 RS880M_FCBGA528
C89 C338 C24
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z U20D
2 2 PAR 4 OF 6
2
AB12 AA18
3 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) 3
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 Y19
MEM_A3(NC) MEM_DQ3/DVO_D0(NC)
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 AA17
MEM_A5(NC) MEM_DQ5/DVO_D1(NC)
AB14 AA15
MEM_A6(NC) MEM_DQ6/DVO_D2(NC)
AD14 Y15
MEM_A7(NC) MEM_DQ7/DVO_D4(NC)
AD13 AC20
MEM_A8(NC) MEM_DQ8/DVO_D3(NC)
AD15 AD19
MEM_A9(NC) MEM_DQ9/DVO_D5(NC)
AC16 AE22

SBD_MEM/DVO_I/F
MEM_A10(NC) MEM_DQ10/DVO_D6(NC)
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 AB20
MEM_A12(NC) MEM_DQ12(NC)
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
AC22
MEM_DQ14/DVO_D10(NC)
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17
MEM_BA1(NC)
AD17 Y17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC)
W18
MEM_DQS0N/DVO_IDCKN(NC)
W12 AD20
MEM_RASb(NC) MEM_DQS1P(NC)
Y12 AE21
MEM_CASb(NC) MEM_DQS1N(NC)
AD18
MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
AE19 15mA
V14 MEM_ODT(NC)
AE23 +1.8VS
IOPLLVDD18(NC)
V15 AE24 +1.1VS
MEM_CKP(NC) IOPLLVDD(NC)
W14 MEM_CKN(NC)
IOPLLVSS(NC)
AD23 26mA
AE12
MEM_COMPP(NC)
AD12 AE18
MEM_COMPN(NC) MEM_VREF(NC)
RS780M_FCBGA528
4 4
+1.8VS=W/S=20/10mil For Memory PLL power
+1.1VS=W/S=20/10mil For Memory PLL power

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 PWR/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 12 of 49
A B C D E
 A B C D E

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DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

(11,22) GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC)
R560 3K_0402_5% 1 : Disable (RS880m)
2 1 0 : Enable (RS880M)
1 R559 @ 3K_0402_5% 1

DFT_GPIO1: LOAD_EEPROM_STRAPS

(11) AUX_CAL 1 2 Selects Loading of STRAPS from EPROM

@ R284 150_0402_1% 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
D29
@ CH751H-40_SC76
0 : I2C Master can load strap values from EEPROM if connected, or use
RS780 DFT_GPIO1 2 1 default values if not connected
(11) SUS_STAT_R# PLT_RST# (11,14,23,30,31,33)
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

2 2

RS780 use HSYNC to enable SIDE PORT

RS780 use HSYNC to enable SIDE PORT RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS880M)
2 1
1 : Disable(RS880M)
(11,22) GMCH_CRT_HSYNC +3VS
R281 3K_0402_5%
2 @ 1
R282 3K_0402_5%

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 STRAPS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 13 of 49
A B C D E
 5 4 3 2 1

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PCIE_GTX_C_MRX_P[0..15]
(10) PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15]
U40A (10) PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P[0..15]
(10) PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]
(10) PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P0 AF30 AH30 PCIE_GTX_MRX_P0 C131

1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N0 VGA@ PCIE_GTX_C_MRX_N0
AE31 PCIE_RX0N PCIE_TX0N AG31 1 2
D C102 0.1U_0402_10V7K D

PCIE_MTX_C_GRX_P1 AE29 AG29 PCIE_GTX_MRX_P1 C126

1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_GTX_MRX_N1 VGA@ PCIE_GTX_C_MRX_N1
AD28 PCIE_RX1N PCIE_TX1N AF28 1 2
C130 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P2 AD30 AF27 PCIE_GTX_MRX_P2 C101

1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P2 U40F
PCIE_MTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N2 VGA@ PCIE_GTX_C_MRX_N2
AC31 PCIE_RX2N PCIE_TX2N AF26 1 2
C107 0.1U_0402_10V7K VGA@1 R292 2
10K_0402_5%
PCIE_MTX_C_GRX_P3 AC29 AD27 PCIE_GTX_MRX_P3 C112
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P3 LVDS CONTROL AB11 VGA@1 R128 2
PCIE_RX3P PCIE_TX3P VARY_BL VGA_VARIBL (21,33)
PCIE_MTX_C_GRX_N3 AB28 AD26 PCIE_GTX_MRX_N3 1 2 VGA@ PCIE_GTX_C_MRX_N3 AB12 0_0402_5%
PCIE_RX3N PCIE_TX3N DIGON VGA_ENVDD (21)
C129 0.1U_0402_10V7K
VGA@1 R907 2
PCIE_MTX_C_GRX_P4 AB30 AC25 PCIE_GTX_MRX_P4 C124
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P4 10K_0402_5%
PCIE_RX4P PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_MTX_C_GRX_N4 AA31 AB25 PCIE_GTX_MRX_N4 1 2 VGA@ PCIE_GTX_C_MRX_N4 add at 8/11
PCIE_RX4N PCIE_TX4N C83 0.1U_0402_10V7K
TXCLK_UP_DPF3P AH20
TXCLK_UN_DPF3N AJ19
PCIE_MTX_C_GRX_P5 AA29 Y23 PCIE_GTX_MRX_P5 C123
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P5
PCIE_MTX_C_GRX_N5 PCIE_RX5P PCIE_TX5P PCIE_GTX_MRX_N5 VGA@ PCIE_GTX_C_MRX_N5
Y28 PCIE_RX5N PCIE_TX5N Y24 1 2 TXOUT_U0P_DPF2P AL21
C98 0.1U_0402_10V7K AK20
TXOUT_U0N_DPF2N
PCIE_MTX_C_GRX_P6 Y30 AB27 PCIE_GTX_MRX_P6 C103
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P6 AH22
PCIE_MTX_C_GRX_N6 PCIE_RX6P PCIE_TX6P PCIE_GTX_MRX_N6 VGA@ PCIE_GTX_C_MRX_N6 TXOUT_U1P_DPF1P
C W31 PCIE_RX6N PCIE_TX6N AB26 1 2 TXOUT_U1N_DPF1N AJ21 C
C105 0.1U_0402_10V7K
TXOUT_U2P_DPF0P AL23
PCIE_MTX_C_GRX_P7 W29 Y27 PCIE_GTX_MRX_P7 C110
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P7 AK22
PCIE_MTX_C_GRX_N7 PCIE_RX7P PCIE_TX7P PCIE_GTX_MRX_N7 VGA@ PCIE_GTX_C_MRX_N7 TXOUT_U2N_DPF0N
V28 PCIE_RX7N PCIE_TX7N Y26 1 2
C125 0.1U_0402_10V7K AK24
TXOUT_U3P
TXOUT_U3N AJ23
PCIE_MTX_C_GRX_P8 V30 W24 PCIE_GTX_MRX_P8 C133
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N8 VGA@ PCIE_GTX_C_MRX_N8
U31 PCIE_RX8N PCIE_TX8N W23 1 2
C135 0.1U_0402_10V7K LVTMDP change at 8/11
PCIE_MTX_C_GRX_P9 U29 V27 PCIE_GTX_MRX_P9 C128
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P9 AL15
PCIE_RX9P PCIE_TX9P TXCLK_LP_DPE3P VGA_TXCLK+ (21)
PCIE_MTX_C_GRX_N9 T28 U26 PCIE_GTX_MRX_N9 1 2 VGA@ PCIE_GTX_C_MRX_N9 AK14
PCIE_RX9N PCIE_TX9N TXCLK_LN_DPE3N VGA_TXCLK- (21)
C132 0.1U_0402_10V7K
TXOUT_L0P_DPE2P AH16 VGA_TXOUT0+ (21)
PCIE_MTX_C_GRX_P10 T30 U24 PCIE_GTX_MRX_P10 C108
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P10 AJ15
PCIE_RX10P PCIE_TX10P TXOUT_L0N_DPE2N VGA_TXOUT0- (21)
PCIE_MTX_C_GRX_N10 R31 U23 PCIE_GTX_MRX_N10 1 2 VGA@ PCIE_GTX_C_MRX_N10
PCIE_RX10N PCIE_TX10N C113 0.1U_0402_10V7K
TXOUT_L1P_DPE1P AL17 VGA_TXOUT1+ (21)
TXOUT_L1N_DPE1N AK16 VGA_TXOUT1- (21)
PCIE_MTX_C_GRX_P11 R29 T26 PCIE_GTX_MRX_P11 C127
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P11
PCIE_MTX_C_GRX_N11 PCIE_RX11P PCIE_TX11P PCIE_GTX_MRX_N11 VGA@ PCIE_GTX_C_MRX_N11
P28 PCIE_RX11N PCIE_TX11N T27 1 2 TXOUT_L2P_DPE0P AH18 VGA_TXOUT2+ (21)
C99 0.1U_0402_10V7K AJ17
TXOUT_L2N_DPE0N VGA_TXOUT2- (21)
PCIE_MTX_C_GRX_P12 P30 T24 PCIE_GTX_MRX_P12 C134
1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P12 AL19
PCIE_MTX_C_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N12 VGA@ PCIE_GTX_C_MRX_N12 TXOUT_L3P
B N31 PCIE_RX12N PCIE_TX12N T23 1 2 TXOUT_L3N AK18 B
C104 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P13 N29 P27 PCIE_GTX_MRX_P13 C109

1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P13
PCIE_MTX_C_GRX_N13 PCIE_RX13P PCIE_TX13P PCIE_GTX_MRX_N13 VGA@ PCIE_GTX_C_MRX_N13
M28 PCIE_RX13N PCIE_TX13N P26 1 2
C136 0.1U_0402_10V7K M9X-S2/S3 + Park-S3

PCIE_MTX_C_GRX_P14 M30 P24 PCIE_GTX_MRX_P14 C106

1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P14 PARK@
PCIE_MTX_C_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_GTX_MRX_N14 VGA@ PCIE_GTX_C_MRX_N14
L31 PCIE_RX14N PCIE_TX14N P23 1 2
C111 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P15 L29 M27 PCIE_GTX_MRX_P15 C97

1 0.1U_0402_10V7K
2 VGA@ PCIE_GTX_C_MRX_P15
PCIE_MTX_C_GRX_N15 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N15 VGA@ PCIE_GTX_C_MRX_N15
K30 PCIE_RX15N PCIE_TX15N N26 1 2
C100 0.1U_0402_10V7K

CLOCK U40
CLK_PCIE_VGA AK30
(20) CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32
(20) CLK_PCIE_VGA# PCIE_REFCLKN

PARK@ CALIBRATION
R293
2 10K_0402_5%
1 Y22 1.27K_0402_1%
1 VGA@ 2R159 M93-S3
PCIE_CALRP M93@
A
(44) VGA_PWROK 1 R127 2 N10 PWRGOOD PCIE_CALRN AA22 2K_0402_5%
1 VGA@ 2R333 +VGA_PCIE
A
@ 0_0402_5%

PLT_RST#
23,30,31,33) PLT_RST# AL27 PERSTB Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
M9X-S2/S3 + Park-S3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 PCIE/LVDS
PARK@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 14 of 49
5 4 3 2 1
 5 4 3 2 1

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CLK_XTALIN CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR

1
U40B
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
R972 THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
1M_0402_5%
VGA@

2
L40 M93-S3/M92-S2 AF2 CLK_XTALOUT STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
+DPC_VDD18 TXCAP_DPA3P
+1.8VS_VGA 2 1 AE9 AF4
BLM15BD121SN1D_0402 PARK@ PARK@ PARK@ DVCNTL_0/ DVPDATA_18 TXCAM_DPA3N Y6
L9
DVCNTL_1 / NC

C56
PARK@ TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0

C322

C695
1 1 1 130mA N9 AG3 1 2

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
DVCNTL_2 / TESTEN#2 TX0P_DPA2P
AE8
DVDATA_12 / DVPDATA_16 DPA TX0M_DPA2N
AG5
AD9 27MHZ_20P_7A27000010
DVDATA_11 / DVPDATA_20 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
AC10 AH3 1 1
2 2 2 DVDATA_10 / DVPDATA_22 TX1P_DPA1P
AD7 AH1 VGA@
DVDATA_9 / DVPDATA_12 TX1M_DPA1N
AC8
DVDATA_8 / DVPDATA_14 C1021 C1022 BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 0
AC7 AK3
D DVDATA_7 / DVPCNTL_0 TX2P_DPA0P 2 22P_0402_50V8J VGA@ 2 22P_0402_50V8J VGA@
D
AB9 AK1
DVDATA_6 / DVPDATA_8 TX2M_DPA0N
AB8
DVDATA_5 / DVPDATA_6 EMI request
AB7 AK5 GPIO8 0
AB4
DVDATA_4 DVPDATA_4 TXCBP_DPB3P
AM3 add at 8/17
VRAM_ID2 DVDATA_3 / DVPDATA_19 TXCBM_DPB3N
(16) VRAM_ID2 AB2
VRAM_ID1 DVDATA_2 / DVPDATA_21 +3VS_VGA BIF_VGA DIS GPIO9 VGA ENABLED 0
Y8 AK6
+VGA_PCIE L23
(16)
(16)
VRAM_ID1
VRAM_ID0
VRAM_ID0 Y7
DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0
TX3P_DPB2P
TX3M_DPB2N
AM5 STRAPS
2 1 +DPC_VDD10 DPB
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ AJ7 GPIO21 0
TX4P_DPB1P
C57

VGA@ DVO
C324

C694

1 1 1 200mA AH6
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K
TX4M_DPB1N GPU_GPIO0 R232 2 VGA@ 1 10K_0402_5%
AK8 GPU_GPIO1 @ R228 2 1 10K_0402_5% BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
TX5P_DPB0P GPU_GPIO2 @ R215
AL7 2 1 10K_0402_5%
2 2 2 TX5M_DPB0N
M93-S3/M92-S2 GPU_GPIO8 @ R233 2 1 10K_0402_5% ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 001
+DPC_PVDD W6 GPU_GPIO9 @ R231 2 1 10K_0402_5%
DPC_PVDD / DVPDATA_11 GPIO21_BBEN @ R216
V6 M92-S2/M93-S3 2 1 10K_0402_5%
DPC_PVSS / GND VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
V4
+DPC_VDD18 DVPDATA_3/TXCCP_DPC3P GPU_GPIO11 R217
AC6 U5 2 VGA@ 1 10K_0402_5%
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N GPU_GPIO12 @ R236
AC5 2 1 10K_0402_5%
DPC_VDD18#2/DVPDAT23 GPU_GPIO13 @ R234
W3 2 1 10K_0402_5% H2SYNC 0
L24 +DPC_VDD10 DVPDATA_7 / TX0P_DPC2P
AA5 V2
+DPC_PVDD DPC_VDD10#1/DVPDAT15 DVPDATA_1 / TX0M_DPC2N
+1.8VS_VGA 2 1 AA6
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ DPC_VDD10#2/DVPDAT17 VGA_CRT_HSYNC @ R229 10K_0402_5% GENERICC 0
Y4 2 1
DVPCNTL_MV1 / TX1P_DPC1P
C55

VGA@ VGA_CRT_VSYNC @ R230 10K_0402_5%

C323

C696

1 1 1 20mA W5 2 1
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K

DVPDATA_9 / TX1M_DPC1N VGA_CRT_VSYNC2 @ R235 10K_0402_5% AUD[1] AUD[0]

2 1
U1 AA3 VGA_CRT_HSYNC2 @ R108 2 1 10K_0402_5% AUD[1] HSYNC 0 0 No audio function
DPC_VSSR#1 / DVPCLK DVPDATA_13 / TX2P_DPC0P GPU_GPIO8 @ R1018 10K_0402_5% 11
W1 Y2 2 1 0 1 Audio for DisplayPort and HDMI if dongle is detected
2 2 2 DPC_VSSR#2 / DVPDAT5 DVPCNTL_1 / TX2M_DPC0N AUD[0] VSYNC
U3 1 0 Audio for DisplayPort only
DPC_VSSR#3 / GND
Y6 AA12 1 1 Audio for both DisplayPort and HDMI
DPC_VSSR#4 / GND VDDR4 / DPCD_CALR
AA1
DPC_VSSR#5/ DVPCNTL_MV0

1
R310 AMD RESERVED CONFIGURATION STRAPS
DPC 150_0402_1%
VGA@ ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,

2
THEY MUST NOT CONFLICT DURING RESET
C VGA_LCD_CLK R1 C
(21) VGA_LCD_CLK SCL
VGA_LCD_DATA R3 I2C
(21) VGA_LCD_DATA SDA H2SYNC GENERICC
AM26 VGA_CRT_R
GENERAL PURPOSE I/O R VGA_CRT_R (22)
AK26
GPU_GPIO0 RB
GPU_GPIO1
U6
GPIO_0 VGA_CRT_G
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
U10 AL25 VGA_CRT_G (22)
GPIO_1 G THEY MUST NOT CONFLICT DURING RESET
+3VS_VGA 1 R300 @2 GPU_GPIO2 T10 AJ25
10K_0402_5% GPU_GPIO3 GPIO_2 GB
U8
D4 GPU_GPIO4 GPIO_3_SMBDATA VGA_CRT_B
U7 AH24 VGA_CRT_B (22)
GPIO_4_SMBCLK B GPIO21_BB_EN
(25,33,39) ACIN 1 2 T9 AG25
GPIO_5_AC_BATT BB
@ RB751V_SOD323 T8
GPIO_6 DAC1
VGA_ENBKL T7 AH26 VGA_CRT_HSYNC
(33) VGA_ENBKL GPIO_7_BLON HSYNC VGA_CRT_HSYNC (22) +3VS_VGA
GPU_GPIO8 P10 AJ27 VGA_CRT_VSYNC L98
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC (22)
GPU_GPIO9 P4 +3VS_VGA 2 1 +A2VDD
GPIO_9_ROMSI L96 BLM15BD121SN1D_0402 PARK@ PARK@ PARK@
P2
GPU_GPIO11 GPIO_10_ROMSCK +AVDD GPU_GPIO3
1 R482 2 VGA@ PARK@ R303 1 2@ 10K_0402_5%

C1004

C1005

C1006
N6 AD22 +1.8VS_VGA 2 1 1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
GPU_GPIO12 GPIO_11 RSET
N5
GPIO_12 70mA499_0402_1% BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ R297 1 2@ 10K_0402_5% GPU_GPIO4
GPU_GPIO13 +AVDD VGA@

C998

C999
C1000
N3 AG24 1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
GPIO_13 AVDD R287 1 VGA_PWRSEL
Y9 AE22 2@ 10K_0402_5%
VGA_PWRSEL GPIO_14_HPD2 AVSSQ 2 2 2
(44) VGA_PWRSEL N1
GPIO_15_PWRCNTL_0 45mA
(20) 27M_SSC 1 R840 2R_27M_SSC M4 AE23 +VDD1DI R302 1 2@ 10K_0402_5% GPIO24_TRSTB
@ 0_0402_5%
THM_ALERT# GPIO_16_SSIN VDD1DI 2 2 2 R305
R6 AD23 1 2@ 10K_0402_5% GPIO25_TDI
GPIO_17_THERMAL_INT VSS1DI R294 GPIO26_TCK
W10 1 2@ 10K_0402_5%
GPIO_18_HPD3 GPIO27_TMS
1 R301 2 @ M2 M92-S2/M93-S3 R299 1 2@ 10K_0402_5%
10K_0402_5% GPIO_19_CTF R298
P8 AM12 1 2@ 10K_0402_5% GPIO28_TDO
GPIO21_BBEN GPIO_20_PWRCNTL_1 R2 / NC L100 R483 TEST_EN
(17) GPIO21_BBEN P7 AK12 1 2@ 5.11K_0402_1%
GPIO_21_BB_EN R2B / NC L97 +A2VDDQ R341
N8 +1.8VS_VGA 2 1 2 VGA@ 1 4.7K_0402_5% VGA_LCD_DATA
GPIO_22_ROMCSB

2
N7 AL11 +1.8VS_VGA 2 1 +VDD1DI BLM15BD121SN1D_0402 PARK@ PARK@ PARK@ R342 2 VGA@ 1 4.7K_0402_5% VGA_LCD_CLK
GPIO_23_CLKREQB G2 / NC BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ PARK@ R315

C1010

C1011

C1012
AJ11 1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
G2B / NC VGA@

C1001

C1002

C1003
1 1 1 10K_0402_5%

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
AK10 VGA@
GPIO24_TRSTB B2 / NC
L6 AL9

1
GPIO25_TDI JTAG_TRSTB B2B / NC 2 2 2
L5
GPIO26_TCK JTAG_TDI 2 2 2
L3
GPIO27_TMS JTAG_TCK
L1 AH12
GPIO28_TDO JTAG_TMS C / NC
K4
JTAG_TDO DAC2 Y / NC
AM10
+3VS_VGA
TEST_EN AF24 AJ9
B (16) TEST_EN TESTEN COMP / NC B

AB13 VGA_CRT_R
GENERICA VGA_CRT_HSYNC2 L99
W8 AL13
GENERICB H2SYNC VGA_CRT_VSYNC2 +VDD2DI +3VS_VGA VGA_CRT_G
W9 AJ13 +1.8VS_VGA 2 1
GENERICC V2SYNC

1
W7 BLM15BD121SN1D_0402 PARK@ PARK@ PARK@
GENERICD PARK@ R714 R713 VGA_CRT_B
50mA

C1007

C1008

C1009
AD10 1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
GENERICE_HPD4 +VDD2DI 10K_0402_5% 10K_0402_5%
AD19
VDD2DI / NC

R311 1

R309 1

R308 1
AC14 AC19 VGA@ VGA@

150_0402_1%

150_0402_1%

150_0402_1%
HPD1 VSS2DI / NC

2
R481

2
+1.8VS_VGA 2 2 2
130mA
1 2 AE20 +A2VDD VGA_SMB_CK2_R 1 6
A2VDD / NC VGA_SMB_CK2 (33)
499_0402_1% 1.5mA

2
5
VGA@ AE17 +A2VDDQ Q54A
+VREFG_GPU A2VDDQ / NC 2N7002DW-T/R7_SOT363-6
add at 8/11 AC16
VREFG
VGA@ AE19 VGA_SMB_DA2_R VGA@ 4 3 VGA@ VGA@ VGA@
+1.8VS_VGA +DPLL_PVDD A2VSSQ VGA_SMB_DA2 (33)
C58

L83 1 add at 8/11

0.1U_0402_10V6K
1

2 1 Q54B VGA@
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ AG13 1 R908 2 VGA@ 2N7002DW-T/R7_SOT363-6
VGA@ 249_0402_1% R2SET / NC 715_0402_1%
C951

C952

C953

1 1 1
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

VGA@ 2
M92-S2/M93-S3 M92-S2/M93-S3 VGA Thermal Sensor G781-1P8F
2

+DPLL_PVDD VGA_CRT_CLK
2 2 2 PLL/CLOCK DDC1CLK
AE6
VGA_CRT_DATA
VGA_CRT_CLK (22) Closed to GPU +3VS_VGA
120mA DDC1DATA
AE5 VGA_CRT_DATA (22)
AF14
R332 DPLL_PVDD
AE14 AD2
DPLL_PVSS AUX1P
AD4 2
DDC/AUX AUX1N C137
300mA
+DPLL_VDDC AD14 AC11
DPLL_VDDC DDC2CLK 0.1U_0402_16V4Z
DDC2DATA
AC13 add at 8/11 1
CLK_XTALIN 1 R843 2 27MCLK_SSIC @ VGA@
@ 0_0402_5%
(20) 27M_CLK
R582 2 1 82.5_0402_1% CLK_XTALIN AM28 AD13 U26
XTALOUT_XTL1 R842 CLK_XTALOUT XTALIN AUX2P VGA_SMB_CK2_R
2 AK28 AD11 1 8
@ 0_0402_5% XTALOUT AUX2N +VGA_PCIE L101 +DPLL_VDDC VDD1 SCLK
AE16 2 1 GPU_THERMAL_D+ 2 7 VGA_SMB_DA2_R
DDCCLK_AUX5P D+ SDATA
1

AD16 BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ C708VGA@

R160 DDCDATA_AUX5N VGA@
C1015

C1014

C1013

AC22 1 1 1 1 2 3 6
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

100_0402_1% NC#2/XO_IN D- ALERT#

AB22 AC1
U46 +3VS_VGA @ NC#1/XO_IN2 DDC6CLK GPU_THERMAL_D- 2200P_0402_50V7K THM_ALERT#
A AC3 4 5 A
27MCLK_SSIC DDC6DATA THERM# GND
1 6
2

REFOUT VSS 2 2 2
AD20
NC/DDCCLK_AUX3P G780P81U_MSOP8
2 5 AC20 2 1 +3VS_VGA
XOUT MODOUT THERMAL NC/DDCDATA_AUX3N 4.7K_0402_5% VGA@ R340
XTALOUT_XTL 3 4 GPU_THERMAL_D+ T4 VGA@
XIN/CLKIN VDD GPU_THERMAL_D- DPLUS
T2
DMINUS
@ ASM3P2872AF-06OR_TSOT-23-6 +1.8VS_VGA
T69 PAD R5
R_27M_SSC R841 2 TS_FDO
1
33_0402_1% @
1 1
@ @ VGA@
AD17
AC17
TSVDD
TSVSS
Security Classification Compal Secret Data Compal Electronics, Inc.
C949 2008/10/06 2009/10/06
C1040

C1041

C1042

1 1 1 Issued Date Title

10U_0603_6.3V6M

Deciphered Date
1U_0402_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K M9X-S2/S3 + Park-S3

08/11 C950 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 Main Generic/MSIC
1U_0402_6.3V4Z PARK@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2 2 2 C 1.0
Spread Spectrum For EMI @ @
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 15 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com
U40C
M_DA[63..0]
(19) M_DA[63..0]
M_MA[13..0] M_DA0 K27 K17 M_MA0
(19) M_MA[13..0] DQA_0 MAA_0 +1.8VS_VGA
M_DA1 J29 J20 M_MA1
M_DQM[7..0] M_DA2 DQA_1 MAA_1 M_MA2
(19) M_DQM[7..0] H30 DQA_2 MAA_2 H23
M_DA3 H32 G23 M_MA3 R834 1 2 H@ 10K_0402_5% VRAM_ID0
M_DQS[7..0] DQA_3 MAA_3 VRAM_ID0 (15)
M_DA4 G29 G24 M_MA4 R835 1 2 S@ 10K_0402_5%
(19) M_DQS[7..0] DQA_4 MAA_4
M_DA5 F28 H24 M_MA5 R836 1 2 S@ 10K_0402_5% VRAM_ID1

MEMORY INTERFACE
M_DQS#[7..0] DQA_5 MAA_5 VRAM_ID1 (15)
M_DA6 F32 J19 M_MA6 R837 1 2 H@ 10K_0402_5%
(19) M_DQS#[7..0] DQA_6 MAA_6
M_DA7 F30 K19 M_MA7 R838 1 2 @ 10K_0402_5% VRAM_ID2
D DQA_7 MAA_7 VRAM_ID2 (15) D
M_DA8 C30 J14 M_MA8 R839 1 2 10K_0402_5%
M_DA9 DQA_8 MAA_8 M_MA9
F27 DQA_9 MAA_9 K14
+1.8VS_VGA M_DA10 A28 J11 M_MA10
M_DA11 DQA_10 MAA_10 M_MA11
C28 DQA_11 MAA_11 J13
M_DA12 E27 H11 M_MA12
DQA_12 MAA_12
1

M_DA13 G26 G11 M_BA2

DQA_13 MAA_13/BA2 M_BA2 (19)
M_DA14 D26 J16 M_BA0
DQA_14 MAA_14/BA0 M_BA0 (19)
R164 M_DA15 F25 L15 M_BA1
DQA_15 MAA_15/BA1 M_BA1 (19)
100_0402_5% M_DA16 A25 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
VGA@ M_DA17 DQA_16 M_DQM0
C25 E32
2

MVREFDA M_DA18 DQA_17 DQMA_0 M_DQM1

E25 DQA_18 DQMA_1 E30
M_DA19 D24 A21 M_DQM2 Hynix H5TQ1G63BFR-12C 1 0 0
M_DA20 DQA_19 DQMA_2 M_DQM3
E23 DQA_20 DQMA_3 C21
1

1 M_DA21 F23 E13 M_DQM4

M_DA22 DQA_21 DQMA_4 M_DQM5
D22 DQA_22 DQMA_5 D12
R163 C295 M_DA23 F21 E3 M_DQM6 Samsung K4W1G1646E-HC12 0 1 0
100_0402_5% 0.1U_0402_16V4Z M_DA24 DQA_23 DQMA_6 M_DQM7
E21 DQA_24 DQMA_7 F4
VGA@ 2 VGA@ M_DA25 D20
2

M_DA26 DQA_25 M_DQS0

F19 DQA_26 RDQSA_0 H28
M_DA27 A19 C27 M_DQS1
M_DA28 DQA_27 RDQSA_1 M_DQS2
D18 DQA_28 RDQSA_2 A23
M_DA29 F17 E19 M_DQS3
+1.8VS_VGA M_DA30 DQA_29 RDQSA_3 M_DQS4
A17 DQA_30 RDQSA_4 E15
C
M_DA31 C17 D10 M_DQS5 C
M_DA32 DQA_31 RDQSA_5 M_DQS6
E17 DQA_32 RDQSA_6 D6
1

M_DA33 D16 G5 M_DQS7

M_DA34 DQA_33 RDQSA_7
F15 DQA_34
R166 M_DA35 A15 H27 M_DQS#0
100_0402_5% M_DA36 DQA_35 WDQSA_0 M_DQS#1
D14 DQA_36 WDQSA_1 A27
VGA@ M_DA37 F13 C23 M_DQS#2
2

MVREFSA M_DA38 DQA_37 WDQSA_2 M_DQS#3

M_DA39
A13
C13
DQA_38 WDQSA_3 C19
C15 M_DQS#4
M93-S3 PARK-S3
M_DA40 DQA_39 WDQSA_4 M_DQS#5
E11 DQA_40 WDQSA_5 E9
1

1 M_DA41 A11 C5 M_DQS#6 R306 NA 10K

M_DA42 DQA_41 WDQSA_6 M_DQS#7
C11 DQA_42 WDQSA_7 H4
R165 C313 M_DA43 F11
100_0402_5% 0.1U_0402_16V4Z M_DA44 DQA_43 M_ODT0
VGA@ 2 VGA@ M_DA45
A9
C9
DQA_44 ODTA0 L18
K16 M_ODT1
M_ODT0 (19) R579 0/short 680
M_ODT1 (19)
2

M_DA46 DQA_45 ODTA1

F9 DQA_46
M_DA47 M_CLK0
M_DA48
D8
E7
DQA_47 CLKA0 H26
H25 M_CLK#0
M_CLK0 (19) R320 2.2K NA
DQA_48 CLKA0B M_CLK#0 (19)
M_DA49 A7
R485 R486 R312 C311 C312 M_DA50 DQA_49 M_CLK1
M_DA51
C7
F7
DQA_50 CLKA1 G9
H9 M_CLK#1
M_CLK1 (19) C287 2.2nF 68pF
DQA_51 CLKA1B M_CLK#1 (19)
M_DA52 A5
M_DA53 DQA_52 M_RAS#0
E5 DQA_53 RASA0B G22 M_RAS#0 (19)
M_DA54 C3 G17 M_RAS#1
DQA_54 RASA1B M_RAS#1 (19)
B M_DA55 E1 R579 C287 B
M_DA56 DQA_55 M_CAS#0
4.7K_0402_5% 4.7K_0402_5% 240_0402_1%0_0402_5% 0_0402_5% G7 DQA_56 CASA0B G19 M_CAS#0 (19)
M93@ M93@ M93@ M93@ M93@ M_DA57 G6 G16 M_CAS#1 +VGA_CORE
DQA_57 CASA1B M_CAS#1 (19)
M_DA58 G1
M_DA59 DQA_58 M_CS#0
G3 DQA_59 CSA0B_0 H22 M_CS#0 (19)
M93-S3 PARK-S3 M_DA60 J6 J22
M_DA61 DQA_60 CSA0B_1
J1 DQA_61 0_0402_5% 2200P_0402_50V7K

1
M_DA62 J3 G13 M_CS#1 M93@ M93@
DQA_62 CSA1B_0 M_CS#1 (19)
R330 NC 240 M_DA63 J5 K13 R320
DQA_63 CSA1B_1 2.2K_0402_5%
MVREFDA K26 K20 M_CKE0 M93@
MVREFDA CKEA0 M_CKE0 (19)
R130 NC 0/short MVREFSA J26 J17 M_CKE1
M_CKE1 (19) R579

2
MVREFSA CKEA1
+1.8VS_VGA 1 2 PARK@
J25 G25 M_WE#0 DRAM_RST 1 PARK@ 2
MEM_CALRN0 WEA0B M_WE#0 (19) DRAM_RST# (19)
1R330 240_0402_1% M_WE#1
R312 240 150 (15) TEST_EN
R130
2
0_0402_5% PARK@
K7 NC/TESTEN#2 WEA1B H10 M_WE#1 (19)
680_0402_5%

1
1 2 PARK@J8 AB16 1
MEM_CALRP1/DPC_CALR PX_EN
R331 NC 240 1R312 150_0402_1%
2 K25 MEM_CALRP0
R306 C287
R331 240_0402_1%
PARK@ 10K_0402_5% 68P_0402_50V8J
DRAM_RST L10 PARK@ PARK@
PARK@ PARK@ DRAM_RST 2
G14

2
RSVD#2
M93-S3 PARK-S3 1R486 51.1_0402_1%
2 1C311 20.1U_0402_16V4Z K8 CLKTESTA
1 2 1 2 L7 G20 M_MA13
R485 51.1_0402_1% C312 0.1U_0402_16V4Z CLKTESTB RSVD#3
A
R485 4.7K 51.1 PARK@ PARK@ A
M9X-S2/S3 + Park-S3
PARK@
R486 4.7K 51.1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
C311 0/short 0.1uF PARK-S3 MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C312 0/short 0.1uF B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 16 of 49
5 4 3 2 1
 5 4 3 2 1

DPE_VDD10
DPF_VDD10
Park-S3: TMDS/DP=110mA@1.0V : LVDS=120mA@1.0V
M9X-S2/S3: TMDS/DP=170mA@1.1V LVDS=100mA@1.1V
www.bufanxiu.com +1.8VS_VGA

1
L84

PARK@
2
PARK@PARK@ PARK@
+DPA_VDD18

0.1U_0402_10V6K
10U_0603_6.3V6M
C954

C955

C91
1U_0402_6.3V4Z
U40G MBK1608121YZF_0603 1 1 1
+1.8VS_VGA
+DPE_VDD18 DP E/F POWER DP A/B POWER
L30
130mA
2 1
200mA AG15 AE11 +DPA_VDD18 2 2 2
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ DPE_VDD18#1 DPA_VDD18#1
AG16 DPE_VDD18#2 DPA_VDD18#2 AF11
D D

0.1U_0402_10V6K
10U_0603_6.3V6M
C327

C402

C64
1U_0402_6.3V4Z
VGA@ 1 1 1
+DPF_VDD10 PARK-S3 1.0V@110mA +VGA_PCIE
L25
+DPA_VDD10M93-S3 1.1V@200mA 1
2 2 2 0.12A AG20
AG21
DPE_VDD10#1 DPA_VDD10#1 AF6
AF7 VGA@ VGA@ VGA@ VGA@
2
DPE_VDD10#2 DPA_VDD10#2

0.1U_0402_10V6K
10U_0603_6.3V6M
C326

C400

C60
1U_0402_6.3V4Z
1 1 1 MBK1608121YZF_0603 +1.8VS_VGA
L85
AG14 AE1 2 1 +DPB_VDD18
DPE_VSSR#1 DPA_VSSR#1 BLM15BD121SN1D_0402 @ @ @
AH14 DPE_VSSR#2 DPA_VSSR#2 AE3
2 2 2

0.1U_0402_10V6K
10U_0603_6.3V6M
C956

C957

C958
1U_0402_6.3V4Z
AM14 AG1 @ 1 1 1
DPE_VSSR#3 DPA_VSSR#3
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5

+VGA_PCIE 2 2 2
+DPE_VDD18
130mA
L31
+DPB_VDD18
1 2 +DPF_VDD10
0.11A AF16
AG17
DPF_VDD18#1 DPB_VDD18#1 AE13
AF13
VGA@ VGA@ VGA@ VGA@ DPF_VDD18#2 DPB_VDD18#2 +VGA_PCIE

0.1U_0402_10V6K
1U_0402_6.3V4Z
PARK-S3 1.0V@110mA add at 8/11

10U_0603_6.3V6M
C401

C62

C328
MBK1608121YZF_0603 1 1 1 +DPF_VDD10 L28
+VPB_VDD10 M93-S3 1.1V@200mA
0.11A AF22
AG22
DPF_VDD10#1 DPB_VDD10#1 AF8
AF9 @ @
2 1
BLM15BD121SN1D_0402
DPF_VDD10#2 DPB_VDD10#2

0.1U_0402_10V6K
10U_0603_6.3V6M

1U_0402_6.3V4Z
1 1 1 @
2 2 2

C325

C404

C63
C C
AF23 AF10 @
DPF_VSSR#1 DPB_VSSR#1
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 AH8 2 2 2
DPF_VSSR#3 DPB_VSSR#3
AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8

+DPE_PVDD 2 R314 1 AF17 AE10 VGA@1 R313 2

+1.8VS_VGA 150_0402_1% DPEF_CALR DPAB_CALR 150_0402_1% +1.8VS_VGA
VGA@ VGA@
L26 L27
2 1 AG18 DP PLL POWER AG8 +DPA_PVDD
0.02A 2 1
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ DPE_PVDD DPA_PVDD M93@ M93@ BLM15BD121SN1D_0402
AF19 DPE_PVSS 20mA 20mA DPA_PVSS AG7
10U_0603_6.3V6M

10U_0603_6.3V6M
C403

C65

C331
0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 1 1 M93@

0.1U_0402_10V6K
C330

C405

C61
1 1 1
R844 0_0402_5% M93@
1 VGA@ 2 AG19 DPF_PVDD 20mA 20mA DPB_PVDD AG10
2 2 2
1 2 AF20 AG11
R845VGA@ 0_0402_5% DPF_PVSS DPB_PVSS 2 2 2

B M9X-S2/S3 + Park-S3 B
add at 8/11 PARK@ +1.8VS_VGA

+DPE_VDD18 +DPE_PVDD L29

+DPB_PVDD
0.02A 2 1
R846
@ @ @ BLM15BD121SN1D_0402

0.1U_0402_10V6K
10U_0603_6.3V6M
C329

C406

C59
1U_0402_6.3V4Z
1 @ 2 1 1 1 @
+DPB_PVDD 2 R996 1 M93@ +DPA_PVDD
+BBP 0_0402_5% 0_0402_5%
R131
2 2 2
1 VGA@ 2

0_0402_5% +1.8VS_VGA +VPB_VDD10 2 R847 1 VGA@ +DPA_VDD10

+VGA_CORE 0_0603_5%
Q37A Q7
3 AO3413_SOT23-3 +DPB_VDD18 2 R848 1 PARK@ +DPA_VDD18
D

1 6 1
@ @ 0_0603_5%

2N7002DW T/R7_SOT-363-6 +DPA_PVDD 2 R849 1 PARK@

G
2

0_0402_5%
1 R168 2 +5VS
@ +DPB_PVDD 2 R850 1 PARK@
3

100K_0402_5% 0_0402_5% add at 8/11

A Q37B A
2N7002DW T/R7_SOT-363-6
5 @
(15) GPIO21_BBEN
Security Classification Compal Secret Data Compal Electronics, Inc.
1

R289 Issued Date 2008/10/06 2009/10/06 Title

10K_0402_5% Deciphered Date
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 DPX Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 17 of 49
5 4 3 2 1
 5 4 3 2 1

VGA@ VGA@ VGA@ VGA@

C430

C411
+1.5VS

VGA@
2.2A
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
www.bufanxiu.com
C425

C419

C593

C410

C431

C592

C376

C374

C73

C74

C70

C66
1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.8VS_VGA
0.4A L93
U40D +PCIE_GDDR 1 2 U40E
+1.5VS VGA@ VGA@ VGA@ VGA@ VGA@ MBK1608221YZF_0603

C408

C434

C424

C409

C377
MEM I/O 1 1 1 1 1 VGA@

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
D D
PCIE
H13 AB23 AA27 A3
VGA@ VGA@ VGA@ VGA@ VDDR1#1 PCIE_VDDR#1 PCIE_VSS#1 GND#1
+VDDC_CT
H16
VDDR1#2 PCIE_VDDR#2
AC23
2 2 2 2 2 add at 8/11 AB24
PCIE_VSS#2 GND#2
A30

C381

C372

C371

C369
1 1 1 1 H19 AD24 AB32 AA13

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDR1#3 PCIE_VDDR#3 PCIE_VSS#3 GND#3 / EVDDQ#2
J10 AE24 AC24 AA16
L94 VDDR1#4 PCIE_VDDR#4 PCIE_VSS#4 GND#4
1 2
0.136A J23
J24
VDDR1#5 PCIE_VDDR#5
AE25
AE26
AC26
AC27
PCIE_VSS#5 GND#5
AB10
AB15
+1.8VS_VGA 2 2 2 2 VDDR1#6 PCIE_VDDR#6 PCIE_VSS#6 GND#6 / EVDDQ#3
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ VGA@ J9 AF25 AD25 AB6
VDDR1#7 PCIE_VDDR#7 PCIE_VSS#7 GND#7
C332

C418

C596

C67
VGA@ 1 1 1 1 K10 AG26 AD32 AC9
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDR1#8 PCIE_VDDR#8 +VGA_PCIE PCIE_VSS#8 GND#8
add at 8/11 K23
VDDR1#9 2A AE27
PCIE_VSS#9 GND#9
AD6
K24 AF32 AD8
VDDR1#10 +PCIE_VDDC PCIE_VSS#10 GND#10
K9 L23 AG27 AE7
2 2 2 2 VDDR1#11 PCIE_VDDC#1 VGA@ VGA@ VGA@ VGA@ VGA@ PCIE_VSS#11 GND#11
L11 L24 AH32 AG12
VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12

C423

C439

C433

C435

C378
L12 L25 1 1 1 1 1 K28 AH10

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDR1#13 PCIE_VDDC#3 PCIE_VSS#13 GND#13
L13 L26 K32 AH28
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#14 GND#14
L20 M22 L27 B10
VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
L21 N22 M32 B12
+3VS_VGA VDDR1#16 PCIE_VDDC#6 2 2 2 2 2 PCIE_VSS#16 GND#16
L22 N23 N25 B14
VDDR1#17 PCIE_VDDC#7 PCIE_VSS#17 GND#17
N24 N27 B16
PCIE_VDDC#8 PCIE_VSS#18 GND#18
0.06A PCIE_VDDC#9
R22
T22
P25
P32
PCIE_VSS#19 GND#19
B18
B20
+VDDC_CT LEVEL PCIE_VDDC#10 PCIE_VSS#20 GND#20
17mA TRANSLATION PCIE_VDDC#11
U22
+VGA_CORE
R27
PCIE_VSS#21 GND#21
B22
VGA@ VGA@ VGA@ VGA@ V22 T25 B24
PCIE_VDDC#12 PCIE_VSS#22 GND#22
C383

C413

C600

1 1 1 C414
1 AA20 9A(RMS)/14A(Peak) T32 B26
10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDD_CT#1 PCIE_VSS#23 GND#23
AA21 U25 B6
VDD_CT#2 PCIE_VSS#24 GND#24
AB20 AA15 U27 B8
VDD_CT#3 CORE VDDC#1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ PCIE_VSS#25 GND#25
AB21 N15 V32 C1
2 2 2 2 VDD_CT#4 VDDC#2 PCIE_VSS#26 GND#26

C590

C436

C417

C427

C438

C426

C597

C594

C432

C421
N17 1 1 1 1 1 1 1 1 1 1 W25 C32

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDC#3 PCIE_VSS#27 GND#27
M93-S3/M92-S2 VDDC#4
R13 W26
PCIE_VSS#28 GND#28
E28

POWER
R16 W27 F10
VDDC#5 PCIE_VSS#29 GND#29
AA17 R18 Y25 F12
VDDR3#1 VDDC#6 2 2 2 2 2 2 2 2 2 2 PCIE_VSS#30 GND#30
AA18
VDDR3#2 I/O VDDC#7
Y21 Y32
PCIE_VSS#31 GND#31
F14
AB17 T12 F16
VDDR3#3 VDDC#8 GND#32
AB18 T15 F18
VDDR3#4 VDDC#9 GND#33
T17 F2
VDDC#10 GND#34
+1.8VS_VGA V12 T20 F20
VGA@ VGA@ VGA@ VDDR4#1 / VDDR5 VDDC#11 +VGA_CORE GND#35
Y12 U13 M6 F22
VDDR4#2 VDDC#12 GND#56 GND#36
C U12 U16 N11 F24 C
0.1U_0402_10V6K
1U_0402_6.3V4Z

VDDR4#3 / VDDR5 VDDC#13 GND#57 GND#37

C370

C428

C72

1 1 1 U18 N12 F26

10U_0603_6.3V6M

+VDDR VDDC#14 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ GND#58 GND#38
AA11 V21 N13 F6
NC#1 / VDDR4 VDDC#15 GND#59 GND#39

C382

C380

C373

C379

C334

C598

C599

C429

C420

C412
Y11 V15 N16 F8
1 1 1 1 1 1 1 1 1 1
GND

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
DVCLK / VDDR4 VDDC#16 GND#60 GND#40
V17 N18 G10
2 2 2 VDDC#17 GND#61 GND#41
V11 V20 N21 G27
NC#3 / VDDR5 VDDC#18 GND#62 GND#42
U11 Y13 P6 G31
TESTEN#2 / VDDR5 VDDC#20 2 2 2 2 2 2 2 2 2 2 GND#63 GND#43
Y16 P9 G8
VDDC#21 GND#64 GND#44
Y18 R12 H14
1U_0402_6.3V4Z M93@ VDDC#22 GND#65 GND#45
R21 R15 H17
+1.5VS VDDC#23 /BIF_VDDC GND#66 GND#46
2 1C407 0.04A U21 R17 H2
L33 MEM CLK VDDC#19/BIF_VDDC GND#67 GND#47
R20 H20
+VDDRHA GND#68 GND#48
1 2 L17 T13 H6
BLM15BD121SN1D_0402 VDDRHA GND#69 GND#49
T16 J27
M93@ R971 ISOLATED GND#70 GND#50
0_0402_5%
L16
VSSRHA CORE I/O 2A(RMS)/3A(Peak) T18
T21
GND#71 GND#51
J31
K11
+1.8VS_VGA +VDDCI GND#72 GND#52
M93@ M13 +VGA_CORE T6 K2
L32 PLL VDDCI#1 VGA@ VGA@ VGA@ VGA@ GND#73 GND#53
40mA VDDCI#2
M15 U15
GND#74 GND#54
K22

C591

C437

C595

C375
1 2 +PCIE_PVDD AM30 M16 1 1 1 1 U17 K6

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@ PCIE_PVDD VDDCI#3 GND#75 GND#55
M17 U20 T11
VDDCI#4 GND#76 GND#85
C335

C415

C71

VGA@ 1 1 1 75mA M18 U9 R11

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

+MPV18 VDDCI#5 GND#77 GND#86

L8 M20 V13
MPV18 VDDCI#6 2 2 2 2 GND#78
M21 V16
VDDCI#7 GND#79
2 2 2 50mA VDDCI#8
N20 V18
GND#80
+SPV18 H7 Y10
SPV18 GND#81
+VGA_PCIE
100mA Y15
GND#82
+SPV10 H8 Y17 A32
+VGA_CORE SPV10 GND#83 VSS_MECH#1
Y20 AM1
GND#84 VSS_MECH#2
J7 AM32
PARK@ L38 SPVSS VSS_MECH#3
1 2
BLM15BD121SN1D_0402 VGA@ VGA@ VGA@
C333

C422

C69

L86 1 1 1 BACK BIAS

10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K

1 2 M11
BLM15BD121SN1D_0402 BBP#1 M9X-S2/S3 + Park-S3
+BBP M12
M93@ VGA@ VGA@ BBP#2
2 2 2
C416

C68

1 1 120mA PARK@
0.1U_0402_10V6K
1U_0402_6.3V4Z

B add at 8/11 B
M9X-S2/S3 + Park-S3
PARK@
2 2

+3VS_VGA +3VS

Q8
+1.8VS_VGA 3 AO3413_SOT23-3

S
1
PARK@ L87 VGA@
1 2 +MPV18

2
BLM15BD121SN1D_0402 PARK@ PARK@

G
2
C959

C960

1 1 R211
0.1U_0402_10V6K
1U_0402_6.3V4Z

100K_0402_5%
VGA@
R132

1
2 2 1 2
VGA@
R923 0_0402_5%
VLDT_EN# 1 2
(38) VLDT_EN#
@

1
0_0402_5% D
PARK@ L88 SUSP# 1 2 3VS_VGA_EN 2 Q36
(31,33,38,41,44,46) SUSP#
1 2 +SPV18 VGA@ G VGA@
BLM15BD121SN1D_0402 PARK@ PARK@ R339 174K_0402_1% S 2N7002_SOT23

3
C961

C962

1 1
1U_0402_6.3V4Z

0.1U_0402_10V6K

C52
1 2
0.1U_0402_25V5K
2 2

A A

PARK@ L95
1 2 +VDDR
BLM15BD121SN1D_0402 PARK@ PARK@
C996

C997

1 1
0.1U_0402_10V6K
1U_0402_6.3V4Z

2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

add at 8/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 18 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com
M_DA[0..63]
(16) M_DA[63..0]
M_MA[13..0]
(16) M_MA[13..0]
M_DQM[7..0]
(16) M_DQM[7..0]
M_DQS[7..0]
(16) M_DQS[7..0]
M_DQS#[7..0]
(16) M_DQS#[7..0]

U21 U22 U23 U24

VREFC_A1 M9 E4 M_DA16 VREFC_A2 M9 E4 M_DA25 VREFC_A3 M9 E4 M_DA38 VREFC_A4 M9 E4 M_DA54

VREFD_Q1 VREFCA DQL0 M_DA23 VREFD_Q2 VREFCA DQL0 M_DA27 VREFD_Q3 VREFCA DQL0 M_DA34 VREFD_Q4 VREFCA DQL0 M_DA52
H2 F8 H2 F8 H2 F8 H2 F8
D VREFDQ DQL1 M_DA19 VREFDQ DQL1 M_DA24 VREFDQ DQL1 M_DA33 VREFDQ DQL1 M_DA53 D
F3 F3 F3 F3
M_MA0 DQL2 M_DA21 M_MA0 DQL2 M_DA31 M_MA0 DQL2 M_DA37 M_MA0 DQL2 M_DA49
N4 F9 N4 F9 N4 F9 N4 F9
M_MA1 A0 DQL3 M_DA17 M_MA1 A0 DQL3 M_DA26 M_MA1 A0 DQL3 M_DA35 M_MA1 A0 DQL3 M_DA51
P8 H4 P8 H4 P8 H4 P8 H4
M_MA2 A1 DQL4 M_DA18 M_MA2 A1 DQL4 M_DA30 M_MA2 A1 DQL4 M_DA39 M_MA2 A1 DQL4 M_DA50
P4 H9 P4 H9 P4 H9 P4 H9
M_MA3 A2 DQL5 M_DA22 M_MA3 A2 DQL5 M_DA28 M_MA3 A2 DQL5 M_DA32 M_MA3 A2 DQL5 M_DA55
N3 G3 N3 G3 N3 G3 N3 G3
M_MA4 A3 DQL6 M_DA20 M_MA4 A3 DQL6 M_DA29 M_MA4 A3 DQL6 M_DA36 M_MA4 A3 DQL6 M_DA48
P9 H8 P9 H8 P9 H8 P9 H8
M_MA5 A4 DQL7 M_MA5 A4 DQL7 M_MA5 A4 DQL7 M_MA5 A4 DQL7
P3 P3 P3 P3
M_MA6 A5 M_MA6 A5 M_MA6 A5 M_MA6 A5
R9 R9 R9 R9
M_MA7 A6 M_DA0 M_MA7 A6 M_DA14 M_MA7 A6 M_DA44 M_MA7 A6 M_DA57
R3 D8 R3 D8 R3 D8 R3 D8
M_MA8 A7 DQU0 M_DA4 M_MA8 A7 DQU0 M_DA10 M_MA8 A7 DQU0 M_DA42 M_MA8 A7 DQU0 M_DA58
T9 C4 T9 C4 T9 C4 T9 C4
M_MA9 A8 DQU1 M_DA1 M_MA9 A8 DQU1 M_DA15 M_MA9 A8 DQU1 M_DA47 M_MA9 A8 DQU1 M_DA60
R4 C9 R4 C9 R4 C9 R4 C9
ZZZ2 X76-S M_MA10 A9 DQU2 M_DA6 M_MA10 A9 DQU2 M_DA11 M_MA10 A9 DQU2 M_DA40 M_MA10 A9 DQU2 M_DA61
L8 C3 L8 C3 L8 C3 L8 C3
M_MA11 A10/AP DQU3 M_DA3 M_MA11 A10/AP DQU3 M_DA12 M_MA11 A10/AP DQU3 M_DA45 M_MA11 A10/AP DQU3 M_DA63
R8 A8 R8 A8 R8 A8 R8 A8
M_MA12 A11 DQU4 M_DA7 M_MA12 A11 DQU4 M_DA8 M_MA12 A11 DQU4 M_DA43 M_MA12 A11 DQU4 M_DA62
N8 A3 N8 A3 N8 A3 N8 A3
M_MA13 A12 DQU5 M_DA2 M_MA13 A12 DQU5 M_DA13 M_MA13 A12 DQU5 M_DA46 M_MA13 A12 DQU5 M_DA56
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 M_DA5 A13 DQU6 M_DA9 A13 DQU6 M_DA41 A13 DQU6 M_DA59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5VS A15/BA3 +1.5VS A15/BA3 +1.5VS A15/BA3 +1.5VS
Hynix Samsung
X76H@ X76S@
M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3
(16) M_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10
(16) M_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
U21 U22 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8
(16) M_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
K9 K9 K9 K9
VDD VDD VDD VDD
N2 N2 N2 N2
M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
(16) M_CLK0 J8 N10 J8 N10 (16) M_CLK1 J8 N10 J8 N10
M_CLK#0 K8 CK VDD M_CLK#0 CK VDD M_CLK#1 K8 CK VDD M_CLK#1 CK VDD
(16) M_CLK#0 R2 K8 R2 (16) M_CLK#1 R2 K8 R2
M_CKE0 K10 CK VDD M_CKE0 CK VDD M_CKE1 K10 CK VDD M_CKE1 CK VDD
SAMSUNG VRAM SAMSUNG VRAM (16) M_CKE0 CKE/CKE0 VDD
R10 K10
CKE/CKE0 VDD
R10 (16) M_CKE1 CKE/CKE0 VDD
R10 K10
CKE/CKE0 VDD
R10
S@ S@ +1.5VS +1.5VS +1.5VS +1.5VS

M_ODT0 K2 A2 M_ODT0 K2 A2 M_ODT1 K2 A2 M_ODT1 K2 A2

(16) M_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ (16) M_ODT1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
U23 U24 M_CS#0 L3 A9 M_CS#0 L3 A9 M_CS#1 L3 A9 M_CS#1 L3 A9
(16) M_CS#0 CS VDDQ CS VDDQ (16) M_CS#1 CS VDDQ CS VDDQ
M_RAS#0 J4 C2 M_RAS#0 J4 C2 M_RAS#1 J4 C2 M_RAS#1 J4 C2
(16) M_RAS#0 RAS VDDQ RAS VDDQ (16) M_RAS#1 RAS VDDQ RAS VDDQ
M_CAS#0 K4 C10 M_CAS#0 K4 C10 M_CAS#1 K4 C10 M_CAS#1 K4 C10
(16) M_CAS#0 CAS VDDQ CAS VDDQ (16) M_CAS#1 CAS VDDQ CAS VDDQ
M_WE#0 L4 D3 M_WE#0 L4 D3 M_WE#1 L4 D3 M_WE#1 L4 D3
(16) M_WE#0 WE VDDQ WE VDDQ (16) M_WE#1 WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
M_DQS2 VDDQ M_DQS3 VDDQ M_DQS4 VDDQ M_DQS6 VDDQ
C SAMSUNG VRAM SAMSUNG VRAM F4
DQSL VDDQ
H3 F4
DQSL VDDQ
H3 F4
DQSL VDDQ
H3 F4
DQSL VDDQ
H3 C
S@ S@ M_DQS0 C8 H10 M_DQS1 C8 H10 M_DQS5 C8 H10 M_DQS7 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

M_DQM2 E8 A10 M_DQM3 E8 A10 M_DQM4 E8 A10 M_DQM6 E8 A10

M_DQM0 DML VSS M_DQM1 DML VSS M_DQM5 DML VSS M_DQM7 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
DMU VSS DMU VSS DMU VSS DMU VSS
E2 E2 E2 E2
VSS VSS VSS VSS
G9 G9 G9 G9
M_DQS#2 VSS M_DQS#3 VSS M_DQS#4 VSS M_DQS#6 VSS
G4 J3 G4 J3 G4 J3 G4 J3
M_DQS#0 DQSL VSS M_DQS#1 DQSL VSS M_DQS#5 DQSL VSS M_DQS#7 DQSL VSS
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS
(16) DRAM_RST# T3 P10 P10 P10 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 B2 J2 B2 J2 B2 J2 B2
R329 NC/ODT1 VSSQ R326 NC/ODT1 VSSQ R328 NC/ODT1 VSSQ R327 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2
VGA@ NC/CE1 VSSQ VGA@ NC/CE1 VSSQ VGA@ NC/CE1 VSSQ VGA@ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA
H@ H@ H@ H@

B B
+1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS
1

1
R356 R355 R345 R351 R354 R350 R352 R359
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@ VGA@
2

2
VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1

1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C80

C78

C82

C79

C76

C81

C75

C77
1 1 1 1 1 1 1 1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R346 R347 R348 R349 R358 R353 R357 R344
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@
2 2 2 2 2 VGA@ 2 VGA@ 2 VGA@ 2
2

2
+1.5VS
+1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VS 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1 1 1 1 1 1

C684

C675

C685

C608

C680

C679

C603

C677

C605

C678
1 1 1 1 1 1 1 1 1 1
C604

C682

C601

C676

C606

C120

C681

C686

C607

C602
M_CLK0 1 2 C386 C387 C389 C385 C388 C384
R576 VGA@ 56_0402_1% M_CLK1 1 2
R574 VGA@ 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
M_CLK#01 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R489 VGA@ 56_0402_1% M_CLK#11 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 R575 VGA@ 56_0402_1% 1
A C53 C54 A
0.01U_0402_16V7K 0.01U_0402_16V7K
VGA@ VGA@
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 DDR3 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 19 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com
+3VS_CLK
L68
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 C483 C476 C480 C526 C479 C498 C511 C477 C474 remove C508 & C528 at 8/12
+1.2V_HT +VDDCLK_IO 10U_0805_6.3V4Z 1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L66
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1U CLOSE PIN 69
FBMA-L11-201209-221LMA30T_0805 C909 C471 C475 C516 C530 C529
D D
2 2 2 2 2 2
remove C527 at 8/12
10U_0805_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

L67
1 2 +3VS_CLKVDDA
+3VS
FBMA-L11-201209-221LMA30T_0805
1 1 U5
C463 100mA
CLK_XTAL_OUT 10U_0805_6.3V4Z C473
0.1U_0402_16V4Z ICS 9LPRS488
CLK_XTAL_IN 2 2 49 1 SB_SMBCLK
VDDA SMBCLK SB_SMBDATA SB_SMBCLK (8,9,24,31)
48 GNDA SMBDAT 2
SB_SMBDATA (8,9,24,31)
100mA
62 41 SRC_SLOW
+3VS_CLK VDDREF SB_SRC_SLOW#
Y1 66 GNDREF
2 1
2 1 C500 0.1U_0402_16V4Z
+VDDCLK_IO 12 VDDSRC_IO CPUKG0T_LPRS 56 CLK_CPU_BCLK (6)
14.31818MHZ_20P_6X14300202 18 55 CPU
VDDSRC_IO CPUKG0C_LPRS CLK_CPU_BCLK# (6)
1 1 100mA 28
VDDATIG_IO
C518 C517 37 VDDSB_SRC_IO R953 1
53 VDDCPU_IO HTT0T_LPRS / 66 M 60 2 0_0402_5% CLK_NBHT (11)
27P_0402_50V8J 27P_0402_50V8J 59 R954 1 2 0_0402_5%
2 2 +3VS_CLK HTT0C_LPRS / 66 M CLK_NBHT# (11)
C
100mA C
+3VS_CLK 3 VDDDOT
17 40
VDDSRC SB_SRC0T_LPRS
Routing the trace at least 10mil 29
VDDATIG SB_SRC0C_LPRS
39
R175 8.2K_0402_5%

R176 8.2K_0402_5%

38 VDDSB_SRC
44 VDDSATA
2

54 35
L70 VDDCPU SB_SRC1T_LPRS +3VS_CLK
61 VDDHTT SB_SRC1C_LPRS 34
1 2 69
VDD48

1
FBMA-L11-160808-601LMT 0603 33 R955 1 2 0_0402_5% CLK_NBGFX (11)
1

ATIG0T_LPRS R956 1
ATIG0C_LPRS 32 2 0_0402_5% CLK_NBGFX# (11) NB GFX R178
@ 8.2K_0402_5%
24 CLKREQ0 #
31 R957 1 VGA@ 2 0_0402_5%
CLK_PCIE_VGA (14)

2
ATIG1T_LPRS R958 1
NEW CARD (31) EXP_CLKREQ# 51 30 2 0_0402_5% CLK_PCIE_VGA# (14) VGA
CLKREQ1# ATIG1C_LPRS SRC_SLOW
VGA@
Mini Card1 (31) MINI1_CLKREQ# 50
CLKREQ2#
26
ATIG2T_LPRS

1
43 25
CLKREQ3# ATIG2C_LPRS R177
42 @ 8.2K_0402_5%
CLKREQ4# R959 1
23 2 0_0402_5% CLK_PCIE_LAN (30)
SRC0T_LPRS R960 1
22 2 0_0402_5% CLK_PCIE_LAN# (30) LAN

2
SRC0C_LPRS
CLK_NB_14.318M For Tigris 27M_SEL 63 21 R961 1 @ 2 0_0402_5%
REF2/SEL_27 SRC1T_LPRS CLK_PCIE_EXP (31)
RS780 1.1V 158R/90.0R 20 R962 1 2 0_0402_5%
SRC1C_LPRS CLK_PCIE_EXP# (31)
2 1 SEL_SATA 64 @
(23) SB710_CLK_14M R185 33_0402_5% REF1/SEL_SATA
1 2 CLK_14.318M 65 16 R963 1 2 0_0402_5%
(11) CLK_NB_14.318M REF0/SEL_HTT66 SRC2T_LPRS CLK_PCIE_MINI1 (31)
R201 158_0402_1% 15 R964 1 2 0_0402_5% MiniCard_1
SRC2C_LPRS CLK_PCIE_MINI1# (31)
B
1 2 NB CLOCK INPUT TABLE B
R187 90.9_0402_1%
(29) CLK_48M_CR 1 2 CLK_48MHZ 71 48MHz_0 SRC3T_LPRS 14 NB CLOCKS RS740 RX780 RS780
R676 47_0402_5% 13
SRC3C_LPRS
1 2 CLK_48M 70 48MHz_1
HT_REFCLKP
(24) CLK_48M_USB R209 47_0402_5% 66M SE(SINGLE END) 100M DIFF 100M DIFF
10 R965 1 2 0_0402_5% HT_REFCLKN NC 100M DIFF 100M DIFF
SRC4T_LPRS CLK_SBLINK_BCLK (11)
9 R966 1 2 0_0402_5% NB A LINK
CLK_XTAL_IN SRC4C_LPRS CLK_SBLINK_BCLK# (11)
67 REFCLK_P
X1 14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
CLK_XTAL_OUT 68 8 REFCLK_N NC NC vref
X2 SRC5T_LPRS
SRC5C_LPRS 7
+3VS_CLK GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)*

6 46 R967 1 2 0_0402_5% GPP_REFCLK NC 100M DIFF NC

GNDDOT SRC6T/SATAT_LPRS CLK_SBSRC_BCLK (23)
11 45 R968 1 2 0_0402_5% SB RCLK
GNDSRC SRC6C/SATAC_LPRS CLK_SBSRC_BCLK# (23)
19 GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF
GNDSRC
27
GNDATIG
2

36 5 CLK_SRC7T R210 1 @ 2 0_0402_5% VGA (Spread spectrum)

GNDSB_SRC SRC7T_LPRS/27MHz_SS CLK_SRC7C 27M_SSC (15)
R200 R198 47 4 R461 1 2 0_0402_5%
GNDSATA SRC7C_LPRS/27MHz_NS 27M_CLK (15)
8.2K_0402_5% 8.2K_0402_5% 52 @ VGA (Non spread spectrum)
@ GNDCPU
58
GNDHTT
72
1

GND48
73 57 2 1 +3VS_CLK
SEL_SATA GNDPAD PD# R573 8.2K_0402_5%
R986 1 2 0_0402_5%
27M_SEL @
2

SLG8SP626VTR_QFN72_10x10
2

R186
8.2K_0402_5% R979
8.2K_0402_5% 1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN
@
1

2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN

1

A A

1 single-ended 66MHz HTT output

SEL_HTT66 Security Classification Compal Secret Data Compal Electronics, Inc.
0* differential 100MHz HTT output Issued Date 2008/10/06 2009/10/06 Title
Deciphered Date
1 NON SPREAD 100M SATA SRC6 output 1 * NON SPREAD 27M and SPREAD 27M output
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
SEL_SATA 27M_SEL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0* SPREAD 100M SATA SRC6 output 0 differential spread SRC_7 output Custom 1.0
* default
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 20 of 49
5 4 3 2 1
 5 4 3 2 1

+UMA_LCDVDD
LCD POWER CIRCUIT www.bufanxiu.com +DIS_LCDVDD

+3VALW +3VS +3VALW +3VS

W=60mils W=60mils
R254 R702

1
150_0603_1% 1 150_0603_1% 1
UMA@ R252 C579 VGA@ R698 C163
100K_0402_5% UMA@ 100K_0402_5% VGA@
D UMA@ 4.7U_0805_10V4Z VGA@ 4.7U_0805_10V4Z D
2 2

2
1

3
D R253
S D R701
S
AO3413_SOT23-3 AO3413_SOT23-3
G G
Q63 2 1 2 2 Q64 2 1 2 2
2N7002_SOT23 G Q33 2N7002_SOT23 G Q34
UMA@S 62K_0402_5% 2
D UMA@ VGA@ S 62K_0402_5% 2
D VGA@

1
1

1
UMA@ +UMA_LCDVDD VGA@ +DIS_LCDVDD
C578 W=60mils C160 W=60mils

OUT

OUT
UMA@ 0.1U_0402_16V4Z VGA@ 0.1U_0402_16V4Z
R512 0_0402_5% 1 R695 0_0402_5% 1
UMA@ VGA@
(11) UMA_ENVDD_R 1 2 2 (14) VGA_ENVDD 1 2 2
IN Q65 IN Q66

GND

GND
1

1
DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
UMA@ VGA@

3
R508 R699
2.7K_0402_5% 10K_0402_5%
2

2
UMA@ @

+3VS
+3VS
C C
1

1
R255
10K_0402_5% R691
D24 UMA@ 10K_0402_5%
RB751V_SOD323 D13 VGA@
2

RB751V_SOD323

2
BKOFF# 1 2 UMA_DISPOFF#
(33) BKOFF# VGA_DISPOFF#
(33) BKOFF# 1 2
UMA@
VGA@
1

1
R256
10K_0402_5% R690
UMA@ 10K_0402_5%
VGA@
2

BKOFF# 1 2

2
C1026 @ 220P_0402_50V7K
1 2
DAC_BRIG C1027 @ 220P_0402_50V7K
1 2
C587 220P_0402_50V7K
PANEL_PWM 1 2
C586 220P_0402_50V7K R1001 1 20_0402_5%
CLOSE TO JLVDS2
R1002 1 20_0402_5%
CLOSE TO JLVDS1 UMA_DISPOFF# 1 2 @
@ C588 UMA@ 220P_0402_50V7K
VGA_DISPOFF# 1 2 +3VS
+3VS C1023 VGA@ 220P_0402_50V7K
(60 MIL)
+DIS_LEDVDD

5
U50
5

B U49 B
2

P
(33) PANEL_PWM B
2 4 VGA_PWM FBMA-L11-201209-221LMA30T_0805
P

(33) PANEL_PWM B UMA_PWM Y

4 (14,33) VGA_VARIBL 1 B+ 2 1
Y A

G
1 NC7SZ08P5X_NL_SC70-5 L41 1
(11,33) UMA_VARIBL A
G

NC7SZ08P5X_NL_SC70-5 @ VGA@ C166

3
@
3

4.7U_0805_25V6-K VGA@
R999 1 20_0402_5% 2
R1000 1
UMA@
20_0402_5% LCD/PANEL BD. Conn. VGA@

700mA JLVDS1 700mA 700mA JLVDS2 700mA

FBMA-L11-201209-221LMA30T_0805 2 1 +UMA_LEDVDD FBMA-L11-201209-221LMA30T_0805 2 1 +DIS_LEDVDD
L16 1 +LCDVDD_L 2 1 L42 1 2 1
2 4 3 +DIS_LCDVDD 2 4 3
UMA@ 4 3 VGA@ 4 3
(60 MIL) 6 6 5 5 (60 MIL) 6 6 5 5
+UMA_LCDVDD 8 7 +3VS 8 7 +3VS
8 7 DAC_BRIG 8 7 DAC_BRIG
1 1 +3VS 10 9 DAC_BRIG (33) 1 1 +3VS 10 9 DAC_BRIG (33)
C114 C46 10 9 UMA_PWM C164 C162 10 9 VGA_PWM
12 11 12 11
UMA@ 12 11 UMA_DISPOFF# VGA@ VGA@ 12 11 VGA_DISPOFF#
14 13 14 13
4.7U_0805_10V4Z 0.1U_0402_25V6 GMCH_TXCLK- 14 13 4.7U_0805_10V4Z 0.1U_0402_25V6 VGA_TXCLK- 14 13
(11) GMCH_TXCLK- 16 15 (14) VGA_TXCLK- 16 15
2 2 GMCH_TXCLK+ 16 15 2 2 VGA_TXCLK+ 16 15
(11) GMCH_TXCLK+ 18 17 (14) VGA_TXCLK+ 18 17
GMCH_TXOUT0- 18 17 VGA_TXOUT0- 18 17
(11) GMCH_TXOUT0- 20 20 19 19 (14) VGA_TXOUT0- 20 20 19 19
GMCH_TXOUT0+ 22 21 (14) VGA_TXOUT0+ VGA_TXOUT0+ 22 21
(11) GMCH_TXOUT0+ GMCH_TXOUT1- 22 21 VGA_TXOUT1- 22 21
(11) GMCH_TXOUT1- 24 24 23 23 (14) VGA_TXOUT1- 24 24 23 23
GMCH_TXOUT1+ 26 25 (14) VGA_TXOUT1+ VGA_TXOUT1+ 26 25
(11) GMCH_TXOUT1+ 26 25 26 25
GMCH_TXOUT2- 28 27 GMCH_LCD_DATA GMCH_LCD_DATA (11) VGA_TXOUT2- 28 27 VGA_LCD_DATA VGA_LCD_DATA (15)
(11) GMCH_TXOUT2- 28 27 (14) VGA_TXOUT2- 28 27
GMCH_TXOUT2+ 30 29 GMCH_LCD_CLK VGA_TXOUT2+ 30 29 VGA_LCD_CLK
(11) GMCH_TXOUT2+ 30 29 GMCH_LCD_CLK (11) (14) VGA_TXOUT2+ 30 29 VGA_LCD_CLK (15)
32 31 32 31
GNDGND GNDGND
ACES_87142-3041-BS ACES_87142-3041-BS
ME@ ME@
A A
280mA (60 MIL) +UMA_LEDVDD

FBMA-L11-201209-221LMA30T_0805
B+ 2 1
L17 1
UMA@ C858
400mA Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_25V6-K UMA@ Issued Date 2008/10/06 2009/10/06 Title
2 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 21 of 49
5 4 3 2 1
 A B C D E

www.bufanxiu.com
CRT CONNECTOR
+5VS +R_CRT_VCC +CRT_VCC
W=40mils
D28 D27 D26
DAN217_SC59 DAN217_SC59 DAN217_SC59 D25 F1
@ @ @ 2 1 1 2

1
1
RB491D_SC59-31.1A_6VDC_FUSE
C622
1 +5VS 0.1U_0402_16V4Z 1
2

3
JCRT1
6
L57 FCM2012C-800_0805 11
2 UMA@ 1 CRT_R 1 2 CRT_R_1 1
(11) GMCH_CRT_R
R439 0_0402_5% 7
L54 FCM2012C-800_0805 DDCDATA 12
2 UMA@ 1 CRT_G 1 2 CRT_G_1 2
(11) GMCH_CRT_G
R277 0_0402_5% 8
L52 FCM2012C-800_0805 HSYNC 13
2 UMA@ 1 CRT_B 1 2 CRT_B_1 3
(11) GMCH_CRT_B
R274 0_0402_5% +CRT_VCC 9

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
VSYNC 14 16
G

140_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 4 G 17

1
R285 R276 R273 C633 C640 C662 10
DVT C948 C660 C639 DDCCLK 15
(15) VGA_CRT_R 2 VGA@ 1 5
R493 0_0402_5% 2 2 2 2 2 2
UMA@ ALLTO_C10534-91507-L

2
(15) VGA_CRT_G 2 VGA@ 1 ME@
R495 0_0402_5%

(15) VGA_CRT_B 2 VGA@ 1

R494 0_0402_5%

R285

2 2

150_0402_1%
VGA@

Place closed to chipset

+3VS_VGA

2
R938
0_0402_5%
+CRT_VCC
VGA@

1
DVT

1
+CRT_VCC
R775
R54 R46 R55 R48
1 2 1 2 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5%
C351 VGA@ VGA@
5
1

3 0.1U_0402_16V4Z 1K_0402_5% 3

2
2
L50 FCM1608C-121T_0603
OE#
P

1 UMA@ 2 2 4 HSYNC_L 1 2 HSYNC

(11,13) GMCH_CRT_HSYNC A Y DDCDATA DDCDATA_R
R491 0_0402_5% 2 R57 1 6 1 2 R939 1
G

U25 VGA@ VGA_CRT_DATA (15)

(15) VGA_CRT_HSYNC 1 VGA@ 2 SN74AHCT1G125GW_SOT353-5 33_0402_5% Q57A 0_0402_5%
3

5
R490 0_0402_5% 2N7002DW-T/R7_SOT363-6
VGA@
1 2 DDCCLK 2 R44 1 DDCCLK_R 3 4 2 R940 1
C628 VGA_CRT_CLK (15)
5
1

0.1U_0402_16V4Z 33_0402_5% Q57B 0_0402_5%

L51 FCM1608C-121T_0603 2N7002DW-T/R7_SOT363-6 VGA@
OE#
P

1 UMA@ 2 2 4 VSYNC_L 1 2 VSYNC VGA@

(11,13) GMCH_CRT_VSYNC A Y
R513 0_0402_5%
G

U27
(15) VGA_CRT_VSYNC 1 VGA@ 2 SN74AHCT1G125GW_SOT353-5
3

R492 0_0402_5%

2 R941 1
UMA@ GMCH_CRT_DATA (11)
0_0402_5%

2 R942 1
0_0402_5% GMCH_CRT_CLK (11)
UMA@
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 22 of 49
A B C D E
 A B C D E

www.bufanxiu.com
U30A

A_RST# N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1
P3
C468 1 2 0.1U_0402_10V7K SB_RX0P_C V23 P1

PCI CLKS
1 (10) SB_RX0P SB_RX0N_C PCIE_TX0P PCICLK2 PCI_CLK2 (27) 1
C465 1 2 0.1U_0402_10V7K V22 P2
(10) SB_RX0N SB_RX1P_C PCIE_TX0N PCICLK3 PCI_CLK3 (27)
C459 1 2 0.1U_0402_10V7K V24 T4
(10) SB_RX1P SB_RX1N_C PCIE_TX1P PCICLK4 PCI_CLK4 (27)
C354 1 2 0.1U_0402_10V7K V25 T3
(10) SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 (27)
C355 1 2 0.1U_0402_10V7K SB_RX2P_C U25
(10) SB_RX2P SB_RX2N_C PCIE_TX2P
C353 1 2 0.1U_0402_10V7K U24
(10) SB_RX2N PCIE_TX2N
C460 1 2 0.1U_0402_10V7K SB_RX3P_C T23
(10) SB_RX3P SB_RX3N_C PCIE_TX3P
C464 1 2 0.1U_0402_10V7K T22 N1
(10) SB_RX3N PCIE_TX3N PCIRST# PAD T68
(10) SB_TX0P U22

PCI EXPRESS INTERFACE

PCIE_RX0P
(10) SB_TX0N U21 U2
PCIE_RX0N AD0
(10) SB_TX1P U19 PCIE_RX1P AD1 P7
(10) SB_TX1N V19 V4
PCIE_RX1N AD2
(10) SB_TX2P R20 PCIE_RX2P AD3 T1
(10) SB_TX2N R21 V3
PCIE_RX2N AD4
(10) SB_TX3P R18 U1
PCIE_RX3P AD5
(10) SB_TX3N R17 V1
PCIE_RX3N AD6
AD7 V2
R572 2 1 562_0402_1% T25 T2
PCIE_CALRP AD8
PCIE_CALRP=W/S=4/8(55ohm impedance), <1" +PCIE_VDDR R173 2 1 2.05K_0402_1% T24
PCIE_CALRN AD9 W1
L78 PCIE_PVDD=43mA +SB_PCIEVDD T9
AD10
PCIE_CALRN=W/S=4/8(55ohm impedance), <1" +1.2V_HT 2 1 P24
PCIE_PVDD AD11
R6
FBMA-L11-160808-221LMT_0603
1 1 R7
AD12
P25 PCIE_PVSS AD13 R5
C757 C762 U8
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z AD14
U5
2 2 AD15
AD16 Y7
+3VALW W8
C798 AD17
V9
AD18
2 1 AD19 Y8
AD20 AA8
5

0.1U_0402_16V4Z U29 Y4
AD21
2 Y3
P

2 B PLT_RST# AD22 PCI_AD23 2

Y 4 PLT_RST# (11,13,14,30,31,33) AD23 Y2 PCI_AD23 (27)
A_RST# 1 AA2 PCI_AD24 PCI_AD24 (27)
A AD24
G

NC7SZ08P5X_NL_SC70-5 AB4 PCI_AD25

AD25 PCI_AD25 (27)
2

N25 AA1 PCI_AD26 PCI_AD26 (27)

(20) CLK_SBSRC_BCLK
3

R426 PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD27

(20) CLK_SBSRC_BCLK# N24 PCIE_RCLKN/NB_LNK_CLKN AD27 AB3 PCI_AD27 (27)
8.2K_0402_5% AB2 PCI_AD28
AD28 PCI_AD28 (27)
@ K23 NB_DISP_CLKP AD29 AC1 PAD T10
K22 AC2 PAD T9
1

NB_DISP_CLKN AD30
1 2 AD31 AD1
R980@ 0_0603_5% M24 W2
NB_HT_CLKP CBE0#

PCI INTERFACE
M25 NB_HT_CLKN CBE1# U7
AA7
CBE2#
P17 CPU_HT_CLKP CBE3# Y1
M18 AA6
CPU_HT_CLKN FRAME#
W5
DEVSEL#
M23 AA5
SLT_GFX_CLKP IRDY#
M22 Y5
SLT_GFX_CLKN TRDY#
U6
PAR
J19 W6
GPP_CLK0P STOP#
J18 GPP_CLK0N PERR# W4
V7
SERR#
L20 AC3
GPP_CLK1P REQ0#
L19 AD4
GPP_CLK1N REQ1#
AB7
REQ2#
M19 AE6 PAD T12
GPP_CLK2P REQ3#/GPIO70
M20 AB6 PAD T11
C853 @ 100P_0402_50V8J @ GPP_CLK2N REQ4#/GPIO71
GNT0# AD2

CLOCK GENERATOR
2 1 2 1 N22 AE4
R470 100_0402_5% GPP_CLK3P GNT1#
P22 AD5
GPP_CLK3N GNT2#
AC6
GNT3#/GPIO72
(20) SB710_CLK_14M L18 AE5
25M_48M_66M_OSC GNT4#/GPIO73
AD6
3 CLKRUN# 3
For Tigris LOCK# V5
J21 25M_X1
Close to SB INTE#/GPIO33
AD3
INTF#/GPIO34 AC4
AE2
@ R380 20M_0402_5% INTG#/GPIO35
J20 AE3
25M_X2 INTH#/GPIO36
1 2 1 2 CLK_PCI_DB (31)
R973 @ 22_0402_5%
G22 CLK_LPC_EC 1 2 CLK_PCI_EC
C779 LPCCLK0 CLK_PCI_EC (27,33)
E22 R551 0_0402_5% LPCCLK1 (27) STRAP PIN
SB_32KHI SB_32KHI LPCCLK1
1 2 A3 X1 LAD0 H24 LPC_AD0 (31,33)
H23 LPC_AD1 (31,33)
15P_0402_50V8J Y4 LAD1
LAD2 J25 LPC_AD2 (31,33)
1

4 3 J24 LPC_AD3 (31,33)

RTC XTAL

OUT NC LAD3
LPC

R382 SB_32KHO B3 H25

X2 LFRAME# LPC_FRAME# (31,33)
20M_0603_5% 1 2 H22
IN NC LDRQ0#
AB8
32.768KHZ_12.5P_1TJS125BJ4A421P LDRQ1#/GNT5#/GPIO68
C787 AD7
2

BMREQ#/REQ5#/GPIO65
V15 SERIRQ (33)
SB_32KHO SERIRQ
1 2
(11) ALLOW_LDTSTOP F23
12P_0402_50V8J H_PROCHOT_R# ALLOW_LDTSTP
(6,33) H_PROCHOT_R# F24 PROCHOT# RTCCLK C3
@
RTC_CLK (27) STRAP PIN
(6) H_PWRGD F22 C2 1 2 +RTCBATT
LDT_PG INTRUDER_ALERT# R403 1M_0402_5%
G25 B2
CPU

(6,11) LDT_STOP# LDT_STP# VBAT

(6) LDT_RST# G24
LDT_RST# +RTCBATT
RTC

1 2
218S7EALA11FG_BGA528_SB700 R400 510_0402_5%
+3VS C795 1 W=20mils
1 C794
+1.8VS
0.1U_0402_16V4Z

1U_0402_6.3V4Z
2

1
4 4
R567
SA00001S570 S IC 218S7EBLA12FG SB700 BGA 528P SB 0FA J7
2 2
4.7K_0402_5% SA000030740 S IC 218-0660017 A14 SB710 FCBGA HF 0FA for Clear CMOS JOPEN

2
@
2
G

H_PWRGD 3 1
H_PWRGD_L (47)
S

Q35 Security Classification Compal Secret Data Compal Electronics, Inc.

FDV301N_NL_SOT23-3 Issued Date 2008/10/06 2009/10/06 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710-PCIE/PCI/ACPI/LPC/RTC
level shift to ISL6265 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 23 of 49
A B C D E
 A B C D E

www.bufanxiu.com
U30D @ @
demo circuit LID use RI# 1 2 C775 1 2 100P_0402_50V8J
Part 4 of 5 R376 100_0402_5%
1 +3VALW E1
SB700 1
PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB (20)
H7 SLP_S2/GPM9#
F5 G8 USB_RCOMP 1 2
(33) PM_SLP_S3# SLP_S3# USB_RCOMP
G1 11.8K_0402_1% R370
(33) PM_SLP_S5# SLP_S5#

USB MISC
H2

ACPI / WAKE UP EVENTS

(33) PBTN_OUT# PWR_BTN#
R1009 H1
(6,11,33) SB_PWRGD SUS_STAT# PWR_GOOD
10K_0402_5% (11) SUS_STAT# K3 SUS_STAT#
1 2 SUS_STAT# @ H5 E6
+3VS T14 PAD TEST2 USB_FSD13P
R405 4.7K_0402_5% H4 E7
T13 PAD

2
TEST1 USB_FSD13N
T15 PAD H3 TEST0

USB 1.1
(33) GATEA20 Y15 F7
GA20IN/GEVENT0# USB_FSD12P
(33) KB_RST# W15 KBRST#/GEVENT1# USB_FSD12N E8
(33) EC_SCI# K4
LPC_PME#/GEVENT3#
(33) EC_SMI# K24 H11
LPC_SMI#/EXTEVNT1# USB_HSD11P
F1 J10
S3_STATE/GEVENT5# USB_HSD11N
J2 SYS_RESET#/GPM7#
SB_PCIE_WAKE# H6 E11 USB20_P10
(31) SB_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB20_P10 (32)
F2 F11 USB20_N10 USB-10 Int USB
EC_RSMRST# H_THERMTRIP# BLINK/GPM6# USB_HSD10N USB20_N10 (32)
1 2 (6) H_THERMTRIP# J6
R404 2.2K_0402_5% NB_PWRGD SMBALERT#/THRMTRIP#/GEVENT2# USB20_P9
(11) NB_PWRGD W14 A11 USB20_P9 (31)
GPU_SEL NB_PWRGD USB_HSD9P USB20_N9
1
R1019 @
2
10K_0402_5% EC_RSMRST# USB_HSD9N
B11 USB20_N9 (31) USB-9 New Card
(33) EC_RSMRST# D3 RSMRST#
C10 USB20_P8
USB_HSD8P USB20_N8 USB20_P8 (31)
SB700 has internal PD USB_HSD8N
D10 USB20_N8 (31) USB-8 Bluetooth
+3VS AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_N7 USB20_P7 (32)
GPU_SEL
AD18
CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N
H12 USB20_N7 (32) USB-7 USB Camera
AA19 SMARTVOLT1/SATA_IS2#/GPIO4
W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12
V17 E14
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N
R183 1 2 2.2K_0402_5% SB_SMBCLK W20
2 SB_SPKR CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 USB20_P5 2
(36) SB_SPKR W21 C12 USB20_P5 (31)

USB 2.0
SPKR/GPIO2 USB_HSD5P
R179 1 2 2.2K_0402_5% SB_SMBDATA (8,9,20,31) SB_SMBCLK SB_SMBCLK AA18 D12 USB20_N5
USB20_N5 (31) USB-5 MiniCard(WLAN)
SB_SMBDATA SCL0/GPOC0# USB_HSD5N
(8,9,20,31) SB_SMBDATA W18
SDA0/GPOC1#
K1 SCL1/GPOC2# USB_HSD4P B12
SB_SPKR=W/S=4/4(55ohm impedance) K2 SDA1/GPOC3# USB_HSD4N A12
AA20
DDC1_SCL/GPIO9

GPIO
Y18 G12 USB20_P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 (32)
C1 G14 USB20_N3 USB-3 Int USB
LLB#/GPIO66 USB_HSD3N USB20_N3 (32)
Y19 SMARTVOLT2/SHUTDOWN#/GPIO5
G5 H14 USB20_P2
DDR3_RST#/GEVENT7# USB_HSD2P USB20_N2 USB20_P2 (29)
+3VALW USB_HSD2N H15 USB20_N2 (29) USB-2 USB Card reader
USB_HSD1P A13
1 2 GPU_SEL B13
R1020 @ 10K_0402_5% USB_HSD1N
1 2 SB_PCIE_WAKE# B14 USB20_P0
USB_HSD0P USB20_P0 (32)
R388 10K_0402_5% B9 A14 USB20_N0 USB-0 Int USB
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 (32)
1 @ 2 EC_LID_OUT# USB_OC#6 B8
(32) USB_OC#6 USB_OC5#/IR_TX0/GPM5#
R379 100K_0402_5% EC_LID_OUT# A8 A18

USB OC
(33) EC_LID_OUT# USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
E5 F21
USB_OC#1 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10
(32) USB_OC#1 F8 D21
@ USB_OC#0 USB_OC1#/GPM1# SCL2/IMC_GPIO11
(32) USB_OC#0 E4 F19
R969 10K_0402_5% USB_OC0#/GPM0# SDA2/IMC_GPIO12
1 2 AMD (un-used) SCL3_LV/IMC_GPIO13
E20
R414 33_0402_5% 1 2 HDA_BITCLK M1 E21
(36) HDA_BITCLK_AUDIO HDA_SDOUT AZ_BITCLK SDA3_LV/IMC_GPIO14
R416 33_0402_5% 1 2 M2 E19
(36) HDA_SDOUT_AUDIO AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
(36) HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 (27)
1
R970
2
10K_0402_5%
J8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17
E18 GPIO17 (27) STRAP PIN
L8
AZ_SDIN2/GPIO44

HD AUDIO
@ M3 G20
R412 33_0402_5% HDA_SYNC AZ_SDIN3/GPIO46 IMC_GPIO18
(36) HDA_SYNC_AUDIO 1 2 L6 G21
AZ_SYNC IMC_GPIO19
M4 D25
3 AZ_RST# IMC_GPIO20 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
C25

INTEGRATED uC
R408 33_0402_5% HDA_RST# IMC_GPIO22
(36) HDA_RST_AUDIO# 1 2 C24
IMC_GPIO23
IMC_GPIO24 B25
C23
IMC_GPIO25

(27) HDA_RST# B24

IMC_GPIO26
B23
IMC_GPIO27
A23
IMC_GPIO28
STRAP PIN IMC_GPIO29 C22
IMC_GPIO30 A22
B22
IMC_GPIO31
IMC_GPIO32 B21
A21
IMC_GPIO33
H19 IMC_GPIO0 IMC_GPIO34 D20
H20 C20
IMC_GPIO1 IMC_GPIO35
H21 A20
INTEGRATED uC

SPI_CS2#/IMC_GPIO2 IMC_GPIO36
F25 B20
IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37
B19
IMC_GPIO38
D22 A19
IMC_GPIO4 IMC_GPIO39
E24 D18
IMC_GPIO5 IMC_GPIO40
E25 IMC_GPIO6 IMC_GPIO41 C18
D23
IMC_GPIO7

218S7EALA11FG_BGA528_SB700

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710 USB/HD audio
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 24 of 49
A B C D E
 A B C D E

www.bufanxiu.com
U30B
1 1
Close chip
C504 1 2 0.01U_0402_16V7K SATA_STX_DRX_P0 AD9
SB700 AA24
(28) SATA_STX_C_DRX_P0 C507 1 SATA_STX_DRX_N0 SATA_TX0P IDE_IORDY
2 0.01U_0402_16V7K AE9 Part 2 of 5 AA25
(28) SATA_STX_C_DRX_N0 SATA_TX0N IDE_IRQ
HDD IDE_A0
Y22
(28) SATA_DTX_C_SRX_N0 AB10 SATA_RX0N IDE_A1 AB23
(28) SATA_DTX_C_SRX_P0 AC10 Y23
SATA_RX0P IDE_A2
IDE_DACK# AB24
C522 1 2 0.01U_0402_16V7K SATA_STX_DRX_P1 AE10 AD25
(28) SATA_STX_C_DRX_P1 SATA_TX1P IDE_DRQ
C519 1 2 0.01U_0402_16V7K SATA_STX_DRX_N1 AD10 AC25
(28) SATA_STX_C_DRX_N1 SATA_TX1N IDE_IOR#
ODD IDE_IOW# AC24
(28) SATA_DTX_C_SRX_N1 AD11 Y25
SATA_RX1N IDE_CS1#
(28) SATA_DTX_C_SRX_P1 AE11 SATA_RX1P IDE_CS3# Y24

AB12 AD24
SATA_TX2P IDE_D0/GPIO15
AC12 AD23
SATA_TX2N IDE_D1/GPIO16

ATA 66/100/133
IDE_D2/GPIO17 AE22
AE12 AC22
SATA_RX2N IDE_D3/GPIO18
AD12 SATA_RX2P IDE_D4/GPIO19 AD21
AE20
IDE_D5/GPIO20
AD13 AB20
SATA_TX3P IDE_D6/GPIO21
AE13 AD19
SATA_TX3N IDE_D7/GPIO22
AE19

SERIAL ATA
IDE_D8/GPIO23
AB14 SATA_RX3N IDE_D9/GPIO24 AC20
AC14 AD20
SATA_RX3P IDE_D10/GPIO25
IDE_D11/GPIO26 AE21
AE14 AB22
SATA_TX4P IDE_D12/GPIO27
AD14 AD22
SATA_TX4N IDE_D13/GPIO28
IDE_D14/GPIO29 AE23
AD15 SATA_RX4N IDE_D15/GPIO30 AC23
AE15
SATA_RX4P
2 SATA_X1 2
2 1 C770 AB16 SATA_TX5P
AC16
SATA_TX5N
1

27P_0402_50V8J DVT G6 SB_SPI_DI

SPI_DI/GPIO12 SB_SPI_DO
AE16 SATA_RX5N SPI_DO/GPIO11 D2
R371 SATA_CAL=W/S=9/20(35ohm impedance), <1" AD16 D1 SB_SPI_CLK
25MHZ_20PF_7A25000012 Y3 10M_0402_5% SATA_RX5P SPI_CLK/GPIO47 SB_SPI_HOLD#
F4
2

SPI_HOLD#/GPIO31

SPI ROM
2 1 SATA_CAL V12 F3 SB_SPI_CS1#
2

SATA_X2 SATA_CAL SPI_CS1#/GPIO32

2 1 C772 R375 1K_0402_1%
SATA_X1 Y12 U15
27P_0402_50V8J SATA_X1 LAN_RST#/GPIO13
J1
SATA_X2 AA12 ROM_RST#/GPIO14
R377 1 SATA_X2
+3VS 2 10K_0402_5% M8
FANOUT0/GPIO3
(35) SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5
+1.2V_HT M7
L82 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5
FBMA-L11-160808-221LMT_0603 PLLVDD_SATA FANIN0/GPIO50
P8
FANIN1/GPIO51
PLLVDD_SATA=93mA

SATA PWR
1 1 W12 R8
XTLVDD_SATA FANIN2/GPIO52
C784 C783 C6
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z TEMP_COMM
B6
2 2 TEMPIN0/GPIO61
A6
TEMPIN1/GPIO62
A5
TEMPIN2/GPIO63
B5 EC_THERM# (33)
TEMPIN3/TALERT#/GPIO64

HW MONITOR
+3VS A4 2 1
VIN0/GPIO53 ACIN (15,33,39)
L81 XTLVDD_SATA=6mA B4 D30 RB751V_SOD323
+XTLVDD_SATA VIN1/GPIO54
2 1 C4
FBMA-L11-160808-221LMT_0603 VIN2/GPIO55
2 1 D4
VIN3/GPIO56
D5
C777 C776 VIN4/GPIO57 R369 2
D6 1 100K_0402_5% +3VALW
1U_0402_6.3V4Z 0.1U_0402_16V4Z VIN5/GPIO58
A7
3 1 2 VIN6/GPIO59 R374 2 3
VIN7/GPIO60 B7 1 100K_0402_5% +3VS
+3VALW @

AVDD
F6 AVDD=5mA
G7
AVSS

218S7EALA11FG_BGA528_SB700

+3VALW C1043 1 2 0.1U_0402_16V4Z

@
Port Number Pri/SEC,Mas/Slave assignment SATA drive controlled by +SB_SPI_VCC

1K_0402_5% 1 @ 2 R1016 U51

Port 0 Primary master SATA controler SB_SPI_CS1# 1 8 @ 4.7K_0402_5%
SB_SPI_DI CS# VCC SB_SPI_HOLD# R1011 2
2 7 1
10K_0402_5%1 @ SO HOLD# SB_SPI_CLK
+3VALW 2 R1010 3 6 1 @ 2
WP# SCLK SB_SPI_DO
Port 1 Secondary master SATA controler 4 GND SI 5 R1012 0_0402_5%

MX25L1605AM2C-12G_SO8
Port 2 Primary slave SATA controler @

1
R1013
Port 3 Secondary slave SATA controler 22_0402_5%
@

2
Port 4 Primary (Secondary) master PATA controler
C1044
4 33P_0402_50V8K 4

Port 5 Primary (Secondary) slave PATA controler

@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710 SATA/IDE/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 25 of 49
A B C D E
 A B C D E

www.bufanxiu.com
U30C U30E
VDD=0.51A
VDDQ=131mA SB700 +1.2V_SB_CORE
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1
L15
M12
1
R171
2
0_0805_5%
+1.2V_HT SB700 A2
VDDQ_2 VDD_2 10U_0805_10V4Z C467 VSS_1
1 2 T15 M14 1 2 A25
C472 22U_0805_6.3V6M VDDQ_3 VDD_3 VSS_2
U9 VDDQ_4 VDD_4 N13 VSS_3 B1

CORE S0
1 1
U16 VDDQ_5 VDD_5 P12 VSS_4 D7
U17 VDDQ_6 VDD_6 P14 T10 AVSS_SATA_1 VSS_5 F20

PCI/GPIO I/O
V8 R11 1U_0402_6.3V4Z 2 1 C478 U10 G19
VDDQ_7 VDD_7 1U_0402_6.3V4Z C487 AVSS_SATA_2 VSS_6
W7 R15 2 1 U11 H8
VDDQ_8 VDD_8 0.1U_0402_16V4Z C494 AVSS_SATA_3 VSS_7
Y6 T16 2 1 U12 K9
C489 0.1U_0402_16V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C482 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C499 1 2 0.1U_0402_16V4Z AB5 V14 K16
C493 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 L10
AVSS_SATA_9 VSS_13
VDD=138mA Y14 AVSS_SATA_10 VSS_14 L11
VDD33=71mA +1.2V_CKVDD
Y17
AVSS_SATA_11 VSS_15
L12
+3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 +1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 L22 AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
AA22 L24 AB11 M6
VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18

IDE/FLSH I/O

CLKGEN I/O
AE25 L25 AB13 M10
VDD33_18_4 CKVDD_1.2V_4 AVSS_SATA_15 VSS_19
AB15 AVSS_SATA_16 VSS_20 M11
AB17 M13
AVSS_SATA_17 VSS_21
AC8 AVSS_SATA_18 VSS_22 M15
AD8 N4
AVSS_SATA_19 VSS_23
AE8 N12
AVSS_SATA_20 VSS_24
PCIE_VDDR=0.6A +PCIE_VDDR VSS_25
N14
P6
L64 POWER VSS_26
VSS_27 P9
+1.2V_HT 2 1 P10
VSS_28
A15 AVSS_USB_1 VSS_29 P11
MBK2012221YZF_0805 P18 B15 P13
C466 1 PCIE_VDDR_1 +3VALW AVSS_USB_2 VSS_30
2 4.7U_0805_10V4Z P19 C14 P15
C763 1 PCIE_VDDR_2 AVSS_USB_3 VSS_31
2 1U_0402_6.3V4Z P20 PCIE_VDDR_3 S5_3.3V=32mA D8 AVSS_USB_4 VSS_32 R1
P21 A17 +S5_3V D9 R2

A-LINK I/O
PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
R22 A24 D11 R4
PCIE_VDDR_5 S5_3.3V_2 AVSS_USB_6 VSS_34
R24 B17 D13 R9
2 PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35 2

GROUND
C759 1 2 0.1U_0402_16V4Z R25 J4 D14 R10
C497 1 PCIE_VDDR_7 S5_3.3V_4 AVSS_USB_8 VSS_36
2 0.1U_0402_16V4Z J5 D15 R12

3.3V_S5 I/O
S5_3.3V_5 2.2U_0603_6.3V4Z C769 AVSS_USB_9 VSS_37
L1 1 2 E15 R14
S5_3.3V_6 AVSS_USB_10 VSS_38
AVDD_SATA=567mA +1.2V_SATA S5_3.3V_7 L2 F12 AVSS_USB_11 VSS_39 T11
2.2U_0603_6.3V4Z 1 2 C486 F14 T12
L79 AVSS_USB_12 VSS_40
G9 T14
AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 H9 AVSS_USB_14 VSS_42 U4
AB18 +1.2VALW H17 U14
MBK2012221YZF_0805 AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 +S5_1.2V
S5_1.2V=113mA J9 AVSS_USB_16 VSS_44 V6
AA17 G2 J11 Y21
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

CORE S5
SATA I/O
C764 1 2 22U_0805_6.3V6M AC18 G4 J12 AB1
C766 1U_0402_6.3V4Z AVDD_SATA_5 S5_1.2V_2 +1.2VALW C797 2 AVSS_USB_18 VSS_46
1 2 AD17 USB_PHY_1.2V=197mA 1 1U_0402_6.3V4Z J14 AB19
C765 1U_0402_6.3V4Z AVDD_SATA_6 L80 C796 2 AVSS_USB_19 VSS_47
1 2 AE17 AVDD_SATA_7 1 1U_0402_6.3V4Z J15 AVSS_USB_20 VSS_48 AB25
C767 1 2 0.1U_0402_16V4Z +1.2_USB 1 2 K10 AE1
C768 0.1U_0402_16V4Z MBK1608221YZF_0603 AVSS_USB_21 VSS_49
1 2 A10 K12 AE24
USB_PHY_1.2V_1 C771 1 AVSS_USB_22 VSS_50
B10 2 10U_0805_10V4Z K14
USB_PHY_1.2V_2 AVSS_USB_23
K15
C773 2 AVSS_USB_24
1 0.1U_0402_16V4Z P23
C774 2 PCIE_CK_VSS_9
1 0.1U_0402_16V4Z R16
PCIE_CK_VSS_10
AVDDTX/RX=658mA +AVDD_USB PCIE_CK_VSS_11 R19
T17
L65 PCIE_CK_VSS_12
+V5_VREF
V5_VREF=1mA PCIE_CK_VSS_13
U18
+3VALW 2 1 A16 AE7 1K_0402_5% 2 1 R386 +5VS H18 U20
AVDDTX_0 V5_VREF D31 PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 2 J17 V18
MBK2012221YZF_0805 AVDDTX_1 +AVDDCK_3.3V PCIE_CK_VSS_2 PCIE_CK_VSS_15
C16 J16 1 2 +3VS J22 V20
C461 1 10U_0805_10V4Z AVDDTX_2 AVDDCK_3.3V C786 PCIE_CK_VSS_3 PCIE_CK_VSS_16
2 D16 K25 V21
C469 1 10U_0805_10V4Z AVDDTX_3 +AVDDCK_1.2V PCIE_CK_VSS_4 PCIE_CK_VSS_17
2 D17 K17 1U_0402_6.3V4Z CH751H-40PT_SOD323-2 M16 W19
PLL

C495 1 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

2 E17 M17 W22
AVDDTX_5 PCIE_CK_VSS_6 PCIE_CK_VSS_19
USB I/O

C485 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
F17
AVDDRX_1 AVDDC=17mA L69
P16
PCIE_CK_VSS_8 PCIE_CK_VSS_21
W25
F18
C481 1 AVDDRX_2
2 0.1U_0402_16V4Z G15 2 1 +3VALW F9 L17
3 AVDDRX_3 FBMA-L11-160808-221LMT_0603 AVSSC AVSSCK 3
G17 AVDDRX_4 Part 5 of 5
G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C484 218S7EALA11FG_BGA528_SB700

218S7EALA11FG_BGA528_SB700 0.1U_0402_16V4Z 2 1 C496

AVDDCK_1.2V=62mA
L77
+AVDDCK_1.2V 2 1 +1.2V_HT
FBMA-L11-160808-221LMT_0603

2.2U_0603_6.3V4Z 2 1 C758

0.1U_0402_16V4Z 2 1 C761

AVDDCK_3.3V=47mA
L76
+AVDDCK_3.3V 2 1 +3VS
FBMA-L11-160808-221LMT_0603

2.2U_0603_6.3V4Z 2 1 C756

0.1U_0402_16V4Z 2 1 C760

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710 power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 26 of 49
A B C D E
 A B C D E

REQUIRED STRAPS www.bufanxiu.com NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

LPC_CLK0
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 CLK_PCI_EC LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
H,H = Reserved
ENABLED STRAPS
1 DEFAULT 1
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default L,NC)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R363

R367
R427

R425

R423

R421

R453

R361

R401

R411
2

2
@ @ @ @ @ @ @ @
(23) PCI_CLK2 @
(23) PCI_CLK3
(23) PCI_CLK4
(23) PCI_CLK5
(23,33) CLK_PCI_EC
(23) LPCCLK1
(23) RTC_CLK
(24) HDA_RST#
2 (24) GPIO17 2
(24) GPIO16

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R402

R362

R366
R424

R422

R420

R398

R454

R452

R410
2

2
@ @ @
@

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK

(23) PCI_AD28
(23) PCI_AD27
(23) PCI_AD26
(23) PCI_AD25
(23) PCI_AD24
(23) PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R392

R393

R395

R389

R396

R399
2

2
@ @ @ @ @ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 27 of 49
A B C D E
 A B C D E F G H

www.bufanxiu.com

1
SATA ODD Conn. 1

JSATA1

1 GND GND 14
SATA_STX_C_DRX_P1 2 15
(25) SATA_STX_C_DRX_P1 SATA_STX_C_DRX_N1 A+ GND
(25) SATA_STX_C_DRX_N1 3 A-
4 GND
(25) SATA_DTX_C_SRX_N1 C513 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N1 5
C510 SATA_DTX_SRX_P1 B-
(25) SATA_DTX_C_SRX_P1 1 2 0.01U_0402_16V7K 6 B+
7
GND

8
DP
9
+5V
+5VS 10 +5V
11
MD
12 GND
13
2A GND
OCTEK_SLS-13SD1G_NR
ME@

+5VS Placea caps. near ODD CONN.

0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1
C491 C492 C505
2 C490 2
2 2 2 2

1000P_0402_25V8J 1U_0402_6.3V4Z

SATA HDD Conn.

JSATA2
1
SATA_STX_C_DRX_P0 GND
2
(25) SATA_STX_C_DRX_P0 SATA_STX_C_DRX_N0 A+
3
(25) SATA_STX_C_DRX_N0 A-
4
C515 SATA_DTX_SRX_N0 GND
(25) SATA_DTX_C_SRX_N0 1 2 0.01U_0402_16V7K 5
3 C521 SATA_DTX_SRX_P0 B- 3
(25) SATA_DTX_C_SRX_P0 1 2 0.01U_0402_16V7K 6 B+
7 GND
Close conn
+3VS 8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12
GND
13 GND
+5VS 14
+5VS VCC5
10U_0805_10V4Z 15
0.1U_0402_16V4Z VCC5
16
+3VS
1 1 1 1 1 1
1A 17
18
VCC5
GND
RESERVED
1 C556 C554 C557 C555 C552 19
C792 GND
20
C551 VCC12
21
0.1U_0402_16V4Z 2 2 2 2 2 2 VCC12
22
2 VCC12
1000P_0402_25V8J 1U_0402_6.3V4Z 23
0.1U_0402_16V4Z 0.1U_0402_16V4Z G1
24 G2
OCTEK_SAT-22SB1G_RV
JALA0
ME@ (CL 9.2mm)

for ESD issue

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 28 of 49
A B C D E F G H
 A B C D E

C748 1
www.bufanxiu.com add at 8/11
EMI reserved
Close to U7 pin24
2 100P_0402_50V8J
@ @ C963
1 R851 2 1 2
R682
U7
22_0402_5% 33P_0402_50V8K
2 1 6.19K_0402_1% 1 REFE
GPIO0 17
+3VALW USB20_N2 2
1 (24) USB20_N2 DM 1
USB20_P2 3 24 CLK_48M_CR
400mA Trace width:20mil
(24) USB20_P2
4
DP

3V3_IN
CLK_IN

XD_D7 23 XD_D7
CLK_48M_CR (20)

+VCC_3IN1 5 CARD_3V3
6 22 XD_D6_MS_BS
V18 SP14 XD_D5_SD_D2_MS_D5
SP13 21

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
1 1 1 2 XD_CD# 7 20 XD_D4_SD_D3_MS_D1
C746 C747 C752 XD_CD# SP12 XD_D3_SD_D4_MS_D4
SP11 19
C751 2 R677 1XD_RDY_SD_WP_MS_CLK 8 18 XD_D2_SD_CMD
10U_0805_10V4Z 0_0402_5% XD_RE#_MS_INS# SP1 SP10 XD_D1_SD_D5_MD_D0 R678
9 SP2 SP9 16
2 2 2 1 XD_CE#_SD_D1 XD_D0_SD_CLK_MS_D2 XD_D0_SD_CLK_MS_D2_R
10 SP3 SP8 15 2 1

EPAD
XD_CLE_SD_D0_MS_D7 11 14 XD_WP_SD_D6_MS_D6
SP4 SP7

XD_RDY_SD_WP_MS_CLK_R
XD_ALE_SD_D7_MS_D3 12 13 XD_WE#_SD_CD#
SP5 SP6 0_0402_5%
RTS5138-GR_QFN24_4X4

25
EMI reserved Close to JP1

XD_D0_SD_CLK_MS_D2_R

XD_RDY_SD_WP_MS_CLK_R

1
2 @ @ 2
R681 R680
10_0402_5% 10_0402_5%

1 1

2
@ @

Card reader(XD/SD/MMC/MS/MS-Pro HD SD) 2

C750
10P_0402_50V8J
2
C749
10P_0402_50V8J

+VCC_3IN1 7 in 1 Card Reader

400mA Trace width:20mil 1
@
R679
2

100K_0402_1%
JP2
3 XD-VCC SD-VCC 21
MS-VCC 28
XD_D0_SD_CLK_MS_D2 32
XD_D1_SD_D5_MD_D0 XD-D0 XD_D0_SD_CLK_MS_D2_R
10 XD-D1 7 IN 1 CONN SD_CLK 20
XD_D2_SD_CMD 9 14 XD_CLE_SD_D0_MS_D7
XD_D3_SD_D4_MS_D4 XD-D2 SD-DAT0 XD_CE#_SD_D1
8 XD-D3 SD-DAT1 12
XD_D4_SD_D3_MS_D1 7 30 XD_D5_SD_D2_MS_D5
XD_D5_SD_D2_MS_D5 XD-D4 SD-DAT2 XD_D4_SD_D3_MS_D1
6 XD-D5 SD-DAT3 29
3 XD_D6_MS_BS 5 27 XD_D3_SD_D4_MS_D4 3
XD_D7 XD-D6 SD-DAT4 XD_D1_SD_D5_MD_D0
4 XD-D7 SD-DAT5 23
18 XD_WP_SD_D6_MS_D6
XD_WE#_SD_CD# SD-DAT6 XD_ALE_SD_D7_MS_D3
34 XD-WE SD-DAT7 16
XD_WP_SD_D6_MS_D6 33 25 XD_D2_SD_CMD
XD_ALE_SD_D7_MS_D3 XD-WP SD-CMD XD_WE#_SD_CD#
35 XD-ALE SD-CD-SW 1
XD_CD# 40
XD_RDY_SD_WP_MS_CLK XD-CD XD_RDY_SD_WP_MS_CLK
39 XD-R/B SD-WP-SW 2
XD_RE#_MS_INS# 38
XD_CE#_SD_D1 XD-RE
37 XD-CE
XD_CLE_SD_D0_MS_D7 36 26 XD_RDY_SD_WP_MS_CLK_R
XD-CLE MS-SCLK XD_D1_SD_D5_MD_D0
MS-DATA0 17
11 15 XD_D4_SD_D3_MS_D1
7IN1 GND MS-DATA1 XD_D0_SD_CLK_MS_D2
31 7IN1 GND MS-DATA2 19
24 XD_ALE_SD_D7_MS_D3
MS-DATA3 XD_RE#_MS_INS#
MS-INS 22
13 XD_D6_MS_BS
MS-BS
41 7IN1 GND
42 7IN1 GND
TAITW_R015-B10-LM_NR
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1
C745 C744
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTS5138 Card Reader
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 29 of 49
A B C D E
 A B C D

www.bufanxiu.com
Place Close to LAN chip
R479 49.9_0402_1%
+3V_LAN D42
MDI0+ 1 2
L39 R360 49.9_0402_1% 1 2 C181 0.1U_0402_16V4Z 10/100_LINK_LED 2
J4 @ 1 2 +1.8_VDD/LX MDI0- 1 2 1 LINK_LED
+3VALW 2 1 JOPEN 60mil S INDUC_ 4.7UH +-20% SIA4012-4R7M 1000_LINK_LED 3
R480 49.9_0402_1%
1 1 1 1 MDI1+ 1 2
R478 49.9_0402_1% CHP202UPT_SOT323-3
1 2 C139 0.1U_0402_16V4Z
C1029 C391 C690 C277 MDI1- 1 2
10U_0805_10V4Z
10U_0805_10V4Z 0.1U_0402_16V4Z +AVDD_CEN +AVDD_CEN
2 8131@ 2 2 2 8131@ R909 49.9_0402_1%
1 1
3 Q5 1U_0402_6.3V4Z C190 C390 MDI2+

S
1 1 2
0.1U_0402_16V4Z 10U_0805_10V4Z 8131@ R910 49.9_0402_1% 1 2 C1016 0.1U_0402_16V4Z
@ AO3414_SOT23-3 MDI2- 1 2
1
+3VALW 2 2 1

Place Close to Pin 2 8131@ C689 close to U9 pin15

G
2
8131@ R911 49.9_0402_1%
MDI3+
C189 close to U9 pin19
1 2
1

8131@ R912 49.9_0402_1% 1 2 C1017 0.1U_0402_16V4Z C845 close to U9 pin25

R337 MDI3- 1 2
33K_0402_5% 8131@
@ L39 close to U9 pin1, C190 and C390 close to L39 add GIGA LAN resistor at 8/12
2

+2.5V_VDDH 0.1U_0402_16V4Z
1 1 1
C689 C189 C845
U9 1U_0402_6.3V4Z 0.1U_0402_16V4Z
2 60mil
1

C182 D 2 2 2
0.1U_0402_16V4Z

@ 2 EN_WOL +1.8_VDD/LX 1 30
EN_WOL (33) VDDHO/VDD18O/VDD18O TWSI_DATA
G Q2 29
1 2N7002_SOT23 TWSI_CLK 10/100_LINK_LED
S
85mA 48
3

@ LED_LINK10_100n ACTIVITY#
+3V_LAN 2 47
VDD3V LED_ACTn
27 1 R693 2 +3V_LAN
+AVDD_CEN SPI_CS/LED_DUPLEXn/LED_DUPLEXn 4.7K_0402_5%
2 1 6
C315 0.1U_0402_16V4Z VDD3V/VDDHO/VDDHO
26 1000_LINK_LED C688, C184 close to U9 pin8
+2.5V_VDDH SPI_DI/NC/LED_Link1000n
2 1 5 C187 close to U9 pin16
C314 0.1U_0402_16V4Z VDDLO/CTR12/CTR12 C8441
40 20.1U_0402_10V7K CLK_PCIE_LAN# (20)
1 R689@ 4.7K_0402_5%
2
REFCLKN
41 C8431 20.1U_0402_10V7K C140 close to U9 pin22
+3V_LAN REFCLKP CLK_PCIE_LAN (20)
(11,13,14,23,31,33) PLT_RST#
PLT_RST# 3 C141 close to U9 pin36
PERSTn MDI0-
R286 14 C846 close to U9 pin39
10K_0402_5% TXN0/TXN0/TRXN0 MDI0+
13
TXP0/TXP0/TRXP0 MDI1-
+3V_LAN 1 2 7 18
VAUX_AVL/VBG1P18/VBG1P18 RXN1/RXN1/TRXN1 MDI1+
17
LAN_WAKE# RXP1/RXP1/TRXP1 MDI2- +1.2_AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z0.1U_0402_16V4Z
(33) LAN_WAKE# 4 21
C317 1 WAKEn NC/NC/TRXN2
2 0.1U_0402_10V7K PCIE_IRX_C_PTX_N2 MDI2+

Atheros
(10) PCIE_PTX_C_IRX_N2 37 20
+1.2_AVDDL C316 1 PCIE_IRX_C_PTX_P2 TX_N NC/NC/TRXP2 MDI3-
(10) PCIE_PTX_C_IRX_P2 2 0.1U_0402_10V7K 38 24 1 1 1 1 1 1
TX_P NC/NC/TRXN3 MDI3+
(10) PCIE_ITX_C_PRX_N2 44 23
RX_N NC/NC/TRXP3 C688 C184 C187 C140 C141 C846
(10) PCIE_ITX_C_PRX_P2 43
RX_P
LAN_XTALO
AR8121/8131 +AVDDVCO2 2 2 2 2 2 2
2 9 42 2

LAN_XTALI XTLO AVDDL0 +1.2_AVDDL 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

10 39
XTLI AVDDL1
36
AVDDL2
22
R157 0_0603_5% DVDDL/AVDDL/AVDDL
34 16
+AVDDVCO1 TESTMODE AVDDL3 +AVDDVCO1
1 2 1 2 35 11
@ NC AVDDL4 +1.2_AVDDL
1 8
R158 AVDDL5
0_0603_5% C138 C687 close U9 pin46
0.1U_0402_16V4Z 31 46 +1.2_DVDDL
2 SMCLK DVDDL0 C193 close U9 pin45
33 45
SMDATA AVDDL/DVDDL/DVDDL C183 close U9 pin28
32
DVDDL1
C138 close to Pin11 of U9 28 C185 close U9 pin32
SPI_CLK/DVDDL/DVDDL
49
GND +2.5V_VDDH +1.2_DVDDL 0.1U_0402_16V4Z
25
+AVDDVCO2 SPI_DO/AVDDH/AVDDH
1 2 19 1 1 1 1
R323 1 AVDDH0
1 2 2.37K_0402_1% 12 15
L18 0_0603_5% 0.1U_0402_16V4Z RBIAS AVDDH1 C687 C193 C183 C185
C192 1U_0402_6.3V4Z 0.1U_0402_16V4Z
2 2 2 2
2 S IC AR8132-AL1E_QFN48P_6X6 0.1U_0402_16V4Z
C192 close to Pin11 of U42
8132@
If overclocking, R157 , L18 stuffed and R158 removed.
If not overclocking, R158 , L18 suffed and R157 removed. LAN_XTALI
AR8131:L18=0ohm (more power saving mode)
LAN_XTALO U9

RJ45 CONN
R694
AR8131 5.1K_0402_5%
Y5 8131@ 2 1
1 2 JRJ45
R335 12
25MHZ_20P 510_0402_5% Amber LED-
1 1
3 ACTIVITY# 2 1 11 16 3

C806 C805 Amber LED+ SHLD4

+AVDD_CEN 27P_0402_50V8J
add signal at 8/12
27P_0402_50V8J 2 MDO3- 8 15
2 2 220P_0402_50V7K PR4- SHLD3
C810 MDO3+ 7
PR4+
1

R688 1 MDO1- 6
0_0603_5% PR2-
C191 close to R688 MDO2- 5
PR3-
2

C191 1 2 1U_0603_10V4Z MDO2+

C810 close to U9 4
PR3+
MDO1+ 3
U41 PR2+
C1018 1 2 0.1U_0402_16V4Z 1 24 MCT3 R913 2 8131@ 1 75_0402_5% MDO0- 2
8131@ TCT1 MCT1 PR1-
14
MDI3+ 1:1 MDO3+ MDO0+ SHLD2
C1018 close to Pin1 2
TD1+ MX1+
23 R334 1
PR1+
510_0402_5%
LINK_LED 2 1 10 13
Green LED- SHLD1

+3V_LAN 1 9
MDI3- MDO3- Green LED+
3 22
TD1- MX1- C811 FOX_JM36113-P2221-7F
C1019 1 2 0.1U_0402_16V4Z 4 21 MCT2 R914 2 8131@ 1 75_0402_5% 220P_0402_50V7K ME@
8131@ TCT2 MCT2 2
C1019 close to Pin4 MDI2+ 5 1:1 20 MDO2+
TD2+ MX2+

C811 close to JRJ45

MDI2- 6 19 MDO2- RJ45_PR 1 2
TD2- MX2- C318
C186 1 2 0.1U_0402_16V4Z 7 18 MCT1 R581 2 1 75_0402_5% 1000P_1206_2KV7K
TCT3 MCT3
C186 close to Pin7 MDI1+ 8 1:1 17 MDO1+
TD3+ MX3+

4 4

MDI1- 9 16 MDO1-
TD3- MX3-
C188 1 2 0.1U_0402_16V4Z 10 15 MCT0 R580 2 1 75_0402_5% RJ45_PR
TCT4 MCT4
C188 close to Pin10 U41 MDI0+ 11 1:1 14 MDO0+
TD4+ MX4+

MDI0- 12 13 MDO0-
NS892404 TD4- MX4- Security Classification Compal Secret Data Compal Electronics, Inc.
8132@ 350uH_NS892406 change to GIGA LAN transformer at 8/12 Issued Date 2008/04/16 2009/04/16 Title
8131@ Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Atheros AR8132 & LAN CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 30 of 49
A B C D
 A B C D E

+3VS
For Wireless LAN
+1.5VS_UMA www.bufanxiu.com
1 1 1 1 1 1
C842 C841 C813 C825 C808 C823
(35) BT_LED#
Q41 BT MODULE CONN

1
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DTC124EKAT146_SC59-3
2 2 2 2 2 2

OUT
JP30
WLAN@ WLAN@ WLAN@ @ @ @ 1
BTON_LED 1
IN 2 2 2
1 JP22 WLAN_ACTIVE 1
3

GND
SB_PCIE_WAKE# R457 1 @ BT_ACTIVE 3
(24) SB_PCIE_WAKE# 2 0_0402_5% 1 WAKE# 3.3V 2 +3VS 4 4
BT_ACTIVE R103 1 2 @ 0_0402_5% 3 4 @ BT@ (24) USB20_P8 USB20_P8 5
WLAN_ACTIVE R102 1 NC GND USB20_N8 5
2 @ 0_0402_5% 5 6 2 1 +1.5VS_UMA (24) USB20_N8 6

3
NC 1.5V J3 LPC_FRAME#_R
JOPEN 6
(20) MINI1_CLKREQ# 7 8 7
CLKREQ# NC LPC_AD3_R 7
9 GND NC 10 8 8
11 12 LPC_AD2_R +5VALW +5VS 9
(20) CLK_PCIE_MINI1# REFCLK- NC LPC_AD1_R GND1
13 14 +3VS +3VS_BT 10
(20) CLK_PCIE_MINI1 REFCLK+ NC LPC_AD0_R GND2
15 GND NC 16 Q43 30mils

D
PLT_RST#
R983 1 @ 2 PLT_RST#_R
0_0402_5% 17 18 3 1 AO3413_SOT23-3 ACES_88231-08001
CLK_PCI_DB NC GND WL_OFF# BT@ ME@
19 NC NC 20 WL_OFF# (33) 1
21 22 PLT_RST# R1017 R257
GND PERST# +3V_WLAN PLT_RST# (11,13,14,23,30,33)
23 24 R458 1 2 0_0603_5% 100K_0402_1% 100K_0402_1% C488

G
(10) PCIE_PTX_C_IRX_N1 +3VS

2
PERn0 +3.3Vaux R459 1 @
(10) PCIE_PTX_C_IRX_P1 25 26 2 0_0603_5% +3VALW @ BT@ 0.1U_0402_16V4Z

2
PERp0 GND @ 2
27 28 1 R1014 2 BT@
GND +1.5V SB_SMBCLK 100K_0402_1%
29 30 SB_SMBCLK (8,9,20,24) 1
GND SMB_CLK

1
31 32 SB_SMBDATA BT@
(10) PCIE_ITX_C_PRX_N1 PETn0 SMB_DATA SB_SMBDATA (8,9,20,24)
C1045
33 34
change pin define

OUT
(10) PCIE_ITX_C_PRX_P1 PETp0 GND
35 36 0.1U_0402_16V4Z
GND USB_D- USB20_N5 (24) 2
1 2 37 38 BT@
+3VS R709 1 WLAN@ 2 0_0402_5% 39
NC
NC
USB_D+
GND
40
USB20_P5 (24)
(33) BT_OFF# 2
IN
for new symbol (JP22)
R710 1 WLAN@ 2 0_0402_5% 41 42 Q42
on C test

GND
+3VALW NC LED_WWAN#
R711 1 @ 2 0_0402_5% 43 NC LED_WLAN# 44 1 2 WLAN_LED# (35) DTC124EKAT146_SC59-3
R712 WLAN@ 0_0402_5% 45 46 (MINI1_LED#) R547 WLAN@ 0_0402_5% BT@
0_0402_5% NC LED_WPAN#
47 48

3
R432 1 EC_TX_P80_DATA_R NC +1.5V
(33) EC_TX_P80_DATA 2 49 NC GND 50
EC_RX_P80_CLK_R
(33) EC_RX_P80_CLK 1 2
R935 0_0402_5%
51
NC +3.3V
52 (9~16mA)
2

53 GND GND 54
R936
100K_0402_5%
@ TAITW_PFPET0-AFGLBG1ZZ4N0 Reserve for SW mini-pcie debug card.
2 2
Series resistors closed to KBC side.
1

ME@
add at 8/13
LPC_FRAME#_R R974 1 @ 2 0_0402_5% LPC_FRAME#
LPC_AD3_R LPC_AD3 LPC_FRAME# (23,33)
R975 1 @ 2 0_0402_5%
LPC_AD2_R LPC_AD2 LPC_AD3 (23,33)
Mini Card Power Rating R976 1 @ 2 0_0402_5%
LPC_AD2 (23,33)
LPC_AD1_R R977 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 (23,33)
Power Primary Power (mA) Auxiliary Power (mA) LPC_AD0_R R978 1 @ 2 0_0402_5% LPC_AD0
CLK_PCI_DB LPC_AD0 (23,33)
CLK_PCI_DB (23)
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable) add at 8/11 +3VS +1.5VS_UMA

1 1
C985 @
@ C986
0.1U_0402_16V4Z 0.1U_0402_16V4Z JEXP1
2 2
1
USB20_N9 GND
(24) USB20_N9 2
USB20_P9 USB_D-
add at 8/11 (24) USB20_P9 3 USB_D+
CPUSB# 4
CPUSB#
5
RSV
6
+1.5VS_CARD1 RSV
(8,9,20,24) SB_SMBCLK 7
SMB_CLK
8
3 +3VS Imax = 0.75A (8,9,20,24) SB_SMBDATA
9
SMB_DATA 3
Express Card Power Switch 1
NEWCARD@
1
+1.5VS_CARD1
10
11
+1.5V
+1.5V
U48 (24) SB_PCIE_WAKE# WAKE#
2

R904 +1.5VS_UMA +1.5VS_CARD1 C989 C987 12

+3VALW_CARD1 +3.3VAUX
12 11 10U_0805_10V4Z 0.1U_0402_16V4Z PERST# 13
+1.5VS_UMA 1.5Vin 1.5Vout 40mil 2 2 NEWCARD@ PERST#
0_1206_5%

14 13 +3VS_CARD1 14
1.5Vin 1.5Vout +3.3V
15
NEWCARD@ +3VS_CARD1 +3.3V
16
1 60mil (20) EXP_CLKREQ#
1

CPUSB# CLKREQ#
2 3 17
C988 3.3Vin 3.3Vout +3VS_CARD1 CPPE#
4 3.3Vin 3.3Vout 5 (20) CLK_PCIE_EXP# 18 REFCLK-
0.1U_0402_16V4Z +3VALW +3VALW_CARD1 19
2 NEWCARD@
17 15
40mil Imax = 1.35A (20) CLK_PCIE_EXP
20
REFCLK+
AUX_IN AUX_OUT GND
1 1 (10) PCIE_ITX_C_PRX_N4 21 PERn0
PLT_RST# 6 19 NEWCARD@ 22
(11,13,14,23,30,33) PLT_RST# SYSRST# OC# (10) PCIE_ITX_C_PRX_P4 PERp0
C990 C991 23
+3VS SYSON PERST# 10U_0805_10V4Z 0.1U_0402_16V4Z GND
(33,38,43) SYSON 20 8 (10) PCIE_PTX_C_IRX_N4 24
SHDN# PERST# 2 2 NEWCARD@ PETn0
(10) PCIE_PTX_C_IRX_P4 25
SUSP# PETp0
1 (18,33,38,41,44,46) SUSP# 1 16 26
STBY# NC GND
C992 +3VALW R905 1 2 @ 100K_0402_5% 10 7 27
0.1U_0402_16V4Z CPPE# GND +3VALW_CARD1 GND
28
2 NEWCARD@ CPUSB# GND
9 CPUSB#
21
Imax = 0.275A
PAD SANTA_130801-5_RT
18 RCLKEN 1 1
@ ME@
+3VALW C993 C994
P2231NL_QFN20
10U_0805_10V4Z 0.1U_0402_16V4Z
1 NEWCARD@ 2 2 NEWCARD@ (NEW)
C995
0.1U_0402_16V4Z
2 NEWCARD@
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD/BT/ NEW CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 31 of 49
A B C D E
 A B C D E

www.bufanxiu.com (24) USB20_N0

USB20_N0 4
4
WCM-2012-900T_4P
3
3 USB20_N0_R

USB20_P0 1 1 2 USB20_P0_R
(24) USB20_P0
@2
CMOS Camera Conn L102
USB20_N10 4 WCM-2012-900T_4P 3 USB20_N10_R
(24) USB20_N10 4 3
+5VS
150mA
Q48
(24) USB20_P10
USB20_P10 1
1
2 USB20_P10_R
@2

D
3 1 AO3413_SOT23-3
1 CMOS@ L103 1
1

1
USB20_P3 4 3 USB20_P3_R
(24) USB20_P3 4 3
C550

G
2
R259 R258 0.1U_0402_16V4Z
100K_0402_5% 0_0603_5% 2 USB20_N3 USB20_N3_R
R1015 (24) USB20_N3 1 2
CMOS@ CMOS@ 1L104 @2

2
1 2 CMOS@ WCM-2012-900T_4P
100K_0402_5%

1
CMOS@ 1 1 R944 0_0402_5%
CMOS@ @ USB20_N0 1 2 USB20_N0_R

OUT
C1046 C1047 JP31 R945 0_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 USB20_P0 1 2 USB20_P0_R
2 2 USB20_N7 1 R946 0_0402_5%
(33) CMOS_OFF# 2 IN (24) USB20_N7 2 2
(24) USB20_P7 USB20_P7 3 USB20_N10 1 2 USB20_N10_R

GND
CMOS@ 3 R947 0_0402_5%
4
Q49 4 USB20_P10 USB20_P10_R
1 5 1 2
DTC124EKAT146_SC59-3 CMOS@ 5 R948 0_0402_5%
6

3
C553 GND1 USB20_N3 USB20_N3_R
7 1 2
10U_0805_10V4Z GND2 R949 0_0402_5%
2 USB20_P3 USB20_P3_R
ACES_88266-05001 EMI request 1 2
ME@
add at 8/14

2 2

JUSB3
8
GND
7 GND
6
6
5 5
+USB_VCCC USB20_P3_R 4
USB20_N3_R 4
3
3
2
2
1
1
ACES_85201-06051

ME@

+5VALW
D43
USB20_N3_R 2
1
+USB_VCCC USB20_P3_R 3
U43 EMI request
1 8 1 PJDLC05_SOT23-3
C501 0.1U_0402_16V4Z 2
GND VOUT
7 1
add at 8/14 @
VIN VOUT + C503
2 1 3 6
3 VIN VOUT 150U_B2_6.3VM_R35M
C545 +USB_VCCA 3
(33) USB_ON# 4 EN FLG 5 USB_OC#1 (24)
470P_0402_50V7K +USB_VCCA
APL3510BKI-TRGSO8 2 2
W=80mils
1 @ @ W=80mils 1
C502 1 C947
@ 1000P_0402_25V8J C946
470P_0402_50V7K
2 470P_0402_50V7K 2
2

+5VALW

JUSB2
JUSB1 1
+USB_VCCA USB20_N10_R VCC
1 2
U45 USB20_N0_R VCC USB20_P10_R D-
2 3
USB20_P0_R D- D+
1 8 1 3 4
C546 0.1U_0402_16V4Z GND VOUT D+ GND
2 VIN VOUT 7 1 4 GND
2 1 3 6 + C548 5
VIN VOUT 150U_B2_6.3VM_R35M
C549 GND1
(33) USB_ON# 4 EN FLG 5 USB_OC#6 (24) 5 GND1 6 GND2
470P_0402_50V7K 6 7
APL3510BKI-TRGSO8 2 2 GND2 GND3
USB_OC#0 (24) 7 8
GND3 GND4
8 GND4
1 @ SUYIN_020173MR004G579ZR
C547 SUYIN_020173MR004G579ZR ME@
@ 1000P_0402_25V8J ME@ D45
D44 USB20_N10_R 2
2 USB20_N0_R 2 1
4 USB20_P10_R 4
1 3
USB20_P0_R 3
EMI request PJDLC05_SOT23-3
EMI request PJDLC05_SOT23-3
add at 8/14
@
@
add at 8/14

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BlueTooth / Int USB x2 /eSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 32 of 49
A B C D E
 www.bufanxiu.com
+3VALW

1 1 1 1 1 1
+3VALW +EC_AVCC
C731 C733 C732 C730 C734 C735
+3VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J
2 2 2 2 2 2
+3VS

111
125
22
33
96

67
1

9
U6
@ R700

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
@ R595 10K_0402_5%
10K_0402_5%

2
2
1 21 KILL_SW# (34) +3VALW 1 2 +EC_AVCC
(24) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# L19 FCM1608CF-121T03_2P
(24) KB_RST# 2 23 BEEP# (36)
KBRST#/GPIO01 BEEP#/PWM2/GPIO10
(23) SERIRQ 3 26 NOVO# (35) 2
SERIRQ# FANPWM1/GPIO12 ACOFF
(23,27) CLK_PCI_EC (23,31) LPC_FRAME# 4 27 ACOFF (39,41)
LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 C728
(23,31) LPC_AD3 5 LAD3
1 2 1 2 LPC_AD2 7 PWM Output 0.1U_0402_16V4Z
(23,31) LPC_AD2 LAD2 1
C742 @ R603@ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
(23,31) LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP BATT_TEMP (40) ECAGND
LAD0 LPC & MISC
(23,31) LPC_AD0 10 64 BATT_OVP (41) 1 2
22P_0402_50V8J BATT_OVP/AD1/GPIO39 L20 FCM1608CF-121T03_2P
65 ADP_I (41)
ver 01:for EMC request ADP_I/AD2/GPIO3A VOUTX
12 PCICLK AD Input AD3/GPIO3B 66
13 75 VOUTY
13,14,23,30,31) PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW 1 2 37 76
R613 47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43
(24) EC_SCI# 20 SCI#/GPIO0E
1

38 +3VALW
2 CLKRUN#/GPIO1D
68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG (21)

1
R591 C729 70 EN_FAN1
EN_DFAN1/DA1/GPIO3D IREF EN_FAN1 (37)
100K_0402_5%
1
0.1U_0402_16V4Z DA Output IREF/DA2/GPIO3E
71 IREF (41)
R594
KSI0 55 72 10K_0402_5%
CHGVADJ (41)
2

KSI1 KSI0/GPIO30 DA3/GPIO3F

56
KSI2 KSI1/GPIO31
57

2
KSI3 KSI2/GPIO32
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# (36)
KSI4 59 84 USB_ON# BATT_OVP 1 2
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# (32)
60 85 C737 100P_0402_50V8J
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C 05/25 BATT_TEMP
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 1 2
KSI7 62 87 TP_CLK C738 100P_0402_50V8J
+3VALW KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK (34)
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (34)
KSO1 40 ACIN 1 2
KSO1 KSO[0..15] KSO2 KSO1/GPIO21 C736 100P_0402_50V8J
1 2 41 KSO2/GPIO22
R611 47K_0402_5% (34) KSO[0..15] KSO3 42 97 WL_OFF#
KSI[0..7] KSO3/GPIO23 SDICS#/GPXOA00 WL_OFF# (31)
1 2 KSO2 KSO4 43 98
(34) KSI[0..7] KSO5 KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL (30)
KSO5/GPIO25 Int. K/B
R612 47K_0402_5% 44 99
KSO6 SDIDO/GPXOA02 LID_SW# BATT_SEL_EC (41)
45 109
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW# (34)
46
KSO7/GPIO27 SPI Device Interface
1 2 LID_SW# KSO8 47 close to EC pin126 for RF request
R608 4.7K_0402_5% KSO9 KSO8/GPIO28 FRD#SPI_SO
48 119 FRD#SPI_SO (34)
+5VALW Ver02:add pull high resister KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI
49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI (34)
KSO11 50 SPI Flash ROM 126 SPI_CLK_R 1 2 SPI_CLK
EC_SMB_CK1 KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# SPI_CLK (34)
1 2 51 128 R602 FBMA-10-100505-101T_0402
1
KSO13 KSO12/GPIO2C SPICS# FSEL#SPICS# (34)
R610 4.7K_0402_5% 52
KSO13/GPIO2D
1 2 EC_SMB_DA1 KSO14 53 KSO14/GPIO2E
R1003
1 @ 20_0402_5% VGA_VARIBL (14,21)
C739
R607 4.7K_0402_5% KSO15 54 73 SSD_DET# 10P_0402_50V8J
KSO15/GPIO2F CIR_RX/GPIO40 2
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 1 2 UMA_VARIBL (11,21)
+3VS 82 89 R1004 @ 0_0402_5%
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0# FSTCHG (41)
90 CHARGE_LED0# (35)
EC_SMB_CK2 BATT_CHGI_LED#/GPIO52 CAPS_LED#
91 CAPS_LED# (35)
EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED1#
R596 4.7K_0402_5%
(40) EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 CHARGE_LED1# (35)
EC_SMB_DA2 EC_SMB_DA1 78 93
(40) EC_SMB_DA1 EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON PWR_LED_SC# (35)
R600 4.7K_0402_5%
(6) EC_SMB_CK2 79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95 SYSON (31,38,43)
1 2 FAN_SPEED1 EC_SMB_DA2 80 121 1 2 VR_ON
(6) EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (47)
R592 10K_0402_5% 127 R991 0_0402_5%
AC_IN/GPIO59 ACIN (15,25,39)
1 2 SSD_DET#
R928 10K_0402_5%
1 2 MUTE_BTN# 6 100
(24) PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# EC_RSMRST# (24)
R929 10K_0402_5% 14 101
(24) PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# (24)
1 2 VOLUME_UP# EC_SMI# 15 102 EC_ON
(24) EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON (35)
R930 10K_0402_5% VOLUME_UP# 16 103 RB751V_SOD323
LID_SW#/GPIO0A EC_SWI#/GPXO06 CMOS_OFF# (32)
1 2 VOLUME_DOWN# VOLUME_DOWN# 17 104 SB_PWRGD_EC 1 2 SB_PWRGD
EC_SEL SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD (6,11,24)
R931 10K_0402_5% 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# (21) D8
1 2 DGPU_BTN# VGATE 19 GPIO 106 @
PANEL_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 BT_OFF# (31)
R932 10K_0402_5% 25 107
(21) PANEL_PWM FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 MUTE_BTN#
add at 8/13 (37) FAN_SPEED1 28
FAN_SPEED1/FANFB1/GPIO14 GPXO11
108 1 2 @ +3VS
DGPU_BTN# 29 R609 0_0402_5% R599 2.2K_0402_5%
EC_TX_P80_DATA FANFB2/GPIO15 Ver02 :change from 4.7K to 2.2K +3VS
(31) EC_TX_P80_DATA 30
EC_RX_P80_CLK EC_TX/GPIO16
(31) EC_RX_P80_CLK 31 110 VLDT_EN (38,44,45,46)
EC_SEL EC_RX/GPIO17 PM_SLP_S4#/GPXID1 ENBKL_R
1 2 (35) ON/OFF# 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 1 UMA@ 2 ENBKL (11)

2
R1005 10K_0402_5% 2 @ 1 34 114 R984 0_0402_5%
(6,23) H_PROCHOT_R# PWR_LED#/GPIO19 GPXID3 EC_THERM# EAPD (36)
@ (35) NUM_LED#
0_0402_5% R992 36
NUMLED#/GPIO1A GPI GPXID4
115 EC_THERM# (25)
R993
116 SUSP# 0_0402_5%
+5VS GPXID5 PBTN_OUT# SUSP# (18,31,38,41,44,46)
117 PBTN_OUT# (24) @
GPXID6 EC_PME#
118

1
TP_CLK XCLKI GPXID7
1 2 122 XCLK1 20mil
R605 4.7K_0402_5% XCLKO 123 124
TP_DATA XCLK0 V18R ENBKL_R 1 VGA@ 2
1 2 1 VGA_ENBKL (15)
AGND

R604 4.7K_0402_5% R985 0_0402_5%

GND
GND
GND
GND
GND

1
C743 D
1 2 SUSP# 4.7U_0805_10V4Z SUSP# 1 2 2 Q62
R590 100K_0402_5% KB926QFE0_LQFP128 2 R994 0_0402_5% G 2N7002_SOT23
11
24
35
94
113

69

1 @ 2 SYSON 1 1 @ S @

3
R589 100K_0402_5%
1

ECAGND

1 @ 2 KSO2 C741 C740 1

R696 @ 100K_0402_5% 27P_0402_50V8J 27P_0402_50V8J
OUT
IN

KSO3 2 2 C1030 VR_ON

1 2
R697 @ 100K_0402_5% 0.1U_0402_16V4Z
VOUTX 2 @
1 2
G3 state ICH_POK

2
R933 10K_0402_5%
NC

NC

1 2 VOUTY X1 R995
R934 10K_0402_5% 32.768K_1TJS125BJ4A421P D6 @ CH751H-40PT_SOD323-2 0_0402_5%
2

VGATE 1 2 SB_PWRGD
(47) VGATE SB_PWRGD (6,11,24) @
1 2 EC_SEL

1
R1006 10K_0402_5% D7 @ CH751H-40PT_SOD323-2
(42,43) SPOK 1 2

add at 8/13 05/25

+3VALW
1

2 VGA@ 1 EC_SMB_CK2
(15) VGA_SMB_CK2
0_0402_5% R997
(15) VGA_SMB_DA2
0_0402_5%
2 VGA@ 1
R998
EC_SMB_DA2 R593
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/23 Deciphered Date 2009/05 Title
CLOSE TO U6 @
BIOS & EC I/O Port
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 EC_PME# Size Document Number Rev
(30) LAN_WAKE# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R587 0_0402_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 33 of 49
 BIOS(SYS / EC / VGA)
www.bufanxiu.com
+5VS 11mA JP27
1 1
TP_CLK 2
(33) TP_CLK 2
TP_DATA 3
(33) TP_DATA SW/L 3
4
U52 SW/R 4
5 5
FSEL#SPICS# 1 8 6
FRD#SPI_SO CS# VCC SPI_HOLD# 6
2 DO HOLD# 7 7 GND
SPI_WP# 3 6 SPI_CLK_R 8
WP# CLK FWR#SPI_SI GND
4 GND DIO 5
ACES_85201-06051
MX25L2005CMI-12G SOP ME@
@

+5VS TP_DATA C560 1 2 @ 100P_0402_50V8J

+3VALW C512 1 2 0.1U_0402_16V4Z
TP_CLK C558 1 2 @ 100P_0402_50V8J
C559
+SPI_VCC
0.1U_0402_16V4Z
U38
FSEL#SPICS# 1 8
(33) FSEL#SPICS# CS# VCC SPI_HOLD#
2 7 4.7K_0402_5% 2 1 R204
(33) FRD#SPI_SO SO HOLD#
+3VALW R207 1 2 4.7K_0402_5% SPI_WP# 3 6 SPI_CLK_R 1 2 SPI_CLK (33)
WP# SCLK R208 0_0402_5% TP_CLK TP_DATA
4 5 FWR#SPI_SI (33)
GND SI
MX25L1605AM2C-12G_SO8

2
1
D40
R206 PJDLC05_SOT23-3
22_0402_5% @
@

2
C524
33P_0402_50V8K

1
@

6
5

6
5
2 4 2 4
SW/L SW/R
1 3 1 3

INT_KBD Conn. SW3

EVQPLHA15_4P
SW2
EVQPLHA15_4P
JP26
KSI1 1
KSI7 1 KSI[0..7]
2 KSI[0..7] (33)
KSI6 2
3 3
KSO9 4 KSO[0..15]
KSI4 4 KSO[0..15] (33)
5
KSI5 5
6
KSO0 6
7 7
KSI2 8
KSI3 8
9 9
KSO5 10
KSO1 10
11
KSI0 11
12
KSO2 12
13
KSO4 13
14
KSO7 14
15
KSO8 15
16 16
KSO6
KSO3
17
18
17
18
Kill Switch
KSO12 19
KSO13 19
20
KSO14 20
21
KSO11 21
22
KSO10 22 SW4
23 23
KSO15 24 2 1 3
24 +3VALW 3
R18 100K_0402_5%
2
(33) KILL_SW# 2
GND2
26 KILL_SW#
25
GND1
1 1
E-T_6905-E24N-01R
ME@ 1BS003-1211L_3P

KSO15 C448 1 2 100P_0402_50V8J KSO7 C440 1 2 100P_0402_50V8J

@ @
KSO14 C447 1 2 100P_0402_50V8J KSO6 C907 1 2 100P_0402_50V8J
@ @
KSO13 C446 1 2 100P_0402_50V8J KSO5 C905 1 2 100P_0402_50V8J
@ @
KSO12 C445 1
@
2 100P_0402_50V8J KSO4 C906 1
@
2 100P_0402_50V8J Lid Switch
KSI0 C451 1 2 100P_0402_50V8J KSO3 C903 1 2 100P_0402_50V8J
@ @
KSO11 C444 1 2 100P_0402_50V8J KSI4 C455 1 2 100P_0402_50V8J
@ @ 1 2 +VCC_LID R318 1 2 100K_0402_5%
+3VALW
KSO10 C443 1 2 100P_0402_50V8J KSO2 C904 1 2 100P_0402_50V8J R317 0_0402_5%
@ @

2
KSI1 C452 1 2 100P_0402_50V8J KSO1 C902 1 2 100P_0402_50V8J A3212ELHLT-T_SOT23W-3
@ @

VDD
KSI2 C453 1 2 100P_0402_50V8J KSO0 C901 1 2 100P_0402_50V8J 1
@ @ 3
KSO9 KSI5 OUTPUT LID_SW# (33)
C442 1 2 100P_0402_50V8J C456 1 2 100P_0402_50V8J C561
@ @ 0.1U_0402_16V4Z 2

GND
KSI3 C454 1 2 100P_0402_50V8J KSI6 C457 1 2 100P_0402_50V8J 2
@ @ C562
KSO8 C441 1 2 100P_0402_50V8J KSI7 C458 1 2 100P_0402_50V8J U39 10P_0402_50V8J

1
@ @ 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 34 of 49
 A B C D E

Power Button www.bufanxiu.com

ON/OFF switch
+5VS Switch Board Conn.

2
R14
0_0603_5% ME@
+3VALW ACES_85201-06051
TOP Side D10
8

1
ON/OFFBTN# GND
2 1 2 7 GND
1 J5 @ JOPEN 1
1 6 6

2
NOVO_BTN# 3 ON/OFFBTN# 5
R8 NOVO_BTN# 5
2 1 4 4
J6 @ JOPEN 3
100K_0402_5% PJSOT24C_SOT23-3 CAPS_LED# 3
(33) CAPS_LED# 2
@ NUM_LED# 2
Bottom Side (33) NUM_LED# 1

1
D3 1
2 JP33
ON/OFFBTN# ON/OFF# (33)
1
3 51_ON# (39)
DAN202UT106_SC70-3
done
Name change at 8/12

1
2
C897 D1

1000P_0402_25V8J RLZ20A_LL34
@1 @

2
1
D ON/OFFBTN#
EC_ON 2 Q1
(33) EC_ON NOVO_BTN#
G
2

S 2N7002_SOT23
3

0.1U_0402_25V6

0.1U_0402_25V6
R6
1 2
10K_0402_5%
2

C584

C589
2
1

@ 2 @ 1

remove C585 at 8/12

+3VALW

LED Green
2

R265 +5VALW +5VS

100K_0402_5%
D41
1

NOVO# 2
(33) NOVO#
1 NOVO_BTN#
51_ON# 3
(39) 51_ON#

DAN202UT106_SC70-3
LED2
3 3
2 1 BT@ BT_LED# (31)
1 2 2 1 R24
0_0402_5%
R249 300_0402_5% 2 1 WLAN_LED# (31)
R25 WLAN@
0_0402_5%
19-213A-T1D-CP2Q2HY-3T_WHITE

LED3

1 2 2 1 SATA_LED# (25)
R244 432_0402_1%

19-213A-T1D-CP2Q2HY-3T_WHITE
LED4

1 2 2 1 PWR_LED_SC# (33)
R246 432_0402_1%
LED5
19-213A-T1D-CP2Q2HY-3T_WHITE
Blue CHARGE_LED0#
1 2 2 1 CHARGE_LED0# (33)
R247 432_0402_1%
19-213A-T1D-CP2Q2HY-3T_WHITE

+3VALW 7.3mA
R245 LED6 Amber CHARGE_LED1#
1 2 2 1 CHARGE_LED1# (33)
499_0402_1%
S LED 19-217/S2C-FM2P1VY/3T 0603 ORANGE
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power BTN/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 35 of 49
A B C D E
 A B C D E F G H

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
www.bufanxiu.com HDA_RST_AUDIO#
EMI
HDA_SYNC_CODEC
Amplifier.
HDA_SDOUT_CODEC
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO). +3VS 1 2 HDA_BITCLK_AUDIO
0_0402_5% @ R121
An integrated 3.3 V to 1.8V Low-dropout

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
voltage regulator (LDO). 60mA 1 1 1 1 1 1 1

C399

C288

C279

C802

C801

C804

C803
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
1 +LDO_OUT_3.3V 1
+3VS 2 1 +VAUX_3.3
0_0402_5% R155 2 2 2 2 2 2 2

1U_0603_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 AVDD_3.3 pinis output of @ @ @ @

10U_0805_10V4Z

0.1U_0402_16V4Z

C702

C289

C395

C281
1 1 internal LDO. NOT connect
To suuport Wake-on-Jack or Wake-on-Ring, the CODEC

C392

C291
VAUX_3.3 & VDD_IO pins must be powerd by a rail that to external supply.
is not removed unless AC power is removed. 2 2 2 2
*DSH page42 has more detail. 2 2

Layout Note:Path from +5VS to LPW R_5.0

RPW R_5.0 must be very low
+3VS
0_0402_5%
2 1
R133 30mA resistance (<0.01 ohms)
+5VS
EMI EMI

1U_0603_10V4Z

0.1U_0402_16V4Z
1 1 10K only needed if supply to VAUX_3.3
1 R15 SPK_R1-_CONN

C700

C294
is removed during system re-start. 2 +5VS

10U_0805_10V4Z

0.1U_0402_16V4Z
1 1 SPK_R2+_CONN
0_0603_5% SPK_L1-_CONN

C394

C293

2200P_0402_50V7K
10U_0805_10V4Z

10U_0805_10V4Z

1000P_0402_25V8J
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2 SPK_L2+_CONN
1 1 1 1 2 2

C284

C280

C397

C396
10U_0805_10V4Z

0.1U_0402_16V4Z
1
2 2

C1034

C1035
10K_0402_5%
1 1

1000P_0402_25V8J

1000P_0402_25V8J

1000P_0402_25V8J

1000P_0402_25V8J
C398

C809
2 2 2 2 1 1 2 2 2 2
R291

C1036

C1037

C1038

C1039
0.1U_0402_16V4Z
2 2

18

29

27
28
26
1

3
7
2
U8 1 1 1 1

C292
2.5A

FILT_1.8

VAUX_3.3
DVDD_3.3

FILT_1.65

AVDD_3.3
VDD_IO

AVDD_5V
AVDD_HP
Please bypass caps very close to device.
12 2
LPWR_5.0
15
HDA_RST_AUDIO# RPWR_5.0
(24) HDA_RST_AUDIO# 9 17
RESET# CLASS-D_REF R484 1 2 5.11K_0402_1% +VAUX_3.3
HDA_BITCLK_AUDIO 5 Sense resistors must be
(24) HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_CODEC 8 36 R213 1 2 10K_0402_1% MIC_JD Port C connected same power
(24) HDA_SYNC_AUDIO SYNC SENSE_A
1 R336 2 33_0402_5% 6 R338 1 2 39.2K_0402_1% PLUG_IN Port A
(24) HDA_SDIN0 SDATA_IN that is used for VAUX_3.3
HDA_SDOUT_CODEC 4
(24) HDA_SDOUT_AUDIO SDATA_OUT
2 35 MIC_INR Internal MIC 2
PORTB_R MIC_INL
34
PORTB_L
33 +MICBIASB
PC_BEEP B_BIAS R321 2.2K_0402_5%
EAPD active low 10
PC_BEEP +MICBIASC
R322 2.2K_0402_5%
0=power down ex AMP 32 +MICBIASC
J8 C_BIAS C707 100_0402_1% EXT_MIC_R
1=power up ex AMP 31 1 2 2.2U_0603_10V7K R161
PORTC_R C705
2 1 30 1 2 2.2U_0603_10V7K EXT_MIC_L External MIC
2 1 0_0402_5% PORTC_L
(33) EAPD 1 2 R122 38 R162 100_0402_1%
@ JUMP_43X118 EC_MUTE# GPIO0/EAPD#
(33) EC_MUTE# 2 1 37
0_0402_5% R17 GPIO1/SPK_MUTE# R919 15_0402_5% HP_OUTR
23 1 2
PORTA_R R920 15_0402_5% HP_OUTL
22 1 2
PORTA_L

C282
40
DMIC_CLK Headphone
1
DMIC_1/2 NC
24 add at 8/12
1 2 25
0_0402_5% NC
39
SPK_L2+ NC
11
C290
1 2 Internal SPEAKER
SPK_L1- 13
LEFT+
LEFT-
AVEE
21
wide 20MIL
0_0402_5% 19 ACES_85204-0400N
SPK_R2+ FLY_P SPK_R1- L37 FBMA-L11-160808-121LMA30T SPK_R1-_CONN 4
16 20 1 2 1 2

10U_0805_10V4Z
0.1U_0402_16V4Z
C283 SPK_R1- RIGHT+ FLY_N C701 1U_0603_10V4Z SPK_R2+ L35 FBMA-L11-160808-121LMA30T SPK_R2+_CONN 3 4
14 1 1 1 2
RIGHT- SPK_L1- L36 FBMA-L11-160808-121LMA30T SPK_L1-_CONN 2 3

C286

C393
1 2 1 2
GND

0_0402_5% SPK_L2+ L34 1 2 FBMA-L11-160808-121LMA30T SPK_L2+_CONN 1 2

1
C278 CX20671-11Z_QFN40_6X6 2 2 JSPK1
41

1 2 ME@
0_0402_5%
R126
1 2 +MICBIASB
0_0402_5%
R124
1 2
1

0_0402_5% 220P_0402_50V7K 220P_0402_50V7K

R123 R343

2
1 2 4.7K_0402_5%
0_0402_5% C800 C799 Headphone

1
3 3
2

1
MIC1 0_0603_5%
1 C704 1 2 2.2U_0603_10V7K MIC_INR 1 2 R981 @ R316 @ R319
2 GNDA 1K_0402_5% 1K_0402_5%
GND GNDA C706 1 2 2.2U_0603_10V7K MIC_INL GNDA

2
WM-64PCY_2P @ GNDA
45@
GNDA JHP1
SM010022410 1
Audio Jack HP_OUTL
R584
1 2 PL-OUT
FBMA-L10-160808-121LMT
2
6
HP_OUTR 1SM010022410
2 PR-OUT 3
R586 FBMA-L10-160808-121LMT
PLUG_IN 4

2
R1007 FOX_JA6333L-B3S0-7F
+3VS 0_0402_5% ME@
PC Beep
1

1
R212
10K_0402_1%
EXT_MIC_L
SM010022410
EXT_MIC_L-2
Audio Jack
1 2
MIC IN
2

2 1C698 1 R583 FBMA-L10-160808-121LMT

1
1

1U_0603_10V4Z C826 @ C319

47P_0402_50V8J 10P_0402_50V8J
R214 2GNDA 2GNDA
10K_0402_1% SM010022410
C697 1U_0603_10V4Z EXT_MIC_R 1 2 EXT_MIC_R-2 JMIC1
2

1 2PC_BEEP1 2 1 PC_BEEP 1 R585 FBMA-L10-160808-121LMT

1 1
R324 20K_0402_5% 2
C807 C321 6
47P_0402_50V8J 10P_0402_50V8J
EC Beep 3
1

C699 C 2GNDA 2GNDA

@
R488
2

(33) BEEP# 2 1 1 2 2 Q4 MIC_JD 4

4 1 B 2SC2411KT146_SOT23-3 R325 4
560_0402_5% E 20K_0402_5% 1 GNDA 5
3

C285 1U_0603_10V4Z
@ 0.1U_0402_16V4Z @ 10P_0402_50V8J C320 FOX_JA6333L-B3S0-7F
1

2 @ ME@
2
C703
R487 GNDA
(24) SB_SPKR 2 1 1 2
1

1U_0603_10V4Z 560_0402_5%
ICH Beep D5 @
R307
RB751V_SOD323
Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
HD Audio Codec ALC888S-VC
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 36 of 49
A B C D E F G H
 www.bufanxiu.com
FAN1 Conn
+5VS
C908 10U_0805_10V4Z +5VS
1 2

1
U31 D11
1 8 1SS355_SOD323-2
VEN GND @
2 VIN GND 7
+VCC_FAN1 3 6

2
VO GND D12
(33) EN_FAN1 2 1 4 5
R62 1K_0402_5% VSET GND
1 2
1 APL5605KI-TRL SOP 8P @
BAS16_SOT23-3
C350 C121
0.1U_0402_16V4Z 10U_0805_10V4Z
2 1 2
+3VS C119
1000P_0402_25V8J
1 2

1
R450
10K_0402_5%
40mil
JP13 H21 H10 H22 H23 H5
2

+VCC_FAN1 H_3P0 H_3P0 H_3P3 H_3P2 H_3P0

1
(33) FAN_SPEED1 2
3
1

1
C670 ACES_85205-03001
1000P_0402_25V8J ME@
2 @ @ @ @ @
H7 H14 H13 H9 H29
H_4P2 H_4P2 H_4P2 H_4P2 H_3p2

1
@ @ @ @ @
H20 H12 H4 H3 H2 H15 H1 H16 H17 H24 H25 H26 H27 H28
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_2P8 H_3P0 H_3P6N H_3P0 H_1p4x0p5
H_1p4x0p5
H_1p4x0p5
H_1p4x0p5
H_1p4x0p5

1
@ @ @ @ @ @ @ @ @ @ @ @ @ @

H18
H_3P6X6P1N

1
@

FD2 FD3 FD1 FD4

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

@ @ @ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 37 of 49
 A B C D E

www.bufanxiu.com
+5VALW

+5VALW TO +5VS +1.2VALW TO +1.2V_HT

2
+5VALW +5VS R169
4.305A +1.2VALW +1.2V_HT 100K_0402_5%
U34 3.265A
8 1 U37

1
D S
7 2 8 1
D S D S

2
6 3 1 1 DVT 7 2 SYSON#
D S D S (43) SYSON#

2
1 1 5 4 C576 R238 6 3 1 1
D G D S

1
C571 C570 470_0603_5% C470 R197 D
1 5 D G 4
SI4800BDY_SO8 10U_0805_10V4Z C573 @ R202 C509 470_0603_5% SYSON 2 Q21
2 2 (31,33,43) SYSON
10U_0805_10V4Z 1K_0402_5% SI4800BDY_SO8 10U_0805_10V4Z C462 @ G 2N7002_SOT23

1
1 2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 S 1

3
1
2 1U_0402_6.3V4Z

2
1
D 10U_0805_10V4Z R174

1
D
2 2 R921 1 SUSP 100K_0402_5%
G 0_0402_5% 2 VLDT_EN# @
B+ 2 1 5VS_GATE 2 R943 1 Q28 S 1 @ G

2
R239 0_0402_5% 2N7002_SOT23 C1020 2 1 1.2VS_GATE S Q22
B+

3
49.9K_0402_1% 1 @ @ R196 2N7002_SOT23
1

D C577 0.1U_0603_25V7K 200K_0402_5% @ +5VALW

SUSP 2
2 1

1
Q29G 0.1U_0603_25V7K D C506

2
2N7002_SOT23 S 2 VLDT_EN# 2
3

Q23G 0.1U_0603_25V7K R242

2N7002_SOT23 S 2 1 2 100K_0402_5%

3
C1028 @ 220P_0402_50V7K
add at 8/12

1
SUSP
SUSP

1
D
2 Q30
(18,31,33,41,44,46) SUSP#
G 2N7002_SOT23
S

3
1
+3VALW TO +3VS
R248
+3VALW +3VS 10K_0402_5%
4.121A @

2
U33
8 D S 1
7 2
D S
6
D S
3 1 1 2 +5VALW
2 C572 R243 2
1 1 5 D G 4
C575 C574 470_0603_5%

2
SI4800BDY_SO8 10U_0805_10V4Z C569 @
10U_0805_10V4Z 2 2 R167
1 1

2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 100K_0402_5%
D
2 SUSP

1
G VLDT_EN#
(18) VLDT_EN#
Q27 S
3

2 1 3VS_GATE 2N7002_SOT23
B+

1
R982 @ D
100K_0402_5% 1 2 Q3
(33,44,45,46) VLDT_EN
1

D C1024 G 2N7002_SOT23
SUSP 2 S

3
1
Q61G 0.1U_0603_25V7K
2N7002_SOT23 S 2
3

R290
10K_0402_5%

2
+1.8V to +1.8VS
+1.8V +1.8VS +1.8V +1.8VS_VGA
6.988A 4.556A
U36 U32
8 D S 1 8 D S 1
7 2 7 2 1 1
D S D S
2

2
6 3 1 1 6 3 C367
D S C712 R570 D S R115
1 1 5 4 1 1 5 4
C714 C710 D G 470_0603_5% C565 C563 D G 10U_0805_10V4Z C368 470_0603_5%
SI4800BDY_SO8 10U_0805_10V4Z C709 @ SI4800BDY_SO8 VGA@ 2 2 @
3 2 2 VGA@ VGA@ VGA@ 1U_0402_6.3V4Z 3
1

1
2 2 1U_0402_6.3V4Z 2 2 VGA@
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
1

1
D D
2 SUSP 2 1.8VS_VGE_EN
G VGA@ G
2 1 1.8VS_GATE S Q46 2 1 1.8VS_VGA_GATE S Q14
B+ B+
3

3
R271 2N7002_SOT23 R154 2N7002_SOT23
150K_0402_5% @ @ 200K_0402_5% 1 @
1 VLDT_EN#1 2
1

D C711 R924 0_0402_5% D C564

SUSP 2 SUSP 1 2 1.8VS_VGE_EN
2 0.1U_0603_25V7K
G Q47 0.1U_0603_25V7K R407 20K_0402_5% G 2 VGA@
S 2N7002_SOT23 2 VGA@ S Q19
3

2N7002_SOT23
1 VGA@

C852
0.1U_0402_16V4Z
VGA@2

add at 8/13

+1.5VS_UMA +2.5VS +0.9V +1.8V +VGA_PCIE

2

4 R241 R153 R112 R113 R925 4

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @ @ @ @
@
1

1 2 VLDT_EN#
R926 0_0402_5%
1

D D D D D
SUSP SUSP SYSON# SYSON# SUSP
G
2
G
2
G
2
G
2
G
2 1
R927@
2
0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
S Q26 S Q18 S Q11 S Q12 S Q60 Issued Date 2008/10/06 2009/10/06 Title
Deciphered Date
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

@ @ @ @ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
add at 8/13 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 38 of 49
A B C D E
 A B C D

DC030006J00 www.bufanxiu.com
VIN
ACIN
Precharge detector
Min. typ. Max.
BATT ONLY
Precharge detector
Min. typ. Max.
PF101 PL101 L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
7A_24VDC_429007.W RML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V
4

3 3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
@ 0.1U_0603_25V7K

@ 0.1U_0603_25V7K
1
2 2 1

PR101

1
1 1K_1206_5%
1 PQ101
1 2

PC104
TP0610K-T1-E3_SOT23-3

2
@ 4602-Q04C-09R 4P P2.5

PC101

PC102

PC103

PC105

PC106
PR102
JDCIN PD101 1K_1206_5%
VIN 2 1 1 2 3 1

LL4148_LL34-2 PR103
1K_1206_5%
1 2

100K_0402_1%
1

1
100K_0402_1%
PR104

PR105

2
Vin Detector

2
Min. typ. Max.
L-->H 17.430V 17.901V 18.384V

100K_0402_1%
H-->L 16.976V 17.262V 17.728V

PR106
1
PR107
1M_0402_1%

1 2
1 2
VINDE-2 VIN 2
VS (33,41) ACOFF PQ102
VIN
DTC115EUA_SC70-3
B+
2 2
0.01U_0402_25V7K

10K_0805_5%
2

3
1
PQ103
1

PC107

PR109
PR108 PR110 DTC115EUA_SC70-3
84.5K_0402_1% 10K_0402_1%
2

3
1 2

2
PR111 ACIN (15,25,33)
2

22K_0402_1%
VINDE-1 1 2 3
P

+ PACIN PR113
1
0.068U_0603_16V7K

O PACIN (41)
VINDE-3 2 -
VL 2.2M_0402_5%
G
1

20K_0402_1%

10K_0402_5%
PU101A
0.1U_0402_16V7K

2 1
1

1
LM393DG_SO8
4
PC108

PR112

PC109

PR114
PD102
2

LLZ4V3B_LL34-2

499K_0402_1%
2

1
PR115
2

PR116
10K_0402_5%

100K_0402_1%
2 1 RTCVREF 3.3V

1
PR117

2
PD103

8
RB715F_SOT323-3
(40,42) MAINPWON 2 5

P
+
VIN 1 7 O

205K_0402_1%

499K_0402_1%
(41) ACON 3 6

0.01U_0402_25V7K
-

1
PU101B

1
PR118

PR119

PC112
LM393DG_SO8

1000P_0402_50V7K
4
2

1
3 3

PC111
PD104

0.1U_0603_25V7K

2
LL4148_LL34-2

PRG++ 2

2
1

PC113
PD105
1

LL4148_LL34-2 51ON-1

2
BATT+ 2 1
1

PQ105
PR121 PR122 PR124 SSM3K7002F_SC59-3 PR125

1
PQ104 68_1206_5% 68_1206_5% 10K_0402_5% D 47K_0402_5%
TP0610K-T1-E3_SOT23-3 2 1 2 2 1
PR123 RTCVREF G PACIN (41)
2

1
200_0603_5% S

3
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

2 +5VALW
2

1
PC114

PR126 PC115
100K_0402_1% 0.1U_0603_25V7K
1

PR127 PQ106
2

3
22K_0402_1% DTC115EUA_SC70-3
1 2 51ON-3
(35) 51_ON# - JRTC + PR129
560_0603_5%
2 1 1 2 +RTCBATT

RTCVREF PD106
1

@ MAXEL_ML1220T10 1 2
PR128 +CHGRTC
PU102 200_0603_5% RB751V-40_SOD323-2
4 +CHGRTC PR130 G920AT24U_SOT89-3 4

560_0603_5% 3.3V
RTC Battery
2

1 2 3 OUT IN 2CHGRTCIN
1

GND PC117
PC116 1U_0805_25V4Z
10U_0603_6.3V6M 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 39 of 49
A B C D
 A B C D

www.bufanxiu.com

1 1

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
VMB2 VMB Recovery at 56 degree C
PF201 PL201 VS
JBATT 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2 VL

0.01U_0402_25V7K
1 BATT+ VL
2 2
3 EC_SMCA
3

PC205
2
4 EC_SMDA 2

2
5 5

1
6 PR202

2
6
1

1
7 PC201 PC202 47K_0402_1%
7 0.01U_0402_25V7K
100_0402_1%

100_0402_1%

8 1000P_0402_50V7K PC207 PR203

MAINPW ON (39,42)

2
GND PH201 47K_0402_1%
9

1
GND 100K_0402_1%_TSM0B104F4251RZ @ 0.01U_0402_25V7K TM-2 1 2
PR204

PR206

TYCO_1775789-1
2

2
@ PR205

8
13.7K_0402_1%

1
TM-1 D
1 2 3

P
+ TM-3 PQ201
O 1 2
TM_REF1 2 G SSM3K7002FU_SC70-3
-

G
PU201A S

3
LM393DG_SO8

4
EC_SMB_CK1 (33)

1000P_0402_50V7K
15.4K_0402_1%
@ 0.01U_0402_25V7K

1
0.22U_0603_25V7K
1

1
PC206

PR207
EC_SMB_DA1 (33) 2 1 VL

PC203

PC204
PR208

1
1 2 +3VALW 100K_0402_1%

2
PR209
6.49K_0402_1% PR210
100K_0402_1%

8
2
1 2 A/D 5

P
BATT_TEMP (33) +
PR211 7
10K_0402_5% O
6 -

G
PU201B
LM393DG_SO8

4
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 40 of 49
A B C D
 5 4 3 2 1

PQ301
FDS6675BZ_SO8
P2
PQ302
FDS6675BZ_SO8
P3
www.bufanxiu.com B+

PR302
VIN 8
7
1
2
1
2
8
7 0.15_1206_1% CHG_B+
6 3 3 6 PJ301
PQ303
5 5 1 4 2 2 1 1
FDS6675BZ_SO8

470P_0603_50V8J
2 3 @ JUMP_43X118 1 8

1
47K_0402_5%

2 7
1

PC302
D 3 6 D

2200P_0402_50V7K
PR301

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
5

2
DTA144EUA_SC70-3

200K_0402_1%
0.1U_0603_25V7K

PC305

4
1

PC306

PC303

PC304
CSIN
2

PC301

PR303
PQ304 CSIP

1
PR304
47K_0402_1%

2
2 1 2

2
VIN
1

2
PD301 PR305 3 ACOFF
1

RB751V-40TE17_SOD323-2 10K_0402_1% 1
1 2 6251_VDD 2
2 PR308

2.2U_0603_6.3V6K

1 1
PC307
PQ305 PR306 PD302 200K_0402_1%

1
10K_0402_1% RB715F_SOT323-3 1 2 VIN
DTC115EUA_SC70-3 2 1 PU301 PC309
(33) FSTCHG 0.1U_0603_25V7K
3

2
1 2 1 24 6251_DCIN2 1 PQ306
VDD DCIN

1
PC308 DTC115EUA_SC70-3

100K_0402_1%
2
PQ307 0.1U_0402_16V7K
1

D 2N7002KW _SOT323-3

PR307
150K_0402_1%

2 ACSET ACPRN 23
PR309

2 PR310

SIS412DN-T1-GE3_PAK1212-8
G 20_0402_5%

0.1U_0603_25V7K
2

3
5

1
6251_EN CSON D
S 3 22 1 2
3

EN CSON

1
PC311
PC310 2 PACIN
2

0.047U_0402_16V7K G
CELLS 4 21 1 2 CSOP S

3
CELLS CSOP

PQ308
PR311 PQ309
C PC312 6800P_0402_25V7K 20_0402_5% 2N7002KW _SOT323-3 C
4
PR313 PQ310 1 2 5 20 2 1
ICOMP CSIN
1

2
3K_0402_1% D 2N7002KW _SOT323-3 PR312
PACIN 1 2 2 PC314 PR314 6.81K_0402_1% PC313 20_0402_5%
(39) PACIN
G 1 2 1 2 6 19 0.1U_0402_16V7K
1 2 PL301 PR317

3
2
1
VCOMP CSIP PR315 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
S
3

0.01U_0402_25V7K 1 2 2.2_0402_5% BATT+

PC315 1 2 7 18 LX_CHG 1 2 CHG
1 4
@ 100P_0402_50V8J PR316 ICM PHASE
(39) ACON

5
(33) ADP_I 100_0402_1% 2 3

SI7716ADN-T1-GE3 _PAK1212-8

1
6251_VREF DH_CHG

@ 4.7_1206_5%
8 VREF UGATE 17
1

PR319
PQ311 PR318 1 2 PR320 PC317
DTC115EUA_SC70-3 154K_0402_1% PC316 0_0402_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ312
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1
(33) IREF CHLIM BOOT

PC318
PR321 4

1
PC319

PC320
ACOFF 2 16.9K_0402_1% PD303
0.01U_0402_25V7K

(33,39) ACOFF
6251_VREF 1 2 10 15 6251_VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1
PC321

PR322 26251_VDD

@ 680P_0603_50V7K
1

3
2
1
1

PC322
100K_0402_1% 11 14 DL_CHG
3

2
VADJ LGATE

1
PR324 PR323
2

3.9K_0402_1% 4.7_0402_5%
2

12 13 PC323

2
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24
PR325
CHGVADJ=(Vcell-4)/0.10627 Connect to EC A/D Pin. 15.4K_0402_1%
Vcell CHGVADJ (33) CHGVADJ
1 2

B
4V 0V B
1

6251_VDD 6251_VDD
4.2V 1.882V PR326
UMA CP mode 31.6K_0402_1% VMB2
4.35V 3.2935V

2
Vaclim=2.39*(1.4K/(1.4K+13.7K))=0.2376V
PR327 PR328
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
2

1
100K_0402_1% 100K_0402_1%
CC=0.25A~3A where Vaclim=0.2376V, Iinput=2.75A
VS PR329

1
IREF=1.016*Icharge @ 340K_0402_1% CELLS

3
IREF=0.254V~3.048V DIS CP mode

@0.01U_0402_25V7K
LI-3S :13.5V----BATT-OVP=1.5012V
VCHLIM need over 95mV Vaclim=2.39*(3.9K/(3.9K+16.9K))=0.478V PR330

PC324
BATT-OVP=0.1112*VMB @ 0_0402_5% 2 5 2 1
Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05)

1
VS PR331

2
where Vaclim=0.478V, Iinput=4A Per cell=3.5V PR332 0_0402_5%

4
@ 499K_0402_1% (33) BATT_SEL_EC
PQ314 TP0610K-T1-E3_SOT23-3 PR333 PQ313A PQ313B

2
8

8
10_0603_5% PU302B PR334 PU302A 2N7002KDW -2N_SOT363-6 2N7002KDW -2N_SOT363-6
3 1 1 2 6251_DCIN @ LM358DT_SO8 5 @ 10K_0402_1% @ LM358DT_SO8 3
P

P
P3 7 0
+
1 2 1 0
+
(33) BATT_OVP
1
100K_0402_1%

- 6 - 2
G

@0.01U_0402_25V7K
1
PR335

1
PR336
@ 105K_0402_1%
2

PR337
2

2
PC325
2 1

2
A 100K_0402_1% A
1

PQ315
DTC115EUA_SC70-3 2 FSTCHG
2 1
FSTCHG (33)
3 SUSP# Security Classification Compal Secret Data Compal Electronics, Inc.
SUSP# (18,31,33,38,44,46) 2007/6/22 2008/6/22 Title
Issued Date Deciphered Date
PD304 CHARGER
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RB715F_SOT323-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 41 of 49

5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com ISL6237_B+
ISL6237_B+
B+
PJ401 PR401
@ JUMP_43X118 0_0402_5%
2 2 1 1 1 2

330P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
D D

1
PC405

PC423

PC401

PC403

PC406

PC422
5

PC404
1U_0603_10V6K
VL

2
2
2

PC408
PC407
PQ401 0.1U_0603_25V7K 4

4.7U_0805_6.3V6K
3/5V_VCC
1

1
3/5V_VIN
4 SIS412DN-T1-GE3_PAK1212-8

PC409
PQ402 +5VALWP

2
SIS412DN-T1-GE3_PAK1212-8

3
2
1
PL402

1
2
3
PL401 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PU401 PC410 2 1
1 2 1U_0603_10V6K

VIN

V5FILT

LDO
+3VALWP 33 19 1 2
TP V5DRV

1
1

5
UG3 26 15 HG5
PR402 DRVH2 DRVH1 PR404
0_0402_5%

4.7_1206_5% BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 4.7_1206_5% 1

VBST2 VBST1
2

PR403 PR405

15V_SNB
1

2
2

2
+
PR406

2.2_0603_5% 2.2_0603_5% PC413

@ 61.9K_0402_1%
4

13V_SNB
2
+ 4 PC411 <BOM Structure> 220U_6.3V_M

2
PC421 0.1U_0603_25V7K

1
2

PR407
220U_6.3V_M SW 3 25 16 SW 5
1

2 PC414 LL2 LL1 PC412

3
2
1
330P_0402_50V7K 0.1U_0603_25V7K PC415

1
2
3

2
2 LG3 23 18 LG5 330P_0402_50V7K

1
PQ403 DRVL2 DRVL1
10K_0402_1%

SI7716ADN-T1-GE3_PAK1212-8
2

PGND 22

2
C C
PR408

FB3 30 PQ404
VOUT2

PR409
0_0402_5%
SI7716ADN-T1-GE3_PAK1212-8
VOUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 VREF2
PC416
0.22U_0603_25V7K 9
VSW
8 LDOREFIN PR410
PD401 29 5V_SKIP 2 1 VL
SKIPSEL @ 0_0402_5%
VL
1 2

100K_0402_1%
1
RB751V-40_SOD323-2 1 PR411 2

PR422
20 28 0_0402_5%
PR412 NC PGOOD2 2VREF_ISL6237
2 PR421 1
VS PD402 100K_0402_1% @ 0_0402_5%
1 2 EN_LDO-1 1 2 EN_LDO 4 13

2
EN_LDO PGOOD1
SPOK (33,43)
2

LLZ5V1B_LL34-2
200K_0402_1%

2
PR413

PC417 3/5V_EN1 14 12 ILM1 2 1

0.22U_0603_25V7K EN1 TRIP1 PR414
301K_0402_1%

TONSE
VREF3
1

3/5V_EN2 27 31 ILIM2 2 1

GND
1

EN2 TRIP2
2 PR415
SN0806081RHBR_QFN32_5X5 301K_0402_1%

21
B VL B
PD403
806K_0603_1%

13/5V_NC
2

1 2 PR416

13/5V_TON
PR417

0_0402_5%
1

RB751V-40_SOD323-2 PR419 1U_0603_10V6K

PC418

@ 47K_0402_1%
2VREF_ISL6237

PR418
1

2 1 1 2
2

0_0402_5% PR420
0.047U_0402_16V7K

0.047U_0402_16V7K

MAINPW ON (39,40) 0_0402_5% PJ402

1

+3VALWP 2 1 +3VALW
2

2 1
PC419

PC420

@ JUMP_43X118
2

2VREF_ISL6237

@ PJ403
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/01/06 2010/01/06
Issued Date Deciphered Date Title
3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 42 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com 1.2V_IN 2
PJ501
2 1 1 B+
@ JUMP_43X118

5
6
7
8

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6
1

1
PQ501

PC502

PC503

PC504
PR502 SI4686DY-T1-E3_SO8

2
240K_0402_1% 4
1.2V_TON 1 2
PR501 PR503
D PC505 D
0_0402_5% 0_0603_5%
1 2 1.2V_EN BST_1.2V 1 2BST_1.2V-1
1 2
(33,42) SPOK

3
2
1
0.1U_0603_25V7K

1
PL501

15

14
1
PC501 1.8UH_SIL104R-1R8PF_9.5A_30%
@0.01U_0402_25V7K 1 2

EN_PSV

TP

VBST
+1.2VALW P

220U_B2_2.5VM_R15M
1
2 13 UG_1.2V
TON DRVH
PR505 3 12 1.2V_SW PR504
VOUT LL

5
6
7
8
100_0603_1% 4.7_1206_5%

10U_0603_6.3V6M
1
+5VALW 1 2 1.2V_V5FILT 4 11 1.2V_TRIP
1 2 +5VALW

2
V5FILT TRIP

1
+

PC506
PR506 PQ502

1.2V_SNB
1.2V_FB 5 10 10K_0402_1%
+3VALW VFB V5DRV

PC507
SI4634DY-T1-E3_SO8

2
1
LG_1.2V 2
6 PGOOD DRVL 9 4

PGND
PC508

GND
2
4.7U_0603_6.3V6K PC509
2

1
@ 47P_0402_50V8J PR507
1 2 100K_0402_1% PC510 PC511

3
2
1
PU501 4.7U_0805_6.3V6K 680P_0402_50V7K

2
TPS51117RGYR_QFN14_3.5x3.5

1
1.2V_PW ROK
PR508
13.7K_0402_1%
1 2
1

PR509 PJ502
C 20.5K_0402_1% 1.8V_IN C
2 2 1 1 B+
2

@
JUMP_43X79

5
6
7
8

@ 10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6
1

1
PQ503
PR522

PC512

PC513

PC514

PC515
@ 0_0402_5% PR510 SI4686DY-T1-E3_SO8

2
1 2 240K_0402_1% 4
(6) VDDIO
1.8V_TON 1 2
PR511
0_0402_5%
1 2 1.8V_EN BST_1.8V 1 2BST_1.8V-1
1 2
(31,33,38) SYSON

3
2
1
PR512 PC516
2.2_0603_5% 0.1U_0603_25V7K
1

PL502

15

14
1
PC517 1.8UH_SIL104R-1R8PF_9.5A_30%
@0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.8VP
2

1
2 13 UG_1.8V
TON DRVH
PR514 3 12 1.8V_SW PR513
VOUT LL

5
6
7
8
100_0603_1% 4.7_1206_5%

220U_6.3V_M

10U_0603_6.3V6M
1
+5VALW 1 2 1.8V_V5FILT 4 11 1.8V_TRIP
1 2 +5VALW

1.8V_SNB 2
V5FILT TRIP

1
+

PC518
PR515 PQ504
1.8V_FB 5 10 8.45K_0402_1%
VFB V5DRV

PC519
SI4634DY-T1-E3_SO8

2
1

LG_1.8V 2
1 2 6 PGOOD DRVL 9 4
PGND

PC520
GND

4.7U_0603_6.3V6K PC521 PR516

2

1
@ 47P_0402_50V8J @ 100K_0402_1%
B 1 2 PC522 PC523 PC524 B
7

3
2
1
@0.1U_0402_16V7K PU502 4.7U_0805_6.3V6K 820P_0402_25V7
2

2
TPS51117RGYR_QFN14_3.5x3.5
1.8V_PGOOD
PR517
31.6K_0402_1%
1 2
1

PR518
22.1K_0402_1%
2

+1.8VP PJ503
+1.2VALWP 2 2 1 1 +1.2VALW
@ JUMP_43X118
1

PJ504
1

@ JUMP_43X79
2

PJ505
PU503 2 1
+1.8VP +1.8V
2

0.9V_IN 2 1
1 VIN VCNTL 6 +3VALW
@ JUMP_43X118
2 GND NC 5
1

PC525
1

4.7U_0805_6.3V6K 3 7 PC526
PR519 VREF NC 1U_0402_6.3V6K
2

1K_0402_1% 4 8 PJ506
VOUT NC
A
+0.9VP 2 2 1 1 +0.9V A
9
2

TP @ JUMP_43X79
0.9V_REF G2992F1U_SO8
1

PR520 +0.9VP
1

@ 0_0402_5% D PR521
1 20.9V_EN 2 1K_0402_1% PC527
(38) SYSON# Security Classification Compal Secret Data Compal Electronics, Inc.
1

G 0.1U_0402_16V7K
2
1

S PQ505 PC529
Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title
3

PC528 @ SSM3K7002FU_SC70-3 10U_0603_6.3V6M

1.2V/1.8V/0.9V
2

@ 0.1U_0402_16V7K
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 43 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com 1.5V_IN 2
PJ601
2 1 1 B+

@
JUMP_43X79

@ 10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
PQ601

0.1U_0402_25V6
1

1
SIS412DN-T1-GE3_PAK1212-8

PC602

PC603

PC604

PC605
PR602

2
240K_0402_1% 4
1.5V_TON 1 2
PR601
D
0_0402_5% D
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2
(18,31,33,38,41,46) SUSP#

3
2
1
PR603 PC606
0_0603_5% 0.1U_0603_25V7K

1
PL601

15

14
1
PC601 2.2UH_PCMC063T-2R2MN_8A_20% PJ602
@0.1U_0402_16V7K 1 2 2 1

EN_PSV

TP

VBST
+1.5VSP +1.5VSP +1.5VS

2
2 1

220U_B2_2.5VM_R15M
1
2 13 UG_1.5V @ JUMP_43X79
TON DRVH
PR605 3 12 1.5V_SW PR604
VOUT LL

5
100_0603_1% @ 4.7_1206_5%

10U_0603_6.3V6M
1
+5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW

1.5V_SNB 2
V5FILT TRIP

1
+

PC607
PR606
1.5V_FB 5 10 17.8K_0402_1%
VFB V5DRV

PC608
2
1

LG_1.5V 2
1 2 6 PGOOD DRVL 9 4

PGND
PC609

GND
4.7U_0603_6.3V6K PC610 PR607
2

1
@ 47P_0402_50V8J @ 100K_0402_1%
1 2 PC611 PC612 PC613

3
2
1
@0.1U_0402_16V7K PU601 4.7U_0805_6.3V6K @ 470P_0402_50V7K

2
TPS51117RGYR_QFN14_3.5x3.5
1.5V_PGOOD PQ602
PR608 SI7716ADN-T1-GE3_PAK1212-8
21K_0402_1%
1 2
1

PR609
21K_0402_1%
C C
2

+3VS
2

PR610
PR622 PR611 205K_0402_1% PJ603
@ 0_0402_5% @ 10K_0402_5% VGA_TON 1 2 VGA_IN 2 1 B+
2 1

10U_1206_25V6M

10U_1206_25V6M
(33,38,45,46) VLDT_EN 2 1
PD601 @ JUMP_43X79
1

5
6
7
8
PR612 1SS355_SOD323-2

1
PC614

PC615
1 2 VGA_EN 1 2 +5VALW
(18,31,33,38,41,46) SUSP#
1

100K_0402_1% PQ603

2
PC616 PR613
PC617
@ 0.1U_0402_16V7K 0_0603_5% 4
2

BST_VGA 1 2BST_VGA-1
1 2 SI4686DY-T1-E3_SO8

0.1U_0603_25V7K
PL602

15

14

3
2
1
1
0.88UH +-20% PCMC104T-R88MN 20A
1 2
EN_PSV

TP

VBST
+VGA_COREP
2 13 UG_VGA
TON DRVH

4.7_1206_5%
PR616 3 12 SW _VGA
VOUT LL

5
6
7
8

5
6
7
8

PR615
100_0603_1%

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
1

330U_D2_2.5VY_R15M
B 1 2 VGA_V5FILT 4 11 VGA_TRIP
1 2 +5VALW B

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8
+5VALW V5FILT TRIP

1
+

PC618

PC620

PC621

PC622
PR617

1VGA_SNB
2
+3VS VGA_FB 5 10 9.1K_0402_1%
VFB V5DRV
@ 100K_0402_1%

1 2

2
2

LG_VGA 2
6 PGOOD DRVL 9 4 4
PGND

PQ604

PQ605
PR619

PC619
GND

4.7U_0603_6.3V6K

680P_0402_50V7K
1

PC624
PC623
1

3
2
1

3
2
1

2
(14) VGA_PW ROK PU602 4.7U_0805_6.3V6K

2
TPS51117RGYR_QFN14_3.5x3.5
2 1 PC626
@ 47P_0402_50V8J
PC625 1 2
@ 0.1U_0402_16V7K
1 2
PR621
2.67K_0402_1%
1 2
PR623
2

10K_0402_1%
+3VALW
+3VALW PR624 M93
20K_0402_1%
1

10K_0402_1%

1PWRSEL-2
1
PR625

VGA_PWRSEL Core Voltage Level PJ604

1

@ 10K_0402_1%

+VGA_COREP 2 2 1 1 +VGA_CORE
PR626

0 1.2 V @ JUMP_43X118
2

PR627 D
2 1PW RSEL-1 2
2

PQ607 10K_0402_1% G 1 0.95 V PJ605

2N7002KW_SOT323-3

A A
1

D
@ 10K_0402_1%

PR628 S PQ606 2 1
3

2 1
1
PR629

2 1 2 2N7002KW _SOT323-3
(15) VGA_PWRSEL 10K_0402_1% G @ JUMP_43X118
@ 10K_0402_1%

S PC627
3

2
1

0.022U_0402_16V7K
2
PR630

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 44 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com
PJ701
NB_CORE_IN 2 1 B+
2 1
D D
@ JUMP_43X118

5
6
7
8

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6
1

1
PQ701

PC702

PC703

PC704

PC705
PR702 SI4686DY-T1-E3_SO8

2
240K_0402_1% 4
NB_CORE_TON 1 2
PR701
34.8K_0402_1%
1 2 NB_CORE_EN BST_NB_CORE
1 2BST_NB_CORE-1
1 2
(33,38,44,46) VLDT_EN

3
2
1
PR703 PC706
0_0603_5% 0.1U_0603_25V7K

1
PL701

15

14
1
PC701 1.8UH_SIL104R-1R8PF_9.5A_30%
0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+NB_COREP

1
2 13 UG_NB_CORE
TON DRVH

220U_B2_2.5VM_R15M
PR705 3 12 NB_CORE_SW PR704
VOUT LL

5
6
7
8
100_0603_1% @ 4.7_1206_5%

NB_CORE_SNB

10U_0603_6.3V6M
1
POWER_SEL +5VALW 1 2 NB_CORE_V5FILT4 11 NB_CORE_TRIP
1 2 +5VALW

2
V5FILT TRIP

1
+

PC707
PR706 PQ702
NB_CORE_FB 5 10 10K_0402_1%
VFB V5DRV

PC708
HIGH 1.0V SI4634DY-T1-E3_SO8

2
1

LG_NB_CORE 2
1 2 6 PGOOD DRVL 9 4

PGND
PC709

GND
LOW 1.1V 4.7U_0603_6.3V6K PC710 PR707
2

1
@ 47P_0402_50V8J @ 100K_0402_1%
1 2 PC711 PC712 PC713

3
2
1
@0.1U_0402_16V7K PU701 4.7U_0805_6.3V6K @ 470P_0402_50V7K

2
C TPS51117RGYR_QFN14_3.5x3.5 C

NB_CORE_PGOOD
PR708
+5VALW 31.6K_0402_1%
1 2
1

10K_0402_1%

1
PR709

PJ702
+NB_COREP 2 2 1 1 +NB_CORE
PR710 PR711
261K_0402_1% 91K_0402_1% @ JUMP_43X118
2

11

PR712 D
2 1PW RSEL-1
2 PJ703
PQ704 10K_0402_1% G
2N7002KW_SOT323-3

2 2 1 1
1

PR713 D
S PQ703
3

2 1 2 2N7002KW _SOT323-3 @ JUMP_43X118

0_0402_5% G
1

1
PC714

0.01U_0402_25V7K

S
11) POWER_SEL
3

PC715
2

0.1U_0402_25V6

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+NB_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 45 of 49
5 4 3 2 1
 5 4 3 2 1

www.bufanxiu.com +1.2VALW

+5VALW

1
1
PJ801 @
JUMP_43X79

2
PC802

2
1U_0402_6.3V6K

2
D D

1
PC803
4.7U_0805_6.3V6K

6
PR815 PU801

2
@ 0_0402_5% 5

VCNTL
VIN
+5VALW 1 2 7
PD801 POK
4 +1.1VSP
VOUT
1 2
3
VOUT

1
@ RB751V-40_SOD323-2

22U_0805_6.3V6M
VLDT_EN

PC805
1 2 8 2
EN FB

1
(33,38,44,45) VLDT_EN PR802

GND

2
1
PR801 @ 9 1.15K_0402_1%
0_0402_5% @ PC801 PR803 VIN

2
1U_0603_10V6K 47K_0402_5% APL5912-KAC-TRL_SO8

1
2
PC804

1
0.01U_0402_25V7K

PR804
3K_0402_1%

2
+1.8V

+5VALW

1
PJ803

1
@ JUMP_43X79

2
PC806 PJ802
@ 1U_0402_6.3V6K 2 1
+1.1VSP +1.1VS

2
2 1

2
@ JUMP_43X118
C PR816 C

6
PU802

1
@ 0_0402_5% 5 PC807

VCNTL
VIN @ 4.7U_0805_6.3V6K
+5VALW 1 2 7
POK PJ804
4

2
PR805 VOUT
+1.5VSP_UMA 2 1 +1.5VS_UMA
2 1
3 +1.5VSP_UMA
@ 10K_0402_1% VOUT @ JUMP_43X79

1
1 2 8 2

@ 22U_0805_6.3V6M
EN FB

1
(18,31,33,38,41,44) SUSP#

PC809
GND
1

9 PR806 PC808

2
VIN
1

PR807 @ 1.54K_0402_1% @ 0.01U_0402_25V7K PJ805

2
PC810 @ 47K_0402_5% @ APL5915KAI-TRL_SO8 2 1
+2.5VSP +2.5VS

2
@ 0.1U_0402_16V7K 2 1
2

@ JUMP_43X79
2

1
PR808
@ 1.74K_0402_1% PJ807
+1.0VSP 2 1 +VGA_PCIE

2
2 1
@ JUMP_43X118

PU803 Park M93

APL5508-25DC-TRL_SOT89-3

+3VS 2 3 VGA_PCIE 1.0V 1.1 V

IN OUT
+2.5VSP
1
4.7U_0805_6.3V6K
PC811

1
GND
2
1

PC812 PR811 4.53K 3K

1U_0402_6.3V6K 1 @ PR809
150_1206_5%
2

B B
2

+1.2VALW

+5VALW
1

PJ806
1

JUMP_43X79
+5VALW
@
1

PC816
PD802 1U_0402_6.3V6K
2
2

@ RB751V-40_SOD323-2
1

1 2
1

PR817 PC815
@ 0_0402_5% 4.7U_0805_6.3V6K
6

PR814 PU804
2

@ 0_0402_5% 5
VCNTL
2

VLDT_EN VIN
1 2 7
(33,38,44,45) VLDT_EN POK
4 +1.0VSP
PR813 VOUT
3
VOUT
1

15K_0402_5%
22U_0805_6.3V6M

SUSP#
PC817

1 2 8 2
EN FB
1

(18,31,33,38,41,44) SUSP# PR812

GND

2
1

PD803 9 1.15K_0402_1%
RB751V-40_SOD323-2 PR810 VIN
2

1 2 @ 47K_0402_5% APL5912-KAC-TRL_SO8
2

A PC814 A
2

1U_0603_10V6K PC813
1

0.01U_0402_25V7K

PR811
4.53K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1V/1.5V/2.5V/1.0V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 46 of 49
5 4 3 2 1
 8 7 6 5 4 3 2 1

www.bufanxiu.com
H H

CPU_B+ PL901
LGATE_NB HCB4532KF-800T90_1812
PC901 1 2 B+
33P_0402_50V8J

10U_1206_25V6M

2200P_0402_50V7K
0.01U_0402_25V7K
2 1

220U_25V_M
1

1
PQ901 +

PC903

PC904

PC905

PC906
2 1 2 1 UGATE_NB 8 1
G2 D2
7 2

2
PR901 PC902 S2/D1 D2 2
6 3
44.2K_0402_1% 1200P_0402_50V7K S2/D1 G1
5 4
PR902 S2/D1 S1
2_0603_5% AO4932_SO8
+5VS 1 2 PC907 PL902
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB
2 1 PHASE_NB 1 2
G PR903
+VDDNB G

1
PC908 PR904 0_0603_5%
0.1U_0603_16V7K 22K_0402_1%
2 1
BOOT_NB 1 2 1 2 PR905
4.7_1206_5% 1
Design Current: 2.8A

2
PR906
10_0402_5%
PC909
0.22U_0603_10V7K + PC910
Max current: 4A

1 2
1 2
1 2 +CPU_CORE_NB
PC911
220U_D2_4VM OCP_min:5A
CPU_B+ 2
680P_0603_50V7K
PR907
CPU_VDDNB_FB_H (6)

2
2_0603_5% PR909
+5VS +3VS 11.3K_0402_1%

1
2 1 PHASE_NB
PR908
0_0402_5% LGATE_NB

1
PC912 CPU_B+
0.1U_0603_16V7K PHASE_NB

2
1

2
PR910 PR911 UGATE_NB

2200P_0402_50V7K
0.01U_0402_25V7K
F 0_0402_5% @ 105K_0402_1% F

10U_1206_25V6M

10U_1206_25V6M
5
2 1 CPU_VDDNB_FB_L (6)
PR912
2

2
1

1
0_0402_5%

PC915

PC913

PC916

PC914
PR914 PQ903

1
PR913 @ 10K_0402_1% PR915 SI7686DP-T1-E3_SO8

2
105K_0402_1% PR916 10_0402_5% UGATE0 4
@ 105K_0402_1%

48

47

46

45

44

43

42

41

40

39

38

37
2

1
PU901
PHASE0

VIN

VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
2

PR917 PL903

3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
(33) VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +CPU_CORE_0
PR918 0_0402_5% OFS/VFIXEN BOOT_NB

2
1 2 2 35 BOOT0 PC917
PGOOD BOOT0

5
6
7
8

5
6
7
8
(23) H_PWRGD_L 1 2 0.22U_0603_10V7K PR922

1
PR919 0_0402_5% @ 3 34 UGATE0 16.2K_0402_1%
PWROK UGATE0 PQ902 PR920
2 1 4 33 PHASE0 PQ904 4.7_1206_5%

1
E SVD PHASE0 E
(6) CPU_SVD PR921 0_0402_5% SI4634DY-T1-E3_SO8 1 PR923 2
5 32 4 4 SI4634DY-T1-E3_SO8 4.02K_0402_1%

1 2
SVC PGND0 +5VS
2 1
(6) CPU_SVC PR924 0_0402_5% 6 31 LGATE0 PC918 PC919
ENABLE LGATE0 680P_0603_50V7K 2 1
7 30

3
2
1

3
2
1

2
RBIAS PVCC 0.1U_0402_16V7K
(33) VR_ON 8 29 LGATE1
OCSET LGATE1

1
PR925 PR926 ISL6265IRZ-T_QFN48_6X6~D PC920
2 1 2 1 9 28 1U_0603_10V6K LGATE0
21.5K_0402_1% 95.3K_0402_1% VDIFF0 PGND1

ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE_0
VW0 BOOT1
Design Current: 12.6A
COMP1
VDIFF1
VSEN0

VSEN1
RTN0

RTN1
ISN0

ISN1
ISP0

VW1

ISP1

2200P_0402_50V7K
0.01U_0402_25V7K
FB1
Max current: 18A

TP
D D

10U_1206_25V6M

10U_1206_25V6M
5
OCP_min:24A
13

14

15

16

17

18

19

20

21

22

23

24

49

1
PC921

PC922

PC923

PC924
ISP0 PQ905
PR927 0_0402_5%

ISN0 SI7686DP-T1-E3_SO8

2
1

ISN1
ISP1
UGATE1 4
(6) CPU_VDD0_FB_H VSEN0 0_0402_5%
0_0402_5%
2 PR930 1

2 PR931 1

PR928 PR929
0_0402_5%

+CPU_CORE_0 2 1 1 2 PHASE1
10_0402_5% PR932 PL904
2

3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
(6) CPU_VDD0_FB_L RTN0 BOOT1 1 2 1 2 1 2 +CPU_CORE_1
PR933 10_0402_5%

2
2 1 PC925

5
6
7
8

5
6
7
8
0.22U_0603_10V7K PR936

1
RTN1 16.2K_0402_1%
(6) CPU_VDD1_FB_L PR935 10K_0402_1% PQ906 PQ907 PR934
2 1 SI4634DY-T1-E3_SO8 SI4634DY-T1-E3_SO8 4.7_1206_5%

1
C 1 PR937 2 C
@ PR938 1K_0402_1% 4 4 4.02K_0402_1%

1 2
+1.8V 2 1
PC926 PC927
(6) CPU_VDD1_FB_H VSEN1 680P_0603_50V7K 2 1
PR939

3
2
1

3
2
1

2
+CPU_CORE_1 2 10_0402_5%
1 0.1U_0402_16V7K

DIFF_0 VW0 DIFF_1 VW1

LGATE1
PR940 PC928 PR941 PC931

ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1

PC929 PC930 PC932 PC933

+CPU_CORE_1
180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K
Design Current: 12.6A
PR942
1K_0402_5% PR943 PC934
PR944
6.81K_0402_1%
PR945
1K_0402_5% PR946 PC935
PR947
6.81K_0402_1%
Max current: 18A
B
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 OCP_min:24A B

54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 10, 2009 Sheet 47 of 49
8 7 6 5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List)

www.bufanxiu.com Page 1 of 1
for PWR
Item Reason for change PG# Modify List Date Phase

Adjust power sequence for VGA_PCIE by HW request PR831=15K

D
1 P46 2009.10.27 EVT
D

Change PC108 from 1000pF to 0.068uF for issue solution 2009.11.17 PVT
2 P39 PC108=0.068uF

Add snubber R & C and modify boost resistor for 1.8VP P43 PR512=2.2 ohm;PR513=4.7 ohm;PC524=820pF 2009.11.17 PVT
3

Adjust power sequence PR701=34.8K,PC701=0.1uF

4 P45 Un-pop PR520,PQ505 2009.12.03 PVT

6
C C

10

B B

11

12

13

14

15

16
A A
17

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 48 of 49
5 4 3 2 1
 5 4 3 2 1

1. change component AP2301GN to AO3413

www.bufanxiu.com
2. remove R521, R517, R520 and R518, and reserve U49 , U50, R999, R1000, R1001 and R1002 for experiment Vari-bright function.
3. U6.18 add a pull up resistor R1005 and pull down resistor R1006 for check ENE KB926 version.
4. reserve R1003 and R1004 for Vari-bright test.
D D

5. add J8, C1034, C1035, C1036, C1037, C1038 and C1039 for EMI request.
6. Change R583, R584, R585 and R586 Bead from SM010018110 to SM010022410.
7. reserve R1007 for EMI request.
8. Change C633, C640, C662, C948, C660 and C639 to 10pF for EMI rquest.

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 49 of 49
5 4 3 2 1