Professional Documents
Culture Documents
1 1
Compal Confidential
2 2
3
2009-03-11 3
REV:1.0
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 1 of 57
A B C D E
A B C D E
Tigris
Puma
Compal Confidential AMD S1G3 Processor
uPGA-638 Package
VRAM 512MB Caspian AMD S1G2 Processor
Model Name : KBLG0 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
64M16 x 4 Fan Control uPGA-638 Package
page 19, 20 page 44 Dual Channel BANK 0, 1, 2, 3 page 8,9
PowerXpress (MUX) Griffin page 4,5,6,7 1.8V DDRII 667/800
1 LCD (LED BL) MUX DDR2 500MHz 1
Hyper Transport Link 5 in 1 socket
page 24 (1:2) ATI M92-M2 XT 16 x 16 page 33
ATI RS880M
uFCBGA-962 PCI-Express 16x uFCBGA-528
CRT MUX Page 14,15,16,17,18,21,22
Gen2 Thermal Sensor Clock Generator
page 26 (1:2) ATI RS780MN Card Reader
ADM1032 SLG8SP626VTR
page 6 page 23 RTS5159
HDMI Conn. uFCBGA-528 page 33
page 25
PCI-Express 1x option1
page 10,11,12,13 page 36,37 page 27 page 37 page 36 page 36
option2
USB CMOS Bluetooth Finger Mini
MINI Card x1 LAN(GbE) Card Reader A link Express2 conn printer card
ATI SB710 Camera Conn
WLAN Atheros AR8131 JMB385 uFCBGA-528 X2 AES1610 (WL)X1
page 36 page 34 page 33 USB port 0,6 USB port 3 USB port 12 USB port 13 USB port 8 USB port 4
port 2 port 3 port 4
2
ATI SB700 3.3V 48MHz USB
2
Power Circuit
4
page 46,47,48,49,50,51 4
52,53,54
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 2 of 57
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF 0 0 0 V 0 V 0 V
+1.8VS 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 Discrete VGA@
Device IDSEL# REQ#/GNT# Interrupts 1 0.2 UMA UMA@
2 0.3 M92-M2 XT M92@
3 0.4 VRAM STRAP VRAM@
4 1.0 LAN 8121 8121@
5 LAN 8131 8131@
6 HDT debug HDT@
7 JMB385 CR JMB385@
RTS5159 CR RTS5159@
FOR PUMA PUMA@
EC SM Bus1 address EC SM Bus2 address FOR TIGRIS TIGRIS@
3 FOR TEST UB@ 3
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 3 of 57
A B C D E
A B C D E
1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1
C727 C666 C725 C726 C722 C668
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10
PUMA@ PUMA@
Change as 10U Near CPU Socket
Change as 10U for Tigris
+1.2V_HT +1.2V_HT for Tigris
JCPU1A
PUMA@
2 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
C664 4.7U_0805_10V4Z
VLDT=1.5A D2
D3
VLDT_A1 VLDT_B1
AE3
AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 W3
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 V1
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 U2
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 AD4
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 AD3
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 AD5
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 AC5
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 AB4
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 V4
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
10 H_CLKIP0 J3 Y1 H_CLKOP0 10
L0_CLKIN_H0 L0_CLKOUT_H0
10 H_CLKIN0 J2 W1 H_CLKON0 10
L0_CLKIN_L0 L0_CLKOUT_L0
10 H_CLKIP1 J5 Y4 H_CLKOP1 10
L0_CLKIN_H1 L0_CLKOUT_H1
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10
10 H_CTLIP0 N1 R2 H_CTLOP0 10
L0_CTLIN_H0 L0_CTLOUT_H0
10 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 10
10 H_CTLIP1 P3 T5 H_CTLOP1 10
L0_CTLIN_H1 L0_CTLOUT_H1
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
6090022100G_B conn@
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 4 of 57
A B C D E
A B C D E
C177
6090022100G_B 6090022100G_B
conn@ conn@
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 DDRII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 5 of 57
A B C D E
A B C D E
+2.5VDDA
L35 VDDA=0.25A
+2.5VS 1 2 3300P_0402_50V7K
FBM_L11_201209_300L_0805
1 1 1 1 +1.8V 1 2
R66 10K_0402_5%
+ C391 4.7U_0805_10V4Z C385 C319 C384 1 2
150U_B2_6.3VM 0.22U_0603_16V4Z R67 300_0402_5%
2 2 2
2
2
B
Q9
JCPU1D
E
1 CPU_THERMTRIP#_R R65 1
3 1 1 2 H_THERMTRIP# 28
C
0_0402_5%
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 KEY1
F9 W18
VDDA2 KEY2
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC
23 CLK_CPU_BCLK CPU_CLKIN_SC_N CLKIN_H SVC CPU_SVD CPU_SVC 53
C723 A8 A4
CLKIN_L SVD CPU_SVD 53
1
+1.8V 1 2
LDT_RST# B7 R69 300_0402_5%
R325 H_PWRGD RESET_L
A7
169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R
F10 LDTSTOP_L THERMTRIP_L AF6
C6 AC7 H_PROCHOT#
11 CPU_LDT_REQ#
2
LDTREQ_L PROCHOT_L H_PROCHOT# R68
23 CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 1 2 H_PROCHOT_R# 27
C724 3900P_0402_50V7K R70 2 1 2.2K_0402_5% CPU_SIC AF4 0_0402_5%
+1.8V SIC
2 1 CPU_SID AF5
+1.8VS +1.8V SID
R71 2.2K_0402_5% AE6 W7 THERMDC_CPU
ALERT_L THERMDC THERMDA_CPU
THERMDA W8
R82 1 2 44.2_0402_1% CPU_HTREF0 R6
HT_REF0
2
R144 300_0402_5%
R337 CPU_TEST25L 1 2
6090022100G_B
300_0402_5% 1 2 R143 300_0402_5%
conn@ CPU_DBREQ# 1 2
C92 @ 0.1U_0402_16V4Z R327 300_0402_5%
1
LDT_STOP# CPU_TEST21 1 2
11,27 LDT_STOP# R52
R53 FDV301N, the Vgs is: R75 300_0402_5%
2 1 2 1 CPU_TEST24 1 2
3
1 +3VS min = 0.65V 3
C719 R74 300_0402_5%
0.01U_0402_25V4Z 20K_0402_5% 34.8K_0402_1% Typ = 0.85V CPU_TEST20 1 2
@ @ @ Max = 1.5V R73 300_0402_5%
2 CPU_TEST23 1 2
2.09V for Gate R72 300_0402_5%
2
G
CPU_TEST25H 1 2
@ R136 300_0402_5%
CPU_SID 3 1 EC_SMB_DA 1 2 EC_SMB_DA2 CPU_TEST25L 1 2
R479 0_0402_5% R135 300_0402_5%
S
EC_SMB_DA1
For Tigris
1 @ 2 TIGRIS@
EC_SMB_DA1 38,47
Q7 @ FDV301N_NL_SOT23-3 R484 0_0402_5%
+1.8V
DVT
2
+1.8V
G
220_0402_5%R117
220_0402_5%R118
220_0402_5%R119
220_0402_5%R120
@
1
CPU_SIC 3 1 EC_SMB_CK 1 2 EC_SMB_CK2
R480 0_0402_5%
S
1 @ 2 EC_SMB_CK1 JP1
EC_SMB_CK1 38,47
Q8 @ FDV301N_NL_SOT23-3 R485 0_0402_5%
1 2
2
3 4
CPU_DBREQ# HDT@ HDT@ 5 6 R140 2
1
+3VS CPU_DBRDY HDT@ HDT@ 7 8 @ 0_0402_5%
CPU_TCK 9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
15 16 MP(Remove)
0.1U_0402_16V4Z
1 CPU_TRST#
17 18
5
CPU_TDO U15
C206 19 20 LDT_RST#
2
P
21 22 HDT_RST# B
2 MP(Remove) 23 24
4
Y
U11 1
26 A SB_PWRGD 11,28,41 4
G
4 EC_SMB_CK2
1 8 EC_SMB_CK2 22,38
VDD SCLK NC7SZ08P5X_NL_SC70-5
3
THERMDA_CPU 2 7 EC_SMB_DA2 CONN@ SAMTEC_ASP-68200-07 HDT@
D+ SDATA EC_SMB_DA2 22,38
C194 THERMDC_CPU 3 6 MP(mask)
D- ALERT#
1 2
2200P_0402_50V7K 4 5
PUMA@ THERM# GND
Change as 3300pF
Security Classification Compal Secret Data Compal Electronics, Inc.
ADM1032ARMZ_MSOP8 Issued Date 2008/10/06 2009/10/06 Title
For Tigris Deciphered Date
http://rusefix.com
Address 1001 100X b THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 CTRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 6 of 57
A B C D E
A B C D E
+1.8V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 V9
+CPU_CORE_NB VSS56 VSS121
F19 VSS57 VSS122 V11
F21 V13
VSS58 VSS123
1 1 1 1 1 1 F23 V15
C195 C228 C222 C294 C295 C274 VSS59 VSS124
1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C207 C186 C249 VSS60 VSS125
H7 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VSS61 VSS126
H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 Y23
2 2 2 VSS63 VSS128
H23 VSS64 VSS129 N6
J4
VSS65
6090022100G_B
Under CPU Socket Athlon 64 S1
Processor Socket
conn@
1 1 1 1 1 1
C309 C307 C218 C308 C310 C219 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C163 C164 C109 C110 C190 C191 C189 C173
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 2 2 2 2 2 2 2 2
to follow AMD Layout
+1.8V
review recommand for
EMI Near CPU Socket Right side.
+0.9V
1
1 1 1 1 C: Change to NBO CAP
+ C226
C211 C209 C208 C210 330U_X_2VM_R6M 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C387 C386 C383 C382 C718 C717 C716 C715
2 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 PWR & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, January 15, 2009 Sheet 7 of 57
A B C D E
A B C D E
+1.8V +1.8V
JDIMM1
+V_DDR_MCH_REF 1 VREF VSS 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 DDRA_SDQ[0..63]
DQ1 VSS DDRA_SDM0 DDRA_SDQ[0..63] 5
9 VSS DM0 10
DDRA_SDQS0# 11 12 DDRA_SDM[0..7]
5 DDRA_SDQS0# DQS0# VSS DDRA_SDM[0..7] 5
DDRA_SDQS0 13 14 DDRA_SDQ6
1 5 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7 1
15 VSS DQ7 16
DDRA_SDQ2 17 18
DDRA_SDQ3 DQ2 VSS DDRA_SDQ12 DDRA_SMA[0..15]
19 DQ3 DQ12 20 DDRA_SMA[0..15] 5
21 22 DDRA_SDQ13
DDRA_SDQ8 VSS DQ13
23 24
DDRA_SDQ9 DQ8 VSS DDRA_SDM1
25 DQ9 DM1 26
27 28 +0.9V +1.8V
DDRA_SDQS1# VSS VSS RP10
29 DQS1# CK0 30 DDRA_CLK0 5
5 DDRA_SDQS1# DDRA_SDQS1 DDRA_SMA6
31 DQS1 CK0# 32 DDRA_CLK0# 5 1 8 1 2
5 DDRA_SDQS1 DDRA_SMA7 C182 0.1U_0402_16V4Z
33 34 2 7
DDRA_SDQ10 VSS VSS DDRA_SDQ14 DDRA_SMA11
35 DQ10 DQ14 36 3 6 1 2
DDRA_SDQ11 37 38 DDRA_SDQ15 DDRA_SMA15 4 5 C198 0.1U_0402_16V4Z
DQ11 DQ15
39 VSS VSS 40
+1.8V 47_0804_8P4R_5%
RP13
41 42 DDRA_CKE0 8 1 1 2
VSS VSS
2
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SBS2# 7 2 C225 0.1U_0402_16V4Z
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 R147 DDRA_SMA14
45 46 6 3 1 2
DQ17 DQ21 1K_0402_1% DDRA_CKE1 C223 0.1U_0402_16V4Z
47 VSS VSS 48 5 4
DDRA_SDQS2# 49 50
5 DDRA_SDQS2# DDRA_SDQS2 DQS2# NC DDRA_SDM2 47_0804_8P4R_5%
51 52
1
5 DDRA_SDQS2 DQS2 DM2 +V_DDR_MCH_REF RP8
53 54 +V_DDR_MCH_REF
DDRA_SDQ18 VSS VSS DDRA_SDQ22 DDRA_SBS1#
55 DQ18 DQ22 56 1 8 1 2
1000P_0402_25V8J
1U_0402_6.3V4Z
DDRA_SDQ19 57 58 DDRA_SDQ23 1 1 DDRA_SMA0 2 7 C159 0.1U_0402_16V4Z
DQ19 DQ23
2
59 60 DDRA_SMA2 3 6 1 2
VSS VSS
C392
C394
DDRA_SDQ24 61 62 DDRA_SDQ28 R148 DDRA_SMA4 4 5 C167 0.1U_0402_16V4Z
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29 1K_0402_1%
63 64
DQ25 DQ29 2 2 47_0804_8P4R_5%
65 66
DDRA_SDM3 VSS VSS DDRA_SDQS3# RP9
67 68
1
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# 5 DDRA_SMA5
69 NC DQS3 70 8 1 1 2
DDRA_SDQS3 5 DDRA_SMA8 C179 0.1U_0402_16V4Z
71 72 7 2
DDRA_SDQ26 VSS VSS DDRA_SDQ30 DDRA_SMA9
73 74 6 3 1 2
2 DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 DDRA_SMA12 C185 0.1U_0402_16V4Z 2
75 DQ27 DQ31 76 5 4
77 78
DDRA_CKE0 VSS VSS DDRA_CKE1 47_0804_8P4R_5%
5 DDRA_CKE0 79 80 DDRA_CKE1 5
CKE0 NC/CKE1 RP7
81 VDD VDD 82
83 84 DDRA_SMA15 DDRA_SBS0# 8 1 1 2
DDRA_SBS2# NC NC/A15 DDRA_SMA14 DDRA_SMA10 C169 0.1U_0402_16V4Z
5 DDRA_SBS2# 85 86 7 2
BA2 NC/A14 DDRA_SMA1
87 VDD VDD 88 6 3 1 2
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SMA3 5 4 C161 0.1U_0402_16V4Z
DDRA_SMA9 A12 A11 DDRA_SMA7
91 A9 A7 92
DDRA_SMA8 93 94 DDRA_SMA6 47_0804_8P4R_5%
A8 A6 RP4
95 VDD VDD 96
DDRA_SMA5 97 98 DDRA_SMA4 DDRA_SCS1# 8 1 1 2
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_ODT1 C157 0.1U_0402_16V4Z
99 A3 A2 100 7 2
DDRA_SMA1 101 102 DDRA_SMA0 DDRA_SWE# 6 3 1 2
A1 A0 DDRA_SCAS# C142 0.1U_0402_16V4Z
103 104 5 4
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 106 DDRA_SBS1# 5
DDRA_SBS0# A10/AP BA1 DDRA_SRAS# 47_0804_8P4R_5%
5 DDRA_SBS0# 107 108 DDRA_SRAS# 5
DDRA_SWE# BA0 RAS# DDRA_SCS0# RP3
5 DDRA_SWE# 109 110 DDRA_SCS0# 5
WE# S0# DDRA_SMA13
111 112 1 8 1 2
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_ODT0 C145 0.1U_0402_16V4Z
5 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 5 2 7
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SCS0# 3 6 1 2
5 DDRA_SCS1# NC/S1# NC/A13
117 118 DDRA_SRAS# 4 5 C135 0.1U_0402_16V4Z
DDRA_ODT1 VDD VDD
5 DDRA_ODT1 119 120
NC/ODT1 NC 47_0804_8P4R_5%
121 122
DDRA_SDQ32 VSS VSS DDRA_SDQ36
123 124
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
125 126
DQ33 DQ37
127 VSS VSS 128
DDRA_SDQS4# 129 130 DDRA_SDM4
5 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4
131 132
5 DDRA_SDQS4 DQS4 VSS DDRA_SDQ38
133 134
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 136
DDRA_SDQ35 DQ34 DQ39
137 138
3 DQ35 VSS DDRA_SDQ44 3
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
143 144
DQ41 VSS DDRA_SDQS5#
145 VSS DQS5# 146
DDRA_SDM5 DDRA_SDQS5 DDRA_SDQS5# 5
147 148
DM5 DQS5 DDRA_SDQS5 5
149 150
DDRA_SDQ42 VSS VSS DDRA_SDQ46
151 152
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
153 154
DQ43 DQ47
155 156
DDRA_SDQ48 VSS VSS DDRA_SDQ52
157 DQ48 DQ52 158
DDRA_SDQ49 159 160 DDRA_SDQ53 DVT(EMI)
DQ49 DQ53
161 162
VSS VSS +1.8V
163 NC,TEST CK1 164 DDRA_CLK1 5
165 166 DDRA_CLK1# 5
DDRA_SDQS6# VSS CK1#
167 DQS6# VSS 168
5 DDRA_SDQS6# DDRA_SDQS6 DDRA_SDM6
169 170 1 2
5 DDRA_SDQS6 DQS6 DM6 C174 0.1U_0402_16V4Z
171 172
DDRA_SDQ50 VSS VSS DDRA_SDQ54
173 174
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55
175 176 1 2
DQ51 DQ55 C175 0.1U_0402_16V4Z
177 178
DDRA_SDQ56 VSS VSS DDRA_SDQ60
179 180
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61
181 DQ57 DQ61 182 1 2
183 184 C176 0.1U_0402_16V4Z
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 DM7 DQS7# 186
DDRA_SDQS7 DDRA_SDQS7# 5
187 188
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 5
189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
ICH_SMBDATA0 VSS DQ63
9,23,28,36 ICH_SMBDATA0 195 196
ICH_SMBCLK0 SDA VSS R39
9,23,28,36 ICH_SMBCLK0 197 198 1 2 10K_0402_5%
SCL SAO R36
+3VS 199 200 1 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204
4 4
FOX_AS0A426-M2RN-7F
+3VS CONN@
C67
1
C63
1
DIMM1 REV H:5.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z Issued Date 2008/10/06 2009/10/06 Title
2
2.2U_0805_10V6K 2 Deciphered Date
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 8 of 57
A B C D E
A B C D E
+V_DDR_MCH_REF +1.8V
+1.8V
2.2U_0603_6.3V4Z
1
C390 JDIMM2 DDRB_SDQ[0..63]
DDRB_SDQ[0..63] 5
1 2
2 VREF VSS DDRB_SDQ4 DDRB_SDM[0..7]
3 VSS DQ4 4 DDRB_SDM[0..7] 5
DDRB_SDQ0 5 6 DDRB_SDQ5
DDRB_SDQ1 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDRB_SDM0
DDRB_SDQS0# VSS DM0 DDRB_SMA[0..15]
11 DQS0# VSS 12 DDRB_SMA[0..15] 5
1 5 DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ6 1
5 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 22
DDRB_SDQ8 VSS DQ13
23 DQ8 VSS 24
DDRB_SDQ9 25 26 DDRB_SDM1
DQ9 DM1
27 VSS VSS 28
DDRB_SDQS1# 29 30
5 DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 5
DDRB_SDQS1 31 32
5 DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# 5 +1.8V
33 34 +0.9V
DDRB_SDQ10 VSS VSS DDRB_SDQ14 RP6
35 36
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15 DDRB_SRAS#
37 DQ11 DQ15 38 1 8 2 1
39 40 DDRB_SMA0 2 7 C171 0.1U_0402_16V4Z
VSS VSS DDRB_SMA2 3 6 1 2
DDRB_SMA4 4 5 C201 0.1U_0402_16V4Z
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20 47_0804_8P4R_5%
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 48 RP12
DDRB_SDQS2# VSS VSS DDRB_SMA6
49 50 1 8 2 1
5 DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2 DDRB_SMA7 C180 0.1U_0402_16V4Z
51 52 2 7
5 DDRB_SDQS2 DQS2 DM2 DDRB_SMA11
53 VSS VSS 54 3 6 1 2
DDRB_SDQ18 55 56 DDRB_SDQ22 DDRB_SMA14 4 5 C224 0.1U_0402_16V4Z
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 58
DQ19 DQ23 47_0804_8P4R_5%
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29 RP14
63 64
DQ25 DQ29 DDRB_CKE0
65 VSS VSS 66 8 1 2 1
DDRB_SDM3 67 68 DDRB_SDQS3# DDRB_SBS2# 7 2 C200 0.1U_0402_16V4Z
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 5 DDRB_SMA15
69 70 6 3 1 2
NC DQS3 DDRB_SDQS3 5 DDRB_CKE1 C231 0.1U_0402_16V4Z
71 72 5 4
2 DDRB_SDQ26 VSS VSS DDRB_SDQ30 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 47_0804_8P4R_5%
DQ27 DQ31
77 78
DDRB_CKE0 VSS VSS DDRB_CKE1 RP11
5 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 5
81 82 DDRB_SMA8 8 1 2 1
VDD VDD DDRB_SMA15 DDRB_SMA5 C183 0.1U_0402_16V4Z
83 84 7 2
DDRB_SBS2# NC NC/A15 DDRB_SMA14 DDRB_SMA12
5 DDRB_SBS2# 85 BA2 NC/A14 86 6 3 1 2
87 88 DDRB_SMA9 5 4 C197 0.1U_0402_16V4Z
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 47_0804_8P4R_5%
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 RP5
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SBS0#
97 A5 A4 98 8 1 2 1
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA10 7 2 C146 0.1U_0402_16V4Z
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA3
101 102 6 3 1 2
A1 A0 DDRB_SMA1 C170 0.1U_0402_16V4Z
103 104 5 4
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 106 DDRB_SBS1# 5
DDRB_SBS0# A10/AP BA1 DDRB_SRAS# 47_0804_8P4R_5%
5 DDRB_SBS0# 107 108 DDRB_SRAS# 5
DDRB_SWE# BA0 RAS# DDRB_SCS0#
5 DDRB_SWE# 109 110 DDRB_SCS0# 5
WE# S0# RP1
111 VDD VDD 112
DDRB_SCAS# 113 114 DDRB_ODT0 DDRB_ODT1 8 1 2 1
5 DDRB_SCAS# CAS# ODT0 DDRB_ODT0 5
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SCS1# 7 2 C122 0.1U_0402_16V4Z
5 DDRB_SCS1# NC/S1# NC/A13 DDRB_SWE#
117 118 6 3 1 2
DDRB_ODT1 VDD VDD DDRB_SCAS# C117 0.1U_0402_16V4Z
5 DDRB_ODT1 119 120 5 4
NC/ODT1 NC
121 122
DDRB_SDQ32 VSS VSS DDRB_SDQ36 47_0804_8P4R_5%
123 124
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
125 DQ33 DQ37 126
127 128 RP2
DDRB_SDQS4# VSS VSS DDRB_SDM4 DDRB_SMA13
129 130 1 8 2 1
5 DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4 DDRB_ODT0 C147 0.1U_0402_16V4Z
131 132 2 7
5 DDRB_SDQS4 DQS4 VSS DDRB_SDQ38 DDRB_SCS0#
133 134 3 6 1 2
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39 DDRB_SBS1# C118 0.1U_0402_16V4Z
135 136 4 5
3 DDRB_SDQ35 DQ34 DQ39 3
137 DQ35 VSS 138
139 140 DDRB_SDQ44 47_0804_8P4R_5%
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 142
DDRB_SDQ41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDRB_SDQS5#
DDRB_SDM5 VSS DQS5# DDRB_SDQS5 DDRB_SDQS5# 5
147 148
DM5 DQS5 DDRB_SDQS5 5
149 150
DDRB_SDQ42 VSS VSS DDRB_SDQ46
151 152
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
153 154
DQ43 DQ47
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 160
DQ49 DQ53
161 VSS VSS 162
163 164 DDRB_CLK1 5
NC,TEST CK1
165 VSS CK1# 166 DDRB_CLK1# 5
DDRB_SDQS6# 167 168
5 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6
169 170
5 DDRB_SDQS6 DQS6 DM6
171 172
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 174
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55
175 176
DQ51 DQ55
177 178
DDRB_SDQ56 VSS VSS DDRB_SDQ60
179 DQ56 DQ60 180
DDRB_SDQ57 181 182 DDRB_SDQ61
DQ57 DQ61
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7#
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 5
187 188
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 5
189 DQ58 VSS 190
DDRB_SDQ59 191 192 DDRB_SDQ62
DQ59 DQ62 DDRB_SDQ63
193 194
ICH_SMBDATA0 VSS DQ63
8,23,28,36 ICH_SMBDATA0 195 196
ICH_SMBCLK0 SDA VSS R37
8,23,28,36 ICH_SMBCLK0 197 198 1 2 10K_0402_5% +3VS
SCL SAO R35
+3VS 199 VDDSPD SA1 200 1 2 10K_0402_5%
4 4
201 202
GND GND
FOX_AS0A426-MARG-7F
CONN@
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 9 of 57
A B C D E
A B C D E
U3B DVT
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C647 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C646 1 PCIE_MTX_C_GRX_N0
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 2 VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N1 A3 A4 PCIE_MTX_GRX_P1 C649 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_P1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C648 1 PCIE_MTX_C_GRX_N1
B3 GFX_RX1N GFX_TX1N B4 2 VGA@ 0.1U_0402_16V7K
1 PCIE_GTX_C_MRX_P2 PCIE_MTX_GRX_P2 1
C2 GFX_RX2P GFX_TX2P C3 C651 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C650 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 C653 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C652 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4
G5 E2 C654 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_N4 GFX_RX4P GFX_TX4P PCIE_MTX_GRX_N4 C655 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
G6 GFX_RX4N GFX_TX4N E1 2
PCIE_GTX_C_MRX_P5 H5 F4 PCIE_MTX_GRX_P5 C656 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 GFX_RX5P GFX_TX5P PCIE_MTX_GRX_N5 C657 1 PCIE_MTX_C_GRX_N5
H6 GFX_RX5N GFX_TX5N F3 2 VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N6 J6 F1 PCIE_MTX_GRX_P6 C658 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_P6 GFX_RX6P GFX_TX6P PCIE_MTX_GRX_N6 C659 1 PCIE_MTX_C_GRX_N6
J5 F2 2 VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P7 GFX_RX6N GFX_TX6N PCIE_MTX_GRX_P7
J7 GFX_RX7P GFX_TX7P H4 C642 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 J8 H3 PCIE_MTX_GRX_N7 C641 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
PCIE_GTX_C_MRX_P8 GFX_RX7N GFX_TX7N PCIE_MTX_GRX_P8
L5 GFX_RX8P GFX_TX8P H1 C638 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_GTX_C_MRX_N8 L6 H2 PCIE_MTX_GRX_N8 C636 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PCIE_GTX_C_MRX_P9 GFX_RX8N GFX_TX8N PCIE_MTX_GRX_P9
M8 J2 C637 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C635 1 PCIE_MTX_C_GRX_N9
L8 J1 2 VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P10 GFX_RX9N GFX_TX9N PCIE_MTX_GRX_P10 C634 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780-HT/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 10 of 57
A B C D E
A B C D E
UMA@ 1 2 GMCH_CRT_R
R45 140_0402_1%
UMA@ 1 2 GMCH_CRT_G
R49 150_0402_1%
UMA@ 1 2 GMCH_CRT_B
R50 150_0402_1%
1 1
+3VS
AVDD=0.11A
PLLVDD=65mA PVT
L15
+1.1VS +NB_PLLVDD 1 2 +AVDD1
L59 FBM-L11-201209-300LMA30T_0805 1 1
1 2 AVDDDI=20mA C94
MBK2012221YZF 0805 1 +1.8VS C874 2.2U_0603_6.3V4Z
1
L10 1U_0402_6.3V4Z
C645 C663 +AVDD2 2 2
1 2
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z FBM-L11-201209-300LMA30T_0805 1
2 2 U3C
C74 F12 A22 GMCH_TXOUT0+ 24
+1.8VS 0.1U_0402_16V4Z AVDD1(NC) TXOUT_L0P(NC)
PLLVDD18=20mA 2
E12
AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC)
B22 GMCH_TXOUT0- 24
+1.8VS +NB_HTPVDD
AVDDQ=4mA F14
AVDDDI(NC) TXOUT_L1P(NC)
A21 GMCH_TXOUT1+ 24
L8 G15 B21 GMCH_TXOUT1- 24
L13 +AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
1 2 H15 B20 GMCH_TXOUT2+ 24
FBM-L11-201209-300LMA30T_0805 AVDDQ(NC) TXOUT_L2P(NC)
1 2 1 1 PVT H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 GMCH_TXOUT2- 24
MBK2012221YZF 0805 1 1 A19
C61 C875 TXOUT_L3P(NC)
E17 B19
C93 C84 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
F17
CRT/TVOUT
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 2 2 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
2 2
TXOUT_U0N(NC) A18
GMCH_CRT_R G18 A17
26 GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
VDDA18HTPLL=20mA GMCH_CRT_G E18 D20
26 GMCH_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 D21
+1.8VS +VDDA18HTPLL GMCH_CRT_B GREENb(NC) TXOUT_U2N(NC)
26 GMCH_CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
L9 F19 D19
BLUEb(NC) TXOUT_U3N(NC)
1 2
GMCH_CRT_HSYNC A11
VDDLTP18=15mA
MBK2012221YZF 0805 1 1 B16 GMCH_TXCLK+ 24 L56
2 13,26 GMCH_CRT_HSYNC GMCH_CRT_VSYNC B11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) +VDDLTP18 2
13,26 GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 GMCH_TXCLK- 24 1 2 +1.8VS
C66 C72 GMCH_CRT_CLK F8 D16 1 1 MBC1608121YZF_0603
26 GMCH_CRT_CLK GMCH_CRT_DATA E8 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z D17
2 2 26 GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) C665 C644
R42 1 2 715_0402_1% G14 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
+1.8VS DAC_RSET(PWM_GPIO1) +VDDLTP18 2 2
VDDA18PCIEPLL=0.12A PVT +NB_PLLVDD VDDLTP18(NC)
A13
U50 +NB_PLLVDD A12 B13
PLLVDD(NC) VSSLTP18(NC)
5
LVTM
P
PLL PWR
MBK2012221YZF 0805 1 Y VDDLT18_2(NC) L12
1 6,28,41 SB_PWRGD 1 A +VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
G
B14 +VDDLT18 1 2
VDDLT33_2(NC) +1.8VS
C87 C86 +VDDA18PCIEPLL D7 1 1 MBC1608121YZF_0603
3
PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R283 300_0402_5% C22
VSSLT7(VSS)
23 CLK_NBHT C25
HT_REFCLKP
23 CLK_NBHT# C24
CLK_NB_14.318M HT_REFCLKN
CLK_NB_14.318M E11
23 CLK_NB_14.318M REFCLK_P/OSCIN(OSCIN)
CLOCKs
F11 E9 UMA_ENVDD
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
F7 UMA_ENBKL 38
LVDS_BLON(PCE_RCALRP)
1
1.27K_0402_1%
1.27K_0402_1%
R477 R293 R290 T1
23 CLK_NBGFX# GFX_REFCLKN
2
100_0402_5% 4.7K_0402_5% 4.7K_0402_5%
@ U1 R469
GPP_REFCLKP
1 R294
1 R29
U2 1.27K_0402_1% UMA@ UMA@
2
GPP_REFCLKN @
3 +3VS V4 3
1 23 CLK_SBLINK_BCLK
2
GPPSB_REFCLKP(SB_REFCLKP)
23 CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
1
C854 DVT
100P_0402_25V8K R483 GMCH_LCD_CLK B9
2 24 GMCH_LCD_CLK I2C_CLK
1.5K_0402_5% GMCH_LCD_DATA
@
@
24 GMCH_LCD_DATA
GMCH_HDMI_DATA_R2
A9
B8
I2C_DATA MIS. TMDS_HPD(NC)
D9
D10
HDMI_DET 15,25
@ GMCH_HDMI_CLK_R2 DDC_DATA0/AUX0N(NC) HPD(NC)
A8
2
GMCH_HDMI_CLK_R1 DDC_CLK0/AUX0P(NC)
24,26,38 PX_GPIO2 1 2 B7 D12 1 2 SUS_STAT# 28
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5)
R486 0_0402_5% DVT GMCH_HDMI_DATA_R1 A7
DDC_DATA1/AUX1N(NC)
R297 0_0402_5% SUS_STAT_R# 13 Strap pin
38 PX_GPIO2_NB 1 2 THERMALDIODE_P AE8
DVT R490 0_0402_5% +3VS 2 @ 1 B10 AD8
@ R288 10K_0402_5% STRP_DATA THERMALDIODE_N
POWER_SEL G11 D13 1 2 UMA@
50 POWER_SEL RSVD TESTMODE R279 R744 0_0402_5% DVT2
C8 1.8K_0402_5% 1 2
13 AUX_CAL AUX_CAL(NC)
Strap pin +3VS
+3VS RS780M_FCBGA528
C857 0.1U_0402_16V4Z
UMA@ POWER_SEL @
R295 1 2 4.7K_0402_5% GMCH_LCD_CLK DVT R491 @ 0_0402_5%
5
R289 1 2 4.7K_0402_5% GMCH_LCD_DATA 1 2 GMCH_HDMI_CLK_R2 PVT
HIGH 1.0V UMA_ENVDD 2
P
B
UMA@ 4 UMA_ENVDD_R 24
R488 UMA@ 0_0402_5% Y
1 A
G
LOW 1.1V 25 GMCH_HDMI_CLK GMCH_HDMI_CLK 1 2 GMCH_HDMI_CLK_R1 U48
GMCH_HDMI_DATA 1 2 GMCH_HDMI_DATA_R1 NC7SZ08P5X_NL_SC70-5
25 GMCH_HDMI_DATA
3
R489 UMA@ 0_0402_5% @
NB_PWRGD
+1.8VS 1 2 GMCH_HDMI_DATA_R2
R492 @ 0_0402_5%
5
PVT
2
P
4 B 4
4 ENBKL 38
Y
2
G
1 2 NB_LDTSTOP# U49
for Tigris 6,27 LDT_STOP#
R61 0_0402_5% R60 R280 @ NC7SZ08P5X_NL_SC70-5
3
1 2 300_0402_5%
6 CPU_LDT_REQ#
PUMA@
1
PUMA@
R59 0_0402_5%
27 ALLOW_LDTSTOP 1 2 NB_ALLOW_LDTSTOP Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 VEDIO/CLK GEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, March 19, 2009 Sheet 11 of 57
A B C D E
A B C D E
U3F
A25 A2
VSSAHT1 VSSAPCIE1
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 D3
VSSAHT3 VSSAPCIE3
G22 VSSAHT4 VSSAPCIE4 D5
VDDHTRX+VDDHT=0.68A G24
VSSAHT5 VSSAPCIE5
E4
G25 VSSAHT6 VSSAPCIE6 G1
1 L49 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1
H19 VSSAHT7 VSSAPCIE7 G2
2 1 +VDDHT J22 G4
+1.1VS VSSAHT8 VSSAPCIE8
L17 VSSAHT9 VSSAPCIE9 H7
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 L22 J4
L3 VSSAHT10 VSSAPCIE10
L24 R7
C612 C75 C71 C62 VSSAHT11 VSSAPCIE11
1 2 +1.1VS L25 VSSAHT12 VSSAPCIE12 L1
VDDPCIE=1.1A FBMA-L11-201209-221LMA30T_0805 M20 L2
2 2 2 2 U3E VSSAHT13 VSSAPCIE13
N22 VSSAHT14 VSSAPCIE14 L4
4.7U_0805_10V4Z 0.1U_0402_16V4Z J17 A6 +VDDA11PCIE C30 1 2 10U_0805_10V4Z P20 L7
VDDHT_1 VDDPCIE_1 C28 VSSAHT15 VSSAPCIE15
K16 PART 5/6 B6 1 2 10U_0805_10V4Z R19 M6
VDDHT_2 VDDPCIE_2 VSSAHT16 VSSAPCIE16
L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
L11 1U_0402_6.3V4Z M16 D6 R24 P6
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C29 VSSAHT18 VSSAPCIE18
2 1 P16 VDDHT_5 VDDPCIE_5 E6 1 2 4.7U_0805_10V4Z R25 VSSAHT19 VSSAPCIE19 R1
R16 F6 H20 R2
FBMA-L11-201209-221LMA30T_0805 VDDHT_6 VDDPCIE_6 C53 VSSAHT20 VSSAPCIE20
1 1 1 1 T16 G7 1 2 1U_0402_6.3V4Z U22 R4
VDDHT_7 VDDPCIE_7 C79 VSSAHT21 VSSAPCIE21
H8 1 2 1U_0402_6.3V4Z V19 V7
C83 C82 C85 C91 VDDPCIE_8 VSSAHT22 VSSAPCIE22
H18 J9 W22 U4
GROUND
VDDHTRX_1 VDDPCIE_9 VSSAHT23 VSSAPCIE23
G19 K9 1 2 W24 V8
2 2 2 2 VDDHTRX_2 VDDPCIE_10 C88 VSSAHT24 VSSAPCIE24
F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z W25 VSSAHT25 VSSAPCIE25 V6
4.7U_0805_10V4Z 0.1U_0402_16V4Z E21 L9 C57 0.1U_0402_16V4Z Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 P9 AD25 W2
VDDHTRX_5 VDDPCIE_13 VSSAHT27 VSSAPCIE27
B23 R9 W4
VDDHTRX_6 VDDPCIE_14 VSSAPCIE28
VDDHTTX=0.68A A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L4 V9 M14 W8
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
+1.2V_HT 2 1 AE25
VDDHTTX_1 VDDPCIE_17
U9 VDDC=7.6A N13
VSS13 VSSAPCIE31
Y6
AD24 VGA@ P12 AA4
FBMA-L11-201209-221LMA30T_0805 VDDHTTX_2 VSS14 VSSAPCIE32
1 1 1 1 1 AC23 K12 +1.1VS 1 2 +NB_CORE P15 AB5
VDDHTTX_3 VDDC_1 L6 0_1206_5% VSS15 VSSAPCIE33
AB22 J14 R11 AB1
C31 C49 C50 C54 C52 VDDHTTX_4 VDDC_2 VSS16 VSSAPCIE34
AA21 VDDHTTX_5 VDDC_3 U16 1 2 R14 VSS17 VSSAPCIE35 AB7
Y20 J11 DVT L7 0_1206_5% T12 AC3
2 2 2 2 2 VDDHTTX_6 VDDC_4 VGA@ VSS18 VSSAPCIE36
W19 K15 U14 AC4
VDDHTTX_7 VDDC_5 VSS19 VSSAPCIE37
POWER
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 U11 AE1
2 VDDHTTX_8 VDDC_6 VSS20 VSSAPCIE38 2
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
FOR Version A11 pop 1.35VS A12 T17
VDDHTTX_10 VDDC_8
L11 V12
VSS22 VSSAPCIE40
AB2
use 1.2V_HT R17 M13 W11
VDDHTTX_11 VDDC_9 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
VDDA18PCIE=0.7A M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14
C27
C35
C60
C34
C69
C43
C76
C64
C81
C68
C36
C44
L5 N14 1 AA14 D11
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS26 VSS2
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8
FBMA-L11-201209-221LMA30T_0805 P10 P13 + AB11 E14
VDDA18PCIE_2 VDDC_14 VSS28 VSS4
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15
330U_D2E_2.5VM
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M10 R12 AB17 J15
C45 C47 C40 C51 C48 C73 VDDA18PCIE_4 VDDC_16 2 2 2 2 2 2 2 2 2 2 2 2 VSS30 VSS6
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
4.7U_0805_10V4Z W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 K11 L15
VDDA18PCIE_8 VDDC_20 VSS34 VSS10
R10 T14
VDDA18PCIE_9 VDDC_21 RS780M_FCBGA528
Y9 J16
VDDA18PCIE_10 VDDC_22
AA9
VDDA18PCIE_11
AB9 AE10
VDDA18PCIE_12 VDD_MEM1(NC)
AD9 AA11
VDDA18PCIE_13 VDD_MEM2(NC)
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 AD10
VDDA18PCIE_15 VDD_MEM4(NC)
VDD18=10mA VDD_MEM5(NC)
AB10
+1.8VS F9 AC10
VDD18_1 VDD_MEM6(NC)
G9
VDD18_2 VDD33=60mA
AE11 H11 +3VS
VDD18_MEM1(NC) VDD33_1(NC)
AD11 H12
VDD18_MEM2(NC) VDD33_2(NC)
1 1
1 RS780M_FCBGA528
C89 C80 C78
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z U3D
2 2 PAR 4 OF 6
2
AB12 AA18
3 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) 3
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 Y19
MEM_A3(NC) MEM_DQ3/DVO_D0(NC)
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 AA17
MEM_A5(NC) MEM_DQ5/DVO_D1(NC)
AB14 AA15
MEM_A6(NC) MEM_DQ6/DVO_D2(NC)
AD14 Y15
MEM_A7(NC) MEM_DQ7/DVO_D4(NC)
AD13 AC20
MEM_A8(NC) MEM_DQ8/DVO_D3(NC)
AD15 AD19
MEM_A9(NC) MEM_DQ9/DVO_D5(NC)
AC16 AE22
SBD_MEM/DVO_I/F
MEM_A10(NC) MEM_DQ10/DVO_D6(NC)
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 AB20
MEM_A12(NC) MEM_DQ12(NC)
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
AC22
MEM_DQ14/DVO_D10(NC)
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17
MEM_BA1(NC)
AD17 Y17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC)
W18
MEM_DQS0N/DVO_IDCKN(NC)
W12 AD20
MEM_RASb(NC) MEM_DQS1P(NC)
Y12 AE21
MEM_CASb(NC) MEM_DQS1N(NC)
AD18
MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
AE19 15mA
V14 MEM_ODT(NC)
AE23 +1.8VS
IOPLLVDD18(NC)
V15 AE24 +1.1VS
MEM_CKP(NC) IOPLLVDD(NC)
W14 MEM_CKN(NC)
IOPLLVSS(NC)
AD23 26mA
AE12
MEM_COMPP(NC)
AD12 AE18
MEM_COMPN(NC) MEM_VREF(NC)
RS780M_FCBGA528
4 4
+1.8VS=W/S=20/10mil For Memory PLL power
+1.1VS=W/S=20/10mil For Memory PLL power
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, January 15, 2009 Sheet 12 of 57
A B C D E
A B C D E
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
11,26 GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC)
R286 3K_0402_5% 1 : Disable (RS780)
2 1 0 : Enable (Rs780)
1 R287 @ 3K_0402_5% 1
DFT_GPIO1: LOAD_EEPROM_STRAPS
2 2
RS780 use HSYNC to enable SIDE PORT RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS780)
2 1
1 : Disable(RS780)
11,26 GMCH_CRT_HSYNC +3VS
R281 3K_0402_5%
2 @ 1
R282 3K_0402_5%
3 3
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 STRAPS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 13 of 57
A B C D E
5 4 3 2 1
PCIE_GTX_C_MRX_P[0..15]
10 PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
10 PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
10 PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
10 PCIE_MTX_C_GRX_N[0..15]
CALIBRATION VGA@
AJ21 Y30 R83 1 2 1.27K_0402_1%
NC#1 PCIE_CALRP
AK21 NC#2
+3VS_DELAY AH16 Y29 R90 1 2 2K_0402_1% +1.1VS_PX
NC_PWRGOOD PCIE_CALRN
VGA@
GPU_RST# AA30 PERSTB
1
A A
R474
10K_0402_5% M92@
VGA@ 216-0729002 A12 M96_BGA962
D4
2
11,13,24,27,33,34,36,38 PLT_RST# 2
GPU_RST#
27 PX_GPIO0 3
1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
CHP202UPT_SOT323-3 M92 PCIE interface
http://rusefix.com
2 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R481 @ 2.2K_0402_5% Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 14 of 57
5 4 3 2 1
5 4 3 2 1
U4B
AU24 HDMI_CLK+_VGA 25
TXCAP_DPA3P
AV23 HDMI_CLK-_VGA 25
TXCAM_DPA3N U4G
AT25 HDMI_TX0+_VGA 25
MUTI GFX TX0P_DPA2P
AR24 HDMI_TX0-_VGA 25
DPA TX0M_DPA2N
AU26 LVDS CONTROL AK27 T11 PAD
TX1P_DPA1P HDMI_TX1+_VGA 25 VARY_BL
AV25 HDMI_TX1-_VGA 25 AJ27 VGA_ENVDD 24
TX1M_DPA1N DIGON
T64 PAD AR8 AT27
DVPCNTL_MVP_0 TX2P_DPA0P HDMI_TX2+_VGA 25
T45 PAD AU8 AR26
DVPCNTL_MVP_1 TX2M_DPA0N HDMI_TX2-_VGA 25
T27 PAD AP8
T51 PAD DVPCNTL_0
AW8 AR30 AK35
D
T55 PAD DVPCNTL_1 TXCBP_DPB3P TXCLK_UP_DPF3P D
AR3 AT29 AL36
T65 PAD DVPCNTL_2 TXCBM_DPB3N TXCLK_UN_DPF3N
AR1
T66 PAD DVPCLK
AU1 AV31 AJ38
T30 PAD DVPDATA_0 TX3P_DPB2P TXOUT_U0P_DPF2P
AU3 AU30 AK37
T60 PAD DVPDATA_1 DPB TX3M_DPB2N TXOUT_U0N_DPF2N
AW3
T29 PAD DVPDATA_2
AP6 AR32 AH35
T61 PAD DVPDATA_3 TX4P_DPB1P TXOUT_U1P_DPF1P
AW5 AT31 AJ36
T56 PAD DVPDATA_4 TX4M_DPB1N TXOUT_U1N_DPF1N
AU5
T63 PAD DVPDATA_5
AR6 AT33 AG38
+3VS_DELAY T57 PAD DVPDATA_6 TX5P_DPB0P TXOUT_U2P_DPF0P
AW6 AU32 AH37
T62 PAD DVPDATA_7 TX5M_DPB0N TXOUT_U2N_DPF0N
AU6
T58 PAD DVPDATA_8
AT7 AU14 AF35
T50 PAD DVPDATA_9 TXCCP_DPC3P TXOUT_U3P
AV7 AV13 AG36
T28 PAD DVPDATA_10 TXCCM_DPC3N TXOUT_U3N
AN7
VGA_LCD_CLK T46 PAD DVPDATA_11
1 2 AV9 AT15
R92 4.7K_0402_5% T59 PAD DVPDATA_12 TX0P_DPC2P LVTMDP
AT9 AR14
T52 PAD DVPDATA_13 TX0M_DPC2N
VGA@ AR10
VGA_LCD_DATA T53 PAD DVPDATA_14 DPC
1 2 AW10 AU16 AP34 VGA_TXCLK+ 24
R88 4.7K_0402_5% T47 PAD DVPDATA_15 TX1P_DPC1P TXCLK_LP_DPE3P
AU10 AV15 AR34 VGA_TXCLK- 24
T48 PAD DVPDATA_16 TX1M_DPC1N TXCLK_LN_DPE3N
VGA@ AP10
T49 PAD DVPDATA_17
AV11 AT17 AW37 VGA_TXOUT0+ 24
R97 VGA_PWRSEL T54 PAD DVPDATA_18 TX2P_DPC0P TXOUT_L0P_DPE2P
2 1 AT11 AR16 AU35 VGA_TXOUT0- 24
@ 10K_0402_5% DVPDATA_19 TX2M_DPC0N TXOUT_L0N_DPE2N
22 VRAM_ID0 AR12
DVPDATA_20
22 VRAM_ID1 AW12 AU20 AR37 VGA_TXOUT1+ 24
DVPDATA_21 TXCDP_DPD3P VGA_CRT_R TXOUT_L1P_DPE1P
22 VRAM_ID2 AU12 AT19 1 VGA@ 2 AU39 VGA_TXOUT1- 24
DVPDATA_22 TXCDM_DPD3N R303 150_0402_1% TXOUT_L1N_DPE1N
22 VRAM_ID3 AP12
DVPDATA_23 VGA_CRT_G
AT21 1 VGA@ 2 AP35 VGA_TXOUT2+ 24
TX3P_DPD2P R302 150_0402_1% TXOUT_L2P_DPE0P
AR20 AR35 VGA_TXOUT2- 24
TX3M_DPD2N VGA_CRT_B TXOUT_L2N_DPE0N
1 VGA@ 2
DPD AU22 R301 150_0402_1% AN36
TX4P_DPD1P TXOUT_L3P
AV21 AP37
TX4M_DPD1N TXOUT_L3N
I2C AT23
TX5P_DPD0P
AR22
TX5M_DPD0N
24 VGA_LCD_CLK AK26
SCL
24 VGA_LCD_DATA AJ26
SDA 216-0729002 A12 M96_BGA962
C GPIO_5_AC_BATT AD39 VGA_CRT_R 26 C
GENERAL PURPOSE I/O R
AC (Performance mode) = 3.3 V AD37 M92@
GPU_GPIO0 RB
Battery saving mode = 0.0 V 22
GPU_GPIO0 AH20
GPU_GPIO1 GPIO_0
22
GPU_GPIO1 AH18 AE36 VGA_CRT_G 26
GPU_GPIO2 GPIO_1 G
22
GPU_GPIO2 AN16 AD35
GPIO_2 GB
+3VS_DELAY 1 2 AH23
R99 VGA@ 100K_0402_5% GPIO_3_SMBDATA
AJ23 AF37 VGA_CRT_B 26
GPIO_5_AC_BATT# GPIO_4_SMBCLK B
29,38,40,46,49 ACIN 1 2 AH17 AE38
D13 VGA@ RB751V_SOD323 R101 1 GPIO_5_AC_BATT DAC1 BB
2 10K_0402_5% AJ17
VGA@ GPIO_6
38 VGA_ENBKL AK17 AC36 VGA_CRT_HSYNC 22,26
GPU_GPIO8 GPIO_7_BLON HSYNC
22 GPU_GPIO8 AJ13 AC38 VGA_CRT_VSYNC 22,26
GPU_GPIO9 GPIO_8_ROMSO VSYNC
+3VS_DELAY
VGA_PWRSEL 22 GPU_GPIO9 AH15
AJ16
GPIO_9_ROMSI VGA@
GPIO_10_ROMSCK
High:VGA_CORE 0.95V 22 GPU_GPIO11
GPU_GPIO11
GPU_GPIO12
AK16
GPIO_11 RSET
AB34 1 R80 2
499_0402_1% +1.8VS_PX +AVDD
Low :VGA_CORE 1.2V 22 GPU_GPIO12
GPU_GPIO13
AL16
GPIO_12 +AVDD L61
AVDD=70mA
22 GPU_GPIO13 AM16 AD34
GPIO_13 AVDD
1
GPIO23_CLKREQB GPIO_18_HPD3 2 2 2
@ R335 0_0402_5% @ 1 R100 2 10K_0402_5% GPU_CTF AM17
GPIO_19_CTF 0.1U_0402_16V7K
AL13 AC30
BB_EN GPIO_20_PWRCNTL_1 R2
R334 & R335 be place close AJ14
GPIO_21_BB_EN R2B
AC31
+3VS_DELAY +VDD1DI
CTF (High active) GPIO23_CLKREQB
AK13
AN13
GPIO_22_ROMCSB
AD30 L62
VDD1DI=45mA
GPIO24_TRSTB GPIO_23_CLKREQB G2 1U_0402_6.3V4Z
AM23 AD31 2 1
JTAG_TRSTB G2B
1
+3VS_DELAY AG32 2 2 2
R110 VSS2DI +3VS_DELAY 0.1U_0402_16V7K
499_0402_1%
VGA@ AG33
A2VDD
2
1
AD33 +A2VDDQ
R95 +VGA_VREF A2VDDQ
AH13
VREFG
10K_0402_5% AF33
@ A2VSSQ
1
1
2
@ DDC/AUX AM26
PLL/CLOCK DDC1CLK VGA_CRT_CLK 26
R96 AN26
DDC1DATA VGA_CRT_DATA 26
1K_0402_5% +DPLL_PVDD AM32
DPLL_PVDD
AN32 AM27
DPLL_PVSS AUX1P
Internal 2% downspread (disable) AL27
2
AUX1N
61.9 ohm +DPLL_VDDC AN31 AM19 VGA_HDMI_SCLK 25
DPLL_VDDC DDC2CLK
AL19 VGA_HDMI_SDATA 25
R306 75_0402_1% DDC2DATA
1 2 27MCLK AV33 AN20
19,23 27M_NSSC XTALIN AUX2P
+1.8VS_PX Voltage Swing: 1.8 V AU34 AM20
XTALOUT AUX2N
2
DPLL_PVDD=0.12A VGA@
L66
R305 AL30
1U_0402_6.3V4Z +DPLL_PVDD VGA@ DDCCLK_AUX3P
1 2 AM30
100_0402_5% DDCDATA_AUX3N
75 ohm
MCK1608471YZF 0603 1 1 1 AL29
1
http://rusefix.com
VGA@ VGA@ VGA@ 2008/10/06 2009/10/06 Title
2 2 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 LVDS/HDMI/CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 15 of 57
5 4 3 2 1
5 4 3 2 1
U4D U4C
MEMORY INTERFACE B
MEMORY INTERFACE A
MDA2 E3 P9 MAA2 A35 H24
MDA3 DQB_2 MAB_2 MAA3 DQA_2 MAA_2
E1 DQB_3 MAB_3 N7 E34 DQA_3 MAA_3 J24
MDA4 F1 N8 MAA4 G32 H26
MDA5 DQB_4 MAB_4 MAA5 DQA_4 MAA_4
F3 DQB_5 MAB_5 N9 D33 DQA_5 MAA_5 J26
MDA6 F5 U9 MAA6 F32 H21
MDA7 DQB_6 MAB_6 MAA7 DQA_6 MAA_6
G4 DQB_7 MAB_7 U8 E32 DQA_7 MAA_7 G21
MDA8 H5 Y9 MAA8 D31 H19
MDA9 DQB_8 MAB_8 MAA9 DQA_8 MAA_8
D H6 DQB_9 MAB_9 W9 F30 DQA_9 MAA_9 H20 D
MDA10 J4 AC8 MAA10 C30 L13
MDA11 DQB_10 MAB_10 MAA11 DQA_10 MAA_10
K6 DQB_11 MAB_11 AC9 A30 DQA_11 MAA_11 G16
MDA12 K5 AA7 MAA12 F28 J16
MDA13 DQB_12 MAB_12 BA2 DQA_12 MAA_12
L4 DQB_13 MAB_13/BA2 AA8 C28 DQA_13 MAA_13/BA2 H16
MDA14 M6 Y8 BA0 A28 J17
MDA15 DQB_14 MAB_14/BA0 BA1 DQA_14 MAA_14/BA0
M1 DQB_15 MAB_15/BA1 AA9 E28 DQA_15 MAA_15/BA1 H17
MDA16 M3 D27
DQB_16 DQMA#[7..0] 20,21 DQA_16
MDA17 M5 H3 DQMA#0 F26 A32
MDA18 DQB_17 DQMB_0 DQMA#1 DQA_17 DQMA_0
N4 DQB_18 DQMB_1 H1 C26 DQA_18 DQMA_1 C32
MDA19 P6 T3 DQMA#2 A26 D23
MDA20 DQB_19 DQMB_2 DQMA#3 DQA_19 DQMA_2
P5 DQB_20 DQMB_3 T5 F24 DQA_20 DQMA_3 E22
MDA21 R4 AE4 DQMA#4 C24 C14
MDA22 DQB_21 DQMB_4 DQMA#5 DQA_21 DQMA_4
T6 DQB_22 DQMB_5 AF5 A24 DQA_22 DQMA_5 A14
MDA23 T1 AK6 DQMA#6 E24 E10
MDA24 DQB_23 DQMB_6 DQMA#7 DQA_23 DQMA_6
U4 DQB_24 DQMB_7 AK5 C22 DQA_24 DQMA_7 D9
MAA[12..0] MDA25 V6 A22
MAA[12..0] 20,21 DQB_25 QSA[7..0] 20,21 DQA_25
MDA26 V1 F6 QSA0 F22 C34
BA[2..0] MDA27 DQB_26 QSB_0/RDQSB_0 QSA1 DQA_26 QSA_0/RDQSA_0
BA[2..0] 20,21 V3 DQB_27 QSB_1/RDQSB_1 K3 D21 DQA_27 QSA_1/RDQSA_1 D29
MDA28 Y6 P3 QSA2 A20 D25
MDA29 DQB_28 QSB_2/RDQSB_2 QSA3 DQA_28 QSA_2/RDQSA_2
Y1 DQB_29 QSB_3/RDQSB_3 V5 F20 DQA_29 QSA_3/RDQSA_3 E20
MDA30 Y3 AB5 QSA4 D19 E16
MDA31 DQB_30 QSB_4/RDQSB_4 QSA5 DQA_30 QSA_4/RDQSA_4
Y5 DQB_31 QSB_5/RDQSB_5 AH1 E18 DQA_31 QSA_5/RDQSA_5 E12
MDA32 AA4 AJ9 QSA6 C18 J10
MDA[63..32] MDA33 DQB_32 QSB_6/RDQSB_6 QSA7 DQA_32 QSA_6/RDQSA_6
21 MDA[63..32] AB6 DQB_33 QSB_7/RDQSB_7 AM5 QSA#[7..0] 20,21 A18 DQA_33 QSA_7/RDQSA_7 D7
MDA34 AB1 F18
MDA[31..0] MDA35 DQB_34 QSA#0 DQA_34
20 MDA[31..0] AB3 DQB_35 QSB_0B/W DQSB_0 G7 D17 DQA_35 QSA_0B/W DQSA_0 A34
MDA36 AD6 K1 QSA#1 A16 E30
MDA37 DQB_36 QSB_1B/W DQSB_1 QSA#2 DQA_36 QSA_1B/W DQSA_1
AD1 DQB_37 QSB_2B/W DQSB_2 P1 F16 DQA_37 QSA_2B/W DQSA_2 E26
C MDA38 AD3 W4 QSA#3 D15 C20 C
MDA39 DQB_38 QSB_3B/W DQSB_3 QSA#4 DQA_38 QSA_3B/W DQSA_3
AD5 DQB_39 QSB_4B/W DQSB_4 AC4 E14 DQA_39 QSA_4B/W DQSA_4 C16
MDA40 AF1 AH3 QSA#5 F14 C12
MDA41 DQB_40 QSB_5B/W DQSB_5 QSA#6 DQA_40 QSA_5B/W DQSA_5
AF3 DQB_41 QSB_6B/W DQSB_6 AJ8 D13 DQA_41 QSA_6B/W DQSA_6 J11
MDA42 AF6 AM3 QSA#7 F12 F8
MDA43 DQB_42 QSB_7B/W DQSB_7 DQA_42 QSA_7B/W DQSA_7
AG4 DQB_43 A12 DQA_43
MDA44 AH5 T7 ODTA0 D11 J21
DQB_44 ODTB0 ODTA0 20 DQA_44 ODTA0
MDA45 AH6 W7 ODTA1 F10 G19
DQB_45 ODTB1 ODTA1 21 DQA_45 ODTA1
MDA46 AJ4 A10
MDA47 DQB_46 CLKA0 DQA_46
AK3 DQB_47 CLKB0 L9 CLKA0 20 C10 DQA_47 CLKA0 H27
MDA48 AF8 L8 CLKA0# G13 G27
DQB_48 CLKB0B CLKA0# 20 DQA_48 CLKA0B
MDA49 AF9 H13
MDA50 DQB_49 CLKA1 DQA_49
AG8 DQB_50 CLKB1 AD8 CLKA1 21 J13 DQA_50 CLKA1 J14
MDA51 AG7 AD7 CLKA1# H11 H14
DQB_51 CLKB1B CLKA1# 21 DQA_51 CLKA1B
MDA52 AK9 G10
MDA53 DQB_52 RASA#0 DQA_52
AL7 DQB_53 RASB0B T10 RASA#0 20 G8 DQA_53 RASA0B K23
MDA54 AM8 Y10 RASA#1 K9 K19
DQB_54 RASB1B RASA#1 21 DQA_54 RASA1B
MDA55 AM7 K10
MDA56 DQB_55 CASA#0 DQA_55
AK1 DQB_56 CASB0B W 10 CASA#0 20 G9 DQA_56 CASA0B K20
MDA57 AL4 AA10 CASA#1 A8 K17
DQB_57 CASB1B CASA#1 21 DQA_57 CASA1B
MDA58 AM6 C8
MDA59 DQB_58 CSA0# DQA_58
AM1 DQB_59 CSB0B_0 P10 CSA0# 20 E8 DQA_59 CSA0B_0 K24
MDA60 AN4 L10 A6 K27
MDA61 DQB_60 CSB0B_1 DQA_60 CSA0B_1
AP3 DQB_61 C6 DQA_61
MDA62 AP1 AD10 CSA1# E6 M13
DQB_62 CSB1B_0 CSA1# 21 +1.8VS_PX DQA_62 CSA1B_0
MDA63 AP5 AC10 A5 K16
+3VS_DELAY DQB_63 CSB1B_1 DQA_63 CSA1B_1
U10 CKEA0 L18 K21
CKEB0 CKEA0 20 MVREFDA CKEA0
+VDD_MEM18_REFD Y12 AA11 CKEA1 L20 J20
MVREFDB CKEB1 CKEA1 21 MVREFSA CKEA1
1
B +VDD_MEM18_REFSAA12 B
R87 MVREFSB WEA#0 243_0402_1% 1 R94
W EB0B N10 WEA#0 20 2 @ L27 NC_MEM_CALRN0 W EA0B K26
5.11K_0402_1% AB11 WEA#1 243_0402_1% 1 R105 2 @ N12 L15
W EB1B WEA#1 21 NC_MEM_CALRN1 W EA1B
@ 243_0402_1% 1 R108 2 @ AG12 NC_MEM_CALRN2
AF28
2
1K_0402_1%
VGA@ T8
2
+1.8VS_PX +1.8VS_PX
Close to pin Y12 Close to pin AA12 M92-S2 and M92-M use memory group A only
1
VGA@ VGA@
2
A A
+VDD_MEM18_REFD +VDD_MEM18_REFS
1 1
1
C388 C381
R131 0.1U_0402_16V4Z R127 0.1U_0402_16V4Z
100_0402_1% 100_0402_1%
2 VGA@ 2 VGA@ Security Classification Compal Secret Data Compal Electronics, Inc.
VGA@ VGA@ 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 16 of 57
5 4 3 2 1
http://rusefix.com
5 4 3 2 1
U4H
AP22 AP25
NC_DPD_VDD18#1 NC_DPB_VDD18#1
AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26
+1.1VS_PX
+1.1VS_PX
AN19 AN29
DPD_VSSR#1 DPB_VSSR#1
AP18 AP29
DPD_VSSR#2 DPB_VSSR#2
AP19 AP30
DPD_VSSR#3 DPB_VSSR#3
AW20 AW30
DPD_VSSR#4 DPB_VSSR#4
AW22 AW32
DPD_VSSR#5 DPB_VSSR#5
R316 R308
C 150_0402_1% 150_0402_1% C
1 2 AW18 DPCD_CALR DPAB_CALR AW28 1 2
VGA@ VGA@
DP E/F POWER DP PLL POWER
+DPE_VDD18 AH34 AU28 +DPA_PVDD
DPE_VDD18#1 DPA_PVDD
DPE_VDD18: Output Driver Analog Power Supply. AJ34 DPE_VDD18#2 DPA_PVSS AV27
DPA_PVDD: DP PLL Power 1.8V +/-3%
+1.8VS_PX DPE_VDD18=0.31A +1.8VS_PX
L17 DPA_PVDD=20mA +1.8VS_PX
2 1 1U_0402_6.3V4Z +DPE_VDD18 +DPE_VDD10 AL33 AV29 L68
BLM18PG121SN1D_0603 DPE_VDD10#1 DPB_PVDD +DPA_PVDD 1U_0402_6.3V4Z
AM33 DPE_VDD10#2 DPB_PVSS AR28 2 1
VGA@ 1 1 1 1 1 1 BLM18PG121SN1D_0603
C149 C151 C150 VGA@
C696 C695 C694
10U_0805_10V4Z VGA@ VGA@ AN34 AU18 10U_0603_6.3V6M 0.1U_0402_16V7K
2 2 2 VGA@ DPE_VSSR#1 DPC_PVDD 2 2 2
AP39 AV17
0.1U_0402_16V7K DPE_VSSR#2 DPC_PVSS VGA@ VGA@ VGA@
AR39
DPE_VSSR#3
AU37 DPE_VSSR#4
AW35 DPE_VSSR#5
DPD_PVDD AV19
AR18
DPD_PVSS
+DPE_VDD18 AF34 DPF_VDD18#1
AG34 DPF_VDD18#2
DPE_VDD10: Output Driver Analog Power Supply. AM37 +DPE_PVDD
DPE_PVDD
DPE_PVSS
AN38 DPE_PVDD: DP PLL Power 1.8V +/-3%
+1.1VS_PX DPE_VDD10=0.27A
L20 +DPE_VDD10 AK33 DPE_PVDD=20mA +1.8VS_PX
1U_0402_6.3V4Z +DPE_VDD10 DPF_VDD10#1 L18
2 1 AK34
BLM18PG121SN1D_0603 DPF_VDD10#2 +DPE_PVDD +DPE_PVDD 1U_0402_6.3V4Z
AL38 2 1
B VGA@ NC_DPF_PVDD BLM18PG121SN1D_0603 B
1 1 1 NC_DPF_PVSS AM35 1 1 1
C192 C188 C187 VGA@
AF39 C165 C168 C166
10U_0805_10V4Z VGA@ VGA@ VGA@ DPF_VSSR#1 10U_0603_6.3V6M 0.1U_0402_16V7K
AH39 DPF_VSSR#2
2 2 2 0.1U_0402_16V7K AK39 2 2 2
DPF_VSSR#3 VGA@ VGA@ VGA@
AL34 DPF_VSSR#4
AM34 DPF_VSSR#5
R304
150_0402_1%
1 2 AM39
DPEF_CALR
VGA@
216-0729002 A12 M96_BGA962
M92@
A A
http://rusefix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 DRX PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, January 15, 2009 Sheet 17 of 57
5 4 3 2 1
5 4 3 2 1
U4E
+1.8VS_PX +PCIE_VDDR_M92 +1.8VS_PX
MEM I/O
PCIE VGA@
VDDR1+VDDRHA+VDDRHB=TBD(2.9A/M96) PCIE_VDDR=0.5A
AC7 AA31 2 1
VDDR1#1 PCIE_VDDR#1 L22 BLM18PG121SN1D_0603
AD11 VDDR1#2 PCIE_VDDR#2 AA32
1 1 2 1 2 1 2 AF7 VDDR1#3 PCIE_VDDR#3 AA33 PCIE_VDDR:PCI-E I/O power. 1 2
C331 10U_0603_6.3V6M VGA@ C339 1U_0402_6.3V4Z VGA@ C378 1U_0402_6.3V4Z VGA@ AG10 AA34 C221 10U_0603_6.3V6M VGA@
+ VDDR1#4 PCIE_VDDR#4
1 2 1 2 1 2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1 2
C355 330U_V_2.5VM_R9M C239 10U_0603_6.3V6M VGA@ C373 1U_0402_6.3V4Z VGA@ C363 1U_0402_6.3V4Z VGA@ AK8 W29 C237 1U_0402_6.3V4Z VGA@
VGA@ VDDR1#6 PCIE_VDDR#6
1 2 1 2 1 2 AL9 VDDR1#7 PCIE_VDDR#7 W30 1 2
2 C314 10U_0603_6.3V6M VGA@ C370 1U_0402_6.3V4Z VGA@ C362 1U_0402_6.3V4Z VGA@ G11 Y31 PCIE_VDDC: PCI-E Digital Power Supply C193 1U_0402_6.3V4Z VGA@
VDDR1#8 PCIE_VDDR#8
1 2 1 2 1 2 G14 VDDR1#9 1 2
D C376 10U_0603_6.3V6M VGA@ C357 1U_0402_6.3V4Z VGA@ C369 1U_0402_6.3V4Z VGA@ G17 +1.1VS_PX C199 1U_0402_6.3V4Z VGA@ D
VDDR1#10
1 2 1 2 1 2 G20 VDDR1#11 PCIE_VDDC#1 G30 1 2
C389 10U_0603_6.3V6M VGA@ C361 1U_0402_6.3V4Z VGA@ C426 1U_0402_6.3V4Z VGA@ G23 G31 PCIE_VDDC=2A C236 1U_0402_6.3V4Z VGA@
VDDR1#12 PCIE_VDDC#2
1 2 1 2 G26 VDDR1#13 PCIE_VDDC#3 H29 1 2
C371 1U_0402_6.3V4Z VGA@ C372 1U_0402_6.3V4Z VGA@ G29 H30 C213 1U_0402_6.3V4Z VGA@
VDDR1#14 PCIE_VDDC#4
1 2 1 2 H10 VDDR1#15 PCIE_VDDC#5 J29 1 2 1 2
C326 1U_0402_6.3V4Z VGA@ C293 1U_0402_6.3V4Z VGA@ J7 J30 C196 10U_0603_6.3V6M VGA@ C212 0.1U_0402_16V7K VGA@
VDDR1#16 PCIE_VDDC#6
1 2 1 2 J9 VDDR1#17 PCIE_VDDC#7 L28 1 2 1 2
C283 1U_0402_6.3V4Z VGA@ C282 1U_0402_6.3V4Z VGA@ K11 M28 C233 1U_0402_6.3V4Z VGA@ C232 0.1U_0402_16V7K VGA@
VDDR1#18 PCIE_VDDC#8
1 2 1 2 K13 VDDR1#19 PCIE_VDDC#9 N28 1 2
C338 1U_0402_6.3V4Z VGA@ C292 1U_0402_6.3V4Z VGA@ K8 R28 C229 1U_0402_6.3V4Z VGA@ +VGA_CORE
VDDR1#20 PCIE_VDDC#10
1 2 1 2 L12 T28 1 2
C342 1U_0402_6.3V4Z VGA@ C350 1U_0402_6.3V4Z VGA@ VDDR1#21 PCIE_VDDC#11 C242 1U_0402_6.3V4Z VGA@
L16 U28
VDDR1#22 PCIE_VDDC#12
L21 1 2
VDDR1#23 C220 1U_0402_6.3V4Z VGA@
L23 1 1
VDDR1#24
L26 VDDR1#25 VDDC#1 AA15 1 2
L7 CORE AA17 C216 1U_0402_6.3V4Z VGA@ + C243 + C333
VDDR1#26 VDDC#2 330U_V_2.5VM_R9M 330U_V_2.5VM_R9M
VDD_CT:Level translation between core and I/O M11 VDDR1#27 VDDC#3 AA20 1 2
N11 AA22 C217 1U_0402_6.3V4Z VGA@ VGA@ VGA@
+1.8VS_PX VDDR1#28 VDDC#4 2 2
VGA@
VDD_CT=0.11A P7 VDDR1#29 VDDC#5 AA24 1
C202
2
1U_0402_6.3V4Z VGA@
R11 AA27
+VDD_CT VDDR1#30 VDDC#6
2 1 U11 VDDR1#31 VDDC#7 AB13
L69 BLM18PG121SN1D_0603 U7 AB16
VDDR1#32 VDDC#8
1 2 Y11 VDDR1#33 VDDC#9 AB18 1 2 1 2 1 2
C706 10U_0603_6.3V6M VGA@ Y7 AB21 C311 10U_0603_6.3V6M VGA@ C352 1U_0402_6.3V4Z VGA@ C337 1U_0402_6.3V4Z VGA@
VDDR1#34 VDDC#10
1 2 AB23 1 2 1 2 1 2
C271 1U_0402_6.3V4Z VGA@ VDDC#11 C312 10U_0603_6.3V6M VGA@ C343 1U_0402_6.3V4Z VGA@ C329 1U_0402_6.3V4Z VGA@
AB26
VDDC#12
1 2 AB28 1 2 1 2 1 2
C703 1U_0402_6.3V4Z VGA@ VDDC#13 C313 10U_0603_6.3V6M VGA@ C279 1U_0402_6.3V4Z VGA@ C353 1U_0402_6.3V4Z VGA@
AC12
LEVEL VDDC#14
1 2 AC15 1 2 1 2 1 2
C702 1U_0402_6.3V4Z VGA@ TRANSLATION VDDC#15 C263 10U_0603_6.3V6M VGA@ C291 1U_0402_6.3V4Z VGA@ C240 1U_0402_6.3V4Z VGA@
VDDC#16 AC17
POWER
C 1 2 +VDD_CT AF26 AC20 1 2 1 2 1 2 C
C245 0.1U_0402_16V7K VGA@ VDD_CT#1 VDDC#17 C264 10U_0603_6.3V6M VGA@ C299 1U_0402_6.3V4Z VGA@ C322 1U_0402_6.3V4Z VGA@
AF27 VDD_CT#2 VDDC#18 AC22
AG26 VDD_CT#3 VDDC#19 AC24 1 2 1 2 1 2
AG27 AC27 C265 10U_0603_6.3V6M VGA@ C336 1U_0402_6.3V4Z VGA@ C285 1U_0402_6.3V4Z VGA@
VDD_CT#4 VDDC#20
VDDR3:ROM+Sync+DDC VDDC#21 AD13 1 2 1 2 1 2
+3VS_DELAY AD16 C262 10U_0603_6.3V6M VGA@ C298 1U_0402_6.3V4Z VGA@ C321 1U_0402_6.3V4Z VGA@
I/O VDDC#22
VDDR5 for DVPDATA[0..11] VDDR3=50mA VDDC#23 AD18 1 2 1 2 1 2
AF23 AD21 C252 1U_0402_6.3V4Z VGA@ C328 1U_0402_6.3V4Z VGA@ C316 1U_0402_6.3V4Z VGA@
+1.8VS_PX VDDR3#1 VDDC#24
L32 BLM18PG121SN1D_0603
VDDR5=0.17A 1
C266
2
10U_0603_6.3V6M VGA@
AF24
VDDR3#2 VDDC#25
AD23 1
C289
2
1U_0402_6.3V4Z VGA@
1
C270
2
1U_0402_6.3V4Z
1
VGA@ C251
2
1U_0402_6.3V4Z VGA@
AG23 VDDR3#3 VDDC#26 AD26
2 1 1U_0402_6.3V4Z +VDDR5 1 2 AG24 AF17 1 2 1 2 1 2
VGA@ C259 1U_0402_6.3V4Z VGA@ VDDR3#4 VDDC#27 C351 1U_0402_6.3V4Z VGA@ C269 1U_0402_6.3V4Z VGA@ C248 1U_0402_6.3V4Z VGA@
2 2 2 VDDC#28 AF20
1 2 AF22 1 2 1 2
C364 C366 C365 C258 1U_0402_6.3V4Z VGA@ VDDC#29 C284 1U_0402_6.3V4Z VGA@ C296 1U_0402_6.3V4Z VGA@
AF13 AG16
VGA@ VGA@ VGA@ VDDR5#1 VDDC#30
1 2 AF15 VDDR5#2 VDDC#31 AG18 1 2 1 2
1 1 1 C260 1U_0402_6.3V4Z VGA@ AG13 AG21 C335 1U_0402_6.3V4Z VGA@ C334 1U_0402_6.3V4Z VGA@
10U_0603_6.3V6M 0.1U_0402_16V7K +VDDR5 VDDR5#3 VDDC#32
AG15 AH22 1 2 1 2
VDDR5#4 VDDC#33 C320 1U_0402_6.3V4Z VGA@ C297 1U_0402_6.3V4Z VGA@
M16
+1.8VS_PX VDDC#34
VDDR4=0.17A VDDRHA:MCLK PAD Power VDDC#35 M18 1 2 1 2
L34 BLM18PG121SN1D_0603 AD12 M23 C286 1U_0402_6.3V4Z VGA@ C267 1U_0402_6.3V4Z VGA@
1U_0402_6.3V4Z +VDDR4 +VDDR4 VDDR4#1 VDDC#36
2
VGA@
1
+1.8VS_PX VDDRHA=20mA AF11 VDDR4#2 VDDC#37 M26 1
C247
2
1U_0402_6.3V4Z
1
VGA@ C268
2
1U_0402_6.3V4Z VGA@
2 2 2 AF12 N15
VDDR4#3 VDDC#38
VDDRHA for M96 ONLY AG11
VDDR4#4 VDDC#39
N17 1 2 1 2
C377 C374 C375 L26 @ BLM18PG121SN1D_0603 N20 VDDC+VDDCI=16A C287 1U_0402_6.3V4Z VGA@ C250 1U_0402_6.3V4Z VGA@
VGA@ VGA@ VGA@ +VDDARHA VDDC#40
2 1 VDDC#41 N22 1 2 1 2
1 1 1 1 2 N24 C275 1U_0402_6.3V4Z VGA@ C261 1U_0402_6.3V4Z VGA@
10U_0603_6.3V6M 0.1U_0402_16V7K C304 @ 1U_0402_6.3V4Z MEM CLK VDDC#42
N27 1 2 1 2
VDDC#43 C332 1U_0402_6.3V4Z VGA@ C323 1U_0402_6.3V4Z VGA@
+1.8VS_PX VDDRHB=20mA M20
VDDRHA VDDC#44
R13
M21 R16 1 2 1 2
VSSRHA VDDC#45
VDDR4 for DVPDATA[12..23] VGA@
VDDC#46
R18 C288 1U_0402_6.3V4Z VGA@ C315 1U_0402_6.3V4Z VGA@
L33 BLM18PG121SN1D_0603 R21 1 2 1 2
B +VDDARHB VDDC#47 C330 1U_0402_6.3V4Z VGA@ C346 1U_0402_6.3V4Z B
VGA@
2 1 V12 VDDRHB VDDC#48 R23
1 2 U12 VSSRHB VDDC#49 R26
C349 1U_0402_6.3V4Z T15
VGA@ VDDC#50
VDDC#51 T17
VDDRHB:MCLK PAD Power VDDC#52
T20
+1.8VS_PX T22
L60 BLM18PG121SN1D_0603 PLL VDDC#53
1U_0402_6.3V4Z
PCIE_PVDD=40mA +PCIE_PVDD VDDC#54 T24
2 1 AB37 PCIE_PVDD VDDC#55 T27
VGA@ 2 2 2 PCIE_PVDD:PCI-E PLL power. U16
VDDC#56
H7 U18
C669 C679 C675 NC_MPV18#1 VDDC#57
H8 U21
VGA@ VGA@ VGA@ NC_MPV18#2 VDDC#58
VDDC#59 U23
1 1 1 U26
+VGA_CORE 10U_0603_6.3V6M 0.1U_0402_16V7K VDDC#60
SPV10=414mA AM10
NC_SPV18 VDDC#61
V15
VDDC#62 V17
2 1 1U_0402_6.3V4Z +SPV10 AN9 V20
L30 BLM18PG121SN1D_0603 2 SPV10 VDDC#63
2 2 VDDC#64 V22
VGA@ AN10 V24
C348 C360 C359 SPVSS VDDC#65
V27
VGA@ VGA@ VGA@ VDDC#66
VDDC#67 Y16
1 1 1 Y18
10U_0603_6.3V6M 0.1U_0402_16V7K VDDC#68
Y21
BACK BIAS VDDC#69
Y23
+VGA_CORE VDDC#70
SPV10: Dedicated power pin for memory BBP=0.12A VDDC#71
Y26
and engine PLLs. AA13 BBP#1 VDDC#72 Y28 VDDCI: Isolated (clean) core power for the l/O logic
Y13 AH27 +VGA_CORE
BBP#2 VDDC#73
2 2 AH28
VDDC#74 VGA@
C327 C318 M15 +VDDCI 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1
VGA@ VGA@ ISOLATED VDDCI#1 N13 2 2 2 2 L31 BLM18PG121SN1D_0603
1 1 CORE I/O VDDCI#2 R12
A VDDCI#3 A
1U_0402_6.3V4Z 0.1U_0402_16V7K T12 C347 C356 C344 C358
VDDCI#4
1 1 1 1
VGA@ VGA@ VGA@ VGA@
216-0729002 A12 M96_BGA962 M92@ 1U_0402_6.3V4Z 10U_0603_6.3V6M
http://rusefix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, January 15, 2009 Sheet 18 of 57
5 4 3 2 1
5 4 3 2 1
U4F
S
D
GND#123 GND#64 +3VS
L2 AL32
GND#124 GND#65 SI2301BDS_SOT23
L22 AL6
GND#125 GND#66
2
L24 AL8 VGA@ R142
G
2
GND#126 GND#67 100K_0402_5%
L6 AM11
GND#127 GND#68 VGA@
M17 GND#128 GND#69 AM31
M22 AM9
GND#129 GND#70
M24 AN11
1
GND#130 GND#71
N16 AN2
GND#131 GND#72
N18 AN30 38 PX_+3VS 1 @ 2 PX_+3VS_R
GND#132 GND#73 R467 0_0402_5%
N2 AN6
B GND#133 GND#74 B
N21 GND#134 GND#75 AN8
1
D
N23 GND#135 GND#76 AP11
N26 AP7 +3VS 1 2 2 Q16
GND#136 GND#77 R151 4.7K_0402_5% G 2N7002_SOT23
N6 GND#137 GND#78 AP9
R15 AR5 VGA@ S VGA@
3
GND#138 GND#79
R17 AW34
GND#139 GND#80
R2 B11 1
GND#140 GND#81
R20 B13
GND#141 GND#82 @ C405
R22 B15
GND#142 GND#83 0.01U_0402_25V7K
R24 GND#143 GND#84 B17
2
R27 GND#144 GND#85 B19
R6 B21
GND#145 GND#86
T11 GND#146 GND#87 B23
T13 B25
GND#147 GND#88
T16 GND#148 GND#89 B27
T18
GND#149 GND#90
B29 Use Delay 3.3V BUS (VDDR3) for GPIO/DDC Pull up to reduce Leakage to VDDR3 Bus.
T21 B31
GND#150 GND#91
T23 B33
GND#151 GND#92
T26 B7
GND#152 GND#93
U15 B9
GND#153 GND#94
U17 C1
GND#154 GND#95
U2 GND#155 GND#96 C39
U20 E35
GND#156 GND#97
U22 GND#157 GND#98 E5
U24 F11
GND#158 GND#99
U27 F13
GND#159 GND#100
U6 GND#160
V11
GND#161
V16
GND#162
V18
GND#163
V21
GND#164
V23 GND#165
A A
V26
GND#166
W2 GND#167
W6 GND#168
Y15
GND#169
Y17 GND#170
Y20
GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24
Y27
GND#173
GND#174
VSS_MECH#2
VSS_MECH#3
AW1
AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13 GND#175 Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
http://rusefix.com
V13 GND#176
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
216-0729002 A12 M96_BGA962 Custom 0.1
M92@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 19 of 57
5 4 3 2 1
5 4 3 2 1
U6 U5
BA0 L2 B9 MDA21 BA0 L2 B9 MDA3 BA[2..0]
BA0 DQ15 BA0 DQ15 16,21 BA[2..0]
BA1 L3 B1 MDA19 BA1 L3 B1 MDA5
D BA1 DQ14 MDA20 BA1 DQ14 MDA1 QSA[7..0] D
DQ13 D9 DQ13 D9 16,21 QSA[7..0]
MAA12 R2 D1 MDA16 MAA12 R2 D1 MDA6
MAA11 A12 DQ12 MDA17 MAA11 A12 DQ12 MDA4 QSA#[7..0]
P7 A11 DQ11 D3 Group2 P7 A11 DQ11 D3 Group0 16,21 QSA#[7..0]
MAA10 M2 D7 MDA22 MAA10 M2 D7 MDA0
MAA9 A10/AP DQ10 MDA18 MAA9 A10/AP DQ10 MDA7 DQMA#[7..0]
P3 C2 P3 C2 16,21 DQMA#[7..0]
MAA8 A9 DQ9 MDA23 MAA8 A9 DQ9 MDA2
P8 A8 DQ8 C8 P8 A8 DQ8 C8
MAA7 P2 F9 MDA12 MAA7 P2 F9 MDA27 MAA[12..0]
MAA6 A7 DQ7 MDA10 MAA6 A7 DQ7 MDA31 16,21 MAA[12..0]
N7 A6 DQ6 F1 N7 A6 DQ6 F1
MAA5 N3 H9 MDA15 MAA5 N3 H9 MDA24 MDA[63..0]
A5 DQ5 A5 DQ5 16,21 MDA[63..0]
MAA4 N8 H1 MDA8 MAA4 N8 H1 MDA28
MAA3 A4 DQ4 MDA11 MAA3 A4 DQ4 MDA29
N2 A3 DQ3 H3 Group1 N2 A3 DQ3 H3 Group3
MAA2 M7 H7 MDA14 MAA2 M7 H7 MDA25 ODTA0
MAA1 A2 DQ2 MDA9 MAA1 A2 DQ2 MDA30 16 ODTA0
M3 A1 DQ1 G2 M3 A1 DQ1 G2
MAA0 M8 G8 MDA13 MAA0 M8 G8 MDA26 CKEA0
A0 DQ0 A0 DQ0 16 CKEA0
RASA#0
CLKA0# CLKA0# 16 RASA#0
K8 CK VDDQ1 A9 +1.8VS_PX K8 CK VDDQ1 A9 +1.8VS_PX
CLKA0 J8 C1 CLKA0 J8 C1 CASA#0
CK VDDQ2 CK VDDQ2 16 CASA#0
VDDQ3 C3 VDDQ3 C3
CKEA0 K2 C7 CKEA0 K2 C7 WEA#0
CKE VDDQ4 CKE VDDQ4 16 WEA#0
C9 C9
VDDQ5 VDDQ5 CSA0#
E9 E9 16 CSA0#
VDDQ6 VDDQ6
VDDQ7 G1 VDDQ7 G1
CSA0# L8 G3 CSA0# L8 G3
CS VDDQ8 CS VDDQ8
G7 G7
WEA#0 VDDQ9 WEA#0 VDDQ9
K3 WE VDDQ10 G9 K3 WE VDDQ10 G9
RASA#0 K7 A1 RASA#0 K7 A1
RAS VDD1 RAS VDD1
VDD2 E1 VDD2 E1
CASA#0 L7 J9 CASA#0 L7 J9
CAS VDD3 CAS VDD3
M9 M9
DQMA#1 VDD4 DQMA#3 VDD4
F3 R1 F3 R1
C DQMA#2 LDM VDD5 DQMA#0 LDM VDD5 C
B3 UDM B3 UDM
J1 0.1U_0402_16V4Z +1.8VS_PX J1 0.1U_0402_16V4Z +1.8VS_PX
VDDL VDDL
J7 1 1 J7 1 1
ODTA0 VSSDL ODTA0 VSSDL
K9 ODT K9 ODT
C745 C734 C412 C399
VGA@ VGA@ VGA@ VGA@
+1.8VS_PX QSA1 2 2 1U_0402_6.3V4Z QSA3 2 2 1U_0402_6.3V4Z
F7 LDQS F7 LDQS
QSA#1 E8 A7 +1.8VS_PX QSA#3 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
B8 B8
VSSQ3 VSSQ3
1
1
VSSQ4 D2 VSSQ4 D2
R349 QSA2 B7 D8 R160 QSA0 B7 D8
4.99K_0402_1% VGA@ QSA#2 UDQS VSSQ5 4.99K_0402_1% VGA@ QSA#0 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
F2 F2 CLKA0
VSSQ7 VSSQ7 16 CLKA0
F8 F8
2
2
+VRAM_REF1 VSSQ8 +VRAM_REF2 VSSQ8 CLKA0#
J2 H2 J2 H2 16 CLKA0#
VREF VSSQ9 VREF VSSQ9
H8 H8
VSSQ10 VSSQ10
1
1
1 A2 1 A2
R353 NC#A2 R162 NC#A2 R164 R161
E2 A3 E2 A3
4.99K_0402_1% BA2 NC#E2 VSS1 4.99K_0402_1% BA2 NC#E2 VSS1 56_0402_5% 56_0402_5%
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
C748 R3 J3 C418 R3 J3
VGA@ 2 0.1U_0402_16V4Z NC#R3 VSS3 VGA@ 2 0.1U_0402_16V4Z NC#R3 VSS3 VGA@ VGA@
R7 N1 R7 N1
2
2
VGA@ NC#R7 VSS4 VGA@ NC#R7 VSS4
R8 P9 R8 P9
NC#R8 VSS5 NC#R8 VSS5
HYB18T256161BF-25 HYB18T256161BF-25 1
VRAM@ VRAM@ C419
470P_0402_50V7K
A A
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 20 of 57
5 4 3 2 1
5 4 3 2 1
D U7 U8 D
BA0 L2 B9 MDA48 BA0 L2 B9 MDA45
BA1 BA0 DQ15 MDA52 BA1 BA0 DQ15 MDA43
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 MDA49 D9 MDA47
MAA12 DQ13 MDA54 MAA12 DQ13 MDA41
R2 D1 R2 D1
MAA11 A12 DQ12 MDA53 MAA11 A12 DQ12 MDA42 BA[2..0]
P7 A11 DQ11 D3 Group6 P7 A11 DQ11 D3 Group5 16,20 BA[2..0]
MAA10 M2 D7 MDA50 MAA10 M2 D7 MDA46
MAA9 A10/AP DQ10 MDA55 MAA9 A10/AP DQ10 MDA40 DQMA#[7..0]
P3 A9 DQ9 C2 P3 A9 DQ9 C2 16,20 DQMA#[7..0]
MAA8 P8 C8 MDA51 MAA8 P8 C8 MDA44
MAA7 A8 DQ8 MDA34 MAA7 A8 DQ8 MDA60 MAA[12..0]
P2 F9 P2 F9 16,20 MAA[12..0]
MAA6 A7 DQ7 MDA37 MAA6 A7 DQ7 MDA58
N7 A6 DQ6 F1 N7 A6 DQ6 F1
MAA5 N3 H9 MDA33 MAA5 N3 H9 MDA63 QSA#[7..0]
MAA4 A5 DQ5 MDA35 MAA4 A5 DQ5 MDA56 16,20 QSA#[7..0]
N8 A4 DQ4 H1 N8 A4 DQ4 H1
MAA3 N2 H3 MDA39 Group4 MAA3 N2 H3 MDA59 Group7 QSA[7..0]
MAA2 A3 DQ3 MDA32 MAA2 A3 DQ3 MDA61 16,20 QSA[7..0]
M7 H7 M7 H7
MAA1 A2 DQ2 MDA38 MAA1 A2 DQ2 MDA57 MDA[63..0]
M3 G2 M3 G2 16,20 MDA[63..0]
MAA0 A1 DQ1 MDA36 MAA0 A1 DQ1 MDA62
M8 A0 DQ0 G8 M8 A0 DQ0 G8
ODTA1
16 ODTA1
CLKA1# K8 A9 +1.8VS_PX CLKA1# K8 A9 +1.8VS_PX CKEA1
CK VDDQ1 CK VDDQ1 16 CKEA1
CLKA1 J8 C1 CLKA1 J8 C1
CK VDDQ2 CK VDDQ2 RASA#1
C3 C3 16 RASA#1
CKEA1 VDDQ3 CKEA1 VDDQ3
K2 CKE VDDQ4 C7 K2 CKE VDDQ4 C7
C9 C9 CASA#1
VDDQ5 VDDQ5 16 CASA#1
E9 E9
VDDQ6 VDDQ6 WEA#1
VDDQ7 G1 VDDQ7 G1 16 WEA#1
CSA1# L8 G3 CSA1# L8 G3
CS VDDQ8 CS VDDQ8 CSA1#
G7 G7 16 CSA1#
WEA#1 VDDQ9 WEA#1 VDDQ9
K3 WE VDDQ10 G9 K3 WE VDDQ10 G9
RASA#1 K7 A1 RASA#1 K7 A1
RAS VDD1 RAS VDD1
E1 E1
C CASA#1 VDD2 CASA#1 VDD2 C
L7 CAS VDD3 J9 L7 CAS VDD3 J9
M9 M9
DQMA#4 VDD4 DQMA#7 VDD4
F3 R1 F3 R1
DQMA#6 LDM VDD5 DQMA#5 LDM VDD5
B3 UDM B3 UDM
J1 0.1U_0402_16V4Z +1.8VS_PX J1 0.1U_0402_16V4Z +1.8VS_PX
VDDL VDDL
J7 1 1 J7 1 1
ODTA1 VSSDL ODTA1 VSSDL
K9 ODT K9 ODT
VGA@ C744 VGA@ C414 C417
+1.8VS_PX C739 VGA@ VGA@
QSA4 F7 2 2 1U_0402_6.3V4Z +1.8VS_PX QSA7 F7 2 2 1U_0402_6.3V4Z
QSA#4 LDQS QSA#7 LDQS
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7
B2 B2
VSSQ2 VSSQ2
1
VSSQ3 B8 VSSQ3 B8
1
R347 D2 D2
4.99K_0402_1% QSA6 VSSQ4 R163 QSA5 VSSQ4
B7 D8 B7 D8
VGA@ QSA#6 UDQS VSSQ5 4.99K_0402_1% VGA@ QSA#5 UDQS VSSQ5
A8 E7 A8 E7
UDQS VSSQ6 UDQS VSSQ6
F2 F2
2
VSSQ7 VSSQ7
F8 F8
2
+VRAM_REF3 VSSQ8 +VRAM_REF4 VSSQ8
J2 H2 J2 H2
VREF VSSQ9 VREF VSSQ9
VSSQ10 H8 VSSQ10 H8
1
1
1 A2 1 A2
R348 NC#A2 R165 NC#A2
E2 A3 E2 A3
4.99K_0402_1% BA2 NC#E2 VSS1 4.99K_0402_1% BA2 NC#E2 VSS1
L1 E3 L1 E3
C747 NC#L1 VSS2 C420 NC#L1 VSS2 CLKA1
R3 J3 R3 J3 16 CLKA1
VGA@ 2 0.1U_0402_16V4Z NC#R3 VSS3 VGA@ 2 0.1U_0402_16V4Z NC#R3 VSS3
R7 N1 R7 N1
2
2
VGA@ NC#R7 VSS4 VGA@ NC#R7 VSS4 CLKA1#
R8 P9 R8 P9 16 CLKA1#
NC#R8 VSS5 NC#R8 VSS5
1
HYB18T256161BF-25 HYB18T256161BF-25 R351 R350
VRAM@ VRAM@ 56_0402_5% 56_0402_5%
VGA@ VGA@
2
B B
1
C746
470P_0402_50V7K
2
VGA@
+1.8VS_PX +1.8VS_PX
1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
C750 C754 C735 C731 C729 C738 C737 C733 C425 C422 C408 C413 C411 C401 C395 C398
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A A
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 21 of 57
5 4 3 2 1
5 4 3 2 1
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
STRAPS +3VS_DELAY THEY MUST NOT CONFLICT DURING RESET
15 GPU_GPIO0 GPU_GPIO0 VGA@ R123 2 1 10K_0402_5% 1 : PCIe bus Full Tx output swing
GPU_GPIO1 VGA@ R133 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 Transmitter Power Savings Enable
D 15 GPU_GPIO1 D
GPU_GPIO2 VGA@ R125 2 1 10K_0402_5% 0 : PCIe bus 50% Tx output swing
15 GPU_GPIO2
1 : Tx de-emphasis enabled
TX_DEEMPH_EN GPIO1 PCI Express Transmitter De-emphasis Enable
15 GPU_GPIO8 GPU_GPIO8 @ R463 2 1 10K_0402_5% 0 : Tx de-emphasis disabled
GPU_GPIO9 @ R134 2 1 10K_0402_5% PCIE GNE2 ENABLED
15 GPU_GPIO9
15 GPU_GPIO11 GPU_GPIO11 VGA@ R130 2 1 10K_0402_5% BIF_GEN2_EN_A GPIO2 0 = Advertises the PCIe device as 2.5 GT/s capable at power-on.
GPU_GPIO12 @ R129 2 1 10K_0402_5% 1 = Advertises the PCIe device as 5.0 GT/s capable at power-on. 0 (5.0 GT/s capability will be controlled by software)
15 GPU_GPIO12
GPU_GPIO13 @ R126 2 1 10K_0402_5%
15 GPU_GPIO13
0 : VGA Controller capacity enabled
VGA Disable determines whether or not the card will
VSYNC_DAC1 and HSYNC_DAC1 VGA_DIS GPIO9 be recognized as the system's VGA controller 1 : The device will not be recognized as the system’s
VGA@ R300 2 1 10K_0402_5% VGA controller
15,26 VGA_CRT_VSYNC
VGA@ R299 2 1 10K_0402_5%
pull up for HDMI & DISPLAYPORT
15,26 VGA_CRT_HSYNC
15 VSYNC_DAC2 @ R81 2 1 10K_0402_5% Audio codec enable
15 HSYNC_DAC2 @ R84 2 1 10K_0402_5% CONFIG(2:0) GPIO[13:11] Size of the primary memory apertures 0 0 1
VIP_DEVICE_STRAP_EN V2SYNC 0
AUD[1] AUD[0]
AUD[1] HSYNC 0 0 No audio function
1
0 1 Audio for DisplayPort and HDMI if dongle is detected 11
R150 AUD[0] VSYNC 1 0 Audio for DisplayPort only
10K_0402_5% 1 1 Audio for both DisplayPort and HDMI
VGA@
1
+3VS RESERVED GPIO21 0
R146
10K_0402_5% 0: Disable external BIOS ROM device
C VGA@ BIOS_ROM_EN GPIO_22_ROMCSB C
1: Enable external BIOS ROM device
2
CCBYPASS GENERICC IGNORE VIP DEVICE STRAPS 0
EC_SMB_CK2_PX 6 1 EC_SMB_CK2 6,38
External VGA Thermal Sensor
5
Q48A BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
2N7002DW-T/R7_SOT363-6
EC_SMB_DA2_PX VGA@ 3 4 EC_SMB_DA2 6,38
+3VS_DELAY Q48B
2N7002DW-T/R7_SOT363-6 AMD RESERVED CONFIGURATION STRAPS
VGA@
2 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
VGA@ C305
THEY MUST NOT CONFLICT DURING RESET
0.1U_0402_16V4Z
1
U12 H2SYNC GENERICC
1 8 EC_SMB_CK2_PX
VCC SMBCLK
2 7 EC_SMB_DA2_PX PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
15 GPU_THERMAL_D+ DXP SMBDATA
C306 VGA@
1 2 3 6 THM_ALERT# 15
THEY MUST NOT CONFLICT DURING RESET
DXN ALERT
2200P_0402_50V7K 4 5 +3VS_DELAY
15 GPU_THERMAL_D- THERM GND VGA@ GPIO_28_TDO GPIO21_BB_EN
1 2
G781-1_SOP8 R85 4.7K_0402_5%
VGA@
VRAM@ VRAM@ STRAPS PIN GPU Project VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 3,2,1,0
R323 10K_0402_5% R319 10K_0402_5%
2 1 +1.8VS_PX 2 1 +1.8VS_PX JV40-PU_KBLG0 512M(x4) Samsung 64Mx16 1.8V (Q-die) SA00002MD00 0000
VRAM@ VRAM@
R321 10K_0402_5% R317 10K_0402_5%
2 1 +1.8VS_PX 2 1 +1.8VS_PX
VRAM_ID2 15 VRAM_ID3 15
1 2 1 2
R322 10K_0402_5% R318 10K_0402_5%
VRAM@ VRAM@
A A
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M92 Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 22 of 57
5 4 3 2 1
5 4 3 2 1
+3VS_CLK
L41
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 C483 C476 C480 C526 C479 C498 C511 C477 C508 C528 C474
L40
1 2 +3VS_CLKVDDA
+3VS +3VS_CLK
FBMA-L11-201209-221LMA30T_0805
1 1 U18
1
C463
CLK_XTAL_OUT 22U_0805_10V4Z C473 R178
0.1U_0402_16V4Z ICS 9LPRS488 8.2K_0402_5%
CLK_XTAL_IN 2 2 49 1
VDDA SMBCLK ICH_SMBCLK0 8,9,28,36
48 2
2
GNDA SMBDAT ICH_SMBDATA0 8,9,28,36
SRC_SLOW
62 41 SRC_SLOW
+3VS_CLK VDDREF SB_SRC_SLOW#
Y1 66 GNDREF
1
2 1
2 1 C500 0.1U_0402_16V4Z R177
+VDDCLK_IO 12 56 @ 8.2K_0402_5%
VDDSRC_IO CPUKG0T_LPRS CLK_CPU_BCLK 6
14.31818MHZ_20P_6X14300202 18 55 CPU
VDDSRC_IO CPUKG0C_LPRS CLK_CPU_BCLK# 6
1 1 28
2
C518 C517 VDDATIG_IO
37 VDDSB_SRC_IO
53 VDDCPU_IO HTT0T_LPRS / 66 M 60 CLK_NBHT 11
22P_0402_50V8J 22P_0402_50V8J 59
2 2 +3VS_CLK HTT0C_LPRS / 66 M CLK_NBHT# 11
C C
+3VS_CLK 3 VDDDOT
17 40
VDDSRC SB_SRC0T_LPRS
Routing the trace at least 10mil 29
VDDATIG SB_SRC0C_LPRS
39
R175 8.2K_0402_5%
R176 8.2K_0402_5%
38 VDDSB_SRC
44 VDDSATA
2
54 35
L45 VDDCPU SB_SRC1T_LPRS
61 VDDHTT SB_SRC1C_LPRS 34
1 2 69
VDD48
FBMA-L11-160808-601LMT 0603 33 CLK_NBGFX 11
1
ATIG0T_LPRS
ATIG0C_LPRS 32 CLK_NBGFX# 11 NB GFX
24 CLKREQ0 #
PVT ATIG1T_LPRS
31 CLK_PCIE_VGA 14
LAN 34 LAN_CLKREQ# 51
CLKREQ1# ATIG1C_LPRS
30 CLK_PCIE_VGA# 14 VGA
Mini Card1 36 MINI1_CLKREQ# 50
CLKREQ2#
26
ATIG2T_LPRS
43 25
CLKREQ3# ATIG2C_LPRS
42
CLKREQ4#
23 CLK_PCIE_LAN 34
SRC0T_LPRS
SRC0C_LPRS
22 CLK_PCIE_LAN# 34 GLAN
CLK_NB_14.318M For Tigris 27M_SEL 63 21
TIGRIS@ REF2/SEL_27 SRC1T_LPRS
RS780 1.1V 158R/90.0R SRC1C_LPRS 20 New Card
2 1 SEL_SATA 64
27 SB710_CLK_14M R185 33_0402_5% REF1/SEL_SATA
1 2 CLK_14.318M 65 16
11 CLK_NB_14.318M REF0/SEL_HTT66 SRC2T_LPRS CLK_PCIE_MINI1 36
R201 158_0402_1% 15 MiniCard_1
SRC2C_LPRS CLK_PCIE_MINI1# 36
B
1 2 NB CLOCK INPUT TABLE B
R187 90.9_0402_1% RTS5159@
DVT2 33 CLK_48M_SD 2 1 CLK_48MHZ 71 48MHz_0 SRC3T_LPRS 14 NB CLOCKS RS740 RX780 RS780
R676 22_0402_5% 13
SRC3C_LPRS
2 1 CLK_48M 70 48MHz_1
HT_REFCLKP
28 CLK_48M_USB R209 33_0402_5% 66M SE(SINGLE END) 100M DIFF 100M DIFF
DVT2 2 1 10 HT_REFCLKN NC 100M DIFF 100M DIFF
34 CLK_48M_LAN SRC4T_LPRS CLK_SBLINK_BCLK 11
R715 33_0402_5% 9 NB A LINK
SRC4C_LPRS CLK_SBLINK_BCLK# 11
@ CLK_XTAL_IN 67 REFCLK_P
X1 14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
CLK_XTAL_OUT 68 8 CLK_PCIE_READER 33 REFCLK_N NC NC vref
X2 SRC5T_LPRS
+3VS_CLK SRC5C_LPRS 7 CLK_PCIE_READER# 33 Card Reader
GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)*
GND48
73 57 2 1 +3VS_CLK
SEL_SATA GNDPAD PD# R184 8.2K_0402_5%
27M_SEL
2
SLG8SP626VTR_QFN72_10x10
R186
8.2K_0402_5%
1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN
1
A
2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN A
http://rusefix.com
1* NON SPREAD 100M SATA SRC6 output 1 * NON SPREAD 27M and SPREAD 27M output
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
SEL_SATA 27M_SEL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0 SPREAD 100M SATA SRC6 output 0 differential spread SRC_7 output Custom 0.1
* default
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 23 of 57
5 4 3 2 1
5 4 3 2 1
DVT U35
10 LVDS_SEL
LCD POWER CIRCUIT SLE0
1
W=60mils VGA_TXCLK+ 59
R254 VGA_TXCLK- 0B2
58 1B2
300_0603_5% L : A-->B1 (INTERNAL GRAPHIC)
1
1 55 2B1 A2 12
R252 C579 54 13 H: A-->B2 (EXTERNAL GRAPHIC)
2
3B1 A3
100K_0402_5%
D 4.7U_0805_10V4Z D
53 2B2 1.8v level
6
2 52
2
3B2 R464 6.8K_0402_5%
3
S
25 LVDS_SEL 1 2
2N7002DW-T/R7_SOT363-6 G
AO3413_SOT23-3 SEL1 PX_GPIO2 11,26,38
2 2 1 2
1
Q32A R253 1K_0402_5% Q33 GMCH_TXOUT2+ 49 18 TXOUT2+ @
GMCH_TXOUT2- 4B1 A4 TXOUT2- R465
1
D 48 19
1
5B1 A5
3
C578 +LCDVDD 10K_0402_5%
W=60mils VGA_TXOUT2+ 47 @
0.047U_0402_16V7K VGA_TXOUT2- 4B2
46
2
2N7002DW-T/R7_SOT363-6 2 5B2
11 UMA_ENVDD_R 5
Q32B GMCH_TXOUT1+ 45 21 TXOUT1+
1 1 6B1 A6
1
C582 C583 GMCH_TXOUT1- 44 22 TXOUT1-
4
R508 7B1 A7
2.7K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z VGA_TXOUT1+ 43
UMA@ 2 2 VGA_TXOUT1- 6B2
42
7B2
DVT2 2 GMCH_TXOUT0+ 39
8B1 A8
27 TXOUT0+
1
D GMCH_TXOUT0- TXOUT0-
38 9B1 A9 28
2 Q49 +1.8VS
15 VGA_ENVDD
G 2N7002_SOT23 VGA_TXOUT0+ 37
1
VGA@ VGA_TXOUT0- 8B2
S 36 2
3
R251 9B2 VDD1
VDD2 8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10K_0402_5% 1 11
VGA@ GND1 VDD3
3 15 1 1 1 1 1
GND2 VDD4
4 16
2
GND3 VDD5
5 20
GND4 VDD6
9 24
GND5 VDD7 2 2 2 2 2
14 GND6 VDD8 26
17 GND7 VDD9 31
+3VS
DVT 23
GND8 VDD10
33
29 40
C GND9 VDD11
C845
C846
C847
C848
C849
C
30 GND10 VDD12 56
32 64
GND11 VDD13
1
@ 34 @ @ @ @ @
R503 0_0402_5% R501 R255 GND12
35 GND13
1 2 @ 4.7K_0402_5% 4.7K_0402_5% 41 51
13,14,27,33,34,36,38 PLT_RST# GND14 GND16
D24 50 57
RB751V_SOD323 GND15 GND17
62
2
PI2LVD512AEX_TSSOP64
1
@ MP(mask)
R256
4.7K_0402_5% @ @
@ 2 5
2N7002DW-T/R7_SOT363-6
2
Q52B
1
2N7002DW-T/R7_SOT363-6 DVT
Q52A
1 2 TXOUT0+ 2 3 VGA_TXOUT0+
11 UMA_DPST VGA_TXOUT0+ 15
TXOUT0- 1 4 VGA_TXOUT0-
VGA_TXOUT0- 15
Not for VaryBright R502 0_0402_5% RP21 VGA@ 0_0404_4P2R_5%
@ DAC_BRIG 1 2 TXOUT1+ 2 3 VGA_TXOUT1+
TXOUT1- VGA_TXOUT1- VGA_TXOUT1+ 15
C587 220P_0402_50V7K 1 4
INVT_PWM VGA_TXOUT1- 15
1 2 RP22 VGA@ 0_0404_4P2R_5%
C586 220P_0402_50V7K TXOUT2- 1 4 VGA_TXOUT2-
VGA_TXOUT2- 15
DISPOFF# 1 2 TXOUT2+ 2 3 VGA_TXOUT2+
VGA_TXOUT2+ 15
C588 220P_0402_50V7K RP23 VGA@ 0_0404_4P2R_5%
LCD/PANEL BD. Conn. TXCLK+
TXCLK-
2
1
3
4
VGA_TXCLK+
VGA_TXCLK- VGA_TXCLK+ 15
VGA_TXCLK- 15
RP20 VGA@ 0_0404_4P2R_5%
B JLVDS1 B
42 GND GND 41
40 39 DAC_BRIG
+INVPWR_B+ 40 39 DAC_BRIG 38
38 37 INVT_PWM
38 37 INVT_PWM 38 +3VS VGA_LCD_CLK 15
+3VS 36 35 DISPOFF# VGA_LCD_DATA 15
I2CC_SCL 36 35
34 33 +LCDVDD
34 33
1
I2CC_SDA 32 31
32 31 Q50A
30
30 29
29 W=60mils 2
2N7002DW-T/R7_SOT363-6
28 27
28 27 TXOUT0- VGA@
26 26 25 25
24 23 TXOUT0+
24 23
4
22 21
6
22 21 TXOUT1- Q50B
20 20 19 19 5
18 17 TXOUT1+ 2N7002DW-T/R7_SOT363-6
18 17 VGA@
16 16 15 15
14 13 TXOUT2+
14 13 TXOUT2-
12 11 DVT
3
12 11 I2CC_SCL GMCH_LCD_CLK
10 9 1 4 GMCH_LCD_CLK 11
10 9 TXCLK- I2CC_SDA GMCH_LCD_DATA
8 7 2 3 GMCH_LCD_DATA 11
8 7 TXCLK+ RP15 UMA@ 0_0404_4P2R_5%
6 5
6 5 TXOUT0- GMCH_TXOUT0-
28 USB20_N3 4 3 2 3 GMCH_TXOUT0- 11
4 3 TXOUT0+ GMCH_TXOUT0+
Camera 28 USB20_P3 2 2 1 1 +3VS 1 4 GMCH_TXOUT0+ 11
RP19 UMA@ 0_0404_4P2R_5%
ACES_88242-4001 TXOUT1- 2 3 GMCH_TXOUT1-
TXOUT1+ GMCH_TXOUT1+ GMCH_TXOUT1- 11
CONN@ 1 4 GMCH_TXOUT1+ 11
RP18 UMA@ 0_0404_4P2R_5%
TXOUT2+ 1 4 GMCH_TXOUT2+
TXOUT2- GMCH_TXOUT2- GMCH_TXOUT2+ 11
2 3 GMCH_TXOUT2- 11
RP17 UMA@ 0_0404_4P2R_5%
TXCLK- 2 3 GMCH_TXCLK-
GMCH_TXCLK- 11
TXCLK+ 1 4 GMCH_TXCLK+
+INVPWR_B+ +LCDVDD GMCH_TXCLK+ 11
RP16 UMA@ 0_0404_4P2R_5%
A A
L47 2 1 B+
W=40mils KC FBM-L11-201209-221LMAT_0805
1 1
L46 2 1 C585 C584
KC FBM-L11-201209-221LMAT_0805
1 1 10U_0805_10V4Z 0.1U_0402_16V4Z
C581 C580 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
680P_0402_50V7K 68P_0402_50V8J Issued Date 2008/10/06 2009/10/06 Title
2 2 Deciphered Date
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 24 of 57
5 4 3 2 1
5 4 3 2 1
10K_0402_5%
10K_0402_5%
2K_0402_5%
2K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
17
DDC/CEC_GND
1
HDMI_SDATA 16
D UMA@ HDMI_SCLK SDA D
15 SCL
11 GMCH_HDMI_CLK 1 2 14 Reserved
2
G
R124 0_0402_5% 13
HDMI_R_CK- CEC
12 20
2
VGA_HDMI_SCLK HDMI_SCLK CK- GND
15 VGA_HDMI_SCLK 3 1 11 21
UMA@ VGA@ VGA@ UMA@ UMA@ HDMI_R_CK+ CK_shield GND
D
10 CK+ GND 22
1 2 HDMI_R_D0- 9 23
D0- GND
2
11 GMCH_HDMI_DATA
G
R121 0_0402_5% BSH111 1N_SOT23-3 8
HDMI_R_D0+ D0_shield
Q13 7 D0+
VGA_HDMI_SDATA 3 1 HDMI_SDATA HDMI_R_D1- 6
15 VGA_HDMI_SDATA D1-
D
5 D1_shield
HDMI_R_D1+ 4
BSH111 1N_SOT23-3 HDMI_R_D2- D1+
Place closed to JHDMI1 3 D2-
Q10 2
HDMI_R_D2+ D2_shield
1
D2+
TAITW_PDVBR5-19FLBS4NN4N_19P-T
CONN@
+HDMI_5V_OUT +HDMI_5V_OUT
HDMI_HPD
W=40mils
D17 F2
1 +5VS 2 1 +HDMI_5V_OUT_1 1 2
C751 2 1 +3VS 1
2
0.1U_0402_16V4Z R352 R354 1 RB491D_SC59-3 1.1A_6VDC_FUSE
5
1
2 4 HDMI_DET 2
A Y HDMI_DET 11,15 2
1
G
U28
SN74AHCT1G125GW_SOT353-5
3
C C
HDMI_CLK+ 1 2 HDMI_R_CK+
R340 0_0402_5%
Close to NB Close to GPU
L72
VGA@ 4 3
C708 1 HDMI_CLK- 4 3
15 HDMI_CLK-_VGA 2 0.1U_0402_16V7K
C707 1 2 0.1U_0402_16V7K HDMI_CLK+
15 HDMI_CLK+_VGA
1 2
UMA@ UMA@ VGA@ 1 2
C98 1 2 0.1U_0402_16V7K HDMICLK- 1 2 @ WCM-2012-900T_0805
10 PCIE_MTX_GRX_N3
R315 0_0402_5%
C97 1 2 0.1U_0402_16V7K HDMICLK+ 1 2 HDMI_CLK- 1 2 HDMI_R_CK-
10 PCIE_MTX_GRX_P3
UMA@ R314 0_0402_5% VGA@ R333 0_0402_5%
UMA@ C705 1 2 0.1U_0402_16V7K HDMI_TX0-
15 HDMI_TX0-_VGA
C704 1 2 0.1U_0402_16V7K HDMI_TX0+ HDMI_TX0+ 1 2 HDMI_R_D0+
15 HDMI_TX0+_VGA
R342 0_0402_5%
UMA@ UMA@ VGA@
C100 1 2 0.1U_0402_16V7K HDMITX0- 1 2 L73
10 PCIE_MTX_GRX_N2
R313 0_0402_5% 4 3
C99 HDMITX0+ 4 3
10 PCIE_MTX_GRX_P2 1 2 0.1U_0402_16V7K 1 2
UMA@ R312 0_0402_5% VGA@
UMA@ C701 1 2 0.1U_0402_16V7K HDMI_TX1- 1 2
15 HDMI_TX1-_VGA HDMI_TX1+ 1 2
C700 1 2 0.1U_0402_16V7K
15 HDMI_TX1+_VGA
@ WCM-2012-900T_0805
UMA@ UMA@ VGA@
C102 1 2 0.1U_0402_16V7K HDMITX1- 1 2 HDMI_TX0- 1 2 HDMI_R_D0-
10 PCIE_MTX_GRX_N1
R311 0_0402_5% R341 0_0402_5%
C101 1 2 0.1U_0402_16V7K HDMITX1+ 1 2
10 PCIE_MTX_GRX_P1 HDMI_TX1+ HDMI_R_D1+
UMA@ R310 0_0402_5% VGA@ 1 2
UMA@ C699 1 2 0.1U_0402_16V7K HDMI_TX2- R344 0_0402_5%
B 15 HDMI_TX2-_VGA B
C698 1 2 0.1U_0402_16V7K HDMI_TX2+
15 HDMI_TX2+_VGA
L74
UMA@ UMA@ VGA@ 4 3
C104 1 HDMITX2- 4 3
10 PCIE_MTX_GRX_N0 2 0.1U_0402_16V7K 1 2
R309 0_0402_5%
C103 1 2 0.1U_0402_16V7K HDMITX2+ 1 2 1 2
10 PCIE_MTX_GRX_P0 1 2
UMA@ R307 0_0402_5%
UMA@ @ WCM-2012-900T_0805
HDMI_TX1- 1 2 HDMI_R_D1-
R343 0_0402_5%
HDMI_TX2+ 1 2 HDMI_R_D2+
R346 0_0402_5%
1
1
1 2
R141 R137 R155 R152 1 2
1
1
1
1
2
2
2
2
6
+3VS
R505 0_0402_5%
A A
1 2 2 5 2 5
1 2
1
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 25 of 57
5 4 3 2 1
A B C D E
CRT CONNECTOR
+5VS +R_CRT_VCC +CRT_VCC
W=40mils
D28 D27 D26
DAN217_SC59 DAN217_SC59 DAN217_SC59 D25 F1
2 1 1 2
1
1
RB491D_SC59-31.1A_6VDC_FUSE
C622
1 +5VS 0.1U_0402_16V4Z 1
2
3
JCRT1
6
L57 FCM2012C-800_0805 L58 FCM2012C-800_0805 RGND
11 ID0
2 UMA@ 1 CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 1
11 GMCH_CRT_R Red
R291 0_0402_5% 7
L54 FCM2012C-800_0805 L55 FCM2012C-800_0805 DDCDATA GGND
12 SDA
2 UMA@ 1 CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 2
11 GMCH_CRT_G Green
R277 0_0402_5% 8
L52 FCM2012C-800_0805 L53 FCM2012C-800_0805 HSYNC BGND
13
CRT_B CRT_B_1 CRT_B_2 Hsync
11 GMCH_CRT_B 2 UMA@ 1 1 2 1 2 3
R274 0_0402_5% Blue
+CRT_VCC 9
+5V
6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K
5P_0402_50V8C
5P_0402_50V8C
5P_0402_50V8C
VSYNC 14 Vsync
140_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 4
res
1
R285 R276 R273 C633 C640 C662 10
C667 C660 C639 DDCCLK SGND
DVT 15
SCL
15 VGA_CRT_R 2 VGA@ 1 5
R493 0_0402_5% 2 2 2 2 2 2 GND
UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ 16
2
GND
15 VGA_CRT_G 2 VGA@ 1 17 GND
R495 0_0402_5%
15 VGA_CRT_B 2 VGA@ 1
R494 0_0402_5% SUYIN_070546FR015S263ZR
CONN@
CRT_DET# 28
2 2
2
R269
+CRT_VCC 100K_0402_5%
1 2 PX_GPIO2#
1
C674
5
1
0.1U_0402_16V4Z +3VS
VGA@
OE#
P
2 4 HSYNC_L +CRT_VCC
15,22 VGA_CRT_HSYNC A Y
1
+3VS
G
U33 R268
SN74AHCT1G125GW_SOT353-5 10K_0402_5%
3
1
VGA@ @
R471
2
1 2 10K_0402_5% PX_GPIO2#
C678 @
5
1
0.1U_0402_16V4Z
1
VGA@ @ D
OE#
P
3
1
SN74AHCT1G125GW_SOT353-5 +CRT_VCC +3VS_DELAY
3
2
VGA@ R475
10K_0402_5% DVT
UMA@
2 +3VS
DVT
1
+CRT_VCC
DVT
R54 R46 R55 R48
1 2 PX_GPIO2_R 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 10K_0402_5%
C626 UMA@ UMA@ VGA@ VGA@
5
1
3 0.1U_0402_16V4Z 3
2
2
UMA@ L50 FCM1608C-121T_0603
OE#
P
2 4 HSYNC_L 1 2 HSYNC
11,13 GMCH_CRT_HSYNC A Y DDCDATA DDCDATA_R
2 R57 1 6 1
G
U25 VGA_CRT_DATA 15
SN74AHCT1G125GW_SOT353-5 33_0402_5% Q6A
3
5
UMA@ 2N7002DW-T/R7_SOT363-6
VGA@
1 2 DDCCLK 2 R44 1 DDCCLK_R 3 4
C628 VGA_CRT_CLK 15
5
1
U26
SN74AHCT1G125GW_SOT353-5
3
UMA@ 1 2
R58 0_0402_5% GMCH_CRT_DATA 11
UMA@
1 2
R47 0_0402_5% GMCH_CRT_CLK 11
UMA@ DVT
DVT
U36 +5VS
15
PX_GPIO2_R EN
1 16
IN VCC
4
1 4
GMCH_CRT_R 2 C850
VGA_CRT_R S1A CRT_R 0.1U_0402_16V4Z
3 S2A DA 4
GMCH_CRT_G 5 7 CRT_G @
VGA_CRT_G S1B DB CRT_B 2
6 9
GMCH_CRT_B S2B DC
11 S1C DD 12
VGA_CRT_B 10
S2C
14 S1D
L : D-->S1 (INTERNAL GRAPHIC)
13 S2D GND 8 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
H: D-->S2 (EXTERNAL GRAPHIC) IDTQS3257QG_QSOP16
http://rusefix.com
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
MP(mask) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Friday, February 20, 2009 Sheet 26 of 57
A B C D E
A B C D E
U14A
A_RST# N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1
P3
C468 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
PCI CLKS
1 10 SB_RX0P SB_RX0N_C PCIE_TX0P PCICLK2 PCI_CLK2 31 1
C465 1 2 0.1U_0402_16V7K V22 P2
10 SB_RX0N SB_RX1P_C PCIE_TX0N PCICLK3 PCI_CLK3 31
C459 1 2 0.1U_0402_16V7K V24 T4
10 SB_RX1P SB_RX1N_C PCIE_TX1P PCICLK4 PCI_CLK4 31
C431 1 2 0.1U_0402_16V7K V25 T3
10 SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 31
C429 1 2 0.1U_0402_16V7K SB_RX2P_C U25
10 SB_RX2P SB_RX2N_C PCIE_TX2P
C430 1 2 0.1U_0402_16V7K U24
10 SB_RX2N PCIE_TX2N
C460 1 2 0.1U_0402_16V7K SB_RX3P_C T23
10 SB_RX3P SB_RX3N_C PCIE_TX3P
C464 1 2 0.1U_0402_16V7K T22 N1
10 SB_RX3N PCIE_TX3N PCIRST#
10 SB_TX0P U22
0.1U_0402_16V4Z U30 Y4
AD21
2 Y3
P
NB_DISP_CLKN AD30
AD31 AD1
M24 W2
NB_HT_CLKP CBE0#
PCI INTERFACE
M25 NB_HT_CLKN CBE1# U7
AA7
CBE2#
P17 CPU_HT_CLKP CBE3# Y1
M18 AA6
CPU_HT_CLKN FRAME#
W5
DEVSEL#
M23 AA5
SLT_GFX_CLKP IRDY#
M22 Y5
SLT_GFX_CLKN TRDY#
U6
PAR
J19 W6
GPP_CLK0P STOP#
J18 GPP_CLK0N PERR# W4
V7
SERR#
L20 AC3
GPP_CLK1P REQ0#
L19 AD4
GPP_CLK1N REQ1#
AB7
REQ2#
M19 AE6
GPP_CLK2P REQ3#/GPIO70
M20
GPP_CLK2N REQ4#/GPIO71
AB6 DVT R496 1 @ 2 0_0402_5% PX_GPIO1_SB 38 GPU_POWER ENABLE (SB->EC)
C853 @ 100P_0402_25V8K @ AD2
GNT0#
CLOCK GENERATOR
2 1 2 1 N22 AE4
R470 100_0402_5% GPP_CLK3P GNT1#
P22 AD5
GPP_CLK3N GNT2# PX_GPIO1_SB_R
GNT3#/GPIO72
AC6 R476 1 @ 2 0_0402_5% PX_GPIO1 38,45 GPU_1.1VS (SB->MOS)
23 SB710_CLK_14M L18 AE5
25M_48M_66M_OSC GNT4#/GPIO73
AD6
3 CLKRUN# 3
For Tigris LOCK# V5
J21 25M_X1
Close to SB INTE#/GPIO33
AD3
INTF#/GPIO34 AC4 DVT
AE2
INTG#/GPIO35 PX_GPIO0_SB
@ R380 20M_0402_5% J20
25M_X2 INTH#/GPIO36
AE3 1 @ 2 PX_GPIO0 14 GPU_RST#
1 2 R482 0_0402_5%
4 3 J24 LPC_AD3 38
RTC XTAL
OUT NC LAD3
LPC
BMREQ#/REQ5#/GPIO65
V15 SERIRQ 38
SERIRQ
1
1 2 SB_32KHO
F23 R237
11 ALLOW_LDTSTOP ALLOW_LDTSTP
18P_0402_50V8J H_PROCHOT_R# F24 C3 STRAP PIN 1K_0402_5%
6 H_PROCHOT_R# PROCHOT# RTCCLK RTC_CLK 31
F22 C2 1 @ 2 +RTCVCC
6 H_PWRGD LDT_PG INTRUDER_ALERT#
G25 B2 R403 1M_0402_5%
CPU
6,11 LDT_STOP#
2
LDT_STP# VBAT +RTCVCC
6 LDT_RST# G24
LDT_RST#
RTC
D22
1 2 3
218S7EALA11FG_BGA528_SB700 R400 510_0402_5%
+3VS
0.1U_0402_16V4Z
C795 1 1 C794 W=20mils 1
2
+1.8VS
0.1U_0402_16V4Z
1U_0402_6.3V4Z 1
2
4 R397 C566 4
R355
SA00001S570 S IC 218S7EBLA12FG SB700 BGA 528P SB 0FA @
2
2 2
4.7K_0402_5% for Clear CMOS 0_0603_5%
2 BAS40-04_SOT23-3
1
2
G
+CHGRTC
1
H_PWRGD 3 1
H_PWRGD_L 53
S
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700-PCIE/PCI/ACPI/LPC/RTC
level shift to ISL6265 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 27 of 57
A B C D E
A B C D E
+3VALW
2
R368
100K_0402_5%
1
CRT_DET
1
D
2 U14D @ @
26 CRT_DET#
Q37G demo circuit LID use RI# 1 2 C775 1 2 100P_0402_25V8K
2N7002_SOT23 Part 4 of 5 R376 100_0402_5%
S SB700
3
1 1
38 EC_SWI# E1 PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 23
CRT_DET H7 SLP_S2/GPM9# USB_RCOMP 1
38 PM_SLP_S3# F5 G8 2
SLP_S3# USB_RCOMP 11.8K_0402_1% R370
38 PM_SLP_S5# G1
SLP_S5#
USB MISC
H2
USB 1.1
38 EC_GA20 Y15 F7 USB20_P12 37
GA20IN/GEVENT0# USB_FSD12P USB20_N12
38 EC_KBRST# W15 KBRST#/GEVENT1# USB_FSD12N E8 USB20_N12 37 USB-12 Bluetooth
38 EC_SCI# K4
LPC_PME#/GEVENT3#
38 EC_SMI# K24 H11
LPC_SMI#/EXTEVNT1# USB_HSD11P
F1 J10
S3_STATE/GEVENT5# USB_HSD11N
J2 SYS_RESET#/GPM7#
36 SB_PCIE_WAKE# H6 E11
CR_PE# WAKE#/GEVENT8# USB_HSD10P
33 CR_PE# F2 BLINK/GPM6# USB_HSD10N F11
1 2 EC_RSMRST# H_THERMTRIP# J6
6 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
R404 2.2K_0402_5% NB_PWRGD W14 A11
11 NB_PWRGD NB_PWRGD USB_HSD9P
B11
EC_RSMRST# USB_HSD9N
38 EC_RSMRST# D3 RSMRST#
C10 USB20_P8
USB_HSD8P USB20_N8 USB20_P8 36
SB700 has internal PD USB_HSD8N
D10 USB20_N8 36 USB-8 MiniCard(WLAN)
+3VS AE18 G11
CR_WAKE# SATA_IS0#/GPIO10 USB_HSD7P
DVT 33 CR_WAKE# AD18
CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N
H12
AA19 SMARTVOLT1/SATA_IS2#/GPIO4
R182 1 2 10K_0402_5% CR_WAKE# R509 1 VGA@ 2 2.2K_0402_5% SKU_ID W17 E12 USB20_P6 USB-6 Int USB 1st
+3VS CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_P6 37
V17 E14 USB20_N6
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USB20_N6 37 (Dedicated HS USB port / lower-left)
R183 1 2 2.2K_0402_5% ICH_SMBCLK0 R510 1 UMA@ 2 2.2K_0402_5% W20
2 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 2
42 SB_SPKR W21 C12
USB 2.0
SPKR/GPIO2 USB_HSD5P
R179 1 2 2.2K_0402_5% ICH_SMBDATA0 8,9,23,36 ICH_SMBCLK0 ICH_SMBCLK0 AA18 D12
ICH_SMBDATA0 W18 SCL0/GPOC0# USB_HSD5N
8,9,23,36 ICH_SMBDATA0 SDA0/GPOC1# USB20_P4
DVT2
K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 33
SB_SPKR=W/S=4/4(55ohm impedance) K2 A12 USB20_N4 USB-4 USB Card reader
SDA1/GPOC3# USB_HSD4N USB20_N4 33
AA20
DDC1_SCL/GPIO9
GPIO
Y18 G12 USB20_P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 24
C1 G14 USB20_N3 USB-3 USB Camera
LLB#/GPIO66 USB_HSD3N USB20_N3 24
Y19 SMARTVOLT2/SHUTDOWN#/GPIO5
G5 H14
DDR3_RST#/GEVENT7# USB_HSD2P
USB_HSD2N H15
+3VALW
USB20_P1
DVT
USB_HSD1P A13 USB20_P1 37
B13 USB20_N1 USB-1 Int USB 2nd (W/eSATA) --> Reserved
USB_HSD1N USB20_N1 37
1 2 SB_PCIE_WAKE# B14 USB20_P0
USB_HSD0P USB20_P0 36
R388 10K_0402_5% B9 A14 USB20_N0 USB-0 Ext USB 3rd
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 36
1 @ 2 EC_LID_OUT# B8
R379 100K_0402_5% EC_LID_OUT# USB_OC5#/IR_TX0/GPM5#
A8 A18
USB OC
38 EC_LID_OUT# USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
R414 33_0402_5% 1 2 USB_OC#2 E5 F21
42 HDA_BITCLK_AUDIO 36 USB_OC#2 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10
R413 33_0402_5% 1 2 HDA_BITCLK USB_OC#1 F8 D21
41 HDA_BITCLK_MDC 37 USB_OC#1 USB_OC#0 USB_OC1#/GPM1# SCL2/IMC_GPIO11
37 USB_OC#0 E4 F19
USB_OC0#/GPM0# SDA2/IMC_GPIO12
AMD (un-used) SCL3_LV/IMC_GPIO13
E20
R415 33_0402_5% 1 2 M1 E21
41 HDA_SDOUT_MDC HDA_SDOUT AZ_BITCLK SDA3_LV/IMC_GPIO14
R416 33_0402_5% 1 2 M2 E19
42 HDA_SDOUT_AUDIO AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
42 HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 31
HDA_SDIN1 J8 E18 STRAP PIN
41 HDA_SDIN1 AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 GPIO17 31
L8
AZ_SDIN2/GPIO44
HD AUDIO
M3 G20
R391 33_0402_5% HDA_SYNC AZ_SDIN3/GPIO46 IMC_GPIO18
41 HDA_SYNC_MDC 1 2 L6 G21
R412 33_0402_5% AZ_SYNC IMC_GPIO19
42 HDA_SYNC_AUDIO 1 2 M4 D25
3 AZ_RST# IMC_GPIO20 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
C25
INTEGRATED uC
R408 33_0402_5% HDA_RST# IMC_GPIO22
42 HDA_RST_AUDIO# 1 2 C24
R409 33_0402_5% IMC_GPIO23
41 HDA_RST_MDC# 1 2 IMC_GPIO24 B25
C23
IMC_GPIO25
31 HDA_RST# B24
IMC_GPIO26
B23
IMC_GPIO27
A23
IMC_GPIO28
STRAP PIN IMC_GPIO29 C22
IMC_GPIO30 A22
B22
IMC_GPIO31
IMC_GPIO32 B21
A21
IMC_GPIO33
H19 IMC_GPIO0 IMC_GPIO34 D20
H20 C20
IMC_GPIO1 IMC_GPIO35
H21 A20
INTEGRATED uC
SPI_CS2#/IMC_GPIO2 IMC_GPIO36
F25 B20
IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37
B19
IMC_GPIO38
D22 A19
IMC_GPIO4 IMC_GPIO39
E24 D18
IMC_GPIO5 IMC_GPIO40
E25 IMC_GPIO6 IMC_GPIO41 C18
D23
IMC_GPIO7
218S7EALA11FG_BGA528_SB700
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 USB/HD audio
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 28 of 57
A B C D E
A B C D E
U14B
1 1
Close chip
C504 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9
SB700 AA24
32 SATA_STX_C_DRX_P0 C507 1 SATA_STX_DRX_N0 SATA_TX0P IDE_IORDY
2 0.01U_0402_25V7K AE9 Part 2 of 5 AA25
32 SATA_STX_C_DRX_N0 SATA_TX0N IDE_IRQ
HDD IDE_A0
Y22
32 SATA_DTX_C_SRX_N0 AB10 SATA_RX0N IDE_A1 AB23
32 SATA_DTX_C_SRX_P0 AC10 Y23
SATA_RX0P IDE_A2
IDE_DACK# AB24
C522 1 2 0.01U_0402_25V7K SATA_STX_DRX_P1 AE10 AD25
32 SATA_STX_C_DRX_P1 SATA_TX1P IDE_DRQ
C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25
32 SATA_STX_C_DRX_N1 SATA_TX1N IDE_IOR#
ODD IDE_IOW# AC24
32 SATA_DTX_C_SRX_N1 AD11 Y25
SATA_RX1N IDE_CS1#
32 SATA_DTX_C_SRX_P1 AE11 SATA_RX1P IDE_CS3# Y24
@
eSATA C862 1 2 0.01U_0402_25V7K SATA_STX_DRX_P2 AB12 AD24
37 SATA_STX_C_DRX_P2 SATA_TX2P IDE_D0/GPIO15
C863 1 2 0.01U_0402_25V7K SATA_STX_DRX_N2 AC12 AD23
(Reserved) 37 SATA_STX_C_DRX_N2 SATA_TX2N IDE_D1/GPIO16
ATA 66/100/133
@ AE22
IDE_D2/GPIO17
37 SATA_DTX_C_SRX_N2 AE12 AC22
SATA_RX2N IDE_D3/GPIO18
DVT 37 SATA_DTX_C_SRX_P2 AD12 SATA_RX2P IDE_D4/GPIO19 AD21
AE20
IDE_D5/GPIO20
AD13 AB20
SATA_TX3P IDE_D6/GPIO21
AE13 AD19
SATA_TX3N IDE_D7/GPIO22
AE19
SERIAL ATA
IDE_D8/GPIO23
AB14 SATA_RX3N IDE_D9/GPIO24 AC20
AC14 AD20
SATA_RX3P IDE_D10/GPIO25
IDE_D11/GPIO26 AE21
AE14 AB22
SATA_TX4P IDE_D12/GPIO27
AD14 AD22
SATA_TX4N IDE_D13/GPIO28
IDE_D14/GPIO29 AE23
AD15 SATA_RX4N IDE_D15/GPIO30 AC23
AE15
SATA_RX4P
2 SATA_X1 2
2 1 C770 AB16 SATA_TX5P
AC16
SATA_TX5N
1
10P_0402_50V8J DVT G6
SPI_DI/GPIO12
AE16 SATA_RX5N SPI_DO/GPIO11 D2
R371 SATA_CAL=W/S=9/20(35ohm impedance), <1" AD16 SATA_RX5P SPI_CLK/GPIO47 D1
25MHZ_20P Y3 10M_0402_5% F4
2
SPI_HOLD#/GPIO31
SPI ROM
2 1 SATA_CAL V12 F3
2
SATA PWR
1 1 W12 R8
XTLVDD_SATA FANIN2/GPIO52
C784 C783 C6
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z TEMP_COMM
B6
2 2 TEMPIN0/GPIO61
A6
TEMPIN1/GPIO62
A5
TEMPIN2/GPIO63
B5 EC_THERM# 38
TEMPIN3/TALERT#/GPIO64
HW MONITOR
+3VS A4 2 1
VIN0/GPIO53 ACIN 15,38,40,46,49
L81 XTLVDD_SATA=6mA B4 D30 RB751V_SOD323
+XTLVDD_SATA VIN1/GPIO54
2 1 C4
BLM18PG121SN1D_0603 VIN2/GPIO55
2 1 D4
VIN3/GPIO56
D5
C777 C776 VIN4/GPIO57 R369 2
D6 1 100K_0402_5% +3VALW
1U_0402_6.3V4Z 0.1U_0402_16V4Z VIN5/GPIO58
A7
3 1 2 VIN6/GPIO59 R374 2 3
VIN7/GPIO60 B7 1 100K_0402_5% +3VS
+3VALW @
AVDD
F6 AVDD=5mA
G7
AVSS
218S7EALA11FG_BGA528_SB700
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 SATA/IDE/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 29 of 57
A B C D E
A B C D E
U14C U14E
VDD=0.51A
VDDQ=131mA SB700 +1.2V_SB_CORE
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1
L15
M12
1
R171
2
0_0805_5%
+1.2V_HT SB700 A2
VDDQ_2 VDD_2 10U_0805_10V4Z C467 VSS_1
1 2 T15 M14 1 2 A25
C472 22U_0805_6.3V6M VDDQ_3 VDD_3 VSS_2
U9 VDDQ_4 VDD_4 N13 VSS_3 B1
CORE S0
1 1
U16 VDDQ_5 VDD_5 P12 VSS_4 D7
U17 VDDQ_6 VDD_6 P14 T10 AVSS_SATA_1 VSS_5 F20
PCI/GPIO I/O
V8 R11 1U_0402_6.3V4Z 2 1 C478 U10 G19
VDDQ_7 VDD_7 1U_0402_6.3V4Z C487 AVSS_SATA_2 VSS_6
W7 R15 2 1 U11 H8
VDDQ_8 VDD_8 0.1U_0402_16V4Z C494 AVSS_SATA_3 VSS_7
Y6 T16 2 1 U12 K9
C489 0.1U_0402_16V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C482 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C499 1 2 0.1U_0402_16V4Z AB5 V14 K16
C493 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 L10
AVSS_SATA_9 VSS_13
VDD=138mA Y14 AVSS_SATA_10 VSS_14 L11
VDD33=71mA +1.2V_CKVDD
Y17
AVSS_SATA_11 VSS_15
L12
+3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 +1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 L22 AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
AA22 L24 AB11 M6
VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18
IDE/FLSH I/O
CLKGEN I/O
AE25 L25 AB13 M10
VDD33_18_4 CKVDD_1.2V_4 AVSS_SATA_15 VSS_19
AB15 AVSS_SATA_16 VSS_20 M11
AB17 M13
AVSS_SATA_17 VSS_21
AC8 AVSS_SATA_18 VSS_22 M15
AD8 N4
AVSS_SATA_19 VSS_23
AE8 N12
AVSS_SATA_20 VSS_24
PCIE_VDDR=0.6A +PCIE_VDDR VSS_25
N14
P6
L37 POWER VSS_26
VSS_27 P9
+1.2V_HT 2 1 P10
FBMA-L11-201209-221LMA30T_0805 VSS_28
A15 AVSS_USB_1 VSS_29 P11
P18 B15 P13
C466 1 PCIE_VDDR_1 +3VALW AVSS_USB_2 VSS_30
2 4.7U_0805_10V4Z P19 C14 P15
C763 1 PCIE_VDDR_2 AVSS_USB_3 VSS_31
2 1U_0402_6.3V4Z P20 PCIE_VDDR_3 S5_3.3V=32mA D8 AVSS_USB_4 VSS_32 R1
P21 A17 +S5_3V D9 R2
A-LINK I/O
PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
R22 A24 D11 R4
PCIE_VDDR_5 S5_3.3V_2 AVSS_USB_6 VSS_34
R24 B17 D13 R9
2 PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35 2
GROUND
C759 1 2 0.1U_0402_16V4Z R25 J4 D14 R10
C497 1 PCIE_VDDR_7 S5_3.3V_4 AVSS_USB_8 VSS_36
2 0.1U_0402_16V4Z J5 D15 R12
3.3V_S5 I/O
S5_3.3V_5 2.2U_0603_6.3V4Z C769 AVSS_USB_9 VSS_37
L1 1 2 E15 R14
S5_3.3V_6 AVSS_USB_10 VSS_38
AVDD_SATA=567mA +1.2V_SATA S5_3.3V_7 L2 F12 AVSS_USB_11 VSS_39 T11
2.2U_0603_6.3V4Z 1 2 C486 F14 T12
L79 AVSS_USB_12 VSS_40
G9 T14
AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 H9 AVSS_USB_14 VSS_42 U4
FBMA-L11-201209-221LMA30T_0805 AB18 +1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 +S5_1.2V
S5_1.2V=113mA J9 AVSS_USB_16 VSS_44 V6
AA17 G2 J11 Y21
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45
CORE S5
SATA I/O
C764 1 2 22U_0805_6.3V6M AC18 G4 J12 AB1
C766 1U_0402_6.3V4Z AVDD_SATA_5 S5_1.2V_2 +1.2VALW C797 2 AVSS_USB_18 VSS_46
1 2 AD17 USB_PHY_1.2V=197mA 1 1U_0402_6.3V4Z J14 AB19
C765 1U_0402_6.3V4Z AVDD_SATA_6 C796 2 AVSS_USB_19 VSS_47
1 2 AE17 AVDD_SATA_7 1 1U_0402_6.3V4Z J15 AVSS_USB_20 VSS_48 AB25
C767 1 2 0.1U_0402_16V4Z +1.2_USB 2 1 K10 AE1
C768 0.1U_0402_16V4Z L80 FBMA-L11-160808-221LMT 0603 AVSS_USB_21 VSS_49
1 2 A10 K12 AE24
USB_PHY_1.2V_1 C771 1 AVSS_USB_22 VSS_50
B10 2 10U_0805_10V4Z K14
USB_PHY_1.2V_2 AVSS_USB_23
K15
C773 2 AVSS_USB_24
1 0.1U_0402_16V4Z P23
C774 2 PCIE_CK_VSS_9
1 0.1U_0402_16V4Z R16
PCIE_CK_VSS_10
AVDDTX/RX=658mA +AVDD_USB PCIE_CK_VSS_11 R19
T17
L38 PCIE_CK_VSS_12
+V5_VREF
V5_VREF=1mA PCIE_CK_VSS_13
U18
+3VALW 2 1 A16 AE7 1K_0402_5% 2 1 R386 +5VS H18 U20
FBMA-L11-201209-221LMA30T_0805 AVDDTX_0 V5_VREF D31 PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 2 J17 V18
AVDDTX_1 +AVDDCK_3.3V PCIE_CK_VSS_2 PCIE_CK_VSS_15
C16 J16 1 2 +3VS J22 V20
C461 10U_0805_10V4Z AVDDTX_2 AVDDCK_3.3V C786 PCIE_CK_VSS_3 PCIE_CK_VSS_16
1 2 D16 K25 V21
C469 10U_0805_10V4Z AVDDTX_3 +AVDDCK_1.2V PCIE_CK_VSS_4 PCIE_CK_VSS_17
1 2 D17 K17 1U_0402_6.3V4Z CH751H-40PT_SOD323-2 M16 W19
PLL
0.1U_0402_16V4Z 2 1 C496
218S7EALA11FG_BGA528_SB700
AVDDCK_1.2V=62mA
L77
+AVDDCK_1.2V 2 1 +1.2V_HT
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2 1 C758
0.1U_0402_16V4Z 2 1 C761
AVDDCK_3.3V=47mA
L76
+AVDDCK_3.3V 2 1 +3VS
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2 1 C756
0.1U_0402_16V4Z 2 1 C760
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, January 15, 2009 Sheet 30 of 57
A B C D E
A B C D E
REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
LPC_CLK0
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 CLK_PCI_EC LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16
PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
H,H = Reserved
ENABLED STRAPS
1 DEFAULT 1
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default L,NC)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)
+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R363
R367
R427
R425
R423
R421
R359
R361
R401
R411
2
2
@ @ @ @ @ @ @ @ @
27 PCI_CLK2
27 PCI_CLK3
27 PCI_CLK4
27 PCI_CLK5
27,38 CLK_PCI_EC
27 LPCCLK1
27 RTC_CLK
28 HDA_RST#
2 28 GPIO17 2
28 GPIO16
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R402
R362
R366
R424
R422
R420
R398
R358
R360
R410
2
2
@ @ @ @
DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3
27 PCI_AD28
27 PCI_AD27
27 PCI_AD26
27 PCI_AD25
27 PCI_AD24
27 PCI_AD23
1
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R392
R393
R395
R389
R396
R399
2
2
@ @ @ @ @ @
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 31 of 57
A B C D E
A B C D E F G H
1
SATA ODD Conn. 1
JSATA1
1 1
SATA_STX_C_DRX_P1 2
29 SATA_STX_C_DRX_P1 SATA_STX_C_DRX_N1 2
29 SATA_STX_C_DRX_N1 3 3
4 4
29 SATA_DTX_C_SRX_N1 C513 1 2 0.01U_0402_25V7K SATA_DTX_SRX_N1 5
C510 SATA_DTX_SRX_P1 5
29 SATA_DTX_C_SRX_P1 1 2 0.01U_0402_25V7K 6 6
7
7
Close conn R199 1 2 1K_0402_1% 8 8
@ 9
9
+5VS 10
10
11
11
12 12
13
13
14 14 GND 16
15 17
15 GND
OCTEK_SLS-13DB1G_NR
Placea caps. near ODD CONN. CONN@
+5VS
0.1U_0402_16V4Z 10U_0805_10V4Z
1 1 1 1
C491 C492 C505
2 C490 2
2 2 2 2
1000P_0402_50V7K 1U_0402_6.3V4Z
1
SATA_STX_C_DRX_P0 GND
2
29 SATA_STX_C_DRX_P0 SATA_STX_C_DRX_N0 HTX+
3
29 SATA_STX_C_DRX_N0 HTX-
4
C515 SATA_DTX_SRX_N0 GND
29 SATA_DTX_C_SRX_N0 1 2 0.01U_0402_25V7K 5
3 C521 SATA_DTX_SRX_P0 HRX- 3
29 SATA_DTX_C_SRX_P0 1 2 0.01U_0402_25V7K 6 HRX+
7 GND
Close conn
+3VS 8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12 GND
+5VS 13
10U_0805_10V4Z GND
+5VS 14
0.1U_0402_16V4Z VCC5
15 VCC5
+3VS 16
VCC5
1 1 1 1 1 1 17 GND
1 C556 C554 C557 C555 C552 18
C792 RESERVED
19
C551 GND
20
0.1U_0402_16V4Z 2 2 2 2 2 2 VCC12
21 24
2 VCC12 GND
22 23
1000P_0402_50V7K 1U_0402_6.3V4Z VCC12 GND
0.1U_0402_16V4Z 0.1U_0402_16V4Z
SUYIN_127043FB022GX78ZR_NR
CONN@
JALA0 (CL 9.2mm)
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 32 of 57
A B C D E F G H
A B C D E
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R218 JMB385@ 10K_0402_5%
D20 R226 XD_RB 1 2
1 1 1 1 1 1 1 1 1 XDCD0#_SDCD# 2 10K_0402_5% R214 JMB385@ 10K_0402_5% +3VS
C538 C550 C540 C531 C562 C558 C559 C536 C542 1 XD_CD# JMB385@
XDCD1#_MSCD# 3 XD_CLE 1 2
1
JMB385@ JMB385@ JMB385@ JMB385@ JMB385@ JMB385@ JMB385@ JMB385@ JMB385@ 28 CR_PE# R217 JMB385@ 10K_0402_5%
2 2 2 2 2 2 2 2 2 DAN202UT106_SC70-3 C553 XDCD0#_SDCD# 1 2
1
10U_0805_10V4Z JMB385@ 270P_0402_50V7K D R224 JMB385@ 4.7K_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K JMB385@ 2 CR_PE XDCD1#_MSCD# 1 2
G R225 JMB385@ 4.7K_0402_5%
S Q24 XD_RE 1 2
3
1 2N7002_SOT23 R212 JMB385@ 200K_0402_5% 1
23 CLK_PCIE_READER#
40mil 3 APCLKN APVDD 5 +1.8VS_APVDD
4 10 RTS5159@ JMB385@ DVT2
23 CLK_PCIE_READER APCLKP APV18 XDCE# XD_SD_MS_D0 XD_D0
30 +3VS 2 1 2 1 RTS5159@ JMB385@
PCIE_ITX_C_PRX_N4 TAV33 R672 0_0402_5% R691 0_0402_5% XD_SD_MS_D2 XD_D2
10 PCIE_ITX_C_PRX_N4 9 APRXN 2 1 2 1
PCIE_ITX_C_PRX_P4 8 19 XDCE_SDCLK_MSCLK 2 1 XDCE#_R SDDAT5_XDD0_MSD62 1 R706 0_0402_5% R704 0_0402_5%
10 PCIE_ITX_C_PRX_P4 JMB385@ APRXP DV33 R675 0_0402_5% R692 0_0402_5% SDDAT7_XDD2_MSD2
DV33 20 2 1
C560 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N4 11 44 RTS5159@ R705 0_0402_5%
10 PCIE_PTX_C_IRX_N4 APTXN DV33 JMB385@
C561 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P4 12 18 2 1 SD_D5 2 RTS5159@
1 SD_D7
10 PCIE_PTX_C_IRX_P4 APTXP DV18 +1.8VS_APVDD
JMB385@ 37 JMB385@ R693 0_0402_5% R707 0_0402_5%
DV18
R227 1 2 8.2K_0402_5% APREXT 7 XD_SD_MS_D2 2 1 SD_D2 RTS5159@ RTS5159@
APREXT XD_SD_MS_D0 XD_D5
APREXT 15 mil MDIO0
48 R678 0_0402_5% 2 1
JMB385@ 47 XD_SD_MS_D1 RTS5159@ R694 0_0402_5% RTS5159@
MDIO1 XD_SD_MS_D2 SDDAT2_XDRE# SDDAT0_XDD6_MSD0 XD_SD_MS_D0
+3VS 38 46 2 1 JMB385@ 2 1
PCIES_EN MDIO2 XD_SD_MS_D3 R679 0_0402_5% R708 0_0402_5%
39 PCIES JMB385 MDIO3
MDIO4
45
43 SDCMD_MSBS_XDWE# 2 1 XD_RE RTS5159@ 2 1 XD_D6
42 XDCE_SDCLK_MSCLK JMB385@ R681 0_0402_5% SDCLK_XDD1_MSCLK2 1 XDCE_SDCLK_MSCLK R709 0_0402_5%
MDIO5
33P_0402_50V8K 22_0402_5%
41 XDWP_SDWP RTS5159@ R695 0_0402_5% RTS5159@
MDIO6 XD_CLE JMB385@
MDIO7 40 2 1
1
29 XD_D4 XD_SD_MS_D3 2 1 R697 0_0402_5% RTS5159@
MDIO8
R223
1 28 XD_D5 R684 0_0402_5% RTS5159@ XD_D4 2 1
11,13,14,24,27,34,36,38 PLT_RST# XRSTN MDIO9 XD_D6 SDDAT3_XDWE# SD_D3 JMB385@ R732 0_0402_5%
2 XTEST MDIO10 27 2 1
26 XD_D7 R685 0_0402_5% XD_SD_MS_D1 2 1 XD_D1 RTS5159@
MDIO11 XD_RE RTS5159@ R696 0_0402_5% XDD4_SDDAT1
25 2 1
2
CR_PE MDIO12 XD_RB R714 0_0402_5%
13 SEEDAT MDIO13 23 2 1
14 22 XD_ALE R687 0_0402_5% JMB385@ JMB385@
SEECLK MDIO14
C543
RTS5159@ XD_D7 2 1 SD_D7 XD_SD_MS_D1 2 1 MS_D1
D19 34 JMB385@ SDCMD_MSBS_XDWE# 2 1 XDWE# R698 0_0402_5% R711 0_0402_5%
2 CH751H-40PT_SOD323-2 XDCD1#_MSCD# NC R686 0_0402_5% SDDAT6_XDD7_MSD3 SDDAT1_XDD3_MSD1 2
15 CR1_CD1N NC 35 2 1 2 1
1 2 XDCD0#_SDCD# 16 36 JMB385@ R699 0_0402_5% R710 0_0402_5%
28 CR_WAKE# CR1_CD0N NC RTS5159@ RTS5159@
JMB385@ +3V_MCVCC 6 JMB385@ RTS5159@ 2 1 XD_SD_MS_D3
APGND XDWP_SDWP XDWP SDDAT6_XDD7_MSD32 MS_D3 R730 0_0402_5%
17 CR1_PCTLN 2 1 1
24 R688 0_0402_5% R700 0_0402_5% RTS5159@
GND SDDAT4_XDWP#_MSD7 2 XD_SD_MS_D3 JMB385@
GND 31 1 2 1
21 32 R689 0_0402_5% R701 0_0402_5% SDCMD_MSBS_XDWE# 2 1 MSBS
40 5IN1_LED# CR1_LEDN GND RTS5159@ R712 0_0402_5%
33 JMB385@
GND SD_D4 JMB385@ XDD5_MSBS
2 1 2 1
R690 0_0402_5% XD_D6 2 1 SD_D6 R713 0_0402_5%
RTS5159@ R702 0_0402_5% RTS5159@
JMB385-LGEZ0A_LQFP48_7X7 XD_D4 2 1 SDDAT6_XDD7_MSD32 1 2 1 XD_D5
JMB385@ R729 0_0402_5% R703 0_0402_5% R731 0_0402_5%
JMB385@ RTS5159@ RTS5159@
RTS5159@ DVT2
RTS5159@
U41 4 IN 1 Socket Push Type(New)
2 1 VREG 1 JREAD1
C864 0.1U_0402_16V4Z AV_PLL
3 +3V_MCVCC 3 21 +3V_MCVCC
@ +3V_CARD NC XD-VCC SD-VCC
+3VALW 1 2 7 28
R718 0_0805_5% +CARDPWR NC XD_D0 MS-VCC
9 32
CARD_3V3 XD_D1 XD-D0 XDCE_SDCLK_MSCLK
+3VS 1 2 11 D3V3 10 XD-D1 7 IN 1 CONN SD_CLK 20
R719 0_0805_5% 33 10 VREG 1 2 XD_D2 9 14 XD_SD_MS_D0
D3V3 VREG C868 1U_0402_6.3V4Z XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
RTS5159@ 1 1 22 8 12
C869 C870 MS_D4 RTS5159@ XD_D4 XD-D3 SD-DAT1 SD_D2
30 7 30
4.7U_0603_6.3V6K 0.1U_0402_16V4Z NC XD_D5 XD-D4 SD-DAT2 SD_D3
8 6 29
@ RTS5159@ RST# 3V3_IN XD_D6 XD-D5 SD-DAT3 SD_D4
44 5 27
3 2 2 MODE_SEL RST# XD_D7 XD-D6 SD-DAT4 SD_D5 3
45 MODE_SEL 4 XD-D7 SD-DAT5 23
T68 PAD 47 43 XD_CLE 18 SD_D6
CLK_48M_SD XTLO XD_CLE_SP19 XDCE# XDWE# SD-DAT6 SD_D7
23 CLK_48M_SD 48 42 34 16
XTLI XD_CE#_SP18 XD_ALE XDWP XD-WE SD-DAT7 SDCMD_MSBS_XDWE#
XD_ALE_SP17 41 33 XD-WP SD-CMD 25
USB20_N4 4 40 SDDAT2_XDRE# XD_ALE 35 1 XDCD0#_SDCD#
28 USB20_N4 USB20_P4 DM SD_DAT2/XD_RE#_SP16 SDDAT3_XDWE# XD_CD# XD-ALE SD-CD-SW
28 USB20_P4 5 39 40
+3VS 5IN1_LED# DP SD_DAT3/XD_WE#_SP15 XD_RB XD_RB XD-CD XDWP_SDWP
14 38 39 2
GPIO0 XD_RDY_SP14 SDDAT4_XDWP#_MSD7 XD_RE XD-R/B SD-WP-SW
37 38
SD_DAT4/XD_WP#/MS_D7_SP13 SDDAT5_XDD0_MSD6 RTS5159@ XDCE#_R XD-RE
35 37
SD_DAT5/XD_D0/MS_D6_SP12 SDCLK_XDD1_MSCLK_L SDCLK_XDD1_MSCLK XD_CLE XD-CE XDCE_SDCLK_MSCLK
SD_CLK/XD_D1/MS_CLK_SP11 34 2 1 36 XD-CLE MS-SCLK 26
2
Internal 200K PU R722 stuff for RTS5159 31 SDDAT6_XDD7_MSD3 R720 0_0402_5% 17 XD_SD_MS_D0
SD_DAT6/XD_D7/MS_D3_SP10 XDCD1#_MSCD# MS-DATA0 MS_D1
29 11 15
@ R721 MODE_SEL MS_INS#_SP9 SDDAT7_XDD2_MSD2 7IN1 GND MS-DATA1 XD_SD_MS_D2
SD_DAT7/XD_D2/MS_D2_SP8 28 31 7IN1 GND MS-DATA2 19
100K_0402_5% 27 SDDAT0_XDD6_MSD0 24 MS_D3
SD_DAT0/XD_D6/MS_D0_SP7 MS-DATA3
1
1 26 SDDAT1_XDD3_MSD1 22 XDCD1#_MSCD#
1
12
DGND
32
DGND EEDO
15 XTAL_CTR
EECS 16 Open --> 12MHz. X'tal
+CARDPWR +3V_MCVCC 6 17
CLK_48M_SD AGND EESK SDCMD_MSBS_XDWE# PU --> CLKGEN 48MHz C541 1 C544 1 C545 1
46 36
AGND SD_CMD
2
RTS5158E,RTS5159
1
0_0402_5%
R726
1
2
1
2
1 Close conn
C873 R717 C867 RTS5159@ RTS5159@
100K_0402_5% 0.1U_0402_16V4Z 10U(RTS5159)
10P_0402_50V8J 2 RTS5159@
1
2 RTS5159@ @
Security Classification Compal Secret Data Compal Electronics, Inc.
EMI Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
http://rusefix.com
reserved Close chip THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTS5159 / (JMB385) card reader
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 33 of 57
A B C D E
A B C D
+3V_LAN
+3V_LAN
60mil
+3VALW 1 2
R262 0_1206_5% 1
1
1 1 1 1 8131@
C594 R260 1 2 +2.5V_VDDH
C596 C8 C12 C4 0.1U_0402_16V4Z 10K_0402_1% R259 0_0402_5%
3
10U_0805_10V4Z 8121@ 2 Q34 8121@
0.1U_0402_16V4Z
2 2 2 2
2
10U_0805_10V4Z 1U_0402_6.3V4Z 1 CTR12
1
NJT4030PT1G_SOT223 C589
4
2
1 1
8121@ 0.1U_0402_16V4Z
Place Close to Pin 2 +1.2_AVDDL 2 8131@
1 1
C5 C6
10U_0805_10V4Z 0.1U_0402_16V4Z
8121@ 8121@ +3V_LAN +3V_LAN
2 2
1 2 +1.8_VDD/LX
1
R7 8121@ 0_0603_5%
DVT 1 R28
C26 4.7K_0402_1%
1 2
L48 8131@ 0.1U_0402_16V4Z
1
S INDUC_ 4.7UH +-20% SIA4012-4R7M @ 2
D2
R25
10/100_LINK_LED 2 U2 4.7K_0402_1%
+AVDD_CEN +AVDD_CEN 1 R257 2 +2.5V_VDDH/VDD17 1 2 +2.5V_VDDH 1 1 8
8131@ 0_0603_5% R258 8121@ 0_0603_5% 1000_LINK_LED LAN_LINK# 35 A0 VCC
1 1 3 2 7
2
C9 C591 A1 WP TW SI_SCL
3 A2 SCL 6
0.1U_0402_16V4Z 10U_0805_10V4Z 4 5 TW SI_SDA
8131@ 8131@ CHP202UPT_SOT323-3 GND SDA
2 2 AT24C02BN-SH-T_SO8
@
LED_LINK10_100n LAN_MIDI1+
+3V_LAN 2 VDD3V LED_ACTn 47 LAN_ACTIVITY# 35 1 2
R21 49.9_0402_1% 1 2 C18 0.1U_0402_16V4Z
8121@ 27 1 2 LAN_MIDI1- 1 2
SPI_CS/LED_DUPLEXn/LED_DUPLEXn LAN_CLKREQ# 23
2 1 +2.5V_VDDH/VDD17 6 R462 0_0402_5% R22 49.9_0402_1%
C7 1U_0402_6.3V4Z VDD3V/VDDHO/VDDHO LAN_MIDI2+ 1 2
2 1 26 1000_LINK_LED R24 49.9_0402_1% 1 2 C21 0.1U_0402_16V4Z
C11 0.1U_0402_16V4Z CTR12 SPI_DI/NC/LED_Link1000n LAN_MIDI2-
5 VDDLO/CTR12/CTR12 1 2
DVT 8131@ 40 R26 49.9_0402_1%
REFCLKN CLK_PCIE_LAN# 23 LAN_MIDI3+
REFCLKP 41 1 2
3 CLK_PCIE_LAN 23 R30 49.9_0402_1% 1 2 C25 0.1U_0402_16V4Z
11,13,14,24,27,33,36,38 PLT_RST# PERSTn
14 LAN_MIDI0- LAN_MIDI3- 1 2
TXN0/TXN0/TRXN0 LAN_MIDI0- 35
8121@ 13 LAN_MIDI0+
LAN_MIDI0+ 35
、19、25
VAUX/VREF TXP0/TXP0/TRXP0 LAN_MIDI1-
2 1 C10 7 VAUX_AVL/VBG1P18/VBG1P18 RXN1/RXN1/TRXN1 18 LAN_MIDI1- 35
17 LAN_MIDI1+
RXP1/RXP1/TRXP1 LAN_MIDI1+ 35
1000P_0402_50V7K LAN_MIDI2-
38 EC_PME#
C24 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3
4 WAKEn NC/NC/TRXN2 21
LAN_MIDI2+
LAN_MIDI2- 35 Place Close to Pin15
Atheros
10 PCIE_PTX_C_IRX_N3 1 37 TX_N NC/NC/TRXP2 20 LAN_MIDI2+ 35
C23 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 LAN_MIDI3-
10 PCIE_PTX_C_IRX_P3 1
PCIE_ITX_C_PRX_N3
38
44
TX_P NC/NC/TRXN3 24
23 LAN_MIDI3+
LAN_MIDI3- 35 C608 close to Pin15
10 PCIE_ITX_C_PRX_N3 RX_N NC/NC/TRXP3 LAN_MIDI3+ 35
PCIE_ITX_C_PRX_P3 43
10 PCIE_ITX_C_PRX_P3 RX_P
@ AR8121/8131 C601
2 1 XTALO 9 42 +AVDDVCO2 0.1U_0402_16V4Z
23 CLK_48M_LAN XTLO AVDDL0
R716 0_0402_5% LAN_XTALI 10 39 +1.2_AVDDL +2.5V_VDDH
XTLI AVDDL1
DVT2 Close R261 AVDDL2 36 1 1 1
22 C608 C598
DVDDL/AVDDL/AVDDL 1U_0402_6.3V4Z 0.1U_0402_16V4Z
34 TESTMODE AVDDL3 16
35 11 +AVDDVCO1
+3V_LAN NC AVDDL4 +1.2_AVDDL 2 2 2
AVDDL5 8
LAN_SMBCLK 31 46 +1.2_DVDDL
LAN_SMBDATA SMCLK DVDDL0
33 SMDATA AVDDL/DVDDL/DVDDL 45
1
3 3
DVDDL1 32
R652 R653 28
4.7K_0402_5% SPI_CLK/DVDDL/DVDDL
4.7K_0402_5%
49 GND
25 +2.5V_VDDH +1.2_AVDDL
2
SPI_DO/AVDDH/AVDDH L1 FBMA-L11-201209-221LMA30T_0805
AVDDH0 19
LAN_SMBDATA R9 1 2 2.37K_0402_1% 12 15 1 2 +1.2_DVDDL
RBIAS AVDDH1 8121@
LAN_SMBCLK
AR8131L-AL1E_QFN48_6X6
SA000038N00 S IC AR8131L-AL1E QFN 48P E-LAN CTRL PVT R264 0_0603_5%
SA000025M00 S IC AR8121-AL1E QFN 48P E-LAN CTRL 1 2 1 2 +AVDDVCO1
、 、 、46 、 、 、36、39
@ 1 1
R263 C600
0_0603_5% C599 1U_0402_6.3V4Z
Place Close to Pin 28 32 45 Place Close to Pin8 16 22 1000P_0402_50V7K
2 2
C15 and C607 close to Pin46 C590 and C595 close to Pin8
C597 C604
C16 close to Pin45 +1.2_AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z
Y2
1 2 LAN_XTALO If not overclocking, R263 , L2 suffed and R264 removed.
AR8131:L2=0ohm (more power saving mode)
1 25MHZ_20P 1
C593 C592
27P_0402_50V8J 27P_0402_50V8J
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
http://rusefix.com
Issued Date 2008/04/16 Deciphered Date 2009/04/16 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Atheros AR8131
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 34 of 57
A B C D
5 4 3 2 1
D D
1
2 2
1
1 1 1 1
C611 C603 C41 C39
R31 R33
B 0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% LAN_ACTIVITY# B
1 2
2 2 2 2 C19
2
68P_0402_50V8J
0.1U_0402_16V4Z 0.1U_0402_16V4Z RJ45_GND @
40mil LAN_LINK# 1 2
C56
Place close to TCT pin 68P_0402_50V8J
@
For EMI
A A
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 35 of 57
5 4 3 2 1
A B C D E
1 1
To USB/B Connector
+3VALW 80mil
JP2
1 +5VALW
1
2 2
1
3
For Wireless LAN +5VALW R435
100K_0402_5%
3
4 4
5
SYSON# 37,45,51
DVT
5 USB20_N0 28
6 USB20_P0 28
+3VS +1.5VS 6
1 7
2
C819 USB_OC#2 7
8 8 USB_OC#2 28
1 9
4.7U_0805_10V4Z GND
1 1 1 1 1 1 GND 10
C842 C841 C813 C825 C808 C823 2 C811
0.1U_0402_16V4Z ACES_85201-08051
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
2 2 2 2 2 2
JMINI1
SB_PCIE_WAKE# R457 1 @ 2 0_0402_5% 1 2
28 SB_PCIE_WAKE# 1 2 +3VS
WLAN_BT_DATA 3 4
37 WLAN_BT_DATA 3 4
WLAN_BT_CLK 5 6
37 WLAN_BT_CLK 5 6 +1.5VS
23 MINI1_CLKREQ# 7 8
7 8
9 10
2 9 10 2
23 CLK_PCIE_MINI1# 11 11 12 12
23 CLK_PCIE_MINI1 13 14
13 14
15 16
15 16
17 18
17 18 WL_OFF#
19 19 20 20 WL_OFF# 38
21 22 PLT_RST# PVT Q55 SI2301BDS_SOT23
21 22 +3V_WLAN PLT_RST# 11,13,14,24,27,33,34,38 R745
23 24 R458 1 2 0_0603_5% +3VS UB@
10 PCIE_PTX_C_IRX_N2 23 24 +3VS_FP
25 26 R459 1 2 0_0603_5% MP(Remove) 2 1 1 3
S
D
10 PCIE_PTX_C_IRX_P2 25 26 +3VALW +3VS
27 28 @
27 28 ICH_SMBCLK0 @ 0_0603_5%
29 30 ICH_SMBCLK0 8,9,23,28
29 30
2
31 32 ICH_SMBDATA0 R746
G
10 PCIE_ITX_C_PRX_N2 ICH_SMBDATA0 8,9,23,28
2
31 32 100K_0402_5%
10 PCIE_ITX_C_PRX_P2 33 34
33 34 UB@
35 36 USB20_N8 28
35 36
37 38 USB20_P8 28
37 38
+3VS 39 40
1
39 40
41 42 (MINI1_LED#)
41 42
43 44 MINI1_LED# 39
43 44
45 45 46 46
0_0402_5% 47
47 48
48 (9~16mA)
1
R432 1 E51TXD_P80DATA_R R747 4.7K_0402_5% D
38 E51TXD_P80DATA 2 49 50
E51RXD_P80CLK 49 50 Q56
38 E51RXD_P80CLK 51 52 24,38 BKOFF# 1 2 2
51 52 G 2N7002_SOT23
UB@ UB@
G1
G2
G3
G3
3
FOX_AS0B226-S99N-7F 1
53
54
55
56
CONN@
高
C876 @
0.01U_0402_25V7K
2
5.2 mm
3 3
+3VALW +3VS
Fingerprint Conn
2
0_0603_5%
0_0603_5%
Mini Card Power Rating D16
R159
R156
USB20_N13 6 3
CH3 CH2
Power Primary Power (mA) Auxiliary Power (mA)
1
Peak Normal Normal @
+3VS 5 2
Vp Vn
+3VS 1000 750
PVT JP3
+3V 330 250 250 (wake enable) C406 6
0.1U_0402_16V4Z G2 USB20_P13
5 4 1
+3VS_FP G1 CH4 CH1
+1.5VS 500 375 5 (Not wake enable) USB20_N13
2 1 4
4
28 USB20_N13 3 CM1293-04SO_SOT23-6
USB20_P13 3
28 USB20_P13 2
2
1 1
ACES_85201-04051
CONN@
4 4
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN) / FP / Ext USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 36 of 57
A B C D E
A B C D E
Bluetooth Conn.
+USB_VCCA
3
2
S
6 3 USB20_P6_R
G
AO3413_SOT23-3 CH3 CH2
38 BT_ON# 1 2 2
R451 10K_0402_5% Q41 1 2
D R172 @ 0_0402_5%
1
+USB_VCCA 5 Vp Vn 2
C840 W=40mils
+BT_VCC DVT L36 JUSB1
0.1U_0402_16V4Z USB20_N6 1 2 1
28 USB20_N6 1 2 USB20_N6_R VCC USB20_N6_R
1 2 4 1
D- CH4 CH1
1
C830 C831 USB20_P6_R 3
R450 USB20_P6 D+ CM1293-04SO_SOT23-6
28 USB20_P6 4 3 4
4.7U_0805_10V4Z 300_0603_5% 4 3 GND
2 0.1U_0402_16V4Z WCM2012F2S-900T04_0805 5
GND1
6
2
GND2
7
GND3
1 2 8 GND4
1
D R170 @ 0_0402_5%
2 Q42 SUYIN_020173MR004G565ZR
G 2N7002_SOT23 CONN@
S
3
+3VALW
+BT_VCC
+5VALW
1
JP4 +USB_VCCA R166
2 U16 R168 0_0402_5% 2
1 1 GND 9 80mil
2 1 8 100K_0402_5% 1 2
2 GND OUT USB_OC#1 28
28 USB20_P12 3 2 7
3 IN OUT
28 USB20_N12 4 3 6
2
R453 0_0402_5% 4 IN OUT R167 1
5 5 1 4 EN# FLG 5 2 10K_0402_5% USB_OC#0 28
1 @ 2 6 C428
36 WLAN_BT_DATA 6
1 2 7 TPS2061DRG4_SO8
36 WLAN_BT_CLK 7
R455 @ 0_0402_5% 8 10 4.7U_0805_10V4Z 1
8 GND 2 C421
ACES_87213-0800G 0.1U_0402_16V4Z
CONN@
2
36,45,51 SYSON#
+USB_VCCA
+USB_VCCA
1 W=80mils
1
C697 + C246
220U_6.3Φ*5.9_6.3VM 470P_0402_50V7K
2 2
3 3
1 2
DVT R102 @ 0_0402_5%
eSATA CONN
(Reserved) 28 USB20_N1
USB20_N1 1
L29
1 2
2
USB20_N1_R
1
JUSB2
VCC
2
+USB_VCCA USB20_P1_R D-
3 D+
USB20_P1 4 3 4
28 USB20_P1 4 3 GND
W=60mils JSAT1
1 USB WCM2012F2S-900T04_0805 5
USB20_N1_R VBUS GND1
2 6
USB20_P1_R D- GND2
3 D+ 7 GND3
4 1 2 8
GND GND4
Close chip R103 @ 0_0402_5%
5 SUYIN_020173MR004G565ZR
SATA_STX_C_DRX_P2 GND
29 SATA_STX_C_DRX_P2 6 CONN@
SATA_STX_C_DRX_N2 A+ ESATA
29 SATA_STX_C_DRX_N2 7
@ A-
8 12
C855 SATA_DTX_SRX_N2 GND SHIELD
29 SATA_DTX_C_SRX_N2 1 2 0.01U_0402_25V7K 9 B- SHIELD 13
C856 1 2 0.01U_0402_25V7K SATA_DTX_SRX_P2 10 14
29 SATA_DTX_C_SRX_P2 B+ SHIELD
@ 11 15 D14
GND SHIELD USB20_P1_R
Close conn 6
CH3 CH2
3
TYCO_1759594-1
@
+USB_VCCA 5 2
Vp Vn
4 USB20_N1_R 4
4 1
CH4 CH1
DVT2
CM1293-04SO_SOT23-6
(PCB footprint : TYCO_1909574-1_11P-T)
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BlueTooth / Int USB x2 /eSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 37 of 57
A B C D E
5 4 3 2 1
ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
KSI[0..7] 39
ACES_85205-0400
ENBKL @
ENBKL 11
D D
+3VALW
DVT2
111
125
22
33
96
67
9
U20 65W /90W # 2 1
R205 100K_0402_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
+3VALW VR_ON 2 1
R213 100K_0402_5%
3S/4S# 1 2
2 1 LID_SW # EC_GA20 1 21 INVT_PW M R203 4.7K_0402_5%
28 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PW M 24
R221 100K_0402_5% EC_KBRST# 2 23 BEEP#
28 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 42
SERIRQ 3 26
27 SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
27 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 49
C547 LPC_AD3 5 2 1 ECAGND
27 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C520 0.01U_0402_16V7K
27 LPC_AD2 LAD2
2 1 R220 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP Analog Project ID definition
27 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 47
LPC_AD0 BATT_OVP
27 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 49
ADP_I/AD2/GPIO3A 65 ADP_I 49
CLK_PCI_EC 12 AD Input 66 AD_BID0 +3VALW
27,31 CLK_PCI_EC PCICLK AD3/GPIO3B
PLT_RST# 13 75
11,13,14,24,27,33,34,36 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
37 76 AD_PID0
ECRST# SELIO2#/AD5/GPIO43
2
EC_SCI# 20
28 EC_SCI# SCI#/GPIO0E
+3VALW 2 1 38 R181
CLKRUN#/GPIO1D
R215 47K_0402_5%
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG
DAC_BRIG 24 Ra 100K_0402_5%
2 1 70 EN_DFAN1 @
EN_DFAN1/DA1/GPIO3D EN_DFAN1 44
C533 0.1U_0402_16V4Z DA Output 71 IREF
IREF 49
1
KSI0 IREF/DA2/GPIO3E CALIBRATE# AD_PID0
55 KSI0/GPIO30 DA3/GPIO3F 72 CALIBRATE# 49
KSI1 56 KSI1/GPIO31
2
KSI2 57 1
KSI2/GPIO32
+5VS KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE
EC_MUTE 43 Rb R180 C488
C KSI4 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 PX_+VGA_CORE PX_+VGA_CORE 41 GPU_CORE (EC->PWM) C
KSI5 60 85 TP_LOCK _LED# TP_LOCK _LED# 39 100K_0402_5% 0.1U_0402_16V4Z
KSI5/GPIO35 PSCLK2/GPIO4C 2
1 2 TP_CLK KSI6 61 PS2 Interface 86 BT_LED# BT_LED# 39 @ @
1
R189 4.7K_0402_5% KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 39 DVT
1 2 TP_DATA KSO0 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA
TP_DATA 39
R188 4.7K_0402_5% KSO1 40
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 3S/4S# Analog Board ID definition
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# 49
KSO4 43 98 65W /90W #
KSO4/GPIO24 SDICLK/GPXOA01 65W /90W # 49
KSO5 EC_VLDT_EN
+3VS KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
EC_VLDT_EN 41
+3VALW
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 39
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
2
1 2 EC_SMB_CK2 KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 39
R191 2.2K_0402_5% KSO10 49 120 R195
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 39
1 2 EC_SMB_DA2 KSO11 50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 EC_SPICLK 39 Ra
R190 2.2K_0402_5% KSO12 51 128 100K_0402_5%
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 39
KSO13 52
1
KSO14 KSO13/GPIO2D R473 @ 0_0402_5% AD_BID0
53 KSO14/GPIO2E
KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 1 2 PX_GPIO1 27,45 GPU_1.1VS (EC->MOS)
1
+3VALW KSO16 81 74 1 2 PX MODE SWITCH (EC->MUX)
KSO16/GPIO48 CIR_RLC_TX/GPIO41 PX_GPIO2 11,24,26 1
KSO17 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 R472 @ 0_0402_5%
FSTCHG 49 Rb R194 C503
1 2 EC_SMB_CK1 BATT_CHGI_LED#/GPIO52 90 BATT_BLUE_LED# BATT_BLUE_LED# 40
R193 2.2K_0402_5% 91 CAPS_LED# 56K_0402_5% 0.1U_0402_16V4Z
CAPS_LED#/GPIO53 CAPS_LED# 40 2
1 2 EC_SMB_DA1 6,47 EC_SMB_CK1
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# BATT_AMB_LED# 40
2
R192 2.2K_0402_5% EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 PW R_LED
6,47 EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 PW R_LED 40
EC_SMB_CK2 79 SM Bus 95 SYSON MP
6,22 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 45,50
EC_SMB_DA2 80 121 VR_ON
6,22 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 53
127 ACIN
B AC_IN/GPIO59 ACIN 15,29,40,46,49 B
EC_CRY1 EC_CRY2
PM_SLP_S3# 6 100 EC_RSMRST#
28 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 28
PM_SLP_S5# 14 101 EC_LID_OUT# 2 2
28 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 28
EC_SMI# 15 102 EC_ON
28 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 41
4
16 103 EC_SW I# C532 C535
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# 28
GPU_POWER ENABLE (SB->EC) 17 104 EC_PW ROK 15P_0402_50V8J
IN
OUT
27 PX_GPIO1_SB SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK 41 1 1
PX MODE SWITCH (NB->EC) 11 PX_GPIO2_NB 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF#
BKOFF# 24,36
15P_0402_50V8J
19 GPIO 106 W L_OFF#
EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# 36
25 EC_THERM#/GPIO11 GPXO10 107 PX_+1.8VS PX_+1.8VS 45 GPU_1.8VS (EC->MOS)
FAN_SPEED1 PX_+3VS GPU_3VS (EC->MOS)
NC
NC
44 FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 PX_+3VS 19
BT_ON# 29 PVT DVT2
+3VALW 37 BT_ON# FANFB2/GPIO15
E51TXD_P80DATA 30
3
E51RXD_P80CLK EC_TX/GPIO16 VGATE D42 RB751V_SOD323
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE 53
1 2 EC_PME# ON/OFF 32 112 ENBKL 1 2
41 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 UMA_ENBKL 11
R222 10K_0402_5% 40 PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD UMA@
PWR_LED#/GPIO19 GPXID3 EAPD 42
NUM_LED# 36 GPI 115 EC_THERM# X1
40 NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# 29
116 SUSP# 1 2 32.768KHZ_12.5P_MC-306
GPXID5 SUSP# 41,45,52 VGA_ENBKL 15
117 PBTN_OUT#
GPXID6 PBTN_OUT# 28
1
118 EC_PME# D41 RB751V_SOD323
EC_CRY1 GPXID7 EC_PME# 34 VGA@ DVT
122 XCLK1
EC_CRY2 123 124 R211
XCLK0 V18R 10K_0402_5%
1
AGND
C534
GND
GND
GND
GND
GND
2
C523 100P_0402_50V8J
1U_0402_6.3V4Z BATT_TEMP 2 1
KB926QFB1_LQFP128_14X14 2 C514 100P_0402_50V8J
11
24
35
94
113
69
20mil BATT_OVP 2 1
A
L44 C539 100P_0402_50V8J A
ECAGND 2 1 ACIN 2 1
FBM-L11-160808-800LMT_0603
KB926 Rev:D3(SA00001J580)
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: W ednesday, March 11, 2009 Sheet 38 of 57
5 4 3 2 1
BIOS(SYS / EC / VGA)
To TP/B Conn.
+3VALW C512 1 2 0.1U_0402_16V4Z
JP7
6 8
+SPI_VCC +5VS TP_CLK 6 8
DVT 38 TP_CLK TP_DATA
5
5 7
7
38 TP_DATA 4
U19 LEFT_BTN# 4
3
EC_SPICS#/FSEL# R208 0_0402_5% +3VS RIGHT_BTN# 3
38 EC_SPICS#/FSEL# 1 CE# VDD 8 2 2
R207 1 2 4.7K_0402_5% SPI_WP# 3 WP# SCK 6 1 2 EC_SPICLK 38 1 1 1 1
+3VALW R204 1 2 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI 38
C403
HOLD# SI C404 ACES_85201-0605
4
VSS SO
2 EC_SI_SPI_SO 38 MP
2
100P_0402_50V8J 100P_0402_50V8J CONN@
MX25L8005M2C-15G_SOP8 R250 2 2
1
620_0402_5%
R206
22_0402_5% PVT RIGHT_BTN#
1
@
+5VS LEFT_BTN#
2
SW4
3
C524 (AMBER)
33P_0402_50V8K LED11 EVQPLHA15_4P C402
HT-191UD_Amber_0603 3 1 D15
@ KSO3 KSI4 0.1U_0402_16V4Z @
4 2 PSOT24C_SOT23
1
5
6
TP_LOCK _LED# SW2 SW3
TP_LOCK _LED# 38
SMT1-05-A_4P SMT1-05-A_4P
LEFT_BTN# RIGHT_BTN#
INT_KBD Conn. T/P lock button LED T/P lock button 3 1 3 1
4 2 4 2
JP8
5
6
5
6
KSI[0..7]
(Left) KSO0
KSI[0..7] 38
1 1
KSO1 2 KSO[0..17]
KSO2 2 KSO[0..17] 38
3
KSO3 3
4
KSO4 4
5 5
KSO5 6
KSO6 6
7
KSO7
KSO8
8
9
7
8 To FUN/B Conn (10PIN)
KSO9 9
10
KSO10 10 JP9
11
KSO11 11
12 1 +5VS
KSO12 12 1 KSO4
13 2
KSO13 13 2 KSO2
14 14 3 3
KSO14 15 4 KSO3
KSO15 15 4 KSI5
16 5
KSO16 16 5 KSI6
17 6
KSO17 17 6
18 7
KSI0 18 7 BT_LED#
19 8
KSI1
KSI2
20
21
19
20
8
9
9
10
MINI1_LED#
BT_LED# 38
MINI1_LED# 36 Lid Switch
KSI3 21 10
KSI4
22
23
22
23
GND
GND
11
12 (Hall Effect Switch)
KSI5 24
KSI6 24 ACES_85201-1005N +3VALW
25 27
KSI7 25 G1
26 28
26 G2
(Right) CONN@ MP
ACES_85201-26051 KSO16 C449 1 2 100P_0402_50V8J
1
CONN@ KSO17 C450 1 2 100P_0402_50V8J 2
2
KSO4 KSO2 KSO3 C70 R38
47K_0402_5%
VDD
KSO15 C448 1 2 100P_0402_50V8J KSO7 C440 1 2 100P_0402_50V8J 0.1U_0402_16V4Z
1
KSI5 WL_BTN# Volume Down Back Up
2
KSO14 C447 1 2 100P_0402_50V8J KSO6 C439 1 2 100P_0402_50V8J 3 1 2 LID_SW#
OUTPUT LID_SW# 38
D10 RB751V_SOD323
KSO13 C446 1 2 100P_0402_50V8J KSO5 C438 1 2 100P_0402_50V8J Program (KBLG0)
GND
KSO12 KSO4
KSI6 BT_BTN# Volume Up 1
C445 1 2 100P_0402_50V8J C437 1 2 100P_0402_50V8J Battery (KALG0) C77
U9
1
A3212ELHLT-T_SOT23W-3 10P_0402_50V8J
KSI0 C451 1 100P_0402_50V8J KSO3 C436 1 100P_0402_50V8J 2
2 2 KSI4 T/P lock
KSO11 C444 1 2 100P_0402_50V8J KSI4 C455 1 2 100P_0402_50V8J
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 39 of 57
Enlightener LED
+5VALW +5VALW
(BLUE) (BLUE) ON/OFF LED RIGHT
2
R16 R10 R13
MP LED5
499_0402_1% 1.5K_0402_5% 620_0402_5%
ACIN# +5VALW 1 2 2 1 PWR_LED#
MP MP HT-191NBQA_BLUE_0603
1
D
PVT PVT ON/OFF LED LEFT (BLUE)
Q3 2 PVT
ACIN 15,29,38,46,49
G
2
2
2N7002_SOT23 S R12 LED1
3
LED7 LED6 392_0402_1%
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 1 2 2 1 PWR_LED#
+5VALW
MP HT-191NBQA_BLUE_0603
(BLUE)
ON/OFF LED DOWN
1
1
ACIN# ACIN# PVT R17 LED8
392_0402_1%
1 2 2 1 PWR_LED#
+5VALW
MP HT-191NBQA_BLUE_0603
(BLUE)
PVT
2
PWR_SUSP_LED#
R1 R2 R3 PWR_LED#
866_0402_1% 866_0402_1% 866_0402_1%
3
PVT PVT PVT
1
6
2N7002DW-T/R7_SOT363-6
2
2
38 PWR_SUSP_LED 5
LED2 LED3 LED4 2N7002DW-T/R7_SOT363-6 Q31B
38 PWR_LED 2
1
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 Q31A
4
1
R249
1
R240 10K_0402_5%
10K_0402_5%
1
1
MEDIA_LED# NUM_LED# NUM_LED# 38 CAPS_LED# CAPS_LED# 38
2
2
PWR_LED# MEDIA_LED# CAPS_LED#
D5 D7 D6
Compal Footprint
4 2
1
MP
R244
1 2 4 3 PWR_SUSP_LED#
+5VALW A
866_0402_1%
HT-297UD/CB _BLUE/AMB_0603
+3VS
MP
R247 LED10
330_0402_5%
1 2 2 1 BATT_BLUE_LED#
+5VALW B
BATT_BLUE_LED# 38
Q2A R246
2
2N7002DW-T/R7_SOT363-6 1 2 4 3 BATT_AMB_LED#
+5VALW A
BATT_AMB_LED# 38
6 1 866_0402_1%
5IN1_LED# 33
HT-297UD/CB _BLUE/AMB_0603
MEDIA_LED# 3 4 SATA_LED# 29
Q2B BLUE/AMBER
5
2N7002DW-T/R7_SOT363-6 +3VS
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 40 of 57
A B C D E
Power Button
ON/OFF switch
+3VALW
TOP Side
1 2
1 R5 @ 10K_0603_5% HDA MDC Conn. +3VALW 1
2
1 2 R8 1
R4 @ 10K_0603_5% C844
100K_0402_5%
JMDC1 20mil 1U_0402_6.3V4Z
Bottom Side
1
SW1 D3 1 2 2
SMT1-05-A_4P 1 2
2 ON/OFF 38 28 HDA_SDOUT_MDC 3 3 4 4
1 3 ON/OFFBTN# 1 5 6
5 6 +3VALW
3 51ON# 46 28 HDA_SYNC_MDC 7 8
HDA_SDIN1_MDC 7 8
2 4 28 HDA_SDIN1 1 2 9 9 10 10
DAN202UT106_SC70-3 R456 33_0402_5% 11 12
28 HDA_RST_MDC# 11 12 HDA_BITCLK_MDC 28
6
5
1
ACES_88018-124N
R460
CONN@ 0_0402_5%
1
2
C3 D1
2
1
1000P_0402_50V7K RLZ20A_LL34 C843
1
2
22P_0402_50V8J
2
1
D
38 EC_ON
EC_ON 2 Q1 For EMI
G
2
S 2N7002_SOT23
R6 3
10K_0402_5%
2 2
1
Power ON Circuit
+3VS
MP(Remove)
+3VALW +3VALW
1
U22A U22B
R235 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
For South Bridge
14
14
P
2
1 2 3 4 1 2 SB_PWRGD 6,11,28
I O I O R234 @ 0_0402_5%
G
G
1
D
2
45 SUSP 2
7
G C568
Q25 S 1U_0805_25V4Z
3
2N7002_SOT23 UB@ 1 1 2
38 EC_PWROK
UB@ R233 0_0402_5%
3 3
+3VS
+3VALW +3VALW
1
R236
U22C U22D For +1.2HT
14
14
P
2
SUSP# 1 2 5 6 9 8 1 @ 2
38,45,52 SUSP# I O I O VLDT_EN 45,50,51
2 R232 0_0402_5%
G
RB751V_SOD323 C567
UB@
7
0.1U_0402_16V4Z 1 2
38 EC_VLDT_EN
UB@ 1 R228 0_0402_5%
+3VALW +3VALW
C565
1 2 0.1U_0402_16V4Z
U22E U22F
For +VGA_CORE
14
14
SUSP# 1 2 11
O 10
13 I
O 12
1 2 VGA_ON 54
I R231 0_0402_5%
G
2
1 2 C563
7
4 0.1U_0402_16V4Z 4
2
D21 VGA@ @
RB751V_SOD323 C564 SUSP# 1
1 2
UB@ 0.22U_0603_16V7K R229 0_0402_5%
1 UB@
38 PX_+VGA_CORE 1 2
R468 0_0402_5%
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK / MDC / CIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 41 of 57
A B C D E
A B C D E F G H
+VDDA 1 2
R446 0_0805_5%
+5VAMP
U32 (output = 300 mA)
1
R441 L92 1 2 60mil 1
10K_0402_5%
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT 5 40mil +VDDA
1 1 2 GND
L93 1 2 C833 C837 1 4.75V
2
KC FBM-L11-201209-221LMAT_0805 3 4 C836
10U_0805_10V4Z SHDN BYP
1 2
C821 1U_0402_6.3V4Z 2 2
0.1U_0402_16V4Z G9191-475T1U_SOT23-5 4.7U_0805_10V4Z
1
1
@ C838 2
R440
10K_0402_5%
1 2 1
2
C820 DVT 0.01U_0402_16V7K
1 2 MONO_IN
1U_0402_6.3V4Z
1
C 1 2
C835 1 R448 Q40 R438 1.3K_0402_1%
38 BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E 2SC2411K_SOT23
3
C834 1 R447 L85
2 1 2
28 SB_SPKR 1U_0402_6.3V4Z MBK1608121YZF_0603
10mil
1
560_0402_5% +3VS_DVDD 1 2 +3VS
D34
R449 CH751H-40PT_SOD323-2 1 1
10K_0402_5% C810 C809
2
0.1U_0402_16V4Z
2 2
10U_0805_10V4Z
L88
+AVDD_HDA MBK1608121YZF_0603
10mil +1.5VS_DVDD 1 2 +3VS
L89 1 2 0.1U_0402_16V4Z
40mil
+VDDA 1 1
FBM-L11-160808-800LMT_0603 1 1 C817 C816
C807
C818 0.1U_0402_16V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2 2
25
38
9
2 2 U31
DVDD_IO
AVDD1
AVDD2
DVDD
14 35 AMP_LEFT
LINE2-L FRONT_L AMP_LEFT 43
15 36 AMP_RIGHT
LINE2-R FRONT_R AMP_RIGHT 43
16 39 HP_LEFT
MIC2_L SURR_L HP_LEFT 43
17 41 HP_RIGHT
MIC2_R SURR_R HP_RIGHT 43
LINE_L 1 2 LINE_C_L 23 45
43 LINE_L LINE1_L SIDE_L
C828 4.7U_0805_6.3V6K
LINE_R 1 2 LINE_C_R 24 46
43 LINE_R LINE1_R SIDE_R
C824 4.7U_0805_6.3V6K For EMI
18 43
CD_L CENTER
20 44 1 2 1 2 C812
CD_R LFE R436 10_0402_5% 22P_0402_50V8J
19
CD_GND
6 HDA_BITCLK_AUDIO 28
MIC1_L MIC1_C_L BITCLK
43 MIC1_L 1 2 21
MIC1_L Close Codec U31
C822 4.7U_0805_6.3V6K
43 MIC1_R
MIC1_R
C826
1 2 MIC1_C_R 22
4.7U_0805_6.3V6K MIC1_R SDATA_IN 8 HDA_SDIN0_AUDIO 1
R437
2
33_0402_5%
HDA_SDIN0 28
(For EMI)
Digital MIC
MONO_IN 12 37 PVT
PCBEEP PIN37_VREFO +3VS
29 L94 JP11
LINE1_VREFO FBMA-11-100505-301T_0402
28 HDA_RST_AUDIO# 11 1
3 RESET# DMIC_CLK DMIC_CLK_R 1 3
LINE2_VREFO 31 1 2 2 2
10 10mil DMIC_DATA 3 5
28 HDA_SYNC_AUDIO SYNC 3 G1
28 MIC1_VREFO_L 4 6
MIC1_VREFO_L 4 G2
28 HDA_SDOUT_AUDIO 5 SDATA_OUT
Place close to Codec 32 MIC1_VREFO_R ACES_88266-04001
MIC1_VREFO_R CONN@
2
DMIC_CLK SPDIFO2
3 30
R439 2 SENSE_A GPIO0/DMIC_CLK MIC2_VREFO
43 HP_PLUG# 1 39.2K_0402_1% 13 10mil 1 2
SENSE A CODEC_VREF
34 27
R443 1 SENSE B VREF
43 LINEIN_PLUG# 2 10K_0402_1% 1 1 C1
R442 2 1 20K_0402_1% 47 40 C814 220P_0402_50V8J
43 MIC_PLUG# 38 EAPD SPDIFI/EAPD JDREF 2 1
C815
1
48 33 0.1U_0402_16V4Z 10U_0805_10V4Z C2
43 SPDIF SPDIFO SENSE C R429 2 2 220P_0402_50V8J
DMIC_DATA 4 26 20K_0402_1%
GPIO1/DMIC_DATA AVSS1
7
DVSS AVSS2
42 R428 close to U31.48
2
ALC888S-VC_LQFP48_7x7
Sense Pin Impedance Codec Signals 1
R373
2
0_0805_5%
1
R372
2
0_0805_5%
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC888S-VC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 42 of 57
A B C D E F G H
A B C D E
+5VAMP
W=40mil
+3VS
1 1
1
C788 C801
C781 0.1U_0402_16V4Z
C799 0.1U_0402_16V4Z 2 2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C
42 AMP_RIGHT C793 1U_0402_6.3V4Z
15
17
25
8
7
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U29
42 AMP_LEFT C802 C800 1U_0402_6.3V4Z
CVDD
HVDD
PVDD
PVDD
VDD
1
1
0.47U_0603_16V4Z
1 R418 R394 1
2
INL_A ROUT-
HPF Fc = 154Hz SPKL+
R390 1 2 100K_0402_5% 24 5
/AMP EN LOUT+ SPKL-
6
R381 1 LOUT-
+5VAMP 2 100K_0402_5% 21 HP_EN
13 HPOUT_R
+5VAMP HP_RIGHT HP_RIGHT_C 1 HP_RIGHT_R HP_R HPOUT_L
1 2 2 28 16
42 HP_RIGHT C803 4.7U_0805_6.3V6K R417 39K_0402_5% HP_LEFT_R INR_H HP_L
2 INL_H
HP_LEFT 1 2 HP_LEFT_C 1 2 3
42 HP_LEFT NC
1
1
1 9 1
2
D 2 2 C790 C789
10
CGND LINE Out/Headphone Out
1
1 2 EC_MUTE 1 29
R385 G EC_MUTE 38 GND 330P_0402_50V7K 330P_0402_50V7K @
100K_0402_1% C785 S Q39 C778 APA2051QBI-TRG_TQFN28_4X4 R383 1 1 JHP1
3
3
2
0.01U_0402_16V7K 2 HPOUT_L HPOUT_L_1 HPOUT_L_2
1 2 1 2 2
2
L84 FBM-11-160808-700T_0603 6
HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
L83 FBM-11-160808-700T_0603
R384 SPDIF_PLUG# 5
56.2_0603_1%
Gain= 10dB 4
2 SPDIF 2
42 SPDIF 7
+5VSPDIF 8
1 10
C782
100P_0402_50V8J 9
2 SINGA_2SJ-E373-T01
CONN@
+5VAMP
+5VAMP
HP_PLUG#
HP_PLUG# 42
2
1
R364
100K_0402_5%
LINE-IN JACK
2
Q36B
R365 5 2N7002DW-T/R7_SOT363-6 D35
6 1
7
1
3
S
G Q36A
2 SPDIF_PLUG# 2 2N7002DW-T/R7_SOT363-6
3
LINEIN_PLUG# 5
D 42 LINEIN_PLUG#
1
R444 L90 4
+5VSPDIF 75_0603_1% FBM-11-160808-700T_0603
1 2 LINE_R_1 1 2 LINE_R_R 3
42 LINE_R
20mil LINE_L_1 1 LINE_L_R
6
42 LINE_L 1 2 2 2
L91 1
R445 FBM-11-160808-700T_06031 1
3 75_0603_1% SINGA_2SJ-E351-S03 3
C829 C827 CONN@
220P_0402_50V7K 220P_0402_50V7K
2 2 (HDA Jack)
For ESD
I/O status:
a. input/output mount 75 ohm
b. input only mount 1K ohm
Int. Speaker Conn. 42 MIC_PLUG#
MIC JACK
JMIC1
MIC1_VREFO_L MIC1_VREFO_R
20mil 8
JP12 7
SPKL+ 1
1
1
SPKL- 2
SPKR+ 2 R430 R431
3 5 5
SPKR- 3 G1 2.2K_0402_5% 2.2K_0402_5%
4 6
4 G2 R434 L87 4
ACES_88266-04001 75_0603_1% FBM-11-160808-700T_0603
2
3
CONN@
42 MIC1_R 1 2 MIC1_R_1 1 2 MIC1_R_R 3
D8 D9 6
SM05T1G_SOT23-3 SM05T1G_SOT23-3 1 2 MIC1_L_1 1 2 MIC1_L_R 2
42 MIC1_L
L86 1
2
@ @ R433 FBM-11-160808-700T_06031 1
75_0603_1% SINGA_2SJ-E351-S01
1
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 43 of 57
A B C D E
FAN1 Conn
+5VS
C108 10U_0805_10V4Z +5VS
1 2
1
U10 D11
1 8 1SS355_SOD323-2
VEN GND
2 VIN GND 7
+VCC_FAN1 3 6
2
VO GND D12
38 EN_DFAN1 2 1 4 5
R62 300_0402_5% VSET GND
1 2
1 APL5605KI-TRL SOP 8P
BAS16_SOT23-3
C105 C121
0.1U_0402_16V4Z 10U_0805_10V4Z
2 1 2
+3VS C119
1000P_0402_50V7K
1 2
1
R298
10K_0402_5%
40mil
JP13 H21 H10 H22 H26 H23 H27 H5
2
1
C670 ACES_85205-03001
1000P_0402_50V7K CONN@
2 @ @ @ @ @ @ @
H7 H14 H13 H9
H_4P2 H_4P2 H_4P2 H_4P2 H6
H_3P7N
1
@ @ @ @ @
H20 H12 H4 H3 H2 H15 H1 H16 H17 H25
H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2
1
@ @ @ @ @ @ @ @ @ @
1
@ @ @ @
@
FD2 FD3 FD1 FD4
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @
H28
H_1P6N
1
@ DVT2
H29
H_6P0x5P0N
1
@ DVT2
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Thursday, February 19, 2009 Sheet 44 of 57
A B C D E
+5VALW
2
+5VALW +5VS R169
4.305A +1.2VALW +1.2V_HT 100K_0402_5%
U24 3.265A
8 1 U17
1
D S
7 2 8 1
D S D S
2
6 3 1 1 DVT 7 2 SYSON#
D S D S 36,37,51 SYSON#
2
1 1 5 4 C576 R238 6 3 1 1
D G D S
1
C571 C570 470_0603_5% C470 R197 D
1 5 D G 4
SI4800BDY_SO8 10U_0805_10V4Z C573 R202 C509 470_0603_5% SYSON 2 Q21
2 2 38,50 SYSON
10U_0805_10V4Z 1K_0402_5% SI4800BDY_SO8 10U_0805_10V4Z C462 G 2N7002_SOT23
1
1 2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 S 1
3
1
2 1U_0402_6.3V4Z
2
1
D 10U_0805_10V4Z R174
1
D
2 SUSP 100K_0402_5%
G 2 VLDT_EN#
+VSB 2 1 5VS_GATE S Q28 G
2
R239 2N7002_SOT23 2 1 1.2VS_GATE S Q22
+VSB
3
200K_0402_5% 1 R196 2N7002_SOT23
1
1
Q29G 0.1U_0603_25V7K D C506
2
2N7002_SOT23 S 2 VLDT_EN# 2
3
1
SUSP
41 SUSP
1
D
2 Q30
+NB_CORE TO +1.1VS_PX 38,41,52 SUSP#
G 2N7002_SOT23
S
3
1
+3VALW TO +3VS +NB_CORE +1.1VS_PX
3.64A R248
+3VALW +3VS U39 10K_0402_5%
4.121A 8 1
2
D S
U23 7 2
D S
2
8 1 6 3 +5VALW
D S D S 1 1
7 2 1 1 5 4 C693 R272
D S D G
6
D S
3 1 1 2 C713 C691 470_0603_5%
2
2 C572 R243 SI4800BDY_SO8 10U_0805_10V4Z C683 VGA@ 2
1 1 5 D G 4
C575 C574 470_0603_5% VGA@ VGA@ VGA@ VGA@ 2 2 R43
1
SI4800BDY_SO8 10U_0805_10V4Z C569 2 2 1U_0402_6.3V4Z 100K_0402_5%
10U_0805_10V4Z 2 2 10U_0805_10V4Z 10U_0805_10V4Z VGA@
1 1
1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z D
1
D
2 PX_+1.1VS_R VLDT_EN#
2 SUSP VGA@ G
G 2 1 1.1VS_PX_GATE S Q44
+VSB
1
Q27 R270 2N7002_SOT23 D
S
3
1
R478 0_0402_5% D
S
3
1
PX_GPIO1 1 @ 2 PX_+1.1VS_R 2 C692
R275 0_0402_5% G Q45 0.1U_0603_25V7K
S 2N7002_SOT23 2 VGA@ R40
3
SUSP 1 2 VGA@ 10K_0402_5%
R278 0_0402_5% 1
2
VGA@
C851
0.1U_0402_16V4Z
+1.8V to +1.8VS @ 2
+5VALW
MP(Remove)
+1.8V +1.8VS +1.8V to +1.8VS_PX
2
6.988A
U40 R63
8 1 +1.8V +1.8VS_PX 100K_0402_5%
D S UB@
7
D S
2 4.556A
2
6 3 1 1 U13
1
D S C712 R292 PX_GPIO1#
1 1 5 4 8 1
C714 C710 D G 470_0603_5% D S
7 2 1 1
D S
2
SI4800BDY_SO8 10U_0805_10V4Z C709 6 3 C367
D S
1
3 2 2 R115 D 3
1 1 5 4
1
3
1
2 2
2 SUSP VGA@
G 10U_0805_10V4Z 10U_0805_10V4Z
1
1.8VS_GATE Q46 D R64
+VSB 2 1 S
3
2
1 +VSB 2 1 1.8VS_PX_GATE S Q14
3
1
2
SUSP 1 2 2N7002_SOT23
R407 0_0402_5% 1 VGA@ R497
VGA@ 100K_0402_5%
C852 UB@
0.1U_0402_16V4Z
1
@ 2 PX_+1.8VS#
1
D
38 PX_+1.8VS 2 Q51
G 2N7002_SOT23
+1.5VS +2.5VS +0.9V +1.8V +1.1VS S UB@
3
1
2
R498
4 R241 R153 R112 R113 R41 10K_0402_5% 4
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% UB@
2
1
1
1
D D D D D
2 SUSP 2 SUSP 2 SYSON# 2 SYSON# 2 VLDT_EN#
G G G G G Security Classification Compal Secret Data Compal Electronics, Inc.
S Q26 S Q18 S Q11 S Q12 S Q5 Issued Date 2008/10/06 2009/10/06 Title
Deciphered Date
3
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 45 of 57
A B C D E
A B C D
1 1
PR1
DC231000500 1M_0402_1%
<BOM Structure>
1 2
SINGA_2DC-G756I200 PL1
SMB3025500YA_2P
VIN VIN
VS
VIN
DC_IN_S1 1 2DC_IN_S2
1
1
@ PR2 PR3
G 2 10K_0402_5% 84.5K_0402_1%
G PR209 PR5
8
3 PC2 PR4 10K_0402_1% 22K_0402_5%
2
PC3 PC4 100P_0402_50V8J PC1 0_0402_5% 3 1 2
P
PJP3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1 2 1
2
15,29,38,40,49 ACIN 0
20K_0402_1%
- 2
1
PR6
PU1A
1
PC6
LM358DT_SO8 PC5
0.1U_0603_25V7K
4
PR7 PD3 1000P_0402_50V7K
2
10K_0402_1% GLZ4.3B_LL34-2
2
2
2
PR8
10K_0402_1%
1 2
RTCVREF
Vin Dectector 2
ML1220T13RE
<BOM Structure>
PJ2 PJ5
+3VALWP 2 2 1 1 +3VALW +0.9VP 2 2 1 1 +0.9V
JUMP_43X118 JUMP_43X79
VIN
PJ4 PJ7
+5VALWP 2 2 1 1 +5VALW +1.8VP 2 2 1 1 +1.8V
2
PD4
LL4148_LL34-2 JUMP_43X118 JUMP_43X118
PD5
1
LL4148_LL34-2
PJ6
BATT+ 2 1 PJ17
1
3 3
200_0603_5%
CHGRTCP 1 2 N1 3 1 PJ18
VS PJ8
+1.2VALWP 2 2 1 1 +1.2VALW 1 1 2 2 +1.5VS
1
+1.5VSP
1
PR12 PC8
100K_0402_1% PC7 0.1U_0603_25V7K JUMP_43X118 @ JUMP_43X79
0.22U_0603_25V7K
2
PR13
2
22K_0402_1%
PJ20
1 2 PJ16
41 51ON# 2 1 1 2
+NB_COREP 2 1 +NB_CORE +VGA_COREP 1 2 +VGA_CORE
JUMP_43X118 @ JUMP_43X79
RTCVREF
1
PJ22 PJ21
PR14
PU2 200_0603_5% 1 2 1 2
PR15 PR16 G920AT24U_SOT89-3 +2.5VSP 1 2 +2.5VS +VGA_COREP 1 2 +VGA_CORE
560_0603_5% 560_0603_5% 3.3V
2
1 2 1 2 3 2 N2 @ JUMP_43X79
OUT IN
+CHGRTC @ JUMP_43X79
PJ23
1
GND PC10
4
PC9 1U_0805_25V4Z PJ9 1 2 4
2 1
@ JUMP_43X118 @ JUMP_43X79
http://rusefix.com
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 46 of 57
A B C D
A B C D
2
PL2 PR17
1
1 1
1
2 47K_0402_1%
3 3
1
4 EC_SMCA 1 2
2
4 EC_SMDA PC12 PC13 PR19 PQ2
5 5
8
6 1000P_0402_50V7K 0.01U_0402_25V7K 13.7K_0402_1% DTC115EUA_SC70-3
2
6 PD6
7 1 2 3
P
7 +
O 1 2 1 2
SUYIN_250133MR007G115ZL TM_REF1 2 -
G
PU3A LL4148_LL34-2
LM393DG_SO8
3
2
0.22U_0603_16V7K
PR20 PR21
100_0402_1% 100_0402_1%
15.4K_0402_1%
1
1
PC14
PR23
PR22
100K_0402_1%
1000P_0402_50V7K
1
2 1 VL
1
PR24
PC15
6.49K_0402_1%
2
2 1 +3VALW P
1
1
PR25
PR26 100K_0402_1%
1K_0402_1%
2
2
2 2
BATT_TEMP 38
2
@ PR27
VL 47K_0402_1%
@ PR28
47K_0402_1%
1
1 2
1
PQ3
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0603_1%_TH11-4H104FT VL
B+
3 1 +VSBP
2
0.22U_1206_25V7K
@ PR30
0.1U_0603_25V7K
1
8
13.7K_0402_1% @ PD7
1
1
PC16
PC17
PR29 1 2 5 LL4148_LL34-2
P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2
G
1
3 3
PR31 PU3B
2
1
VL 22K_0402_1% LM393DG_SO8
4
1 2 @ PC18 @ PR32
0.22U_0603_16V7K 15.4K_0402_1%
2
2
PR33
100K_0402_1%
PR34
1
0_0402_5% PQ4 D
1 2 2
48,51 SPOK G 2N7002W -T/R7_SOT323-3
0.1U_0402_16V7K
S
3
1
PC19
@
2
4 4
http://rusefix.com
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 47 of 57
A B C D
5 4 3 2 1
TPS51427_B+
TPS51427_B+
PR35
PJ10 0_0805_5%
2 1 1 2
D
B+ 2 1
D
JUMP_43X118
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
1
2200P_0402_25V7K
2200P_0402_25V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
1
5
6
7
8
PC20
PC21
PC22
2
8
7
6
5
1
PC25
PC116
VL
PC23
PC24
PC114
1U_0603_10V6K
2
2
PQ6
1
2
2
PQ5 PC26 AO4466_SO8
2
AO4466_SO8 0.1U_0603_25V7K 4
4.7U_0603_6.3V6M
1
PC27
4
PC28
1
+5VALWP
3
2
1
PL4
1
2
3
PL3 8.2UH +-20% FDV0630-8R2M=P3 3.7A
7
8.2UH +-20% FDV0630-8R2M=P3 3.7A PU4 PC29 2 1
1 2 1U_0603_10V6K
LDO
VIN
V5FILT
+3VALWP 33 19 1 2
TP V5DRV
5
6
7
8
1
4.7_1206_5%
1
8
7
6
5
DH3 DH5
PR39
26 DRVH2 DRVH1 15
PR36 PR37 PR40 0_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
VBST2 VBST1
1
AO4712_SO8 0_0603_5%
63.4K_0402_1%
1
2
2
2
PR38 PC32 4
2
PC30 + PC31 0.1U_0603_25V7K
PR41
0_0402_5% 4
2
330U_D2E_6.3VM_R25M 0.1U_0603_25V7K
680P_0402_50V7K
1
1
1
LX3 25 16 LX5 1
2
PC34
3
2
1
2
C 680P_0402_50V7K + PC35 C
1
2
3
DL3 23 18 DL5 150U_D2E_6.3VM_R18
1
DRVL2 DRVL1
2
2
10K_0402_1%
PGND 22
2
FB3 30
@ PR42 VOUT2
PR43
10K_0402_1% 10
VOUT1
VL 32
1
REFIN2
1
11 FB5
2VREF_ISL6237 FB1
1 2 1 VREF2
PC36 0.22U_0603_10V7K
VSW 9
8 LDOREFIN @ PR44 0_0402_5%
SKIPSEL 29 2 1 VL
+3.3VALWP Ipeak=5.92A ; Imax=4.18A PR45 0_0402_5%
Choke DCRmax=60m ohm, DCRtyp=54m ohm 1 2
20 NC PGOOD2 28
Rds(on)=18m ohm(max) ; Rds(on)=15m PD8 PR46
GLZ5.1B_LL34-2 100K_0402_1%
ohm(typical) 1 2 1 2 4 13 SPOK 47,51
VS EN_LDO PGOOD1 PR48
Vlimit=(5E-06 * 330K)/10=165mV
2
330K_0402_1%
200K_0402_5%
B B
PR47
TONSE
VREF3
1
27 31 ILIM2 2 1
GND
1
EN2 TRIP2
1
PD12 PR49
0_0402_5%
21
0_0402_5%
PR51
Iocp=Ilimit+Delta I/2
2
@
2
PR52
=9.71A ~ 11.543A
1
1
806K_0603_1%
1U_0603_10V6K
+5VALWP Ipeak=8.07A ; Imax=5.65A
1
2
0_0402_5% 47K_0402_5% 0_0402_5%
PC143
2VREF_ISL6237
Vlimit=(5E-06 * 330K)/10=165mV
1
PC38
Ilimit=165mV/18m ~ 165mV/15m
2
=9.167A ~ 11A
1
@ PC39
3
0.047U_0402_16V7K
2
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 48 of 57
5 4 3 2 1
A B C D
PQ9 PQ10 B+
AO4407A_SO8 AO4407A_SO8
VIN 8 1 1 8
7 2 2 7 PJ11
6 3 3 6 1 PR56
4 2 1 CHG_B+
2 1
1
5 5
2
0.015_2512_1% JUMP_43X118 PR57
2200P_0402_25V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
2 3
PR58 CHGEN# PC40 100K_0402_1%
2
3.3_1210_5% 0.01U_0402_25V7K
0.01U_0402_25V7K
1
PC42
PC43
PC44
100K_0402_1%
2
1
PC46 PC48
1
2
5
6
7
8
3
2
1
1 1
PC45
PR59
0.1U_0402_16V7K 0.1U_0603_25V7K
1 2 1 2 PQ12
1
PU5 SI4835DDY-T1-E3_SO8
1
PR174 1 CHGEN 28 PVCC PR61 /BATDRV 4
2
3.3_1210_5% PC47 @PC49
@PC49 PVCC 0_0603_5% PQ11
0.1U_0603_25V7K 0.1U_0603_25V7K 1 2 4 AO4466_SO8
2
2
2
PR60 27 BTST
340K_0402_1% BTST
1
3
2
1
5
6
7
8
PC50 ACN 2 26 DH_CHG
1
2.2U_0805_25V6K ACP ACN HIDRV PL5
3
2
10U_1206_25V6M
5 ACDET 2 1 1 2
10U_1206_25V6M
10U_1206_25V6M
2 3
1
PC92
LL4148_LL34-2 PC51 @ PR64
5
6
7
8
PC53
24751_VREF PR63 0.1U_0603_25V7K 4.7_1206_5%
PC52
CELLS GND 3 Cell 54.9K_0402_1%
2
1REGN
2
VREF 4 Cell ACSET 6
1
ACSET
2
24 PQ13
@ PR65 REGN PC54 AO4466_SO8 @
4
@
47K_0402_1% PR66 PC56 1U_0603_10V6K PC55
P C55
2
2
1 2 1 2
1
2
PR67
3
2
1
340K_0402_1% 7
CELLS ACOP DL_CHG
23
1
LODRV
@ PQ14 PC57
1
PGND 22
2 OVPSET 8 1 2
3S/4S# 38 OVPSET
G ACOFF 38
2
S
3
1
PR68 9 21
54.9K_0402_1% AGND LEARN PC58 @PC59
@PC59
24751_VREF 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector
2
1
20 CELLS
PQ15 CELLS
3
1
SI2301BDS-T1-E3_SOT23-3 24751_VREF 10
PC60 VREF
PR69 1U_0603_10V6K
2
100K_0402_1% RTCVREF
CP Point Setting 1 2PQ15_GATE
2 SRP 19 SE_CHG+
1
CP point=Iadapter*85% 11 18 SE_CHG-
VDAC SRN
1
PR70
90W adapter PC62 100K_0402_1% 17
BAT
1
Vacset=3.3*(100K/(64.9K+100K))=2.001V 0.1U_0603_25V7K
2
VADJ 0.1U_0603_25V7K
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A Icharge Setting
2
ACGOOD#
29
ICHG setting PR71 For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
TP 17.4K_0402_1% For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
65W adapter R=(100K*100K)/(100K+100K)=50K 13 ACGOOD
VMB SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
Vacset=3.3*(50K/(50K+64.9K))=1.436V IREF 38 IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
1
PR72
SRSET 16 IREF=0.7748*Icharge
1
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A /BATDRV 14 PR73
BATDRV
1
1 2 100K_0402_1% PC63
100P_0402_25V8K
2
VS PR74 10_0603_5% 24751_VREF
Input OVP : 22.3V 15
2
3
340K_0402_1% IADAPT 3
LI-4S :18.0V----BATT-OVP=2.001V
1
Input UVP : 17.26V BQ24751ARHDR_QFN28_5X5
2
2
BATT-OVP=0.1112*VMB PC64
0.01U_0402_25V7K
2
LI-3S :13.5V----BATT-OVP=1.5012V 100K_0402_1%
1
PC65
1
PR76
200K_0402_1%
1 2
2
1
Per cell=4.5V 499K_0402_1%
100K_0402_1%
ACIN 15,29,38,40,46
1
1
PR180
PQ15_GATE
1
D
PR179
PR78
2
8
1
10K_0402_1% LM358DT_SO8 PQ36 D PQ17 G 2N7002W -T/R7_SOT323-3
5
P
+ SI2301BDS-T1-E3_SOT23-3 PR80
1 2 7 0 2 S
2
3
38 BATT_OVP 6 PC163 G 2N7002W -T/R7_SOT323-3 0_0402_5%
-
G
S
0.1U_0402_16V7K PQ37 REGN 3 VADJ
D
S 1 1 2
3
1
ACOFF 1 24751_VREF
2 2
0.01U_0402_25V7K
4
1
PC66
105K_0402_1%
G
S
3
2
1
2
PR82
340K_0402_1%
221K_0402_1%
2
1
PR181
PR84
@ PR177 1000P_0402_50V7K 100K_0402_1%
2
PR83 4.3K_0402_5%
2
64.9K_0402_1%
2
1
24751_VREF 1 2 ACSET CHGEN#
2
1
PQ19 D
1
1
PQ18 D
2
38 CALIBRATE# G 2N7002W -T/R7_SOT323-3 38 FSTCHG 2
PR85 S G 2N7002W -T/R7_SOT323-3
3
100K_0402_1% S
3
1
PR86
100K_0402_1%
1
PQ20 D
G 2N7002W -T/R7_SOT323-3
S
3
http://rusefix.com
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
4.1V L 887K 221K CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V(1.32) H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 49 of 57
A B C D
A B C D
FB1_NB_COREP
POWER_SEL +5VALW
2
HIGH 1.0V PR122
@ 12K_0402_1%
1
PC68
1
LOW 1.1V PR102 PC67 1U_0402_6.3V6K
1
@ 10K_0402_1% 1U_0402_6.3V6K
PR123
2
1
@ 0_0402_5% D PR87 PR88
2
1 2 2 2.2_0603_1% 2.2_0603_1%
PQ25 G 2 1 1 2
+5VALW +5VALW
1
1 1
@ SSM3K7002F_SC59-3 D
S
3
1 2 2 PQ28
11 POW ER_SEL
1
PR121 G @ SSM3K7002F_SC59-3
@ 0_0402_5% S
3
1
1
PC105 PC70 PC69
2
PC107 @ 0.01U_0402_16V7K 0.1U_0603_25V7K 0.1U_0603_25V7K
@ 0.01U_0402_25V7K
2
PR89 PR90
10_0603_1% 10_0603_1%
ISL6228_B+ 2 1 2 1 ISL6228_B+
PJ12
JUMP_43X118
2 2 1 1
B+ ISL6228_B+
22K_0402_1%
2
100U_25V_M
1000P_0402_50V7K
<BOM Structure>
2
PR92
1
+
PC218
PR91
18.2K_0402_1%
1
PC72 PR93 PC71
PC73
1000P_0402_50V7K 3.3K_0402_5% PR94 1000P_0402_50V7K
1
2 59K_0402_1%
2 1 1 2
2
1
PR95
1
51K_0402_1%
+NB_COREP 2 1 FB1_NB_COREP 29
PGOOD1
FSET1
VIN1
VCC1
VCC2
VIN2
FSET2
GND_T
PR98 PC74
2
PR96 3.3K_0402_5% 1000P_0402_50V7K
10.5K_0402_1% 8 28 PR97 2 1 1 2
2
6228_1.1VO1 FB1 PGOOD2 22.6K_0402_1% 2
1 2
PR99
1
45.3K_0402_1%
ISL6228_B+ 9 27 FB_1.8V-1 1 2 FB_1.8V
VO1 FB2
<BOM Structure>PR100
Structure> PR100
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
PC76
PC77
25.5K_0402_1%
8
7
6
5
1 2 PQ21
AO4466_SO8
Vref=0.6V
2
1
2
3
8
7
6
5
4.7U_1206_25V6K
4.7U_1206_25V6K
5
6
7
8
1
PC81
PC79
1.0UH_PCMC104T-1R0MN_20A_20% PQ22 1 2 4700P_0402_25V7K
D
D
D
D
2
PC80 + <BOM Structure> UGATE1 PHASE2
2
2
330U_D2E_2.5VM 4
G PR106 PQ23 PR105
4
2 0_0603_5% 25.5K_0402_1%
1
S
S
S
1
LGATE1
LGATE2
<BOM Structure> PC84
PGND1
PGND2
BOOT2
PVCC1
PVCC2
2
3
2
1
3 3
0.1U_0402_16V7K LX_1.8V 1 2
+1.8VP
1
5
6
7
8
PR108 PL12
4.7_1206_5% 1UH_FDV0630-1R0M-P3_10.3A_20%
FDS6670AS_NL_SO8
1
D
D
D
D
15
16
17
18
19
20
21
<BOM Structure> <BOM Structure>
+
PQ24
PC88
2
PR109 PC87 330U_D2E_2.5VM
0_0603_5% 0.1U_0402_16V7K 4 G
1
BST_1.8V 1 PC89 2
+5VALW 2 1 2
680P_0402_50V7K
+5VALW
2
S
S
S
<BOM Structure>
2
PC85 PC86
3
2
1
1U_0402_6.3V6K 1U_0402_6.3V6K
1
http://rusefix.com
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP / 1.1VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 50 of 57
A B C D
5 4 3 2 1
PJ13
JUMP_43X118
4.7U_1206_25V6K
51117_B+ 2 2 1 1 B+
PC91
2200P_0402_25V7K
2200P_0402_25V7K
2
2
PQ26
PC120
PC118
DH_1.2V 8 1
PR111 G2 D2
7 2
1
300K_0402_5% S2/D1 D2 DL_1.2V
6 S2/D1 G1 3
PR110 1 2 5 4
0_0402_5% S2/D1 S1
2 1 AO4932_SO8
47,48 SPOK
D D
PR113 PC93 2.2UH +-20% FDV0630-2R2M=P3 7.2A
1
0_0603_1% 0.1U_0603_25V7K PL8
15
14
+1.2VALWP
1
@ PC90 PU7 BST_1.2V 1 2BST_1.2V-1 1 2 1 2
0.01U_0402_25V7K
EN_PSV
TP
VBST
2
2 13 DH_1.2V
TON DRVH
3 12 LX_1.2V 1
VOUT LL
VFB=0.75V + PC95
4 V5FILT TRIP 11 +5VALW 330U_D2E_2.5VM
5 VFB V5DRV 10
2
6 9 DL_1.2V
PGOOD DRVL
PGND
PR114
GND
1
10K_0402_1%
300_0603_5%
PR115
1 2 @ PC96 PC97
+5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K
2
1 2
2
PC98
1U_0603_10V6K
2
PR116
6.34K_0402_1%
1 2
1
+1.2VALW
PR117
C 10K_0402_1% C
+5VALW
2
1
PJ15
1
JUMP_43X79
@
2
PC110
2
1U_0402_6.3V6K
1
PC111
4.7U_0805_6.3V6K
6
PU9
2
5
VCNTL
VIN
VFB=0.75V 7 POK
4 +1.1VSP
Vo=VFB*(1+PR116/PR117)=0.75*(1+10K/10K)=1.5V PR128 VOUT
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/vin)+50ns=3.2E-7 VOUT 3
1
0_0402_5%
22U_0805_6.3V6M
Fsw=200KHz
PC113
VLDT_EN 1 2 8 2
EN FB
1
41,45,50 VLDT_EN PR129
GND
2
1
@ 9 1.15K_0402_1%
@ PC109 PR194 VIN
Cout ESR=15m ohm
2
1U_0603_10V6K 47K_0402_5% APL5912-KAC-TRL_SO8
Ipeak=3.58A, Imax=2.51A
1
2
Delta I=((19-1.2)*(1.2/19))/(L*Fsw)=2.59A PC108
1
0.01U_0402_25V7K
=>1/2DeltaI=1.295A
Vtrip=Rtrip*10uA=10K*10uA=0.1V PR127
Iocp_min=Vtrip/Rdsonmax*1.4+1.295A 3K_0402_1%
B B
2
=0.1/(0.0196*1.4)+1.295=3.644A+1.295A=4.939A
Iocpmax=(0.1/(0.016*1.2))+1.1.295A=5.208A+1.295A +1.8V
=6.503A
Iocp=6.503A~4.939A
1
PJ14
1
JUMP_43X79
2
PU8
2
1 VIN VCNTL 6 +3VALW
2 GND NC 5
1
1
PC99 3 7 PC100
4.7U_0603_6.3V6M PR118 REFEN NC 1U_0402_6.3V6K
2
1K_0402_1% 4 8
VOUT NC
9
2
GND
RT9173DPSP_SO8
PR119
0.1U_0402_16V7K
+0.9VP
1
0_0402_5% PQ27 D
36,37,45 SYSON#
PC101
1 2 2 PR120
1
G 2N7002W -T/R7_SOT323-3
2
1
S PC104
3
PC103 1K_0402_1% 10U_0805_6.3V6M
2
A 0.1U_0402_16V7K A
2
http://rusefix.com
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VALWP/+0.9VP/1.1VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 51 of 57
5 4 3 2 1
5 4 3 2 1
D D
+1.8V
+5VALW
1
PJ24
1
@ JUMP_43X79
2
PC112
1U_0402_6.3V6K
2
2
6
PU11
1
5 PC115
VCNTL
VIN 4.7U_0805_6.3V6K
7 POK
4
2
PR130 VOUT
VOUT 3 +1.5VSP
10K_0402_1%
22U_0805_6.3V6M
1 2 8 EN FB 2
1
38,41,45 SUSP#
PC119
GND
1
@ 9 PR132 PC117
2
VIN
1
PR188 1.54K_0402_1% 0.01U_0402_25V7K
2
C PC121 47K_0402_5% APL5915KAI-TRL_SO8 C
2
0.1U_0402_16V7K
1
PR133
1.74K_0402_1%
2
PU15
APL5508-25DC-TRL_SOT89-3
+3VS 2 3
IN OUT
+2.5VSP
1
4.7U_0805_6.3V6K
PC106
1
B GND B
2
1
A A
http://rusefix.com
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+2.5VSP/+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0
Date: Thursday, February 19, 2009 Sheet 52 of 57
5 4 3 2 1
5 4 3 2 1
CPU_B+ PL15
LGATE_NB HCB4532KF-800T90_1812
PC183 1 2 B+
33P_0402_50V8K
10U_1206_25V6M
2200P_0402_50V7K
0.01U_0402_25V7K
100U_25V_M
2 1
<BOM Structure>
1
1
+
PC185
PC186
PC187
PC188
PQ43
2 1 2 1 UGATE_NB 8 1
G2 D2
7 2
2
PR213 PC184 S2/D1 D2 2
6 S2/D1 G1 3
44.2K_0402_1% 1200P_0402_50V7K 5 4
PR214 S2/D1 S1
2_0603_5% AO4932_SO8
D +5VS 1 2 PC189 PL16 D
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB
2 1 PHASE_NB 1 2
PR215
+VDDNB
1
PC190 PR216 0_0603_5%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 PR217
2 1
2 1 2
4.7_1206_5% 1
Design Current: 2.1A
2
PR218
10_0402_5%
PC191
0.22U_0603_10V7K + PC192
Max current: 3A
1 2
1 2
1 2 +CPU_CORE_NB
PC193
220U_D2_4VM
OCP_min:5A
CPU_B+ 2
680P_0603_50V7K
PR219
CPU_VDDNB_FB_H 6
2
2_0603_5% PR221
+5VS +3VS 11.3K_0402_1%
1
2 1 PHASE_NB
PR220
0_0402_5% LGATE_NB
1
PC194 CPU_B+
0.1U_0603_16V7K PHASE_NB
2
1
2
PR222 PR223 UGATE_NB
2200P_0402_50V7K
0.01U_0402_25V7K
0_0402_5% @ 105K_0402_1%
10U_1206_25V6M
10U_1206_25V6M
5
2 1 CPU_VDDNB_FB_L 6
PR224
2
2
1
1
PC195
PC196
PC197
PC198
0_0402_5%
PR225 PQ45
1
2
105K_0402_1% PR228 10_0402_5% UGATE0 4
@ 105K_0402_1%
48
47
46
45
44
43
42
41
40
39
38
37
2
1
PU14
PHASE0
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
2
C PR229 PL17 C
3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
38 VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +CPU_CORE_0
PR230 0_0402_5% OFS/VFIXEN BOOT_NB
2
1 2 2 35 BOOT0 PC199
PGOOD BOOT0
5
6
7
8
5
6
7
8
27 H_PW RGD_L 1 2 0.22U_0603_10V7K PR232
1
PR231 0_0402_5% @ 3 34 UGATE0 16.2K_0402_1%
PWROK UGATE0 PR233
2 1 4 33 PHASE0 PQ46 PQ47 4.7_1206_5%
1
6 CPU_SVD PR234 0_0402_5% SVD PHASE0 AO4456_SO8 AO4456_SO8 1 PR235 2
5 32 4 4 4.02K_0402_1%
1 2
SVC PGND0 +5VS
2 1
6 CPU_SVC PR236 0_0402_5% 6 31 LGATE0 PC200 PC201
ENABLE LGATE0 680P_0603_50V7K 2 1
7 30
3
2
1
3
2
1
2
RBIAS PVCC 0.1U_0402_16V7K
38 VR_ON 8 29 LGATE1
OCSET LGATE1
1
PR238 PR239 ISL6265IRZ-T_QFN48_6X6~D PC202
2 1 2 1 9 28 1U_0603_16V6K LGATE0
34.8K_0402_1% 82.5K_0402_1% VDIFF0 PGND1
ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE_0
VW0 BOOT1
Design Current: 12.6A
COMP1
VDIFF1
VSEN0
VSEN1
RTN0
RTN1
2200P_0402_50V7K
0.01U_0402_25V7K
ISN0
ISN1
ISP0
VW1
ISP1
FB1
10U_1206_25V6M
10U_1206_25V6M
TP
5
OCP_min:24A
13
14
15
16
17
18
19
20
21
22
23
24
49
1
PC203
PC204
PC205
PC206
PR242 0_0402_5%
B ISP0 PQ48 B
ISN0 SI7686DP-T1-E3_SO8
2
1
ISN1
ISP1
UGATE1 4
6 CPU_VDD0_FB_H
0_0402_5%
VSEN0 0_0402_5%
2 PR244 1
2 PR250 1
0_0402_5%
PR241 PR240
+CPU_CORE_0 2 1 1 2 PHASE1
10_0402_5% PR243 PL18
2
3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
6 CPU_VDD0_FB_L RTN0 BOOT1 1 2 1 2 1 2 +CPU_CORE_1
PR245 10_0402_5%
2
2 1 PC207
5
6
7
8
5
6
7
8
0.22U_0603_10V7K PR247
1
PR246 change as 10K for EVT2 Tigris 16.2K_0402_1%
PR248
RTN1 PQ49 PQ50 4.7_1206_5%
1
6 CPU_VDD1_FB_L PR246 10_0402_5% AO4456_SO8 AO4456_SO8 1 PR249 2
2 1 4 4 4.02K_0402_1%
1 2
PC208 PC209
6 CPU_VDD1_FB_H VSEN1 680P_0603_50V7K 2 1
PR251
3
2
1
3
2
1
2
+CPU_CORE_1 2 10_0402_5%
1 0.1U_0402_16V7K
DIFF_0 VW 0 DIFF_1 VW 1
LGATE1
PR253 PC210 PR254 PC213
ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1
http://rusefix.com
Issued Date Deciphered Date
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KBLG0 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 11, 2009 Sheet 53 of 57
5 4 3 2 1
5 4 3 2 1
PL13
1 2 B+_core
B+
FBMA-L11-322513-201LMA40T_1210 VGA_CORE
10U_1206_25V6M
10U_1206_25V6M
LX_VCORE
1
Imax=11.37A
1
PC164
DH_VCORE 1 PR183 2 DH_VCORE-1
Ipeak=16.24A
PC165
PR184 0_0603_5%
2
BST_VCORE
1 2 1 2
Iocp=19.49A
2
D 0_0603_5%
+5VS
PC166 0.1U_0603_25V7K Cesr=9 mOHM D
Rds(on)=4.8 mOHM
5
PR185 PQ38
0_0603_5% SI7686DP-T1-E3_SO8
16
15
8
1
PU12
2
1 PR1862 6269_VCORE 4
UG
BOOT
PHASE
GND
PGOOD
4.7_0603_5%
3 VIN PVCC 14 1 2 PC167 DCR=3m OHM
+3VS
3
2
1
6269_VCORE 2.2U_0603_6.3V6K
PL14
PC168 4 13 DL_VCORE
2
2.2U_0603_6.3V6K VCC LG 0.56UH_ETQP4LR56WFC_21A_20%
1
1 2 +VGA_COREP
PR187
1
@ 10K_0402_5% 12
2
PGND PQ39 PQ40 PR191
2
@4.7_1206_5% 1 PC169
PR189
1
10_0402_1%
PR190 SI7636DP-T1-E3_SO8 SI7636DP-T1-E3_SO8
+
PR192
1 2 5 11 ISEN_VCORE
1 2
41 VGA_ON
1 2
EN ISEN
330U_V_2.5VM_R9M
4 G 4 G
COMP
100K_0402_1% 7.5K_0402_1% PC171
FSET
<BOM Structure>
1
1
VO
FB
S
S
S
S
S
S
PC170 @680P_0603_50V7K
2
2
10
3
2
1
3
2
1
C 0.1U_0402_16V7K ISL6268CAZ-T_SSOP16 C
2
PR193
1
1
1
22P_0402_50V8J
1 Rds=4.8mOHM 3.48K_0402_1%
1
PR195 VFB=0.6V
+3VS
PC172
PR196
2200P_0402_25V7K
33K_0402_1% PC173
2
0.01U_0402_25V7K PR197
2
2
8.25K_0402_1%
2
PR198 <BOM Structure>
PC174
PR211
40.2K_0402_1% 5.9K_0402_1%
1
2N7002W-T/R7_SOT323-3 10K_0402_5%
2
1
PQ41 PR199
1
D 10K_0402_1%
2 1 2
G
2
S
1
@ PR200
PC175 10K_0402_1%
0.022U_0402_25V7K
1
B B
+3VS
<BOM Structure>
2
PR212
2N7002W-T/R7_SOT323-3 10K_0402_5%
1
1
PR202 D 10K_0402_1% VGA_PWRSEL 15
PQ42 21 2
G
2
S
3
PR201
M92-M2 XT 10K_0402_1%
1
VGA_PWRSEL Core Voltage Level
0 1.2 V
1 0.95 V
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KBLG0 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 19, 2009 Sheet 54 of 57
5 4 3 2 1
http://rusefix.com
5 4 3 2 1
Switch NB_core voltage 0.1 51 ADD PC110, PC111, PC108, PC109, PC1113, PR1128, 2009/01/04
ADD circuit PR194, PR129, PR127 at UMA Sku DVT
2
EMI requestmrnt 0.1 50 Add PR104 4.7 ohm and PC83 680p 2009/01/04 DVT
ADD snubber
3
EMI requestmrnt 0.1 50 Add PR108 4.7 ohm and PC89 680p 2009/01/04
ADD snubber DVT
4
EMI requestmrnt 0.1 53 Add PR229 2.2 ohm 2009/01/04 DVT
ADD CPU boot
5
EMI requestmrnt 0.1 53 Add PR243 2.2 ohm 2009/01/04 DVT
ADD CPU boot
6
Change resistance value Switch NB_core voltage 0.1 50 Change PR95 from 51 Kohm to 39.2 Kohm 2009/01/04 DVT
7
Change resistance value Switch NB_core voltage 0.1 50 Change PR122 from 12 Kohm to 226 Kohm 2009/01/04 DVT
8
C C
Change resistance value soft start of Switch NB_core voltage 0.1 50 Change PR123 from 0 ohm to 10 Kohm 2009/01/04 DVT
9
Change capacitor value soft start of Switch NB_core voltage 0.1 50 Change PC105 from 0.01 uF to o.1 uF 2009/01/04 DVT
10
Change IC part number Change IC part number 0.1 48 Change PU4 part number to SA00002V400 2009/01/04 DVT
11
12
13
14
15
B B
16
17
18
19
20
21
22
A A
23
http://rusefix.com
5 4 3 2 1
D D
P.10 C646/C647/C648/C649/C650/C651/C652/C653 with VGA@ BOM error
P.11 Add R488/R489 (0ohm_0402) & reserve R491/R492 (0ohm_0402) UMA HDMI I2C bus mainly to RS780MN DDC port1 & reserve to port0
P.12 Change L6/L7 from 0ohm_0805 as 0ohm_1206 & with VGA@ For DIS +1.1VS power source from fixed +NB_CORE
P.24 U35/R464/R465/C845/C846/C847/C848/C849 with @ & RP15 with UMA@ Separately as DIS sku only & UMA sku only
C C
P.24 Add RP20/RP21/RP22/RP23(0ohm_0404_4P2R) with VGA@ For DIS sku only
P.24 Reserve Q52/R501/R502/R503 Reserve for UMA sku white screen flash when boot issue check
P.25 Change JHDMI1 from SMD type as DIP type(DC232000800) DFX request
P.25 Change single MOS as 2 dual N-ch MOS(Q53/Q54) & reserve R506 NA (Just no need to modify)
P.26 R47/R58/U25/U26/C626/C628/R475 with UMA@ & R507 with VGA@ , Separately as DIS sku only & UMA sku only
U36/C850 with @ & delete R466 , add R493/R494/R495 with VGA@
B B
P.28 Add R509 with VGA@ & R510 with UMA@ Reserve SKU ID for SW even SW check device ID instead currently
P.37 Change JUSB1 as SB700 USB port6 Dedicated HS port on lower-left position
P.38 D41 with VGA@ & D42 with UMA@ Separately as DIS sku only & UMA sku only
P.38 U20.85 defined as TP_LOCK _LED# feature LED control simultaneously with Tutch-Pad locked function
A A
P.38 Change R194 as 8.2kohm_0402 Change board ID as 1 (PCB revision : 0.2)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: Wednesday, March 11, 2009 Sheet 56 of 57
5 4 3 2 1
http://rusefix.com
5 4 3 2 1
P.45 Stuff R202 +1.2VALW leakege 640mv pulse when AC insertion & then might cause OVP
D D
P.11/38 Add U49/C857/R744 (Reserve U48) & D42 with @, remove D42 NA
P.23/34 Add R676 for CLK_48M_SD , reserve R715 / R716 for CLK_48M_LAN NA
C C
P.33 Add(co-layout) Realtek RTS5159 card reader NA
TIGRIS@ TIGRIS@
P.11 Add C874 / C875 (1u_0402) For CRT(acer lab) flicker
RS880M SB710
B 1 1 1 1 B
P.11/38 C857 / U49 with @ , R744 / D42 with UMA@ NA
1
R60 C664 C666 C727 C194
TIGRIS@ TIGRIS@ 2 TIGRIS@ 2 TIGRIS@ 2 TIGRIS@ 2
1K_0402_5% 10U_0805_10V4Z 3300P_0402_50V7K
P.42 Add L94(SM010027780) close to audio codec For EMI 10U_0805_10V4Z 10U_0805_10V4Z
2
P.40 Modify LED 1 / 5 / 8 from dual Blue/Amber LED as single Blue LED Follow acer spec For Discrete(CRT)
1 1 1
2 1 C633 C640 C662
R285 VGA@ 150_0402_1% VGA@ 2 VGA@ 2 VGA@ 2
Modify R12/R13/R17/R16 (300->220ohm) , modify R1/R2/R3 (1.2K-> 3.3P_0402_50V8J
P.39/40 866ohm) , modify R10 (300->715ohm) , modify R245/R247 (4.99K-> For LED brightness test 3.3P_0402_50V8J 3.3P_0402_50V8J
2 1 1 1 1
750ohm) , modify R244/R246 (4.99K->866ohm) , modify R250 (1.2K->5.1K) R54 VGA@ 2.2K_0402_5% C667 C660 C639
2 1 VGA@ 2 VGA@ 2 VGA@ 2
R46 VGA@ 2.2K_0402_5% 8P_0402_50V8J
P.23 Change LAN_CLKREQ# from U18.51 to U18.24 output NA 8P_0402_50V8J 8P_0402_50V8J
ZZZ
For Discrete(HDMI)
Change test pad (execpt T8/T13/T15/T17/T18/T24/T28 2 1 2 1
NA /T29/T33/T45/T46/T48/T50/T56/T57/T12) from TPC12 to TPC24 PCB R141 VGA@ 499_0402_1% R155 VGA@ 499_0402_1%
2 1 2 1
PCB 047 LA-4921P REV1 M/B R137 VGA@ 499_0402_1% R152 VGA@ 499_0402_1%
Reserve Q55 / Q56 / R745 / R746 / R747 / C876 to turn
off power of finger printer LA4921MB Rev0: DA80000DP00
A P.36 2 1 2 1 A
LA4921MB Rev1: DA80000DP10 R149 VGA@ 499_0402_1% R158 VGA@ 499_0402_1%
2 1 2 1
R194 change as 18K_0402 for change board ID as 3 LA4921MB with Sub/B Rev1: DAZ07R00100 R145 VGA@ 499_0402_1% R157 VGA@ 499_0402_1%
P.38 (PCB revision : 0.4)
Security Classification Compal Secret Data Compal Electronics, Inc.
MP Search for MP font Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
HW PIR
http://rusefix.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBLG0 LA-4921P
Date: W ednesday, March 11, 2009 Sheet 57 of 57
5 4 3 2 1