A B C D E

1 1

ZZZ1
DA2@
MAIN BOARD

DA600007E10
PCB

Compal Confidential
KAYF0 M/B Schematics Document
2 2

Intel Penryn Processor with Cantiga + DDRIII + ICH9M

3
2009-03-09 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 1 of 43
A B C D E
 A B C D E

Compal Confidential page

Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : KAYF0 page 4
EMC1402-1-ACZL ICS9LPRS387
uPGA-478 Package page 4 page 15
File Name : LA-5021P
(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

HDMI Conn. LCD Conn. CRT Conn.

page 25 page 17 page 16
Intel Montevina DDR3 800/1066 MHz 1.5/0.75V DDR3-SO-DIMM X2
LVDS BANK 0, 1, 2, 3 page 13,14

TMDS LVDS uFCBGA-1329 Dual Channel

PCI-Express page 7,8,9,10,11,12
MXM III VGA/B 16X
DMI C-Link MINI Card
page 24
TV-Tuner
7318 Level shift page 22
page 17 PCI-Express
PCI-Express USB Bus Card Reader 6 IN 1
2
Intel ICH9-M RTS5159
2

Bluetooth
S-ATA
Conn
BGA-676 page 32
CMOS
MINI Card LAN(GbE) page 18,19,20,21
BROADCOM 3.3V 48MHz
Camera
WLAN page 17
page 22
BCM5784 page 30
page 23
USB conn x4
port 0 port 1 port 2
3.3V 24.576MHz/48Mhz HD Audio
RJ45
page 25
SATA HDD SATA HDD CDROM
Conn1. Conn2. CONN LPC BUS
page 22 page 22 page 22
3
GMCH HDA MDC 1.5 HDA Codec MXM HDA 3

Conn ALC272
ENE KB926 page 07 page 32 page 26 page 26
RTC CKT. page 31
page 35

RJ11 Phone Jack x3

Power On/Off CKT. Touch Pad Int.KBD page 32
page 27
page 32 page 31
page 32

Cap Sensor BIOS

DC/DC Interface CKT. page 33 ESB BUS page 30

page 34
Audio AMP Subwoofer
page 27 page 27
Power Circuit DC/DC
4
page 39,40,41,42 4
43,44,45,46 Speaker
page 27

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 2 of 43
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails

Symbol Note :
+5VS
+3VS
+1.5VS : means Digital Ground
power
plane +0.75V
+VCCP
+5VALW +1.5V +CPU_CORE : means Analog Ground
+B
+3VALW @ : means just reserve , no build
DEBUG@ : means just reserve for debug.
State +1.8VS

S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1

THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD

SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
SMB_CK_DAT1 ICH9 X X X X V V V X
LCD_CLK
LCD_DAT Cantiga
X X X X X X X V

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 3 of 43
A
 5 4 3 2 1

D D
+VCCP

XDP_TDI R60 1 2 150_0402_1%

<BOM Structure>
XDP_TMS R50 1 2 39_0402_1%
CONN@
(7) H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# (7)

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# (7)
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# (7)
H_A#6 K5 XDP_TRST# R62 1 2 56_0402_5%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# (7)
H_A#8 N2 F21 H_DRDY# XDP_TCK R49 1 2 54.9_0402_1%
A[8]# DRDY# H_DRDY# (7)
H_A#9 J1 E1 H_DBSY# <BOM Structure>
A[9]# DBSY# H_DBSY# (7)
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# (7)
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
A[13]# IERR# PAD T1
H_A#14 P4 B3 H_INIT#
A[14]# INIT# H_INIT# (19)
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# (7)
H_ADSTB#0 M1
(7) H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# (7)
H_REQ#0 K3 F3 H_RS#0
(7) H_REQ#0 REQ[0]# RS[0]# H_RS#0 (7)
H_REQ#1 H2 F4 H_RS#1
(7) H_REQ#1 REQ[1]# RS[1]# H_RS#1 (7)
H_REQ#2 K2 G3 H_RS#2
(7) H_REQ#2 REQ[2]# RS[2]# H_RS#2 (7)
H_REQ#3 J3 G2 H_TRDY#
(7) H_REQ#3 REQ[3]# TRDY# H_TRDY# (7)
H_REQ#4 L1
(7) H_REQ#4 REQ[4]#
G6 H_HIT#
(7) H_A#[17..35] HIT# H_HIT# (7)
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# (7) C
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4 PAD T124
ADDR GROUP_1

H_A#20 W6 AD3
A[20]# BPM[1]# PAD T123
H_A#21 U4 AD1
A[21]# BPM[2]# PAD T122
H_A#22 Y5 AC4
A[22]# BPM[3]# PAD T121
XDP/ITP SIGNALS

H_A#23 U1 AC2
A[23]# PRDY# PAD T125
H_A#24 R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK +3VS
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI
H_A#27 A[26]# TDI
W2 A[27]# TDO AB3
H_A#28 W5 AB5 XDP_TMS
A[28]# TMS

0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# (20)
H_A#31 V4 C2
H_A#32 A[31]# SA00001Z700
W3 A[32]#
H_A#33 2
AA4 A[33]# THERMAL
H_A#34 AB2 H_PROCHOT# R13 1 2 68_0402_5% U1
H_A#35 A[34]# +VCCP SMB_EC_CK2
AA3 A[35]# PROCHOT# D21 1 VDD SCLK 8 SMB_EC_CK2 (31,32)
H_ADSTB#1 V1 A24 H_THERMDA_R R14 1 2 0_0402_5% H_THERMDA
(7) H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC_R R15 1 2 0_0402_5% H_THERMDC H_THERMDA 2 7 SMB_EC_DA2
THERMDC D+ SDATA SMB_EC_DA2 (31,32)
H_A20M# A6 C3
(19) H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6 1 R195 2 +3VS

(19) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (7,19) D- ALERT/THERM2
H_IGNNE# C4 2200P_0402_50V7K 10K_0402_5%
(19) H_IGNNE# IGNNE#
4 THERM GND 5
H_STPCLK# D5
(19) H_STPCLK# STPCLK#
H_INTR C6 H CLK
(19) H_INTR LINT0 ADT7421ARMZ-REEL_MSOP8
H_NMI B4 A22 CLK_CPU_BCLK Address:100_1100
(19) H_NMI LINT1 BCLK[0] CLK_CPU_BCLK (15)
H_SMI# A3 A21 CLK_CPU_BCLK#
(19) H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# (15)
M4 RSVD[01]
THRMDA_2
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2
B (32) THRMDA_2
(32) THRMDC_2
THRMDC_2 V3
RSVD[03]
RSVD[04]
Trace width / Spacing = 10 / 10 mil 2007/09/011 FAN1 Conn B
RESERVED

+VCCP 1 2 B2 RSVD[05]
R5 1K_0402_5% QUAD@ D2
QUAD@ RSVD[06] +5VS
1 2 D22 RSVD[07]
R103 0_0402_5% D3 C638 +5VS
RSVD[08]
F6 RSVD[09] 1 2
1

1
R375 10U_0805_10V4Z
2K_0402_1% U19 D53
QUAD@ 1 VEN 8 1SS355_SOD323-2
Penryn GND
2 VIN 7
2

+VCC_FAN1 GND
3 VO 6 <BOM Structure>

2
EN_FAN11 GND
(31) EN_FAN1 2 0_0402_5%
4 VSET GND 5 D54
1 1 2
+VCCP R1007 C949 APL5607_SOP8
0.1U_0402_16V4Z BAS16_SOT23-3
SA00002XA00 <BOM Structure>
2 C639
1

@ 1 2
R17 @ 10U_0805_10V4Z
56_0402_5% +3VS C640
1000P_0402_50V7K
1 2
2 2

1
B

R538
10K_0402_5%
E

H_PROCHOT# 3 1 OCP# 40mil

OCP# (20)
C

@ Q2 JP32

2
MMBT3904_SOT23 +VCC_FAN1
1
(31) FAN_SPEED1 2
+VCCP+VCCP 3
1
A C641 ACES_85205-03001 A
1000P_0402_50V7K CONN@
2

@R106
@ R106
R97 R18 2
(31) FAN_PWM 1 2
50_0402_5% 56_0402_5% 0_0603_5%
QUAD@
DUAL@
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 4 of 43
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
(7) H_D#[0..15] CONN@ CONN@
H_D#[32..47] (7)
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
(7) H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 (7) B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
(7) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (7) VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
(7) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (7) VCC[019] VCC[086]
(7) H_D#[16..31] H_D#[48..63] (7) C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100]
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21 R19 1 2 0_0402_5%
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6 R20 1 2 0_0402_5%
C H_D#31 H_D#63 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
(7) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (7) VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
(7) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (7) VCC[039] VCCP[05] + C6
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
(7) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (7) VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R15
V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R21
@R21 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@R22
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6 0814 Change to 220uF
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 PAD C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6 0819 Change to C_D2E
T3 PAD TEST4 VCC[046] VCCP[12]
TEST5 AF1 E5 H_DPRSTP# R23 R24 R25 R26 F15 T21
T4 PAD TEST5 DPRSTP# H_DPRSTP# (7,19,42) VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 PAD TEST6 DPSLP# H_DPSLP# (19) VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 PAD TEST7 DPWR# H_DPWR# (7) VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
(15) CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD (19) VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# DUAL@
1 2 AA7
(15) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (7) VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# R93 0_0402_5% AA9 B26
(15) CPU_BSEL2 BSEL[2] PSI# H_PSI# (42) VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M

0.01U_0402_16V7K
Penryn AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 (42)
AA15 VCC[056] VID[1] AF5 CPU_VID1 (42) 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 (42)
AA18 AF4 C7 C8
VCC[058] VID[3] CPU_VID3 (42)
AA20 VCC[059] VID[4] AE3 CPU_VID4 (42) 2 2
Resistor placed within AB9 VCC[060] VID[5] AF3 CPU_VID5 (42)
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs 0.5" of CPU pin.Trace AC10 VCC[061] VID[6] AE2 CPU_VID6 (42)
AB10 VCC[062]
should be at least 25 AB12 VCC[063]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AB14 AF7 VCCSENSE VCCSENSE (42)
mils away from any other AB15
VCC[064] VCCSENSE
Near pin B26
VCC[065]
toggling signal. AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE (42)
166 0 1 1 COMP[0,2] trace width is VCC[067] VSSSENSE
B 18 mils. COMP[1,3] trace Penryn B

width is 4 mils. .

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCCP
1

R27
1K_0402_1%
<BOM Structure> +VCC_CORE
2

V_CPU_GTLREF
R28 1 2 100_0402_1% VCCSENSE
1

R29 R30 1 2 100_0402_1% VSSSENSE

2K_0402_1%
<BOM Structure>
2

Close to CPU pin AD26

Close to CPU pin
within 500mils.
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 5 of 43
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
C9 C10 C11 C12 C13 C14 C15 C16
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
CONN@ 2 2 2 2 2 2 2 2
JCPU1D
A4 VSS[001] VSS[082] P6
D D
A8 VSS[002] VSS[083] P21
+VCC_CORE
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22 1 1 1 1 1 1 1 1
A23 R25 C17 C18 C19 C20 C21 C22 C23 C24
VSS[007] VSS[088] Place these capacitors on L8
AF2 VSS[008] VSS[089] T1
B6 T4 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[009] VSS[090] 2 2 2 2 2 2 2 2
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
+VCC_CORE
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5 1 1 1 1 1 1 1 1
C8 V22 C25 C26 C27 C28 C29 C30 C31 C32
VSS[018] VSS[099] Place these capacitors on L8
C11 VSS[019] VSS[100] V25
C14 W1 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[020] VSS[101] 2 2 2 2 2 2 2 2
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
+VCC_CORE
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
DUAL@ 1 2 D8 AA2 1 1 1 1 1 1 1 1
R96 0_0402_5% VSS[028] VSS[109] C33 C34 C35 C36 C37 C38 C39 C40
D11 VSS[029] VSS[110] AA5
D13 AA8 1 2 Place these capacitors on L8
VSS[030] VSS[111] R95 DUAL@ 0_0402_5% (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D16 VSS[031] VSS[112] AA11
2 2 2 2 2 2 2 2
D19 VSS[032] VSS[113] AA14
D23 VSS[033] VSS[114] AA16
C C
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25 Mid Frequence Decoupling
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
1 2 F8 VSS[045] VSS[126] AB26
DUAL@ R101 0_0402_5% F11 AC3
VSS[046] VSS[127]
F13 VSS[047] VSS[128] AC6
F16 AC8 DUAL@ 1 2
VSS[048] VSS[129] R94 0_0402_5%
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
+VCC_CORE
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21 330U_D2E_2.5VM_R9
VSS[053] VSS[134]
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8 1 1 1 1 1 1
H6 VSS[058] VSS[139] AD11
H21 AD13 C41 + C42 + C43 + C44 + C93 + C95 +
VSS[059] VSS[140] 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
2 2 2 2 2 2
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 AE4 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
B VSS[065] VSS[146] B
K4 VSS[066] VSS[147] AE8
K23 AE11 330U_D2E_2.5VM_R9
VSS[067] VSS[148]
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16 0814 Change to C_D2E
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26 Place these inside
M2 VSS[073] VSS[154] A2 socket cavity on L8
M5 VSS[074] VSS[155] AF6 (North side
M22 VSS[075] VSS[156] AF8
M25 AF11
Secondary)
VSS[076] VSS[157]
N1 VSS[077] VSS[158] AF13
N4 AF16 +VCCP
VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25 1 1 1 1 1 1
AF25 C45 C46 C47 C48 C49 C50
VSS[163]
Penryn 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 6 of 43
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] (4) U23B

(5) H_D#[0..63] U23A
A14 H_A#3 M36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0

DDR CLK/ CONTROL/COMPENSATION

F2 H_D#_0 H_A#_4 C15 N36 RSVD2 SA_CK_0 AP24 M_CLK_DDR0 (13)

0.01U_0402_25V7K
H_D#1 H_A#5 DDR3 M_CLK_DDR1

2.2U_0603_6.3V4Z
G8 H_D#_1 H_A#_5 F16 R33 RSVD3 SA_CK_1 AT21 M_CLK_DDR1 (13)
H_D#2 F8 H13 H_A#6 0915 ADD PM@ T33 AV24 M_CLK_DDR2 M_CLK_DDR2 (14)
H_D#3 H_D#_2 H_A#_6 H_A#7 +1.5V RSVD4 SB_CK_0 M_CLK_DDR3
E6 H_D#_3 H_A#_7 C18 AH9 RSVD5 SB_CK_1 AU20 M_CLK_DDR3 (14)
H_D#4 G2 M16 H_A#8 AH10
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6 M_CLK_DDR#0
H6 H_D#_5 H_A#_9 J13 1 1 AH12 RSVD7 SA_CK#_0 AR24 M_CLK_DDR#0 (13)

1
C51

C52
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SA_CK#_1 M_CLK_DDR#1 (13)
H_D#7 F6 R16 H_A#11 R31 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SB_CK#_0 M_CLK_DDR#2 (14)
H_D#8 D4 N17 H_A#12 1K_0402_1% PM@ R71 AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 RSVD10 SB_CK#_1 M_CLK_DDR#3 (14)
H_D#9 H3 M13 H_A#13 0_0402_5% AK34
H_D#10 H_D#_9 H_A#_13 H_A#14 CLK_MCH_DREFCLK 1 RSVD11 DDR_CKE0_DIMMA
M9 E17 2 AN35 BC28 DDR_CKE0_DIMMA (13)

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH PM@ R72 RSVD12 SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 AM35 RSVD13 SA_CKE_1 AY28 DDR_CKE1_DIMMA (13)
D H_D#12 H_A#16 0_0402_5% DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 RSVD14 SB_CKE_0 AY36 DDR_CKE2_DIMMB (14)

1
H_D#13 J2 G20 H_A#17 CLK_MCH_DREFCLK# 1 2 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB (14)

RSVD
H_D#14 N12 B19 H_A#18 R32 PM@ R73 B31
H_D#15 H_D#_14 H_A#_18 H_A#19 3.01K_0402_1% 0_0402_5% RSVD15 DDR_CS0_DIMMA#
J6 H_D#_15 H_A#_19 J16 B2 RSVD16 SA_CS#_0 BA17 DDR_CS0_DIMMA# (13)
H_D#16 P2 E20 H_A#20 MCH_SSCDREFCLK 1 2 M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 RSVD17 SA_CS#_1 DDR_CS1_DIMMA# (13)
H_D#17 L2 H16 H_A#21 PM@ R74 AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# (14)

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL 0_0402_5% SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# (14)
H_D#19 N9 L17 H_A#23 MCH_SSCDREFCLK# 1 2 AY21
H_D#_19 H_A#_23 RSVD20

1
0.01U_0402_25V7K
H_D#20 H_A#24 M_ODT0

2.2U_0603_6.3V4Z
L6 H_D#_20 H_A#_24 A17 SA_ODT_0 BD17 M_ODT0 (13)
H_D#21 M5 B17 H_A#25 1 1 R33 AY17 M_ODT1 M_ODT1 (13)
H_D#22 H_D#_21 H_A#_25 H_A#26 1K_0402_1% SA_ODT_1 M_ODT2 +1.5V DDR3
J3 H_D#_22 H_A#_26 L16 SB_ODT_0 BF15 M_ODT2 (14)

C53

C54
H_D#23 N2 C21 H_A#27 <BOM Structure> BG23 AY13 M_ODT3 M_ODT3 (14)
H_D#24 H_D#_23 H_A#_27 H_A#28 RSVD22 SB_ODT_1
R1 J17 BF23

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD23 SMRCOMP R34
N5 H_D#_25 H_A#_29 H20 BH18 RSVD24 SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 N6 B18 H_A#30 BF18 BH21 SMRCOMP# R35 1 2 80.6_0402_1%
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD25 SM_RCOMP#
P13 H_D#_27 H_A#_31 K17
H_D#28 N8 B20 H_A#32 BF28 SMRCOMP_VOH
H_D#29 H_D#_28 H_A#_32 H_A#33 SM_RCOMP_VOH SMRCOMP_VOL
L7 H_D#_29 H_A#_33 F21 SM_RCOMP_VOL BH28
H_D#30 N10 K21 H_A#34
H_D#_30 H_A#_34 DDR3_SM_PWROK (30)
H_D#31 M3 L20 H_A#35 AV42 +V_DDR3_MCH_REF
H_D#32 H_D#_31 H_A#_35 +3VS SM_VREF DDR3_SM_PWROK
Y3 H_D#_32 SM_PWROK AR36
H_D#33 AD14 H12 H_ADS# R38 BF17 SM_REXT R37 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# (4) SM_REXT
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 1 2 BC36 SM_DRAMRST#
H_D#_34 H_ADSTB#_0 H_ADSTB#0 (4) SM_DRAMRST# SM_DRAMRST# (13,14)
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 (4)
H_D#36 Y12 A9 H_BNR# 10K_0402_5% B38 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# (4) DPLL_REF_CLK CLK_MCH_DREFCLK (15)
H_D#37 Y14 F11 H_BPRI# A38 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# (4) DPLL_REF_CLK# CLK_MCH_DREFCLK# (15)
H_D#38 Y7 G12 H_BR0# R39 E41 MCH_SSCDREFCLK
HOST
H_D#_38 H_BREQ# H_BR0# (4) DPLL_REF_SSCLK MCH_SSCDREFCLK (15)
H_D#39 W2 E9 H_DEFER# PM_EXTTS#0_1 1 2 F41 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# (4) DPLL_REF_SSCLK# MCH_SSCDREFCLK# (15)
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# (4)
H_D#41 CLK_MCH_BCLK 10K_0402_5% CLK_MCH_3GPLL

CLK
Y9 H_D#_41 HPLL_CLK AH7 CLK_MCH_BCLK (15) PEG_CLK F43 CLK_MCH_3GPLL (15)
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# (15) PEG_CLK# CLK_MCH_3GPLL# (15)
H_D#43 AA9 J11 H_DPWR# R40
C H_D#_43 H_DPWR# H_DPWR# (5) C
H_D#44 AA11 F9 H_DRDY# CLKREQ#_7 1 2
H_D#_44 H_DRDY# H_DRDY# (4)
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# (4)
H_D#46 AD10 E12 H_HITM# 10K_0402_5% AE41 DMI_TXN0
H_D#_46 H_HITM# H_HITM# (4) DMI_RXN_0 DMI_TXN0 (20)
H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# (4) DMI_RXN_1 DMI_TXN1 (20)
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# (4) DMI_RXN_2 DMI_TXN2 (20)
H_D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 (20)
H_D#50 AA2
H_D#51 H_D#_50 DMI_TXP0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_TXP0 (20)
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_TXP1
H_D#_52 (15) MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 (20)
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 (5) (15) MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 (20)
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 (5) (15) MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 (20)
H_D#55 AE14 Y13 H_DINV#2 P20
H_D#_55 H_DINV#_2 H_DINV#2 (5) CFG_3
H_D#56 AF3 Y1 H_DINV#3 P24 AE35 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 (5) CFG_4 DMI_TXN_0 DMI_RXN0 (20)
H_D#57 AC1 T75 PAD CFG5 C25 AE43 DMI_RXN1
H_D#_57 CFG_5 DMI_TXN_1 DMI_RXN1 (20)
H_D#58 AE3 L10 H_DSTBN#0 T76 PAD CFG6 N24 AE46 DMI_RXN2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 (5) CFG_6 DMI_TXN_2 DMI_RXN2 (20)
H_D#59 AC3 M7 H_DSTBN#1 T77 PAD CFG7 M24 AH42 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 (5) CFG_7 DMI_TXN_3 DMI_RXN3 (20)
H_D#60 AE11 AA5 H_DSTBN#2 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 (5) CFG_8

DMI
CFG
H_D#61 AE8 AE6 H_DSTBN#3 T79 PAD CFG9 C23 AD35 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 (5) CFG_9 DMI_TXP_0 DMI_RXP0 (20)
H_D#62 AG2 T80 PAD CFG10 C24 AE44 DMI_RXP1
H_D#_62 CFG_10 DMI_TXP_1 DMI_RXP1 (20)
H_D#63 AD6 L9 H_DSTBP#0 N21 AF46 DMI_RXP2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 (5) CFG_11 DMI_TXP_2 DMI_RXP2 (20)
M8 H_DSTBP#1 T82 PAD CFG12 P21 AH43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 (5) CFG_12 DMI_TXP_3 DMI_RXP3 (20)
AA6 H_DSTBP#2 T83 PAD CFG13 T21
H_DSTBP#_2 H_DSTBP#2 (5) CFG_13
H_SWNG C5 AE5 H_DSTBP#3 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 (5) CFG_14
H_RCOMP E3 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 B15 H_REQ#0 (4) T86 PAD L21 CFG_16
K13 H_REQ#1 H21
H_REQ#_1 H_REQ#1 (4) CFG_17
H_REQ#2 VGATE GMCH_PWROK

GRAPHICS VID
H_REQ#_2 F13 H_REQ#2 (4) P29 CFG_18 (20,42) VGATE 1 2
B13 H_REQ#3 T89 PAD CFG19 R28 R55 @ 0_0402_5%
H_REQ#_3 H_REQ#3 (4) CFG_19
(4) H_RESET# H_RESET# C12 B14 H_REQ#4 T90 PAD CFG20 T28 B33 ICH_PWROK 1 2
H_CPURST# H_REQ#_4 H_REQ#4 (4) CFG_20 GFX_VID_0 (20) ICH_PWROK
(5) H_CPUSLP# H_CPUSLP# E11 B32 R66 0_0402_5%
H_CPUSLP# H_RS#0 GFX_VID_1
H_RS#_0 B6 H_RS#0 (4) GFX_VID_2 G33
F12 H_RS#1 H_RS#1 (4) F33
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_3 B
H_RS#_2 C8 H_RS#2 (4) (20) PM_BMBUSY# R29 PM_SYNC# GFX_VID_4 E33
H_VREF A11 H_DPRSTP# B7
H_AVREF (5,19,42) H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#0_1 P32
(13,14) PM_EXTTS#0_1 PM_EXT_TS#_1

PM
CANTIGA_1p0 GMCH_PWROK AT40 C34
PLT_RST# PLT_RST#_NB PWROK GFX_VR_EN +VCCP
(18,20,22,23) PLT_RST# 1 2 AT11 RSTIN#
(4,19) H_THERMTRIP# 1 2 R520 100_0402_5% THERMTRIP# T20
R41 0_0402_5% DPRSLPVR THERMTRIP#
(20,42) DPRSLPVR R32 DPRSLPVR CL_CLK0 (20)

1
Layout Note: CL_DATA0 (20)
AH37 CL_CLK0 R42
H_RCOMP / H_VREF / H_SWNG +1.5V DDR3 CL_CLK

0.1U_0402_16V4Z
Layout Note: AH36 CL_DATA0 1K_0402_1%
CL_DATA ICH_PWROK
trace width and spacing is 10/20 V_DDR_MCH_REF 1 @ BG48 NC_1 CL_PWROK AN36 1 2 R51
C55 BF48 AJ35 CL_RST# 0_0402_5%
CL_RST# (20)

2
NC_2 CL_RST#
1

ME
trace width and BD48 AH34 CL_VREF
+VCCP R44 NC_3 CL_VREF
spacing is 20/20. BC48 NC_4

1
+VCCP 1K_0402_1% 2
BH47 NC_5 1
BG47 C56
NC_6 511_0402_1%
1K_0402_1%

221_0603_1%

BE47 N28 0.1U_0402_16V4Z

PAD T36
2

NC_7 DDPC_CTRLCLK
1

+V_DDR3_MCH_REF BH46 M28 R43

NC_8 DDPC_CTRLDATA PAD T37 2
R45 R46 BF46 G36 SDVO_SCLK (17)

2
NC_9 SDVO_CTRLCLK
1

NC
0.1U_0402_16V4Z

BG45 E36 SDVO_SDAT

NC_10 SDVO_CTRLDATA SDVO_SDAT (17)
1 R47 BH44 K36 CLKREQ#_7
NC_11 CLKREQ# CLKREQ#_7 (15)
C57 1K_0402_1% BH43 H36 MCH_ICH_SYNC#
MCH_ICH_SYNC# (20)
2

H_VREF H_RCOMP H_SWNG NC_12 ICH_SYNC#

BH6

MISC
NC_13
BH5
change logic
2

2 NC_14
24.9_0402_1%

0.1U_0402_16V4Z

<BOM Structure> BG4 B12 MCH_TSATN#

NC_15 TSATN#
1

1
100_0402_1%
0.1U_0402_16V4Z

1 1 BH3
define by EC NC_16
2K_0402_1%

R52 C58 R53 R54 C59 BF3 33_0402_5%

NC_17 GM@ R102
BH2 NC_18
BG2 B28 HDA_BITCLK_MCH
2 2 +3VS NC_19 HDA_BCLK HDA_BITCLK_MCH (19)
BE2 B30 HDA_RST_MCH#
HDA_RST_MCH# (19)
2

NC_20 HDA_RST# HDA_SDIN2_MCH

BG1 NC_21 HDA_SDI B29 1 2 HDA_SDIN2 (19)
A HDA_SDOUT_MCH A
BF1 NC_22 HDA_SDO C29 HDA_SDOUT_MCH (19)
1

+VCCP

HDA
normal:low BD1 A28 HDA_SYNC_MCH HDA_SYNC_MCH (19)
R63 NC_23 HDA_SYNC
over temp:high BC1 NC_24
within 100 mils from NB Near B3 pin 1K_0402_5% F1 NC_25
1

A47 NC_26
R64
2

54.9_0402_1% MCH_TSATN_EC# (31) CANTIGA_1p0

R68 Security Classification Compal Secret Data Compal Electronics, Inc.
1

C
2

MCH_TSATN# 1 2 2 Q5 2007/09/29 2007/09/29 Title

B Issued Date Deciphered Date
MMBT3904_SOT23-3
330_0402_5% E
<BOM Structure>
SCHEMATIC,MB A3806
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 7 of 43
5 4 3 2 1
 5 4 3 2 1

D D

(13) DDR_A_D[0..63] (14) DDR_B_D[0..63]

U23D U23E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 (13) SB_DQ_0 SB_BS_0 DDR_B_BS0 (14)
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS1 (13) SB_DQ_1 SB_BS_1 DDR_B_BS1 (14)
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 (13) SB_DQ_2 SB_BS_2 DDR_B_BS2 (14)
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# (13) AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# (13) SB_DQ_5 SB_RAS# DDR_B_RAS# (14)
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# (13) DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# (14)
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# (14)
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] (13) SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] (14)
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 SA_DQ_19 DDR_A_DQS[0..7] (13) BF43 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] (14)
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 MEMORY BC37 DDR_A_DQS3 DDR_B_D23 BF41 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BG41
DDR_A_D24 AY37 AW12 DDR_A_DQS4 DDR_B_D24 BG38 BG37 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 DDR_A_DQS#[0..7] (13) BG35 SB_DQ_27 SB_DQS_6 AU1
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] (14) C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SYSTEM

SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] (13) SB_DQ_35 SB_DQS#_6

DDR_A_D36 DDR_B_D36 DDR_B_DQS#7

SYSTEM
AU13 SA_DQ_36 BH12 SB_DQ_36 SB_DQS#_7 AN5
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] (14)
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 SA_DQ_38 SA_MA_1 BC24 BF8 SB_DQ_38 SB_MA_0 AV17
DDR_A_D39 BC12 BG24 DDR_A_MA2 DDR_B_D39 BG7 BA25 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 SA_DQ_40 SA_MA_3 BH24 BC5 SB_DQ_40 SB_MA_2 BC25
DDR_A_D41 BA9 BG25 DDR_A_MA4 DDR_B_D41 BC6 AU25 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 SA_DQ_42 SA_MA_5 BA24 AY3 SB_DQ_42 SB_MA_4 AW25
DDR_A_D43 AV9 BD24 DDR_A_MA6 DDR_B_D43 AY1 BB28 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 SA_DQ_44 SA_MA_7 BG27 BF6 SB_DQ_44 SB_MA_6 AU28
DDR_A_D45 BD9 BF25 DDR_A_MA8 DDR_B_D45 BF5 AW28 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 SA_DQ_46 SA_MA_9 AW24 BA1 SB_DQ_46 SB_MA_8 AT33
DDR_A_D47 BA6 BC21 DDR_A_MA10 DDR_B_D47 BD3 BD33 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
DDR

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16

DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 8 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS DPST_PWM U23C

(17) DPST_PWM

PEGCOMP trace width Strap Pin Table

0_0402_5% R56 +VCC_PEG and spacing is 20/25 mils.
L32 L_BKLT_CTRL 10mils 000 = FSB 1066MHz

2
GM@ GM@ (24,31) ENABLT GM@ R91 G32 T37 1 2 CFG[2:0] FSB Freq select
R570 R571 R57 1 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 2 10K_0402_5% M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%
2.2K_0402_5% 2.2K_0402_5% GM@
R58 1 2 10K_0402_5% M33
011 = FSB 667MHz
DDC2_CLK GM@ L_CTRL_DATA PCIE_GTX_MRX_N0 C211
(17) DDC2_CLK K33 H44 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N0 Others = Reserved
1

1 L_DDC_CLK PEG_RX#_0
DDC2_CLK DDC2_DATA J33 J46 PCIE_GTX_MRX_N1 C221 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N1
(17) DDC2_DATA L_DDC_DATA PEG_RX#_1
DDC2_DATA L44 PCIE_GTX_MRX_N2 C225 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N2
PEG_RX#_2 PCIE_GTX_MRX_N3 C355 1 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3
PEG_RX#_3 L40 2 CFG[4:3] Reserved
(17) ENAVDD ENAVDD M29 N41 PCIE_GTX_MRX_N4 C361 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4
R59 L_VDD_EN PEG_RX#_4
1 2 2.37K_0402_1% C44 LVDS_IBG PEG_RX#_5 P48 PCIE_GTX_MRX_N5 C354 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5 0 = DMI x 2
D For Crestline:2.4kohm GM@ B43 N44 PCIE_GTX_MRX_N6 C357 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N6 CFG5 (DMI select) D
LVDS_VBG PEG_RX#_6 1 = DMI x 4
For Calero: 1.5Kohm
For Cantiga: 2.37Kohm
R92
GM@ 0_0402_5%
E37
E38
LVDS_VREFH
LVDS_VREFL
PEG_RX#_7
PEG_RX#_8
T43
U43
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_N8
C350 1 2 PM@ 0.1U_0402_16V7K
C359 1 2 PM@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8 *
0 = The iTPM Host Interface is enable

LVDS
(17) LVDS_A_C- LVDS_A_C- C41 Y43 PCIE_GTX_MRX_N9 C360 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9 CFG6
LVDS_A_C+ LVDSA_CLK# PEG_RX#_9 PCIE_GTX_MRX_N10 C358
C40 Y48 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10 1 = The iTPM Host Interface is disable
(17)
(17)
(17)
LVDS_A_C+
LVDS_B_C-
LVDS_B_C+
LVDS_B_C-
LVDS_B_C+
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11 Y36
AA43
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_N12
C352 1 2 PM@ 0.1U_0402_16V7K
C362 1 2 PM@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12 0 =(TLS)chiper suite with no confidentiality
*
LVDSB_CLK PEG_RX#_12 PCIE_GTX_MRX_N13 C351 1
PEG_RX#_13 AD37 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N13 CFG7 (Intel Management
2 1 ENABLT LVDS_A_0- H47 AC47 PCIE_GTX_MRX_N14 C353 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N14 1 =(TLS)chiper suite with confidentiality
R227 100K_0402_5%
(17) LVDS_A_0-
(17) LVDS_A_1-
(17) LVDS_A_2-
LVDS_A_1-
LVDS_A_2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15 AD39 PCIE_GTX_MRX_N15 C356 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15 Engine Crypto strap)
*
LVDSA_DATA#_2 PCIE_GTX_MRX_P0 C228
A40 LVDSA_DATA#_3 PEG_RX_0 H43 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0

GRAPHICS
J44 PCIE_GTX_MRX_P1 C226 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1 CFG8 Reserved
LVDS_A_0+ PEG_RX_1 PCIE_GTX_MRX_P2 C227
(17) LVDS_A_0+ H48 LVDSA_DATA_0 PEG_RX_2 L43 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P2
(17) LVDS_A_1+ LVDS_A_1+ D45 L41 PCIE_GTX_MRX_P3 C378 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
LVDS_A_2+ LVDSA_DATA_1 PEG_RX_3 PCIE_GTX_MRX_P4 C367
(17) LVDS_A_2+ F40 LVDSA_DATA_2 PEG_RX_4 N40 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4 CFG9 0 = Reverse Lane,15->0, 14->1
B40 P47 PCIE_GTX_MRX_P5 C365 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
LVDSA_DATA_3 PEG_RX_5 PCIE_GTX_MRX_P6 C373
PEG_RX_6 N43 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
LVDS_B_0- A41 T42 PCIE_GTX_MRX_P7 C379 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P7
(17) LVDS_B_0-
(17) LVDS_B_1-
(17) LVDS_B_2-
LVDS_B_1-
LVDS_B_2-
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_P9 C364 1 2 PM@
C376
0.1U_0402_16V7K
1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9 0 = Enable
*
LVDSB_DATA#_2 PEG_RX_9 PCIE_GTX_MRX_P10 C372
J37 LVDSB_DATA#_3 PEG_RX_10 W47 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10 CFG10 (PCIE Lookback enable)
Y37 PCIE_GTX_MRX_P11 C377 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11 1 = Disable
(17) LVDS_B_0+
(17) LVDS_B_1+
LVDS_B_0+
LVDS_B_1+
B42
G38
LVDSB_DATA_0
PEG_RX_11
PEG_RX_12 AA42
AD36
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_P13 C368 1 2 PM@
C371
0.1U_0402_16V7K
1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13 CFG11 Reserved
*
LVDS_B_2+ LVDSB_DATA_1 PEG_RX_13 PCIE_GTX_MRX_P14 C366
(17) LVDS_B_2+ F37 LVDSB_DATA_2 PEG_RX_14 AC48 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14

PCI-EXPRESS
K37 AD40 PCIE_GTX_MRX_P15 C363 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15 CFG[13:12] (XOR/ALLZ) 00 = Reserved
LVDSB_DATA_3 PEG_RX_15
01 = XOR Mode Enabled
J41 PCIE_MTX_GRX_N0 C210 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 10 = All Z Mode Enabled
PEG_TX#_0 PCIE_MTX_GRX_N1 C219 1
M46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 11 = Normal Operation(Default)
R880 2 GM@
R881 2 GM@
1 75_0402_1%GMCH_TV_COMPS
1 75_0402_1%GMCH_TV_LUMA
F25
H25
TVA_DAC
PEG_TX#_1
PEG_TX#_2 M47
M40
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3 C229 1 2 PM@ 0.1U_0402_16V7K
C222 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3 CFG[15:14] Reserved
*
R882 2 GM@ TVB_DAC PEG_TX#_3
C
1 75_0402_1%GMCH_TV_CRMA K25 TVC_DAC PEG_TX#_4 M42 PCIE_MTX_GRX_N4 C231 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 C

TV
R48 PCIE_MTX_GRX_N5 C235 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PEG_TX#_5 PCIE_MTX_GRX_N6 C237 1 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
H24 TV_RTN PEG_TX#_6 N38 2 CFG16 (FSB Dynamic ODT) 0 = Disabled
T40 PCIE_MTX_GRX_N7 C242 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
PEG_TX#_7 PCIE_MTX_GRX_N8 C267 1
U37 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 1 = Enabled
R87 GM@ 0_0402_5%
TV_DCONSEL_0 C31
PEG_TX#_8
PEG_TX#_9 U40
Y40
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
C308 1 2 PM@ 0.1U_0402_16V7K
C265 1
PCIE_MTX_C_GRX_N9
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
*
R88 GM@ 0_0402_5%
TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C261 1
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11 CFG[18:17] Reserved
AA37 PCIE_MTX_GRX_N12 C309 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
M_BLUE PEG_TX#_12 PCIE_MTX_GRX_N13 C252 1
(16) M_BLUE PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
M_GREEN AD43 PCIE_MTX_GRX_N14 C260 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 CFG19 (DMI Lane Reversal) 0 = Normal Operation
(16) M_GREEN
(16) M_RED M_RED
R552
PEG_TX#_14
PEG_TX#_15 AC46 PCIE_MTX_GRX_N15 C264 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
(Lane number in Order)
*
1 GM@ 2 E28 CRT_BLUE PEG_TX_0 J42 PCIE_MTX_GRX_P0 C208 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
R553 150_0402_1% L46 PCIE_MTX_GRX_P1 C218 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1 1 = Reverse Lane
PEG_TX_1
1 GM@ 2 G28 CRT_GREEN PEG_TX_2 M48 PCIE_MTX_GRX_P2 C220 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
R554 150_0402_1% M39 PCIE_MTX_GRX_P3 C223 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
1 GM@ 2 J28 CRT_RED
PEG_TX_3
PEG_TX_4 M43 PCIE_MTX_GRX_P4 C230 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
150_0402_1%
G29 CRT_IRTN
VGA PEG_TX_5
PEG_TX_6
R47
N37
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
C232 1 2 PM@ 0.1U_0402_16V7K
C236 1
PCIE_MTX_C_GRX_P5
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 1 = PCIE/SDVO are operating simu.
T39 PCIE_MTX_GRX_P7 C238 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
3VDDCCL PEG_TX_7 PCIE_MTX_GRX_P8 C307 1
(16) 3VDDCCL H32 CRT_DDC_CLK PEG_TX_8 U36 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
3VDDCDA J32 U39 PCIE_MTX_GRX_P9 C250 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
(16) 3VDDCDA CRT_DDC_DATA PEG_TX_9
(16) CRT_HSYNC CRT_HSYNC J29 Y39 PCIE_MTX_GRX_P10 C263 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
CRT_HSYNC PEG_TX_10 PCIE_MTX_GRX_P11 C266 1
E29 CRT_TVO_IREF PEG_TX_11 Y46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
(16) CRT_VSYNC CRT_VSYNC L29 AA36 PCIE_MTX_GRX_P12 C254 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
CRT_VSYNC PEG_TX_12 PCIE_MTX_GRX_P13 C262 1
PEG_TX_13 AA39 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
AD42 PCIE_MTX_GRX_P14 C255 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PEG_TX_14 PCIE_MTX_GRX_P15 C251 1
PEG_TX_15 AD46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
R89 R90
2

0_0402_5% 0_0402_5%
PM@ PM@ R81 CANTIGA_1p0
1.02K_0402_1%
B GM@ B
1

GM@ 0.1U_0402_16V7K
GM@ 0.1U_0402_16V7K
GM@ 0.1U_0402_16V7K
GM@ 0.1U_0402_16V7K

PCIE_MTX_GRX_N0 C224 1 2 TMDS_B_DATA2#

TMDS_B_DATA2# (17)
PCIE_MTX_GRX_N1 C212 1 2 TMDS_B_DATA1#
PCIE_MTX_C_GRX_N[0..15] TMDS_B_DATA1# (17)
PCIE_MTX_GRX_N2 C247 1 2 TMDS_B_DATA0#
PCIE_MTX_C_GRX_N[0..15] (24) TMDS_B_DATA0# (17)
PCIE_MTX_GRX_N3 C240 1 2 TMDS_B_CLK#
PCIE_MTX_C_GRX_P[0..15] TMDS_B_CLK# (17)
PCIE_MTX_C_GRX_P[0..15] (24)
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15] (24)
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_P[0..15] (24)
GM@ 0.1U_0402_16V7K
GM@ 0.1U_0402_16V7K
GM@ 0.1U_0402_16V7K
GM@ 0.1U_0402_16V7K
PCIE_MTX_GRX_P0 C239 1 2 TMDS_B_DATA2
TMDS_B_DATA2 (17)
PCIE_MTX_GRX_P1 C241 1 2 TMDS_B_DATA1
TMDS_B_DATA1 (17)
PCIE_MTX_GRX_P2 C246 1 2 TMDS_B_DATA0
L41 TMDS_B_DATA0 (17)
PCIE_MTX_GRX_P3 C234 1 2 TMDS_B_CLK
TMDS_B_CLK (17)
R147
PCIE_GTX_MRX_P3 1 2 DVI_HPDT#
DVI_HPDT# (17)
0_0402_5%

GM@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 9 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS_DAC_BG +3VS
L47
1 2 +1.05VS_DPLLA
+VCCP +VCCP

0.022U_0402_16V7K
BLM18PG181SN1D_0603
+VCCP
4.7U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
GM@ GM@ +V1.05VS_AXF
R528 2

GM@
0_0402_5%

1 1 1 1 U23H 1 2 R99
PM@

C60

C61

C62
220U_D2_4VM_R15 L48 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z
852mA 0_1210_5% 0_0603_5%

220U_D2_4VM_R15
VTT_1 U13 1

R529 2
GM@

GM@

GM@

4.7U_0805_10V4Z

C65

C66

1U_0603_10V4Z
0_0402_5%
73mA T13 1 1 1
2 2 2 2 VTT_2

PM@
+
C655

B27 U12 1 C63 1 1

1

VCCA_CRT_DAC_1 VTT_3

C67

C68

C69
A26 T12 C64 + GM@
+3VS_DAC_CRT VCCA_CRT_DAC_2 VTT_4
U11 GM@ GM@
2.68mA VTT_5 2 2 2
T11

1
VTT_6 2 2 2 2
A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT_7
B25 VSSA_DAC_BG VTT_8 T10
D U9 <BOM Structure> D
+3VS_DAC_CRT +3VS VTT_9
VTT_10 T9
L49 U8
64.8mA VTT_11
1 2 +1.05VS_DPLLA F47 VCCA_DPLLA VTT_12 T8
0.022U_0402_16V7K

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
BLM18PG181SN1D_0603 U7

VTT
VTT_13 +1.5V_SM_CK
4.7U_0805_10V4Z

0.1U_0402_16V4Z

GM@ L48 64.8mA T7 1 1 1 DDR3 L50 +1.5V

+1.05VS_DPLLB VCCA_DPLLB VTT_14
R527 2

+1.05VS_DPLLB +VCCP
C871 GM@

C73

C74
0_0402_5%

1 1 1 1 U6 MBK1608121YZF_0603
VTT_15
PM@

0.1U_0402_16V4Z
C70

C71

C72
C606 AD1 24mA T6 1 2

PLL
+1.05VS_HPLL VCCA_HPLL VTT_16

10U_0805_10V4Z
+ GM@ U5 1 2
VTT_17 2 2 2
GM@

GM@

0.1U_0402_16V4Z
220U_D2_4VM_R15 +1.05VS_MPLL AE1 139.2mA T5 L51 1 1
VCCA_MPLL VTT_18

2
2 2 2

C78

C79

10U_0805_10V4Z

C77
V3 0_1210_5%
1

VTT_19

R530 2
2

0_0402_5%
13.2mA U3 1 1 GM@ @ R883
VTT_20

PM@

C75
+1.8V_TXLVDS J48 VCCA_LVDS VTT_21 V2 1_0402_1%
2 2
1 U2

A LVDS
C80 GM@ VTT_22 GM@ GM@
J47 T2

1
VSSA_LVDS VTT_23 2 2

10U_0805_10V4Z
V1

1
@ R104 1000P_0402_50V7K 414uA VTT_24
VTT_25 U1 1
2

C76
+3VS 1 2
0_0603_5% AD48
+1.5VS_PEG_BG VCCA_PEG_BG
R105 2 <BOM Structure>
1 2

A PEG
+1.5VS +1.05VS_HPLL +VCCP +1.5VS_TVDAC +1.5VS
0_0603_5% 50mA
1 +1.05VS_PEGPLL AA48 L52 R107
VCCA_PEG_PLL
<BOM Structure>

C81 1 2 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
MBK2012121YZF_2P 0_0805_5%
0.1U_0402_16V4Z DDR3:747.5mA AR20
2 VCCA_SM_1

0.1U_0402_16V4Z

10U_0805_10V4Z
AP20 VCCA_SM_2 1 1 1 1

C82

C83
AN20 VCCA_SM_3
POWER

C84

C85
AR17 VCCA_SM_4
AP17 VCCA_SM_5
+VCCP AN17 2 2 2 2
+1.05VS_A_SM VCCA_SM_6
AT16 VCCA_SM_7
220U_D2_4VM_R15 R108 AR16

A SM
VCCA_SM_8
C
1 2 AP16 VCCA_SM_9 C
1 0_0805_5%
1 1 1
C86 + C800 C88 C89
+VCC_PEG +VCCP
J1
4.7U_0805_10V4Z DDR3:37.95mA JUMP_43X79
2 2 2 2 321.35mA +1.05VS_MPLL +VCCP @
22U_0805_6.3V6M <BOM Structure>
1U_0603_10V4Z AP28 L53 1
VCCA_SM_CK_1 1 2 2
AN28 VCCA_SM_CK_2 VCC_AXF_1 B22 +V1.05VS_AXF 1 2

10U_0805_10V4Z
AP25 B21 MBK2012121YZF_2P 220U_D2_4VM_R15 1

AXF
VCCA_SM_CK_3 VCC_AXF_2

1
R111 +1.05VS_A_SM_CK

4.7U_0805_10V4Z
AN25 VCCA_SM_CK_4 VCC_AXF_3 A21 1 1

C91
1 2 AN24 R884 C90 + C801
VCCA_SM_CK_5 1
1U_0603_10V4Z

0.1U_0402_16V4Z

0_0603_5% AM28 124mA C92 0.5_0603_1%

VCCA_SM_CK_NCTF_1
AM26
A CK
VCCA_SM_CK_NCTF_2 0.1U_0402_16V4Z 2 2 2
1 1 1 1 AM25

2
VCCA_SM_CK_NCTF_3 2
C96

C97

C94 C802 AL25 BF21 +1.5V_SM_CK 1

VCCA_SM_CK_NCTF_4 VCC_SM_CK_1
AM24 BH20

SM CK
1U_0603_10V4Z VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 C803
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
2 2 2 2 DDR3
AM23 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 BF20 22U_0805_6.3V6M
22U_0805_6.3V6M 2
AL23 VCCA_SM_CK_NCTF_8 DDR3:149.5mA
TVA 24.15mA
+1.05VS_PEGPLL +VCCP +1.05VS_DMI +VCC_PEG
TVB 39.48mA VCC_TX_LVDS K47 +1.8V_TXLVDS
B24 TVX 24.15mA L1 R112
VCCA_TV_DAC_1 +3VS_HV
+3VS_TVDAC A24 VCCA_TV_DAC_2 VCC_HV_1 C35 1 2 1 2
TV

105.3mA B35 BLM18PG121SN1D_0603 0_0603_5%

VCC_HV_2

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
A35
HV

R525 VCC_HV_3
1 1

0.1U_0402_16V4Z

C98

C99
+1.5VS 1 2 VCC_HDA A32 50mA 1
VCC_HDA

C100
HDA

0_0402_5% V48 +VCC_PEG 1

VCC_PEG_1
0.1U_0402_16V4Z

C101
GM@ 1732mA U48
VCC_PEG_2 2 2
GM@C475

0814 Add R,C V47

PEG

VCC_PEG_3
R533 2

2
0_0402_5%

1 VCC_PEG_4 U47
2
PM@

D TV/CRT

+1.5VS_TVDAC M25 58.67mA U46

VCCD_TVDAC VCC_PEG_5
B +1.5VS_QDAC L28 48.363mA B
2 VCCD_QDAC
AH48 +1.05VS_DMI
1

157.2mA VCC_DMI_1
+1.05VS_HPLL AF1 VCCD_HPLL VCC_DMI_2 AF48
AH47
DMI

50mA VCC_DMI_3
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI_4 AG47
+VCCP_D
456mA
M38 VCCD_LVDS_1
LVDS

+1.8V_LVDS L37 A8 D3 R113 R114

VCCD_LVDS_2 VTTLF1
VTTLF2 L1 +VCCP 2 1 1 2 1 2 +3VS_HV
VTTLF

60.31mA AB2 10_0402_5% 0_0402_5%

VTTLF3 CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS
1 1 1
C102

C103

C104

CANTIGA_1p0

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
40 mils
R115 GM@ R116
1 2 +1.8V 1 2 +1.8V

10U_0805_10V4Z

1000P_0402_50V7K
0_0603_5% 0_0603_5%

10U_0805_10V4Z
+1.5VS_QDAC 1 1

R534 2

R531 2
+1.5VS

C105

C106

1U_0603_10V4Z

C108
0_0402_5%

0_0402_5%
+3VS_TVDAC 1 1 GM@

PM@

PM@
+3VS

C107
L54 GM@ R120
2 GM@ 2 GM@ GM@
1 2 1 2
2 2
0.022U_0402_16V7K

0.022U_0402_16V7K

BLM18PG181SN1D_0603 100_0603_1% GM@

1

1
A A
0.1U_0402_16V4Z

0.1U_0402_16V4Z
R536 2

C110

C111

C112

C113
0_0402_5%

1 1 1 1
PM@

GM@
GM@
2 2 2 2
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 10 of 43
5 4 3 2 1
 5 4 3 2 1

U23G +VGFX_CORE

DDR3 AP33 W28

DDR3:4140mA VCC_SM_1 VCC_AXG_NCTF_1
AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28
+1.5V BH32 VCC_SM_3 VCC_AXG_NCTF_3 W26
U23F BG32 V26
+VCCP VCC_SM_4 VCC_AXG_NCTF_4

0.01U_0402_16V7K
BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 VCC_SM_6 VCC_AXG_NCTF_6 V25
C117 1 1 2 BC32 W24
VCC_SM_7 VCC_AXG_NCTF_7

C118

C119

C120
D
AG34 + BB32 V24 D
VCC_1 VCC_SM_8 VCC_AXG_NCTF_8
AC34 VCC_2 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AB34 330U_D2E_2.5VM_R15 AY32 V23
VCC_3 2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_10
AA34 VCC_4 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
Y34 VCC_5 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
V34 VCC_6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
U34 VCC_7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AM33 0317 change value AR32 V21
VCC_8 VCC_SM_15 VCC_AXG_NCTF_15

POWER
AK33 VCC_9 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
AJ33 J3 AN32 AM20
VCC_10 VCC_SM_17 VCC_AXG_NCTF_17
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z JUMP_43X79
AG33 VCC_11 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
10U_0805_10V4Z

220U_D2_4VM_R15 1 AF33 @ BG31 W20

VCC_12 VCC_SM_19 VCC_AXG_NCTF_19
1 1 1 1 1 1 2 2 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20
+VGFX_CORE
C122

C123

C124

C121 + C125
AE33 VCC_13 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19
+VCCP

VCC CORE
AC33 VCC_14 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
AA33 GM@ BG29 AK19
2 2 2 2 2 VCC_15 R109 VCC_SM_23 VCC_AXG_NCTF_23
Y33 VCC_16 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
W33 1 2 0.1U_0402_16V4Z 4.7U_0603_6.3V6M BD29 AH19
VCC_17 VCC_SM_25 VCC_AXG_NCTF_25

VCC SM
V33 0_0805_5% BC29 AG19
VCC_18 VCC_SM_26 VCC_AXG_NCTF_26

R537 2
0_0402_5%
U33 VCC_19 1 1 1 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19

PM@
AH28 @ C114 C115 C116 BA29 AE19
VCC_20 VCC_SM_28 VCC_AXG_NCTF_28
AF28 VCC_21 1 1 2 2 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AC28 GM@ GM@ GM@ AW29 AA19
VCC_22 J2 JUMP_43X79 2 2 2 VCC_SM_30 VCC_AXG_NCTF_30
AA28 AV29 Y19

1
VCC_23 VCC_SM_31 VCC_AXG_NCTF_31
AJ26 VCC_24 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AG26 0.22U_0402_10V4Z AT29 V19
VCC_25 VCC_SM_33 VCC_AXG_NCTF_33
AE26 VCC_26 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AC26 VCC_27 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17
AH25 VCC_28 VCC_AXG_NCTF_36 AK17
AG25 VCC_SM_BA36 BA36 AH17
VCC_29 VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_37
AF25 VCC_30 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AG24 VCC_SM_BD16 BD16 AF17
C VCC_31 +VCCP VCC_SM_38/NC VCC_AXG_NCTF_39 C
AJ23 VCC_32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
AH23 VCC_SM_AW16 AW16 AC17
VCC_33 POWER VCC_SM_40/NC VCC_AXG_NCTF_41
AF23 VCC_34 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
AM32 VCC_SM_AT13 AT13 Y17
VCC_NCTF_1 VCC_SM_42/NC VCC_AXG_NCTF_43
T32 VCC_35 VCC_NCTF_2 AL32 VCC_AXG_NCTF_44 W17
AK32 6326.84mA V17

VCC GFX NCTF

VCC_NCTF_3 VCC_AXG_NCTF_45
VCC_NCTF_4 AJ32 VCC_AXG_NCTF_46 AM16
VCC_NCTF_5 AH32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
VCC_NCTF_6 AG32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
AE32 +VGFX_CORE AB25 AJ16
VCC_NCTF_7 VCC_AXG_3 VCC_AXG_NCTF_49
VCC_NCTF_8 AC32 AA25 VCC_AXG_4 VCC_AXG_NCTF_50 AH16
VCC_NCTF_9 AA32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
Y32 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 AF16
VCC_NCTF_10 VCC_AXG_6 VCC_AXG_NCTF_52
VCC_NCTF_11 W32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_12 U32 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
VCC_NCTF_13 AM30 1 1 1 1 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
AL30 C126 + C128 C129 C130 AC23 AA16
VCC_NCTF_14 VCC_AXG_10 VCC_AXG_NCTF_56
VCC_NCTF_15 AK30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
AH30 1U_0603_10V4Z C127 AA23 W16
VCC_NCTF_16 2 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_58
VCC_NCTF_17 AG30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
AE30 10U_0805_10V4Z AE21
VCC_NCTF_19 330U_D2E_2.5VM_R15 VCC_AXG_15
VCC_NCTF_20 AC30 AC21 VCC_AXG_16
VCC_NCTF_21 AB30 AA21 VCC_AXG_17
VCC_NCTF_22 AA30 Y21 VCC_AXG_18
VCC_NCTF_23 Y30 AH20 VCC_AXG_19
VCC_NCTF_24 W30 AF20 VCC_AXG_20
VCC NCTF

VCC_NCTF_25 V30 AE20 VCC_AXG_21

VCC_NCTF_26 U30 AC20 VCC_AXG_22
VCC_NCTF_27 AL29 AB20 VCC_AXG_23
VCC_NCTF_28 AK29 AA20 VCC_AXG_24
VCC_NCTF_29 AJ29 T17 VCC_AXG_25
B B
VCC_NCTF_30 AH29 T16 VCC_AXG_26
VCC_NCTF_31 AG29 AM15 VCC_AXG_27
VCC_NCTF_32 AE29 AL15 VCC_AXG_28
VCC_NCTF_33 AC29 AE15 VCC_AXG_29
VCC_NCTF_34 AA29 AJ15 VCC_AXG_30
VCC_NCTF_35 Y29 AH15 VCC_AXG_31
VCC_NCTF_36 W29 AG15 VCC_AXG_32
VCC_NCTF_37 V29 AF15 VCC_AXG_33
VCC_NCTF_38 AL28 AB15 VCC_AXG_34
VCC_NCTF_39 AK28 AA15 VCC_AXG_35

VCC GFX
VCC_NCTF_40 AL26 Y15 VCC_AXG_36
VCC_NCTF_41 AK26 V15 VCC_AXG_37
VCC_NCTF_42 AK25 U15 VCC_AXG_38
VCC_NCTF_43 AK24 AN14 VCC_AXG_39
VCC_NCTF_44 AK23 AM14 VCC_AXG_40
U14 VCC_AXG_41 VCC_SM_LF1 AV44 VCCSM_LF1

VCC SM LF
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
VCC_SM_LF6 AM10 VCCSM_LF6
CANTIGA_1p0
VCC_SM_LF7 BB13 VCCSM_LF7

C131 0.1U_0402_16V4Z

C132 0.1U_0402_16V4Z

C133

C134

C135

C136

C137
1 1 1 1 1 1 1
VCC_SM_BA36
VCC_SM_BB24 AJ14
T42 PAD VCC_AXG_SENSE
VCC_SM_BD16 AH14
T43 PAD VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
VCC_SM_AW16
VCC_SM_AT13

1 1 1 1 1
C875 C876 C877 C878 C879
@ @ @ @ @
A 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K A
2 2 2 2 2
0.1U_0402_16V7K 0.1U_0402_16V7K CANTIGA_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 11 of 43
5 4 3 2 1
 5 4 3 2 1

U23J
U23I BG21 AH8
VSS_199 VSS_297
L12 VSS_200 VSS_298 Y8
AU48 VSS_1 VSS_100 AM36 AW21 VSS_201 VSS_299 L8
AR48 VSS_2 VSS_101 AE36 AU21 VSS_202 VSS_300 E8
AL48 VSS_3 VSS_102 P36 AP21 VSS_203 VSS_301 B8
BB47 VSS_4 VSS_103 L36 AN21 VSS_204 VSS_302 AY7
AW47 VSS_5 VSS_104 J36 AH21 VSS_205 VSS_303 AU7
AN47 VSS_6 VSS_105 F36 AF21 VSS_206 VSS_304 AN7
AJ47 VSS_7 VSS_106 B36 AB21 VSS_207 VSS_305 AJ7
AF47 VSS_8 VSS_107 AH35 R21 VSS_208 VSS_306 AE7
D D
AD47 VSS_9 VSS_108 AA35 M21 VSS_209 VSS_307 AA7
AB47 VSS_10 VSS_109 Y35 J21 VSS_210 VSS_308 N7
Y47 VSS_11 VSS_110 U35 G21 VSS_211 VSS_309 J7
T47 VSS_12 VSS_111 T35 BC20 VSS_212 VSS_310 BG6
N47 VSS_13 VSS_112 BF34 BA20 VSS_213 VSS_311 BD6
L47 VSS_14 VSS_113 AM34 AW20 VSS_214 VSS_312 AV6
G47 VSS_15 VSS_114 AJ34 AT20 VSS_215 VSS_313 AT6
BD46 VSS_16 VSS_115 AF34 AJ20 VSS_216 VSS_314 AM6
BA46 VSS_17 VSS_116 AE34 AG20 VSS_217 VSS_315 M6
AY46 VSS_18 VSS_117 W34 Y20 VSS_218 VSS_316 C6
AV46 VSS_19 VSS_118 B34 N20 VSS_219 VSS_317 BA5
AR46 VSS_20 VSS_119 A34 K20 VSS_220 VSS_318 AH5
AM46 VSS_21 VSS_120 BG33 F20 VSS_221 VSS_319 AD5
V46 VSS_22 VSS_121 BC33 C20 VSS_222 VSS_320 Y5
R46 VSS_23 VSS_122 BA33 A20 VSS_223 VSS_321 L5
P46 VSS_24 VSS_123 AV33 BG19 VSS_224 VSS_322 J5
H46 VSS_25 VSS_124 AR33 A18 VSS_225 VSS_323 H5
F46 VSS_26 VSS_125 AL33 BG17 VSS_226 VSS_324 F5
BF44 VSS_27 VSS_126 AH33 BC17 VSS_227 VSS_325 BE4
AH44 VSS_28 VSS_127 AB33 AW17 VSS_228
AD44 P33 AT17 BC3
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
U44 VSS_32 VSS_131 N32 H17 VSS_232 VSS_330 R3
T44 K32 C17 P3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32 BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
F3
BA2
BC43 VSS_36 VSS_135 A31 VSS_334 AW2
AV43 VSS_37 VSS_136 AN29 AU16 VSS_237 VSS_335 AU2
AU43 VSS_38 VSS_137 T29 AN16 VSS_238 VSS_336 AR2
AM43 VSS_39 VSS_138 N29 N16 VSS_239 VSS_337 AP2
J43 VSS_40 VSS_139 K29 K16 VSS_240 VSS_338 AJ2
C C
C43 VSS_41 VSS_140 H29 G16 VSS_241 VSS_339 AH2
BG42 VSS_42 VSS_141 F29 E16 VSS_242 VSS_340 AF2
AY42 VSS_43 VSS_142 A29 BG15 VSS_243 VSS_341 AE2
AT42 VSS_44 VSS_143 BG28 AC15 VSS_244 VSS_342 AD2
AN42 VSS_45 VSS_144 BD28 W15 VSS_245 VSS_343 AC2
AJ42 VSS_46 VSS_145 BA28 A15 VSS_246 VSS_344 Y2
AE42 VSS_47 VSS_146 AV28 BG14 VSS_247 VSS_345 M2
N42 VSS_48 VSS_147 AT28 AA14 VSS_248 VSS_346 K2
L42 VSS_49 VSS_148 AR28 C14 VSS_249 VSS_347 AM1
BD41 VSS_50 VSS_149 AJ28 BG13 VSS_250 VSS_348 AA1
AU41 VSS_51 VSS_150 AG28 BC13 VSS_251 VSS_349 P1
AM41 VSS_52 VSS_151 AE28 BA13 VSS_252 VSS_350 H1
AH41 VSS_53 VSS_152 AB28
AD41 VSS_54 VSS_153 Y28 VSS_351 U24
AA41 VSS_55 VSS_154 P28 AN13 VSS_255 VSS_352 U28
Y41 VSS_56 VSS_155 K28 AJ13 VSS_256 VSS_353 U25
U41 VSS_57 VSS_156 H28 AE13 VSS_257 VSS_354 U29
T41 VSS_58 VSS_157 F28 N13 VSS_258
M41 VSS_59 VSS_158 C28 L13 VSS_259
G41 VSS_60 VSS_159 BF26 G13 VSS_260 VSS_NCTF_1 AF32
B41 VSS_61 VSS_160 AH26 E13 VSS_261 VSS_NCTF_2 AB32
BG40 VSS_62 VSS_161 AF26 BF12 VSS_262 VSS_NCTF_3 V32
BB40 VSS_63 VSS_162 AB26 AV12 VSS_263 VSS_NCTF_4 AJ30
AV40 VSS_64 VSS_163 AA26 AT12 VSS_264 VSS_NCTF_5 AM29
AN40 VSS_65 VSS_164 C26 AM12 VSS_265 VSS_NCTF_6 AF29
H40 B26 AA12 AB29

VSS NCTF
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 VSS_67 VSS_166 BH25 J12 VSS_267 VSS_NCTF_8 U26
AT39 VSS_68 VSS_167 BD25 A12 VSS_268 VSS_NCTF_9 U23
AM39 VSS_69 VSS_168 BB25 BD11 VSS_269 VSS_NCTF_10 AL20
AJ39 VSS_70 VSS_169 AV25 BB11 VSS_270 VSS_NCTF_11 V20
AE39 VSS_71 VSS_170 AR25 AY11 VSS_271 VSS_NCTF_12 AC19
N39 VSS_72 VSS_171 AJ25 AN11 VSS_272 VSS_NCTF_13 AL17
B B
L39 VSS_73 VSS_172 AC25 AH11 VSS_273 VSS_NCTF_14 AJ17
B39 VSS_74 VSS_173 Y25 VSS_NCTF_15 AA17
BH38 VSS_75 VSS_174 N25 Y11 VSS_275 VSS_NCTF_16 U17
BC38 VSS_76 VSS_175 L25 N11 VSS_276
BA38 VSS_77 VSS_176 J25 G11 VSS_277
AU38 G25 C11 BH48

VSS SCB
VSS_78 VSS_177 VSS_278 VSS_SCB_1
AH38 VSS_79 VSS_178 E25 BG10 VSS_279 VSS_SCB_2 BH1
AD38 VSS_80 VSS_179 BF24 AV10 VSS_280 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AT10 VSS_281 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AJ10 VSS_282 VSS_SCB_5 A3
U38 VSS_83 VSS_182 AT24 AE10 VSS_283
T38 VSS_84 VSS_183 AJ24 AA10 VSS_284 NC_26 E1
J38 VSS_85 VSS_184 AH24 M10 VSS_285 NC_27 D2
F38 VSS_86 VSS_185 AF24 BF9 VSS_286 NC_28 C3
C38 VSS_87 VSS_186 AB24 BC9 VSS_287 NC_29 B4
BF37 VSS_88 VSS_187 R24 AN9 VSS_288 NC_30 A5
BB37 VSS_89 VSS_188 L24 AM9 VSS_289 NC_31 A6
AW37 VSS_90 VSS_189 K24 AD9 VSS_290 NC_32 A43
AT37 VSS_91 VSS_190 J24 G9 VSS_291 NC_33 A44
AN37 G24 B9 B45

NC
VSS_92 VSS_191 VSS_292 NC_34
AJ37 VSS_93 VSS_192 F24 BH8 VSS_293 NC_35 C46
H37 VSS_94 VSS_193 E24 BB8 VSS_294 NC_36 D47
C37 VSS_95 VSS_194 BH23 AV8 VSS_295 NC_37 B47
BG36 VSS_96 VSS_195 AG23 AT8 VSS_296 NC_38 A46
BD36 VSS_97 VSS_196 Y23 NC_39 F48
AK15 VSS_98 VSS_197 B23 NC_40 E48
AU36 VSS_99 VSS_198 A23 NC_41 C48
VSS_199 AJ6 NC_42 B48

CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 12 of 43
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

+V_DDR3_DIMM_REF
(8) DDR_A_DQS#[0..7]

(8) DDR_A_D[0..63] JDIMM2

1 VREF_DQ VSS1 2
+1.5V DDR_A_D4
(8) DDR_A_DM[0..7] 3 VSS2 DQ4 4
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
(8) DDR_A_DQS[0..7] 7 DQ1 VSS3 8

1
9 10 DDR_A_DQS#0
R540 DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
(8) DDR_A_MA[0..14] 11 DM0 DQS0 12
1K_0402_1% 13 14
+V_DDR3_DIMM_REF DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7

2
D +V_DDR3_DIMM_REF DQ3 DQ7 D
(14) +V_DDR3_DIMM_REF 19 VSS7 VSS8 20

0.1U_0402_16V4Z
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
2.2U_0805_16V4Z
<BOM Structure> DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13

C209
1 1 R541 25 26
DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1
27 DQS#1 DM1 28

C642
1K_0402_1% DDR_A_DQS1 29 30 SM_DRAMRST#
DQS1 RESET# SM_DRAMRST# (7,14)
31 32

2
2 2 DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 DQ10 DQ14 34
<BOM Structure> DDR_A_D11 35 36 DDR_A_D15
<BOM Structure> DQ11 DQ15
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
+RTCVCC 49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
<BOM Structure> 51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
1 59 DQ25 VSS21 60
C968 61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
0.1U_0402_16V4Z 65 66
2 ADD FOR 1111 DDR_A_D26 VSS23 VSS24 DDR_A_D30
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
71 VSS25 VSS26 72

Layout Note: DDR_CKE0_DIMMA DDR_CKE1_DIMMA

(7) DDR_CKE0_DIMMA 73 CKE0 CKE1 74 DDR_CKE1_DIMMA (7)
Place near JP4 75 76
C VDD1 VDD2 C
77 NC1 A15 78
DDR_A_BS2 79 80 DDR_A_MA14
(8) DDR_A_BS2 BA2 A14
Layout Note: Place these 4 Caps near Command 81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
and Control signals of DIMMA DDR_A_MA9 85
A12/BC# A11
86 DDR_A_MA7
A9 A7
87 VDD5 VDD6 88
+1.5V DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
A3 A2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
1 1 1 1 1 1 1 1 1 1 99 VDD9 VDD10 100
C146

C147

C148

C149
C784

C785

C786

C787

C788

C789

+ C140 M_CLK_DDR0 101 102 M_CLK_DDR1

(7) M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 (7)
330U_D2E_2.5VM_R7 M_CLK_DDR#0 103 104 M_CLK_DDR#1
(7) M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 (7)
105 VDD11 VDD12 106
2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA10 DDR_A_BS1
107 A10/AP BA1 108 DDR_A_BS1 (8)
DDR_A_BS0 109 110 DDR_A_RAS#
(8) DDR_A_BS0 BA0 RAS# DDR_A_RAS# (8)
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
(8) DDR_A_WE# WE# S0# DDR_CS0_DIMMA# (7)
DDR_A_CAS# 115 116 M_ODT0
(8) DDR_A_CAS# CAS# ODT0 M_ODT0 (7)
117 VDD15 VDD16 118
DDR_A_MA13 M_ODT1 +V_DDR3_DIMM_REF
119 A13 ODT1 120 M_ODT1 (7)
DDR_CS1_DIMMA# 121 122
(7) DDR_CS1_DIMMA# S1# NC2 R542
123 VDD17 VDD18 124
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure> 125 126 DDR_VREF_CA_DIMMA 1 2
NCTEST VREF_CA
127 VSS27 VSS28 128
Layout Note: DDR_A_D32 129 130 DDR_A_D36 0_0402_5%
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132
Place near JP4.203 & JP4.204 133 134
VSS29 VSS30

0.1U_0402_16V4Z
DDR_A_DQS#4 135 136 DDR_A_DM4
DQS#4 DM4

2.2U_0603_6.3V4Z
DDR_A_DQS4 137 138 1 1
DQS4 VSS31 DDR_A_D38
139 VSS32 DQ38 140

C790

C791
B DDR_A_D34 DDR_A_D39 B
141 DQ34 DQ39 142
+0.75V DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44 2 2
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

151 152 DDR_A_DQS#5

DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
10U_0805_6.3V6M

2 2 2 2 1 155 VSS37 VSS38 156

C804

DDR_A_D42 157 158 DDR_A_D46

DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
1 1 1 1 2
C159

C160

C161

C162

DDR_A_D48 163 164 DDR_A_D52

DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R124 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0_1 (7,14)
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBDATA (14,15)
201 202 CLK_SMBCLK
SA1 SCL CLK_SMBCLK (14,15)
2.2U_0603_6.3V4Z

1 1 203 VTT1 VTT2 204 +0.75V

1
10K_0402_5%

A A
0.1U_0402_16V4Z

C164
C163 205 206
G1 G2
R123

2 2
<BOM Structure><BOM Structure>
+0.75V DDR3 SO-DIMM A
REVERSE
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
<BOM
AND TRADE SECRET Structure>
<BOM Structure>
INFORMATION.
Size Document Number
THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 13 of 43
5 4 3 2 1
 5 4 3 2 1

(8) DDR_B_DQS#[0..7] +1.5V +1.5V

(8) DDR_B_D[0..63]
+V_DDR3_DIMM_REF

(8) DDR_B_DM[0..7] JDIMM1

(8) DDR_B_DQS[0..7] (13) +V_DDR3_DIMM_REF 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
(8) DDR_B_MA[0..14] 5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
9 VSS4 DQS#0 10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DQ2 DQ6

C165

C166
D DDR_B_D3 DDR_B_D7 D
17 DQ3 DQ7 18
19 VSS7 VSS8 20
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# (7,13)
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
Layout Note: 47 DQS2 VSS17 48
DDR_B_D22
49 VSS18 DQ22 50
Place near JP5 DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
Layout Note: Place these 4 Caps near Command 55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 58
and Control signals of DIMMA DDR_B_D25 59
DQ24 DQ29
60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
+1.5V DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
10U_0603_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 71 VSS25 VSS26 72
1 1 1 1 1 1 1 1 1 1
C172

C173

C174

C175
C792

C793

C794

C795

C796

C797

+ C643
330U_D2E_2.5VM_R7
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
C 2 2 2 2 2 2 2 2 2 2 2 (7) DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB (7) C
75 VDD1 VDD2 76
77 NC1 A15 78
DDR_B_BS2 79 80 DDR_B_MA14
(8) DDR_B_BS2 BA2 A14
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure> 93 VDD7 VDD8 94
Layout Note: DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
Place near JP5.203 & JP5.204 99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
(7) M_CLK_DDR2 101 CK0 CK1 102 M_CLK_DDR3 (7)
M_CLK_DDR#2 103 104 M_CLK_DDR#3
(7) M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 (7)
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
+0.75V A10/AP BA1 DDR_B_BS1 (8)
DDR_B_BS0 109 110 DDR_B_RAS#
(8) DDR_B_BS0 BA0 RAS# DDR_B_RAS# (8)
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
(8) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (7)
DDR_B_CAS# 115 116 M_ODT2
(8) DDR_B_CAS# CAS# ODT0 M_ODT2 (7)
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

117 VDD15 VDD16 118

DDR_B_MA13 M_ODT3 +V_DDR3_DIMM_REF
119 A13 ODT1 120 M_ODT3 (7)
10U_0805_6.3V6M

2 2 2 2 1 DDR_CS3_DIMMB# 121 122

(7) DDR_CS3_DIMMB# S1# NC2
C805

123 124 R543

VDD17 VDD18 DDR_VREF_CA_DIMMB
125 NCTEST VREF_CA 126 1 2 0_0402_5%
127 VSS27 VSS28 128
1 1 1 1 2
C185

C186

C187

C188

DDR_B_D32 129 130 DDR_B_D36

DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS29 VSS30 134

0.1U_0402_16V4Z
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS#4 DM4

2.2U_0603_6.3V4Z
DDR_B_DQS4 137 138 1 1
DQS4 VSS31

C798
B DDR_B_D38 B
139 VSS32 DQ38 140

C799
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39
143 DQ35 VSS33 144
DDR_B_D44 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
1 R127 2 195
DQ59
VSS51
DQ63
VSS52 196 same with intel DDR3 CRB connection
10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0_1 (7,13)
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBDATA (13,15)
201 202 CLK_SMBCLK
A SA1 SCL CLK_SMBCLK (13,15) A
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

1 2 203 204

C189
1 1
R126
10K_0402_5%
VTT1 VTT2 +0.75V
DDR3 SO-DIMM B
205 206
2 2
C190 G1
+0.75V
G2
REVERSE
<BOM Structure>

Security Classification
<BOM Structure>
Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
<BOM Structure>
<BOM
DEPARTMENT Structure>
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 14 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505
Routing the trace at least 10mil L55
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 1 2
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz CLK_XTAL_OUT MBK2012121YZF_2P 1
C191
1
C192
1
C193
1
C194
1
C195
1
C196
1
C197
CLK_XTAL_IN
0 0 0 266 100 33.3 14.318 96.0 48.0 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure> 2 <BOM Structure>
<BOM Structure>

0 0 1 133 100 33.3 14.318 96.0 48.0 14.31818MHZ_16P

Y1
+VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 2 1
Place close to U3
D L56 D
0 1 1 166 100 33.3 14.318 96.0 48.0 2 2
C205 C206 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
18P_0402_50V8J 18P_0402_50V8J MBK2012121YZF_2P
1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 C198 C199 C200 C201 C202 C203 C204
1 1
<BOM Structure> <BOM Structure>
2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0 <BOM Structure>
<BOM Structure> <BOM Structure>
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 0 400 100 33.3 14.318 96.0 48.0

1 1 1 Reserved +3VS_CK505 +1.05VS_CK505

R131
CLK_MCH_3GPLL (7)
1 2 +VCCP CLK_MCH_3GPLL# (7) 3G_PLL
R155 1 2 475_0402_1% R_CLKREQ#_7
(7) CLKREQ#_7
@ 56_0402_5% R875 1 2 +3VS
(7) CLK_MCH_BCLK#
NB R_CLKREQ#_6 R154 1 2 10K_0402_5%
(7) CLK_MCH_BCLK MCARD_CLKREQ# (22)
475_0402_1%
(4) CLK_CPU_BCLK# CLK_PCIE_MCARD1 (22)
R132 CPU MiniCard
(4) CLK_CPU_BCLK CLK_PCIE_MCARD1# (22)
FSA 1 2 1 2 +3VS_CK505
MCH_CLKSEL0 (7)
2.2K_0402_5% R133
R134 1K_0402_5%

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
(5) CPU_BSEL0 1 2
<BOM Structure>
0_0402_5% <BOM Structure> U3
+1.05VS_CK505
1

+3VS_CK505

SRC_8/CPU_ITP
VDD_CPU

CPU_0#
VSS_CPU

CPU_1#
VDD_CPU_IO

VDD_SRC_IO
CPU_0

CPU_1

CLKREQ_7#

SRC_7#
VSS_SRC

VDD_SRC
SRC_8#/CPU_ITP#

SRC_7

CLKREQ_6#
SRC_6
SRC_6#
@
R137
1K_0402_5%
C C
2

R138 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI# MCARD_CLKREQ2# 1 R886 2 +3VS

(20) CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# (20)
FSB 2 53 H_STP_CPU# 10K_0402_5%
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# (20)
3 VSS_REF VDD_SRC_IO 52
+VCCP CLK_XTAL_OUT 4 51 CLK_PCIE_VGA#
XTAL_OUT SRC_10# CLK_PCIE_VGA# (24)
CLK_XTAL_IN 5 50 CLK_PCIE_VGA VGA_CLKREQ# 1 R889 2 +3VS
XTAL_IN SRC_10 CLK_PCIE_VGA (24)
6 VDD_REF CLKREQ_10# 49 1 R159 2 VGA_CLKREQ#
VGA_CLKREQ# (24)
10K_0402_5%
2

@ R158 1 2 33_0402_1% FSC 7 48 475_0402_1%

(20) CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_PCIE_MCARD2 (22)
R150 T98 PAD 8 47 LAN_CLKREQ# 1 R890 2 +3VS
REF_1 SRC_11# CLK_PCIE_MCARD2# (22)
1K_0402_5% (13,14) CLK_SMBDATA CLK_SMBDATA 9 46 1 R156 2 MCARD_CLKREQ2# (22) 10K_0402_5%
CLK_SMBCLK SDA CLKREQ_11# 475_0402_1%
(13,14) CLK_SMBCLK 10 SCL SRC_9# 45 CLK_PCIE_LAN# (23)
11 44 CLK_PCIE_LAN (23) GLAN
1

FSB NC SRC_9
1 2 MCH_CLKSEL1 (7) 0905 Connect PCI_CLK 12 VDD_PCI CLKREQ_9# 43 1R160 2 LAN_CLKREQ# (23)
R157 13 42 475_0402_1%
R162 1K_0402_5% PCI2_TME PCI_1 VSS_SRC
1 2 R142 1 2 33_0402_1% 27_SEL
14
15
PCI_2 CLKREQ_4# 41
40
DEL NEW Card
(5) CPU_BSEL1 (31) CLK_PCI_EC PCI_3 SRC_4#
0_0402_5% R873 PCI_CLK4 16 39
PCI_4/SEL_LCDCL SRC_4
1

USB_1/CLKREQ_A#
PCI_CLK 1 2 ITP_EN 17 38

LCDCLK#/27M_SS
(18) PCI_CLK PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
@ 33_0402_1% 18 37 R_CLKREQ#_C 1 2 475_0402_1%
VSS_PCI CLKREQ_3# CLKREQ#_C (20)

SRC_0/DOT_96
R165 R149

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A
0_0402_5%

VDD_PLL3

VSS_PLL3

VSS_SRC
2008/10/07
2

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
Add 48M for Card reader
+VCCP
SA000020H10 SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R371 1 2 12_0402_5% +3VS_CK505
1

@ (28) CLK_SD_48M
R177
1K_0402_5% CLK_PCIE_SATA# (19)
R372 1 2 12_0402_5% FSA SATA
(20) CLK_48M_ICH CLK_PCIE_SATA (19)
B T112 PAD B
R182
CLK_PCIE_ICH# (20)
2

FSC 1 2 1 2 +1.05VS_CK505 ICH

MCH_CLKSEL2 (7) CLK_PCIE_ICH (20)
10K_0402_5% R183 +1.05VS_CK505
R187 1K_0402_5%
(7) CLK_MCH_DREFCLK
(5) CPU_BSEL2 1 2 NB (UMA) (7) CLK_MCH_DREFCLK# MCH_SSCDREFCLK# (7)
0_0402_5% NB_SSC (UMA)
MCH_SSCDREFCLK (7)
1

@
R188
0_0402_5%
0 = SRC8/SRC8#
ITP_EN
2

1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
PCI_CLK3 +3VS
+3VS 1 = Enable SRC0 & 27MHz(DIS) +3VS
1

+3VS
R208 0820 R192 @ +3VS R189 R190
10K_0402_5%
1

@ 2.2K_0402_5% 2.2K_0402_5%
R192
2

10K_0402_5%
PCI2_TME 5
2

ITP_EN (20,22) ICH_SMBDATA 3 4 CLK_SMBDATA

1

PCI_CLK4
2

R207 SB, MINI PCI Q3B

1

@ 10K_0402_5%
1

R193 6 1 2N7002DW T/R7_SOT363-6 CLK_SMBCLK

A 10K_0402_5% (20,22) ICH_SMBCLK A
R194
2

10K_0402_5% 2N7002DW T/R7_SOT363-6

Q3A
2

for ICS Overclocking setting

0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 15 of 43
5 4 3 2 1
 A B C D E

Place close to JP6 BLUE

GREEN
RED
DHSYNC
DVSYNC

1
@ D15
@D15 @ D14 @ D5
@D5 @ D6 @ D7

DAN217_SC59

DAN217_SC59

DAN217_SC59

DAN217_SC59

DAN217_SC59
+CRTVDD

3
1 1

NOTE: L : A-->B1
CRT Connector
H: A-->B2
+5VS +RCRT_VCC +CRTVDD

D4 F1
2 1 1 2 W=40mils
1
CH491D_SC59 1.1A_6VDC_FUSE C213
0.1U_0402_16V4Z
2
JCRT1
6
11
CRT_R 1 2 RED 1
L24 FCM2012CF-800T06_2P 7
12
CRT_G 1 2 GREEN 2
L26 FCM2012CF-800T06_2P 8
+CRTVDD
13
CRT_B 1 2 BLUE 3
L28 FCM2012CF-800T06_2P 9

1
14 G 16

2
2 R560R561 C661 2
4 G 17
R562 1 1 1 1 1 1 10 R555
C657C658C659 22P_0402_50V8J C660 C662 15 100K_0402_5%
150_0402_1% 5

2
CRT_VSYNC R61 1 GM@ 2 30.1_0402_1% CRT_VSYNC_R 22P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
(9) CRT_VSYNC

1
150_0402_1% 2 2 2 2 2 2 SUYIN_070546FR015S233ZR
CRT_DET# (20)
CRT_HSYNC R69 1 GM@ 2 30.1_0402_1% CRT_HSYNC_R 150_0402_1% <BOM Structure>
(9) CRT_HSYNC +3VS
22P_0402_50V8J
M_BLUE R328 1 GM@ 2 0_0402_5% CRT_B +CRTVDD +CRTVDD +3VS
(9) M_BLUE
10P_0402_50V8J GM@ GM@
M_GREEN R330 1 GM@ 2 0_0402_5% CRT_G
(9) M_GREEN

1
1
1 2 R349
M_RED R332 1 GM@ 0_0402_5% CRT_R R197 R198 R199 R200 PM@ 0_0402_5% VGA_DDC_DATA (24)
(9) M_RED 2

2
+5VS +5VS 2.2K_0402_5%2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

2
2
C214 C215 D_DDCDATA 6 1 3VDDCDA_R 2 1 R350
0.1U_0402_16V4Z 0.1U_0402_16V4Z GM@ 0_0402_5% 3VDDCDA (9)
1 2 1 2 2N7002DW T/R7_SOT363-6

5
Q4A
2 1 R352
R872 D_DDCCLK 3 4 3VDDCCL_R 2 1 3VDDCCL (9)
5
1

10K_0402_5% U4 GM@ 0_0402_5%

SN74AHCT1G125GW_SOT353-5 R196
P
OE#

CRT_HSYNC_R HSYNC_G_A Q4B

2 A Y 4 1 2 0_0603_5% DHSYNC
2N7002DW T/R7_SOT363-6 1 2 R356 VGA_DDC_CLK (24)
G

5
1

PM@ 0_0402_5%
R202
P
OE#
3

CRT_VSYNC_R 2 4 VSYNC_G_A 1 2 0_0603_5% DVSYNC

A Y
G

U5 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C216 C217
3
1

3 3
R204 R205 5P_0402_50V8C 5P_0402_50V8C
51K_0402_5% 51K_0402_5% 2 2
2

R65 1 2 PM@ 0_0402_5% CRT_VSYNC_R

(24) VGA_CRT_VSYNC
R67 1 2 PM@ 0_0402_5% CRT_HSYNC_R
(24) VGA_CRT_HSYNC
R333 1 2 PM@ 0_0402_5% CRT_B
(24) VGA_CRT_B
R334 1 2 PM@ 0_0402_5% CRT_G
(24) VGA_CRT_G
R335 1 2 PM@ 0_0402_5% CRT_R
(24) VGA_CRT_R

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 16 of 43
A B C D E
 5 4 3 2 1

+3VS +LCDVDD +INVPWR_B+ +LCDVDD +LCDVDD +3VS

+3VS 2N7002_SOT23-3
L29 1 2 Q30
B+

1
U54 0.1U_0402_16V4Z FBMA-L11-201209-221LMA30T_0805

10U_0805_10V4Z
W=40mils R563

S
1 1 1 1 1 1 3

P
NC
GMCH_INV_PWM 4 2 C663 C664 C943 C667 C665 L30 1 2 300_0603_5% AO3413_SOT23
Y A DPST_PWM (9) +5VALW

680P_0402_50V7k
C868 FBMA-L11-201209-221LMA30T_0805

G
1800P_0402_50V7K 0.1U_0402_16V4Z 1 1 1 1 1

G
2

2
NC7SZ14P5X_NL_SC70-5 GM@ 2 2 2 2 2 C666 C669 C670

2
390P_0402_50V7K C668 4.7U_0603_6.3V6K

1+LCDVDD_R
R968 68P_0402_50V8J R564 0.1U_0402_16V4Z 4.7U_0805_10V4Z
GMCH_INV_PWM 1 2 2 2 2 2
2 0_0402_5% VGA_PNL_PWM (24) <BOM Structure>
@ 100K_0402_5%

1
42 41 DAC_BRIG
GND GMD DAC_BRIG (31)
+INVPWR_B+ 40 39 Q31 D
40 39 GMCH_INV_PWM 1
D 38 38 37 37 2INV_PWM INV_PWM (31) 2 2 1 D
+3VS 36 35 DISPLAYOFF# R1004 0_0402_5% EC@ 2N7002_SOT23 G R565 4.7K_0402_5%
DDC2_CLK_R 36 35
34 33 +LCDVDD S 2 C938

3
DDC2_DATA_R 34 33 220P_0402_50V7K
32 32 31 31
30 29 W=60mils DAC_BRIG 1 2 0.047U_0402_16V7K
LVDS_B_0-_R 30 29 C672 0_0402_5%
28 28 27 27

1
LVDS_B_0+_R LVDS_A_0-_R INV_PWM D 1
26 26 25 25 1 2 220P_0402_50V7K GM@
24 23 LVDS_A_0+_R C673 1 R283 2 2 Q54
24 23 (9) ENAVDD

1
LVDS_B_1+_R 22 21 DISPLAYOFF# 1 2 220P_0402_50V7K G 2N7002_SOT23
LVDS_B_1-_R 22 21 LVDS_A_1-_R C674
20 19 (24) ENVDD 1 2 S

3
20 19 LVDS_A_1+_R PM@ R282 R885
18 18 17 17
LVDS_B_2+_R 16 15 0_0402_5% 100K_0402_5%
LVDS_B_2-_R 16 15 LVDS_A_2+_R
14 13

2
14 13 LVDS_A_2-_R
12 12 11 11
LVDS_B_C-_R 10 9
R567 LVDS_B_C+_R 10 9 LVDS_A_C-_R
8 8 7 7
0_0402_5% 6 5 LVDS_A_C+_R
@ USB20_CMOS_N3 4 6 5 LVDS_A_0-_R RP2 2 VGA_TXOUT0- LVDS_A_0-_R RP3 1 LVDS_A_0-
1 2 4 3 3 3 VGA_TXOUT0- (24) 4 LVDS_A_0- (9)
L57 USB20_CMOS_P3 2 1 +3VS LVDS_A_0+_R 1 4 VGA_TXOUT0+ LVDS_A_0+_R 2 3 LVDS_A_0+
2 1 VGA_TXOUT0+ (24) LVDS_A_0+ (9)
2 2 PM@ 0_0404_4P2R_5% GM@ 0_0404_4P2R_5%
(20) USB20_N3 1 1 JLVDS ACES_87242-4001-09 LVDS_A_1-_R RP4 2 VGA_TXOUT1- LVDS_A_1-_R RP5 1 LVDS_A_1-
3 VGA_TXOUT1- (24) 4 LVDS_A_1- (9)
LVDS_A_1+_R 1 4 VGA_TXOUT1+ LVDS_A_1+_R 2 3 LVDS_A_1+
VGA_TXOUT1+ (24) LVDS_A_1+ (9)
3 4 +3VS PM@ 0_0404_4P2R_5% GM@ 0_0404_4P2R_5%
(20) USB20_P3 3 4 LVDS_A_2-_R 1 4 VGA_TXOUT2- LVDS_A_2-_R 2 3 LVDS_A_2-
VGA_TXOUT2- (24) LVDS_A_2- (9)
WCM2012F2S-900T04_0805 LVDS_A_2+_R 2 3 VGA_TXOUT2+ LVDS_A_2+_R 1 4 LVDS_A_2+
VGA_TXOUT2+ (24) LVDS_A_2+ (9)
2

1 2 RP6 PM@ 0_0404_4P2R_5% RP7 GM@ 0_0404_4P2R_5%

@ R568 R970 R569 @ LVDS_A_C-_R RP8 2 3 VGA_TXCLK- LVDS_A_C-_R RP9 1 4 LVDS_A_C-
VGA_TXCLK- (24) LVDS_A_C- (9)
0_0402_5% 1 2 0_0402_5% LVDS_A_C+_R 1 4 VGA_TXCLK+ LVDS_A_C+_R 2 3 LVDS_A_C+
VGA_TXCLK+ (24) LVDS_A_C+ (9)
4.7K_0402_5% PM@ 0_0404_4P2R_5% GM@ 0_0404_4P2R_5%
LVDS_B_0-_R 1 4 VGA_TZOUT0- LVDS_B_0-_R 2 3 LVDS_B_0-
VGA_TZOUT0- (24) LVDS_B_0- (9)
1

D43 @ LVDS_B_0+_R 2 3 VGA_TZOUT0+ LVDS_B_0+_R 1 4 LVDS_B_0+

VGA_TZOUT0+ (24) LVDS_B_0+ (9)
(31) BKOFF# BKOFF# 1 2 DISPLAYOFF# RP10 PM@ 0_0404_4P2R_5% RP11 GM@ 0_0404_4P2R_5%
LVDS_B_1-_R RP12
2 3 VGA_TZOUT1- LVDS_B_1-_R RP13
1 4 LVDS_B_1-
VGA_TZOUT1- (24) LVDS_B_1- (9)
CH751H-40PT_SOD323-2 LVDS_B_1+_R 1 4 VGA_TZOUT1+ LVDS_B_1+_R 2 3 LVDS_B_1+
VGA_TZOUT1+ (24) LVDS_B_1+ (9)
PM@ 0_0404_4P2R_5% GM@ 0_0404_4P2R_5%
C C
DDC2_CLK_R RP1 2 3GM@ DDC2_CLK DDC2_CLK (9) LVDS_B_2-_R RP14
2 3 VGA_TZOUT2-
VGA_TZOUT2- (24)
LVDS_B_2-_R RP15
1 4 LVDS_B_2-
LVDS_B_2- (9)
DDC2_DATA_R 1 4 DDC2_DATA LVDS_B_2+_R 1 4 VGA_TZOUT2+ LVDS_B_2+_R 2 3 LVDS_B_2+
DDC2_DATA (9) VGA_TZOUT2+ (24) LVDS_B_2+ (9)
0_0404_4P2R_5% PM@ 0_0404_4P2R_5% GM@ 0_0404_4P2R_5%
LVDS_B_C-_R 1 4 VGA_TZCLK- LVDS_B_C-_R 2 3 LVDS_B_C-
VGA_TZCLK- (24) LVDS_B_C- (9)
LVDS_B_C+_R 2 3 VGA_TZCLK+ LVDS_B_C+_R 1 4 LVDS_B_C+
VGA_TZCLK+ (24) LVDS_B_C+ (9)
DDC2_CLK_R 1 4 I2CC_SCL I2CC_SCL (24) RP16 PM@ 0_0404_4P2R_5% RP17 GM@ 0_0404_4P2R_5%
DDC2_DATA_R 2 3 I2CC_SDA
RP19 PM@ 0_0404_4P2R_5%
I2CC_SDA (24) LVDS and USB CAM connector
+5VS
+3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 GM@ GM@

2
GM@ C774 C775 C776 C777 C779 C780 C781 U36
GM@
R878 R879
10U_0805_10V4Z GM@ GM@ GM@ GM@ GM@ GM@ 0_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2 2 2 2 2 2 2 R859
OE* 25 1 2

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS 2 VCC3V DVI_SCLK
11 VCC3V SCL_SINK 28 DVI_SCLK (25)
15 VCC3V
21 29 DVI_SDATA
VCC3V SDA_SINK DVI_SDATA (25)
disable 26
33
VCC3V
VCC3V
+3VS
inverting 40 VCC3V HPD_SINK 30 DVI_DET
DVI_DET (25)
46 0_0402_5%
output VCC3V
DDC_EN 32 R860 1 2
GM@
+3VS
GM@
+3VS 10K_0402_5%
@ R99210K_0402_5% 1 2 3 34 1 @ 2
R990 FUNCTION1 FUNCTION3 R991 10K_0402_5% +3VS
1 2 4 35
FUCNTION2 FUNCTION4 Docking Conn
2

B R862 R861 1 2 B
2.2K_0402_5% 2.2K_0402_5% GM@ R993 R863 1K_0402_5% 1 2
10K_0402_5% 2 1 6 R999 10K_0402_5% GM@
GM@ GM@ ANALOG1(REXT)
GM@
HPD_7318_R 7 +3VS 0 = disable inverting output
pin 4
1

HPD_SOURCE 10K_0402_5%
SDVO_SDAT 8 R994 1 2
GM@ 1 = enable inverting output
(7) SDVO_SDAT SDA_SOURCE
1 2 0 =Default value
SDVO_SCLK 9 R995 10K_0402_5%
(7) SDVO_SCLK SCL_SOURCE pin 35
@ 1 = output driver current
inverting level shift for NB 10 ANALOG2 increased 10%
DVI_TXD0+ 13 48
+3VS (25) DVI_TXD0+ OUT_D4+ IN_D4+ TMDS_B_DATA0 (9)
DVI_TXD0- 14 47
DVI Conn (25) DVI_TXD0- OUT_D4- IN_D4- TMDS_B_DATA0# (9)
DVI_TXC+ 16 45
GM@ (25) DVI_TXC+ OUT_D3+ IN_D3+ TMDS_B_CLK (9)
1

DVI_TXC- 17 44
(25) DVI_TXC- OUT_D3- IN_D3- TMDS_B_CLK# (9)
R868
20K_0402_5% DVI_TXD1+ 19 42
(25) DVI_TXD1+ OUT_D2+ IN_D2+ TMDS_B_DATA1 (9)
@ DVI_TXD1- 20 41
(25) DVI_TXD1- OUT_D2- IN_D2- TMDS_B_DATA1# (9)
0_0402_5%
2

R871 1 2 DVI_HPDT# (9) DVI_TXD2+ 22 39

(25) DVI_TXD2+ OUT_D1+ IN_D1+ TMDS_B_DATA2 (9)
DVI_TXD2- 23 38
(25) DVI_TXD2- OUT_D1- IN_D1- TMDS_B_DATA2# (9)
R874 2N7002_SOT23
1

0_0402_5% D
HPD_7318_R 1 2HPD_7318 2 Q52 R869
20K_0402_5%

G 7.5K_0402_1% 1
@ GND
GM@ S GM@ 5
3

GND
2

12
2

R887 R888 GND

18 GND
R870

0_0402_5% GM@ 0_0402_5% 24 GND

GM@ GM@ 27 GND
GM@ C772 GM@ 31
1

A
DVI_TXC- GND A
2 R864 1 1 2 DVI_TXC+ 36 GND
200_0402_5% 0_0402_50V 37 GND
C773 GM@ 43 GND
GM@
DVI_TXD2- 2 R865 1 1 2 DVI_TXD2+
200_0402_5% 0_0402_50V CH7318A-BF-TR_QFN48_7X7
SA00001U920
HPD_7318_EC (31) GM@ C782 GM@
HPD_7318_R_EC (31) DVI_TXD1- 2 R866 1
200_0402_5%
1 2 DVI_TXD1+
00402_50V
GM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

GM@ C783 GM@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
DVI_TXD0- 2 R867 1 1 2 DVI_TXD0+ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
200_0402_5% 0_0402_50V DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 17 of 43

5 4 3 2 1
 5 4 3 2 1

+3VS

RP29 8.2K_1206_8P4R_5%
4 5 PCI_PIRQE#
3 6 PCI_SERR#
2 7 PCI_PIRQA#
1 8 PCI_PIRQF#

RP30 8.2K_1206_8P4R_5%
1 8 PCI_PLOCK# U6B
2 7 PCI_IRDY# D11 F1 PCI_REQ0#
PCI_PIRQB# AD0 REQ0# PCI_GNT0#
D
3
4
6
5 PCI_REQ3#
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1# D
AD2 REQ1#/GPIO50
E12 AD3 GNT1#/GPIO51 A7 PAD T65
E9 F13 PCI_REQ2#
AD4 REQ2#/GPIO52
C9 AD5 GNT2#/GPIO53 F12 PAD T66
E10 E6 PCI_REQ3#
AD6 REQ3#/GPIO54 PCI_GNT3#
B7 AD7 GNT3#/GPIO55 F6
C7 AD8
C5 AD9 C/BE0# D8 PAD T67
G11 AD10 C/BE1# B4 PAD T68
F8 AD11 C/BE2# D6 PAD T69
+3VS F11 A5
AD12 C/BE3# PAD T70
E7 AD13
RP31 A3 D3 PCI_IRDY#
PCI_STOP# AD14 IRDY#
1 8 D2 AD15 PAR E3 PAD T71
2 7 PCI_PIRQD# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# (31)
3 6 PCI_FRAME# D5 C6 PCI_DEVSEL#
AD17 DEVSEL#

1
4 5 PCI_PERR# D10 E4 PCI_PERR#
AD18 PERR# PCI_PLOCK# R942
B3 AD19 PLOCK# C2
8.2K_1206_8P4R_5% F7 J4 PCI_SERR# 100K_0402_5%
PCI_TRDY# AD20 SERR# PCI_STOP#
1 8 C3 AD21 STOP# A4
2 7 PCI_REQ0# F3 F5 PCI_TRDY#

2
PCI_PIRQG# AD22 TRDY# PCI_FRAME#
3 6 F4 AD23 FRAME# D7
4 5 PCI_PIRQH# C1
RP32 AD24 PLT_RST#
G7 AD25 PLTRST# C14 PLT_RST# (7,20,22,23)
RP33 8.2K_1206_8P4R_5% H7 D4 PCI_CLK
AD26 PCICLK PCI_CLK (15)
1 8 PCI_PIRQC# D1 R2
AD27 PME# PAD T72
2 7 PCI_REQ2# G5
PCI_REQ1# AD28
3 6 H6 AD29
4 5 PCI_DEVSEL# G1 AD30
H3 AD31
8.2K_1206_8P4R_5%

C
<BOM Structure>
PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# C
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# +3VS
E1 PIRQB# PIRQF#/GPIO3 K6
PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2

5
U7
ICH9M REV 1.0 PLT_RST# 2

P
B
1
Y 4 2
R70
1
100_0402_5%
PLTRST_VGA# (24) For VGA/B
A

G
PM@

1
NC7SZ08P5X_NL_SC70-5

3
PM@ R36
100K_0402_5%
PM@

2
A16 swap override Strap Boot BIOS Strap
B B
Low= A16 swap override Enble
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

@ R249 0 1 SPI
PCI_GNT3# 1 2
1K_0402_5%

1 0 PCI

1 1 LPC *
@ R944
@R944 1K_0402_5%
1 2 +3VALW

@ R250
SPI_CS1#_R 1 2
(20) SPI_CS1#_R
1K_0402_5%
@ R251
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 18 of 43
5 4 3 2 1
 5 4 3 2 1

ICH8M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN Low = Internal VR Disabled +3VS

+RTCVCC
High = Internal VR Enabled(Default) R253
GATEA20 1 2
1 2 SM_INTRUDER# 10K_0402_5%
R252 1M_0402_5% ICH8M LAN100 SLP Strap
1 2 LAN100_SLP R256
R254 330K_0402_1% (Internal VR for VccLAN1.05 and VccCL1.05) KB_RST# 1 2
1 2 ICH_INTVRMEN C340 10K_0402_5%
R255 R279 330K_0402_1% 18P_0402_50V8J
D ICH_SRTCRST# ICH_RTCX1 D
1 2 2 1 ICH_LAN100_SLP Low = Internal VR Disabled
20K_0402_5% <BOM Structure> +VCCP
High = Internal VR Enabled(Default)

10M_0402_5%
0_0402_5%

0_0402_5%
1 32.768KHZ_12.5P_MC-306
1

1
C253 @ @ 3 NC @ R260
@R260
OUT 4

R270
@ R258 R259 H_DPRSTP# 1 2
0_0603_5% 2 1 56_0402_5%
CLRP3 2 NC IN
LPC_AD[0..3] (31)

2
1U_0603_10V4Z X1 C339 U6A @ R261
@R261
2

2
18P_0402_50V8J
<BOM Structure> C23 K5 LPC_AD0 H_DPSLP# 1 2
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
2 1 C24 RTCX2 FWH1/LAD1 K4
R262 <BOM Structure> L6 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2
ICH_SRTCRST#

RTC
LPC
20K_0402_5% F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# (31)

1
+VCCP +VCCP
1
C243 @ ICH_INTVRMEN B22 J3
0_0603_5% LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1U_0603_10V4Z CLRP2

2
2 GATEA20
E25 N7 GATEA20 (31)

2
GLAN_CLK A20GATE H_A20M# R263 R98
A20M# AJ27 H_A20M# (4)
C13 56_0402_5% 50_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R264 <BOM
DPRSTP# AJ25 1 Structure>
2 H_DPRSTP#
H_DPRSTP# (5,7,42)
+3VALW F14 AE23 H_DPSLP# 0_0402_5%

LAN / GLAN
H_DPSLP# (5)

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R265 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# (4)

2
56_0402_5% DUAL@ QUAD@
R946 D13 AD22 H_PWRGOOD 3/28 add 56ohm
LAN_TXD0 CPUPWRGD H_PWRGOOD (5)
10K_0402_5% D12 LAN_TXD1
within 2" from R1557
E13 AF25 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# (4) +VCCP

CPU
1
+1.5VS GPIO56 B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# (4) +VCCP
AG25 H_INTR
C INTR H_INTR (4) C
B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# (31)

2
R266 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
AF23 H_NMI DUAL@ R100
NMI H_NMI (4)
R267 33_0402_5% 1 2 HDA_BITCLK AF6 AF24 H_SMI# R269 50_0402_5%
(26) HDA_BITCLK_CODEC HDA_BIT_CLK SMI# H_SMI# (4)
R271 33_0402_5% 1 2 HDA_SYNC AH4 56_0402_5%
(26) HDA_SYNC_CODEC HDA_SYNC
AH27 H_STPCLK#
H_STPCLK# (4)

1
R272 33_0402_5% HDARST# STPCLK#
(26) HDA_RST#_CODEC 1 2 AE7

2
HDA_RST# THRMTRIP_ICH# R274
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# (4,7)
CODEC HDA_SDIN0 AF4 QUAD@
(26) HDA_SDIN0 HDA_SDIN0
MDC HDA_SDIN1 AG4 AG27 placed within 2" from
(32) HDA_SDIN1 HDA_SDIN1 TP12
HDA_SDIN2

IHDA
NB (7) HDA_SDIN2 AH3 HDA_SDIN2 ICH8M
MXM (24) HDA_SDIN3 AE5 HDA_SDIN3
SATA4RXN AH11 SATA_RXN2_C (22)
R276 33_0402_5% 1 2 HDA_SDOUT AG5 AJ11 0.01U_0402_16V7K
(26) HDA_SDOUT_CODEC HDA_SDOUT SATA4RXP SATA_RXP2_C (22)
AG12 SATA_TXN2_C 2 1 C346 SATA_TXN2
SATA4TXN SATA_TXN2 (22)
AG7 AF12 SATA_TXP2_C 2 1 C347 SATA_TXP2
T45 PAD HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP2 (22)
0814 Add pull up R +3VS 1 2 T46 PAD AE8 HDA_DOCK_RST#/GPIO34
R52210K_0402_5% AH9 0.01U_0402_16V7K
SATA5RXN PAD T51
SATA_LED# AG8 AJ9
(33) SATA_LED# SATALED# SATA5RXP PAD T52
SATA5TXN AE10 PAD T54
(22) SATA_RXN0_C AJ16 SATA0RXN SATA5TXP AF10 PAD T53
0.01U_0402_16V7K AH16
(22) SATA_RXP0_C

SATA
SATA_TXN0 C248 SATA_TXN0_C SATA0RXP CLK_PCIE_SATA#
S- HDD (22) SATA_TXN0
SATA_TXP0 C249
1
1
2
SATA_TXP0_C
2<BOM Structure>
AF17
AG17
SATA0TXN SATA_CLKN AH18
AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA# (15)
(22) SATA_TXP0 SATA0TXP SATA_CLKP CLK_PCIE_SATA (15)
0.01U_0402_16V7K AH13 AJ7
(22) SATA_RXN4_C SATA1RXN SATARBIAS#
0.01U_0402_16V7K AJ13 AH7 R277 1 2
(22) SATA_RXP4_C SATA1RXP SATARBIAS
SATA_TXN4 C244 SATA_TXN4_C
ODD (22) SATA_TXN4
SATA_TXP4 C245
1
1
2<BOM Structure>
SATA_TXP4_C
2<BOM Structure>
AG14
AF14
SATA1TXN 24.9_0402_1%
(22) SATA_TXP4 SATA1TXP
0.01U_0402_16V7K ICH9M REV 1.0
Within 500 mils
B B

+RTCBATT

1 2 HDA_BITCLK
(32) HDA_BITCLK_MDC
R268 33_0402_5%

2
1 2 HDA_SYNC
+3VS
HDA for MDA
(32) HDA_SYNC_MDC
R273 33_0402_5%
HDARST#
RTC Battery R48
(32) HDA_RST_MDC# 1 2 1K_0402_5%
R275 33_0402_5%
@ R280 1 2 HDA_SDOUT
(32) HDA_SDOUT_MDC

1 1
1 2 HDA_SDOUT R278 33_0402_5%
1K_0402_5% D8

GM@ 1 2 HDA_BITCLK
(7) HDA_BITCLK_MCH
@ R281 R408 33_0402_5%
1 2 ICH_RSVD (7) HDA_SYNC_MCH GM@ 1 2 HDA_SYNC +RTCVCC
ICH_RSVD (20)
1K_0402_5% R410 33_0402_5%

2
HDA for GMCH GM@ 1 2 HDARST#
(7) HDA_RST_MCH#
R411 33_0402_5% BAS40-04_SOT23-3
GM@ HDA_SDOUT
XOR CHAIN ENTRANCE STRAP:RSVD (7) HDA_SDOUT_MCH 1
R409
2
33_0402_5% 1
+CHGRTC
C109
<BOM Structure>
PM@ 1 2 HDA_BITCLK 0.1U_0402_16V4Z
(24) HDA_BITCLK_VGA 2
R418 33_0402_5%
ICH_RSVD HDA_SDOUT_CODEC (24) HDA_SYNC_VGA PM@ 1 2 HDA_SYNC
HDA for VGA R413 33_0402_5%
PM@ 1 2 HDARST#
(24) HDA_RST_VGA#
R412 1K_0402_1%
A 0 0 (24) HDA_SDOUT_VGA PM@ 1 2 HDA_SDOUT Change BATT1 P/N : SP093PA0200 (Panasonic) A
R416 33_0402_5%
SP093MX0000 (MAXELL)
0 1
1 0
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 19 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS 1 2 SIRQ Place closely pin AF3 Place closely pin H1

R286 10K_0402_5% +3VALW R287 1 2 2.2K_0402_5%
1 2 PM_CLKRUN# R289 1 2 2.2K_0402_5%
R288 8.2K_0402_5% U6C CLK_48M_ICH CLK_14M_ICH
1 2 GPIO39 ICH_SMBCLK G16 AH23 PROJECT_ID1
(15,22) ICH_SMBCLK SMBCLK SATA0GP/GPIO21
@R290
@ R290 10K_0402_5% ICH_SMBDATA A13 AF19 PROJECT_ID0
(15,22) ICH_SMBDATA SMBDATA SATA1GP/GPIO19

1
1 2 THERM_SCI# LINKALERT# E17 AE21 1 2 @

SATA
GPIO
ME_EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

SMB
@R291
@ R291 8.2K_0402_5% C17 AD20 R945 10K_0402_5% R292 R293
CLKREQ#_C ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
1 2 B18 SMLINK1
R294 10K_0402_5% H1 CLK_14M_ICH 10_0402_5% 10_0402_5%
+3VS CLK14 CLK_14M_ICH (15)
1 2 VGA_PRSNT_L EC_SWI# F19 AF3 CLK_48M_ICH

Clocks
CLK_48M_ICH (15)

2
R295 10K_0402_5% (31) EC_SWI# RI# CLK48
1 2 CR_WAKE# SUS_STAT# R4 P1 ICH_SUSCLK 1 1 @
T47 PAD SUS_STAT#/LPCPD# SUSCLK PAD T48
R296 8.2K_0402_5% XDP_DBRESET# G19 C256 C257
(4) XDP_DBRESET# SYS_RESET#

1
1 2 GPIO20 @ @ C16 SLP_S3#
D SLP_S3# SLP_S3# (31) D
@ R297 8.2K_0402_5% R298 R299 PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
(7) PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# (31) 2 2
1 2 OCP# 10K_0402_5% 10K_0402_5% G17 SLP_S5#
SLP_S5# SLP_S5# (31)
R300 10K_0402_5% (31) EC_LID_OUT# EC_LID_OUT# A17
PM_BMBUSY# SMBALERT#/GPIO11 S4_STATE#
1 2 C10

2
@ R301 8.2K_0402_5% H_STP_PCI# S4_STATE#/GPIO26
(15) H_STP_PCI# A14 STP_PCI#
R303 2 0_0402_5% R_STP_CPU# ICH_PWROK

SYS GPIO
(15) H_STP_CPU# 1 E19 STP_CPU# PWROK G20 ICH_PWROK (7)
@
1 2 EC_SCI# (31) PM_CLKRUN# PM_CLKRUN# L4 M2 1 2 0_0402_5%
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR (7,42)
R305 8.2K_0402_5% R306
1 2 VGA_PRSNT_R ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT# ICH_PWROK 1 2

Power MGT
(22,23) ICH_PCIE_WAKE# WAKE# BATLOW#
R307 10K_0402_5% SIRQ M5 R302 R304 10K_0402_5%
(31) SIRQ SERIRQ
THERM_SCI# AJ23 R3 PWRBTN_OUT# 0_0402_5%
(31) THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# (31)
1 2 CR_CPPE# 1 2 PLT_RST# (7,18,22,23)
R949 10K_0402_5% VGATE D21 D20 1 2
(7,42) VGATE VRMPWRGD LAN_RST# R526 0_0402_5% @
1 2 GPIO48 R311 1 2 T49 PAD ICH_TP11 A20 D22 SB_RSMRST# PM_PWROK 1 2
@R310
@ R310 8.2K_0402_5% 100K_0402_5% TP11 RSMRST# R312 10K_0402_5%
(4) OCP# OCP# AG19 R5 CK_PWRGD_R R315 1 2 0_0402_5%
GPIO1 CK_PWRGD CK_PWRGD (15)
1 JV70@ 2 PROJECT_ID0 CRT_DET AH21 GPIO6
R339 8.2K_0402_5% CR_CPPE# AG21 R6 R351 1 2 ICH_PWROK
CR_CPPE# GPIO7 CLPWROK
(31) EC_SMI# EC_SMI# A21 0_0402_5%
GPIO8 +3VS
1 JM70@ 2 PROJECT_ID0 (31) EC_SCI# EC_SCI# C12 GPIO12 SLP_M# B16 PM_SLP_M#
PAD T92
R314 8.2K_0402_5% C21
(23) ENERGY_DET GPIO13
1 2 PROJECT_ID1 (24) VGA_PRSNT_R VGA_PRSNT_R AE18 F24 CL_CLK0 R319
GPIO17 CL_CLK0 CL_CLK0 (7)
R316 8.2K_0402_5% (24) VGA_PRSNT_L VGA_PRSNT_L K1 B19 0.1U_0402_16V4Z 1 2
GPIO20 GPIO18 CL_CLK1 3.24K_0402_1%
AF8 GPIO20

1
1 2 GPIO49 CR_WAKE# AJ22 F22 CL_DATA0 1
CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 (7)
@R318
@ R318 10K_0402_5% GPIO27 A9 C19 C258 R320
T50 PAD

GPIO
Controller Link
GPIO27 CL_DATA1 453_0402_1%
(23) LAN_LOWPWR D19 GPIO28
CLKREQ#_C L1 C25 CL_VREF0_ICH <BOM Structure>
(15) CLKREQ#_C SATACLKREQ#/GPIO35 CL_VREF0 2
0812 No install +3VS 1 2 GPIO38 AE19 A19 CL_VREF1_ICH NA lead free

2
R321 @ 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C GPIO48 AF21 F21 CL_RST# +3VALW C
+3VALW SDATAOUT1/GPIO48 CL_RST0# CL_RST# (7)
GPIO49 AH24 D18
LINKALERT# @ GPIO57 GPIO49 CL_RST1# R324
1 2 A8 GPIO57/CLGPIO5
R322 10K_0402_5% +3VS R323 1 2 1K_0402_5% A16 GPIO24 0.1U_0402_16V4Z 1 2
ICH_PCIE_WAKE# SB_SPKR MEM_LED/GPIO24 GPIO10 3.24K_0402_1%
1 2 (26) SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18

1
R326 1K_0402_5% MCH_ICH_SYNC# AJ24 C11 1
(7) MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
1 2 EC_SMI# ICH_RSVD B21 C20 C259 R327
(19) ICH_RSVD TP3 WOL_EN/GPIO9
R336 8.2K_0402_5% @ ICH_TP8 453_0402_1%

MISC
T95 PAD AH20 TP8 2 1 +3VALW
1 2 ICH_LOW_BAT# ICH_TP9 AJ20 R329 100K_0402_5% <BOM Structure>
T96 PAD TP9 2
R325 8.2K_0402_5% ICH_TP10 AJ21 ICH_ACIN 2 1
T97 PAD EC_ACIN (24,31)

2
S4_STATE# TP10 D10
1 2
R331 10K_0402_5% @ ICH9M REV 1.0 GPIO9 CH751H-40PT_SOD323-2
PAD T111
RP34
4 5 ME_EC_CLK1 U6D
3 6 ME_EC_DATA1 N29 V27 DMI_RXN0 DMI_RXN0 (7) @
XDP_DBRESET# PERN1 DMI0RXN DMI_RXP0 R355 2
2 7 N28 PERP1 DMI0RXP V26 DMI_RXP0 (7) 1 0_0402_5%

Direct Media Interface

EC_SWI# DMI_TXN0
1 8 New Card Del P27
P26
PETN1 DMI0TXN U29
U28 DMI_TXP0
DMI_TXN0 (7) +3VALW
PETP1 DMI0TXP DMI_TXP0 (7)
10K_1206_8P4R_5%
4 5 GPIO24 PCIE_RXN2 L29 Y27 DMI_RXN1 DMI_RXN1 (7)
(22) PCIE_RXN2 PERN2 DMI1RXN

5
3 6 EC_LID_OUT# PCIE_RXP2 L28 Y26 DMI_RXP1 DMI_RXP1 (7) U24
(22) PCIE_RXP2 PERP2 DMI1RXP
GPIO10 C683 1 2 0.1U_0402_16V7K PCIE_C_TXN2 DMI_TXN1 PM_PWROK
2 7 WLAN M27 W29 2

P
(22) PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 (7) B PM_PWROK (31)
1 8 (22) PCIE_TXP2 C681 1 2 0.1U_0402_16V7K PCIE_C_TXP2 M26 W28 DMI_TXP1 DMI_TXP1 (7) ICH_PWROK 4
PETP2 DMI1TXP Y VGATE
A 1

G
RP35 10K_1206_8P4R_5% GLAN_RXN J29 AB27 DMI_RXN2 DMI_RXN2 (7)
(23) GLAN_RXN PERN3 DMI2RXN
GLAN_RXP J28 AB26 DMI_RXP2 DMI_RXP2 (7) NC7SZ08P5X_NL_SC70-5 2 1 +3VS
(23) GLAN_RXP

3
PERP3 DMI2RXP

PCI-Express
C268 1 2 0.1U_0402_16V7K GLAN_TXN_C DMI_TXN2 R337 @ 2K_0402_1%
GIGA LAN (23) GLAN_TXN
C269 1 2 0.1U_0402_16V7K GLAN_TXP_C
K27
K26
PETN3 DMI2TXN AA29
AA28 DMI_TXP2
DMI_TXN2 (7)
(23) GLAN_TXP PETP3 DMI2TXP DMI_TXP2 (7)
PCIE_RXN4 G29 AD27 DMI_RXN3 DMI_RXN3 (7) @
(22) PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 G28 AD26 DMI_RXP3 R353 2 1 0_0402_5%
RP27
MINI CARD (22) PCIE_RXP4
C684 1 2 0.1U_0402_16V7K PCIE_C_TXN4 H27
PERP4 DMI3RXP
AC29 DMI_TXN3
DMI_RXP3 (7)
Q21
B
(22) PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 (7) B
USB_OC#7 4 5 (22) PCIE_TXP4 C685 1 2 0.1U_0402_16V7K PCIE_C_TXP4 H26 AC28 DMI_TXP3 DMI_TXP3 (7) MMBT3906_SOT23-3
+3VALW PETP4 DMI3TXP
USB_OC#4 3 6 SB_RSMRST# 1 <BOM 3Structure>

C
EC_RSMRST# (31)
USB_OC#0 2 7 E29 T26 CLK_PCIE_ICH#

E
PERN5 DMI_CLKN CLK_PCIE_ICH# (15)
1 8 E28 T25 CLK_PCIE_ICH
CARD READER PERP5 DMI_CLKP CLK_PCIE_ICH (15)

1
F27

B
2
10K_1206_8P4R_5% PETN5 R338 24.9_0402_1% R357
F26 PETP5 DMI_ZCOMP AF29
DMI_IRCOMP
Within 500 mils 1
R358
2
4.7K_0402_5%
+3VALW
DMI_IRCOMP AF28 1 2 +1.5VS 10K_0402_5%
RP28 C29
USB_OC#8 +3VALW PERN6/GLAN_RXN USB20_N0 D51A
4 5 C28 AC5 USB20_N0 (29)

2
PERP6/GLAN_RXP USBP0N

R
i
g
h
t
s
i
d
e
2
USB_OC#9 3 6 D27 AC4 USB20_P0 1
PETN6/GLAN_TXN USBP0P USB20_P0 (29)
USB_OC#5 2 7 D26 AD3 USB20_N1 6
PETP6/GLAN_TXP USBP1N USB20_N1 (29)
2

USB_OC#11 1 8 @ AD2 USB20_P1 2

USBP1P USB20_P1 (29)

R
i
g
h
t
s
i
d
e
1
R309 ICH_SPI_CLK R641 1 2 33_0402_5% ICH_SPI_CLK_R D23 AC1 USB20_N2
SPI_CLK USBP2N USB20_N2 (29)
10K_1206_8P4R_5% 10K_0402_5% ICH_SPI_CS0# R649 1 2 33_0402_5% ICH_SPI_CS0#_R D24 AC2 USB20_P2 BAV99DW-7_SOT363
SPI_CS0# USBP2P USB20_P2 (29)

C
a
m
e
r
a
(18) SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3 <BOM Structure>
10K_1206_8P4R_5% SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 (17)
AA4 USB20_P3 D51B
USB20_P3 (17)
1

USBP3P

C
a
r
d
r
e
a
d
e
r
CP_PE# 1 8 GPIO57 GLAN ICH_SPI_MOSI R650 1 2 33_0402_5% ICH_SPI_MOSI_R D25 AB2 USB20_N4 4
SPI_MOSI USBP4N USB20_N4 (28)
SPI

USB_OC#2 2 7 ICH_SPI_MISO R651 1 2 33_0402_5% ICH_SPI_MISO_R E23 AB3 USB20_P4 3

SPI_MISO USBP4P USB20_P4 (28)

E
S
A
T
A
2

USB_OC#10 3 6 AA1 USB20_N5 5

USBP5N USB20_N5 (22)

1
USB_OC#3 4 5 USB_OC#0 N4 AA2 USB20_P5
100K_0402_5% (29) USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 (22)

H
S
P
o
r
t
CP_PE# USB20_N6 +3VS BAV99DW-7_SOT363 R354
N5 OC1#/GPIO40 USBP6N W5 USB20_N6 (29)
RP36 R524 USB_OC#2 USB20_P6 2.2K_0402_5%
(29) USB_OC#2
USB_OC#3
N6
P6
OC2#/GPIO41 USBP6P USB W4
Y3
USB20_P6 (29) <BOM Structure>
(22) USB_OC#3
1

OC3#/GPIO42 USBP7N

2
USB_OC#4 M1 Y2

2
OC4#/GPIO43 USBP7P

B
T
USB_OC#5 N2 W1 USB20_N8 R360
OC5#/GPIO29 USBP8N USB20_N8 (32)
USB_OC#6 M4 W2 USB20_P8 10K_0402_5%
(29) USB_OC#6 OC6#/GPIO30 USBP8P USB20_P8 (32)
0814 UPDATE USB_OC#7 M3 V2 High: CRT Plugged
USB_OC#8 OC7#/GPIO31 USBP9N
N3 V3

1
OC8#/GPIO44 USBP9P

W T
L V
A T
N u
USB_OC#9 N1 U5 USB20_N10 CRT_DET
OC9#/GPIO45 USBP10N USB20_N10 (22)
USB_OC#10 P5 U4 USB20_P10
OC10#/GPIO46 USBP10P USB20_P10 (22)

n
e
r

1
USB_OC#11 USB20_N11 D
P3 OC11#/GPIO47 USBP11N U1 USB20_N11 (22)
U2 USB20_P11 2 2N7002_SOT23
A +3VS USBP11P USB20_P11 (22) (16) CRT_DET# A
ICH SPI ROM for HDCP @ USBRBIAS AG2 G
U40 USBRBIAS
AG1 S <BOM Structure>

3
USBRBIAS#
1

ICH_SPI_CS0# 1 8 Within 500 mils Q22

R652 1 CS# VCC
+3VS 2 3.3K_0402_5% ICH_SPI_WP# 3 WP# SCLK 6 ICH_SPI_CLK ICH9M REV 1.0
R653 1 2 3.3K_0402_5% ICH_SPI_HOLD# 7 5 ICH_SPI_MOSI R340
HOLD# SI ICH_SPI_MISO 22.6_0402_1%
4 GND SO 2
2

MX25L512AMC-12G_SO8
SA000022S00 Security Classification Compal Secret Data Compal Electronics, Inc.
If ICH SPI not used, Left NC SPI ROM Footprint 150mil Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 20 of 43
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U6E

20 mils U6F AA26 H5
G3: 6uA VSS[1] VSS[107]
A23 VCCRTC VCC1_05[1] A15 AA27 VSS[2] VSS[108] J23

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1634mA
VCC1_05[2] B15 AA3 VSS[3] VSS[109] J26
1 1 ICH_V5REF_RUN A6 2mA C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[3] VSS[4] VSS[110]

C270

C271
VCC1_05[4] D15 1 1 AB1 VSS[5] VSS[111] AC22
ICH_V5REF_SUS AE1 2mA E15 C272 C273 AA23 K28
V5REF_SUS VCC1_05[5] VSS[6] VSS[112]
VCC1_05[6] F15 AB28 VSS[7] VSS[113] K29
2 2
AA24 VCC1_5_B[1] VCC1_05[7] L11 AB29 VSS[8] VSS[114] L13
646mA 2 2
0820 Change to 0805 AA25 VCC1_5_B[2] VCC1_05[8] L12 AB4 VSS[9] VSS[115] L15
AB24 VCC1_5_B[3] VCC1_05[9] L14 AB5 VSS[10] VSS[116] L2
AB25 VCC1_5_B[4] VCC1_05[10] L16 AC17 VSS[11] VSS[117] L26
R341 40 mils AC24 L17 0.01U_0402_16V7K AC26 L27
VCC1_5_B[5] VCC1_05[11] VSS[12] VSS[118]

<BOM Structure>
+1.5VS 1 2 10U_0805_10V4Z AC25 L18 +1.5VS_VCCDMIPLL R342 1 2 +1.5VS AC27 L5
0_0805_5% VCC1_5_B[6] VCC1_05[12] MBK1608301YZF_0603 VSS[13] VSS[119]
1 AD24 VCC1_5_B[7] VCC1_05[13] M11 AC3 VSS[14] VSS[120] L7
D D
1 1 1 AD25 VCC1_5_B[8] VCC1_05[14] M18 1 1 AD1 VSS[15] VSS[121] M12
+

220U_D2_4VM_R15
C275 C276 C277 AE25 P11 C278 C279 AD10 M13
VCC1_5_B[9] VCC1_05[15] VSS[16] VSS[122]

C274
AE26 VCC1_5_B[10] VCC1_05[16] P18 AD12 VSS[17] VSS[123] M14
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD13 VSS[18] VSS[124] M15
2 2 2 2 2 2
0816 Change to 10 ohm <BOM Structure>
<BOM Structure>
<BOM Structure> AE28 VCC1_5_B[12] VCC1_05[18] T18 <BOM Structure>
<BOM Structure> AD14 VSS[19] VSS[125] M16
AE29 U11 AD17 M17

CORE
10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[19] 10U_0805_10V4Z VSS[20] VSS[126]
F25 VCC1_5_B[14] VCC1_05[20] U18 AD18 VSS[21] VSS[127] M23
+5VS +3VS G25 V11 AD21 M28
VCC1_5_B[15] VCC1_05[21] VSS[22] VSS[128]
H24 VCC1_5_B[16] VCC1_05[22] V12 AD28 VSS[23] VSS[129] M29
H25 VCC1_5_B[17] VCC1_05[23] V14 +VCCP AD29 VSS[24] VSS[130] N11
1

22U_0805_6.3VAM
J24 VCC1_5_B[18] VCC1_05[24] V16 AD4 VSS[25] VSS[131] N12
R343 D11 J25 V17 1 0905 Connect to +VCCP AD5 N13
VCC1_5_B[19] VCC1_05[25] C280 VSS[26] VSS[132]
K24 VCC1_5_B[20] VCC1_05[26] V18 AD6 VSS[27] VSS[133] N14
100_0402_5% CH751H-40PT_SOD323-2 K25 AD7 N15
VCC1_5_B[21] VSS[28] VSS[134]
L23 R29 AD9 N16
2

VCC1_5_B[22] VCCDMIPLL 2 VSS[29] VSS[135]

L24 VCC1_5_B[23] AE12 VSS[30] VSS[136] N17
SD028100080 ICH_V5REF_RUN L25 23mA W23 AE13 N18
VCC1_5_B[24] VCC_DMI[1] +VCCP VSS[31] VSS[137]
1 20 mils M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE14 VSS[32] VSS[138] N26
C281 M25 AE16 N27
VCC1_5_B[26] VSS[33] VSS[139]
N23 48mA AB23 AE17 P12
1U_0402_6.3V4Z VCC1_5_B[27] V_CPU_IO[1] VSS[34] VSS[140]
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE2 VSS[35] VSS[141] P13
2 SE100105Z80

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N25 VCC1_5_B[29] AE20 VSS[36] VSS[142] P14
P24 2mA AG29 +3VS AE24 P15
VCC1_5_B[30] VCC3_3[1] 1 1 1 VSS[37] VSS[143]

C282

C283

C284
P25 VCC1_5_B[31] AE3 VSS[38] VSS[144] P16

VCCA3GP
R24 VCC1_5_B[32] VCC3_3[2] AJ6 AE4 VSS[39] VSS[145] P17
+5VALW +3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R25 VCC1_5_B[33] AE6 VSS[40] VSS[146] P2
2 2 2
R26 VCC1_5_B[34] VCC3_3[7] AC10 1 1 1 AE9 VSS[41] VSS[147] P23
R27 VCC1_5_B[35] AF13 VSS[42] VSS[148] P28
1

C285

C286

C287
D12 T24 AD19 AF16 P29
R344 VCC1_5_B[36] VCC3_3[3] VSS[43] VSS[149]

VCCP_CORE
T27 VCC1_5_B[37] VCC3_3[4] AF20 AF18 VSS[44] VSS[150] P4
2 2 2 (DMI)
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF22 VSS[45] VSS[151] P7
100_0402_5% CH751H-40PT_SOD323-2 T29 AC20 +3VS AH26 R11
C VCC1_5_B[39] VCC3_3[6] VSS[46] VSS[152] C
U24 AF26 R12
2

ICH_V5REF_SUS VCC1_5_B[40] 0.1U_0402_16V4Z VSS[47] VSS[153]

U25 VCC1_5_B[41] 308mA
VCC3_3[8] B9 AF27 VSS[48] VSS[154] R13
20 mils V24 VCC1_5_B[42] VCC3_3[9] F9 1 1 0816 Add 0.1uF AF5 VSS[49] VSS[155] R14
SD028100080 1 V25 G3 C288 C479 AF7 R15
C289 VCC1_5_B[43] VCC3_3[10] VSS[50] VSS[156]
U23 VCC1_5_B[44] VCC3_3[11] G6 AF9 VSS[51] VSS[157] R16
W24 J2 0.1U_0402_16V4Z AG13 R17
1U_0402_6.3V4Z VCC1_5_B[45] VCC3_3[12] 2 2 VSS[52] VSS[158]

PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[53] VSS[159] R18
2 SE100105Z80
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[54] VSS[160] R28
Y24 PM@ R964 0_0402_5% AG20 T12
VCC1_5_B[48] +VCCHDA 0.1U_0402_16V4Z VSS[55] VSS[161]
Y25 VCC1_5_B[49] VCCHDA AJ4 1 2 +3VS AG23 VSS[56] VSS[162] T13
R345 PM@ R965 0_0402_5% 1 1 2 +1.5VS AG3 T14
47mA 11mA +VCCSUSHDA C290 GM@ R966 VSS[57] VSS[163]
+1.5VS 1 2 AJ19 VCCSATAPLL VCCSUSHDA AJ3 1 2 +3VALW AG6 VSS[58] VSS[164] T15
1U_0603_10V4Z

MBK1608301YZF_0603 0.1U_0402_16V4Z 1 1 2 +1.5V 0_0402_5% AG9 T16

11mA VSS[59] VSS[165]
10U_0805_10V4Z

AC16 GM@ R967

+1.5VS VCC1_5_A[1] VCCSUS1_05[1] AC8 PAD T55
0_0402_5% 2
AH12 VSS[60] VSS[166] T17
1 1 AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 PAD T56 AH14 VSS[61] VSS[167] T23
C292

C293

1 AD16 C291 AH17 B26

VCC1_5_A[3] 2 VSS[62] VSS[168]
ARX

C294 AE15 VCCSUS1_5_ICH_1

VCC1_5_A[4] VCCSUS1_5[1] AD8 PAD T57 AH19 VSS[63] VSS[169] U12
AF15 VCC1_5_A[5] AH2 VSS[64] VSS[170] U13
2 2 1U_0603_10V4Z VCCSUS1_5_ICH_2
<BOM Structure>
<BOM Structure> AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 PAD T58 AH22 VSS[65] VSS[171] U14
2
AH15 VCC1_5_A[7] 1 AH25 VSS[66] VSS[172] U15
AJ15 +3VALW C480 AH28 U16
VCC1_5_A[8] 0.1U_0402_16V4Z VSS[67] VSS[173]
A18 AH5 U17
VCCPSUS

VCCSUS3_3[1] VSS[68] VSS[174]

0.1U_0402_16V4Z
AC11 D16 1 1 0.1U_0402_16V4Z AH8 AD23
+1.5VS VCC1_5_A[9] VCCSUS3_3[2] 2 VSS[69] VSS[175]
1 AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AJ12 VSS[70] VSS[176] U26

C295

C296
C297 AE11 E22 AJ14 U27
VCC1_5_A[11] VCCSUS3_3[4] VSS[71] VSS[177]
ATX

AF11 VCC1_5_A[12] AJ17 VSS[72] VSS[178] U3

1U_0603_10V4Z 212mA 2 2
2
AG10 VCC1_5_A[13] 0816 Add 0.1uF AJ8 VSS[73] VSS[179] V1
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 B11 VSS[74] VSS[180] V13
AH10 VCC1_5_A[15] B14 VSS[75] VSS[181] V15
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 B17 VSS[76] VSS[182] V23
VCCSUS3_3[7] T2 B2 VSS[77] VSS[183] V28
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 B20 VSS[78] VSS[184] V29
B
T4 +3VALW B23 V4 B
VCCSUS3_3[9] VSS[79] VSS[185]
AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 B5 VSS[80] VSS[186] V5
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B8 VSS[81] VSS[187] W26
1342mA U6 1 C26 W27
VCCPUSB

+1.5VS VCCSUS3_3[12] VSS[82] VSS[188]

AC21 U7 C298 C27 W3
VCC1_5_A[20] VCCSUS3_3[13] VSS[83] VSS[189]
1 VCCSUS3_3[14] V6 E11 VSS[84] VSS[190] Y1
C299 G10 V7 4.7U_0603_6.3V6M E14 Y28
VCC1_5_A[21] VCCSUS3_3[15] 2 VSS[85] VSS[191]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z W7 E2 Y4
2 VCCSUS3_3[17] VSS[87] VSS[193]
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E21 VSS[88] VSS[194] Y5
AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 E24 VSS[89] VSS[195] AG28
+1.5VS AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E5 VSS[90] VSS[196] AH6
1 11mA 11mA E8 AF2
C300 VCCCL1_05_ICH VSS[91] VSS[197]
AJ5 VCCUSBPLL VCCCL1_05 G22 F16 VSS[92] VSS[198] B25
1 F28 VSS[93]
0.1U_0402_16V4Z AA7 G23 C481 F29 A1
2 VCC1_5_A[26] VCCCL1_5 VSS[94] VSS_NCTF[1]
USB CORE

AB6 VCC1_5_A[27]
19/73/73mA G12 VSS[95] VSS_NCTF[2] A2
AB7 VCC1_5_A[28] VCCCL3_3[1] A24 +3VS 1 @ 2
0.1U_0402_16V4Z G14 VSS[96] VSS_NCTF[3] A28
AC6 B24 C301 G18 A29
VCC1_5_A[29] VCCCL3_3[2] 1U_0603_10V4Z VSS[97] VSS_NCTF[4]
AC7 VCC1_5_A[30] G21 VSS[98] VSS_NCTF[5] AH1
0.1U_0402_16V4Z C310 G24 AH29
VCC_LAN1_05_INT_ICH_1 2 VSS[99] VSS_NCTF[6]
+3VS
1 2 A10 VCCLAN1_05[1] 0816 Add 0.1uF G26 VSS[100] VSS_NCTF[7] AJ1
A11 VCCLAN1_05[2] G27 VSS[101] VSS_NCTF[8] AJ2
R535 0_0603_5% G8 AJ28
+3VS_VCCLAN VSS[102] VSS_NCTF[9]
1 2 A12 VCCLAN3_3[1] H2 VSS[103] VSS_NCTF[10] AJ29
0.1U_0402_16V4Z

1 B12 19/78/78mA H23 B1

C302 R346 0_0603_5% VCCLAN3_3[2] VSS[104] VSS_NCTF[11]
23mA H28 VSS[105] VSS_NCTF[12] B29
1 2 +1.5VS_VCCGLANPLL A27 H29
R347 VCCGLANPLL
80mA VSS[106]
2 +1.5VS
GLAN POWER
10U_0805_10V4Z

2+1.5VS_VCCGLAND28 ICH9M REV 1.0

2.2U_0603_6.3V4Z

+1.5VS 1 VCCGLAN1_5[1]
D29 VCCGLAN1_5[2]
1 1 0_0603_5% 1 E26
A C303 C304 VCCGLAN1_5[3] A
E27 VCCGLAN1_5[4]
1mA
+3VS A26 VCCGLAN3_3
2 2 2
0316 change design C305 ICH9M REV 1.0
4.7U_0805_10V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 21 of 43
5 4 3 2 1
 5 4 3 2 1

HDD Connector +5VS CD-ROM Connector

Placea caps. near ODD CONN. JSATA2
+5VS JSATA1 Near CONN side.
GND 1 GND 1
2 SATA_TXP0 2 SATA_TXP4
A+ SATA_TXP0 (19) A+ SATA_TXP4 (19)
10U_0805_10V4Z

0.1U_0402_16V4Z
3 SATA_TXN0 3 SATA_TXN4
A- SATA_TXN0 (19) A- SATA_TXN4 (19)

0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z
1 1 1 1 4 0.01U_0402_16V7K 4 0.01U_0402_16V7K
GND GND
C311

C314
5 SATA_RXN0 2 1 C306 SATA_RXN0_C 1 1 1 1 5 SATA_RXN4 2 1 C322 SATA_RXN4_C
B- SATA_RXN0_C (19) B- SATA_RXN4_C (19)

C324
C312 C313 6 SATA_RXP0 2 1 C315 SATA_RXP0_C 6 SATA_RXP4 2 1 C323 SATA_RXP4_C
B+ SATA_RXP0_C (19) B+ SATA_RXP4_C (19)

C325

C326
7 0.01U_0402_16V7K C327 7 0.01U_0402_16V7K
2 2 2 2 GND 10U_0805_10V4Z GND

D
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side. 2 2 2 2
D
V33 8 DP 8
9 +3VS_HDD1 9 +5VS
V33 +5V
Pleace near HD CONN (JP23) V33 10 +5V 10
GND 11 MD 11
GND 12 15 GND GND 12
+3VS 13 14 13
@ R3480_0805_5%
@R3480_0805_5% +3VS_HDD1 GND GND GND
V5 14
2 1 15 +5VS
0.1U_0402_16V4Z V5 CONN@ OCTEK_0709015-SD001_RV
V5 16
1 1 1 GND 17
Reserved 18
@C319
@ C319 @C320
@ C320 @ C321 19
GND R572 JMINI2
V12 20
2 2 2 ICH_PCIE_WAKE#1 @
V12 21 (20,23) ICH_PCIE_WAKE# 2 0_0402_5% 1 1 2 2 +3VS_WLAN
1000P_0402_50V7K 1U_0603_10V4Z 22 WLAN_BT_DATA 3 4
V12 (32) WLAN_BT_DATA 3 4
WLAN_BT_CLK 5 6 +1.5VS
(32) WLAN_BT_CLK 5 6
Pleace near HD CONN SUYIN_127043FR022G226ZL_NR (15) MCARD_CLKREQ# 7 7 8 8
<BOM Structure> 9 9 10 10
(15) CLK_PCIE_MCARD1# 11 11 12 12
(15) CLK_PCIE_MCARD1 13 13 14 14
15 15 16 16
17 17 18 18
19 20 WL_OFF#
19 20 WL_OFF# (31)
21 22 PLT_RST#
21 22 PLT_RST# (7,18,20,23)
23 24 R573 1 2 0_0603_5% +3VS_WLAN
(20) PCIE_RXN2 23 24
25 26 R654 1 2 0_0603_5%
HDD Connector (20) PCIE_RXP2
27
29
25
27
29
26
28
30
28
30 ICH_SMBCLK
ICH_SMBDATA
@
+3VALW

ICH_SMBCLK (15,20)
(20) PCIE_TXN2 31 31 32 32 ICH_SMBDATA (15,20)
(20) PCIE_TXP2 33 33 34 34
35 35 36 36 USB20_N10 (20)
+5VS JSATA3 37 38
37 38 USB20_P10 (20)
GND 1 +3VS_WLAN 39 39 40 40
C SATA_TXP2 C
A+ 2 SATA_TXP2 (19) 41 41 42 42
10U_0805_10V4Z

0.1U_0402_16V4Z

3 SATA_TXN2 43 44 (MINI1_LED#) MINI1_LED# (31)

A- SATA_TXN2 (19) 43 44
1 1 1 1 4 0.01U_0402_16V7K 45 46
GND 45 46
C332

C329

SATA_RXN2 1 C317 SATA_RXN2_C

C333 C318 B- 5
6 SATA_RXP2
2
2 1 C334 SATA_RXP2_C
SATA_RXN2_C (19)
UTX
47
49
47 48 48
50
R998 (9~16mA)
B+ SATA_RXP2_C (19) (31) UTX 49 50
7 0.01U_0402_16V7K URX 51 52 1 2 +3VS
2 2 2 2 GND (31) URX 51 52
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side. 53 GND1 GND2 54 10K_0402_5%
VCC3.3 8
+3VS_HDD2 @
VCC3.3 9 For MINICARD Port80 Debug FOX_AS0B226-S52N-7F~N R415 1
Pleace near HD CONN (JP23) VCC3.3 10 +3VS_WLAN 2 0_1206_5% +3VS
GND 11 <BOM Structure>
12 R414 1 @ 2 0_1206_5% +3VALW
+3VS GND
GND 13
@R359
@ R359 +3VS_HDD2 14 +3VS_WLAN +1.5VS +3VS
VCC5 +5VS
2 1 VCC5 15
0.1U_0402_16V4Z 16
0_0805_5% VCC5
1 1 1 GND 17 1 1 1 1 1 1
18 C686 C687 C688 C689 C690 C691
@ C331 @ C328 @C330
@ C330 RESERVED
GND 19
20 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 VCC12 2 2 2 2 2 2
VCC12 21
1000P_0402_50V7K 1U_0603_10V4Z 22
VCC12
Pleace near HD CONN G1 23
24
For Wireless LAN
G2
OCTEK_SAT-22SB1G_RV
<BOM Structure>

For TV Tuner
B B
eSATA w/ USB R574 0_0402_5% JMINI1
port ICH_PCIE_WAKE#
WLAN_BT_DATA
1 @ 2 1
3
1
3
2
4
2
4
+3VS_TV
WLAN_BT_CLK 5 6 +1.5VS
5 6
+5VALW (15) MCARD_CLKREQ2# 7 7 8 8
+USB_VCCA
U25
80mil 9 9 10 10
JM70@ C403 C404
(15) CLK_PCIE_MCARD2# 11 11 12 12
1 8 13 14 JM70@
GND OUT (15) CLK_PCIE_MCARD2 13 14
2 7 15 16 0.1U_0402_16V4Z 0.1U_0402_16V4Z
IN OUT 15 16
3 IN OUT 6
1 4 EN# FLG 5 USB_OC#3 (20)
C343 17 18
TPS2061DRG4_SO8 17 18
1 19 19 20 20
4.7U_0805_10V4Z C335 21 22 PLT_RST#
2 21 22 PLT_RST# (7,18,20,23)
@ 23 24
(20) PCIE_RXN4 23 24
0.1U_0402_16V4Z 25 26
2 (20) PCIE_RXP4 25 26
27 27 28 28
USB20_N5 29 30 ICH_SMBCLK ICH_SMBCLK (15,20)
(29,34) SYSON# +USB_VCCA 29 30
USB20_P5 (20) PCIE_TXN4 31 32 ICH_SMBDATA ICH_SMBDATA (15,20)
31 32
W=60mils 1000P_0402_50V7K
(20) PCIE_TXP4 33 33 34 34
USB20_N11
35 35 36 36 USB20_N11 (20)
3

1 D19 37 38 USB20_P11 USB20_P11 (20)

37 38
1 1 +3VS_TV 39 39 40 40
C806 + PJDLC05_SOT23~D 41 42 R417 1 JM70@2 0_1206_5%
41 42 +3VS_TV +3VS
150U_B2_6.3VM_R45M C808 C807 43 44
43 44
45 45 46 46
2 2 2 +3VS_TV +1.5VS
47 48
1

0.1U_0402_16V4Z UTX 47 48
49 49 50 50
JUSB4 URX 51 52
51 52
1 VCC 1 1 1 1
USB20_N5 C695 C694 C696 C697

G1
G2
G3
G3
(20) USB20_N5 2 D-
A USB20_P5 3 A
(20) USB20_P5 D+
4 FOX_AS0B226-S99N-7F 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z

53
54
55
56
GND CONN@ 2 2 2 2
5 JM70@ JM70@ JM70@ JM70@
GND1
6 GND2
SUYIN_020173MR004S512ZL

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
PVT- Update ESATA connector footprint for latche hole size. Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 22 of 43
5 4 3 2 1
 5 4 3 2 1

+3VALW R1052 1 2 0_1206_5% +3V_LAN

R1053 1 2 0_1206_5% +3V_LAN_R

+3V_LAN 1 2 LAN_PME#

2
R1054 4.7K_0402_5%
R1084
1.5_1206_5%
<BOM Structure>
1 1

3 1
+3V_LAN C970 C971
60mil 0.1U_0402_16V4Z
D LAN_REGCTL12 1 2 2 D

1 1 1 1 4.7U_0805_10V4Z
C973 C979 C974 C975 Q71 +1.2V_LAN
MMJT9435T1G_SOT223

2
4
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1 1 1 1
C972 C976 C1043 C977 C978 C980 C1021 C981 C982 C983 C984
@ @
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

+3V_LAN
U56

2
41 LAN_MIDI0-
TRD0_N LAN_MIDI0- (25)
28 40 LAN_MIDI0+ R1055
(15) CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_MIDI0+ (25)
42 +LAN_AVDD
TRD1_N/AVDD 4.7K_0402_5%
(15) CLK_PCIE_LAN 29 PCIE_REFCLK_P TRD1_P/T1_N 43 LAN_MIDI1- (25)
48 +LAN_AVDD

1
TRD2_N/AVDD SPROM_DIN
(15) LAN_CLKREQ# 11 CLKREQ TRD2_P/T2_N 47 LAN_MIDI2- (25)
@ 49 LAN_MIDI3-
TRD3_N LAN_MIDI3- (25)
R1058 1 2 0_0402_5% 50 LAN_MIDI3+
(20) LAN_LOWPWR TRD3_P LAN_MIDI3+ (25)
0_0402_5% 1 R1104 2 3 LOW PWR
R1059 1 2 1K_0402_5% 53 2 2 R1060 1 0_0402_5% +3V_LAN +3V_LAN +3V_LAN
+3VS VMAIN_PRSNT LINKLED LAN_LINK# (25)
SPD100LED 1 +3V_LAN
C R1057 1 C
+3V_LAN 2 1K_0402_5% 54 VAUX_PRSNT SPD1000LED 67 1
66 2 1 C985
TRAFFICLED LAN_ACTIVITY# (25)

2
R1061 0_0402_5%
0_0402_5% 0.1U_0402_16V4Z R1062 R1063 R1064
R1105 SPROM_CLK 2
(20) ENERGY_DET 1 2 59 ENERGY_DET SCLK(EECLK) 65 4.7K_0402_5% 4.7K_0402_5%4.7K_0402_5%
63 SPROM_DIN U57
+LAN_GPHYPLLVDD SI SPROM_DOUT
35 64 1 8

1
GPHY_PLLVDD SO(EEDATA) SPROM_CS R1065 1 A0 VCC
CS 62 2 4.7K_0402_5% 2 A1 WP 7 SPROM_WP
32 2 1 3 6 SPROM_CLK
(20) GLAN_TXN PCIE_RXD_N A2 SCL
R1066 0_0402_5% 4 5 SPROM_DOUT
GND SDA
(20) GLAN_TXP 31 PCIE_RXD_P
14 LAN_REGCTL12 AT24C64AN-10SU-2.7_SO8
C986 1 GLAN_RXN_C REGCTL12
(20) GLAN_RXN 2 25 PCIE_TXD_N REGCTL25/12_IO 18 +Lan_VDDIO_1.2
0.1U_0402_16V7K 37 LAN_RDAC 1 2
C987 1 GLAN_RXP_C RDAC R1067 1.24K_0402_1%
(20) GLAN_RXP 2
0.1U_0402_16V7K
26 PCIE_TXD_P 20mil L70
L69
+LAN_PCIEPLLVDD 1 2 +1.2V_LAN
23 +LAN_XTALVDD 1 2 +Lan_VDDIO_1.2 BLM18AG601SN1D_2P
XTALVDD +3V_LAN 1 1
R1068 1 2 0_0402_5% LAN_RESET# 10 6 +3V_LAN BLM18AG601SN1D_2P C988 C989
(7,18,20,22) PLT_RST# PERST VDDIO
VDDIO 15 1
R1069 1 @ 2 0_0402_5% LAN_PME# 12 19 C990 0.1U_0402_16V4Z
(20,22) ICH_PCIE_WAKE# WAKE VDDIO 2 2
(31) EC_LAN_PME# R1070 1 2 0_0402_5% 56 1 1
VDDIO 0.1U_0402_16V4Z C991 C992 4.7U_0805_10V4Z
VDDIO 61
2
58 17 +Lan_VDDIO_1.2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 20mil
SMB_CLK VDDP 2 2 L71
VDDP/DC 68
57 +LAN_PCIEVDD 1 2 +1.2V_LAN
SMB_DATA BLM18AG601SN1D_2P
VDDC 5 1 1
13 +1.2V_LAN C993 C994
VDDC
VDDC 20
4 34 0.1U_0402_16V4Z
GPIO_0(SERIAL_DO) VDDC 2 2
VDDC 55
B SPROM_WP 4.7U_0805_10V4Z B
7 GPIO_1(SERIAL_DI) VDDC 60 L72
8 36 +LAN_BIASVDD 1 2 +3V_LAN 20mil
GPIO_2 BIASVDD L73
30 +LAN_PCIEPLLVDD BLM18AG601SN1D_2P
PCIE_PLLVDD +LAN_AVDD
9 UART_MODE PCIE_VDD/PLL 27 1 1 2 +3V_LAN
33 +LAN_PCIEVDD C995 1 1 BLM18AG601SN1D_2P
PCIE_VDD C996 C997
38 0.1U_0402_16V4Z
LAN_XTALI AVDD/DC 2
21 XTALI AVDD/AVDDL 45 +LAN_AVDDL 0.1U_0402_16V4Z
2 2
AVDD/DC 52
XTALO 22 0.1U_0402_16V4Z
XTALO
AVDDL 39 +LAN_AVDDL
If BCM5788,R150 0 ohm AVDDL/T1_P 44 LAN_MIDI1+ (25) 20mil L74
R1075 1 2 16 46
REG_GND/S_IDDQ AVDDL/T2_P LAN_MIDI2+ (25)
0_0402_5% 51 +LAN_AVDDL +LAN_AVDDL 1 2 +1.2V_LAN
+LAN_PCIEVDD AVDDL BLM18AG601SN1D_2P
24 PCIE_GND/VDD E- PAD 69 1 1
C998 C999

BCM5784MKML_QFN68 0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z

20mil L75
LAN_XTALI +LAN_GPHYPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_2P
XTALO C1000 C1001
1

0.1U_0402_16V4Z
R1076 2 2
200_0402_1% 4.7U_0805_10V4Z

A A
2

Y6
1 2 LAN_XTALO

1 25MHZ_20P 1
Place closed to Pin2 & Pin59
C1002 C1003
27P_0402_50V8J 27P_0402_50V8J
2 2 Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29
SCHEMATIC,MB A3806
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 23 of 43
5 4 3 2 1
 5 4 3 2 1

+MXM_B+
PCIE_MTX_C_GRX_N[0..15] PM@ L67
(9) PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
160mil(4A) 1 2
FBMA-L11-201209-221LMA30T_0805
B+
(9) PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15] PM@ 1
2 160mil(4A)
(9) PCIE_GTX_C_MRX_N[0..15] 2 L68 C958
FBMA-L11-201209-221LMA30T_0805 PM@
PCIE_GTX_C_MRX_P[0..15] 1 1
(9) PCIE_GTX_C_MRX_P[0..15] 1
C959 C960 0.1U_0603_25V7K
PM@ +5VS
D +3VS D
680P_0603_50V7K 68P_0402_50V8J
2 2 PM@

1 1 1
+3VS C410 C380 C180
PM@ PM@ PM@
TH_OVERT# R79 1 PM@ 2 10K_0402_5% 4.7U_0805_10V4Z 10U_0805_6.3V6M
+MXM_B+ +MXM_B+ VGA_PWRGD R77 1 PM@ 10K_0402_5% 2 2 2
JMXM2A 2
VGA_HDMI_CEC R80 1 @ 2 10K_0402_5% (Reserved) 0.1U_0402_16V4Z
1 2 VGA_DISABLE# R78 1 @ 2 10K_0402_5% (Reserved)
PWR_SRC PWR_SRC VGA_WAKE# R82 1 @ 10K_0402_5% (Reserved)
3 PWR_SRC PWR_SRC 4 2
5 PWR_SRC PWR_SRC 6
7 PWR_SRC PWR_SRC 8
9 PWR_SRCE1 E2 PWR_SRC 10
11 PWR_SRC PWR_SRC 12 JMXM2B
13 PWR_SRC PWR_SRC 14
15 PWR_SRC PWR_SRC 16 163 GND GND 162
17 18 2 PM@ 1 R110 +3VS PCIE_GTX_C_MRX_N2 165 164 PCIE_MTX_C_GRX_N2
PWR_SRC PWR_SRC 10K_0402_5% PCIE_GTX_C_MRX_P2 PEX_RX2# PEX_TX2# PCIE_MTX_C_GRX_P2
167 PEX_RX2 PEX_TX2 166
AC_BATT# 2 1 169 168
EC_ACIN (20,31) PCIE_GTX_C_MRX_N1 GND GND PCIE_MTX_C_GRX_N1
19 GND GND 20 171 PEX_RX1# PEX_TX1# 170
21 22 D1 PM@ PCIE_GTX_C_MRX_P1 173 172 PCIE_MTX_C_GRX_P1
GND GND CH751H-40PT_SOD323-2 PEX_RX1 PEX_TX1
23 GND GND 24 175 GND GND 174
25 26 2 1 PCIE_GTX_C_MRX_N0 177 176 PCIE_MTX_C_GRX_N0
GND GND PCIE_GTX_C_MRX_P0 PEX_RX0# PEX_TX0# PCIE_MTX_C_GRX_P0
27 GND GND 28 179 PEX_RX0 PEX_TX0 178
29 E3 E4 30 R117 181 180
GND GND 0_0402_5% CLK_PCIE_VGA# GND GND VGA_CLKREQ#
31 GND GND 32 (15) CLK_PCIE_VGA# 183 PEX_REFCLK# PEX_CLK_REQ# 182 VGA_CLKREQ# (15)
33 34 @ CLK_PCIE_VGA 185 184 PLTRST_VGA#
GND GND (15) CLK_PCIE_VGA PEX_REFCLK PEX_RST# PLTRST_VGA# (18)
35 36 187 186 VGA_DDC_DATA VGA_DDC_DATA (16)
GND GND GND VGA_DDC_DAT VGA_DDC_CLK
+5VS 37 38 VGA_PRSNT_R (20) (Pull-UP 10K 189 188 VGA_DDC_CLK (16)
5V PRSNT_R# VGA_WAKE# RSVD VGA_DDC_CLK VGA_CRT_VSYNC
39 5V WAKE# 40 at PCH) 191 RSVD VGA_VSYNC 190 VGA_CRT_VSYNC (16)
100mil(2.5A, 5VIA) 41 42 VGA_PWRGD VGA_PWRGD (31) 193 192 VGA_CRT_HSYNC VGA_CRT_HSYNC (16)
5V PWR_GOOD RSVD VGA_HSYNC
43 5V PWR_EN 44 VGA_ON (30) 195 RSVD GND 194
C VGA_CRT_R C
45 5V RSVD 46 197 RSVD VGA_RED 196 VGA_CRT_R (16)
LVDS DDC Module have 4.7K 47 48 VGA_TZCLK- 199 198 VGA_CRT_G
GND RSVD (17) VGA_TZCLK- LVDS_UCLK# VGA_GREEN VGA_CRT_G (16)
Pull-UP R76 49 50 VGA_PWRGD/TH_OVERT# Connect to EC VGA_TZCLK+ 201 200 VGA_CRT_B
GND RSVD (17) VGA_TZCLK+ LVDS_UCLK VGA_BLUE VGA_CRT_B (16)
0_0402_5% 51 52 203 202
GND RSVD AC_BATT# GND GND VGA_TXCLK-
1 @ 2 53 GND PWR_LEVEL 54 205 LVDS_UTX3# LVDS_LCLK# 204 VGA_TXCLK- (17)
55 56 TH_OVERT# TH_OVERT# (31) 207 206 VGA_TXCLK+ VGA_TXCLK+ (17)
VGA_DISABLE# PEX_STD_SW# TH_OVERT# R75 1 LVDS_UTX3 LVDS_LCLK
57 VGA_DISABLE# TH_ALERT# 58 2 +3VS 209 GND GND 208
59 60 0_0402_5% PM@ (17) VGA_TZOUT2- VGA_TZOUT2- 211 210
(17) ENVDD PNL_PWR_EN TH_PWM LVDS_UTX2# LVDS_LTX3#
61 62 (17) VGA_TZOUT2+ VGA_TZOUT2+ 213 212
(9,31) ENABLT PNL_BL_EN GPIO0 LVDS_UTX2 LVDS_LTX3
(17) VGA_PNL_PWM 63 PNL_BL_PWM GPIO1 64 215 GND GND 214
VGA_HDMI_CEC 65 66 (17) VGA_TZOUT1- VGA_TZOUT1- 217 216 VGA_TXOUT2- VGA_TXOUT2- (17)
HDMI_CEC GPIO2 D_EC_SMB_DA1 VGA_TZOUT1+ LVDS_UTX1# LVDS_LTX2# VGA_TXOUT2+
67 DVI_HPD SMB_DAT 68 (17) VGA_TZOUT1+ 219 LVDS_UTX1 LVDS_LTX2 218 VGA_TXOUT2+ (17)
(17) I2CC_SDA I2CC_SDA 69 70 D_EC_SMB_CK1 SYSTEM 221 220
I2CC_SCL LVDS_DDC_DAT SMB_CLK VGA_TZOUT0- GND GND VGA_TXOUT1-
(17) I2CC_SCL 71 LVDS_DDC_CLK GND 72 (17) VGA_TZOUT0- 223 LVDS_UTX0# LVDS_LTX1# 222 VGA_TXOUT1- (17)
73 74 (17) VGA_TZOUT0+ VGA_TZOUT0+ 225 224 VGA_TXOUT1+ VGA_TXOUT1+ (17)
GND OEM HDA_BITCLK_VGA (19) LVDS_UTX0 LVDS_LTX1
(19) HDA_RST_VGA# 75 OEM OEM 76 HDA_SDOUT_VGA (19) 227 GND GND 226
R122 33_0402_5%
1 PM@ 2 77 78 229 228 VGA_TXOUT0- VGA_TXOUT0- (17)
(19) HDA_SDIN3 OEM OEM HDA_SYNC_VGA (19) DP_C_L0# LVDS_LTX0#
79 80 231 230 VGA_TXOUT0+ VGA_TXOUT0+ (17)
(26) SPDIF_MXM OEM OEM DP_C_L0 LVDS_LTX0
+3VS 1 R125 2 1 R129 2 81 OEM GND 82 233 GND GND 232
@ 10K_0402_5% 36K_0402_5% @ 83 84 PCIE_MTX_C_GRX_N15 235 234
PCIE_GTX_C_MRX_N15 GND PEX_TX15# PCIE_MTX_C_GRX_P15 DP_C_L1# DP_D_L0#
85 PEX_RX15# PEX_TX15 86 237 DP_C_L1 DP_D_L0 236
PCIE_GTX_C_MRX_P15 87 88 239 238
PEX_RX15 GND PCIE_MTX_C_GRX_N14 GND GND
89 GND PEX_TX14# 90 241 DP_C_L2# DP_D_L1# 240
PCIE_GTX_C_MRX_N14 91 92 PCIE_MTX_C_GRX_P14 243 242
PCIE_GTX_C_MRX_P14 PEX_RX14# PEX_TX14 DP_C_L2 DP_D_L1
93 PEX_RX14 GND 94 245 GND GND 244
95 96 PCIE_MTX_C_GRX_N13 247 246
PCIE_GTX_C_MRX_N13 GND PEX_TX13# PCIE_MTX_C_GRX_P13 DP_C_L3# DP_D_L2#
97 PEX_RX13# PEX_TX13 98 249 DP_C_L3 DP_D_L2 248
PCIE_GTX_C_MRX_P13 99 100 251 250
PEX_RX13 GND PCIE_MTX_C_GRX_N12 GND GND
101 GND PEX_TX12# 102 253 DP_C_AUX# DP_D_L3# 252
PCIE_GTX_C_MRX_N12 103 104 PCIE_MTX_C_GRX_P12 255 254
PCIE_GTX_C_MRX_P12 PEX_RX12# PEX_TX12 DP_C_AUX DP_D_L3
105 PEX_RX12 GND 106 257 RSVD GND 256
107 108 PCIE_MTX_C_GRX_N11 259 258
PCIE_GTX_C_MRX_N11 GND PEX_TX11# PCIE_MTX_C_GRX_P11 RSVD DP_D_AUX#
109 PEX_RX11# PEX_TX11 110 261 RSVD DP_D_AUX 260
B PCIE_GTX_C_MRX_P11 111 112 263 262 B
PEX_RX11 GND PCIE_MTX_C_GRX_N10 RSVD DP_C_HPD
113 GND PEX_TX10# 114 265 RSVD DP_D_HPD 264
PCIE_GTX_C_MRX_N10 115 116 PCIE_MTX_C_GRX_P10 267 266
PCIE_GTX_C_MRX_P10 PEX_RX10# PEX_TX10 RSVD RSVD
117 PEX_RX10 GND 118 269 RSVD RSVD 268
119 120 PCIE_MTX_C_GRX_N9 271 270
PCIE_GTX_C_MRX_N9 GND PEX_TX9# PCIE_MTX_C_GRX_P9 RSVD RSVD
121 PEX_RX9# PEX_TX9 122 273 RSVD GND 272
PCIE_GTX_C_MRX_P9 123 124 275 274
PEX_RX9 GND PCIE_MTX_C_GRX_N8 RSVD DP_B_L0#
125 GND PEX_TX8# 126 277 RSVD DP_B_L0 276
PCIE_GTX_C_MRX_N8 127 128 PCIE_MTX_C_GRX_P8 279 278
PCIE_GTX_C_MRX_P8 PEX_RX8# PEX_TX8 RSVD GND
129 PEX_RX8 GND 130 281 GND DP_B_L1# 280
131 132 PCIE_MTX_C_GRX_N7 (25) VGA_DVI_TXD2- 283 282
PCIE_GTX_C_MRX_N7 GND PEX_TX7# PCIE_MTX_C_GRX_P7 DP_A_L0# DP_B_L1
133 PEX_RX7# PEX_TX7 134 (25) VGA_DVI_TXD2+ 285 DP_A_L0 GND 284
PCIE_GTX_C_MRX_P7 135 136 287 286
PEX_RX7 GND PCIE_MTX_C_GRX_N6 GND DP_B_L2#
137 GND PEX_TX6# 138 (25) VGA_DVI_TXD1- 289 DP_A_L1# DP_B_L2 288
PCIE_GTX_C_MRX_N6 139 140 PCIE_MTX_C_GRX_P6 (25) VGA_DVI_TXD1+ 291 290
PCIE_GTX_C_MRX_P6 PEX_RX6# PEX_TX6 DP_A_L1 GND
141 PEX_RX6 GND 142 293 GND DP_B_L3# 292
143 144 PCIE_MTX_C_GRX_N5 (25) VGA_DVI_TXD0- 295 294
PCIE_GTX_C_MRX_N5 GND PEX_TX5# PCIE_MTX_C_GRX_P5 DP_A_L2# DP_B_L3
145 PEX_RX5# PEX_TX5 146 (25) VGA_DVI_TXD0+ 297 DP_A_L2 GND 296
PCIE_GTX_C_MRX_P5 147 148 299 298
PEX_RX5 GND PCIE_MTX_C_GRX_N4 GND DP_B_AUX#
149 GND PEX_TX4# 150 (25) VGA_DVI_TXC- 301 DP_A_L3# DP_B_AUX 300
PCIE_GTX_C_MRX_N4 151 152 PCIE_MTX_C_GRX_P4 (25) VGA_DVI_TXC+ 303 302
PCIE_GTX_C_MRX_P4 PEX_RX4# PEX_TX4 DP_A_L3 DP_B_HPD
153 PEX_RX4 GND 154 305 GND DP_A_HPD 304 HDMI_DET (25)
155 156 PCIE_MTX_C_GRX_N3 (25) VGA_DVI_SDATA 307 306 +3VS
PCIE_GTX_C_MRX_N3 GND PEX_TX3# PCIE_MTX_C_GRX_P3 DP_A_AUX# 3V3
157 PEX_RX3# PEX_TX3 158 (25) VGA_DVI_SCLK 309 DP_A_AUX 3V3 308
PCIE_GTX_C_MRX_P3 159 160 (20) VGA_PRSNT_L 310 40mil(1A)
PEX_RX3 GND (Pull-UP 10K at PCH) PRSNT_L#
161 GND
311 GND GND 312

JAE_MM70-314-310B1-1 JAE_MM70-314-310B1-1
+3VS +3VS

+3VS
1

A R84 A
PM@ PM@
10K_0402_5% R83
2

10K_0402_5%
G

1 3 D_EC_SMB_DA1
(31,36) SMB_EC_DA1
Place closed to Pin2 & Pin59
D

Q69
2N7002_SOT23
Security Classification Compal Secret Data Compal Electronics, Inc.
2

PM@
G

Issued Date 2007/09/29 Title

D_EC_SMB_CK1 2007/09/29 Deciphered Date
(31,36) SMB_EC_CK1 1 3 SCHEMATIC,MB A3806
D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Q70 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2N7002_SOT23 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
PM@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 24 of 43
5 4 3 2 1
 5 4 3 2 1

DVI_TXC-_R 1 2 C_DVI_R_TXC-
R1026 0_0402_5%
Need Check (17) DVI_TXC- 1 2 DVI_TXC-_R WCM-2012-900T_0805
R1019 GM@ 0_0402_5% 4 3
+HDMI_5V_OUT DVI_TXC+_R 4 3
DDC to HDMI CONN 3.3V Level (17) DVI_TXC+ 1 2
@
+3VS R1020 GM@ 0_0402_5%
1 2 DVI_TXD0-_R 1 2
(17) DVI_TXD0- 1 2

2.2K_0402_5%
R1021 GM@ 0_0402_5%

1
PM@ 1 2 DVI_TXD0+_R L64
(17) DVI_TXD0+
R203 R201 R1022 GM@ 0_0402_5%
+3VS R550 1 PM@ 2 4.7K_0402_5% PM@ 2.2K_0402_5% 1 2 DVI_TXD1-_R DVI_TXC+_R 1 2 C_DVI_R_TXC+
(17) DVI_TXD1-

5
PM@ R1023 GM@ 0_0402_5% R1027 0_0402_5%
1 2 DVI_TXD1+_R
(17) DVI_TXD1+

2
(24) VGA_DVI_SCLK 4 3 DVI_SCLK_L R1024 GM@ 0_0402_5%
D 1 2 DVI_TXD2-_R DVI_TXD0-_R 1 2 C_DVI_R_TXD0- D
(17) DVI_TXD2-
Q68B R1025 GM@ 0_0402_5% R1028 0_0402_5%

2
2N7002DW-T/R7_SOT363-6 1 2 DVI_TXD2+_R
(17) DVI_TXD2+ WCM-2012-900T_0805
R1034 GM@ 0_0402_5%
(24) VGA_DVI_SDATA 1 6 DVI_SDATA_L 4 3
4 3
Q67A PM@ @
2N7002DW-T/R7_SOT363-6 Place closed to JHDMI1 1 2
R551 1 PM@ 1 2
+3VS 2 4.7K_0402_5%
FCM2012CF-800T06_2P L65
PM@
DVI_SDATA_L 1 2 DVI_SDATA DVI_TXD0+_R 1 2 C_DVI_R_TXD0+
L25 R1029 0_0402_5%

FCM2012CF-800T06_2P
DVI_SCLK_L 1 2 DVI_SCLK DVI_TXD1-_R 1 2 C_DVI_R_TXD1-
L27 PM@ R1030 0_0402_5%

WCM-2012-900T_0805
1 1
C677 C678 4 3
PM@ 4 3
10P_0402_50V8J 10P_0402_50V8J @
PM@ 2 2
1 2
1 2
HDMI Connector L63

DVI_TXD1+_R 1 2 C_DVI_R_TXD1+
R1031 0_0402_5%
+HDMI_5V_OUT
F2 D64
CONN@
JHDMI1 +HDMI_5V_OUT 2 1 1 2 +5VS R1043 L31 DVI_TXD2-_R 1 2 C_DVI_R_TXD2-
HP_DETECT 19 W=40mils 1 PM@ MBK1608221YZF_2P R1032 0_0402_5%
HP_DET 1.1A_6VDC_FUSE HDMI_DET
C +HDMI_5V_OUT 18 +5V SS1040_SOD123 (24) HDMI_DET 1 2 1 2 HP_DETECT C
17 C957 10K_0402_5% PM@ WCM-2012-900T_0805
DVI_SDATA DDC/CEC_GND 0.1U_0402_16V4Z
(17) DVI_SDATA 16 SDA 1 PM@ 4 4 3 3

1
DVI_SCLK 2
(17) DVI_SCLK 15 SCL
14 D9 C679 @
Reserved 220P_0402_50V7K
13 CEC BAV99-7-F_SOT23-3 1 1 2 2
C_DVI_R_TXC- 2
12 CK- GND 20 Need Check @ L66
11 CK_shield GND 21
C_DVI_R_TXC+ 10 22

3
C_DVI_R_TXD0- CK+ GND DVI_TXD2+_R C_DVI_R_TXD2+
9 D0- GND 23 1 2
8 R1033 0_0402_5%
C_DVI_R_TXD0+ D0_shield
7 D0+
C_DVI_R_TXD1- 6 D1- DVI_DET HP_DETECT
5 (17) DVI_DET 1 2 +3VS
C_DVI_R_TXD1+ D1_shield R1014 0_0402_5%
4 D1+

1
C_DVI_R_TXD2- 3 GM@
D2-
2 D2_shield
C_DVI_R_TXD2+ 1 D63
D2+ @ SKS10-04AT_TSMA
SUYIN_100042MR019SX53ZL 2
Need CHECK
JRJ45
C_DVI_R_TXD2- R1113 1 PM@ 2 499_0402_1% LAN_ACTIVITY# 12
C_DVI_R_TXD2+ R1056 1 PM@ (23) LAN_ACTIVITY# Yellow LED-
2 499_0402_1% (24) VGA_DVI_TXD2-
VGA_DVI_TXD2- C741 PM@ 2 1 0.1U_0402_16V7K DVI_TXD2-_R
VGA_DVI_TXD2+ C747 PM@ 2 1 0.1U_0402_16V7K DVI_TXD2+_R 2 1 11
(24) VGA_DVI_TXD2+ +3V_LAN Yellow LED+
C_DVI_R_TXD1- R1108 1 PM@ 2 499_0402_1% R308 1K_0402_5%

220P_0402_50V7K
C_DVI_R_TXD1+ R1107 1 PM@ 2 499_0402_1% VGA_DVI_TXD1- C809 PM@ 2 1 0.1U_0402_16V7K DVI_TXD1-_R 1 RJ45_MIDI3- 8 Guide Pin
(24) VGA_DVI_TXD1- PR4-
VGA_DVI_TXD1+ C765 PM@ 2 1 0.1U_0402_16V7K DVI_TXD1+_R
(24) VGA_DVI_TXD1+ C440
C_DVI_R_TXD0- R1109 1 PM@ 2 499_0402_1% RJ45_MIDI3+ 7
C_DVI_R_TXD0+ R1110 1 PM@ VGA_DVI_TXD0- DVI_TXD0-_R PR4+
2 499_0402_1% (24) VGA_DVI_TXD0-
C811 PM@ 2 1 0.1U_0402_16V7K
VGA_DVI_TXD0+ C810 PM@ 2 DVI_TXD0+_R 2 RJ45_MIDI1-
(24) VGA_DVI_TXD0+ 1 0.1U_0402_16V7K 6 PR2-
B C_DVI_R_TXC- R1111 1 PM@ 2 499_0402_1% B
C_DVI_R_TXC+ R1112 1 PM@ 2 499_0402_1% VGA_DVI_TXC- C813 PM@ 2 1 0.1U_0402_16V7K DVI_TXC-_R RJ45_MIDI2- 5
(24) VGA_DVI_TXC- PR3-
VGA_DVI_TXC+ C812 PM@ 2 1 0.1U_0402_16V7K DVI_TXC+_R
(24) VGA_DVI_TXC+
RJ45_MIDI2+ 4 PR3+
0_0402_5% RJ45_MIDI1+ 3 PR2+
1

+HDMI_5V_OUT 1 2 2 RJ45_MIDI0- 2
R1035 G PR1-
SHLD2 14
PM@ Q12 S RJ45_MIDI0+ 1
3

2N7002_SOT23 PR1+
SHLD1 13
PM@ LAN_LINK# 10
(23) LAN_LINK# Green LED-

+3V_LAN 2 1 9 Green LED+

T105 R3 1K_0402_5%
1 24 SUYIN_100073FR012G101ZL
LAN_MIDI0+ TCT1 MCT1 RJ45_MIDI0+
(23) LAN_MIDI0+ 2 TD1+ MX1+ 23 conn@
(23) LAN_MIDI0- LAN_MIDI0- 3 22 RJ45_MIDI0- 1 2
TD1- MX1-
4 TCT2 MCT2 21
(23) LAN_MIDI1+ LAN_MIDI1+ 5 20 RJ45_MIDI1+ C138
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- 220P_0402_50V7K
(23) LAN_MIDI1- 6 TD2- MX2- 19
7 TCT3 MCT3 18
(23) LAN_MIDI2+ LAN_MIDI2+ 8 17 RJ45_MIDI2+
LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2-
(23) LAN_MIDI2- 9 TD3- MX3- 16
10 15 RJ45_GND 1 2 LANGND 40mil
LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+
(23) LAN_MIDI3+ 11 TD4+ MX4+ 14 2 2 1 1
(23) LAN_MIDI3- LAN_MIDI3- 12 13 RJ45_MIDI3- C87
TD4- MX4- 1000P_1206_2KV7K C316 C233
350uH_GSL5009-1 LF 4.7U_0805_10V4Z
LAN_ACTIVITY# C463 1 1 2 2
1 2
C945 100P_0402_50V8J
68P_0402_50V8J C946 0.1U_0402_16V4Z
@ 68P_0402_50V8J
1

A A
LAN_LINK# 1 2
1 1 1 1 R921 R922 C947
C863 C859 C864 C858 75_0402_1% 75_0402_1% 68P_0402_50V8J
@
2

0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
R916 R915
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
2

RJ45_GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Place close to TCT pin AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
40mil DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 25 of 43
5 4 3 2 1
 A B C D E

+VDDA
Codec Regulator

1
R1077
R121
10K_0402_5% 0_0805_5%
2 1
+5VS

2
1 2 U58 +VDDA
C1004 1U_0402_6.3V4Z

1
4.7U_0805_10V4Z +VDDA
R1078 C1005
1 VIN VOUT 5 4.75v
1 10K_0402_5% C1006 2 1
EC Beep R1079
0.1U_0402_16V4Z GND C1007
(31) BEEP# C1008 1 2 1 2 3 4 C1010 4.7U_0805_10V4Z

2
1U_0402_6.3V4Z C1009 SHDN# BP @
560_0402_5% 2 1
1 2 MONO_IN +5VS 1 2
R1080 10K_0402_5% @ 0.22U_0402_6.3V6K
1U_0402_6.3V4Z APL5151-475BC-TRL_SOT23-5
PCI Beep

1
C 1 2
C1011 1 R1081 Q73
(20) SB_SPKR 2 1 2 2
1U_0402_6.3V4Z 560_0402_5% B R1082 2.4K_0402_1%
E 2SC2411K_SOT23 HD Audio Codec

3
1

1
D67 L76
@
R1083 10mil 0.1U_0402_16V4Z +3VS_DVDD
MBK1608121YZF_0603
1 2 +3VS
10K_0402_5% RB751V_SOD323
1 1 1
2

C1012 C1014 PM@

2
C1013 +MIC2_VREFO
R118
2 2 2
0_0805_5%
0.1U_0402_16V4Z

1
10U_0805_10V4Z

1
+AVDD_AC97 R472
L77 40mil R119
2.2K_0402_5%
0.1U_0402_16V4Z 10mil For EMI AMIC@
+VDDA 1 2
FBM-L11-160808-800LMT_0603
2 1 +1.5VS 15mil
1 1 1

2
C1017 C1018 1 1 GM@ DMIC_CLK_R INT_MIC
C1016 C1015 C1022 0_0805_5% R470 AMIC@FBM-11-160808-700T_0603
2 2
DMIC_DATA_R 1
10U_0805_10V4Z 2 2
<BOM Structure> 2 0.1U_0402_16V4Z 10U_0805_10V4Z R471 AMIC@FBM-11-160808-700T_0603 C535
0.1U_0402_16V4Z 2 2 AMIC@

25

38

9
U59 220P_0402_50V7K
2

DVDD
AVDD1

AVDD2

DVDD_IO
14 35 AMP_LEFT
LINE2_L LOUT1_L AMP_LEFT (27)
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT (27)
R1085 1 2 MIC2_C_L 16 39
INT_MIC MIC2_L LOUT2_L
1 2INT_MIC_R C1019 4.7U_0805_6.3V6K
1 2 MIC2_C_R 17 41 0.01U_0402_16V7K
MIC2_R LOUT2_R C143
1K_0402_1% C1020 4.7U_0805_6.3V6K
LINE_L 2 R930 1 1 2 23 45 1 2
(27) LINE_L LINE1_L SPDIFO2 SPDIF_MXM (24)
1K_0603_1% C1037 4.7U_0805_6.3V6K
LINE_R 2 R931 1 1 2 24 46 DMIC_CLK PM@
(27) LINE_R LINE1_R DMIC_CLK1/2
1K_0603_1% C1038 4.7U_0805_6.3V6K R1086 C1023
18 LINE1_VREFO NC 43
10_0402_5% 10P_0402_50V8J
20 LINE2_VREFO DMIC_CLK3/4 44 2 1 1 2 For EMI
+MIC2_VREFO 19 MIC2_VREFO
BITCLK 6 HDA_BITCLK_CODEC (19)
MIC1_L 1 2 MIC1_C_L 21
(27) MIC1_L MIC1_L
C1024 4.7U_0805_6.3V6K
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2
(27) MIC1_R MIC1_R SDATA_IN HDA_SDIN0 (19)
C1025 4.7U_0805_6.3V6K R1087 33_0402_5%
MONO_IN 12 37 WOOFER_MONO

3
PCBEEP_IN MONO_OUT
29
WOOFER_MONO (27)
DMIC Conn. 3
CBP
(19) HDA_RST#_CODEC 11 RESET# 2
31 1 2 C1026 +3VS
CPVEE 2.2U_0603_6.3V4Z C1027 0_0603_5% JP41
(19) HDA_SYNC_CODEC 10 SYNC 10mil
MIC1_VREFO 28 +MIC1_VREFO_L 2.2U_0603_6.3V4Z 1 1
1 DMIC_CLK DMIC_CLK_R
(19) HDA_SDOUT_CODEC 5 SDATA_OUT 2 2
HP_R DMIC_DATA R482 DMIC@ DMIC_DATA_R
(27) LINEIN_PLUG#
R602 1 2 10K_0402_1% DMIC_DATA 2 GPIO0/DMIC_DATA1/2
HPOUT_R 32 HP_R (27) C1026 C1027 must close R481 DMIC@
3
4
3
4
G1
G2
5
6
3 30 0_0603_5%
(27) MIC_PLUG# 2 1 SENSE A 13
GPIO1/DMIC_DATA3/4
SENSE A
CBN
10mil
codec ACES_88266-04001

2
(27) HP_PLUG# 1 2 R1089 20K_0402_1% SENSE B 34 SENSE B VREF 27 CODEC_VREF CONN@
R1088 5.11K_0402_1% 1 1 D68
1 2 47 40 C1028 PJSOT05C_SOT23-3 1 2
(31) CODEC_EAPD R1090 0_0402_5% EAPD JDREF C1029 <BOM Structure>
(27) SPDIF 48 SPDIFO1 HPOUT_L 33 HP_L
HP_L 1
(27)
0.1U_0402_16V4Z 10U_0805_10V4Z C675
2 2
220P_0402_50V8J

1
2 1
4 DVSS1 AVSS1 26 @
7 42 R1091 C676
DVSS2 AVSS2 220P_0402_50V8J
2

ALC272X-GR_LQFP48_7X7 20K_0402_1% @

Sense Pin Impedance Codec Signals 1

R1092
2
0_0805_5%
1
R1102
2
0_0805_5%
AGND
DGND
39.2K PORT-A (PIN 39, 41)
1 2 1 2
R1093 0_0805_5% R1101 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K PORT-C (PIN 23, 24) R1094 0_0805_5% R1103 0_0805_5%

4 4
5.1K PORT-D (PIN 35, 36)
GND GNDA GND GNDA
39.2K PORT-E (PIN 14, 15)

20K PORT-F (PIN 16, 17)

SENSE B Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-G (PIN 43, 44) Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
5.1K PORT-H (PIN 45, 46) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 26 of 43
A B C D E
 A B C D E

Int. Speaker Conn.

+5VS 20mil JP3
SPKL+ R619 1 2 0_0603_5% SPK_L+ 1
SPKL- R618 0_0603_5% SPK_L- 1
1 2 2 2
SPKR+ R617 1 2 0_0603_5% SPK_R+ 3 5
SPKR- R616 0_0603_5% SPK_R- 3 G1
1 2 4 4 G2 6
1 1

2
C1030 ACES_88266-04001
C1031 D70 D71 CONN@
10U_0805_10V4Z 0.1U_0402_16V4Z PJSOT05C_SOT23-3 PJSOT05C_SOT23-3
1 2 2 <BOM Structure> <BOM Structure> 1

1
+5VS +5VS

HP_PLUG#
HP_PLUG# (26)

2
2
+5VS R626
R625 100K_0402_5%

1
D
100K_0402_5%

2
U60

16
15
2

1 1
6
R1095 R1097 G

1
3
100K_0402_5%
S D Q38
100K_0402_5% S

VDD
PVDD1
PVDD2

3
G
@ 2 SPDIF_PLUG# 2
G 2N7002_SOT23

1
D Q39 Q40 S

3
1 2 7 2 GAIN0 AO3413_SOT23-3 2N7002_SOT23
C1032 RIN+ GAIN0
+5VSPDIF
0.47U_0603_16V4Z 3 GAIN1
GAIN1

(26) AMP_RIGHT 1 2 1 2AMP_C_RIGHT 17 RIN-

2
C1033 R1096 0_0402_5% 18 SPKR+
0.47U_0603_16V4Z ROUT+ R1099
100K_0402_5%
ROUT- 14 SPKR- LINE Out/Headphone Out
1 2 9

1
C1034 LIN+ R1098 @
0.47U_0603_16V4Z
LOUT+ 4 SPKL+ 100K_0402_5% 2007/12/07 S/PDIF Out JACK @
2
(26) AMP_LEFT 1 2 1 2 AMP_C_LEFT 5 LIN- 20mil D60 1
C1035 R1100 0_0402_5% 8 SPKL- 2 2 3
2 0.47U_0603_16V4Z LOUT- C759 C760 2
C950
PJDLC05_SOT23~D
330P_0402_50V7K 330P_0402_50V7K 1 2 JHP1
1 1
1 1
12 HP_R 1 2 HPOUT_R_1
1 2 HPOUT_R_2 0.1U_0402_16V4Z 2
NC (26) HP_R R633 56.2_0603_1% L41 FBM-11-160808-700T_0603 2
Keep 10 mil width HP_L HPOUT_L_1 1 HPOUT_L_2
BYPASS 10 (26) HP_L 1 2 2 3 3
EC_MUTE 19 R634 56.2_0603_1% L42 FBM-11-160808-700T_0603
(31) EC_MUTE SHUTDOWN
2 4 4

2
GND5
GND1
GND2
GND3
GND4

C1036 D65 SPDIF_PLUG#

Check with EC 0.47U_0603_16V4Z PJSOT05C_SOT23-3
5 5
1 <BOM Structure> 8 8
21
20
13
11
1

TPA6017A2PWP_TSSOP20 DRIVE
+5VSPDIF 9

1
9 IC
10 10 GND 6
GND 7
SPDIF
(26) SPDIF
SINGA_2SJ-A373-H01
1 <BOM Structure>
C762
100P_0402_50V8J
2
LINE-IN JACK
2 @ PJDLC05_SOT23~D
D61 1
3 JM70@
+5VS JLINE1
LINEIN_PLUG# 5
(26) LINEIN_PLUG#
3 3
4
JM70@ L43 JM70@
C671
1 2
Gain = 5.1dB(BTL Mode) (26) LINE_R
LINE_R 1 2 LINE_R_R 3
C652 JM70@ FBM-11-160808-700T_0603 6
10U_0805_10V4Z LINE_L 1 2 LINE_L_R 2
2 1
0.1U_0603_25V7K
Fc(low)= 2KHz (26) LINE_L
L44 FBM-11-160808-700T_0603 1

SM05_SOT23
R519 1.8K_0402_5% JM70@ 1 1

2
1 2 SINGA_2SJ-S351-015
JM70@ C763 C764
@ R467 220P_0402_50V7K 220P_0402_50V7K
C656 0.01U_0603_50V7K 100K_0402_5% JM70@ 2 2 JM70@
1 2 1 2
Fc(high)= 482Hz JM70@
+5VS
D66

1
+5VS U44 +MIC1_VREFO_L +MIC1_VREFO_L @
1K_0402_1% JM70@ 6 VDD SHUTDOWN# 1 EC_MUTE
EC_MUTE (31)
MIC2_R_1 Left
R517 R518
30mil

2
WOOFER_MONO 1 2 1 2 1 2 WOOFER_IN- 4 5 JP17 MIC2_L_1
(26) WOOFER_MONO
C654
JM70@ 4.7K_0402_1%
WOOFER_IN+ 3
IN- Vo+ WOOFER+
WOOFER-
1 1
D28 D29
@
MIC JACK
1 IN+ Vo- 8 2 2 RB751V-40TE17_SOD323-2 2

2
0.33U_0603_16V4Z RB751V-40TE17_SOD323-2 D72 1 PJDLC05_SOT23~D
JM70@ C651 JM70@ 2 7 D69 3

1
BYPASS GND PJSOT05C_SOT23-3
3 G1
2
0.068U_0603_16V7K <BOM Structure>
4 G2

1
SINGA_2SJ-S351-015
2 APA3011XA-TRL_MSOP8 ACES_88266-02001 MIC_PLUG# 5
(26) MIC_PLUG#

1
JM70@ CONN@ R645 R647
C653 2.2K_0402_5% 2.2K_0402_5% 4
2.2U_0603_6.3V4Z

2
1 JM70@ MIC1_R_L MIC2_R_1
(26) MIC1_R 1 2 1 2 3
R1002 1K_0603_1% L45 FBM-11-160808-700T_0603 6
1 2 MIC1_L_L 1 2 MIC2_L_1 2
(26) MIC1_L
R1003 1K_0603_1% L46 FBM-11-160808-700T_0603 1
4 4
1 1
JMIC1
C770 C771
220P_0402_50V7K 220P_0402_50V7K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 27 of 43
A B C D E
 5 4 3 2 1

+REG18_PLL 2 1 +REG18
+3VS R362 0_0402_5%

2
D U14 D

@ R365 2 1 1
100K_0402_5% C381 0.1U_0402_16V4Z AV_PLL
3 NC
Internal 200K Pull UP 7

1
+XDPWR_SDPWR_MSPWR NC
+XDPWR_SDPWR_MSPWR 9 CARD_3V3
+3VS 11 D3V3
RST#
Vender suggesttion 1
R364
2
0_0402_5%
33 D3V3 VREG 10 1 2
1 1 1 C383 MS_D4 22 C341 1U_0402_6.3V4Z
C382 0.1U_0402_16V4Z 30
C384 @ NC
8 3V3_IN
1U_0402_6.3V4Z RST# 44
2 4.7U_0603_6.3V6K 2 2 MODE_SEL RST#
45 MODE_SEL
XTLO 47 43 XDCLE
XTLI XTLO XD_CLE_SP19 XDCE#
48 XTLI XD_CE#_SP18 42
41 XDALE
USB20_N4 XD_ALE_SP17 SDDAT2_XDRE#
(20) USB20_N4 4 DM SD_DAT2/XD_RE#_SP16 40
USB20_P4 5 39 SDDAT3_XDWE#
(20) USB20_P4 DP SD_DAT3/XD_WE#_SP15
14 38 XD_RDY
(33) 5IN1_LED# GPIO0 XD_RDY_SP14
37 SDDAT4_XDWP#_MSD7
SD_DAT4/XD_WP#/MS_D7_SP13 SDDAT5_XDD0_MSD6
SD_DAT5/XD_D0/MS_D6_SP12 35
34 SDCLK_XDD1_MSCLK_L 2 1 SDCLK_XDD1_MSCLK
SD_CLK/XD_D1/MS_CLK_SP11 SDDAT6_XDD7_MSD3 R317 0_0402_5%
SD_DAT6/XD_D7/MS_D3_SP10 31
29 MS_INS#
MODE_SEL MS_INS#_SP9 SDDAT7_XDD2_MSD2
SD_DAT7/XD_D2/MS_D2_SP8 28
27 SDDAT0_XDD6_MSD0
SD_DAT0/XD_D6/MS_D0_SP7 XDD3_MSD1
1 SD_DAT1/XD_D3/MS_D1_SP6 26
1 25 XDD5_MSBS
R366 XD_D5_SP5 XDD4_SDDAT1
XD_D4/SD_DAT1_SP4 23
@ C385 0_0402_5% 21 SDCD
47P_0402_50V8J SD_CD#_SP3 SDWP
SD_WP_SP2 20
2 XDCD
19
2

C XD_CD#_SP1 C
EEDI 18

2 1 2 13 XTAL_CTR 2 1 +3VS
R363 6.19K_0402_1% RREF XTAL_CTR R284 0_0603_5%
MS_D5 24
12 DGND
32 DGND EEDO 15
EECS 16
CARD_AGND 6 17
AGND EESK SD_CMD
46 AGND SD_CMD 36

2
RTS5159-GR_LQFP48_7X7
R361
0_0603_5%

1
(15) CLK_SD_48M 1 2
R368 0_0402_5%

@
1 2 XTLI +CARDPWR
C386 6P_0402_50V8D
1

+CARDPWR +CARDPWR
R367
33_0402_5% JREAD1 1 1 1
1

3 XD-VCC SD-VCC 21
@ Y3 28 C476 C342 C482
2

B 12MHZ_16PF_6X12000012 SDDAT5_XDD0_MSD6 MS-VCC 0.1U_0402_16V4Z B

1 32 XD-D0
SDCLK_XDD1_MSCLK SDCLK_XDD1_MSCLK 2 2 2
10 7 IN 1 CONN 20
2

C387 SDDAT7_XDD2_MSD2 XD-D1 SD_CLK SDDAT0_XDD6_MSD0

9 XD-D2 SD-DAT0 14
22P_0402_50V8J XDD3_MSD1 8 12 XDD4_SDDAT1 10U_0805_10V4Z 0.1U_0402_16V4Z
2 @ XDD4_SDDAT1 XD-D3 SD-DAT1 SDDAT2_XDRE#
7 XD-D4 SD-DAT2 30
1 2 XTLO XDD5_MSBS 6 29 SDDAT3_XDWE#
C389 6P_0402_50V8D SDDAT0_XDD6_MSD0 XD-D5 SD-DAT3 SDDAT4_XDWP#_MSD7
5 XD-D6 SD-DAT4 27
SDDAT6_XDD7_MSD3 SDDAT5_XDD0_MSD6
EMI 4 XD-D7 SD-DAT5 23
18 SDDAT6_XDD7_MSD3
SDDAT3_XDWE# SD-DAT6 SDDAT7_XDD2_MSD2
34 XD-WE SD-DAT7 16
SDDAT4_XDWP#_MSD7 33 25 SD_CMD
XDALE XD-WP SD-CMD SDCD
35 XD-ALE SD-CD-SW 1
XDCD 40
XD_RDY XD-CD SDWP
39 XD-R/B SD-WP-SW 2
SDDAT2_XDRE# 38
XDCE# XD-RE
37 XD-CE
XDCLE 36 26 SDCLK_XDD1_MSCLK
XD-CLE MS-SCLK SDDAT0_XDD6_MSD0
MS-DATA0 17 1
11 15 XDD3_MSD1
+XDPWR_SDPWR_MSPWR 7IN1 GND MS-DATA1 SDDAT7_XDD2_MSD2 C477
31 7IN1 GND MS-DATA2 19
+CARDPWR 24 SDDAT6_XDD7_MSD3 @ 22P_0402_50V8J
MS-DATA3 MS_INS# 2
MS-INS 22
XDD5_MSBS
40~60 mil 1 2 41
MS-BS 13
R369 0_0603_5% 7IN1 GND
42 7IN1 GND
2

1
TAITW_R015-A10-LM_NR
R4 C388
100K_0402_5% 0.1U_0402_16V4Z
2
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 28 of 43
5 4 3 2 1
 5 4 3 2 1

D D

C C

ON board HS PORT +USB_VCCB

+5VALW
+5VALW
+USB_VCCB
U37 JUSB3 JP54
1 GND OUT 8 1 VCC 1 1
C569 0.1U_0402_16V4Z 2 7 USB20_N6 2 2
IN OUT (20) USB20_N6 USB20_P6 D- 2
2 1 3 IN OUT 6 (20) USB20_P6 3 D+ 3 3
4 EN# FLG 5 4 GND (22,34) SYSON# 4 4
R206 5
TPS2061DRG4_SO8 100K_0402_5% USB20_N0 5
5 GND1 (20) USB20_N0 6 6
1 2 +3VALW 6 USB20_P0 7
SYSON# GND2 (20) USB20_P0 7
8 8
USB20_N6 SUYIN_020173MR004S512ZL USB20_N1 9
USB_OC#6 (20) (20) USB20_N1 9
USB20_P6 USB20_P1 10
(20) USB20_P1 10
11 11
(20) USB_OC#0 12 12
3

13 G1
14 G2
D18
PJDLC05_SOT23~D E&T_3703-E12N-03R

B +USB_VCCB B
1

W=60mils
1
1000P_0402_50V7K 2 PORT
1 1
C814 +
150U_B2_6.3VM_R45M C816 C815
2 2 2
0.1U_0402_16V4Z

+5VALW

JP55
1 1 GND 9
2 2
(22,34) SYSON# 3 3
4 4
USB20_N2 5
(20) USB20_N2 USB20_P2 5
(20) USB20_P2 6 6
7 7
(20) USB_OC#2 8 8 GND 10

E-T_3703-E08N-03R

A
1 PORT A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 29 of 43
5 4 3 2 1
 5 4 3 2 1

BIOS H1 H2 H3 H4 H5 H6 H7 H8 H9
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

+3VALW
@ @ @ @ @ @ @ @ @

1
C551 1 2 0.1U_0402_16V4Z
<BOM Structure>

H10 H11 H12

(31) FSEL# U35 H_3P0 H_3P0 H_3P0
+3VALW 4.7K_0402_5% 1 8
R935 1 SPI_WP# CE# VDD R443 1
2 3 WP# SCK 6 2 0_0402_5% SPI_CLK (31)
D R936 1 SPI_HOLD# 7 R445 1 D
2 5 2 0_0402_5% FWR# (31)
@ @ @

1
4.7K_0402_5% HOLD# SI R442 1
4 VSS SO 2 2 0_0402_5% FRD# (31)
MX25L8005M2C-15G_SOP8

ENE suggestion SPI Frequency over 66MHz

SST: 50MHz H17 H18 H23 H26 H32 H25 H27
MXIC: 70MHz H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2

ST: 40MHz
@ @ @ @ @ @ @

1
H40 H41 H35 H38 H39
H_3P2 H_3P2 H_3P2 H_3P2 H_3P2

@ @ @ @ @

1
VS_ON will be drived by EC reserve Power ON Circuit H42
H_3P0
H43
H_3P0
+1.5V
@ @

1
+3VALW

2
C 0.1U_0402_16V4Z C

+3VALW 2 R925
C1039 U45F 10K_0402_5%
1

SN74LVC14APWLE_TSSOP14
R1399

1
47K_0402_5% 1 2N7002W-T/R7_SOT323-3
14

Q41
D58
2

1
CH751H-40PT_SOD323-2 D
P

SYSON 1 2 13 12 2
(31,34,40) SYSON I O DDR3_SM_PWROK (7)
1 G
G

C1040 3 S
0.1U_0603_25V7K
7

H19 H20 H21 H22

H_4P2 H_4P2 H_4P2 H_4P2
+3VALW +3VALW
@ @ @ @

1
U45A U45B
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14
P

1 I O 2 3 I O 4
G

H31 H28
B H_4P1N H_4P1X4P6N B
7

@ @

1
+3VS
+3VALW +3VALW
1

R919
47K_0402_5% U45C U45D FD1 FD2 FD3 FD4
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
P

P
2

5 6 9 8 1 2 @ @ @ @
VS_ON (39)

1
I O I O R920
2
1

D C856 0_0402_5% FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

SUSP 2
For +VCCP
(34,41) SUSP
7

G
Q57 S 1
3

2N7002_SOT23
0.1U_0402_16V4Z

+3VALW +3VS
0.1U_0402_16V4Z
+3VS 2 PM@
2

C1041 U45E
1

PM@ SN74LVC14APWLE_TSSOP14 R926

R1400 PM@ 10K_0402_5%
A 100K_0402_5% 1 2N7002W-T/R7_SOT323-3 A
14

Q44
2

D
P

11 I O 10 2 VGA_ON (24)
1 G
G

C1042 S
3
1

D 0.1U_0603_25V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
7

SUSP 2 PM@ PM@

PM@ 2
G
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
Q58 S
SCHEMATIC,MB A3806
3

2N7002_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 30 of 43
5 4 3 2 1
 +3VALW_EC +3VALW_EC
+3VALW_EC

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
1 1 1 1 1
Ra Ra
JM70@ R466 R450
C446 C447 C448 C449 C450 +3VALW +3VALW_EC +EC_AVCC 100K_0402_5% 100K_0402_5%

2
2 2 2 2 2 R451 Project ID M/B_ID
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 Rb Rb

1
0_0805_5% 1 1
C462 R468 C451 R452
100K_0402_5% 0_0402_5%

111
125
+5VALW +3VS 0.1U_0402_16V4Z JV70@ 0.1U_0402_16V4Z

22
33
96

67
9
U18 2 2

2
SMB_EC_DA1 R453 1 2 4.7K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R454 1 2 4.7K_0402_5% VCC 3.3V+/-5%
SMB_EC_DA2 R455 1 2 2.2K_0402_5%
SMB_EC_CK2 R456 1 2 2.2K_0402_5% Ra 100K+/-5%
GATEA20 1 21 INV_PWM
(19) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM (17)
KB_RST# 2 23 BEEP# Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
(19) KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (26)
SIRQ 3 26
(20) SIRQ SERIRQ# FANPWM1/GPIO12 FAN_PWM (4)
@ LPC_FRAME# 4 27 ACOFF 0 0 0V 0V 0V
(19) LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (38)
C452 @ R457 (19) LPC_AD3 LPC_AD3 5
LPC_AD2 LAD3 C453 1 ECAGND
1 2 1 2 (19) LPC_AD2 7 LAD2 PWM Output 2 1 8.2K+/-5% 0.216V 0.250V 0.289V
33_0402_5% (19) LPC_AD1 LPC_AD1 8 63 BATT_TEMP 100P_0402_50V8J
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (36)
15P_0402_50V8J LPC_AD0 BATT_OVP
(19) LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP (38) 2 18K+/-5% 0.436V 0.503V 0.538V
ADP_I/AD2/GPIO3A 65 ADP_I (38)
CLK_PCI_EC 12 AD Input 66 M/B_ID 3 33K+/-5% 0.712V 0.819V 0.875V
(15) CLK_PCI_EC PCICLK AD3/GPIO3B
PCI_RST# 13 75 VGA_PWRGD VGA_PWRGD (24)
R458 1 (18) PCI_RST# ECRST# PCIRST#/GPIO05 AD4/GPIO42 Project ID
+3VALW 2 37 ECRST# SELIO2#/AD5/GPIO43 76 4 56K+/-5% 1.036V 1.185V 1.264V
1 2 47K_0402_5% EC_SCI# 20 @ 2 1
(20) EC_SCI# SCI#/GPIO0E PGD_IN (42)
0.1U_0402_16V4Z 38 R486 0_0402_5% 5 100K+/-5% 1.453V 1.650V 1.759V
C454 CLKRUN#/GPIO1D
(20) PM_CLKRUN# 1 2 PM_CLKRUN#_R DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG
DAC_BRIG (17)
R943 0_0402_5% 70 EN_FAN1 6 200K+/-5% 1.935V 2.200V 2.341V
EN_DFAN1/DA1/GPIO3D EN_FAN1 (4)
CY@ DA Output 71 IREF
IREF/DA2/GPIO3E IREF (38)
2 1 SMB_EC_CK2 KSI0 55 72 7 NC 2.500V 3.300V 3.300V
(33) ESB_EC_CK2 KSI0/GPIO30 DA3/GPIO3F Calibrate# (38)
R474 0_0402_5% KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
(33) ESB_EC_DA2 2 CY@ 1 SMB_EC_DA2 KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE
EC_MUTE (27)
+5VS
R475 0_0402_5% KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B MEDIA_LED#_IN (33)
KSI5 60 85 TP_CLK R462 1 2 4.7K_0402_5%
ENE@ KSI6 KSI5/GPIO35 PSCLK2/GPIO4C BT_LED# EC_ACIN (20,24)
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 BT_LED# (33)
(33) ESB_EC_CK2 2 1ESB_EC_CK2_R KSI7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK
TP_CLK (32)
TP_DATA R463 1 2 4.7K_0402_5%
R477 0_0402_5% KSO0 39 88 TP_DATA
KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 3S/4S# TP_DATA (32)
40 KSO1/GPIO21 3S/4S# (38)
(33) ESB_EC_DA2 2 ENE@ 1ESB_EC_DA2_R KSO2 41 KSO2/GPIO22
4.7K_0402_5%
R478 0_0402_5% KSO3 42 97 2 R465 1 @ select SPI ROM or LPC ROM
KSO4 KSO3/GPIO23 SDICS#/GPXOA00 65W90W#
43 KSO4/GPIO24 SDICLK/GPXOA01 98 65W90W# (38)
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
MINI1_LED# (22)
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# (33)
R479 0_0402_5% KSO7 46 SPI Device Interface
KSO7/GPIO27
(33) EC_I2C_INT2 2 1 EC_I2C_INT2_R KSO8 47 KSO8/GPIO28
KSO9 48 119 FRD#
KSO9/GPIO29 SPIDI/RD# FRD# (30)
KSO10 49 120 FWR#
KSO10/GPIO2A SPIDO/WR# FWR# (30)
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK (30)
2 1 EC_I2C_INT1_R KSO12 51 128 FSEL#
(33) EC_I2C_INT1
R480 0_0402_5% KSO13 52
KSO12/GPIO2C
KSO13/GPIO2D
SPICS# FSEL# (30) 2007/12/07
KSO14 53
KSO15 KSO14/GPIO2E EC_RCIRRX C861 100P_0402_50V8J
54 KSO15/GPIO2F CIR_RX/GPIO40 73
Pin 74--ENE RST(R) or CY INT(R) KSO16 81 74 EC_I2C_INT1_R BATT_OVP 2 1
KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41 C862 100P_0402_50V8J
82 89
Pin16--ENE RST(L) or CY INT(L) KSO17/GPIO49 FSTCHG/SELIO#/GPIO50
90
FSTCHG (38)
ACIN 2 1
BATT_CHGI_LED#/GPIO52 BATT_GRN_LED# (33)
91 CAPS_LED#
SMB_EC_CK1 CAPS_LED#/GPIO53 CAPS_LED# (33)
(24,36) SMB_EC_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# (33)
SMB_EC_DA1 78 93
+3VS (24,36) SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED (33)
R135 SMB_EC_CK2 79 SM Bus 95 SYSON
(4,32) SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON (30,34,40)
4.7K_0402_5% SMB_EC_DA2 80 121 VR_ON 47K_0402_5%
(4,32) SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (42)
1 2 ESB_EC_CK2_R AC_IN/GPIO59 127 ACIN
ACIN (35,38)
KSO1 1 R585 2 +3VALW For EMI
2 2 1
1 2 ESB_EC_DA2_R R469 10K_0402_5% KSO2 1 2 +3VALW CP1
C458 SLP_S3# 6 100 EC_RSMRST# R586 KSI6 1 8
(20) SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# (20)
4.7K_0402_5% 15P_0402_50V8J SLP_S5# 14 101 47K_0402_5% KSI7 2 7
1 (20) SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# (20)
R128 ENE@ EC_SMI# 15 102 EC_ON KSI5 3 6
(20) EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON (32)
EC_I2C_INT2_R 16 103 CP7 KSI4 4 5
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# (20)
ESB_EC_CK2_R 17 104 PM_PWROK KSO16 1 8
ESB_EC_DA2_R SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PM_PWROK (20) KSO17 100P_1206_8P4C_50V8
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# (17) 2 7
@ R485 0_0402_5% TH_OVERT# 19 GPIO 106 WL_OFF# 3 6 CP2
(24) TH_OVERT# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# (22)
2 1 25 107 4 5 KSO0 1 8
(7) MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10 HPD_7318_R_EC (17)

1
28 108 KSO1 2 7
(33) MEDIA_LED#_OUT (4) FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 HPD_7318_EC (17)
BT_ON# 29 100P_1206_8P4C_50V8 KSO2 3 6
(32) BT_ON# FANFB2/GPIO15
UTX 30 R489 KSO3 4 5
(22) UTX URX EC_TX/GPIO16 SLP_S4# 10K_0402_5%
31 110
(22) URX
(32) ON/OFF
ON/OFF 32
EC_RX/GPIO17 PM_SLP_S4#/GPXID1
112 ENABLT
SLP_S4# (20)
ENABLT (9,24)
2007/12/07 100P_1206_8P4C_50V8

2
PWR_SUSP_LED34 ON_OFF/GPIO18 ENBKL/GPXID2
(33) PWR_SUSP_LED PWR_LED#/GPIO19 GPXID3 114 CODEC_EAPD (26)
NUM_LED# 36 GPI 115 THERM_SCI# (Left) JKB1 CP3
(33) NUM_LED# NUMLED#/GPIO1A GPXID4 THERM_SCI# (20)
116 SUSP# KSO4 1 8
EC DEBUG port C455 GPXID5
117 PWRBTN_OUT#
SUSP# (34,41)
KSO0 26 28 KSO5 2 7
GPXID6 PWRBTN_OUT# (20) KSO0 G2
CONN@ 15P_0402_50V8J 118 EC_PME# KSO1 25 27 KSO6 3 6
JP26 CRY1 GPXID7 KSO2 KSO1 G1 KSO7
1 2 122 XCLK1 24 KSO2 4 5

4.7U_0805_10V4Z
1 123 124 KSO3 23
1 +3VALW XCLK0 V18R KSO3
2 URX 1 KSO4 22 100P_1206_8P4C_50V8
2 Y5 KSO4
1

AGND

C478
3 UTX KSO5 21 CP4
GND
GND
GND
GND
GND

3 @ KSO6 KSO5 KSO8

4 4 2 NC IN 1 20 KSO6 1 8
R476 KSO7 19 KSO9 2 7
ACES_85205-0400 20M_0402_5% KB926QFD2_LQFP128 2 KSO8 KSO7 KSO10
3 4 18 3 6
11
24
35
94
113

69

NC OUT KSO9 KSO8 KSO11

17 4 5
2

32.768KHZ_12.5P_MC-306 KSO10 KSO9

16 KSO10
KSO11 15 100P_1206_8P4C_50V8
CRY2 KSO12 KSO11
1 2
+3VALW_EC For KB926 C0 reversion KSO13
14 KSO12 CP5
13 KSO13
C456 KSO14 12 KSI3 1 8
ECAGND

15P_0402_50V8J KSO15 KSO14 KSI2

11 KSO15 2 7
1

KSO16 10 KSI1 3 6
+EC_AVCC R85 KSO17 KSO16 KSI0
9 KSO17 4 5
0_0603_5% KSI0 8
KSI1 KSI0 100P_1206_8P4C_50V8
7 KSI1
R86 KSI2 6 CP6
2

KSI3 KSI2 KSO12

1 2 1 2 5 KSI3 1 8
C457 0.1U_0402_16V4Z 0_0603_5% KSI4 4 KSO13 2 7
<BOM Structure> KSI5 KSI4 KSO14
3 KSI5 3 6
<BOM Structure> <BOM Structure> KSI6 2 KSO15 4 5
R473 KSI7 KSI6
1 KSI7
EC_PME# 2 1 100P_1206_8P4C_50V8
0_0402_5% EC_LAN_PME# (23)
(Right) ACES_88747-2601

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 31 of 43
 A B C D E

Power Button pin1

+3VALW
pin1
TOP Side
1 2
R578 @ 10K_0603_5%

2
+3VALW
1 2 R580
R579 @ 10K_0603_5% 1
1 100K_0402_5% GM@ C705 1
20mil
ON/OFF switch Bottom Side JMDC1 1 2 +1.5V

1
D44 R969 0_0402_5% 1U_0603_10V4Z
2
2 ON/OFF (31) 1 GND1 RES0 2 1 2
ON/OFFBTN# 1 3 4 R962 0_0402_5%
(33) ON/OFFBTN# (19) HDA_SDOUT_MDC IAC_SDATA_OUT RES1
3 51ON# 5 6
51ON# (35) GND2 3.3V +3VALW
(19) HDA_SYNC_MDC 7 8 PM@
DAN202UT106_SC70-3 HDA_SDIN1_MDC IAC_SYNC GND3
(19) HDA_SDIN1 1 2 9 IAC_SDATA_IN GND4 10
R583 33_0402_5% 11 12
(19) HDA_RST_MDC# IAC_RESET# IAC_BITCLK HDA_BITCLK_MDC (19)

1
R584

GND
GND
GND
GND
GND
GND
1
2 0_0402_5%
C704 D45
ACES_88018-124G

13
14
15
16
17
18

2
1000P_0402_50V7K RLZ20A_LL34 SP01000AT00 CONN@ 1
1
HDA MDC Conn. C706

2
Connector for MDC Rev1.5
22P_0402_50V8J
2

1
D
EC_ON 2 Q36
(31) EC_ON
G
2

S 2N7002_SOT23

3
R581

10K_0402_5%
1

+3VS

2 2
+3VS
1
C698 C699
0.1U_0402_16V4Z
0.1U_0402_16V4Z

1 1U_0603_10V4Z

3
2
S
C5
G
1 2 2 Q33
(31) BT_ON#
@ SA00001Z700 R575 10K_0402_5% AO3413_SOT23
2 D

1
U2
1 8 SMB_EC_CK2 SMB_EC_CK2 (4,31) W=40mils
VDD SCLK

(4) THRMDA_2
THRMDA_2
C4
THRMDA_2 2 D+ SDATA 7 SMB_EC_DA2
SMB_EC_DA2 (4,31) BT 1
+BT_VCC

1
THRMDC_2 1 2 THRMDC_2 3 6 1 R209 2 +3VS C702 C703
(4) THRMDC_2 D- ALERT/THERM2
2200P_0402_50V7K 10K_0402_5% R576
@ 4 5 @ 4.7U_0805_10V4Z 300_0603_5%
THERM GND 2 0.1U_0402_16V4Z

2
Address:100_1100 ADT7421ARMZ-REEL_MSOP8
@

1
D
2 Q34 USB20_P8
G 2N7002_SOT23 USB20_N8
S

2
T/P Board TP_DATA
TP_CLK
D62
PJDLC05_SOT23~D
3

3 3

1
+5VS D25 +BT_VCC
CONN@
PSOT24C-LF-T7_SOT23-3
ACES_87213-0800G
8 8 GND 10
7
1

USB20_P8 7
(20) USB20_P8 6 6
1 @ (20) USB20_N8
USB20_N8 5 5
C459 4 4
(22) WLAN_BT_DATA 1 2 WLAN_BT_DATA_R 3 3
0.1U_0402_16V4Z R996
1 @ 0_0402_5%
2 WLAN_BT_CLK_R 2
2 (22) WLAN_BT_CLK 2
JP7 R997@ 0_0402_5% 1 9
1 GND
1 1
2 JP37
2
3 3 TP_DATA (31)
4 4 TP_CLK (31)
5 5
6 6
7 BTN_R
7
8 8 1 1
9 @ @
9 C460 C461
10 10
13 11 100P_0402_50V8J
G13 11 BTN_L 2 2
14 G14 12 12
100P_0402_50V8J
ACES_87151-1207G Left Right
SW6 JM70@ SW5 JM70@
EVQPLHA15_4P EVQPLHA15_4P
BTN_L 3 1 BTN_R 3 1

4 2 4 2
4 4
5
6

5
6

Left Right
SW3 JV70@ SW4 JV70@
EVQPLHA15_4P EVQPLHA15_4P
BTN_L 3 1 BTN_R 3 1 Security Classification Compal Secret Data Compal Electronics, Inc.
4 2 4 2 Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
SCHEMATIC,MB A3806
5
6

5
6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 32 of 43
A B C D E
 5 4 3 2 1

LED/B
Need Check POWER BOARD
MEDIA_LED#_OUT_R

+3VS

1
Q45
JP12
1
JM70 JV70
DTC114EKA_SC59-3 1 MEDIA_LED#_OUT_R
2 2
3 3 BT_LED# (31)
2 4 1.HDD
(31) MEDIA_LED#_OUT
7
4
5
CAPS_LED# (31) 1.HDD
D 7 5 NUM_LED# (31) D
8 8 6 6
2.B/T 2.BT_LED JP45
ACES_85201-0605 1 ON/OFFBTN# (32)

3
CONN@ 3.CAP LED 1
4.NUM LED 2 2
1
4.NUM_LED 3.CAP LED
C951
0.1U_0402_16V4Z
G1 3
G2 4
2
ACES_88266-02001

+3VS

5
U38
2 SATA_LED#

P
B SATA_LED# (19)
MEDIA_LED#_IN 4
(31) MEDIA_LED#_IN Y
A 1 5IN1_LED# (28)

G
NC7SZ08P5X_NL_SC70-5

PWR_LED# PWR_SUSP_LED#
C CAP Sansor right CAP Sansor lift C
1

Q42 Q43
DTC114EKA_SC59-3 DTC114EKA_SC59-3
10K 10K
(31) PWR_LED 2 (31) PWR_SUSP_LED 2
10K 10K
3

+5VS +3VS
+5VS +3VS
JP2
Compal Footprint R483 0_0402_5% 300_0402_5% R459 6 6 8 8 JP6
R484 0_0402_5% 300_0402_5% R460 5 7 R487 0_0402_5% 300_0402_5% R461 6 8
ESB_EC_CK2 2 5 7 R488 0_0402_5% 300_0402_5% R464 6 8
(31) ESB_EC_CK2 1 1 2 4 4 5 5 7 7
ESB_EC_DA2 2 1 1 2 3 ESB_EC_CK22 1 1 2 4
(31) ESB_EC_DA2 3 (31) ESB_EC_CK2 4
2 ESB_EC_DA22 1 1 2 3
(31) EC_I2C_INT1 2 (31) ESB_EC_DA2 3
HT-297USD/CB _BLUE/RED_0603 1 1 1 2
1 (31) EC_I2C_INT2 2
C952 1
33P_0402_50V4Z ACES_85201-0605 1
1 1
+5VALW 1 2 4 A 3 PWR_SUSP_LED# CONN@ C954 ACES_85201-0605
R313 453_0402_1% 2 2 33P_0402_50V4Z 33P_0402_50V4Z CONN@
C953 C955
PWR_LED# 2 2 33P_0402_50V4Z
+5VALW 2 B 1
R370 560_0402_5%
LED1
Color Need Confirm
HT-297UD/CB _BLUE/RED_0603

+3VALW
B BATT_AMB_LED# B
+5VALW 1 2 4 A 3 BATT_AMB_LED# (31)
R373 453_0402_1%

2
+5VALW 2 B 1 BATT_GRN_LED# BATT_GRN_LED# (31)
R374 560_0402_5%

VDD
<BOM Structure> LED2
Lid Switch A3212ELHLT-T_SOT23W-3
OUTPUT 3 LID_R

HT-297UD/CB _BLUE/AMB_0603
(Hall Effect Switch)

GND
JV70@

+5VALW 1 2 4 3 PWR_SUSP_LED# +3VALW U28

1
A
R376 453_0402_1%

+5VALW 2 B 1 PWR_LED#
R377 240_0402_5%

1
LED3
Color Need Confirm 2

2
JM70@ C430 R285
0.1U_0402_16V4Z 47K_0402_5%

VDD
1

2
3 LID_R 1 2 LID_SW# (31)
OUTPUT D30
Power BTN MB Side Needs Pull-Up

GND
ON/OFFBTN# JM70@ CH751H-40PT_SOD323-2
1
C429
U27
SW

1
A3212ELHLT-T_SOT23W-3 10P_0402_50V8J
2
3

A A
SMT1-05_4P D21
SW1 PJSOT24C_SOT23~D
JM70@
1 3
1

2 4 ON/OFFBTN#
ON/OFFBTN# (32)
Need change P/N
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
6
5

CLRP5 CLRP4
SHORT PADS SHORT PADS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 33 of 43

5 4 3 2 1
 5 4 3 2 1

+5VALW to +5VS Transfer

+3VALW to +3VS Transfer
+5VALW +5VS +3VALW
+3VS
U20 0.1U_0402_16V4Z U21 0.1U_0402_16V4Z
8 D S 1 8 D S 1
C644 1 7 2 1 7 2
+VSB 10U_0805_10V4Z D S +VSB C637 D S
6 D S 3 1 1 6 D S 3 1 1
5 4 10U_0805_10V4Z 5 4 C648 C649
1 D G C645 C646 D G

1
D 2 SI4800DY_SO8 10U_0805_10V4Z 2 SI4800DY_SO8 10U_0805_10V4Z D
R546 2 2 R548 2 2
22K_0402_5% 33K_0402_5%
2

2
RUNON +3VS_GATE R549 1 2 RUNON
@ 0_0402_5%
1 1
1

1
D C647 D C650
SUSP 2 Q27 0.1U_0603_25V7K SUSP 2 Q28 0.1U_0603_25V7K
G G
2N7002_SOT23 2 2N7002_SOT23 2
S S
3

3
+5VALW +5VALW +3VALW

+1.5V to +1.5VS Transfer

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1
C C139 C141 C142 +1.5V C
+1.5VS
2 2 2 U22 0.1U_0402_16V4Z
8 D S 1
1 7 D S 2
+VSB C682 6 3
D S 1 1
10U_0805_10V4Z 5 4 C692 C693
D G

1
2 SI4800DY_SO8 10U_0805_10V4Z
R556 2 2
33K_0402_5%

2
+1.5VS_GATE

1
1

1
D Q29 C680 R597
SUSP 2 0.1U_0603_25V7K 300K 0402 +-5%
G 2N7002W-T/R7_SOT323-3 @
S 2

2
1029 DEL

B B

+5VALW

+5VALW

1
R544
Discharge circuit

1
47K_0402_5% R545

2
10K_0402_5%
(22,29) SYSON# SYSON#

2
+5VS +3VS +1.5V +1.5VS +VCCP +0.75V SUSP
(30,41) SUSP

1
D D
1

2 2 Q26
(30,31,40) SYSON (31,41) SUSP#
R498 R499 R500 R501 R502 R503 G G
2N7002_SOT23

2
Q49 S S

3
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% R532 2N7002_SOT23 R547
100K_0402_5%
2

10K_0402_5%

1
6

Q9A Q9B Q10A Q10B Q11A Q11B

SUSP 2 SUSP 5 SYSON# 2 SUSP 5 SUSP 2 SUSP 5

1

2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401668 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 29, 2009 Sheet 34 of 43
5 4 3 2 1
 A B C D

1 1

DC231000500 VIN PR1

1M_0402_1%
1 2
SINGA_2DC-G756I200 PL1 VIN VIN
SMB3025500YA_2P VS
1 DC_IN_S1 1 2

1
@PR2
@ PR2 PR3
G 2 10K_0402_5% 84.5K_0402_1%
G PR6

8
3 PC3 PR4 PR5 22K_0402_5%

2
PC1 PC2 100P_0402_50V8J PC4 0_0402_5% 10K_0402_1% 3 1 2

P
PJP1 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1 2 1

2
(31,38) ACIN 0

20K_0402_1%
- 2

1
G

PR7
PU1A

1
PC5
0.1U_0603_25V7K
LM358DT_SO8 PC6

4
PR8 PD1 1000P_0402_50V7K

2
10K_0402_5% GLZ4.3B_LL34-2

2
2

2
PR9
10K_0402_5%
1 2
RTCVREF

2 2

Vin Dectector
Min. Typ Max.
- PBJ1 + H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
+RTCBATT

ML1220T13RE
45@

PJ1 PJ2
+3VALWP 2 2 1 1 +3VALW +1.8VSP 2 2 1 1 +1.8V
JUMP_43X118 JUMP_43X118

VIN
PJ3 PJ4
2

+5VALWP 2 2 1 1 +5VALW +0.75VSP 2 2 1 1 +0.75V

PD2
LL4148_LL34-2 JUMP_43X118 JUMP_43X79

PD3
1

LL4148_LL34-2
BATT+ 2 1 PJ5
1

3 3

PJ6
PR10 PR11 2 1 +1.5VP 2 1 +1.5V
PQ1 68_1206_5% 68_1206_5% +VSBP 2 1 +VSB 2 1
TP0610K-T1-E3_SOT23-3 JUMP_43X39 JUMP_43X118
PR12
2

200_0603_5%
CHGRTCP 1 2 N1 3 1
VS PJ7 PJ8
+1.05VSP 2 2 1 1 +VCCP 2 2 1 1
1

PR13 PC8 JUMP_43X118 JUMP_43X118

100K_0402_1% PC7 0.1U_0603_25V7K
0.22U_1206_25V7K
2

PR14
2

22K_0402_1% PJ9
1 2 2 2 1 1
(32) 51ON#
JUMP_43X118

RTCVREF
1

PR15
PU2 200_0603_5%
PR16 PR17 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
OUT IN
+CHGRTC
1

GND PC10
4
PC9 1U_0805_25V4Z 4

10U_0805_10V4Z 1
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 35 of 43
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 70 degree C
VL
VL
VL
VMB

2
SUYIN_200275MR007G161ZL
@ PL2 PR18
PJP2

1
1 1

SMB3025500YA_2P 100K_0402_1%
1
BATT_S1 1 2 BATT+ PH1 PC11
MAINPWON (37)
100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR19

1
2 100K_0402_1%
3

1
EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR20 PQ2
5

8
1000P_0402_50V7K 0.01U_0402_25V7K 18K_0402_1% DTC115EUA_SC70-3

2
6 PD4
1 2 3

P
7 +
O 1 2 1 2
TM_REF1 2 -

G
PU3A LL4148_LL34-2
LM393DG_SO8

3
2

0.22U_0603_16V7K
PR21 PR22

11.3K_0402_1%
100_0402_1% 100_0402_1%

1
PC14
PR23

1000P_0402_50V7K
PR24
100K_0402_1%
1

2 1 VL

1
PR25

PC15
6.49K_0402_1%

2
2 1 +3VALWP

1
1

PR26
PR27 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP (31)

SMB_EC_CK1 (24,31) PH2 near main Battery CONN :

BAT. thermal protection at 92 degree C
SMB_EC_DA1 (24,31)
Recovery at 56 degree C
VL

2
@ PR28
@PR28
VL 47K_0402_1%
@PR29
@ PR29
47K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
@PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL

B+ 3 1 +VSBP

2
0.22U_1206_25V7K

0.1U_0603_25V7K

PR31
1

8
@ 13.7K_0402_1% @PD5
@ PD5
1

1
PC16

PC17

PR30 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
3 3

PR32 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18
@PC18 @ PR33
@PR33
0.22U_0603_16V7K 15.4K_0402_1%

2
2

PR34
100K_0402_1%

PR35
1

0_0402_5% D
1 2 2 PQ4
(37) SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 36 of 43
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PL11
FBMA-L11-322513-151LMA50T_1210 PR56
0_0805_5%
1 2 1 2
D D

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

PC22

8
7
6
5

1
PC25
PC139 VL

2
0.1U_0402_25V6

PC23

PC24
2

1U_0603_10V6K
PQ6

2
2
PQ5 PC26 AO4466_SO8

4.7U_0603_6.3V6M
AO4466_SO8 0.1U_0603_25V7K 4

1
PC27
4

PC28
1
+5VALWP

3
2
1
PL3

1
2
3
PL4 10UH_SIL1045RA-100PF_4.5A_30%

7
10UH_SIL1045RA-100PF_4.5A_30% PU4 PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5
4.7_1206_5%

PR37
DH3 26 15 DH5
UGATE2 UGATE1

PR36
PR38 PR39 PQ8
0_0402_5%

PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8

BOOT2 BOOT1
2

1 AO4712_SO8 2.2_0603_5%

2
2

2
PR40

63.4K_0402_1%
2.2_0603_5% PC32 4

2
+ PC30 4 PC31

2
680P_0603_50V7K
220U_6.3V_M 0.1U_0603_25V7K 0.1U_0603_25V7K

1
1
680P_0603_50V7K

PR41
LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC33

PC34
3
2
1

2
C + PC35 C

1
2
3
DL3 23 18 DL5 220U_6.3V_M

1
LGATE2 LGATE1
2
10K_0402_1%
2

@ 22
PGND

2
FB3 30 OUT2

10K_0402_1%
PR42

PR43
OUT1 10
VL 32
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN @ PR44 0_0402_5%
SKIP 29 2 1 VL
PR45 0_0402_5%
1 2
20 NC POK2 28
PR46
PD9 100K_0402_1%
1 2 1 2 4 13 SPOK (36)
VS EN_LDO POK1 PR48
2
200K_0402_5%

GLZ5.1B_LL34-2 287K_0402_1%
2

B B
PR47

PC37 14 12 ILM1 2 1
EN1 ILIM1
2

0.22U_0603_25V7K
1

PQ43 27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2

TP0610K-T1-E3_SOT23-3 2 PR49

0_0402_5%
@ PR50 ISL6237IRZ-T_QFN32_5X5 287K_0402_1%

21
1 3 VL 0_0402_5%
806K_0603_1%

PR51
2

1
1

1
PR52

1U_0402_6.3V6K
2VREF_ISL6237 1

PR55 @
2
PC135

47K_0402_5% PR53
PR54 0_0402_5%
+5VALWP Ipeak=8.444A ; Imax=5.91A
1

(36) MAINPWON
2 1 1 2
2VREF_ISL6237 2
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
0.047U_0402_16V7K

0_0402_5%
2

Ilimit=165mV/18m ~ 165mV/15m
1

1
0.047U_0402_16V7K

@
PC38

+3.3VALWP Ipeak=8.444A ; Imax=5.91A =9.167A ~ 11A

PC39

PD12
2

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) 1SS355_SOD323-2

Iocp=Ilimit+Delta I/2
1

Vlimit=(5E-06 * 330K)/10=165mV =10.147A ~ 11.980A

Ilimit=165mV/18m ~ 165mV/15m VS Delta I=1.96A (Freq=400KHz)
=9.167A ~ 11A
A Iocp=Ilimit+Delta I/2 A

=10.134A ~ 11.967A
Delta I=1.934A (Freq=300KHz)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 37 of 43
5 4 3 2 1
 A B C D

B+
PQ10 PQ11
AO4407A_SO8 AO4407A_SO8 PR57
VIN 8 1 1 8 0.015_2512_1%
7 2 2 7 PJ14
6 3 3 6 1 4 2 1 CHG_B+
2 1

1
5 5

2
2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
2 3 JUMP_43X118 PR59
PR58 CHGEN# PC42 100K_0402_1%

2
0.01U_0402_25V7K
3.3_1210_5% 0.01U_0402_25V7K

1
100K_0402_1%

PC43

PC44

PC45

2
1
PC48 PC46

1
2

5
6
7
8

3
2
1
1 1

PC47

PR61
0.1U_0402_16V7K PU5 0.1U_0805_25V7K
1 2 1 28 PVCC 1 2 PQ13
CHGEN PVCC

1
AO4407A_SO8

1
PR60 PR62 /BATDRV 4

2
3.3_1210_5% PC49 @PC51
@PC51 0_0603_5% PQ12
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
2
PR63
340K_0402_1% @PD13
@ PD13 RLZ24B_LL34 ACN 2 26 DH_CHG
ACN HIDRV
1

1 2 ACP 3

3
2
1

5
6
7
8
PC50 ACP PR64

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL5 0.02_2512_1%
2

ACDET ACDRV PH PD8 10UH_PCMB104T-100MS_6A_20%

5 ACDET
2 1 1 2 1 2 1 4
BATT+
Input OVP : 22.3V

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
LL4148_LL34-2 PC52

REGN
2 3

2
Input UVP : 17.26V 0.1U_0603_25V7K PR66

5
6
7
8

1
PC53

PC54

PC55
24751_VREF PR65 @ 4.7_1206_5%
CELLS GND 3 Cell 54.9K_0402_1% ACSET 6 PQ14
ACSET AO4466_SO8
24

2
REGN @
VREF 4 Cell
1
2

1
PC56

680P_0402_50V7K
PR69 1U_0603_10V6K 4

@ PC58
47K_0402_1% @ PR67
@PR67 PC57

2
2

0_0402_5% 0.47U_0603_16V7K
1 2 1 2 7
1

2
PR68 ACOP DL_CHG
23

3
2
1
340K_0402_1% LODRV
CELLS
1

PGND 22
PQ15 OVPSET 8 PC59
OVPSET
1

2 D 2N7002W-T/R7_SOT323-3 0.1U_0402_16V7K 2

2 3S/4S# (31) 1 2
G 9 21 ACOFF (31)
AGND LEARN
2

S
3

1
PR70
54.9K_0402_1% PC60 @PC61
@PC61
24751_VREF CELLS 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector 20

2
SI2301BDS-T1-E3_SOT23-3 CELLS
1

24751_VREF 10
VREF
1

1
PR71 PQ16 PC62
3

1U_0603_10V6K
100K_0402_1% 19 SE_CHG+

2
SRP
CP Point Setting (I_adapter*85%) 11 18 SE_CHG-
2

PQ15_GATE VDAC SRN

2
90W adapter Vacset=3.3*(100K/(64.9K+100K))=2.001V BAT 17
1

1
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A PC64 VADJ 12
0.1U_0603_25V7K VADJ PC63
2

65W adapter Vacset=3.3*(50K/(50K+64.9K))=1.436V 0.1U_0603_25V7K

CC=0.2~3.52A
1

2
ACSET 29
ACGOOD# TP
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 13 ACGOOD ICHG setting IREF=0.77448*Icharge
PR72
17.4K_0402_1%
16 SRSET 2 1
Iref=0.155~3.52A
24751_VREF 24751_VREF /BATDRV 14
SRSET IREF (31)
BATDRV

1
PR73 RTCVREF 24751_VREF

1
200K_0402_1%

10_0603_5% PR74
1
100K_0402_1%

15 1 2 100K_0402_1% @PC65
@PC65
IADAPT
1

2
100K_0402_1%
PR76

PQ15_GATE 0.01U_0402_25V7K

2
PR75

PR77
BQ24751ARHDR_QFN28_5X5 @ PR78
@PR78

2
3 3

100K_0402_1%
1

1
D
2

2 PQ17 PC66
2

1
G SSM3K7002F_SC59-3 100P_0402_50V8J ACIN (31,35)

2
1

PC67 D
S
3

ACOFF 1 2 2 ADP_I (31) 24751_VREF

1

1
VMB D
G VS
0.1U_0402_16V7K S ACGOOD# 2 @ PQ19
3
1
340K_0402_1%

PQ18 PR79 @PR80

@ PR80 G 2N7002W-T/R7_SOT323-3
PR81

0.01U_0402_25V7K

SSM3K7002F_SC59-3 340K_0402_1% 0_0402_5% S

3
1
1 2
2

@PR82
@ PR82
1

PC68

887K_0402_1%
LI-3S :13.5V----BATT-OVP=1.501V
2

@ PQ20
PR83 SI2301BDS-T1-E3_SOT23-3 @PR84
@ PR84
LI-4S :18.0V----BATT-OVP=2.001V
2

2
499K_0402_1% 0_0402_5%
24751_VREF

S
REGN VADJ

D
BATT-OVP=0.1112*VMB 3 1 1 2
2
8

PR85 PU1B

2
10K_0402_1% LM358DT_SO8

G
5
P

2
+

1000P_0402_50V7K
499K_0402_1%
1 2 7 0 @PR86
@ PR86 PR87
(31) BATT_OVP

PC69
6 100K_0402_1% 100K_0402_1%
-
G

PR89
PR90 PR88

2
1

0.01U_0402_25V7K

64.9K_0402_1% 210K_0402_1%
4

1
1

24751_VREF 1 2 ACSET PR91 @ CHGEN#

PC70

105K_0402_1%

2
2
1

1
D D
2

2 2 PQ22
PR92 G G 2N7002W-T/R7_SOT323-3
100K_0402_1% S @ (31) FSTCHG S

3
(31) CALIBRATE#
1

4
PQ21 4
2

PR93 2N7002W-T/R7_SOT323-3
100K_0402_1%
1

D
(31) 65W90W# 2 Charger ADJ Calibrate# PR78 PR84
2

G
PQ23 S
3

2N7002W-T/R7_SOT323-3 4.0V L @ @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title
4.1V L 887K 221K SCHEMATIC,MB A3806
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 38 of 43
A B C D
 5 4 3 2 1

D D

PL12
FBMA-L11-322513-151LMA50T_1210

51117_1.05V_B+ 1 2 B+

4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC71

PC72

PC136

PC137
PQ24 PC138

5
6
7
8
AO4466_SO8 0.1U_0402_25V6

2
PR94 4
300K_0402_5%
PR95 1 2
0_0402_5%
(30) VS_ON 1 2

3
2
1
PR96 PC73 PL6
2.2_0603_1% 0.1U_0603_25V7K 1UH_PCMB103E-1R0MS_20A_20%

15

14
1

1
@PC74
@PC74
PU6 BST_1.05V 1 2BST_1.05V-1 1 2 1 2 +1.05VSP

EN_PSV

TP

VBST
0.1U_0402_16V7K
2

2 13 DH_1.05V
TON DRVH

1
5
6
7
8
3 12 LX_1.05V PR97 1
C VOUT LL PQ25 4.7_1206_5% C

D
D
D
D
VFB=0.75V FDS6670AS_NL_SO8 + PC75
4 V5FILT TRIP 11 +5VALW 330U_D2_2.5VY_R15M

2
5 VFB V5DRV 10
2
4 G

1
6 9 DL_1.05V
PGOOD DRVL

PGND
PR98 PC76

GND

S
S
S
300_0402_5% 680P_0603_50V7K

2
1

18K_0402_1%
1 2 @PC77
@ PC77
+5VALW

3
2
1
1
PR99
47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5

8
1 2 PC78
1

4.7U_0805_10V6K

2
PC79

2
1U_0603_10V6K
2

PR100
7.32K_0402_1%
1 2
1

PR101
18K_0402_1%
2

B B

VFB=0.75V
Vo=VFB*(1+PR100/PR101)=1.055V
Fsw=262KHz

Cout ESR=15m ohm

Rdsonmax=11.5m ohm, Rdsontyp=9m ohm
Ipeak=7.15A, Imax=3.5A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=2.103A
=>1/2DeltaI=1.052A
Vtrip=Rtrip*10uA=9.09K*10uA=0.0909V
Iocpmin=Vtrip/Rdsonmax*1.3+1.052A=7.132A
Iocpmax=Vtrip/Rdsontyp*1.1+1.052A=10.233A
Iocp=7.132A~10.233A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 39 of 43
5 4 3 2 1
 5 4 3 2 1

D D

PJ16
JUMP_43X118
51117_1.5V_B+ 2 2 1 1 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC80

PC81
PQ26

5
6
7
8
AO4466_SO8

2
PR102 4
300K_0402_5%
PR103 1 2
0_0402_5%
(30,31,34) SYSON 1 2

3
2
1
PR104 PC82 PL7
0_0603_1% 0.1U_0603_25V7K 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

15

14
1

1
@PC83
@PC83
PU7 BST_1..5V 1 2BST_1..5V-1 1 2 1 2 +1.5VP

EN_PSV

TP

VBST
0.1U_0402_16V7K
2

C DH_1..5V C
2 TON DRVH 13

1
@

5
6
7
8
3 12 LX_1..5V PR105 1
VOUT LL 4.7_1206_5%

D
D
D
D
VFB=0.75V + PC84
4 V5FILT TRIP 11 +5VALW 330U_6.3V_M

2
5 VFB V5DRV 10
2
4 G

1
6 9 DL_1.5V @
PGOOD DRVL

PGND
PR106 PC85

GND

S
S
S
300_0402_5% PQ27 680P_0603_50V7K

2
1

18K_0402_1%
1 2 @ PC86
@PC86 FDS6670AS_NL_SO8
+5VALW

3
2
1
1
PR107
47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5

8
1 2 PC87
1

4.7U_0805_10V6K

2
PC88

2
1U_0603_10V6K
2

PR108
10K_0402_1%
1 2
1

PR109
10K_0402_1%
2

B B

VFB=0.75V
Vo=VFB*(1+PR108/PR109)=1.5V
Fsw=262KHz

Cout ESR=15m ohm

Rdsonmax=11.5m ohm, Rdsontyp=9m ohm
Ipeak=13.67A, Imax=8A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.930A
=>1/2DeltaI=1.465A
Vtrip=Rtrip*10uA=18K*10uA=0.180V
Iocpmin=Vtrip/Rdsonmax*1.4+1.465A=12.645A
Iocpmax=Vtrip/Rdsontyp*1.2+1.465A=18.131A
Iocp=12.645A~18.131A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 40 of 43
5 4 3 2 1
 5 4 3 2 1

+3VALW
+5VALW

1
PJ17

1
D JUMP_43X79 D

2
1

2
PC89
1U_0402_6.3V6K

1
PC90
4.7U_0805_6.3V6K

2
PU8
6 VCNTL
5 3
PR110 9
VIN
VIN
VOUT
VOUT 4 +1.8VSP
0_0402_5%

22U_0805_6.3V6M
(31,34) SUSP# SUSP# 1 2 8 EN

PC93
7 2

GND
POK FB

1
PR112

2
PC92 PR111 1.5K_0402_1%
1U_0603_10V6K 47K_0402_5% APL5913-KAC-TRL_SO8
2

2
2 PC91

1
0.01U_0402_25V7K

PR113
1.2K_0402_1%

2
C C

+1.5V

PU10
1 VIN VCNTL 6 +3VALW
2 GND NC 5
2

1
B B
1

PC99 3 7 PC100
4.7U_0805_6.3V6K PR117 VREF NC 1U_0603_6.3V6M
1

1K_0402_1% 4 VOUT NC 8 2

9
2

TP
APL5331KAC-TRL_SO8
0.1U_0402_16V7K

PR118 PQ28
+0.75VSP
1

0_0402_5% 2N7002W-T/R7_SOT323-3 D
PC101

(30,34) SUSP 1 2 2 PR119

1

G 1K_0402_1%
2
1

S PC103
3

PC102 10U_0805_6.3V6M
2

0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 41 of 43
5 4 3 2 1
 5 4 3 2 1

+5VS

B+
CPU_VID6 (5) CPU_B+

2
CPU_VID5 (5) PR120 PL8
1_0603_5% FBMA-L18-453215-900LMA90T_1812
CPU_VID4 (5) 2 1
(31) VR_ON

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
CPU_VID3 (5) 1
PR121

1
PC109

PC104
499_0402_1% + PC106
D CPU_VID2 (5) D

PC105
(7,20) DPRSLPVR 1 2 PC108 PQ29 220U_25V_M
CPU_VID1 (5) PC107 2.2U_0603_6.3V6K TPCA8030-H_SOP-ADV8-5

2
5

5
PR122 0_0402_5% 0.022U_0402_16V7K 2

2
(5,7,19) H_DPRSTP# 1 2 CPU_VID0 (5)
PR123 0_0402_5%
1 2

1
PR129 0_0402_5%

PR130 0_0402_5%

PR131 0_0402_5%

PR132 0_0402_5%
CLK_ENABLE#

PR125 0_0402_5%

PR126 0_0402_5%

PR127 0_0402_5%

PR128 0_0402_5%
4 UGATE_CPU1 4
PR124 0_0402_5%
+3VS 1 2 PQ35 @
TPCA8030-H_SOP-ADV8-5
+3VS PL9

3
2
1

3
2
1
1
1U_0603_6.3V6M
PR135 PC111 0.36UH_PCMC104T-R36MN1R17_30A_20%

PC110
1.91K_0402_1%
2.2_0603_1% 0.22U_0603_10V7K
+VCC_CORE
1
BOOT_CPU1 1 2 1 2 1 4

2
2

PR134

1
6.8_1206_5%
PR133 2 3

PR136
499_0402_1%

49

48

47

46

45

44

43

42

41

40

39

38

37

1
10K_0402_1%
3.65K_0805_1%
UGATE_CPU1
2

PR137

PR138
PQ30 PR139

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

TPCA8028-H_SOP-ADVANCE8-5 1_0402_5%

1 2

680P_0402_50V7K
1 36 @ @ PR141
@PR141
(7,20) VGATE PGOOD BOOT1 0_0603_5%
4 4

2
PC112
(5) H_PSI# PR140
1 20_0402_5% 2 35 1 2
PSI# UGATE1 VSUM PC113

2
(31) PGD_IN 1@
@PR142
PR142 2 3 34 PHASE_CPU1 1 2
PMON PHASE1
VCC_PRM

3
2
1

3
2
1
0_0402_5% 1 PR143
2 147K_0402_1% 4 33 ISEN1
RBIAS PGND1 PQ31 0.22U_0603_10V7K
VR_TT# 5 32 LGATE_CPU1 TPCA8028-H_SOP-ADVANCE8-5 CPU_B+
VR_TT# LGATE1

2200P_0402_50V7K
5

5
C C

10U_1206_25V6M

10U_1206_25V6M
6 31 TPCA8030-H_SOP-ADV8-5
NTC PVCC PQ36

1
7 PU11 30 LGATE_CPU2 TPCA8030-H_SOP-ADV8-5
SOFT LGATE2

PC114

PC115

PC116
ISL6262ACRZ-T_QFN48_7X7 @PQ32
@ PQ32
PC117 8 29

2
0.022U_0603_25V7K OCSET PGND2 UGATE_CPU2-14
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR144 13K_0402_1% 10 27 UGATE_CPU2-1 PL10
COMP UGATE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2

3
2
1

3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR145
1 2

1
6.8_1206_5%
PC119 1000P_0402_50V7K 2.2_0603_1% PC118
DROOP

12 FB2 NC 25 2 3
VDIFF

ISEN2

ISEN1
VSUM

PR147
VSEN

PR146 11.3K_0402_1% 0.22U_0603_10V7K

GND

VDD
RTN

DFB

1
VIN

3.65K_0805_1%
VO

1 2

PR148

1
10K_0402_1%
1 2
13

14

15

16

17

18

19

20

21

22

23

24

1 2

PR149
PC120 1000P_0402_50V7K PR151

2
680P_0402_50V7K
PC121
ISEN1 4 4 1_0402_5%
ISEN2

2
2

0_0402_5%

1K_0402_1%

PR152 97.6K_0402_1% PC122 270P_0402_50V7K 1 2 +5VS PQ33 VSUM @ PR155

@PR155
1
@ PR153

1 2 2 1 PR150 1_0603_5% TPCA8028-H_SOP-ADVANCE8-5 0_0603_5%

1
PR154

1 2

3
2
1

3
2
1
PC124 100P_0402_50V8J PC123
1 2 1U_0402_6.3V4Z
1

1 2
2

PR156 PR157 PQ34 @ PC125

100_0402_1% PC126 2200P_0402_50V7K 10_0603_5% TPCA8028-H_SOP-ADVANCE8-5 0.22U_0603_10V7K
1 2 1 2 1 2 CPU_B+ VCC_PRM
B ISEN2 B
1

1 2 PC127
PR158 1K_0402_1% 0.1U_0603_25V7K
PR159
2

0_0402_5% PC128 330P_0402_50V7K

(5) VCCSENSE 1 2 1 2
VSUM
1

PR160
1

20_0402_5% PC130 PC129

+VCC_CORE 1 2 330P_0402_50V7K 0.01U_0603_50V7K PR161
2

PR162 2.61K_0402_1%
2

0_0402_5%
(5) VSSSENSE 1 2
2
1
11K_0402_1%

PC131 180P_0402_50V8J
2

PR164

1 2
2

PR163
20_0402_5% 1 2 1 2 PH3
10KB_0603_5%_ERTJ1VR103J
2

PR165 1K_0402_1% PR166 4.42K_0402_1%

1

VCC_PRM
PC132
0.1U_0402_16V7K
1 2

2 1
2

PC133 0.22U_0402_6.3V6K
PC134
A 0.22U_0603_10V7K A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 42 of 43
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D D

1 Solve power noise for HDD signal Solve power noise for HDD signal 0.1 P37 Change PJ13 to BEAD PL11 12/19 DVT

2 Solve power noise for HDD signal Solve power noise for HDD signal 0.1 P39 Change PJ15 to BEAD PL12 12/19 DVT

3 +1.05V Efficiency +1.05V Efficiency 0.1 P39 Change PL6 from 1.2U to 1.0U 12/19 DVT

4 For EMI solution For EMI solution 0.1 P39 Add PC136,PC137,PC138 ,Change PR96 to 2.2 ohm 12/19 DVT

5 For EMI solution For EMI solution 0.1 P37 Add PC139 12/19 DVT

6 For EMI solution For EMI solution 0.1 P42 Change PR135, PR145 to 2.2 ohm 12/19 DVT

7 For EMI solution For EMI solution 0.2 P39 Pop PR97 and PC76 02/02 PVT

C 8 Modify CPU MOSFET solution Modify CPU MOSFET solution 0.2 P42 change PQ29,PQ36 to SB00000HL00 02/02 PVT C

9 Modify CPU MOSFET solution Modify CPU MOSFET solution 0.2 P42 change PQ31,PQ33 to SB00000GL00 02/02 PVT

10 Modify CPU MOSFET solution Modify CPU MOSFET solution 0.2 P42 Unpop PQ32,PQ35,PQ30,PQ34 02/02 PVT

11 Modify CPU PWM frequency Modify CPU PWM frequency 0.2 P42 change PR146 to SD034113280 02/02 PVT

12

13

14

15
B B

16

17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A3806
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401668
Date: Wednesday, April 29, 2009 Sheet 43 of 43
5 4 3 2 1
www.s-manuals.com