A B C D E

1 1

Compal Confidential
2 2

NCL20 ULV M/B Schematics Document

Intel Penryn Processor with Cantiga SFF + DDRIII + ICH9M SFF

3
2009-10-08 3

REV:0.4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
Date: Tuesday, November 10, 2009 Sheet 1 of 41
A B C D E
 A B C D E

Compal confidential CK505

File Name : LA-5631P Thermal Sensor
Mobile Penym EMC1402-1-ACZL Clock Generator
page4 ICS9LPRS387
LV/ULV Dual Core
LS5631P I/O Board uFCPGA-956 CPU - SFF page 19
1 1

page 4,5,6,7
LS5632P C/R Board
H_A#(3..35) FSB
H_D#(0..63)
667/800/1066MHz 1.05V
LS5633P LED Board HDMI Conn. LCD CONN. CRT CONN.
page25 page 17 page 18

LS5634P SW Board Intel Cantiga GS45 DDR3 800MHz 1.5V DDR3

LVDS FCBGA 1363 - SFF SO-DIMM X2
Level shift
Dual Channel page 14,15
LS5635P TP/B Board
TMDS page 8,9,10,11,12,13

LS5636P ODD/B Board

2
DMI X4 USB conn x2 Bluetooth CMOS 2

conn Camera 1.3M

page 28 page 28 page23
IO board
PCI-Express
Intel ICH9-M 3.3V 48MHz USB
WBMMAP-569 - SFF 3.3V 24.576MHz/48Mhz
S-ATA
HD Audio
MINI Card x1 MINI Card x1 LAN ATHEROS Card Reader
page 19,20,21,22 RTS5159-GR
USB conn x1
3G WLAN AR8131L
page23
page 27 page 24 HDA Codec
port 0 ALC269X-GR
LPC BUS page 32

SIM CONN. RJ45 LAN HDD IO board

3 connector connector 3
page 23
page 25
ENE KB926 D2
port 1 page 29

CDROM SPEAKER Audio Jack

page 33 page 33
connector
RTC CKT. page 23
page 24

Power On/Off CKT. Touch Pad Int.KBD

page 30 page 30
page 32

DC/DC Interface CKT. IO/B Conn. BIOS

4
page 29 4

page 35 page 30

TP/B Conn.
page 31
Power Circuit DC/DC Security Classification Compal Secret Data Compal Electronics, Inc.
page 36~~42 2009/02/27 2009/02/20 Title
Speaker Conn. Issued Date Deciphered Date
Block Diagram
page 31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 2 of 41
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
ON OFF OFF

+1.5V 1.5V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+0.75V 0.75V switched power rail for DDR terminator ON OFF OFF Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON ON 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1
1
2
3
4
5
6
7 PCIE table

PCIE port1 3G Card

EC SM Bus1 address EC SM Bus2 address USB table
PCIE port2 Wireless Card
3
Port0 MB USB Conn1. 3
Device Address Device Address UHCI1
Smart Battery ADI ADT7421
Port1 MB USB Conn2. PCIE port3 GLAN
0001 011X b 1001 100X b
Port2 sub board
EHCI1 UHCI2 PCIE port4
Port3 WLAN
Port4 Card Reader PCIE port5
UHCI3
Port5 3G
PCIE port6
Port6 BT
UHCI4
Port7 CMOS Camera SATA table
EHCI2 Port8
ICH9M SMBUS Address UHCI5
Port9 SATA port0 HDD
Port10
UHCI6 SATA port1 ODD
Device HEX Address Port11
SATA port2
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100 SATA port3
CLOCK GENERATOR D2 11010010
(ICS9LPRS387, SLG8SP556V) SATA port4
4 4
SATA port5

ZZZ1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
PCB-MB AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
DA80000GO00 Date: Tuesday, October 20, 2009 Sheet 3 of 41
A B C D E
 5 4 3 2 1

+5VS +5VS
C638
1 2 @

1
1

0_0603_5%
R111 10U_0805_10V4Z D53 @
1SS355_SOD323-2
U19
Add it 090909. 1 VEN 8

2
GND D54
D 2 VIN 7 D

2
+VCCP +VCC_FAN1 GND
Place close to U1. 3 VO GND 6 1 2 @
EN_FAN1 1 2 4 VSET 5
(29) EN_FAN1 GND
0_0402_5% 1 BAS16_SOT23-3
(8) H_A#[3..16]
U1A R1007 C949 G990P11U SOP @
H_A#3 P2 M4 @ 0.1U_0402_16V4Z C639
A[3]# ADS# H_ADS# (8)
H_A#4 V4 J5 @ SA00002GW00 1 2
A[4]# BNR# H_BNR# (8) 2
H_A#5 W1 L5 10U_0805_10V4Z
A[5]# BPRI# H_BPRI# (8)

2
56_0402_5%
H_A#6 T4 C640
A[6]# +3VS

ADDR GROUP 0
H_A#7 AA1 N5 R10 1000P_0402_50V7K
A[7]# DEFER# H_DEFER# (8)
H_A#8 AB4 F38 51_0402_1% 1 2
A[8]# DRDY# H_DRDY# (8)
H_A#9 T2 J1 @
A[9]# DBSY# H_DBSY# (8)

1
R9
H_A#10 AC5 9/20

1
A[10]#

CONTROL
H_A#11 AD2 M2 R1586
A[11]# BR0# H_BR0# (8)
H_A#12 AD4 10K_0402_5%
A[12]#
H_A#13 AA5 B40 Change to NU 072709. 40mil
H_A#14 A[13]# IERR# JP32
AE5 D8 H_INIT# (18)

2
H_A#15 A[14]# INIT# +VCC_FAN1
AB2 A[15]# 1 1
H_A#16 AC1 N1 2
A[16]# LOCK# H_LOCK# (8) (29) FAN_SPEED1 2
Y4 FAN_PWM 3 5
(8) H_ADSTB#0 ADSTB[0]# (29) FAN_PWM 3 G1
G5 H_RESET# 1 4 6
RESET# H_RESET# (8) 4 G2
R1 K2 C641
(8) H_REQ#0 REQ[0]# RS[0]# H_RS#0 (8)
R5 H4 1000P_0402_50V7K E-T_3801-E04N-01R
(8) H_REQ#1 REQ[1]# RS[1]# H_RS#1 (8)
(8) H_REQ#2 U1 REQ[2]# RS[2]# K4 H_RS#2 (8) 2 CONN@ SP020907300
(8) H_REQ#3 P4 REQ[3]# TRDY# L1 H_TRDY# (8)
(8) H_REQ#4 W5 REQ[4]#
(8) H_A#[17..35] H2 H_HIT# (8) Change footprint 073109.
H_A#17 HIT#
AN1 A[17]# HITM# F2 H_HITM# (8)
H_A#18 AK4
C H_A#19 A[18]# C
AG1 A[19]# BPM[0]# AY8
ADDR GROUP 1

H_A#20 AT4 BA7

H_A#21 A[20]# BPM[1]#
AK2 A[21]# BPM[2]# BA5
H_A#22 AT2 AY2
A[22]# BPM[3]#
H_A#23 AH2 AV10 Del XDP_BPM#5 net.071309.
XDP/ITP SIGNALS

H_A#24 A[23]# PRDY#

AF4 A[24]# PREQ# AV2
H_A#25 AJ5 AV4 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI +VCCP
AH4 A[26]# TDI AW7
H_A#27 AM4 AU1 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS
AP4 A[28]# TMS AW5
H_A#29 AR5 AV8 XDP_TRST# XDP_TDI R1 1 2 51_0402_1%
H_A#30 A[29]# TRST# XDP_DBRESET#
AJ1 A[30]# DBR# J7 XDP_DBRESET# (19)
H_A#31 AL1 XDP_TMS R2 1 2 51_0402_1%
H_A#32 A[31]# R558 1 @
AM2 A[32]# 2 0_0402_5% H_PROCHOT# (40)
H_A#33 AU5 THERMAL XDP_TDO R3 1 2 51_0402_1%
H_A#34 A[33]# +VCCP
AP2 A[34]#
H_A#35 AR1 D38 R22 1 2 68_0402_5%
A[35]# PROCHOT# H_THERMDA_R R23
(8) H_ADSTB#1 AN5 ADSTB[1]# THERMDA BB34 1 2 0_0402_5% H_THERMDA
BD34 H_THERMDC_R R24 1 2 0_0402_5% H_THERMDC
THERMDC
(18) H_A20M# C7 A20M#
D4 B10 H_THERMTRIP# XDP_TRST# R6 1 2 51_0402_1%
(18) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (8,18)
ICH

(18) H_IGNNE# F10 IGNNE#

H_THERMDA, H_THERMDC routing together, XDP_TCK R7 1 2 51_0402_1%
(18) H_STPCLK# F8 STPCLK#
(18) H_INTR C9 H CLK Trace width / Spacing = 10 / 10 mil This shall place near CPU
LINT0
(18) H_NMI C5 A35 CLK_CPU_BCLK (16) Change from 54.9 ohm to 51ohm 072709.
LINT1 BCLK[0]
(18) H_SMI# E5 SMI# BCLK[1] C35 CLK_CPU_BCLK# (16)
V2 RSVD01
B B
Y2 RSVD02
AG5 RSVD03
RESERVED

AL5 add it 073109.

RSVD04 XDP_DBRESET#
J9 RSVD05
F4 RSVD06
H8 XDP_TDO
RSVD07

XDP_TRST#
+3VS
XDP_TDI C1034
0.1U_0402_16V4Z
PENRYN SFF_UFCBGA956 1 2
XDP_TMS

XDP_TCK U7
H_THERMDA
@ @ @
3

1 VDD SMCLK 8 EC_SMB_CK2 (29)

D9 D10 D11 1
PJDLC05_SOT23-3 PJDLC05_SOT23-3 PJDLC05_SOT23-3 C1035 2 7
DP SMDATA EC_SMB_DA2 (29)
2200P_0402_50V7K 3 6 1 2 +3VS
2 DN ALERT#
4 5 R305
H_THERMDC THERM# GND 10K_0402_5%
1

EMC1402-1-ACZL-TR_MSOP8
A For ESD A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3) & FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
Date: Tuesday, October 20, 2009 Sheet 4 of 41
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
(8) H_D#[0..15] H_D#[32..47] (8)
U1B U1C
H_D#0 F40 AP44 H_D#32 F32 AB28
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
G43 D[1]# D[33]# AR43 G33 VCC[002] VCC[069] AD30
H_D#2 E43 AH40 H_D#34 H32 AD28
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
J43 D[3]# D[35]# AF40 J33 VCC[004] VCC[071] Y26

DATA GROUP 0
D H_D#4 H_D#36 D
H40 D[4]# D[36]# AJ43 K32 VCC[005] VCC[072] AB26
H_D#5 H44 AG41 H_D#37 L33 AD26
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
G39 AF44 M32 AF30

DATA GROUP 2
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E41 D[7]# D[39]# AH44 N33 VCC[008] VCC[075] AF28
H_D#8 L41 AM44 H_D#40 P32 AH30
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
K44 D[9]# D[41]# AN43 R33 VCC[010] VCC[077] AH28
H_D#10 N41 AM40 H_D#42 T32 AF26
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
T40 D[11]# D[43]# AK40 U33 VCC[012] VCC[079] AH26
H_D#12 M40 AG43 H_D#44 V32 AK30
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
G41 D[13]# D[45]# AP40 W33 VCC[014] VCC[081] AK28
H_D#14 M44 AN41 H_D#46 Y32 AM30
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
L43 D[15]# D[47]# AL41 AA33 VCC[016] VCC[083] AM28
H_DSTBN#0 K40 AK44 H_DSTBN#2 AB32 AP30
(8) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (8) VCC[017] VCC[084]
H_DSTBP#0 J41 AL43 H_DSTBP#2 AC33 AP28
(8) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (8) VCC[018] VCC[085]
H_DINV#0 P40 AJ41 H_DINV#2 AD32 AK26
(8) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (8) VCC[019] VCC[086]
(8) H_D#[16..31] H_D#[48..63] (8) AE33 VCC[020] VCC[087] AM26
AF32 VCC[021] VCC[088] AP26
H_D#16 P44 AV38 H_D#48 AG33 AT30
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
V40 D[17]# D[49]# AT44 AH32 VCC[023] VCC[090] AT28
H_D#18 V44 AV40 H_D#50 AJ33 AV30
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
AB44 D[19]# D[51]# AU41 AK32 VCC[025] VCC[092] AV28
H_D#20 R41 AW41 H_D#52 AL33 AY30
D[20]# D[52]# VCC[026] VCC[093]

DATA GROUP 1
H_D#21 W41 AR41 H_D#53 AM32 AY28
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
N43 BA37 AN33 AT26

DATA GROUP 3
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
U41 D[23]# D[55]# BB38 AP32 VCC[029] VCC[096] AV26
H_D#24 AA41 AY36 H_D#56 AR33 AY26
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
AB40 D[25]# D[57]# AT40 AT34 VCC[031] VCC[098] BB30
H_D#26 AD40 BC35 H_D#58 AT32 BB28 +VCCP
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099]
AC41 D[27]# D[59]# BC39 AU33 VCC[033] VCC[100] BD30
H_D#28 AA43 BA41 H_D#60 AV32
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
Y40 D[29]# D[61]# BB40 AY32 VCC[035] VCCP_001 J11 R27 1 2 0_0402_5%
H_D#30 Y44 BA35 H_D#62 BB32 E11 R28 1 2 0_0402_5%
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP_002 C
T44 D[31]# D[63]# AU43 BD32 VCC[037] VCCP_003 G11 R29 1 2 0_0402_5%
H_DSTBN#1 U43 AY40 H_DSTBN#3 B28 J37 1
(8) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (8) VCC[038] VCCP_004
H_DSTBP#1 W43 AY38 H_DSTBP#3 B30 K38 Change to 330u_R9,
(8) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (8) VCC[039] VCCP_005 +
H_DINV#1 R43 BC37 H_DINV#3 B26 L37 C5
(8) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (8)
D28
VCC[040] VCCP_006
N37 330U_D2E_2.5VM_R9 casue high
V_CPU_GTLREF COMP0 VCC[041] VCCP_007 limitation. 12/14
AW43 GTLREF COMP[0] AE43 D30 VCC[042] VCCP_008 P38
COMP1 2
E37 TEST1 MISC COMP[1] AD44 F30 VCC[043] VCCP_009 R37
TEST2 D40 AE1 COMP2 F28 U37
T8 TEST2 COMP[2] VCC[044] VCCP_010

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
C43 AF2 COMP3 H30 V38
TEST3 COMP[3] VCC[045] VCCP_011
AE41 TEST4 H28 VCC[046] VCCP_012 W37
TEST5 AY10 G7 D26 AA37
T9 TEST5 DPRSTP# H_DPRSTP# (8,18,40) VCC[047] VCCP_013
TEST6 AC43 B8 F26 AB38
T10 TEST6 DPSLP# H_DPSLP# (18) VCC[048] VCCP_014

R30 1

R31 1

R32 1

R33 1
DPWR# C41 H_DPWR# (8) H26 VCC[049] VCCP_015 AC37
(16) CPU_BSEL0 A37 BSEL[0] PWRGOOD E7 H_PWRGOOD (18) K30 VCC[050] VCCP_016 AE37
(16) CPU_BSEL1 C37 BSEL[1] SLP# D10 H_CPUSLP# (8) K28 VCC[051]
B38 BD10 H_PSI# M30 B34
(16) CPU_BSEL2 BSEL[2] PSI# T11 VCC[052] VCCA[01] +1.5VS
M28 D34

2
VCC[053] VCCA[02]

10U_0805_6.3V6M
Near pin B34
0.01U_0402_16V7K
PENRYN SFF_UFCBGA956

Near pin D34

K26 VCC[054]
Cause CPU core power change to M26 VCC[055] VID[0] BD8 CPU_VID0 (40)
P30 BC7 1 1
1 phase, and not need support P28
VCC[056] VID[1]
BB10
CPU_VID1 (40)
VCC[057] VID[2] CPU_VID2 (40)
the pin, leave it as TP. 10/02 T30 VCC[058] VID[3] BB8 CPU_VID3 (40)
C6 C7
layout note: Route TEST3 & TEST5 traces on Resistor placed within T28 VCC[059] VID[4] BC5 CPU_VID4 (40) 2 2
V30 BB4 CPU_VID5 (40)
ground referenced layer to the TPs 0.5" of CPU pin.Trace V28
VCC[060] VID[5]
AY4
VCC[061] VID[6] CPU_VID6 (40)
should be at least 25 P26 VCC[062]
T26
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils away from any other V26
VCC[063]
BD12 VCCSENSE
VCC[064] VCCSENSE VCCSENSE (40)
toggling signal. Y30 VCC[065]
COMP[0,2] trace width is Y28 VCC[066]
AB30 BC13 VSSSENSE VSSSENSE (40)
VCC[067] VSSSENSE
166 0 1 1 18 mils. COMP[1,3] trace
B PENRYN SFF_UFCBGA956 B
width is 4 mils.

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0

+CPU_CORE

R34
1 2 VCCSENSE
+VCCP 100_0402_1%

R35
1

1 2 VSSSENSE
100_0402_1%
R36
1K_0402_1%
2

V_CPU_GTLREF

Close to CPU pin

1

R37
within 500mils.
A 2K_0402_1% A
2

Close to CPU pin AW43

within 500mils. Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 5 of 41
5 4 3 2 1
 A
B
C
D

5
5

BD28 VCC_101 VCCP_021 AL37

BB26 VCC_102 VCCP_022 AN37
BD26 VCC_103 VCCP_023 AP38
B22 VCC_104 VCCP_024 B32
B24 VCC_105 VCCP_025 C33
D22 VCC_106 VCCP_026 D32
D24 VCC_107 VCCP_027 E35
F24 VCC_108 VCCP_028 E33
F22 VCC_109 VCCP_029 F34
H24 VCC_110 VCCP_030 G35
H22 VCC_111 VCCP_031 F36
K24 VCC_112 VCCP_032 H36
K22 VCC_113 VCCP_033 J35
M24 VCC_114 VCCP_034 L35
M22 VCC_115 VCCP_035 N35
P24 VCC_116 VCCP_036 K36
P22 VCC_117 VCCP_037 R35
T24 VCC_118 VCCP_038 U35
T22 VCC_119 VCCP_039 P36
V24 VCC_120 VCCP_040 V36
V22 VCC_121 VCCP_041 W35
Y24 VCC_122 VCCP_042 AA35
Y22 VCC_123 VCCP_043 AC35
AB24 VCC_124 VCCP_044 AB36
AB22 VCC_125 VCCP_045 AE35
AD24 VCC_126 VCCP_046 AG35
AD22 VCC_127 VCCP_047 AJ35
AF24 VCC_128 VCCP_048 AF36
AF22 VCC_129 VCCP_049 AL35
AH24 VCC_130 VCCP_050 AN35
AH22 VCC_131 VCCP_051 AK36
AK24 VCC_132 VCCP_052 AP36
AK22 VCC_133 VCCP_053 B12
AM24 B14

4
4

VCC_134 VCCP_054
AM22 VCC_135 VCCP_055 C13
AP24 VCC_136 VCCP_056 D12
AP22 VCC_137 VCCP_057 D14
AT24 VCC_138 VCCP_058 E13
AT22 VCC_139 VCCP_059 F14
AV24 VCC_140 VCCP_060 F12
AV22 VCC_141 VCCP_061 G13
AY24 VCC_142 VCCP_062 H14
AY22 VCC_143 VCCP_063 H12
BB24 VCC_144 VCCP_064 J13
BB22 VCC_145 VCCP_065 K14
BD24 VCC_146 VCCP_066 K12
BD22 VCC_147 VCCP_067 L13
B16 VCC_148 VCCP_068 L11
B18 VCC_149 VCCP_069 M14
B20 VCC_150 VCCP_070 N13
D16 VCC_151 VCCP_071 N11
D18 VCC_152 VCCP_072 K10
F18 VCC_153 VCCP_073 P14
F16 VCC_154 VCCP_074 P12
H18 VCC_155 VCCP_075 R13
H16 VCC_156 VCCP_076 R11
D20 VCC_157 VCCP_077 T14
F20 VCC_158 VCCP_078 U13
H20 VCC_159 VCCP_079 U11
K18 VCC_160 VCCP_080 V14
K16 VCC_161 VCCP_081 V12
M18 VCC_162 VCCP_082 W13
M16 VCC_163 VCCP_083 W11
K20 VCC_164 VCCP_084 P10
M20 VCC_165 VCCP_085 V10
P18 VCC_166 VCCP_086 Y14
P16 AA13

Issued Date
VCC_167 VCCP_087
T18 VCC_168 VCCP_088 AA11

3
3

T16 VCC_169 VCCP_089 AB14

V18 AB12

Security Classification
VCC_170 VCCP_090
V16 VCC_171 VCCP_091 AC13
P20 VCC_172 VCCP_092 AC11
T20 VCC_173 VCCP_093 AD14
V20 VCC_174 VCCP_094 AB10
Y18 VCC_175 VCCP_095 AE13
Y16 VCC_176 VCCP_096 AE11
AB18 VCC_177 VCCP_097 AF14
AB16 VCC_178 VCCP_098 AF12
AD18 VCC_179 VCCP_099 AG13
AD16 VCC_180 VCCP_100 AG11
Y20 AH14

2009/02/27
VCC_181 VCCP_101
AB20 VCC_182 VCCP_102 AJ13
AD20 VCC_183 VCCP_103 AJ11
AF18 VCC_184 VCCP_104 AF10
AF16 VCC_185 VCCP_105 AK14
AH18 VCC_186 VCCP_106 AK12
AH16 VCC_187 VCCP_107 AL13
AF20 VCC_188 VCCP_108 AL11
AH20 VCC_189 VCCP_109 AN13
AK18 VCC_190 VCCP_110 AN11
AK16 VCC_191 VCCP_111 AP12
AM18 VCC_192 VCCP_112 AR13
AM16 VCC_193 VCCP_113 AR11
AP18 VCC_194 VCCP_114 AK10
AP16 VCC_195 VCCP_115 AP10
AK20 VCC_196 VCCP_116 AU13
AM20 AU11

Compal Secret Data

VCC_197 VCCP_117
AP20 L9

Deciphered Date
VCC_198 VCCP_118
AT18 VCC_199 VCCP_119 L7
AT16 VCC_200 VCCP_120 N9
AV18 VCC_201 VCCP_121 N7
AV16 VCC_202 VCCP_122 R9
AY18 R7

2
2

VCC_203 VCCP_123
AY16 VCC_204 VCCP_124 U9
AT20 VCC_205 VCCP_125 U7
AV20 VCC_206 VCCP_126 W9
AY20 VCC_207 VCCP_127 W7
BB18 VCC_208 VCCP_128 AA9
BB16 AA7
2009/02/20

VCC_209 VCCP_129
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

BD18 VCC_210 VCCP_130 AC9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

BD16 AC7
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VCC_211 VCCP_131
BB20 AE9
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

VCC_212 VCCP_132
BD20 VCC_213 VCCP_133 AE7
AM14 VCC_214 VCCP_134 AG9
AP14 VCC_215 VCCP_135 AG7
AT14 VCC_216 VCCP_136 AJ9
AV14 VCC_217 VCCP_137 AJ7
AY14 VCC_218 VCCP_138 AL9
BB14 VCC_219 VCCP_139 AL7
BD14 VCC_220 VCCP_140 AN9
AN7
Title

Date:

VCCP_141
+CPU_CORE

AF38 VCCP_017 VCCP_142 AR9

AG37 VCCP_018 VCCP_143 AR7
AJ37 VCCP_019 VCCP_144 A33
AK38 VCCP_020 VCCP_145 A13
+VCCP
+VCCP

U1F

Size Document Number

Custom NCL20 M/B LA-5631P

Tuesday, October 20, 2009

1
1

PENRYN SFF_UFCBGA956

Schematic
Sheet
Penryn(3/3)-Power

6
of
Compal Electronics, Inc.

41
Rev
0.1
A
B
C
D
 5 4 3 2 1

U1D U1E
B42 AM36 G25 AA15
+CPU_CORE Mid Frequence Decoupling
VSS[001] VSS[082] VSS_164 VSS_280
F44 VSS[002] VSS[083] AR35 G23 VSS_165 VSS_281 AC15
D44 VSS[003] VSS[084] AU35 G21 VSS_166 VSS_282 Y10
D42 VSS[004] VSS[085] AV34 J25 VSS_167 VSS_283 AD10
F42 VSS[005] VSS[086] AW35 J23 VSS_168 VSS_284 AH12

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
H42 VSS[006] VSS[087] AW33 J21 VSS_169 VSS_285 AE15
K42 VSS[007] VSS[088] AY34 L25 VSS_170 VSS_286 AG15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
M42 VSS[008] VSS[089] AT36 L23 VSS_171 VSS_287 AJ15
P42 VSS[009] VSS[090] AV36 L21 VSS_172 VSS_288 AH10

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31
T42 VSS[010] VSS[091] BA33 N25 VSS_173 VSS_289 AM12
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
V42 VSS[011] VSS[092] BC33 N23 VSS_174 VSS_290 AL15
Y42 VSS[012] VSS[093] BB36 N21 VSS_175 VSS_291 AN15
D D
AB42 VSS[013] VSS[094] BD36 R25 VSS_176 VSS_292 AR15
AD42 VSS[014] VSS[095] C27 R23 VSS_177 VSS_293 AM10
AF42 VSS[015] VSS[096] C29 R21 VSS_178 VSS_294 AT12
AH42 VSS[016] VSS[097] C31 U25 VSS_179 VSS_295 AV12
AK42 VSS[017] VSS[098] E29 U23 VSS_180 VSS_296 AW13
AM42 VSS[018] VSS[099] E27 U21 VSS_181 VSS_297 AW11 Replace 10uF_0805 to 10uF_0603.071309.
AP42 VSS[019] VSS[100] G29 W25 VSS_182 VSS_298 AY12
AY44 VSS[020] VSS[101] G27 W23 VSS_183 VSS_299 AU15
AV44 VSS[021] VSS[102] E31 W21 VSS_184 VSS_300 AW15
AT42 VSS[022] VSS[103] G31 AA25 VSS_185 VSS_301 AT10
+CPU_CORE
AV42 VSS[023] VSS[104] J29 AA23 VSS_186 VSS_302 BA13
AY42 VSS[024] VSS[105] J27 AA21 VSS_187 VSS_303 BA11 High Frequence Decoupling
BA43 VSS[025] VSS[106] L29 AC25 VSS_188 VSS_304 BB12
BB42 VSS[026] VSS[107] L27 AC23 VSS_189 VSS_305 BC11
C39 VSS[027] VSS[108] N29 AC21 VSS_190 VSS_306 BA15

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
E39 VSS[028] VSS[109] N27 AE25 VSS_191 VSS_307 BC15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
G37 VSS[029] VSS[110] J31 AE23 VSS_192 VSS_308 B6
H38 VSS[030] VSS[111] L31 AE21 VSS_193 VSS_309 D6

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55
J39 VSS[031] VSS[112] N31 AG25 VSS_194 VSS_310 E9
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
L39 VSS[032] VSS[113] R29 AG23 VSS_195 VSS_311 F6
M38 VSS[033] VSS[114] R27 AG21 VSS_196 VSS_312 G9
N39 VSS[034] VSS[115] U29 AJ25 VSS_197 VSS_313 H6
R39 VSS[035] VSS[116] U27 AJ23 VSS_198 VSS_314 K8
T38 VSS[036] VSS[117] R31 AJ21 VSS_199 VSS_315 K6
U39 VSS[037] VSS[118] U31 AL25 VSS_200 VSS_316 M8
W39 VSS[038] VSS[119] W29 AL23 VSS_201 VSS_317 M6
Y38 VSS[039] VSS[120] W27 AL21 VSS_202 VSS_318 P8 6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.
AA39 VSS[040] VSS[121] W31 AN25 VSS_203 VSS_319 P6
AC39 VSS[041] VSS[122] AA29 AN23 VSS_204 VSS_320 T8
AD38 VSS[042] VSS[123] AA27 AN21 VSS_205 VSS_321 T6
AE39 VSS[043] VSS[124] AC29 AR25 VSS_206 VSS_322 V8
AG39 VSS[044] VSS[125] AC27 AR23 VSS_207 VSS_323 V6
C C
AH38 VSS[045] VSS[126] AA31 AR21 VSS_208 VSS_324 U5
AJ39 VSS[046] VSS[127] AC31 AU25 VSS_209 VSS_325 Y8
AL39 VSS[047] VSS[128] AE29 AU23 VSS_210 VSS_326 Y6
AM38 AE27 AU21 AB8
AN39
AR39
VSS[048]
VSS[049]
VSS[129]
VSS[130] AG29
AG27
AW25
AW23
VSS_211
VSS_212
VSS_327
VSS_328 AB6
AD8
ESR <= 1.5m ohm
VSS[050] VSS[131] VSS_213 VSS_329
AR37 VSS[051] VSS[132] AJ29 AW21 VSS_214 VSS_330 AD6
AT38 AJ27 BA25 AF8
AU39
VSS[052]
VSS[053]
VSS[133]
VSS[134] AE31 BA23
VSS_215
VSS_216
VSS_331
VSS_332 AF6 Near CPU CORE regulator
AU37 VSS[054] VSS[135] AG31 BA21 VSS_217 VSS_333 AH8
AW39 VSS[055] VSS[136] AJ31 BC25 VSS_218 VSS_334 AH6
AW37 VSS[056] VSS[137] AL29 BC23 VSS_219 VSS_335 AK8
+CPU_CORE
BA39 VSS[057] VSS[138] AL27 BC21 VSS_220 VSS_336 AK6
BC41 VSS[058] VSS[139] AN29 C17 VSS_221 VSS_337 AM8
BD40 VSS[059] VSS[140] AN27 C19 VSS_222 VSS_338 AM6
BD38 VSS[060] VSS[141] AL31 E19 VSS_223 VSS_339 AP8
B36 VSS[061] VSS[142] AN31 E17 VSS_224 VSS_340 AP6

220U_D2_2VK_R9

220U_D2_2VK_R9

220U_D2_2VK_R9
H34 VSS[062] VSS[143] AR29 G19 VSS_225 VSS_341 AT8 1 1 1

C56

C57

C58
D36 VSS[063] VSS[144] AR27 G17 VSS_226 VSS_342 AT6
K34 AR31 J19 AU9 + + +
VSS[064] VSS[145] VSS_227 VSS_343
M34 VSS[065] VSS[146] AU29 J17 VSS_228 VSS_344 AV6
M36 VSS[066] VSS[147] AU27 L19 VSS_229 VSS_345 AU7
2 2 2
P34 VSS[067] VSS[148] AW29 L17 VSS_230 VSS_346 AW9
T34 VSS[068] VSS[149] AW27 N19 VSS_231 VSS_347 AY6
V34 VSS[069] VSS[150] AU31 N17 VSS_232 VSS_348 BA9
T36 VSS[070] VSS[151] AW31 R19 VSS_233 VSS_349 BB6
Y34 VSS[071] VSS[152] BA29 R17 VSS_234 VSS_350 BC9
AB34 VSS[072] VSS[153] BA27 U19 VSS_235 VSS_351 BD6
AD34 VSS[073] VSS[154] BC29 U17 VSS_236 VSS_352 B4
Y36 VSS[074] VSS[155] BC27 W19 VSS_237 VSS_353 C3
AD36 VSS[075] VSS[156] BA31 W17 VSS_238 VSS_354 E3 Del C37 to improve power plan. 6/14
AF34 VSS[076] VSS[157] BC31 AA19 VSS_239 VSS_355 G3
B B
AH34 VSS[077] VSS[158] C21 AA17 VSS_240 VSS_356 J3
AH36 VSS[078] VSS[159] C23 AC19 VSS_241 VSS_357 L3
AK34 VSS[079] VSS[160] C25 AC17 VSS_242 VSS_358 N3
AM34 VSS[080] VSS[161] E25 AE19 VSS_243 VSS_359 R3
AP34 VSS[081] VSS[162] E23 AE17 VSS_244 VSS_360 U3
VSS[163] E21 AG19 VSS_245 VSS_361 W3
AG17 VSS_246 VSS_362 AA3
AJ19 VSS_247 VSS_363 AC3
PENRYN SFF_UFCBGA956 AJ17 AE3
VSS_248 VSS_364
AL19 VSS_249 VSS_365 AG3
AL17 VSS_250 VSS_366 AJ3
AN19 VSS_251 VSS_367 AL3
AN17 AN3 +VCCP
VSS_252 VSS_368
AR19 VSS_253 VSS_369 AR3
AR17 VSS_254 VSS_370 AU3
AU19 VSS_255 VSS_371 AW3
AU17 VSS_256 VSS_372 BA3
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AW19 VSS_257 VSS_373 BC3 1 1 1 1 1 1 1 1 1 1 1 1
AW17 VSS_258 VSS_374 D2
BA19 VSS_259 VSS_375 E1
C59

C60

C61

C62

C63

C64

C65

C66

C67

C68

C69

C70
BA17 VSS_260 VSS_376 G1
2 2 2 2 2 2 2 2 2 2 2 2
BC19 VSS_261 VSS_377 AW1
BC17 VSS_262 VSS_378 BA1
C11 VSS_263 VSS_379 BB2
C15 VSS_264 VSS_380 A41
E15 VSS_265 VSS_381 A39
G15 VSS_266 VSS_382 A29
H10 VSS_267 VSS_383 A27
M12 VSS_268 VSS_384 A31
J15 VSS_269 VSS_385 A25
L15 VSS_270 VSS_386 A23
N15 VSS_271 VSS_387 A21
A A
M10 VSS_272 VSS_388 A19
T12 VSS_273 VSS_389 A17
R15 VSS_274 VSS_390 A11
U15 VSS_275 VSS_391 A15
W15 VSS_276 VSS_392 A7
T10 VSS_277 VSS_393 A5
Y12 VSS_278 VSS_394 A9
AD12 BD4
VSS_279 VSS_395 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title
PENRYN SFF_UFCBGA956
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-GND/Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 7 of 41
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] (4) U3B

(5) H_D#[0..63] U3A
L15 H_A#3 J43
H_D#0 H_A#_3 H_A#4 RSVD1
J7 H_D#_0 H_A#_4 B14 L43 RSVD2 SA_CK_0 BB32 M_CLK_DDR0 (14)
H_D#1 H_A#5

DDR CLK/ CONTROL/COMPENSATION

H6 H_D#_1 H_A#_5 C15 J41 RSVD3 SA_CK_1 BA25 M_CLK_DDR1 (14)
H_D#2 L11 D12 H_A#6 L41 BA33 M_CLK_DDR2 (15)
H_D#3 H_D#_2 H_A#_6 H_A#7 RSVD4 SB_CK_0
J3 H_D#_3 H_A#_7 F14 AN11 RSVD5 SB_CK_1 BA23 M_CLK_DDR3 (15)
H_D#4 H4 G17 H_A#8 AM10
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6
G3 H_D#_5 H_A#_9 B12 Add them for Boundary Scan. 10/23 AK10 RSVD7 SA_CK#_0 BA31 M_CLK_DDR#0 (14)
H_D#6 K10 J15 H_A#10 AL11 BC25
H_D#_6 H_A#_10 RSVD8 SA_CK#_1 M_CLK_DDR#1 (14)
H_D#7 K12 D16 H_A#11 F12 BC33
H_D#_7 H_A#_11 RSVD9 SB_CK#_0 M_CLK_DDR#2 (15)

RSVD
H_D#8 L1 C17 H_A#12 R38 1 2 @ 1K_0402_5% TCK AN45 BB24
H_D#_8 H_A#_12 RSVD10 SB_CK#_1 M_CLK_DDR#3 (15)
H_D#9 M10 D14 H_A#13 R39 1 2 @ 4.7K_0402_5% TDI AP44
H_D#10 H_D#_9 H_A#_13 H_A#14 R40 @ 4.7K_0402_5% TDO RSVD11
M6 H_D#_10 H_A#_14 K16 1 2 AT44 RSVD12 SA_CKE_0 BC35 DDR_CKE0_DIMMA (14)
H_D#11 N11 F16 H_A#15 +3VS R41 1 2 @ 1K_0402_5% TMS AN47 BE33
H_D#_11 H_A#_15 RSVD13 SA_CKE_1 DDR_CKE1_DIMMA (14)
H_D#12 L7 B16 H_A#16 C27 BE37
H_D#_12 H_A#_16 RSVD14 SB_CKE_0 DDR_CKE2_DIMMB (15)
D H_D#13 K6 C21 H_A#17 D30 BC37 D
H_D#_13 H_A#_17 RSVD15 SB_CKE_1 DDR_CKE3_DIMMB (15)
H_D#14 M4 D18 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
K4 H_D#_15 H_A#_19 J19 J9 RSVD17 SA_CS#_0 BK18 DDR_CS0_DIMMA# (14)
H_D#16 P6 J21 H_A#20 BK16
H_D#_16 H_A#_20 SA_CS#_1 DDR_CS1_DIMMA# (14)
H_D#17 W9 B18 H_A#21 BE23
H_D#_17 H_A#_21 SB_CS#_0 DDR_CS2_DIMMB# (15)
H_D#18 V6 D22 H_A#22 AW42 BC19
H_D#_18 H_A#_22 RSVD20 SB_CS#_1 DDR_CS3_DIMMB# (15)
H_D#19 H_A#23

0.01U_0402_25V7K
2.2U_0603_6.3V4Z
V2 H_D#_19 H_A#_23 G19
H_D#20 P10 J17 H_A#24 BJ17 M_ODT0 (14)
H_D#_20 H_A#_24 +1.5V SA_ODT_0
H_D#21 W7 L21 H_A#25 DDR3 BJ19 M_ODT1 (14)
H_D#22 H_D#_21 H_A#_25 H_A#26 SA_ODT_1 +1.5V DDR3
N9 H_D#_22 H_A#_26 L19 BB20 RSVD22 SB_ODT_0 BC17 M_ODT2 (15)
H_D#23 P4 G21 H_A#27 1 1 BE19 BE17 M_ODT3 (15)
H_D#_23 H_A#_27 RSVD23 SB_ODT_1

1
C71

C72
H_D#24 U9 D20 H_A#28 BF20
H_D#25 H_D#_24 H_A#_28 H_A#29 RSVD24 SMRCOMP R43
V4 H_D#_25 H_A#_29 K22 BF18 RSVD25 SM_RCOMP BL25 1 2 80.6_0402_1%
H_D#26 U1 F18 H_A#30 R42 BK26 SMRCOMP# R44 1 2 80.6_0402_1%
H_D#27 H_D#_26 H_A#_30 H_A#31 2 2 1K_0402_1% SM_RCOMP#
W3 H_D#_27 H_A#_31 K20
H_D#28 V10 F20 H_A#32 BK32 SMRCOMP_VOH 2 1 SYSON (29,31,37)

2
H_D#29 H_D#_28 H_A#_32 H_A#33 SMRCOMP_VOH SM_RCOMP_VOH SMRCOMP_VOL D2 CH751H-40_SC76
U7 H_D#_29 H_A#_33 F22 SM_RCOMP_VOL BL31
H_D#30 W11 B20 H_A#34 R26 1 2
H_D#_30 H_A#_34 DDR3_PG (37)

1
H_D#31 U11 A19 H_A#35 BC51 +V_DDR_MCH_REF 0_0402_5%
H_D#32 H_D#_31 H_A#_35 R45 SM_VREF SM_PWROK R46 @1
AC11 H_D#_32 SM_PWROK AY37 2 10K_0402_1%
H_D#33 AC9 F10 3.01K_0402_1% BH20 SM_REXT R47 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# (4) SM_REXT
H_D#34 Y4
HOST A15 BA37 SM_DRAMRST# SM_DRAMRST# (14,15)
H_D#_34 H_ADSTB#_0 H_ADSTB#0 (4) SM_DRAMRST#
H_D#35 Y10 C19 H_ADSTB#1 (4)

2
H_D#_35 H_ADSTB#_1
H_D#36 AB6 C9 H_BNR# (4)
SMRCOMP_VOL B42 CLK_DREF_96M (16) add it for change to use
H_D#_36 H_BNR# DPLL_REF_CLK
H_D#37 AA9 B8 H_BPRI# (4) D42 CLK_DREF_96M# (16) DDR3.070309
H_D#_37 H_BPRI# DPLL_REF_CLK#

1
H_D#38

0.01U_0402_25V7K
2.2U_0603_6.3V4Z
AB10 H_D#_38 H_BREQ# C11 H_BR0# (4) DPLL_REF_SSCLK B50 CLK_DREF_SSC (16)
H_D#39 AA1 E5 1 1 R48 D50
H_D#_39 H_DEFER# H_DEFER# (4) DPLL_REF_SSCLK# CLK_DREF_SSC# (16)
H_D#40 AC3 D6 1K_0402_1%
H_D#_40 H_DBSY# H_DBSY# (4)

C73

C74
H_D#41 AC7 AH10 R49
H_D#_41 HPLL_CLK CLK_MCH_BCLK (16) PEG_CLK CLK_MCH_3GPLL (16)
H_D#42 AD12 AJ11 P50
CLK_MCH_BCLK# (16) CLK_MCH_3GPLL# (16)

2
H_D#43 H_D#_42 HPLL_CLK# 2 2 PEG_CLK#
AB4 G11

CLK
H_D#_43 H_DPWR# H_DPWR# (5)
H_D#44 Y6 H2
H_D#_44 H_DRDY# H_DRDY# (4)
H_D#45 AD10 C7
H_D#_45 H_HIT# H_HIT# (4)
H_D#46 AA11 F8 AG55
H_D#_46 H_HITM# H_HITM# (4) DMI_RXN_0 DMI_TXN0 (19)
H_D#47 AB2 A11 AL49
C H_D#_47 H_LOCK# H_LOCK# (4) DMI_RXN_1 DMI_TXN1 (19) C
H_D#48 AD4 D8 AH54
H_D#_48 H_TRDY# H_TRDY# (4) DMI_RXN_2 DMI_TXN2 (19)
H_D#49 AE7 AL47
H_D#_49 DMI_RXN_3 DMI_TXN3 (19)
H_D#50 AD2
H_D#51 H_D#_50
AD6 H_D#_51 DMI_RXP_0 AG53 DMI_TXP0 (19)
H_D#52 AE3 K26 AK50
H_D#_52 (16) MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 (19)
H_D#53 AG9 L9 G23 AH52
H_D#_53 H_DINV#_0 H_DINV#0 (5) (16) MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 (19)
H_D#54 AG7 N7 G25 AL45
H_D#_54 H_DINV#_1 H_DINV#1 (5) (16) MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 (19)
H_D#55 AE11 AA7 J25
H_D#_55 H_DINV#_2 H_DINV#2 (5) T30 CFG_3
H_D#56 AK6 AG3 L25 AG49
H_D#_56 H_DINV#_3 H_DINV#3 (5) T31 CFG_4 DMI_TXN_0 DMI_RXN0 (19)
H_D#57 AF6 L27 AJ49
H_D#_57 (10) CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 (19)
H_D#58 AJ9 K2 F24 AJ47
H_D#_58 H_DSTBN#_0 H_DSTBN#0 (5) (10) CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 (19)
H_D#59 AH6 N3 D24 AG47
H_D#_59 H_DSTBN#_1 H_DSTBN#1 (5) (10) CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 (19)
H_D#60 AF12 AA3 D26

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 (5) T32 CFG_8

CFG
H_D#61 AH4 AF4 J23 AF50
H_D#_61 H_DSTBN#_3 H_DSTBN#3 (5) (10) CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 (19)
H_D#62 AJ7 B26 AH50
H_D#_62 (10) CFG10 CFG_10 DMI_TXP_1 DMI_RXP1 (19)
H_D#63 AE9 L3 A23 AJ45
H_D#_63 H_DSTBP#_0 H_DSTBP#0 (5) T33 CFG_11 DMI_TXP_2 DMI_RXP2 (19)
H_DSTBP#_1 M2 H_DSTBP#1 (5) (10) CFG12 C23 CFG_12 DMI_TXP_3 AG45 DMI_RXP3 (19)
H_DSTBP#_2 Y2 H_DSTBP#2 (5) (10) CFG13 B24 CFG_13
H_SWNG B6 AF2 B22
H_SWING H_DSTBP#_3 H_DSTBP#3 (5) T34 CFG_14
H_RCOMP D4 K24 VGATE 1 2 GMCH_PWROK
H_RCOMP T35 CFG_15 (16,19,40) VGATE
J13 C25 R106 @ 0_0402_5%
H_REQ#_0 H_REQ#0 (4) (10) CFG16 CFG_16

GRAPHICS VID
L13 L23 M_PWROK 1 2
H_REQ#_1 H_REQ#1 (4) T36 CFG_17 (19) M_PWROK
C13 L33 R107 0_0402_5%
H_REQ#_2 H_REQ#2 (4) T37 CFG_18
H_REQ#_3 G13 H_REQ#3 (4) (10) CFG19 K32 CFG_19
(4) H_RESET# J11 G15 H_REQ#4 (4) (10) CFG20 K34 G33 DFGT_VID_0 (39) add it.062309
H_CPURST# H_REQ#_4 CFG_20 GFX_VID_0
(5) H_CPUSLP# G9 H_CPUSLP# GFX_VID_1 G37 DFGT_VID_1 (39)
H_RS#_0 F4 H_RS#0 (4) GFX_VID_2 F38 DFGT_VID_2 (39)
H_RS#_1 F2 H_RS#1 (4) GFX_VID_3 F36 DFGT_VID_3 (39)
H_RS#_2 G7 H_RS#2 (4) (19) PM_BMBUSY# J35 PM_SYNC# GFX_VID_4 G35 DFGT_VID_4 (39)
L17 H_AVREF (5,18,40) H_DPRSTP# F6 PM_DPRSTP#
H_VREF K18 PM_EXTTS#0 J39 R455 1 2 Modify in 9/26
H_DVREF (14) PM_EXTTS#0 PM_EXT_TS#_0

PM
PM_EXTTS#1 L39
(15) PM_EXTTS#1 PM_EXT_TS#_1
Trace < = 500mils CANTIGA GMCH SFF_FCBGA1363 GMCH_PWROK AY39 G39 100K_0402_5%
PWROK GFX_VR_EN GFXVR_EN (39) +VCCP
layout note: R50 1 2 100_0402_1% BB18
(17,29) PLT_RST# RSTIN#
B (4,18) H_THERMTRIP# 1 2 K28 Refer to spec. pull low 100k.062909 B
R51 0_0402_5% THERMTRIP#
Route H_SCOMP and H_SCOMP# with trace width, (19,40) PM_DPRSLPVR K36 DPRSLPVR

1
spacing and impedance (55 ohm) same as FSB data layout note:
Add R428 in 9/26

C75
AK52 R52
CL_CLK CL_CLK0 (19)
traces Place them close to U4 pin BC51. 1 AK54 1K_0402_1%
CL_DATA CL_DATA0 (19)
A7 AW40 M_PWROK
NC_1 CL_PWROK

ME
A49 AL53 CL_RST# (19)

2
+1.5V NC_2 CL_RST#
Layout Note: V_DDR_MCH_REF trace DDR3 CL_VREF

@ 0.1U_0402_16V4Z
Layout Note: 2
A52 NC_3 CL_VREF AL55
width and spacing is 20/20. A54
H_RCOMP / H_VREF / H_SWNG NC_4

1
B54 NC_5 1
1

trace width and spacing is 10/20 D55 C76 R53

NC_6
1K_0402_5% G55 NC_7 DDPC_CTRLCLK F34 T38 499_0402_1%

NC
BE55 F32 0.1U_0402_16V4Z
R54 NC_8 DDPC_CTRLDATA T39 2
BH55 B38 SDVO_SCLK SDVO_SCLK (24)

2
+VCCP NC_9 SDVO_CTRLCLK
BK55 A37 SDVO_SDAT Change from 511

MISC
SDVO_SDAT (24)
2

+VCCP NC_10 SDVO_CTRLDATA

+V_DDR_MCH_REF BK54 C31 MCH_CLKREQ# (16) to 499.070709.
NC_11 CLKREQ#
BL54 NC_12 ICH_SYNC# K42 MCH_ICH_SYNC# (19)
1K_0402_1%

221_0603_1%

C77
0.1U_0402_16V4Z

BL52 NC_13
1

1 BL49 NC_14
R55 R56 BL7 D10 TSATN# R58 1 2 54.9_0402_1% +VCCP
1K_0402_5% NC_15 TSATN#
BL4 NC_16
R57 BL2
2 NC_17
BK2
2

H_VREF H_RCOMP H_SWNG NC_18

BK1 NC_19
BH1 NC_20
R59

24.9_0402_1%

0.1U_0402_16V4Z

BE1 NC_21
1

1
100_0402_1%

HDA_BITCLK_MCH
0.1U_0402_16V4Z

1 1 G1 NC_22 HDA_BCLK C29 HDA_BITCLK_MCH (18)

C78 R60 R61 C79 +3VS B30 HDA_RST#_MCH R313
HDA_RST# HDA_RST#_MCH (18)

HDA
2K_0402_1%

D28 HDA_SDIN2_MCH 1 2
HDA_SDI HDA_SDIN2 (18)
1

+3VS A27 HDA_SDOUT_MCH

2 2 HDA_SDO HDA_SDOUT_MCH (18)
R325 B28 HDA_SYNC_MCH 33_0402_5%
HDA_SYNC_MCH (18)
2

1K_0402_5% HDA_SYNC
1

R326
2

@ Near B6 pin 1K_0402_5% MCH_TSATN_EC# (29)

A A
within 100 mils from NB CANTIGA GMCH SFF_FCBGA1363 +3VS
1

C
2

2 Q1
B MMBT3904_SOT23-3 PM_EXTTS#0 R62 1 2 10K_0402_5%
R327
1

C E
3

TSATN# 1 2 2 Q2 PM_EXTTS#1 R63 1 2 10K_0402_5%

B MMBT3904_SOT23-3
330_0402_5% E
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 8 of 41
5 4 3 2 1
 5 4 3 2 1

D D

(14) DDR_A_D[0..63] (15) DDR_B_D[0..63]

U3D U3E
DDR_A_D0 AP46 BC21 DDR_B_D0 AP54 BJ13
SA_DQ_0 SA_BS_0 DDR_A_BS0 (14) SB_DQ_0 SB_BS_0 DDR_B_BS0 (15)
DDR_A_D1 AU47 BJ21 DDR_B_D1 AM52 BK12
SA_DQ_1 SA_BS_1 DDR_A_BS1 (14) SB_DQ_1 SB_BS_1 DDR_B_BS1 (15)
DDR_A_D2 AT46 BJ41 DDR_B_D2 AR55 BK38
SA_DQ_2 SA_BS_2 DDR_A_BS2 (14) SB_DQ_2 SB_BS_2 DDR_B_BS2 (15)
DDR_A_D3 AU49 DDR_B_D3 AV54
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AR45 SA_DQ_4 SA_RAS# BH22 DDR_A_RAS# (14) AM54 SB_DQ_4
DDR_A_D5 AN49 BK20 DDR_B_D5 AN53 BE21
SA_DQ_5 SA_CAS# DDR_A_CAS# (14) SB_DQ_5 SB_RAS# DDR_B_RAS# (15)
DDR_A_D6 AV50 BL15 DDR_A_WE# (14) DDR_B_D6 AT52 BH14
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# (15)
DDR_A_D7 AP50 DDR_B_D7 AU53 BK14 DDR_B_WE# (15)
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AW47 SA_DQ_8 AW53 SB_DQ_8
DDR_A_D9 BD50 DDR_B_D9 AY52
DDR_A_D10 SA_DQ_9 DDR_B_D10 SB_DQ_9
AW49 SA_DQ_10 DDR_A_DM[0..7] (14) BB52 SB_DQ_10
DDR_A_D11 BA49 AT50 DDR_A_DM0 DDR_B_D11 BC53
SA_DQ_11 SA_DM_0 SB_DQ_11 DDR_B_DM[0..7] (15)
DDR_A_D12 BC49 BB50 DDR_A_DM1 DDR_B_D12 AV52 AP52 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
DDR_A_D14 BA47 BE39 DDR_A_DM3 DDR_B_D14 BD52 BJ49 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43

A
DDR_A_D16 BF46 BE7 DDR_A_DM5 DDR_B_D16 BF54 BH12 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
DDR_A_D18 BF50 AR9 DDR_A_DM7 DDR_B_D18 BH48 AY2 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BF48 SA_DQ_19 DDR_A_DQS[0..7] (14) BK48 SB_DQ_19 SB_DM_7 AJ3
DDR_A_D20 BC43 AR47 DDR_A_DQS0 DDR_B_D20 BE53
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] (15)

MEMORY
DDR_A_D21 BE49 BA45 DDR_A_DQS1 DDR_B_D21 BH52 AR53 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BA43 SA_DQ_22 SA_DQS_2 BE45 BK46 SB_DQ_22 SB_DQS_1 BA53
DDR_A_D23 BE47 BC41 DDR_A_DQS3 DDR_B_D23 BJ47 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BH50
DDR_A_D24 BF42 BC13 DDR_A_DQS4 DDR_B_D24 BL45 BK42 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BC39 SA_DQ_25 SA_DQS_5 BB10 BJ45 SB_DQ_25 SB_DQS_4 BH8
DDR_A_D26 BF44 BA7 DDR_A_DQS6 DDR_B_D26 BL41 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
BF40 SA_DQ_27 SA_DQS_7 AN7 DDR_A_DQS#[0..7] (14) BH44 SB_DQ_27 SB_DQS_6 AV2
DDR_A_D28 BB40 AR49 DDR_A_DQS#0 DDR_B_D28 BH46 AM2 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] (15) C
DDR_A_D29 BE43 AW45 DDR_A_DQS#1 DDR_B_D29 BK44 AT54 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
BF38 SA_DQ_30 SA_DQS#_2 BC45 BK40 SB_DQ_30 SB_DQS#_1 BB54
DDR_A_D31 BE41 BA41 DDR_A_DQS#3 DDR_B_D31 BJ39 BJ51 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BA15 SA_DQ_32 SA_DQS#_4 BA13 BK10 SB_DQ_32 SB_DQS#_3 BH42
DDR_A_D33 BE11 BA11 DDR_A_DQS#5 DDR_B_D33 BH10 BK8 DDR_B_DQS#4
SYSTEM

DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5

BE15 SA_DQ_34 SA_DQS#_6 BA9 BK6 SB_DQ_34 SB_DQS#_5 BC3
DDR_A_D35 BF14 AN9 DDR_A_DQS#7 DDR_B_D35 BH6 AW3 DDR_B_DQS#6
DDR_A_D36 SA_DQ_35 SA_DQS#_7 DDR_B_D36 SB_DQ_35 SB_DQS#_6 DDR_B_DQS#7

SYSTEM
BB14 SA_DQ_36 DDR_A_MA[0..14] (14) BJ9 SB_DQ_36 SB_DQS#_7 AN3
DDR_A_D37 BC15 BC23 DDR_A_MA0 DDR_B_D37 BL11 DDR_B_MA[0..14] (15)
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BE13 SA_DQ_38 SA_MA_1 BF22 BG5 SB_DQ_38 SB_MA_0 BJ15
DDR_A_D39 BF16 BE31 DDR_A_MA2 DDR_B_D39 BJ5 BJ33 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BF10 SA_DQ_40 SA_MA_3 BC31 BG3 SB_DQ_40 SB_MA_2 BH24
DDR_A_D41 BC11 BH26 DDR_A_MA4 DDR_B_D41 BF4 BA17 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
BF8 SA_DQ_42 SA_MA_5 BJ35 BD4 SB_DQ_42 SB_MA_4 BF36
DDR_A_D43 BG7 BB34 DDR_A_MA6 DDR_B_D43 BA3 BH36 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BC7 SA_DQ_44 SA_MA_7 BH32 BE5 SB_DQ_44 SB_MA_6 BF34
DDR_A_D45 BC9 BB26 DDR_A_MA8 DDR_B_D45 BF2 BK34 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
DDR

BD6 SA_DQ_46 SA_MA_9 BF32 BB4 SB_DQ_46 SB_MA_8 BJ37

DDR_A_D47 BF12 BA21 DDR_A_MA10 DDR_B_D47 AY4 BH40 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
AV6 SA_DQ_48 SA_MA_11 BG25 BA1 SB_DQ_48 SB_MA_10 BH16
DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
BB6 SA_DQ_49 SA_MA_12 BH34 AP2 SB_DQ_49 SB_MA_11 BK36
DDR_A_D50 AW7 BH18 DDR_A_MA13 DDR_B_D50 AU1 BH38 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AY6 SA_DQ_51 SA_MA_14 BE25 AT2 SB_DQ_51 SB_MA_13 BJ11
DDR_A_D52 AT10 DDR_B_D52 AT4 BL37 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AW11 SA_DQ_53 AV4 SB_DQ_53
DDR_A_D54 AU11 DDR_B_D54 AU3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AW9 SA_DQ_55 AR3 SB_DQ_55
DDR_A_D56 AR11 DDR_B_D56 AN1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AT6 SA_DQ_57 AP4 SB_DQ_57
DDR_A_D58 AP6 DDR_B_D58 AL3
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AL7 SA_DQ_59 AJ1 SB_DQ_59
DDR_A_D60 AR7 DDR_B_D60 AK4
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AT12 SA_DQ_61 AM4 SB_DQ_61
DDR_A_D62 AM6 DDR_B_D62 AH2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AU7 SA_DQ_63 AK2 SB_DQ_63
CANTIGA GMCH SFF_FCBGA1363 CANTIGA GMCH SFF_FCBGA1363

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 9 of 41
5 4 3 2 1
 5 4 3 2 1

U3C Strap Pin Table

PEGCOMP trace width +VCC_PEG 000 = FSB 1066MHz
and spacing is 20/25 mils. CFG[2:0] FSB Freq select
(22) DPST_PWM D38 010 = FSB 800MHz
L_BKLT_CTRL PEGCOMP
(29) ENBKL C37 U45 1 2
R65 1 2 10K_0402_5% K38
L_BKLT_EN PEG_COMPI
T44 R64 49.9_0402_1% 011 = FSB 667MHz
+3VS L_CTRL_CLK PEG_COMPO
Others = Reserved
R66 1 2 10K_0402_5% L37 layout note:
L_CTRL_DATA
(22) LVDS_DDC2_CLK J37 L_DDC_CLK PEG_RX#_0 D52
(22) LVDS_DDC2_DATA L35 L_DDC_DATA PEG_RX#_1 G49 Place R64 <500mils to U4 pin U45&T44. CFG[4:3] Reserved
PEG_RX#_2 K54
Change from 4.22k to2.4k 072709. H50 0 = DMI x 2
PEG_RX#_3
(22) GMCH_ENVDD B36 L_VDD_EN PEG_RX#_4 M52 CFG5 (DMI select) 1 = DMI x 4
D
R67 1
T42
2 2.4K_0402_1% F50
H46
LVDS_IBG
LVDS_VBG
PEG_RX#_5
PEG_RX#_6
N49
P54
*
0 = The iTPM Host Interface is enable D
P44 LVDS_VREFH PEG_RX#_7 V46 CFG6
K46 Y50 1 = The iTPM Host Interface is disable
(22) LVDS_A_C-
(22) LVDS_A_C+
LVDS_A_C-
LVDS_A_C+
D46
B46
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_8
PEG_RX#_9 V52
W49 0 =(TLS)chiper suite with no confidentiality
*
LVDSA_CLK PEG_RX#_10

LVDS
D44 LVDSB_CLK# PEG_RX#_11 AB54 CFG7 (Intel Management
B44 AD46 1 =(TLS)chiper suite with confidentiality
(22) LVDS_A_0- LVDS_A_0- G45
LVDSB_CLK PEG_RX#_12
PEG_RX#_13 AC55
AE49
Engine Crypto strap)
*
LVDS_A_1- LVDSA_DATA#_0 PEG_RX#_14
(22) LVDS_A_1- F46 LVDSA_DATA#_1 PEG_RX#_15 AF54

GRAPHICS
(22) LVDS_A_2- LVDS_A_2- G41 CFG8 Reserved
LVDSA_DATA#_2
C45 LVDSA_DATA#_3 PEG_RX_0 E51
PEG_RX_1 F48
(22) LVDS_A_0+ LVDS_A_0+ F44 J55 CFG9 0 = Reverse Lane,15->0, 14->1
LVDS_A_1+ LVDSA_DATA_0 PEG_RX_2 HDMI_HPD#
(22) LVDS_A_1+ G47 LVDSA_DATA_1 PEG_RX_3 J49 HDMI_HPD# (24)
LVDS_A_2+ F40 M54 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
(22) LVDS_A_2+
A45
LVDSA_DATA_2
LVDSA_DATA_3
PEG_RX_4
PEG_RX_5 M50
P52
*
PEG_RX_6
B40 LVDSB_DATA#_0 PEG_RX_7 U47 0 = Enable
A41 LVDSB_DATA#_1 PEG_RX_8 AA49 CFG10 (PCIE Lookback enable)
F42 V54 1 = Disable
D48
LVDSB_DATA#_2
LVDSB_DATA#_3
PEG_RX_9
PEG_RX_10 V50
AB52 CFG11 Reserved
*
PEG_RX_11
D40 LVDSB_DATA_0 PEG_RX_12 AC47
C41 AC53 CFG[13:12] (XOR/ALLZ) 00 = Reserved

PCI-EXPRESS
LVDSB_DATA_1 PEG_RX_13
G43 LVDSB_DATA_2 PEG_RX_14 AD50 01 = XOR Mode Enabled
B48 LVDSB_DATA_3 PEG_RX_15 AF52 10 = All Z Mode Enabled
11 = Normal Operation(Default)
For EMI. 9/26 PEG_TX#_0 L47
F52
HDMI_C_TX2-
HDMI_C_TX1-
C1036 1
C1037 1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
TX2D-
TX1D-
(24)
(24) CFG[15:14] Reserved
*
R68 75_0402_5% PEG_TX#_1 HDMI_C_TX0- C1038 1 0.1U_0402_16V4Z
1 2 J27 TVA_DAC PEG_TX#_2 P46 2 TX0D- (24)

TV
R69 1 2 75_0402_5% E27 H54 HDMI_C_CLK- C1039 1 2 0.1U_0402_16V4Z TXCD- (24)
C R70 75_0402_5% TVB_DAC PEG_TX#_3 C
1 2 G27 TVC_DAC PEG_TX#_4 L55 CFG16 (FSB Dynamic ODT) 0 = Disabled
PEG_TX#_5 T46
Del TV_LUMA & CRMA in 10/12. F26 R53 1 = Enabled
Change to mount 072709.
TVA_RTN PEG_TX#_6
PEG_TX#_7 U49
T54
*
PEG_TX#_8
PEG_TX#_9 Y46 CFG[18:17] Reserved
B34 TV_DCONSEL_0 PEG_TX#_10 AB46
D34 TV_DCONSEL_1 PEG_TX#_11 W53
Y54 CFG19 (DMI Lane Reversal) 0 = Normal Operation
Tie to GND. 9/28
PEG_TX#_12
PEG_TX#_13 AC49
AF46 (Lane number in Order)
*
PEG_TX#_14
PEG_TX#_15 AD54
1 = Reverse Lane
(23) GMCH_CRT_B GMCH_CRT_B J29 J47 HDMI_C_TX2+ C1040 1 2 0.1U_0402_16V4Z TX2D+ (24)
CRT_BLUE PEG_TX_0 HDMI_C_TX1+ C1041 1 0.1U_0402_16V4Z
PEG_TX_1 F54 2 TX1D+ (24)
GMCH_CRT_G G29 N47 HDMI_C_TX0+ C1042 1 2 0.1U_0402_16V4Z CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.
(23) GMCH_CRT_G
GMCH_CRT_R F30
CRT_GREEN PEG_TX_2
PEG_TX_3 H52
L53
HDMI_C_CLK+ C1043 1 2 0.1U_0402_16V4Z
TX0D+
TXCD+
(24)
(24)
1 = PCIE/SDVO are operating simu.
*
(23) GMCH_CRT_R CRT_RED PEG_TX_4
VGA

PEG_TX_5 R47
E29 CRT_IRTN PEG_TX_6 R55
PEG_TX_7 T50
(23) GMCH_CRT_CLK GMCH_CRT_CLK D36 T52
GMCH_CRT_DATA CRT_DDC_CLK PEG_TX_8
(23) GMCH_CRT_DATA C35 CRT_DDC_DATA PEG_TX_9 W47
(23) GMCH_CRT_HSYNC R71 1 2 30.1_0402_1% CRT_HSYNC_R J33 AA47
CRT_HSYNC PEG_TX_10 R72
D32 CRT_TVO_IREF PEG_TX_11 W55 (8) CFG5 1 2 @ 2.21K_0402_1%
(23) GMCH_CRT_VSYNC R73 1 2 30.1_0402_1% CRT_VSYNC_R G31 Y52
CRT_VSYNC PEG_TX_12 R74
PEG_TX_13 AB50 (8) CFG6 1 2 @ 2.21K_0402_1%
PEG_TX_14 AE47
2

AD52 R75 1 2 @ 2.21K_0402_1%

PEG_TX_15 (8) CFG7
R76
1.02K_0402_1% R77 1 2 @ 2.21K_0402_1%
(8) CFG9
Close to pin D32 and keep CANTIGA GMCH SFF_FCBGA1363
B R78 B
30mil space to other (8) CFG10 1 2 @ 2.21K_0402_1%
1

part/trace. (8) CFG12

R79 1 2 @ 2.21K_0402_1%

R80 1 2 @ 2.21K_0402_1%
(8) CFG13
R81 1 2 @ 2.21K_0402_1%
(8) CFG16
+3VS

GMCH_CRT_B
R559 1 2 2.2K_0402_5% LVDS_DDC2_CLK
GMCH_CRT_G +3VS
R560 1 2 2.2K_0402_5% LVDS_DDC2_DATA
GMCH_CRT_R
R82 1 2 @ 4.02K_0402_1%
(8) CFG19
R561 1 2 2.2K_0402_5% GMCH_CRT_CLK
@ R83 1 2 @ 4.02K_0402_1%
(8) CFG20
R562 1 2 2.2K_0402_5% GMCH_CRT_DATA
@
Nu it 101309.
1

1
150_0402_1%

150_0402_1%

150_0402_1%
R13

R15

R16
2

1 2 ENBKL
R469 100K_0402_5%
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 10 of 41
5 4 3 2 1
 5 4 3 2 1

9/27
9/27 +1.05VM_DPLLA +VCCP +V1.05VM_AXF 9/27 +VCCP
R84
Change to 330u_R9, 1 2 R85 1 2 0_0603_5%
BLM18PG181SN1D_0603
casue high +VCCP

10U_0805_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z

22U_0805_6.3V
limitation. 12/14 1 1 1 1

C80
U3H
+3VS +3VS_DAC_CRT

C81

C82

C83
BLM18PG181SN1D_0603 R13
R86 VTT_1 2 2 2 2

330U_D2E_2.5VM_R9
VTT_2 T12

0.47U_0603_10V7K

2.2U_0805_16V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
2 1 J31 VCCA_CRT_DAC VTT_3 R11 1
+3VS_DAC_BG VTT_4 T10 1 1 1 1
+3VS
0.1U_0402_16V4Z

10U_0603_6.3V

0.1U_0402_16V4Z

0.01U_0402_16V7K
R9 + 9/27
R87 VTT_5
1 1 1 1 VTT_6 T8
DDR3

C87
C85

C86

C88

C84
2 1 L31 R7

CRT
BLM18PG181SN1D_0603 VCCA_DAC_BG VTT_7 2 2 2 2 2 +1.05VM_DPLLB +VCCP +1.5V_SM_CK +1.5V

0.01U_0402_16V7K
D M33 VSSA_DAC_BG VTT_8 T6 9/27 D
C89

C90

C91

C92 R88
R5

22U_0805_6.3V
2 2 2 2 VTT_9 R89
1 1 9/27 VTT_10 T4 1 2 1 2 0_0603_5%
R3 BLM18PG181SN1D_0603
VTT_11

0.1U_0402_16V4Z
+1.05VM_DPLLA J45 VCCA_DPLLA VTT_12 T2

2
Change package 081709.

C93

C94

22U_0805_6.3V

0_0603_5%
R1 1 1

VTT
2 2 VTT_13

C95

0.1U_0402_16V4Z
+1.05VM_DPLLB L49 VCCA_DPLLB +3VS_TVDAC +3VS

10U_0603_6.3V6M
1 1

PLL

C96

C98
R90
install 0.1U & 10U for wavy issue. 7/29 +1.05VM_HPLL AF10 VCCA_HPLL 2 2
R91

C97
+1.05VM_MPLL AE1 VCCA_MPLL VCCA_TV_DAC K30 1 2
+1.8V_TXLVDS 2 2

10U_0603_6.3V6M
BLM18PG181SN1D_0603

TV

0.01U_0402_16V7K

0.1U_0402_16V4Z
9/27 1
change 0.1U to 22U for wavy issue. 5/20 R92 1 1

A PEG A LVDS
+VCC_HDA 0_0402_5%
+1.5VS_PEG_BG U43 VCCA_LVDS1 +1.05VM_HPLL +VCCP

C99
1 U41 A31 1 2

D TV/CRT HDA
VCCA_LVDS2 VCC_HDA 2

C100

C101
C102 @ R93
1000P_0402_50V7K 2 2
V44 VSSA_LVDS 1 2
BLM18PG181SN1D_0603
2

0.1U_0402_16V4Z

4.7U_0805_10V4Z
VCCD_QDAC N34 +1.5VS_QDAC
+1.5VS R94 1 2 0_0603_5% AJ43 1 1
VCCA_PEG_BG
VCCD_TVDAC N32 +1.5VS_TVDAC
1

C103

C104
C105
Disable HDMI audio 2 2
9/27 +1.05VM_PEGPLL AG43 VCCA_PEG_PLL
0.1U_0402_16V4Z
2
9/27 +VCC_HDA +1.5VS
9/27
AW24 VCCA_SM_1
AU24
+VCCP +1.05VM_A_SM
AW22
AU22
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
POWER R321 1 2 0_0603_5%
+1.05VM_MPLL
R95
+VCCP +1.5VS_TVDAC +1.5VS

AU21 1 1 2 R96
VCCA_SM_5

0.1U_0402_16V4Z
AW20 BLM18PG181SN1D_0603 1 2
VCCA_SM_6

C1045

10U_0805_6.3V6M
BLM18PG181SN1D_0603

0.1U_0402_16V4Z
AU19 VCCA_SM_7

0.01U_0402_16V7K

0.1U_0402_16V4Z
C106

C107
R97 1 2 0_0805_5% AW18 Enable HDMI audio 1 1

A SM
C VCCA_SM_8 2 C
AU18 VCCA_SM_9 1 1
10U_0805_6.3V6M

4.7U_0805_10V4Z

1U_0603_10V4Z
220U_D2_4VM_R15

1 1 1 1 AW16 VCCA_SM_10
C146 AU16 VCCA_SM_11 2 2

C108

C109
+ AT16 VCCA_SM_12 2 2
C111

C112

C113

AR16 VCCA_SM_13
2 2 2 AU15
2 VCCA_SM_14
AT15 VCCA_SM_15 9/27
AR15 VCCA_SM_16
AW14 VCCA_SM_17 VCC_AXF_1 M25 +V1.05VM_AXF +1.8V_TXLVDS +1.8V
9/21
N24

AXF
VCC_AXF_2
AT24 VCCA_SM_NCTF_1 VCC_AXF_3 M23 +VCCP
Change to use 220uf_D2 090909. AR24 R98 1 2 0_0603_5% +VCC_PEG
VCCA_SM_NCTF_2

1000P_0402_50V7K
AT22 VCCA_SM_NCTF_3
AR22 VCCA_SM_NCTF_4
AT21 1 1 R99 1 2 0_0805_5%
VCCA_SM_NCTF_5 C115
AR21 VCCA_SM_NCTF_6 VCC_SM_CK_1 BK24 +1.5V_SM_CK
DDR3

4.7U_0805_10V4Z

10U_0805_6.3V6M

220U_D2_4VM_R15
AT19 BL23 @ 10U_0805_6.3V6M 1

SM CK
VCCA_SM_NCTF_7 VCC_SM_CK_2

C114
AR19 VCCA_SM_NCTF_8 VCC_SM_CK_3 BJ23 1 1
+1.05VM_A_SM_CK 2 2 +
AT18 VCCA_SM_NCTF_9 VCC_SM_CK_4 BK22
AR18 VCCA_SM_NCTF_10 +3VS_HV

C117

C118

C116
2 2 2
9/27
VCC_TX_LVDS T41 +1.8V_TXLVDS
R100 1 2 0_0805_5% AU27 9/27
VCCA_SM_CK_4 +1.05VM_PEGPLL +VCCP
AU28 VCCA_SM_CK_3 VCC_HV_1 C33
10U_0805_6.3V6M

0.1U_0402_16V4Z

AU29 A33 L1 9/21

VCCA_SM_CK_2 VCC_HV_2
1 1 AU31 1 2
HV

VCCA_SM_CK_1

0.1U_0402_16V4Z
AT31 BLM18PG121SN1D_0603
VCCA_SM_CK_NCTF_1 +1.05VM_DMI

0.1U_0402_16V4Z

10U_0805_10V4Z
AR31 1 9/29 +VCCP
VCCA_SM_CK_NCTF_2
C119

C120

AT29 VCCA_SM_CK_NCTF_3 VCC_PEG_1 AB44 +VCC_PEG 1 1

2 2 AR29 Y44
VCCA_SM_CK_NCTF_4 VCC_PEG_2

C121
AT28 AC43 R101 1 2 0_0603_5%
PEG

VCCA_SM_CK_NCTF_5 VCC_PEG_3 2

C122

C123

0.1U_0402_16V4Z
AR28 VCCA_SM_CK_NCTF_6 VCC_PEG_4 AA43
2 2
AT27 VCCA_SM_CK_NCTF_7 1
B AR27 VCCA_SM_CK_NCTF_8
B

C124
VCC_DMI_1 AM44 +1.05VM_DMI 2
VCC_DMI_2 AN43
AL43 9/29
DMI

VCC_DMI_3
+1.05VM_HPLL AH12 VCCD_HPLL
0.1U_0402_16V4Z

+1.05VM_PEGPLL AE43 VCCD_PEG_PLL +VCCP_D

C125

1
0.1U_0402_16V4Z

9/27 K14
VTTLF

VTTLF1
C126

1 M46 VCCD_LVDS_1 VTTLF2 Y12

LVDS

+1.8V R102 2 1 0_0603_5% L45 P2

2 VCCD_LVDS_2 VTTLF3 R103 1
+VCCP 2 1 2 10_0402_5% R104 1 2 0_0402_5% +3VS_HV
1U_0603_10V4Z

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

1 D1 CH751H-40_SC76
2
1 1 1 +3VS
+1.8V_LVDS CANTIGA GMCH SFF_FCBGA1363
C127

2
C128

C129

C130

2 2 2
+1.5VS_QDAC +1.5VS

R105
1 2
BLM18PG181SN1D_0603

0.01U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0603_6.3V
1 1 1

C131

C132

C133
2 2 2

install 4.7U for wavy issue. 7/29

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NAV30 M/B LA-5451P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 11 of 41
5 4 3 2 1
 5 4 3 2 1

U3G

+VCCGFX
3000mA
Extnal Graphic: 1210.34mA T32 change from +VCCP to +VCCGFX 062909.
VCC_AXG_NCTF_1
BB36 U31
integrated Graphic: 1930.4mA DDR3 BE35
VCC_SM_1 VCC_AXG_NCTF_2
T31
VCC_SM_2 VCC_AXG_NCTF_3
+1.5V AW34 VCC_SM_3 VCC_AXG_NCTF_4 R31
U3F AW32 U29
VCC_SM_4 VCC_AXG_NCTF_5

10U_0805_6.3V6M

10U_0805_6.3V6M

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.22U_0402_10V4Z

4.7U_0805_10V4Z
9/21 BK30 VCC_SM_5 VCC_AXG_NCTF_6 T29 1 1 1

330U_B2_2.5VM_R15M
1 BH30 VCC_SM_6 VCC_AXG_NCTF_7 R29
1 1 2 BF30 VCC_SM_7 VCC_AXG_NCTF_8 U28
+VCCP

C137

C138

C139

C140
+

C134

C135

C136
BD30 VCC_SM_8 VCC_AXG_NCTF_9 U27
D 2 2 2 D
BB30 VCC_SM_9 VCC_AXG_NCTF_10 T27
AW30 VCC_SM_10 VCC_AXG_NCTF_11 R27
2 2 2 1
AT41 VCC_1 BL29 VCC_SM_11 VCC_AXG_NCTF_12 U25
AR41 VCC_2 BJ29 VCC_SM_12 VCC_AXG_NCTF_13 T25
AN41 VCC_3 BG29 VCC_SM_13 VCC_AXG_NCTF_14 R25
AJ41 VCC_4 BE29 VCC_SM_14 VCC_AXG_NCTF_15 U24
AH41 VCC_5 BC29 VCC_SM_15 VCC_AXG_NCTF_16 U22

POWER
AD41 VCC_6 BA29 VCC_SM_16 VCC_AXG_NCTF_17 T22
AC41 Change to D2 size.073109. AY29 R22
VCC_7 VCC_SM_17 VCC_AXG_NCTF_18
Y41 VCC_8 BK28 VCC_SM_18 VCC_AXG_NCTF_19 U21
W41 VCC_9 BH28 VCC_SM_19 VCC_AXG_NCTF_20 T21
AT40 VCC_10 BF28 VCC_SM_20 VCC_AXG_NCTF_21 R21
330U_D2E_2.5VM_R9

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AM40 VCC_11 BD28 VCC_SM_21 VCC_AXG_NCTF_22 AM19
10U_0805_6.3V6M

1 AL40 VCC_12 BB28 VCC_SM_22 VCC_AXG_NCTF_23 AL19

1 1 1 1 BL27 VCC_SM_23 VCC_AXG_NCTF_24 AH19
C141

C142

C143

C144

C145
+ AJ40 BJ27 AG19
VCC_13 VCC_SM_24 VCC_AXG_NCTF_25

VCC CORE
AH40 VCC_14 BG27 VCC_SM_25 VCC_AXG_NCTF_26 AE19

VCC SM
AG40 VCC_15 BE27 VCC_SM_26 VCC_AXG_NCTF_27 AD19
2 2 2 2 2
AE40 BC27 AC19

VCC GFX NCTF

VCC_16 VCC_SM_27 VCC_AXG_NCTF_28
AD40 VCC_17 BA27 VCC_SM_28 VCC_AXG_NCTF_29 W19
AC40 VCC_18 AY27 VCC_SM_29 VCC_AXG_NCTF_30 U19
AA40 VCC_19 AW26 VCC_SM_30 VCC_AXG_NCTF_31 AM18
Y40 VCC_20 BF24 VCC_SM_31 VCC_AXG_NCTF_32 AL18
AN35 VCC_21 BL19 VCC_SM_32 VCC_AXG_NCTF_33 AJ18
AM35 VCC_22 BB16 VCC_SM_33 VCC_AXG_NCTF_34 AH18
AJ35 +VCCGFX AG18
VCC_23 VCC_AXG_NCTF_35
AH35 VCC_24 VCC_AXG_NCTF_36 AE18
AD35 VCC_25 VCC_AXG_NCTF_37 AD18
AC35 VCC_26 VCC_AXG_NCTF_38 AC18
W35 VCC_27 W32 VCC_AXG_1 VCC_AXG_NCTF_39 AA18
AM34 VCC_28 AG31 VCC_AXG_2 VCC_AXG_NCTF_40 Y18

10U_0805_6.3V

10U_0805_6.3V

1U_0603_10V4Z

0.1U_0402_16V4Z
AL34 VCC_29 9/21 1 AE31 VCC_AXG_3 VCC_AXG_NCTF_41 W18

C147

C148

C149

C150
C C
AJ34 VCC_30 1 1 1 1 AD31 VCC_AXG_4 VCC_AXG_NCTF_42 U18
AH34 C110 + AC31 T18
VCC_31 +VCCP 330U_D2E_2.5VM_R9 VCC_AXG_5 VCC_AXG_NCTF_43
AG34 VCC_32 AA31 VCC_AXG_6 VCC_AXG_NCTF_44 R18
AE34 VCC_33 Y31 VCC_AXG_7
2 2 2 2 2
POWER
AD34 VCC_34 W31 VCC_AXG_8
VCC_NCTF_1 AT38 AH29 VCC_AXG_9
AC34 VCC_35 VCC_NCTF_2 AR38 AG29 VCC_AXG_10
AA34 VCC_36 VCC_NCTF_3 AN38 AE29 VCC_AXG_11
VCC_NCTF_4 AM38 AD29 VCC_AXG_12 VCC_AXG_62 AJ16
Y34 VCC_37 VCC_NCTF_5 AL38 AC29 VCC_AXG_13 VCC_AXG_63 AH16
W34 VCC_38 VCC_NCTF_6 AG38 AA29 VCC_AXG_14 VCC_AXG_64 AD16
AM32 VCC_39 VCC_NCTF_7 AE38 Y29 VCC_AXG_15 VCC_AXG_65 AC16
AL32 VCC_40 VCC_NCTF_8 AA38 W29 VCC_AXG_16 VCC_AXG_66 AA16
AJ32 VCC_41 VCC_NCTF_9 Y38 AH28 VCC_AXG_17 VCC_AXG_67 U16
AH32 VCC_42 VCC_NCTF_10 W38 AG28 VCC_AXG_18 VCC_AXG_68 T16

VCC GFX
AE32 VCC_43 VCC_NCTF_11 U38 AE28 VCC_AXG_19 VCC_AXG_69 R16
AD32 VCC_44 VCC_NCTF_12 T38 AA28 VCC_AXG_20 VCC_AXG_70 AM15
AA32 VCC_45 VCC_NCTF_13 R38 AH27 VCC_AXG_21 VCC_AXG_71 AL15
AM31 VCC_46 VCC_NCTF_14 AT37 6326.84mA AG27 VCC_AXG_22 VCC_AXG_72 AJ15
AL31 VCC_47 VCC_NCTF_15 AR37 AE27 VCC_AXG_23 VCC_AXG_73 AH15
AJ31 VCC_48 VCC_NCTF_16 AN37 AD27 VCC_AXG_24 VCC_AXG_74 AG15
AH31 VCC_49 VCC_NCTF_17 AM37 AC27 VCC_AXG_25 VCC_AXG_75 AE15
AM29 VCC_50 VCC_NCTF_18 AL37 AA27 VCC_AXG_26 VCC_AXG_76 AA15
AL29 VCC_51 VCC_NCTF_19 AJ37 Y27 VCC_AXG_27 VCC_AXG_77 Y15
AM28 VCC_52 VCC_NCTF_20 AH37 W27 VCC_AXG_28 VCC_AXG_78 W15
AL28 VCC_53 VCC_NCTF_21 AG37 AH25 VCC_AXG_29 VCC_AXG_79 U15
AJ28 VCC_54 VCC_NCTF_22 AE37 AD25 VCC_AXG_30 VCC_AXG_80 T15
AM27 VCC_55 VCC_NCTF_23 AD37 AC25 VCC_AXG_31
AL27 VCC_56 VCC_NCTF_24 AC37 W25 VCC_AXG_32
VCC NCTF

AM25 VCC_57 VCC_NCTF_25 AA37 AJ24 VCC_AXG_33

AL25 VCC_58 VCC_NCTF_26 Y37 AH24 VCC_AXG_34
AJ25 VCC_59 VCC_NCTF_27 W37 AG24 VCC_AXG_35
B B
AM24 VCC_60 VCC_NCTF_28 U37 AE24 VCC_AXG_36
N36 VCC_61 VCC_NCTF_29 T37 AD24 VCC_AXG_37
VCC_NCTF_30 R37 AC24 VCC_AXG_38
VCC_NCTF_31 AT35 AA24 VCC_AXG_39
VCC_NCTF_32 AR35 Y24 VCC_AXG_40
VCC_NCTF_33 U35 W24 VCC_AXG_41
VCC_NCTF_34 AT34 AM22 VCC_AXG_42
VCC_NCTF_35 AR34 AL22 VCC_AXG_43
VCC_NCTF_36 U34 AJ22 VCC_AXG_44

VCC GFX
VCC_NCTF_37 T34 AH22 VCC_AXG_45
VCC_NCTF_38 R34 AG22 VCC_AXG_46
AE22 VCC_AXG_47
AD22 VCC_AXG_48
AC22 VCC_AXG_49
AA22 AU45 VCCSM_LF1
VCC_AXG_50 VCC_SM_LF1

VCC SM LF
AM21 BF52 VCCSM_LF2
VCC_AXG_51 VCC_SM_LF2 VCCSM_LF3
AL21 VCC_AXG_52 VCC_SM_LF3 BB38
AJ21 BA19 VCCSM_LF4
VCC_AXG_53 VCC_SM_LF4 VCCSM_LF5
AH21 VCC_AXG_54 VCC_SM_LF5 BE9
AD21 AU9 VCCSM_LF6
VCC_AXG_55 VCC_SM_LF6 VCCSM_LF7
AC21 VCC_AXG_56 VCC_SM_LF7 AL9

C156 0.1U_0402_16V4Z

C157 0.1U_0402_16V4Z

C151 0.22U_0603_10V7K

C152 0.22U_0603_10V7K

C153 0.47U_0402_6.3V6K

C154 1U_0603_10V4Z

C155 1U_0603_10V4Z
AA21 VCC_AXG_57 1 1 1 1 1 1 1
Y21 VCC_AXG_58
W21 VCC_AXG_59
AM16 VCC_AXG_60
CANTIGA GMCH SFF_FCBGA1363 2 2 2 2 2 2 2
AL16 VCC_AXG_61

PAD T43 AG13 VCC_AXG_SENSE

PAD T44 AE13 VSS_AXG_SENSE

A A

CANTIGA GMCH SFF_FCBGA1363

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 12 of 41
5 4 3 2 1
 5 4 3 2 1

U3I

BA55 C43 U3J

VSS_1 VSS_100
AU55 VSS_2 VSS_101 A43
AN55 VSS_3 VSS_102 BD42 AN25 VSS_199 VSS_300 AM8
AJ55 VSS_4 VSS_103 H42 AG25 VSS_200 VSS_301 AK8
AE55 VSS_5 VSS_104 BG41 AE25 VSS_201 VSS_302 AH8
AA55 VSS_6 VSS_105 AY41 AA25 VSS_202 VSS_303 AF8
U55 VSS_7 VSS_106 AU41 Y25 VSS_203 VSS_304 AD8
N55 VSS_8 VSS_107 AM41 E25 VSS_204 VSS_305 AB8
BD54 VSS_9 VSS_108 AL41 A25 VSS_205 VSS_306 Y8
BG53 VSS_10 VSS_109 AG41 BD24 VSS_206 VSS_307 V8
AJ53 VSS_11 VSS_110 AE41 AN24 VSS_207 VSS_308 P8
AE53 VSS_12 VSS_111 AA41 AL24 VSS_208 VSS_309 M8
D D
AA53 VSS_13 VSS_112 R41 H24 VSS_209 VSS_310 K8
U53 VSS_14 VSS_113 M41 BG23 VSS_210 VSS_311 H8
N53 VSS_15 VSS_114 E41 AY23 VSS_211 VSS_312 BJ7
J53 VSS_16 VSS_115 BD40 E23 VSS_212 VSS_313 E7
G53 VSS_17 VSS_116 AU40 BD22 VSS_213 VSS_314 BF6
E53 VSS_18 VSS_117 AR40 BB22 VSS_214 VSS_315 BC5
K52 VSS_19 VSS_118 AN40 AN22 VSS_215 VSS_316 BA5
BG51 VSS_20 VSS_119 W40 Y22 VSS_216 VSS_317 AW5
BA51 VSS_21 VSS_120 U40 W22 VSS_217 VSS_318 AU5
AW51 VSS_22 VSS_121 T40 H22 VSS_218 VSS_319 AR5
AU51 VSS_23 VSS_122 R40 BL21 VSS_219 VSS_320 AN5
AR51 VSS_24 VSS_123 K40 BG21 VSS_220 VSS_321 AL5
AN51 VSS_25 VSS_124 H40 AY21 VSS_221 VSS_322 AJ5
AL51 VSS_26 VSS_125 BL39 AN21 VSS_222 VSS_323 AG5
AJ51 VSS_27 VSS_126 BG39 AG21 VSS_223 VSS_324 AE5
AG51 VSS_28 VSS_127 BA39 AE21 VSS_224 VSS_325 AC5
AE51 VSS_29 VSS_128 E39 M21 VSS_225 VSS_326 AA5
AC51 VSS_30 VSS_129 C39 E21 VSS_226 VSS_327 W5
AA51 VSS_31 VSS_130 A39 A21 VSS_227 VSS_328 U5
W51 VSS_32 VSS_131 BD38 BD20 VSS_228 VSS_329 N5
U51 AU38 H20 L5
R51
N51
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
H38
BG37
BG19
AY19
VSS_229
VSS_230
VSS_231
VSS VSS_330
VSS_331
VSS_332
J5
G5
L51 VSS_36 VSS_135 AU37 M19 VSS_232 VSS_333 C5
J51 VSS_37 VSS_136 M37 E19 VSS_233 VSS_334 BH4
G51 VSS_38 VSS_137 E37 BD18 VSS_234 VSS_335 BE3
C51 VSS_39 VSS_138 BD36 N18 VSS_235 VSS_336 U3
BK50 VSS_40 VSS_139 AW36 H18 VSS_236 VSS_337 E3
AM50 VSS_41 VSS_140 H36 BL17 VSS_237 VSS_338 BC1
K50 VSS_42 VSS_141 BL35 BG17 VSS_238 VSS_339 AW1
BG49 VSS_43 VSS_142 BG35 AY17 VSS_239 VSS_340 AR1
E49 VSS_44 VSS_143 AY35 M17 VSS_240 VSS_341 AL1
C C
C49 VSS_45 VSS_144 AU35 E17 VSS_241 VSS_342 AG1
BD48 VSS_46 VSS_145 AL35 A17 VSS_242 VSS_343 AC1
BB48 VSS_47 VSS_146 AG35 BD16 VSS_243 VSS_344 W1
AY48 VSS_48 VSS_147 AE35 AN16 VSS_244 VSS_345 N1
AV48 VSS_49 VSS_148 AA35 AG16 VSS_245 VSS_346 J1
AT48 VSS_50 VSS_149 Y35 AE16 VSS_246 VSS_347 AU43
AP48 VSS_51 VSS_150 M35 Y16 VSS_247 VSS_348 BB42
AM48 VSS_52 VSS_151 E35 W16 VSS_248 VSS_349 AW38
AK48 VSS_53 VSS_152 A35 N16 VSS_249 VSS_350 BA35
AH48 VSS_54 VSS_153 BD34 H16 VSS_250 VSS_351 L29
AF48 VSS_55 VSS_154 AU34 BG15 VSS_251 VSS_352 N28
AD48 VSS_56 VSS_155 AN34 AY15 VSS_252 VSS_353 N22
AB48 VSS_57 VSS_156 H34 AN15 VSS_253 VSS_354 N20
Y48 VSS_58 VSS_157 BL33 AD15 VSS_254 VSS_355 N14
V48 VSS_59 VSS_158 BG33 AC15 VSS_255 VSS_356 AL13
T48 VSS_60 VSS_159 AY33 R15 VSS_256 VSS_357 B10
P48 VSS_61 VSS_160 E33 M15 VSS_257 VSS_358 AN13
M48 VSS_62 VSS_161 BD32 E15 VSS_258
K48 VSS_63 VSS_162 AU32 BD14 VSS_259 VSS_359 N42
H48 VSS_64 VSS_163 AN32 H14 VSS_260 VSS_360 N40
BL47 VSS_65 VSS_164 AG32 BL13 VSS_261 VSS_361 N38
BG47 VSS_66 VSS_165 AC32 BG13 VSS_262 VSS_362 M39
E47 VSS_67 VSS_166 Y32 AY13 VSS_263
C47 VSS_68 VSS_167 H32 AU13 VSS_264
A47 VSS_69 VSS_168 B32 AR13 VSS_265 VSS_NCTF_1 AJ38
BD46 VSS_70 VSS_169 BJ31 AJ13 VSS_266 VSS_NCTF_2 AH38
AY46 VSS_71 VSS_170 BG31 AC13 VSS_267 VSS_NCTF_3 AD38
AM46 VSS_72 VSS_171 AY31 AA13 VSS_268 VSS_NCTF_4 AC38
AK46 VSS_73 VSS_172 AN31 W13 VSS_269 VSS_NCTF_5 T35
AH46 M31 U13 R35

VSS NCTF
VSS_74 VSS_173 VSS_270 VSS_NCTF_6
BG45 VSS_75 VSS_174 E31 M13 VSS_271 VSS_NCTF_7 AT32
AE45 VSS_76 VSS_175 N30 E13 VSS_272 VSS_NCTF_8 AR32
B B
AC45 VSS_77 VSS_176 H30 A13 VSS_273 VSS_NCTF_9 U32
AA45 VSS_78 VSS_177 AN29 BD12 VSS_274 VSS_NCTF_10 R32
W45 VSS_79 VSS_178 AJ29 AV12 VSS_275 VSS_NCTF_11 T28
R45 VSS_80 VSS_179 M29 AP12 VSS_276 VSS_NCTF_12 R28
N45 VSS_81 VSS_180 A29 AM12 VSS_277 VSS_NCTF_13 AT25
E45 VSS_82 VSS_181 AW28 AK12 VSS_278 VSS_NCTF_14 AR25
BD44 VSS_83 VSS_182 AN28 AB12 VSS_279 VSS_NCTF_15 T24
BB44 VSS_84 VSS_183 AD28 V12 VSS_280 VSS_NCTF_16 R24
AV44 VSS_85 VSS_184 AC28 P12 VSS_281 VSS_NCTF_17 AN19
AK44 VSS_86 VSS_185 Y28 H12 VSS_282 VSS_NCTF_18 AJ19
AH44 VSS_87 VSS_186 W28 BG11 VSS_283 VSS_NCTF_19 AA19
AF44 VSS_88 VSS_187 H28 AG11 VSS_284 VSS_NCTF_20 Y19
AD44 VSS_89 VSS_188 F28 E11 VSS_285 VSS_NCTF_21 T19
K44 VSS_90 VSS_189 AN27 BD10 VSS_286 VSS_NCTF_22 R19
H44 VSS_91 VSS_190 AJ27 AY10 VSS_287 VSS_NCTF_23 AN18
BL43 VSS_92 VSS_191 M27 AP10 VSS_288
BG43 VSS_93 VSS_192 BF26 H10 VSS_289
AY43 VSS_94 VSS_193 BD26 BL9 VSS_290
AR43 VSS_95 VSS_194 N26 BG9 VSS_291
W43 VSS_96 VSS_195 H26 E9 VSS_292
R43 VSS_97 VSS_196 BJ25 A9 VSS_293 VSS_SCB_1 BL55
M43 AY25 BD8 BL1

VSS SCB
VSS_98 VSS_197 VSS_294 VSS_SCB_2
E43 VSS_99 VSS_198 AU25 BB8 VSS_295 VSS_SCB_3 A55
AY8 VSS_296 VSS_SCB_4 D1
AV8 VSS_297 VSS_SCB_5 B55
CANTIGA GMCH SFF_FCBGA1363 AT8 B2
VSS_298 VSS_SCB_6
AP8 VSS_299 VSS_SCB_7 A4

CANTIGA GMCH SFF_FCBGA1363

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 13 of 41
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

+V_DDR3_DIMM_REF

(9) DDR_A_DQS#[0..7]
JDIMM1
(9) DDR_A_D[0..63] 1 VREF_DQ VSS 2
3 4 DDR_A_D4
+1.5V DDR_A_D0 VSS DQ4 DDR_A_D5
(9) DDR_A_DM[0..7] 5 DQ0 DQ5 6
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
(9) DDR_A_DQS[0..7] 9 VSS DQS0# 10

1
DDR_A_DM0 11 12 DDR_A_DQS0
R1577 DM0 DQS0
(9) DDR_A_MA[0..14] 13 VSS VSS 14
1K_0402_1% DDR_A_D2 15 16 DDR_A_D6
+V_DDR3_DIMM_REF DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 20

2
D DDR_A_D8 VSS VSS DDR_A_D12 D
21 DQ8 DQ12 22

0.1U_0402_16V4Z
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13

1
2.2U_0805_16V4Z
25 VSS VSS 26

C1460
1 1 R1578 DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# (8,15)

C1459
1K_0402_1% 31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34

2
2 2 DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
(8) DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA (8)
Layout Note: 75 VDD VDD 76
77 NC A15 78
Place near JP4 (9) DDR_A_BS2
DDR_A_BS2 79 80 DDR_A_MA14
C BA2 A14 C
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
Layout Note: Place these 4 Caps near Command 85 A9 A7 86
87 88
and Control signals of DIMMA DDR_A_MA8 89
VDD VDD
90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
+1.5V 93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD VDD 100
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U_B2_2.5VM_R15M

1 M_CLK_DDR0 101 102 M_CLK_DDR1

(8) M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 (8)
1 1 1 1 1 1 1 1 1 1 C1471 M_CLK_DDR#0 103 104 M_CLK_DDR#1
(8) M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 (8)
C1467

C1468

C1469

C1470
C1461

C1462

C1463

C1464

C1465

C1466

+ 105 106
DDR_A_MA10 VDD VDD DDR_A_BS1
107 A10/AP BA1 108 DDR_A_BS1 (9)
DDR_A_BS0 109 110 DDR_A_RAS#
2 2 2 2 2 2 2 2 2 2 2 (9) DDR_A_BS0 BA0 RAS# DDR_A_RAS# (9)
111 VDD VDD 112
Change package 072709. DDR_A_WE# 113 114 DDR_CS0_DIMMA#
DDR_CS0_DIMMA# (8)
(9) DDR_A_WE# DDR_A_CAS# WE# S0# M_ODT0
(9) DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 (8)
117 VDD VDD 118
DDR_A_MA13 M_ODT1 +V_DDR3_DIMM_REF
119 A13 ODT1 120 M_ODT1 (8)
DDR_CS1_DIMMA# 121 122
(8) DDR_CS1_DIMMA# S1# NC R1580
123 VDD VDD 124
125 126 DDR_VREF_CA_DIMMA 1 2
TEST VREF_CA
127 VSS VSS 128
DDR_A_D32 129 130 DDR_A_D36 0_0402_5%
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132
Layout Note: 133 VSS VSS 134

0.1U_0402_16V4Z
DDR_A_DQS#4 135 136 DDR_A_DM4
Place near JP4.203 & JP4.204 DQS4# DM4

2.2U_0603_6.3V4Z
DDR_A_DQS4 137 138 1 1
DQS4 VSS DDR_A_D38
139 VSS DQ38 140

C1472

C1473
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS 144
B DDR_A_D44 2 2 B
145 VSS DQ44 146
+0.75V DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
153 DM5 DQS5 154
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

155 VSS VSS 156

DDR_A_D42 157 158 DDR_A_D46
DQ42 DQ46
10U_0805_6.3V6M

2 2 2 2 1 DDR_A_D43 159 160 DDR_A_D47

DQ43 DQ47
C1478

161 VSS VSS 162

DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
1 1 1 1 2
C1474

C1475

C1476

C1477

167 VSS VSS 168

DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS DDR_A_D60
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS DQS7# DDR_A_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
+1.5V DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 196
EMI 1215 +3VS
R1581 1 2 10K_0402_5% 197
199
VSS
SA0
VDDSPD
VSS
EVENT#
SDA
198
200
PM_EXTTS#0
CLK_SMBDATA
PM_EXTTS#0 (8)
CLK_SMBDATA (15,16)
0.1U_0402_16V4Z

201 202 CLK_SMBCLK

SA1 SCL CLK_SMBCLK (15,16)
2.2U_0603_6.3V4Z

1 1 203 VTT VTT 204 +0.75V

1
10K_0402_5%

1 1
1

C1479 C1480 C1482 C1483 205 206

GND1 BOSS1
R1582

A C1481 A
207 GND2 BOSS2 208
2 2
10P_0402_50V8J

47P_0402_50V8J

120P_0402_50V8
DDR3 SO-DIMM A
2

2 2
2

FOX_AS0A626-U2RN-7F
CONN@ +0.75V SP07000IM00 REVERSE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 14 of 41
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V
(9) DDR_B_DQS#[0..7]
+V_DDR3_DIMM_REF
(9) DDR_B_D[0..63]
JDIMM2
(9) DDR_B_DM[0..7] 1 VREF_DQ VSS 2
3 4 DDR_B_D4
DDR_B_D0 VSS DQ4 DDR_B_D5
(9) DDR_B_DQS[0..7] 5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
(9) DDR_B_MA[0..14] 9 VSS DQS0# 10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
DQ2 DQ6

C1484

C1485
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7
19 VSS VSS 20
D 2 2 DDR_B_D8 DDR_B_D12 D
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# (8,14)
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
Layout Note: DDR_B_D19
51 DQ18 DQ23 52
53 DQ19 VSS 54
Place near JDIMM2 55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 DQ24 DQ29 58
Layout Note: Place these 4 Caps near Command DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3
61 62
and Control signals of DIMMA DDR_B_DM3 63
VSS DQS3#
64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
+1.5V DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U_B2_2.5VM_R15M
1
1 1 1 1 1 1 1 1 1 1 C1496 DDR_CKE2_DIMMB
73 74 DDR_CKE3_DIMMB
(8) DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB (8)
C1492

C1493

C1494

C1495
C1486

C1487

C1488

C1489

C1490

C1491

+ 75 76
VDD VDD
77 NC A15 78
DDR_B_BS2 79 80 DDR_B_MA14
C 2 2 2 2 2 2 2 2 2 2 2 (9) DDR_B_BS2 BA2 A14 C
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
A8 A6
Change package 072709. DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
Layout Note: M_CLK_DDR2 101 102 M_CLK_DDR3
(8) M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 (8)
M_CLK_DDR#2 103 104 M_CLK_DDR#3
Place near JDIMM2.203 & JDIMM2.204 (8) M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 (8)
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 (9)
DDR_B_BS0 109 110 DDR_B_RAS#
(9) DDR_B_BS0 BA0 RAS# DDR_B_RAS# (9)
111 VDD VDD 112
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
+0.75V (9) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (8)
DDR_B_CAS# 115 116 M_ODT2
(9) DDR_B_CAS# CAS# ODT0 M_ODT2 (8)
117 VDD VDD 118
DDR_B_MA13 M_ODT3 +V_DDR3_DIMM_REF
119 A13 ODT1 120 M_ODT3 (8)
DDR_CS3_DIMMB# 121 122
(8) DDR_CS3_DIMMB# S1# NC
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

123 124 R1583

VDD VDD DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2 0_0402_5%
10U_0805_6.3V6M

2 2 2 2 1 127 VSS VSS 128

C1501

DDR_B_D32 129 130 DDR_B_D36

DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS VSS 134
1 1 1 1 2
C1497

C1498

C1499

C1500

0.1U_0402_16V4Z
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS4# DM4

2.2U_0603_6.3V4Z
DDR_B_DQS4 137 138 1 1
DQS4 VSS

C1502
139 140 DDR_B_D38
VSS DQ38

C1503
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39
143 DQ35 VSS 144
B DDR_B_D44 2 2 B
145 VSS DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
153 DM5 DQS5 154
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
+1.5V 161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
EMI 1215 DDR_B_DQS#6
167
169
DQ49
VSS
DQS6#
DQ53
VSS
DM6
168
170 DDR_B_DM6
DDR_B_DQS6 171 172
DQS6 VSS DDR_B_D54
173 VSS DQ54 174
1 1 DDR_B_D50 175 176 DDR_B_D55
DQ50 DQ55
1

C1504 C1505 DDR_B_D51 177 178

C1506 DQ51 VSS DDR_B_D60
179 VSS DQ60 180
10P_0402_50V8J

47P_0402_50V8J

120P_0402_50V8 DDR_B_D56 181 182 DDR_B_D61

2

2 2 DDR_B_D57 DQ56 DQ61

183 DQ57 VSS 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
195
DQ59
VSS
DQ63
VSS 196 same with intel DDR3 CRB connection
R1584 1 2 10K_0402_5% 197 198 PM_EXTTS#1
SA0 EVENT# PM_EXTTS#1 (8)
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBDATA (14,16)
1 2 201 202 CLK_SMBCLK
SA1 SCL CLK_SMBCLK (14,16)
0.1U_0402_16V4Z

R1585 10K_0402_5% 203

2.2U_0603_6.3V4Z

204

C1507
1 1
C1508
VTT VTT +0.75V
DDR3 SO-DIMM B
205 206
A
2 2
207
GND1
GND2
BOSS1
BOSS2 208 REVERSE A

FOX_AS0A626-U2RN-7F
SP07000IO00 +0.75VCONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 15 of 41
5 4 3 2 1
 A B C D E F G H

FSLC FSLB FSLA CPU SRC PCI +CLK_VDDSRC Clock Generator

CLKSEL2 CLKSEL1 CLKSEL0 +CLK_VDD
MHz MHz MHz L2 2 1 FBMA-L11-201209-221LMA30T_0805
+VCCP
C1102 C1109 C1455 C1103 C1104 C1105 C1106 C1107 C1108 +3VS L3 2 1 FBMA-L11-201209-221LMA30T_0805

10U_0805_10V4Z

0.1U_0402_16V4Z

47P_0402_50V8J

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0 0 0 266 100 33.3 1 1 1 1 1 1 1 1 1 C1110 C1117 C1456 C1111 C1112 C1113 C1114

10U_0805_10V4Z

0.1U_0402_16V4Z

47P_0402_50V8J

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1

0 1 0 200 100 33.3 @

2 2 2 2 2 2 2 2 2 @
2 2 2 2 2 2 2
0 1 1 166 100 33.3
add it.071109
Table : ICS9LPRS387 add it.071109
1 1

CLK_REQ# Control Free-Run

CR#_10(WLAN) PCIEX10 PCIEX0
U27
CR#_6(MCH) PCIEX6 PCIEX1 +1.5VS +CLK_VDD +CLK_VDD ICS9LPRS387, PN:SA000020H10
CR#_4(NEW CARD) PCIEX4 9 CLK_SMBDATA CLK_SMBDATA (14,15)
SLG8SP556V, PN:SA000020K00 SDATA
1
R1551
2
0_0603_5%
6 VDDREF CLK_SMBCLK
RAM
CR#_9(MINI CARDII) PCIEX9 SCLK 10 CLK_SMBCLK (14,15)
19 VDD48
+1.5VSCLK_VDD
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable]
1 2 72 71 CLK_CPU_BCLK
VDDCPU CPUT0_LPR_F CLK_CPU_BCLK (4)
R1552 @ 0_0603_5% CPU
0.1U_0402_16V4Z 12 70 CLK_CPU_BCLK#
+3VS VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# (4)
1 1 1 1
C1450 C1451 C1452 C1453 27
CLK_PCI2 VDDPLL3 CLK_MCH_BCLK
1 2 CPUT1_LPR_F 68 CLK_MCH_BCLK (8)
R343 10K_0402_5% 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 55 NB
2 2 2 2 VDDSRC CLK_MCH_BCLK#
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed) CPUC1_LPR_F 67 CLK_MCH_BCLK# (8)

mount to Enable ITP_CLK add it.062309 +CLK_VDDSRC 52 VDDSRC_IO CLK_DREF_96M

1 2 SRCT0_LPR/DOTT_96_LPR 24 CLK_DREF_96M (8)
R344 @ 10K_0402_5% 38 NB
+3VS VDDSRC_IO CLK_DREF_96M#
+CLK_VDDSRC 1 2 SRCC0_LPR/DOTC_96_LPR 25 CLK_DREF_96M# (8)
R1563 0_0603_5% 62 VDDSRC_IO
2

+3VS 1 2 31 28 CLK_DREF_SSC
+1.5VSCLK_VDD VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 CLK_DREF_SSC (8)
R342 R1564 @ 0_0603_5% 1 NB_SSC
10K_0402_5% C1454 66 29 CLK_DREF_SSC#
VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 CLK_DREF_SSC# (8)
@1 2 @
R379 10K_0402_5% 0.1U_0402_16V4Z 23
1

2 CK505_PWRGD 2 VDD96_IO CLK_PCIE_SATA 2

SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA (18)
add it.073109 SATA
1

CLK_PCI5 D CLK_PCIE_SATA#
1 2 SRCC2_LPR/SATAC_LPR 33 CLK_PCIE_SATA# (18)
R345 10K_0402_5% 2 H_STP_CPU# 53
CLKEN# (40) (19) H_STP_CPU# CPU_STOP#
G
+3VS CLK_PCI5=0, Pin63,64 is SRC_CLK S Q3 H_STP_PCI# 54 35 CLK_PCIE_ICH
(19) H_STP_PCI# CLK_PCIE_ICH (19)
3

PCI_STOP# SRCT3_LPR
CLK_PCI5=1, Pin63,64 is ITP_CLK 2N7002_SOT23
CLK_PCIE_ICH#
ICH
@ SRCC3_LPR 36 CLK_PCIE_ICH# (19)
@1 2
R380 10K_0402_5%
13 39 CLK_PCIE_WWAN
PCI1 SRCT4_LPR CLK_PCIE_WWAN (28)
CLK_PCI4 CLK_PCI2 CLK_PCIE_WWAN#
WWAN
1 2 14 PCI2/TME SRCC4_LPR 40 CLK_PCIE_WWAN# (28)
R346 10K_0402_5%
CLK_PCI4=0, Pin28, 29 is SRC_CLK CLK_PCI_LPC R348 2 1 33_0402_5% CLK_PCI3 15
(29) CLK_PCI_LPC PCI3
Pin24, 25 is DOT96_CLK 57 CLK_MCH_3GPLL
SRCT6_LPR CLK_MCH_3GPLL (8)
CLK_PCI4 16 3G_PLL
PCI4/27_SELECT CLK_MCH_3GPLL#
SRCC6_LPR 56 CLK_MCH_3GPLL# (8)
CLK_PCI_ICH R349 2 1 33_0402_5% CLK_PCI5 17
(17) CLK_PCI_ICH PCI_F5/ITP_EN

SRCT7_LPR 61
0_0402_5% 2 1 R350 CK505_PWRGD1 UMA: disable this pair by BIOS
(19) CK_PWRGD CK_PWRGD/PD#
1 2 CK_PWRGD 0_0402_5% 2 @ 1 R351 60
(8,19,40) VGATE SRCC7_LPR
R347 @ 10K_0402_5%
C1120
1 2 CLK_XTALIN 5 64
+VCCP X1 CPUT2_ITP_LPR/SRCT8_LPR
1

22P_0402_50V8J CLK_XTALOUT 4 63
22P_0402_50V8J Y3 X2 CPUC2_ITP_LPR/SRCC8_LPR
2

R352 14.31818MHz_20P_FSX8L14.318181M20FDB
@ 56_0402_5% C1121 11 44 CLK_PCIE_MINI2
CLK_PCIE_MINI2 (28)
2

NC SRCT9_LPR
3 R353 R354
1 2
CLK_PCIE_MINI2#
WLAN 3
SRCC9_LPR 45 CLK_PCIE_MINI2# (28)
2.2K_0402_5% 1K_0402_5% Change to use 22pf.091509
1

CLKSEL0 1 2 1 2 CLK_ICH_48M R355 2 1 CLKSEL0 20

MCH_CLKSEL0 (8) (19) CLK_ICH_48M USB_48MHz/FSLA
CLK_SD_48M R358 2 @ 133_0402_5% 50
(30) CLK_SD_48M SRCT10_LPR
22_0402_5% CLKSEL1 2 FSLB/TEST_MODE
1 2 1 2 CPU_BSEL0 (5) SRCC10_LPR 51
R356 R357 CLK_ICH_14M R359 2 1 CLKSEL2 7
(19) CLK_ICH_14M FSLC/TEST_SEL/REF0
@ 1K_0402_5% 0_0402_5% 1 1 1 33_0402_5%
10P_0402_50V8J

C1289
10P_0402_50V8J

C1266
10P_0402_50V8J

C1264

8 48 CLK_PCIE_LAN
REF1 SRCT11_LPR CLK_PCIE_LAN (28)
+VCCP CLK_PCIE_LAN#
GLAN
SRCC11_LPR 47 CLK_PCIE_LAN# (28)
2 @ 2 @ 2 @
69 GNDCPU
2

R360
@ 1K_0402_5% 3 37
GNDREF CR#3
add it for EMI.072409. 1 2 +3VS
R361 18 41 R363 10K_0402_5%
GNDPCI CR#4 WWAN_CLKREQ# (28)
1K_0402_5% 1 2 +3VS
1

CLKSEL1 1 2 22 58 R364 10K_0402_5% 2 R365 1

MCH_CLKSEL1 (8) GND48 CR#6 MCH_CLKREQ# (8)
0_0402_5%
30 GND CR7# 65
1 2 1 2 +3VS R362 1 2
CPU_BSEL1 (5) +3VS
R366 R367 4.7K_0402_5% 26 43 R368 10K_0402_5%
GND CR#9 MINI2_CLKREQ# (28)
@ 0_0402_5% 0_0402_5% 1 2 +3VS
2

<BOM Structure> 34 GNDSRC CR10# 49

1 2 +3VS
(19,28) ICH_SMBDATA 6 1 CLK_SMBDATA 59 46 R370 10K_0402_5%
+VCCP GNDSRC CR#11 LAN_CLKREQ# (28)
1 2 +3VS
2N7002DW-T/R7_SOT363-6 42 21 R371 10K_0402_5%
GNDSRC CR#A SATA_CLKREQ# (19)
Q4A 73 GND_THERMAL_PAD
2

R372
@ 1K_0402_5% ICS9LPRS387BKLFT_MLF72_10x10
4 +3VS R369 4
R373 R374 4.7K_0402_5%
10K_0402_5% 1K_0402_5% 1 2 +3VS
1

CLKSEL2 1 2 1 2 MCH_CLKSEL2 (8)

(19,28) ICH_SMBCLK 3 4 CLK_SMBCLK

1 2 1 2 CPU_BSEL2 (5)
R375 R376
@ 0_0402_5% 0_0402_5% Q4B Security Classification Compal Secret Data Compal Electronics, Inc.
2N7002DW-T/R7_SOT363-6 2009/02/27 2010/01/21 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAV30 M/B LA-5451P Schematic
Date: Tuesday, October 20, 2009 Sheet 16 of 41
A B C D E F G H
 5 4 3 2 1

+3VS

1 2 PCI_DEVSEL#
R159 8.2K_0402_5%
1 2 PCI_STOP#
R160 8.2K_0402_5%
1 2 PCI_TRDY#
R161 8.2K_0402_5%
1 2 PCI_FRAME# U5B
R162 8.2K_0402_5% A11 G4 PCI_REQ0#
PCI_PLOCK# AD0 REQ0# PCI_GNT0#
D
1
R163
2
8.2K_0402_5%
B12
A10
AD1 PCI GNT0# E1
A9 PCI_REQ1# D
PCI_IRDY# AD2 REQ1#/GPIO50
1 2 C12 AD3 GNT1#/GPIO51 E12
R164 8.2K_0402_5% A8 B11 PCI_REQ2#
PCI_SERR# AD4 REQ2#/GPIO52
1 2 A12 AD5 GNT2#/GPIO53 C10
R165 8.2K_0402_5% E10 D6 PCI_REQ3#
PCI_PERR# AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C11 AD7 GNT3#/GPIO55 C6
R166 8.2K_0402_5% B9 AD8
D8 AD9 C/BE0# D10
A4 AD10 C/BE1# A5
E8 AD11 C/BE2# E6
A3 AD12 C/BE3# C9
D9 AD13
C8 C3 PCI_IRDY#
+3VS AD14 IRDY#
C2 AD15 PAR B1
D7 AD16 PCIRST# T3
B3 A7 PCI_DEVSEL#
PCI_PIRQA# AD17 DEVSEL# PCI_PERR#
1 2 D11 AD18 PERR# D4
R167 8.2K_0402_5% B6 C5 PCI_PLOCK#
PCI_PIRQB# AD19 PLOCK# PCI_SERR#
1 2 D5 AD20 SERR# H5
R168 8.2K_0402_5% D3 A6 PCI_STOP#
PCI_PIRQC# AD21 STOP# PCI_TRDY#
1 2 F4 AD22 TRDY# A2
R169 8.2K_0402_5% E3 B8 PCI_FRAME#
PCI_PIRQD# AD23 FRAME#
1 2 E4 AD24
R170 8.2K_0402_5% B2 A21 PLT_RST#
AD25 PLTRST# PLT_RST# (8,29)
1 2 PCI_PIRQE# C4 B5 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH (16)
R171 8.2K_0402_5% C1 T1
AD27 PME# T12
1 2 PCI_PIRQF# D1
R172 8.2K_0402_5% AD28
E2 AD29
1 2 PCI_PIRQG# J4
R173 8.2K_0402_5% AD30
H2 AD31
2 1 PCI_PIRQH# R108 1 2 0_0603_5%
R174 8.2K_0402_5%
C
1 2 PCI_REQ0# PCI_PIRQA# F1
Interrupt I/F G3 PCI_PIRQE# C
PIRQA# PIRQE#/GPIO2 +3VS
R175 8.2K_0402_5% PCI_PIRQB# F5 G1 PCI_PIRQF# add it.062609
PCI_REQ1# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
1 2 F2 PIRQC# PIRQG#/GPIO4 F3
R176 8.2K_0402_5% PCI_PIRQD# C7 H4 PCI_PIRQH#
PIRQD# PIRQH#/GPIO5

5
1 2 PCI_REQ2# U31
R178 8.2K_0402_5% ICH9-M SFF ES_FCBGA569 PLT_RST# 2

P
PCI_REQ3# B
1 2 Y 4 PLT_RST_BUF# (28)
R179 8.2K_0402_5% 1 A

1
NC7SZ08P5X_NL_SC70-5

3
@ R396
100K_0402_5%

2
A16 swap override Strap Boot BIOS Strap Place closely pin B10
B B
Low= A16 swap override Enble CLK_PCI_ICH
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

1
@
R180
10_0402_5%

0 1 SPI

2
PCI_GNT3# 1
@
1 0 PCI C235
1

8.2P_0402_50V
2
R181
@ 1K_0402_5% 1 1 LPC *
2

PCI_GNT0#
(19) KBC_SPI_CS1#
1

R182 R183
1K_0402_5% @ 1K_0402_5%
@
2

A A

DEL J3. 9/29

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 17 of 41
5 4 3 2 1
 5 4 3 2 1

+RTCVCC

1 2 LAN100_SLP
R184 330K_0402_1%
1 2 SM_INTRUDER#
R185 1M_0402_5%
1 2 ICH_INTVRMEN
R186 330K_0402_1%

0_0402_5%

0_0402_5%
R188

R189
1 2 ICH_SRTCRST#

2
R187 20K_0402_5%
Change from 180K to 20K C236
1
& 0.1u to 1u. 9/29
1U_0603_10V4Z @ @

1
D 2 D

ICH_RSVD HDA_SDOUT_CODEC Description

0 0 RV U5A
LPC_AD[0..3] (29)
ICH_RTCX1 F25 H3 LPC_AD0 9/27
0 1 XOR ICH_RTCX2 G25
RTCX1
RTCX2
FWH0/LAD0
FWH1/LAD1 J3 LPC_AD1
R318 K5 LPC_AD2
1 0 Normal(D) +RTCVCC 1 2 ICH_RTCRST# G24 RTCRST#
FWH2/LAD2
FWH3/LAD3 L3 LPC_AD3 Del PU R203~R204 9/27
20K_0402_5% ICH_SRTCRST# C24
1 1 PCIE Bit1

RTC
LPC
SRTCRST# for H_DPRSTP# &

1U_0603_10V4Z
SM_INTRUDER# C23 J2
INTRUDER# FWH4/LFRAME# LPC_FRAME# (29)
XOR CHAIN ENTRANCE STRAP:RSVD 1 1 H_DPSLP#. +VCCP
C1044 CLRP2 ICH_INTVRMEN E25 H1
+3VS LAN100_SLP INTVRMEN LDRQ0#
D25 LAN100_SLP LDRQ1#/GPIO23 J1 T46 PAD
1U_0603_10V4Z @

2
2 2 EC_GA20
G22 GLAN_CLK A20GATE N3 EC_GA20 (29)
1 2 HDA_SDOUT AB23 R192
A20M# H_A20M# (4)
R191 @ 1K_0402_5% close to DIMM D14 56_0402_5%
LAN_RSTSYNC
1 2 ICH_RSVD
ICH_RSVD (19) Change footprint to Cap.062309 AE23 H_DPRSTP_R# R194 1 2 0_0402_5% H_DPRSTP# (5,8,40)
R193 @ 1K_0402_5% DPRSTP#
A14 AE24

LAN / GLAN
H_DPSLP# (5)

1
LAN_RXD0 DPSLP#
D12 LAN_RXD1
B14 AD25 H_FERR#_R R195 1 2 56_0402_5% H_FERR#
LAN_RXD2 FERR# H_FERR# (4)
D13 LAN_TXD0 CPUPWRGD AE22 H_PWRGOOD (5)
C13 LAN_TXD1
Place Close to U8.
A13 AD23 +3VS
LAN_TXD2 IGNNE# H_IGNNE# (4)

CPU
D15 GPIO56 INIT# AE21 H_INIT# (4)
AD24 +VCCP EC_GA20 R196 1 2 10K_0402_5%
C INTR H_INTR (4) C
H22 L1 EC_KBRST# EC_KBRST# R197 1 2 10K_0402_5%
GLAN_COMPI RCIN# EC_KBRST# (29)
+1.5VS R198 1 2 24.9_0402_1% GLAN_COMP H21 GLAN_COMPO

1
NMI AD21 H_NMI (4)
R1553 33_0402_5% 1 2 HDA_BITCLK AE7 AC21 H_SMI# R201
(25) HDA_BITCLK_CODEC HDA_BIT_CLK SMI# H_SMI# (4)
R1554 33_0402_5% 1 2 HDA_SYNC AB7 56_0402_5%
(25) HDA_SYNC_CODEC HDA_SYNC
AC25 H_STPCLK#
STPCLK# H_STPCLK# (4)
R1555 33_0402_5% 1 2 HDA_RST# AA7
(25) HDA_RST#_CODEC

2
HDA_RST# THRMTRIP_ICH# R206
THRMTRIP# AC23 1 2 54.9_0402_1% H_THERMTRIP# (4,8)
Codec (25) HDA_SDIN0 AB6 HDA_SDIN0
placed within 2" from
PAD T65 AE6 HDA_SDIN1 TP11 AC22 T48 PAD ICH9M
GMCH (8) HDA_SDIN2 AC6

IHDA
HDA_SDIN2
add it 062609. AA5 HDA_SDIN3
SATA4RXN AD12
(25) HDA_SDOUT_CODEC
R1556 1 2 HDA_SDOUT AC7 HDA_SDOUT SATA4RXP AE12
33_0402_5% AB12
SATA4TXN
AD8 HDA_DOCK_EN#/GPIO33 SATA4TXP AA12
PAD T49 AB8 HDA_DOCK_RST#/GPIO34
+3VS 2 1 SATA5RXN AC11
R209 10K_0402_5% AC9 AD11
(30) SATA_LED# SATALED# SATA5RXP
SATA5TXN AB10
(21) SATA_RXN0_C AE14 SATA0RXN SATA5TXP AA10
(21) SATA_RXP0_C AD14 SATA0RXP

SATA
SATA_TXN0 C1153 SATA_TXN0_C AC15 CLK_PCIE_SATA#
HDD (21) SATA_TXN0
SATA_TXP0 C1154
1
1
2
20.01U_0402_16V7K SATA_TXP0_C AD15 SATA0TXN SATA_CLKN AC16
AB16 CLK_PCIE_SATA
CLK_PCIE_SATA# (16)
(21) SATA_TXP0 SATA0TXP SATA_CLKP CLK_PCIE_SATA (16)
0.01U_0402_16V7K
(21) SATA_RXN1_C AD13 SATA1RXN SATARBIAS# AD10
0.01U_0402_16V7K AC13 AE10 R212 1 2 24.9_0402_1%
(21) SATA_RXP1_C SATA1RXP SATARBIAS
SATA_TXN1 C244 SATA_TXN1_C
ODD (21) SATA_TXN1
SATA_TXP1 C245
1
1
2
2 SATA_TXP1_C
AA14
AB14
SATA1TXN Within 500 mils
(21) SATA_TXP1 SATA1TXP
0.01U_0402_16V7K ICH9-M SFF ES_FCBGA569

B ICH_RTCX1 B

R215
1 2 ICH_RTCX2

10M_0402_5%
+RTCBATT

2
C246 Y2 C247

4
1 1 R397
1K_0402_5%

IN

OUT
15P_0402_50V8J

12P_0402_50V8J
1 2 HDA_BITCLK
(8) HDA_BITCLK_MCH

1 1
R416 33_0402_5% 2 2
HDA_SYNC

NC

NC
(8) HDA_SYNC_MCH 1 2 D14
R410 33_0402_5%
HDA for GMCH 1 2 HDA_RST#
(8) HDA_RST#_MCH

3
R414 33_0402_5%
(8) HDA_SDOUT_MCH 1 2 HDA_SDOUT +RTCVCC
R415 33_0402_5%

2
32.768KHZ_12.5P_MC-306
BAS40-04_SOT23-3
+CHGRTC
1
Change use SJ132P7K220.091109. C1155

0.1U_0402_16V4Z
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 18 of 41
5 4 3 2 1
 5 4 3 2 1
+3VS
1 2 GPIO48 +3VALW
R271 10K_0402_5%
1 2 GPIO1

1
R220 10K_0402_5%
1 2 SERIRQ
R222 10K_0402_5% R223 R224
1 2 PM_CLKRUN# 2.2K_0402_5% 2.2K_0402_5%
R225 8.2K_0402_5% U5C

2
1 2 EC_THERM# (16,28) ICH_SMBCLK C18 SMBCLK SATA0GP/GPIO21 AE19 GPIO21
R227 @ 8.2K_0402_5% C15 AA18 GPIO19
(16,28) ICH_SMBDATA SMBDATA SATA1GP/GPIO19
1 2 GPIO19 LINKALERT# B21 AE20 NPCI_RST#

SATA
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

GPIO
SMB
R228 8.2K_0402_5% 9/21 ME__EC_CLK1 E18 AA20 GPIO37 PM_PWROK 1 2
SMLINK0 SATA5GP/GPIO37 EC_PWROK (29)
1 2 GPIO22 ME__EC_DATA1 A24 SMLINK1
R491 0_0402_5%

1
R231 8.2K_0402_5% K1 CLK_14M_ICH
+3VS CLK14 CLK_ICH_14M (16)
1 2 NPCI_RST# EC_SWI# C20 AB5 CLK_48M_ICH

Clocks
D (29) EC_SWI# RI# CLK48 CLK_ICH_48M (16) D
R232 10K_0402_5%
1 2 GPIO17 T5 R3 ICH_SUSCLK R492
SUS_STAT#/LPCPD# SUSCLK T50 PAD
R233 @ 8.2K_0402_5% XDP_DBRESET# C25 0_0402_5%
(4) XDP_DBRESET#

2
SYS_RESET#

1
1 2 GPIO21 D18 M_PWROK
SLP_S3# PM_SLP_S3# (29)
R234 8.2K_0402_5% R235 R236 PM_BMBUSY# L2 B20
(8) PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# (29)
1 2 GPIO37 @ 10K_0402_5% @ 10K_0402_5% D16
SLP_S5# PM_SLP_S5# (29)
R237 8.2K_0402_5% (29) EC_LID_OUT# EC_LID_OUT# A23 SMBALERT#/GPIO11
1 2 GPIO18 Add R621 in 12/03. E14 S4_STATE#

2
R238 10K_0402_5% H_STP_PCI# S4_STATE#/GPIO26
(16) H_STP_PCI# B15 STP_PCI#/GPIO15
GPIO57 R240 1 2 0_0402_5% R_STP_CPU# PM_PWROK R241 1 10K_0402_5%

SYS GPIO
1 2 (16) H_STP_CPU# A20 STP_CPU#/GPIO25 PWROK D23 2
R239 @ 10K_0402_5%
+3VALW PM_CLKRUN# M5 M1 DPRSLPVR 1 2
(29) PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR (8,40)
R243 0_0402_5%

Power MGT
1 2 LINKALERT# (28) PCIE_WAKE#
PCIE_WAKE# C21 WAKE# BATLOW# C16 ICH_LOW_BAT#
R244 10K_0402_5% SERIRQ L4
(29) SERIRQ SERIRQ
1 2 PCIE_WAKE# (29) EC_THERM#
EC_THERM# AD20 THRM# PWRBTN# U4 PBTN_OUT# (29)
LAN_RST 2 1
R245 10K_0402_5% 10K_0402_5% R273
1 2 EC_SWI# (8,16,40) VGATE
R247 1 2 0_0402_5% VRMPWRGD B24 VRMPWRGD LAN_RST# D22 LAN_RST
R246 10K_0402_5% R248 1 2 100K_0402_5%
1 2 XDP_DBRESET# PAD T51 A19 TP12 RSMRST# D19 SB_RSMRST#
R250 1K_0402_5%
1 2 S4_STATE# GPIO1
GPIO1 AE16 GPIO1 CK_PWRGD U1 CK_PWRGD_R 1 2 CK_PWRGD (16)
R252 10K_0402_5% CRT_DET AE18 R253 0_0402_5%
GPIO6
1 2 ICH_LOW_BAT# AD18 GPIO7 CLPWROK T4 M_PWROK
M_PWROK (8)
R254 10K_0402_5% B25
(29) EC_SMI# GPIO8
Add R321 in 10/03. (29) EC_SCI# C14 GPIO12 SLP_M# B23
D20 R257
GPIO13
1 2 GPIO24 GPIO17 AE17 GPIO17 CL_CLK0 C22 CL_CLK0
CL_CLK0 (8)
3.24K_0402_1%
R256 10K_0402_5% GPIO18 K3 A18 1 2 +3VS
GPIO18 CL_CLK1

0.1U_0402_16V4Z
PAD T52 AC8 GPIO20

1
453_0402_1%
GPIO22 AC19 E22 CL_DATA0
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 (8)

Controller Link
1 2 ME__EC_CLK1 D17 B18 1

GPIO
PAD T53 GPIO27 CL_DATA1

R260
C R259 10K_0402_5% C
PAD T54 E20 GPIO28
1 2 ME__EC_DATA1 (16) SATA_CLKREQ# M4 SATACLKREQ#/GPIO35 CL_VREF0 F21 CL_VREF0_ICH

C263
R261 10K_0402_5% +3VS 1 2 GPIO38 AB18 A17

2
SLOAD/GPIO38 CL_VREF1 2
R262 @ 8.2K_0402_5%
PAD T55
GPIO39 AC18 Del CL_VREF1_ICH.072709.
GPIO48 SDATAOUT0/GPIO39 CL_RST#
AB19 SDATAOUT1/GPIO48 CL_RST0# C17 CL_RST# (8)
+3VALW NU it 073109. AC20 B17
PAD T56 GPIO49 CL_RST1#
GPIO57 A16
RP29 R264 1 GPIO57/CLGPIO5
+3VS 2 @ 1K_0402_5% MEM_LED/GPIO24 A22 GPIO24
GPIO24
5 4 USB_OC#7 SB_SPKR K4 E16
(25) SB_SPKR SPKR GPIO10/SUS_PWR_ACK
6 3 USB_OC#5 MCH_ICH_SYNC# AB20 A15 2 1 +3VALW
(8) MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
7 2 USB_OC#0 ICH_RSVD C19 D21 R406 100K_0402_5%
(18) ICH_RSVD TP3 WOL_EN/GPIO9

MISC
8 1 USB_OC#4 PAD T57 AB17 2 1
TP8 D15 ACIN (29,32)
PAD T58 AC17 TP9
10K_1206_8P4R_5% PAD T59 AD17 CH751H-40PT_SOD323-2
TP10 GPIO9
T64 PAD
1 2 USB_OC#6 ICH9-M SFF ES_FCBGA569
R270 10K_0402_5% U5D add it.062309
1 2 GPIO44 (28) PCIE_PTX_C_IRX_N1 T25 PERN1 DMI0RXN V25 DMI_RXN0 DMI_RXN0 (8)
R272 10K_0402_5% DMI_RXP0

Direct Media Interface

(28) PCIE_PTX_C_IRX_P1 T24 PERP1 DMI0RXP V24 DMI_RXP0 (8)
1 2 USB_OC#2 3G (28) PCIE_ITX_C_PRX_N1 C265 1 2 0.1U_0402_10V7K PCIE_ITX_PRX_N1 R24 PETN1 DMI0TXN U24 DMI_TXN0 DMI_TXN0 (8)
R274 10K_0402_5% (28) PCIE_ITX_C_PRX_P1 C266 1 2 0.1U_0402_10V7K PCIE_ITX_PRX_P1 R23 PETP1 DMI0TXP U23 DMI_TXP0 DMI_TXP0 (8) Q11
add it.091109 MMBT3906_SOT23-3
P25 W23 DMI_RXN1 SB_RSMRST# 1 3

C
(28) PCIE_PTX_C_IRX_N2 PERN2 DMI1RXN DMI_RXN1 (8) EC_RSMRST# (29)
1 2 EC_LID_OUT# P24 W24 DMI_RXP1

E
(28) PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_RXP1 (8)
R269 10K_0402_5% WLAN (28) PCIE_ITX_C_PRX_N2 C269 1 2 0.1U_0402_10V7K PCIE_ITX_PRX_N2 P21 V21 DMI_TXN1 DMI_TXN1 (8)
PETN2 DMI1TXN

1
RP31 C270 1 2 0.1U_0402_10V7K PCIE_ITX_PRX_P2 P22 V22 DMI_TXP1

B
(28) PCIE_ITX_C_PRX_P2 DMI_TXP1 (8)

2
USB_OC#9 PETP2 DMI1TXP R407
5 4 1 2 +3VALW
6 3 USB_OC#10 N23 Y24 DMI_RXN2 DMI_RXN2 (8) 10K_0402_5% R408 4.7K_0402_5%
(28) PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN
7 2 USB_OC#11 N24 Y25 DMI_RXP2

PCI-Express
(28) PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_RXP2 (8)
8 1 GPIO42 GLAN (28) PCIE_ITX_C_PRX_N3 C271 1 2 0.1U_0402_10V7K PCIE_ITX_PRX_N3 M21 Y21 DMI_TXN2 DMI_TXN2 (8) D16A

2
PETN3 DMI2TXN
(28) PCIE_ITX_C_PRX_P3 C272 1 2 0.1U_0402_10V7K PCIE_ITX_PRX_P3 M22 PETP3 DMI2TXP Y22 DMI_TXP2 DMI_TXP2 (8) 1
10K_1206_8P4R_5% 6
B add it.062309 M25 AB24 DMI_RXN3 DMI_RXN3 (8) 2 B
PERN4 DMI3RXN DMI_RXP3
M24 PERP4 DMI3RXP AB25 DMI_RXP3 (8)
L24 AA23 DMI_TXN3 DMI_TXN3 (8) BAV99DW-7_SOT363
PETN4 DMI3TXN DMI_TXP3
L23 PETP4 DMI3TXP AA24 DMI_TXP3 (8)
D16B
K24 T21 CLK_PCIE_ICH# 4
PERN5 DMI_CLKN CLK_PCIE_ICH# (16)
K25 T22 CLK_PCIE_ICH 3
PERP5 DMI_CLKP CLK_PCIE_ICH (16)
K21 PETN5 5

1
+3VS
K22 PETP5 DMI_ZCOMP AB21
DMI_IRCOMP R276 1
Within 500 mils
DMI_IRCOMP AB22 2 24.9_0402_1% +1.5VS BAV99DW-7_SOT363 R409
H24 2.2K_0402_5%
PERN6/GLAN_RXN
2

H25 AE2 USB20_N0

PERP6/GLAN_RXP USBP0N USB20_N0 (28)
R712 J24 AD1 USB20_P0
USB20_P0 (28) USB port 1

2
PETN6/GLAN_TXN USBP0P USB20_N1
10K_0402_5% J23 PETP6/GLAN_TXP USBP1N AD3 USB20_N1 (28)
High: CRT Plugged USBP1P AD4 USB20_P1
USB20_P1 (28) USB Port 2
E24 AC2 USB20_N2
USB20_N2 (28)
1

SPI_CLK USBP2N
CRT_DET E23 SPI_CS0# USBP2P AC3 USB20_P2
USB20_P2 (28) SUB USB Port 1
F23 AC5 USB20_N3
(17) KBC_SPI_CS1# SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 (28)
1

D
USBP3P AB4 USB20_P3
USB20_P3 (28) WLAN
(23) CRT_DET# CRT_DET# 2 Q40 F22 AB2 USB20_N4 Place closely pin AF3 Place closely pin H1
SPI_MOSI USBP4N USB20_N4 (30)
Card Reader
SPI

G G23 AB1 USB20_P4

SPI_MISO USBP4P USB20_P4 (30)
S 2N7002_SOT23 AA3 USB20_N5
USB20_N5 (28)
3

USBP5N
(28) USB_OC#0
USB_OC#0 P4 OC0#/GPIO59 USBP5P AA2 USB20_P5
USB20_P5 (28) 3G CLK_48M_ICH CLK_14M_ICH
N4 Y1 USB20_N6
OC1#/GPIO40 USBP6N USB20_N6 (28)
add it.062309 (28) USB_OC#2
USB_OC#2 N1 USB Y2 USB20_P6
USB20_P6 (28) BT
OC2#/GPIO41 USBP6P

1
GPIO42 P5 W2 USB20_N7 @ @
OC3#/GPIO42 USBP7N USB20_N7 (22)
USB_OC#4 P1 OC4#/GPIO43 USBP7P W3 USB20_P7
USB20_P7 (22) CMOS Camera R283 R284
USB_OC#5 P2 V1 10_0402_5% 10_0402_5%
USB_OC#6 OC5#/GPIO29 USBP8N
M3 OC6#/GPIO30 USBP8P V2
USB_OC#7 M2 Y5

2
GPIO44 OC7#/GPIO31 USBP9N
P3 OC8#/GPIO44 USBP9P Y4
USB_OC#9 R1 U3 1 @ 1 @
A USB_OC#10 OC9#/GPIO45 USBP10N C273 C274 A
R4 OC10#/GPIO46 USBP10P U2
USB_OC#11 R2 V4
OC11#/GPIO47 USBP11N
add it.062309 V5 4.7P_0402_50V8C 4.7P_0402_50V8C
USBRBIAS USBP11P 2 2
AE5 USBRBIAS
AD5 USBRBIAS#
1

Within 500 mils ICH9-M SFF ES_FCBGA569

R287
22.6_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title
2

Take off ICH SPI ROM for HDCP.081009 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 19 of 41
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U5E

20 mils U5F B4 U5
VSS[001] VSS[107]
G17 VCCRTC VCC1_05[01] L11 B7 VSS[002] VSS[108] U10

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCC1_05[02] L12 B10 VSS[003] VSS[109] W11

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 ICH_V5REF_RUN G7 L13 B13 U14
V5REF VCC1_05[03] VSS[004] VSS[110]

C275

C276
VCC1_05[04] L14 1 1 B16 VSS[005] VSS[111] W16
ICH_V5REF_SUS U7 L15 B19 U21
V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
VCC1_05[06] M11 B22 VSS[007] VSS[113] U22
2 2

C277

C278
J19 VCC1_5_B[01] VCC1_05[07] M15 D2 VSS[008] VSS[114] U25
+1.5VS_PCIE_ICH 2 2
K18 VCC1_5_B[02] VCC1_05[08] N11 D24 VSS[009] VSS[115] V3
K19 VCC1_5_B[03] VCC1_05[09] N15 E5 VSS[010] VSS[116] V8
L18 VCC1_5_B[04] VCC1_05[10] P11 E7 VSS[011] VSS[117] V19
L19 VCC1_5_B[05] VCC1_05[11] P15 E9 VSS[012] VSS[118] V23
R289 40 mils M18 R11 E11 W1
VCC1_5_B[06] VCC1_05[12] VSS[013] VSS[119]
+1.5VS 1 2 M19 VCC1_5_B[07] VCC1_05[13] R12 E13 VSS[014] VSS[120] W4
D BLM18PG181SN1D_0603 D
N18 VCC1_5_B[08] VCC1_05[14] R13 E15 VSS[015] VSS[121] W5

10U_0603_6.3V6M

10U_0603_6.3V6M
C282
220U_B2_2.5VM_R35

2.2U_0402_6.3V6M
1 1 1 1 N19 VCC1_5_B[09] VCC1_05[15] R14 E17 VSS[016] VSS[122] W7
P18 VCC1_5_B[10] VCC1_05[16] R15 E19 VSS[017] VSS[123] W9
+ R18 9/29 E21 W15
VCC1_5_B[11] VSS[018] VSS[124]

C279

C280

C281
T18 R290 F24 W19
2 2 2 VCC1_5_B[12] VSS[019] VSS[125]
T19 VCC1_5_B[13] 1 2 +1.5VS G2 VSS[020] VSS[126] W21
2 VCC_DMI

0.01U_0402_16V7K

1U_0603_10V4Z
U18 G5 W22

CORE
VCC1_5_B[14] VSS[021] VSS[127]
U19 VCC1_5_B[15] 1 1 MBK1608301YZF 0603 G10 VSS[022] VSS[128] W25

1U_0603_10V4Z
G13 VSS[023] VSS[129] Y3
1 G16 VSS[024] VSS[130] Y23

C283

C284
G19 VSS[025] VSS[131] AA1
2 2
G21 VSS[026] VSS[132] AA4
Change to SGA00001700 090909.

C285
H10 VSS[027] VSS[133] AA6
2
H12 VSS[028] VSS[134] AA8
VCCDMIPLL P19 +1.5VS_DMIPLL H18 VSS[029] VSS[135] AA11
9/29 9/29 +VCCP
H23 VSS[030] VSS[136] AA13
T17 R292 J5 AA15
+5VS +3VS +5VALW +3VALW VCC_DMI[1] VCC_DMI VSS[031] VSS[137]
VCC_DMI[2] U17 1 2 +VCCP J9 VSS[032] VSS[138] AA16
(DMI) J10 AA17
MBK1608301YZF 0603 VSS[033] VSS[139]
V_CPU_IO[1] V16 J11 VSS[034] VSS[140] AA19
1

2 V_CPU_IO[2] U16 J12 VSS[035] VSS[141] AA21

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
R293 D5 R294 D6 J13 AA22
VSS[036] VSS[142]
VCC3_3[01] V18 +3VS 1 1 J15 VSS[037] VSS[143] AA25
100_0402_5% CH751H-40_SC76 100_0402_5% CH751H-40_SC76 J21 AB3
VSS[038] VSS[144]

VCCA3GP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AE9 J22 AB9
2

VCC3_3[02] VSS[039] VSS[145]

C286
ICH_V5REF_SUS 1 1 1 J25 AB11
2 2 VSS[040] VSS[146]

C287
ICH_V5REF_RUN 20 mils K2 AB13
VSS[041] VSS[147]
20 mils K9 VSS[042] VSS[148] AB15

C288

C289

C290
1 1 VCC3_3[03] AA9 K10 VSS[043] VSS[149] AC24
C291 C292 2 2 2
VCC3_3[04] V14 K11 VSS[044] VSS[150] AC1
W14 +3VS K12 AC4
1U_0402_6.3V6K 1U_0402_6.3V6K VCC3_3[05] VSS[045] VSS[151]
9/19 2 2
K13 VSS[046] VSS[152] AC10

VCCP_CORE
C C

0.1U_0402_16V4Z
K15 VSS[047] VSS[153] AC12
change to 1uf.072709 G8 K17 AC14
VCC3_3[06] VSS[048] VSS[154]
VCC3_3[07] H7 1 K23 VSS[049] VSS[155] AD2
VCC3_3[08] H8 L5 VSS[050] VSS[156] AD6
L9 VSS[051] VSS[157] AD9

C293
@ R322 1 2 +3VS L10 AD16
2 0_0402_5% VSS[052] VSS[158]
L16 VSS[053] VSS[159] AD19
+1.5VS_VCCSATAPLL R323 1 2 L17 AD22
+VCCHDA +1.5VS VSS[054] VSS[160]

PCI
0_0402_5% L21 AE3
VSS[055] VSS[161]
VCCHDA AD7 L22 VSS[056] VSS[162] AE4
+VCCSUSHDA

0.1U_0402_16V4Z
R296 L25 AE11
R319 1 VSS[057] VSS[163]
+1.5VS 1 2 W17 VCCSATAPLL VCCSUSHDA V10 2 +1.5V M9 VSS[058] VSS[164] AE13

0.1U_0402_16V4Z
MBK1608301YZF 0603 0_0402_5% 1 M10 AE15
VCCSUS1_05_ICH_1 R324 1 VSS[059] VSS[165]
+1.5VS U13 VCC1_5_A[01] VCCSUS1_05[1] T7 T60 1 2 +3VALW M12 VSS[060] VSS[166] V17
10U_0603_6.3V6M

1U_0603_10V4Z
1U_0402_6.3V6K

1 1 V13 VCC1_5_A[02] VCCSUS1_05[2] H15 VCCSUS1_05_ICH_2 T61 @ 0_0402_5% M13 VSS[061] VSS[167] AE8

C294
1 W13 VCC1_5_A[03] M14 VSS[062] VSS[168] V9
2
ARX
C296

C295
VCCSUS1_5[1] H16 VCCSUS1_5_ICH_1 T62 M16 VSS[063] VSS[169] J16
2
C297

M17 VSS[064]
2 2
C298

V7 VCCSUS1_5_ICH_2 T63 M23

2 VCCSUS1_5[2] VSS[065]
N2 VSS[066]
N5 VSS[067]
VCCSUS3_3[01] G14 +3VALW follow CPU/B add it.062309 N9 VSS[068]
U12 VCC1_5_A[04] VCCSUS3_3[02] G15 N10 VSS[069]
1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V12 VCC1_5_A[05] VCCSUS3_3[03] H14 N12 VSS[070]
VCCPSUS

1 W12 VCC1_5_A[06] 1 1 N13 VSS[071]

+3VALW
ATX

N14 VSS[072]
N16 VSS[073]
C299

C300

C301
W8 If it support 3.3V audio signals N17
2 VCCSUS3_3[04] 2 2 POP:R322/R324, VSS[074]
N21 VSS[075]

4.7U_0603_6.3V6K
J7 Depop R319/R323 N22
VCCSUS3_3[05] VSS[076]
VCCSUS3_3[06] J8 1 N25 VSS[077]
W10 K7 If it support 1.5V audio signals P9
B VCC1_5_A[07] VCCSUS3_3[07] VSS[078] B
0.1U_0402_16V4Z

K8 POP:R319/R323, P10
VCCSUS3_3[08] Depop R322/R324 VSS[079]
1 U15 VCC1_5_A[08] VCCSUS3_3[09] L7 P12 VSS[080]
2

C302
V15 VCC1_5_A[09] VCCSUS3_3[10] L8 P13 VSS[081]
VCCSUS3_3[11] M7 P14 VSS[082]
W18 VCC1_5_A[10] VCCSUS3_3[12] M8 P16 VSS[083]
2
C303

VCCSUS3_3[13] N7 P17 VSS[084]

VCCPUSB

G9 VCC1_5_A[11] VCCSUS3_3[14] N8 P23 VSS[085]

H9 VCC1_5_A[12] VCCSUS3_3[15] P7 R5 VSS[086]
VCCSUS3_3[16] P8 R7 VSS[087]
+1.5VS_USBPLL V11 R8
VCC1_5_A[13] VSS[088]
U11 VCC1_5_A[14] 9/21 R9 VSS[089]
C304 R10
R298 0.1U_0402_16V4Z VSS[090]
R16 VSS[091]
+1.5VS 1 2 U8 G18 VCCCL1_05_ICH 1 2 R17
VCCUSBPLL VCCCL1_05 VSS[092]
R19 VSS[093]
0.1U_0402_16V4Z

0.1U_0402_16V4Z

MBK1608301YZF 0603 1 1 T9 H17 1 2 R21 A1

VCC1_5_A[15] VCCCL1_5 VSS[094] VSS_NCTF[01]
USB CORE

U9 C305 1U_0402_6.3V6K R22 A25

VCC1_5_A[16] VSS[095] VSS_NCTF[02]
J14 +3VS R25 AE1
VCCCL3_3[1] 9/21 VSS[096] VSS_NCTF[03]
C306

C307

VCCCL3_3[2] K14 T2 VSS[097] VSS_NCTF[04] AE25

2 2 C308 T8 VSS[098]
0.1U_0402_16V4Z T10
+3VS VCC_LAN1_05_INT_ICH VSS[099]
2 1 G11 VCCLAN1_05[1] T11 VSS[100]
H11 VCCLAN1_05[2] T12 VSS[101]
R303 T13 VSS[102]
1 2 G12 VCCLAN3_3[1] T14 VSS[103]
R304 H13 T15
MBK1608301YZF 0603 MBK1608301YZF 0603 VCCLAN3_3[2] VSS[104]
T16 VSS[105]
+1.5VS 1 2 +1.5VS_GLAN J17 T23
VCCGLANPLL VSS[106]
0.1U_0402_16V4Z

1
GLAN POWER

H19 ICH9-M SFF ES_FCBGA569

+1.5VS_PCIE_ICH VCCGLAN1_5[1]
10U_0603_6.3V6M

1 J18 VCCGLAN1_5[2]
C309

2
10U_0603_6.3V6M

A A
1
C310

2
+3VS K16 VCCGLAN3_3
C311

2 ICH9-M SFF ES_FCBGA569

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2009/02/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 20 of 41
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS +3VS_HDD1

0.1U_0402_16V4Z 1U_0402_6.3V6K R109 1 2 1U_0402_6.3V6K 0.1U_0402_16V4Z

0_0805_5%
1 1 1 1 1 1 1 1
C1156 C1157 C1158 C159 C158 C1159 C1160 C1161

2 2 2 2 2 2 2 2

1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z

SATA HDD Conn.
Add it.070709 Add it.070709 JSATA1
D D
GND 1
2 SATA_TXP0
A+ SATA_TXP0 (18)
3 SATA_TXN0
A- SATA_TXN0 (18)
GND 4
5 SATA_RXN0
B- SATA_RXP0
B+ 6
GND 7

VCC3.3 8
SATA_RXN0_C 1 2 SATA_RXN0 9 +3VS_HDD1
(18) SATA_RXN0_C VCC3.3
C1162 0.01U_0402_16V7K 10
VCC3.3
GND 11
SATA_RXP0_C 1 2 SATA_RXP0 12
(18) SATA_RXP0_C GND
C1163 0.01U_0402_16V7K 13
GND
VCC5 14
15 +5VS
VCC5
VCC5 16
GND 17
RESERVED 18
GND 19
23 G1 VCC12 20
24 G2 VCC12 21
VCC12 22

FOX_LD2822V-SA5L6
C CONN@ SP010907230 C

CD-ROM Connector
+5VMOD

JSATA2
1 1
2 2
3 3
4 4

0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z
5 5
SI3456DV: N CHANNEL +5VALW Q49 6
1 1 1 1 6

C324
+5VMOD 7
VGS: 4.5V, RDS: 65 mOHM 7
D

C325

C326
6 W=60mils C327 8
S

Id(MAX): 5.1A 8 +5VMOD

10U_0805_10V4Z
VGS,+-20V
W=60mils 5 4
2 2 2 2 9 9
2 10 10
1 11 11
B B
12
G

12
1

13
3

R1592 13 0.01U_0402_16V7K
14 14
SI3456BDV-T1-E3_TSOP6 470_0402_5% 15 SATA_RXP1 2 1 C323 SATA_RXP1_C
15 SATA_RXP1_C (18)
16 SATA_RXN1 2 1 C322 SATA_RXN1_C
16 SATA_RXN1_C (18)
21 17 0.01U_0402_16V7K
2

GND1 17 SATA_TXN1
+VSB 2 1 22 GND2 18 18 SATA_TXN1 (18)
R1593 23 19 SATA_TXP1
GND3 19 SATA_TXP1 (18)
6

200K_0402_5% Q50A 24 20
GND4 20
3

2N7002DW-T/R7_SOT363-6
FOX_GS12201-1011-9F
1 2 ODD_ON# CONN@ SP010907090
5 C1517
(29) ODD_ON#
1

0.1U_0603_25V7K
4

Q50B 2
2N7002DW-T/R7_SOT363-6

Modify +5VMOD control schematic 100809.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Add it for ODD button.072109. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 21 of 41
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD
+3VALW +3VS
W=60mils

1
D D
R386

1
300_0603_5% 1 1 1
R387 C1141 C1164 C1165
100K_0402_5%

3 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 68P_0402_50V8J
2 2 2

2
Q8B
Place close to JLVDS1

3
S

Add it to solve Flicker occurs issue 101209.

G
2N7002DW-T/R7_SOT363-6 5 2 1 2 Q9
R389 1K_0402_5% AO3413_SOT23-3
1
D Change to use SB934130020.091509
4

1
6
C1142 +LCDVDD

Q8A 0.047U_0402_16V7K
W=60mils
2
(10) GMCH_ENVDD 1 2 2
2N7002DW-T/R7_SOT363-6 1 1
R391 0_0402_5% C1143 C1144
1
1

4.7U_0805_10V4Z 0.1U_0402_16V4Z
R392 2 2
100K_0402_5%
2

+LCDVDD
C +INVPWR_B+ C

L12 2 1 B+
W=40mils FBMA-L11-201209-221LMA30T_0805 1 1 1
C1150 C1151 C1152
L13 2 1
FBMA-L11-201209-221LMA30T_0805 10U_0805_10V4Z 0.1U_0402_16V4Z 68P_0402_50V8J
2 2 2
1 1
C1145 C1146

680P_0402_50V7K 68P_0402_50V8J Place close to JLVDS1

2 2 Add it to solve Flicker occurs issue 101209.

+3VS

5
U30

P
NC
GMCH_INV_PWM 4 2
LVDS and USB CAM connector Y A NC7SZ14P5X_NL_SC70-5 DPST_PWM (10)

G
3
JLVDS1
1 LVDS_DDC2_CLK
1 LVDS_DDC2_CLK (10)
41 2 LVDS_DDC2_DATA
G1 2 LVDS_DDC2_DATA (10)
42 G2 3 3
43 4 LVDS_A_0- R110 1 2 INVT_PWM
G3 4 LVDS_A_0- (10) INVT_PWM (29)
44 5 LVDS_A_0+ @ 0_0402_5%
G4 5 LVDS_A_0+ (10)
45 G5 6 6
46 7 LVDS_A_1-
B G6 7 LVDS_A_1- (10) B
8 LVDS_A_1+
8 LVDS_A_1+ (10)
9 9
10 LVDS_A_2- +3VS
10 LVDS_A_2- (10)
11 LVDS_A_2+
11 LVDS_A_2+ (10)
12 12

1
13 LVDS_A_C-
13 LVDS_A_C- (10)
14 LVDS_A_C+ R393
14 LVDS_A_C+ (10)
15 15
16 GMCH_INV_PWM 4.7K_0402_5%
16 +3VS D13
17 DISPLAYOFF#

2
17 BKOFF# DISPLAYOFF#
18 18 (29) BKOFF# 1 2
19 +CAM_VCC R328 1 2 0_0603_5%
19 USB20_CMOS_N7 0_0402_5%1
20 20 2 R1515 USB20_N7 (19) CH751H-40PT_SOD323-2
21 21 USB20_CMOS_P7 0_0402_5%1 2 R1516 USB20_P7 (19) Camera
22 22
23 DMIC_CLK_R
23 DMIC_CLK_R (25)
24 24 DMIC_DATA_R
DMIC_DATA_R (25) DMIC
25 25
26 26 +3VS
27 Change DMIC on LVDS conn .070909
27
28 28
29 29 +LCDVDD
30 30 W=60mils
31 31
32 +INVPWR_B+ GMCH_INV_PWM 1 2
32 USB20_CMOS_N7 C1148 220P_0402_50V7K
33 33
34 DISPLAYOFF# 1 2
34 C1149 220P_0402_50V7K
35 35
36 USB20_CMOS_P7
36
37 37 1 1
10P_0402_50V8J

C1292
10P_0402_50V8J

C1291

38 38
39 39
A A
40 40
2 @ 2 @
IPEX_20143-040E-20F
SP010016810 CONN@
Swap net for layout 072709.

add it for EMI.072409.

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
Date: Tuesday, October 20, 2009 Sheet 22 of 41
5 4 3 2 1
 A B C D E

NOTE: L : A-->B1
H: A-->B2

Place closed to chipset

L34
1 GMCH_CRT_R RED 1
(10) GMCH_CRT_R 1 2
FCM2012CF-800T06_2P
L35 BLUE
GMCH_CRT_G 1 2 GREEN GREEN
(10) GMCH_CRT_G
FCM2012CF-800T06_2P RED
L36
GMCH_CRT_B 1 2 BLUE
(10) GMCH_CRT_B
FCM2012CF-800T06_2P

1
@ D36
@D36 @ D37
@D37 @ D38

DAN217_SC59
C1387

DAN217_SC59

DAN217_SC59
R697 R698 R699 1 1 1 1 1 1
C1383 C1384 C1385 C1386 C1388

150_0402_1%

150_0402_1%
2
+CRTVDD

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
10P_0402_50V8J 10P_0402_50V8J

3
150_0402_1% 2 2 2 2 2 2

10P_0402_50V8J

Change to 10pf 102009.

Place close to JCRT1

+5VS +5VS

C1389 C1390
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2
2
2
R700
1
CRT PORT 2
5
1

10K_0402_5% U79
SN74AHCT1G125GW_SOT353-5 R701
P
OE#

GMCH_CRT_HSYNC 2 CRT_HSYNC 2 0_0603_5% JVGA_HS

(10) GMCH_CRT_HSYNC A Y 4 1
+5VS +RCRT_VCC +CRTVDD
G

5
1

Place closed to chipset R702 D39 F1

W=40mils
P
OE#
3

GMCH_CRT_VSYNC 2 4 CRT_VSYNC 1 2 0_0603_5% JVGA_VS 2 1 1 2 W=40mils

(10) GMCH_CRT_VSYNC A Y
1 1 1 1
G

U80 1 @ 1 @ CH491D_SC59 1.1A_6VDC_FUSE C1393 C1147 C1448 C167

68P_0402_50V8J

0.1U_0402_16V4Z

0.47U_0603_10V7K
SN74AHCT1G125GW_SOT353-5 C1391 C1392 0.1U_0402_16V4Z
3
1

R703 R704 5P_0402_50V8C 5P_0402_50V8C 2 2 2 2

51K_0402_5% 51K_0402_5% 2 2 JCRT1
1 1
RED 2
2

2
3 3
GREEN 4 4
5 5 Place close to JCRT1
BLUE 6 6
7 Add it to solve Flicker occurs issue 100909.
JVGA_VS 7
8 8
(19) CRT_DET# CRT_DET# 9
JVGA_HS 9
10 10
VGA_DDC_DAT 11 11

2
+3VS VGA_DDC_CLK 12
+3VS +CRTVDD +CRTVDD R713 R705 12
NU it 101309. 0_0603_5% 100K_0402_5%
@ 13 GND1
1

14

1
R706 R707 R708 R709 GND2
3 Add it 101409. ACES_87213-1200G 3
2

2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% +CRTVDD CONN@ SP02000FT00

R710
2

GMCH_CRT_DATA 1 2 CRT_DATA_R 1 6 VGA_DDC_DAT Swap net for layout 072809.

(10) GMCH_CRT_DATA 0_0402_5% Change Conn to12pin 080409.
2N7002DW T/R7_SOT363-6
5

Q38A
R711
GMCH_CRT_CLK 1 2 CRT_CLK_R 4 3 VGA_DDC_CLK
(10) GMCH_CRT_CLK 0_0402_5%
Q38B
2N7002DW T/R7_SOT363-6

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 23 of 41
A B C D E
 5 4 3 2 1

EQ_1 EQ_0 Equalization PC_2 PC_1 PC_0 Swing Pre-amp Slew-rate

0 0 12dB * 0 0 0 450 0 0

close to IC VCC (+3VS) pins (one Pin one Capacitor) 0 1 9dB 0 0 1 420 0 -3dB Shortest trace

+3VS +3VS 1 0 6dB 0 1 0 450 0 -3dB Shortest trace

* 1 1 3dB 0 1 1 460 0 -4dB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_0603_6.3V6M
1 1 1 1 1 1 1 1
C1437 C1438 C1439 C1440 C1441 C1442 C1443 C1444
@ @ @ @ 1 0 0 340 0 0
D D
2 2 2 2 2 2 2 2 U84
1 0 1 400 2dB 0 Longest trace
+3VS 25 HDMI_DET#
OE#
Change package 081709. 1 1 0 400 2dB 0 Longest trace
2 VCC3V
11 28 HDMI_SCLK
VCC3V SCL_SINK
15 Add it.071109 1 1 1 420 0 0
VCC3V
NU it for vender's suggestion 091509. 21 29 HDMI_SDATA
VCC3V SDA_SINK
26 VCC3V
33 VCC3V
+HDMI_5V_OUT R1519 1 @ DVI_DET
+3VS 2 4.7K_0402_5% 40 VCC3V HPD_SINK 30
46 VCC3V
R1520 1 @ 2 4.7K_0402_5% 32 R1521 1 2 4.7K_0402_5% +3VS
+3VS DDC_EN
W=40mils F2 D55
R1522 1 @
+3VS 2 4.7K_0402_5%
2 1 1 2 +5VS 3 34 R1523 1 @ 2 4.7K_0402_5% +3VS
R1524 1 @ CG_0 EQ_0
1 1 1 2 4.7K_0402_5% 4 CG_1 EQ_1 35

1
C1445 C1447 C166 1.1A_6VDC_FUSE SS1040_SOD123 +3VS 1 2 R1526 1 @ 2 4.7K_0402_5%
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.47U_0603_10V7K

R1525 R1527 R1545 @ 4.7K_0402_5%

2.2K_0402_5% 2.2K_0402_5% R1528 1 2 6 R1529 1 @ 2 4.7K_0402_5% +3VS
2 2 2 3.4K_0402_1% REXT
TMDS_B_HPD 7 R1530 1 @ 2 4.7K_0402_5%

2
HPD# +5VS
(8) SDVO_SDAT 8 SDA
5V Level
(8) SDVO_SCLK 9 SCL R1518 R1517

1
Add it to solve Flicker occurs issue 100909.

2.2K_0402_5%

2.2K_0402_5%
1 @ 2 10
R1532 0_0402_5% CG_2

DVI_TXC+ 13 48 TXCD+ (10)

2
DVI_TXC- OUT_D4+ IN_D4+
14 OUT_D4- IN_D4- 47 TXCD- (10)
HDMI_SDATA HDMI_SDATA
DVI_TXD2+ 16 45
OUT_D3+ IN_D3+ TX2D+ (10)
C DVI_TXD2- 17 44 C
OUT_D3- IN_D3- TX2D- (10)
Take off Q48 090909.
DVI_TXD1+ 19 42
OUT_D2+ IN_D2+ TX1D+ (10)
DVI_TXD1- 20 41 HDMI_SCLK HDMI_SCLK
OUT_D2- IN_D2- TX1D- (10)
DVI_TXD0+ 22 39 Place closed to JHDMI1
OUT_D1+ IN_D1+ TX0D+ (10)
DVI_TXD0- 23 38
OUT_D1- IN_D1- TX0D- (10)
Trace AS Short PASS
Add it.071109
1 GND
5 GND
12 GND GND 49
+3VS
inverting level shift for NB 18
24
GND
GND
27 GND

2
31 GND
+3VS 36 R1531
GND
37 GND 2.2K_0402_5%
43 GND

1
1

R1534 ASM1442T_QFN48_7X7 HDMI_DET#

20K_0402_5% U84. 49 (THERMAL_GND) to GND Plane
Change use from ST to ASM1442T 091009.

1
R1565 D
2

1 2 DVI_DET 2 Q42
(10) HDMI_HPD#
0_0402_5% G 2N7002_SOT23
S

3
1

2
100K_0402_5%
R1536 Q43 2TMDS_B_HPD_R TMDS_B_HPD

0.1U_0402_16V4Z
1 2 1

R1533

C1446
G R1535 0_0402_5%
7.5K_0402_1% @S
3

2
20K_0402_1%

R1567 R1568
2

2N7002_SOT23 R1566 2

1
0_0402_5% @
0_0402_5%
For Power Saving Application
@ @ When Plug-in HDMI
1

B B
HDMI_HPD=High OE#=Low Enable Level Shift
HPD_7318_R_EC (29) When Plug-out HDMI
add it.062309 HDMI_HPD=Low OE#=High Disable Level Shift
HPD_7318_EC (29)

HDMI Connector
NU 090909.

DVI_TXD0+ R1537 1 2 0_0402_5% HDMI_TXD0+_R DVI_TXC- @ R1587 C1509 1 2 @ DVI_TXC+

DVI_TXD2+ R1538 1 2 0_0402_5% HDMI_TXD2+_R 220_0402_5% 12P_0402_50V8J +HDMI_5V_OUT
L42
L41 3 4 DVI_TXD2- @ R1588 C1510 1 2 @ DVI_TXD2+ JHDMI1
3 4 DVI_DET
3 3 4 4 220_0402_5% 12P_0402_50V8J 1 2HP_DETECT 19 HP_DET
SWAP R1569 0_0402_5% 18 +5V

1U_0603_10V4Z
SWAP 2 1 1 17
2 1 DDC/CEC_GND

C160
2 1 DVI_TXD1- @ R1589 C1511 1 2 @ DVI_TXD1+ HDMI_SDATA 16
2 1 WCM-2012-900T_4P @ 220_0402_5% 12P_0402_50V8J HDMI_SCLK SDA
15 SCL
WCM-2012-900T_4P @ 14
DVI_TXD0- HDMI_TXD0-_R 2 Reserved
1 2 13 CEC
DVI_TXD2- 1 2 HDMI_TXD2-_R R1539 0_0402_5% DVI_TXD0- @ R1590 C1512 1 2 @ DVI_TXD0+ HDMI_TXC-_R 12 20
R1540 0_0402_5% 220_0402_5% 12P_0402_50V8J CK- GND
11 CK_shield GND 21
HDMI_TXC+_R 10 22
HDMI_TXD0-_R CK+ GND
9 D0- GND 23
For Vender suggest to add it.062609 8
DVI_TXC- R1541 1 HDMI_TXC-_R HDMI_TXD0+_R D0_shield
2 0_0402_5% 7 D0+
DVI_TXD1- R1542 1 2 0_0402_5% HDMI_TXD1-_R HDMI_TXD1-_R 6 D1-
5 D1_shield
L44 HDMI_TXD1+_R 4
L43 HDMI_TXD2-_R D1+
2 2 1 1 3 D2-
2 2 1 1 2 D2_shield
A HDMI_TXD2+_R 1 A
D2+
3 3 4 4
3 SUYIN_100042MR019S153ZL
3 4 @4 WCM-2012-900T_4P @ CONN@ DC232000900
WCM-2012-900T_4P
DVI_TXC+ 1 2 HDMI_TXC+_R
DVI_TXD1+ 1 2 HDMI_TXD1+_R R1543 0_0402_5%
R1544 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 24 of 41
5 4 3 2 1
 A B C D E

+VDDA
J5
2 2 1 1

1
R723 JUMP_43X39
10K_0402_5%
+5VAMP
U82
40mil @
(output = 300 mA)

2
+5VS L37 1 2 0.1U_0402_16V4Z 1
FBMA-L11-201209-221LMA30T_0805 IN
1 2 OUT 5 +VDDA 4.75V
40mil
1 C1407 4.7U_0805_10V4Z 1
1 1 2 GND C1410

1
C1408 C1409
R724 3 4 1 2 @
10K_0402_5% Reserve to change 4.7u for audio noise issue.100809. 0.1U_0402_16V4Z SHDN BYP
2 2 G9191-475T1U_SOT23-5
2.2U_0603_6.3V6K

2
C1411 DVT NU it.091509.
1 2 MONO_IN
1U_0402_6.3V4Z

1
C 1 2
C1412 1 R725 Q41 R726 1.3K_0402_1%
(29) BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E 2SC2411K_SOT23

3
C1413 1 R727 +5VS
(19) SB_SPKR 2 1 2
1U_0402_6.3V4Z W=40mil

1
560_0402_5%
D40 1 1
R728 CH751H-40PT_SOD323-2
10K_0402_5% C1414 C1415
10U_0805_10V4Z 0.1U_0402_16V4Z
2

2
+1.5VS_HD 2 2
L45
+1.5VS 1 2 10U_0805_10V4Z
FBM-L11-160808-800LMT_0603 1 1
+5VS
C1434 C1435 W=40mil
2 2
1 1
2 add it.070709 0.1U_0402_16V4Z 2
C1416 C1417
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2

+3VS +3VS_HD
L38 20mil
10U_0805_10V4Z +HD_AVDD +VDDA
1 2
FBM-L11-160808-800LMT_0603 1 1 1
40mil
L39
100P_0402_50V8J 0.1U_0402_16V4Z 2 1
C1418 C1419 C1420 1 1 1 1 FBM-L11-160808-800LMT_0603
@ C1422 C1423 C1424 C1425
2 2 2
100P_0402_50V8J 0.1U_0402_16V4Z @ HDA_BITCLK_AUDIO 1 2 1 2
2 2 2 2 R729 @

39

46

25

38
1

9
0.1U_0402_16V4Z 10U_0805_10V4Z 22_0402_5% C1426 @
U83 10P_0402_50V8J

DVDD

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
23 40 SPKL+ SPKL+ (26)
LINE1_L SPK_OUT_L+ SPKL-
24 LINE1_R SPK_OUT_L- 41 SPKL- (26)
add it.100709 14 45 SPKR+ SPKR+ (26)
LINE2_L SPK_OUT_R+ SPKR-
15 LINE2_R SPK_OUT_R- 44 SPKR- (26)
MIC1_L 1 2 MIC1_C_L 21 32 HP_LEFT HP_LEFT (26) +MIC1_VREFO_R +MIC1_VREFO_L
(26) MIC1_L MIC1_L HP_OUT_L
C1421 4.7U_0805_10V4Z 22 33 HP_RIGHT HP_RIGHT (26)
MIC1_R MIC1_C_R MIC1_R HP_OUT_R
(26) MIC1_R 1 2
C1436 4.7U_0805_10V4Z 16 MIC2_L C1427 C1428
17 MIC2_R
3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3
SYNC 10 HDA_SYNC_CODEC (18)
DMIC_DATA_R R730 1 DMIC_DATA
2 2 6 HDA_BITCLK_AUDIO 1 2
(22) DMIC_DATA_R GPIO0/DMIC_DATA BCLK HDA_BITCLK_CODEC (18)
0_0402_5% R732 0_0402_5%
(22) DMIC_CLK_R
DMIC_CLK_R R731 1 2 DMIC_CLK 3 add it for EMI.072409.
C1293 1 GPIO1/DMIC_CLK
2 @ 0_0402_5% SDATA_OUT 5 1 2 HDA_SDOUT_CODEC (18)
add it for EMI.072409. 10P_0402_50V8J R741 0_0402_5%
R744 1 2 4 8 AZ_SDIN0_HD_R 1 2
(29) EC_MUTE# PD# SDATA_IN HDA_SDIN0 (18)
0_0402_5% R733 33_0402_5%
add it.070709 add it 090909.
(18) HDA_RST#_CODEC 11 RESET# EAPD/SPDIFO2 47 EAPD 1 2EC_EAPD EC_EAPD (29) add it 090909.
(26) HP_PLUG# 2 1 SENSE_A R734 0_0402_5%
R735 39.2K_0402_1% 48 SPDIF_L 1 2 L46 SPDIF (26)
MONO_IN SPDIFO FBMA-L11-160808-301LMA20T_0603~D
(26) MIC_PLUG# 1 2 12 PCBEEP
R736 20K_0402_1% 1 2 20 add it for EMI 101309.
MONO_OUT
C1429 @ 100P_0402_50V8J mount R 0ohm 102009.
SENSE_A 13 SENSE A
29
10mil DGND To AGND Bypass
MIC2_VREFO +MIC2_VREFO
SENSE_B 18 SENSE B
30
10mil
MIC1_VREFO_R +MIC1_VREFO_R
Sense Pin Impedance Codec Signals 1
C1430
2 36
2.2U_0402_6.3V4Z CBP MIC1_VREFO_L 28 +MIC1_VREFO_L 1
R737
2
0_0603_5%
35 27
10mil 1 2
CBN VREF R738 0_0603_5%
39.2K PORT-A (PIN 32, 33) 1 1
31 19 1 2
EXPOSE_PAD

CPVREF JDREF C1431 C1432 R739 @ 0_0603_5%

1
20K PORT-B (PIN 21, 22) 43 34 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2
PVSS2 CPVEE 2 2 R742 @ 0_0603_5%
SENSE A 42 PVSS1 2
C1433 R740
AVSS1 26 1 2
10K PORT-C (PIN 23, 24) 7 37 2.2U_0402_6.3V4Z 20K_0402_1% R743 @ 0_0603_5%
DVSS AVSS2
2
ALC269X-GR QFN 48P_7X7 1 add it for EMI.081009
49

4 4
5.1K PORT-D (PIN 48) DGND AGND

39.2K PORT-E (PIN 14, 15) DGND AGND

20K PORT-F (PIN 16, 17)

SENSE B Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-G (PIN 20) Issued Date 2008/05/30 Deciphered Date 2011/05/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA-ALC269Q-GR
5.1K PORT-H (PIN 47) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 21, 2009 Sheet 25 of 41
A B C D E
 A B C D E

Int. Speaker Conn.

JSPK1
SPKL+ R518 1 2 0_0603_5% SPK_L+ 4 6
20mil
(25)
(25)
SPKL+
SPKL- SPKL- R519 1 2 0_0603_5% SPK_L- 3
4 GND
3 GND 5 Left
(25) SPKR- SPKR- R521 1 2 0_0603_5% SPK_R- 2
SPKR+ R522 0_0603_5% SPK_R+ 2
20mil (25) SPKR+ 1 2 1 1 Right
Swap net for layout 072709. ACES 88266-04001
SP02000K200 CONN@

1 1

Change to 4pin conn.0622

+5VAMP

+5VAMP

2
HP_PLUG#
HP_PLUG# (25)
R1575

3
100K_0402_5%

2
Q44B

1
R1576 5 2N7002DW-T/R7_SOT363-6
Q46 100K_0402_5%

6
AO3413_SOT23-3

4
1
3
S
G Q44A
2 SPDIF_PLUG# 2 2N7002DW-T/R7_SOT363-6
D
LINE Out/Headphone Out

1
Change to use SB934130020.091509
2
+5VSPDIF 2

20mil For Vender's suggestion change from DGND to AGND.072009.

PJDLC05_SOT23~D
2 2 2 @
C485 C486 C1098 D61 1
1 2 3
330P_0402_50V7K
1 1 0.1U_0402_16V4Z
20mil 330P_0402_50V7K JHP1
6
(25) HP_RIGHT HP_RIGHT 1 2 HPOUT_R_1 1 2 HPOUT_R_2 4
R378 56.2_0402_1% L30 FBM-11-160808-700T_0603
(25) HP_LEFT HP_LEFT 1 2 HPOUT_L_1 1 2 HPOUT_L_2 1
R377 56.2_0402_1% L33 FBM-11-160808-700T_0603
JHP1 conn PIN1/4 need swap 100809. 5
Chenge to 56.2 ohm for DA-HP FSOV
SPDIF_PLUG# 7
20081104 3
+5VSPDIF
SPDIF 8
(25) SPDIF
Take off D28 090909.
1 2
C1083
100P_0402_50V8J
TAITW_PJKAT1-08FNBT1TT4N0
2 CONN@ DC230006600

3 3

+MIC1_VREFO_L +MIC1_VREFO_R

2
D34 D35
RB751V-40TE17_SOD323-2
RB751V-40TE17_SOD323-2

1 1

1 1
R403 R402
MIC JACK
4.7K_0402_5% 4.7K_0402_5%

2
JMIC1
1
1 2 1 2 FBM-11-160808-700T_0603 MIC1_L_1 2
(25) MIC1_L
R405 1K_0603_1% L31
1 2 1 2 FBM-11-160808-700T_0603 MIC1_R_1 3
(25) MIC1_R
R404 1K_0603_1% L32
4

2
D29
1 1 MIC_PLUG# 5
(25) MIC_PLUG#
C488 C489
220P_0402_50V8J 220P_0402_50V8J
2 2 PJDLC05_SOT23-3 6

1
SINGA_2SJ-0960-C01
4 @ CONN@ 4
For EMI mount it.091509
P/N:DC230004K00 symbol use DC230710010 .070809

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 21, 2009 Sheet 26 of 41
A B C D E
 5 4 3 2 1

H1 H2 H3 H4
H_2P9 H_2P9 H_2P9 H_4P1N
Power Button Logic
@ @ @ @

1
D Modify to H_4P1N.100909. D

+3VALW
TOP Side H5
H_2P5
H6
H_2P5
H7
H_2P5
H8
H_2P5
H9
H_2P5
H10
H_2P5
1 2
R578 @ 10K_0603_5%

2
@ @ @ @ @ @

1
1 2 R488
R579 @ 10K_0603_5%
100K_0402_5%

ON/OFF switch Bottom Side

1
D22
2 ON/OFF (29)
ON/OFFBTN# 1
(28) ON/OFFBTN#
3 51ON#
51ON# (32)
DAN202UT106_SC70-3

1
2
C1521 D63
H20 H19
1000P_0402_50V7K RLZ20A_LL34 H_1P2 H_1P2
1

2
@ @

1
add it .073109.

1
C D C
EC_ON 2 Q19 FD1 FD2
(29) EC_ON
G
2

S 2N7002_SOT23

3
R489 @ @

1
10K_0402_5% FIDUCIAL_C40M80 FIDUCIAL_C40M80
1

FD3 FD4

@ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80

+3VALW C161 1 2@ +1.5V

0.1U_0402_16V4Z

+3VS C162 1 2@ +VCCP

0.1U_0402_16V4Z

+1.5V C163 1 2@
0.1U_0402_16V4Z
+VCCP
Lid Switch
(Hall Effect Switch)
+3VALW C164 1 2@ +1.5V
0.1U_0402_16V4Z
B B

+3VS C165 1 2@ +1.5V

0.1U_0402_16V4Z
+3VALW

For EMI to add it.091109.

1
2

2
C1378 R557
47K_0402_5%

VDD
1

2
OUTPUT 3 1 2 LID_SW# (29)
0.1U_0402_16V4Z D30 RB751V_SOD323

GND
1 Change to use SC1H751H010.091509
C1379
U78

1
A3212ELHLT-T_SOT23W-3 10P_0402_50V8J
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/22 Deciphered Date 2009/11/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR ON/OFF & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 27 of 41
5 4 3 2 1
 A B C D E

Add PWR net.071309

JP5
BT Module CONN. +3VS

ADD PMOS SOFT START 11/14

B+ 1 1 2 2 B+
P3 3 3 4 4
5 5 6 6
7 7 8 8 1
BATT+ 9 9 10 10 BATT+
11 12 C357
11 12
(29,31,36) SUSP# SUSP# 13 13 14 14 FSTCHG
FSTCHG (29) change EC signal name form 2
0.1U_0402_16V4Z
ADP_I IREF
1
(29) ADP_I 15 15 16 16
CHGVADJ
IREF (29) BT_OFF# to BT_ON# 11/14 1
CSIN 17 17 18 18 CHGVADJ (29) R291
CSIP 19 20 WWAN_CLKREQ# WWAN_CLKREQ# (16)
LAN_CLKREQ# 19 20 E51TXD_P80DATA
(16) LAN_CLKREQ# 21 21 22 22 E51TXD_P80DATA (29) (29) BT_ON# 2 1
PCIE_WAKE# 23 24 E51RXD_P80CLK
(19) PCIE_WAKE# 23 24 E51RXD_P80CLK (29)
(16) MINI2_CLKREQ# MINI2_CLKREQ# 25 26 WWAN_WAKEUP# WWAN_WAKEUP# (29) 10K_0402_5%
ICH_SMBDATA 25 26 WXMIT_OFF#
(16,19) ICH_SMBDATA 27 27 28 28 WXMIT_OFF# (29)
ICH_SMBCLK 29 30 WL_OFF#
(16,19) ICH_SMBCLK 29 30 WL_OFF# (29)
USB_OC#2 31 32 PLT_RST_BUF#
(19) USB_OC#2 31 32 PLT_RST_BUF# (17)
(29) USB_ON# USB_ON# 33 34 EC_LAN_PME# EC_LAN_PME# (29) +3VS +3VS_BT
ON/OFFBTN# 33 34 Q20
(27) ON/OFFBTN# 35 35 36 36
ON/OFF_LED# 37 38 PCIE_ITX_C_PRX_P3 AO3413_SOT23-3
(29) ON/OFF_LED# 37 38 PCIE_ITX_C_PRX_P3 (19)
MINI1_LED# 39 40 PCIE_ITX_C_PRX_N3 C348
(30) MINI1_LED# 39 40 PCIE_ITX_C_PRX_N3 (19)

D
WWAN_LED# 41 42 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_P3 (19) 3 1 2 1
(30) WWAN_LED# CLK_PCIE_MINI2# 41 42 PCIE_PTX_C_IRX_N3
(16) CLK_PCIE_MINI2#
CLK_PCIE_MINI2
43 43 44 44 PCIE_PTX_C_IRX_N3 (19) GLAN 0.1U_0402_16V4Z
(16) CLK_PCIE_MINI2 45 45 46 46
PCIE_ITX_C_PRX_P2

G
47 48 PCIE_ITX_C_PRX_P2 (19)

2
47 48
(16) CLK_PCIE_LAN# CLK_PCIE_LAN# 49 50 PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_N2 (19) Change to use SB934130020.091509
CLK_PCIE_LAN 49 50 PCIE_PTX_C_IRX_P2

+3VS_BT
(16) CLK_PCIE_LAN 51 51 52 52
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2 (19) WLAN
53 53 54 54 PCIE_PTX_C_IRX_N2 (19)
(16) CLK_PCIE_WWAN# CLK_PCIE_WWAN# 55 56
CLK_PCIE_WWAN 55 56 PCIE_ITX_C_PRX_P1
(16) CLK_PCIE_WWAN 57 57 58 58 PCIE_ITX_C_PRX_P1 (19)
59 60 PCIE_ITX_C_PRX_N1
59 60 PCIE_ITX_C_PRX_N1 (19) JBT1
USB20_P3 61 62 PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_P1 (19) 3G
(19) USB20_P3 61 62
WLAN USB20_N3 63 64 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_N1 (19) 1
(19) USB20_N3 63 64 1
USB20_P5 65 66 2
(19) USB20_P5 65 66 2
3G USB20_N5 67 68 (19) USB20_P6 USB20_P6 3 5
(19) USB20_N5 67 68 3 GND
USB20_P2 69 70 +1.5VS (19) USB20_N6 USB20_N6 4 6
(19) USB20_P2 69 70 4 GND
USB USB20_N2 71 72
(19) USB20_N2 71 72
73 73 74 74 ACES 88266-04001
75 75 76 76 +3VS
Change from SUSP# to USB_ON#.073109. 77 78 CONN@
77 78 SP02000K200
+5VALW 79 79 80 80 +3VALW
2 2
81 GND GND 82

SP020907220 CONN@
Change conn 072409.

USB CONN. USB CONN.

+USB_VCCA
+USB_VCCA W=80mils
W=80mils +USB_VCCA
+USB_VCCA 1
150U_B2_6.3VM_R45M

470P_0402_50V7K

1 1
+3VALW
150U_B2_6.3VM_R45M

470P_0402_50V7K

+ C1231 C1232
1
+ C1233 C1234 80mil
+5VALW

1
2 2 +USB_VCCA
3 2 2 U34 3
1 8 R446
GND OUT 100K_0402_5%
2 IN OUT 7
JUSB1 3 6

2
JUSB2 IN OUT
1 VCC 1 4 EN# FLG 5 1 2 USB_OC#0 (19)
1 USB20_N0 2 C1240 R447
VCC (19) USB20_N0 D-
(19) USB20_N1
USB20_N1 2 (19) USB20_P0
USB20_P0 3 TPS2061DRG4_SO8 10K_0402_5% 1 Change use USB_OC#0 to control.091109.
USB20_P1 D- D+ 4.7U_0805_10V4Z C1241
(19) USB20_P1 3 D+ 4 GND 2
4 GND
5 0.1U_0402_16V4Z
GND1
3

D32 2
5 GND1 6 GND2
3

D31 6 7
GND2 GND3 USB_ON#
7 GND3 8 GND4
8 GND4 @ SUYIN_020133GB004M25MZL Change use USB_ON# to control.072009.
@ SUYIN_020133GB004M25MZL PJDLC05_SOT23-3
1

PJDLC05_SOT23-3
1

P/N:LTCX001OP00 symbol use SP010906181 .070909

For EMI.090909.
For EMI.090909.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & USB Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 28 of 41
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

L17
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 +EC_VCCA +3VALW
1 1 C1245 1 1 2 2
2
FBM-L11-160808-800LMT_0603 JP6 Place on RAM door
C1244 1 KSI[0..7] 1
+3VALW KSI[0..7] (30) 1
C1242 C1246 C1247 C1248 2 E51TXD_P80DATA
KSO[0..17] 2 E51TXD_P80DATA (28)
1000P_0402_50V7K 1000P_0402_50V7K C1243 3 E51RXD_P80CLK
2 2 2 2 1 1 KSO[0..17] (30) 3 E51RXD_P80CLK (28)
1 2 EC_PME# 4
R448 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4

ECAGND
@ ACES_85205-0400
@ SP020007200
D Add it 090909. D

111
125
PLT_RST#

22
33
96

67
1 2

9
R449 100K_0402_5% U35
Take off 3S/4S# and 65W/90W# signel.072009.

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
(18) EC_GA20 1 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 21
2 23 BEEP#
(18) EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (25)
(19) SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 1 2FAN_PWM FAN_PWM (4) add it 072209.
(18) LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 R450 0_0402_5%
ACOFF (35)
C1249 LPC_AD3 5 2 1 ECAGND
(18) LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C1251 0.01U_0402_16V7K
(18) LPC_AD2 LAD2
2 1 R452 2 1 @ 33_0402_5% (18) LPC_AD1 8 63 BATT_TEMP
LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (33)
LPC_AD0 BATT_OVP
(18) LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP (35)
ADP_I/AD2/GPIO3A 65 ADP_I (28)
12 AD Input 66 AD_BID0
(16) CLK_PCI_LPC PCICLK AD3/GPIO3B
PLT_RST# 13 75
(8,17) PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 +3VALW
37 ECRST# SELIO2#/AD5/GPIO43 76
EC_SCI# 20
(19) EC_SCI# SCI#/GPIO0E
+3VALW 2 1 38 @
R453 47K_0402_5% (19) PM_CLKRUN# CLKRUN#/GPIO1D WXMIT_OFF#
DAC_BRIG/DA0/GPIO3C 68 2 1
2 1 70 EN_FAN1 R454 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_FAN1 (4)
C1250 0.1U_0402_16V4Z DA Output 71 IREF
IREF/DA2/GPIO3E IREF (28)
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGVADJ (28)
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 ODD_ON#
KSI3/GPIO33 PSCLK1/GPIO4A ODD_ON# (21)
C KSI4 59 84 USB_ON# C
KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# (28)
KSI5 60 85
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C ODD LED#
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 ODD LED# (30)
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK (30)
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (30)
KSO1 40 KSO1/GPIO21
KSO2 41 add it 072809.
KSO3 KSO2/GPIO22 ODD BTN#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 ODD BTN# (30)
KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 MCH_TSATN_EC# (8)
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# (27)
KSO7 46 SPI Device Interface Please see page 3.
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO (30) +3VALW
+5VS KSO10 49 120 EC_SO_SPI_SI
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI (30)
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK (30)
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# (30)

2
1 2 TP_CLK KSO13 52 KSO13/GPIO2D
R458 4.7K_0402_5% KSO14 53 R459
KSO14/GPIO2E
1 2 TP_DATA KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 WWAN_WAKEUP# (28) Ra 100K_0402_5%
R460 4.7K_0402_5% KSO16 81 74 EC_MUTE#
KSO16/GPIO48 CIR_RLC_TX/GPIO41 EC_MUTE# (25)
KSO17 82 89 FSTCHG
FSTCHG (28)

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_BLUE_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_BLUE_LED# (30)
91 CAPS_LED# EC modify pin define
CAPS_LED#/GPIO53 CAPS_LED# (30)

2
EC_SMB_CK1 77 GPIO 92 BATT_RED_LED# CAPS_LED#/NUM_LED# 101309. 1
(33) EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_RED_LED# (30)
EC_SMB_DA1 78 93 PWR_LED R461 C1252
(33) EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED (30)
EC_SMB_CK2 79 SM Bus 95 SYSON Rb
+3VALW (4) EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON (8,31,37)
EC_SMB_DA2 80 121 VR_ON 33K_0402_5% 0.1U_0402_16V4Z
(4) EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (40) 2
127 ACIN
ACIN (19,32)

1
B AC_IN/GPIO59 B
1 2 EC_SMB_CK1
R462 2.2K_0402_5%
1 2 EC_SMB_DA1 (19) PM_SLP_S3#
PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# (19)
R463 2.2K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
(19) PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# (19)
1 2 KSO1 (19) EC_SMI#
EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON
EC_ON (27)
R464 47K_0402_5% HPD_7318_EC 16 103
(24) HPD_7318_EC LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# (19)
1 2 KSO2 (30) BT_LED#
BT_LED# 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 EC_PWROK
EC_PWROK (19)
EC_CRY1 EC_CRY2
R465 47K_0402_5% 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# (22)
1 2 LID_SW# (24) HPD_7318_R_EC
HPD_7318_R_EC 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF#
WL_OFF# (28) 1 1
R466 100K_0402_5% INVT_PWM 25 107 WXMIT_OFF# C1253 C1254
(22) INVT_PWM EC_THERM#/GPIO11 GPXO10 WXMIT_OFF# (28)

4
1 2 EC_LAN_PME# (4) FAN_SPEED1
FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 ON/OFF_LED# (28)
R477 4.7K_0402_5% BT_ON# 29

OUT
IN
(28) BT_ON# FANFB2/GPIO15 2 2
Add it 090909. E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16 22P_0402_50V8J 22P_0402_50V8J
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# (19)
ON/OFF 32 112 ENBKL
+3VS (27) ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL (10)
PWR_SUSP_LED EC_EAPD Change to use 22pf.091509

NC

NC
(30) PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EC_EAPD (25)
NUM_LED# 36 GPI 115
(30) NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# (19)
116 SUSP#
SUSP# (28,31,36)

3
GPXID5
1 2 EC_SMB_CK2 GPXID6 117 PBTN_OUT#
PBTN_OUT# (19)
R467 2.2K_0402_5% 118 EC_PME# 1 2
GPXID7 EC_LAN_PME# (28)
1 2 EC_SMB_DA2 EC_CRY1 122 XCLK1
R25 0_0402_5% X1
R468 2.2K_0402_5% EC_CRY2 123 124 add it 062609. 32.768KHZ_12.5P_MC-306
XCLK0 V18R
1
AGND

C1255
GND
GND
GND
GND
GND

4.7U_0805_10V4Z C1256 100P_0402_50V8J

KB926QFD3_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

20mil C1257 100P_0402_50V8J

L18 BATT_OVP 2 1
A A
ECAGND 2 1 C1258 100P_0402_50V8J
FBM-L11-160808-800LMT_0603 ACIN 2 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 29 of 41
5 4 3 2 1
 To TP/B Conn.
+3VALW 1 2 C1259 1 2 0.1U_0402_16V4Z JTP1
R470 0_0603_5% 6 8
+5VS TP_CLK 6 G2
(29) TP_CLK 5 5 G1 7
+SPI_VCC TP_DATA 4
(29) TP_DATA 4
3 3
U37 2
EC_SPICS#/FSEL# 2
(29) EC_SPICS#/FSEL# 1 CE# VDD 8 1 1
R471 1 2 4.7K_0402_5% SPI_WP# 3 6 EC_SPICLK_R R472 1 2 0_0402_5% 1 1
WP# SCK EC_SPICLK (29)
+3VALW R473 1 2 4.7K_0402_5% SPI_HOLD# 7 5 R474 1 2 0_0402_5% E-T_7182K-F06N-00R
HOLD# SI EC_SO_SPI_SI (29)

C1260

C1261
4 2 R475 1 2 0_0402_5% SP020907230 CONN@
VSS SO EC_SI_SPI_SO (29)
@ @
MX25L8005M2C-15G_SOP8 2 2 Change conn 072409.
swap net.072809.
ENE suggestion SPI Frequency over 66MHz 100P_0402_50V8J

SST: 50MHz
EC_SPICLK_R FOR EMI Take off U36.072009 JTP2 100P_0402_50V8J
GND 8

2
MXIC: 70MHz 7 TP_CLK
R476 GND
6
ST: 40MHz 22_0402_5%
+5VS TP_CLK 5
6 +5VS TP_DATA
5
@ TP_DATA 4 4 swap net.101409.

3
3

1
3 C1262
2 2
2 1 D21
1 0.1U_0402_16V4Z PJDLC05_SOT23-3
C1263 ACES_85201-0605N
10P_0402_50V8J SP01000LB00

1
1
@

Co-lay NON-ZIF CONN 091009. for EMI mount it.091509

KSI[0..7]
To Card Reader/B Conn.
INT_KBD Conn. KSO[0..15]
KSI[0..7] (29)

KSO[0..15] (29)
JKB1
PWR_SUSP_LED# JCRB1
GND2 26 +3VALW 1 1

3
GND1 25 2 2
Q16B +3VS 3
2N7002DW-T/R7_SOT363-6 3
+5VALW 4 4
(29) PWR_SUSP_LED 5 +5VS 5 5
24 KSI0 2 1 KSI0 KSO4 1 2 PWR_SUSP_LED# 6
24 6

1
23 KSI1 100P_0402_50V8J C1265 C1268 100P_0402_50V8J PWR_LED# 7

4
23 KSI2 KSI1 KSO5 R481 BATT_BLUE_LED# 7
22 22 2 1 1 2 (29) BATT_BLUE_LED# 8 8
21 KSO0 100P_0402_50V8J C1267 C1270 100P_0402_50V8J BATT_RED_LED# 9
21 KSO1 KSI2 KSO6 10K_0402_5% (29) BATT_RED_LED# MINI1_LED# 9
20 20 2 1 1 2 (28) MINI1_LED# 10 10
19 KSO2 100P_0402_50V8J C1269 C1272 100P_0402_50V8J WWAN_LED# 11

2
19 KSI3 KSI3 KSO7 (28) WWAN_LED# BT_LED# 11
18 18 2 1 1 2 (29) BT_LED# 12 12
17 KSO3 100P_0402_50V8J C1271 C1274 100P_0402_50V8J ODD BTN# 13
17 KSO4 KSI4 KSO8 (29) ODD BTN# ODD LED# 13
16 16 2 1 1 2 (29) ODD LED# 14 14
15 KSO5 100P_0402_50V8J C1273 C1276 100P_0402_50V8J CLK_SD_48M 15
15 (16) CLK_SD_48M 15
14 KSO6 2 1 KSI5 KSO9 1 2 PWR_LED# 5IN1_LED# 16
14 KSO7 100P_0402_50V8J C1275 C1278 100P_0402_50V8J 16
13 13 17 17

6
12 KSO8 2 1 KSI6 KSO10 1 2 USB20_N4 18
12 (19) USB20_N4 18
11 KSI4 100P_0402_50V8J C1277 C1280 100P_0402_50V8J Q16A USB20_P4 19 21
11 (19) USB20_P4 19 G1
10 KSO9 2 1 KSI7 KSO11 1 2 2N7002DW-T/R7_SOT363-6 20 22
10 KSI5 100P_0402_50V8J C1279 C1282 100P_0402_50V8J 20 G2
9 9 (29) PWR_LED 2
8 KSI6 2 1 KSO0 KSO12 1 2 E-T_7082K-F20N-00R
8

1
7 KSO10 100P_0402_50V8J C1281 C1284 100P_0402_50V8J SP020907241 CONN@

1
7
6 KSO11 2 1 KSO1 KSO13 1 2 R480 Change conn 072809.
6 KSI7 100P_0402_50V8J C1283 C1286 100P_0402_50V8J
5 5
4 KSO12 2 1 KSO2 KSO14 1 2 10K_0402_5%
4 KSO13 100P_0402_50V8J C1285 C1288 100P_0402_50V8J
3

2
3 KSO14 KSO3 KSO15
2 2 2 1 1 2
1 KSO15 100P_0402_50V8J C1287 C1290 100P_0402_50V8J
1 JCRB2
CONN@ +3VALW 1
ACES_85208-24071 1
2 2
SWAP KB PIN define 082009. +3VS 3 3
KB P/N:SP01000RY00 +5VALW 4 4
+5VS 5 5
PWR_SUSP_LED# 6
PWR_LED# 6
7 7
BATT_BLUE_LED# 8
BATT_RED_LED# 8
9 9
MINI1_LED# 10
WWAN_LED# 10
11

To LED/B To SW/B BT_LED#

ODD BTN#
12
13
11
12
+3VS 13
Change from 5vs to 3vs.073109. ODD LED# 14 14
CLK_SD_48M 15
JLEDB1 5IN1_LED# 15
16 16
1 1 17 17
2 USB20_N4 18
CAPS_LED# 2 JSWB1 USB20_P4 18
(29) CAPS_LED# 3 3 19 19
(29) NUM_LED# NUM_LED# 4 KSO1 1 20
4 KSI1 1 20
5 5 G1 7 2 2 21 GND
6 8 KSI5 3 5 22
+3VS 6 G2 3 GND GND
4 4 GND 6
E-T_7182K-F06N-00R ACES_87151-2005N
SP020907230 CONN@ ACES 88266-04001
5

U86 SP02000K200 CONN@

SATA_LED# 2 Co-lay NON- ZIF CONN091009.
P

(18) SATA_LED# B
4 MEDIA_LED#
5IN1_LED# Y
1 A
G

NC7SZ08P5X_NL_SC70-5
3

<BOM Structure>
+3VS
JLEDB2
1 1
add it .072009 2 2
CAPS_LED# 3
NUM_LED# 3
4 4
MEDIA_LED# 5 5
6 6
GND 7
8
GND Security Classification Compal Secret Data Compal Electronics, Inc.
ACES_85201-0605N 2009/02/27 2010/01/21 Title
Issued Date Deciphered Date
Co-lay NON-ZIF CONN 091009. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 30 of 41
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS

+5VALW +5VS +3VALW +3VS

U42 U43
8 D S 1 8 D S 1
7 D S 2 7 D S 2

2
6 D S 3 1 1 6 D S 3 1 1
1 1 1 1 5 4 C1344 C1345 R539 1 1 5 4 C1348 C1349 R545
C1340 C1341 C1342 C1343 D G C1352 C1353 D G 470_0603_5%
AP4800_SO8 10U_0805_10V4Z 470_0603_5% AP4800_SO8 10U_0805_10V4Z
2 2 2 2

5VS_GATE
100P_0402_50V8J 10U_0805_10V4Z <BOM Structure> 1U_0603_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z

1
1 2 2 2 2 2 2
10U_0805_10V4Z 1
1000P_0402_50V7K 10U_0805_10V4Z

1
D

1
D
2 SUSP
+VSB 2 1 2 1 2 SUSP +VSB 2 1 3VS_GATE G
R540 R541 G R548 S Q25

3
33K_0402_5% 120K_0402_5% S Q23 200K_0402_5% 1 2N7002_SOT23

3
1 C1356
C1347 2N7002_SOT23

1
D D 0.1U_0603_25V7K
SUSP Q24 0.1U_0603_25V7K Mount it.070709 SUSP 2
2 2
G 2 G
S Q27 S

3
2N7002_SOT23 2N7002_SOT23
<BOM Structure>

+1.5V to +1.5VS Transfer

2 2

+5VALW +5VALW
+1.5V
+1.5VS

2
U85 0.1U_0402_16V4Z
8 1 R538 R543
D S 100K_0402_5% 100K_0402_5%
1 7 D S 2
+VSB C1513 6 3
D S 1 1
10U_0805_10V4Z 5 4 C1514 C1515

1
D G SUSP
(38) SUSP
1

2 SI4800DY_SO8 10U_0805_10V4Z SYSON#

2 2 SYSON#
R1591
510K_0402_5%

1
D D
2

+1.5VS_GATE SYSON 2 Q30 2 Q33

(8,29,37) SYSON (28,29,36) SUSP#
G 2N7002_SOT23 G 2N7002_SOT23

1
1 S S

3
1

1
D C1516 R542
SUSP 2 Q47 0.1U_0603_25V7K 100K_0402_5% R547
G 10K_0402_5%
S 2N7002_SOT23 2 modify it.071109
3

2
add it.070709
3 3

Discharge circuit
+1.5V +1.5VS

+VCCP +0.75V
2

R554 R551
2

470_0603_5% 470_0603_5%
R552 R553
470_0603_5% 470_0603_5%
1

1
6

Q18A Q18B D D
2SYSON# 5 SUSP 2 SUSP 2 SUSP
G G
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 S Q31 S Q32
1

2N7002_SOT23 2N7002_SOT23
modify it.071109
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
Date: Tuesday, October 20, 2009 Sheet 31 of 41
A B C D E
 A B C D

PR1
1M_0402_1%
1 2
VIN VIN
VS

1
1 1

VIN @PR2
@ PR2
10K_0402_5%
PR3
84.5K_0402_1%
PR4

8
PL1 PR5 PR6 22K_0402_5%

2
HCB2012KF-121T50_0805 0_0402_5% 10K_0402_5% PU1A 3 1 2

P
DC_IN_S1 PACIN +
1 2 1 2 2 1 1 0
(19,29) ACIN

1
- 2

1
G
PC1
SP02000K200

1
PR7 1000P_0402_50V7K
PJP1

4
PD1 PC2 20K_0402_1%

2
1

1
6 4 PR8 RLZ4.3B_LL34 LM358DT_SO8 0.1U_0603_25V7K

2
G2 4 PC3 PC4 PC5 PC6 10K_0402_5%
5 G1 3 3
2 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K

2
2
1 1

PR9
ACES_88266-04001 10K_0402_5%
CONN@ 1 2
RTCVREF
(35) PACIN

2 2

Vin Dectector
Min. Typ Max.
- PBJ1 + H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
+RTCBATT

ML1220T13RE
45@

PJ7
2 2 1 1

JUMP_43X118
VIN 2
PJ1
1
PJ2
2 2
+3VALWP 2 1 +3VALW +1.5VP 1 1 +1.5V

2
@ PC7
@PC7 JUMP_43X118 @PC8
@ PC8 JUMP_43X118
2

0.1U_0402_16V7K (4.69A,200mils ,Via NO.= 10) 0.1U_0402_16V7K (3.464A,160mils ,Via NO.=8)

PD2

1
RLS4148_LL34-2
PD3
RLS4148_LL34-2 PJ3
1

+5VALWP 2 2 1 1 +5VALW
BATT+ 2 1
1

2
3 3

@ PC9
@PC9 JUMP_43X118
PR10 PR11 0.1U_0402_16V7K (5.58A,240mils ,Via NO.= 12)
68_1206_5% 68_1206_5%

1
PQ1
PR12 TP0610K-T1-E3_SOT23-3
PJ5
2

200_0603_5% PJ6
CHGRTCP 1 2 N1 3 1 2 1 +1.8VP 2 1 +1.8V
VS +VSBP 2 1 +VSB 2 1

2
PC11 JUMP_43X39 @PC12
@ PC12 JUMP_43X118
1

0.1U_0402_25V6 (120mA,40mils ,Via NO.= 2) 0.1U_0402_16V7K

1

PR13

1
100K_0402_1% PC14
PC13 0.1U_0603_25V7K
2

PR14 0.22U_1206_25V7K (4.6A,200mils ,Via NO.=10)

2

22K_0402_1%
1 2 PJ8 PJ9
(27) 51ON# 2 1 +VCCPP 2 1 +VCCP
+VCCGFXP 2 1 +VCCGFX 2 1
JUMP_43X118 JUMP_43X118

RTCVREF
1

PR15 (7.09A,300mils ,Via NO.=16)

200_0603_5%
PR16 PR17 PU2 G920AT24U_SOT89-3 PJ11
560_0603_5% 560_0603_5% 3.3V +VCCPP 2 1 +VCCGFX
2

N2 2 1
1 2 1 2 3 OUT IN 2
+CHGRTC JUMP_43X118
1

GND PC18
4
PC17 1U_0805_25V4Z 4

10U_0805_10V4Z 1
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic 0.1
Date: Tuesday, October 20, 2009 Sheet 32 of 41
A B C D
 A B C D

PH1 under CPU botten side :

VMB
CPU thermal protection at 92 degree C
PL2
HCB2012KF-121T50_0805
Recovery at 56 degree C
BATT_S1 1 2 BATT+ VL
VL

1
VL
PC20 PC19
1000P_0402_50V7K 0.01U_0402_25V7K

2
CONN@ PR21

1
1 1

10 47K_0402_1%
GND PC21
GND 9 MAINPWON (34)
8 PH1 0.1U_0603_25V7K PR22

1
8 PR23 1K_0402_5% 100K_0603_1%_TSM1A104F4361RZ 47K_0402_1%
7 7

1
6 B/I 1 2 1 2

2
6 TS PR24
5 5

8
4 EC_SMCA 13.7K_0402_1% PD4
4 EC_SMDA RLS4148_LL34-2
3 1 2 3

P
3 +
2 2 O 1 2 1 2
1 TM_REF1 2 PQ2
1 -

G
PU3A DTC115EUA_SC70-3
PJP2 LM393DG_SO8

4
SUYIN_200275GR008G13GZR

3
2

15.4K_0402_1%
1

1
PR27

1000P_0402_50V7K
PR28
PR25 PR26 PC22 100K_0402_1%
100_0402_1% 100_0402_1% 0.22U_0603_10V7K 2 1 VL

1
1

PC23
2
PR29

2
6.49K_0402_1%

1
2 1 +3VALW
PR30
100K_0402_1%

2
PR31
1K_0402_1%
2 2
2

BATT_TEMP (29)

PH2 near main Battery CONN :

EC_SMB_CK1 (29) BAT. thermal protection at 92 degree C
Recovery at 56 degree C
EC_SMB_DA1 (29)
VL

2
@ PR32
@PR32
VL 47K_0402_1%
@PR33
@ PR33
47K_0402_1%

1
1 2

1
PQ3 @PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL

B+ 3 1 +VSBP

2
0.22U_1206_25V7K

0.1U_0603_25V7K

PR35
1

8
@ 13.7K_0402_1% @PD5
@ PD5
1

1
PC24

PC25

1 2 5 LL4148_LL34-2

P
PR34 +
O 7 2 1
100K_0402_1% @ @ TM_REF1 6
2

G
3 3

TP0610K-T1-E3_SOT23-3 PU3B
2

1
VL LM393DG_SO8

4
1 2 @ PC26
@PC26 @ PR37
@PR37
PR36 0.22U_0603_16V7K 15.4K_0402_1%

2
22K_0402_1%

2
2

PR38
100K_0402_1%

PR39
1

0_0402_5% D
1 2 2 PQ4
(34) SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S <BOM Structure>
3
1

PC27

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 33 of 41
A B C D
 5 4 3 2 1

TPS51427_B+
TPS51427_B+
PL13 PR40
HCB2012KF-121T50_0805 0_0805_5%
1 2 1 2
B+

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.1U_0402_25V6
5

PC142
VL

5
PC28

PC29

PC32

PC30

PC31

PC33
PC141
D D

1
PQ5
AON7408L_DFN8-5

2
2

1U_0603_10V6K
PC34 4

2
0.1U_0603_25V7K

4.7U_0805_6.3V6K
4

1
PC35
1

PC36
PQ6

1
AON7408L_DFN8-5 +5VALWP

3
2
1
1
2
3
PL4
PL3 2.2UH_MMD-06AH-2R2M-X2A_6A_20%

7
2.2UH_MMD-06AH-2R2M-X2A_6A_20% PU4 PC37 2 1
1 2 1U_0603_10V6K

V5FILT

LDO
VIN
+3VALWP

3
33 TP V5DRV 19 1 2

1
1
DH3 26 15 DH5 PR41 @
@ PR45 PR42 0_0603_5% DRVH2 DRVH1 PR43 0_0603_5% 4.7_1206_5%
4.7_1206_5% 2 1 BST3A 24 17 BST5A 2 1
VBST2 VBST1
1

63.4K_0402_1%
1 2

2
2

2
PR44 2 PC41

2
+

PR46
PC38 0_0402_5% PC39 0.1U_0603_25V7K

2
150U_B2_6.3VM 0.1U_0603_25V7K

1
1
LX3 25 16 LX5 PC42 @ 1
2

1
2 @ PC40 LL2 LL1 680P_0402_50V7K

2
680P_0402_50V7K + PC43

2
PQ7 DL3 23 18 DL5 PQ8 150U_B2_6.3VM

1
IRFH3707TRPBF_PQFN8-3 DRVL2 DRVL1 IRFH3707TRPBF_PQFN8-3
2
2

10K_0402_1%
C 22 C
PGND

2
FB3 30 VOUT2

PR48
@ PR47
10K_0402_1% 10
VOUT1
VL 32
1

REFIN2

1
11 FB5
2VREF_TPS51427 FB1

1 2 1 VREF2
PC44 0.22U_0603_10V7K
VSW 9
8 LDOREFIN @ PR49 0_0402_5%
SKIPSEL 29 2 1 VL
PR50 0_0402_5%
1 2
20 NC PGOOD2 28
PD6 PR51
GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK (33)
VS EN_LDO PGOOD1 PR53
2
200K_0402_1%

200K_0402_1%
2
PR52

14 12 ILM1 2 1
PC45 EN1 TRIP1
0.22U_0603_10V7K

TONSE
VREF3
1

27 31 ILIM2 2 1

GND
1

EN2 TRIP2
1

B B

2
PR54
VL

0_0402_5%
PD7 @ PR55 SN0806081RHBR_QFN32_5X5 200K_0402_1%

21
PR56
1SS355TE-17_SOD323-2 0_0402_5%
2
2

PR57
1

1
1U_0603_10V6K
806K_0603_1% 2VREF_TPS514271

PR59 @ PR60 PR58

1

2
PC46
0_0402_5% 47K_0402_5% 0_0402_5%
+3.3VALWP Ipeak=4.687A ; Imax=3.281A 2 1 1 2

2VREF_TPS514272
1
Choke DCRmax=40m ohm (33) MAINPWON
0.047U_0603_16V7K

+5VALWP Ipeak=5.58A ; Imax=3.906A

Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical) Choke DCRmax=40m ohm
1

PC47

Vlimit=(5E-06 * 200K)/10=100mV Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)

Ilimit=100mV/17.9m ~100mV/14.5m Vlimit=(5E-06 * 200K)/10=100mV
2

=5.58A ~ 6.89A
1

Ilimit=100mV/17.9m ~ 100mV/14.5m
Iocp=Ilimit+Delta I/2 @ PC48
=5.58A ~ 6.89A
3

0.047U_0402_16V7K
=6.54A ~ 6.659A
2

Iocp=Ilimit+Delta I/2
Delta I=1.933A (Freq=300KHz) =6.559A ~ 7.869A
2 PQ9 Delta I=1.959A (Freq=400KHz)
TP0610K-T1-E3_SOT23-3

A A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 34 of 41

5 4 3 2 1
 A B C D

P2 P3 B+
PQ10
P1403EVG_SO8
PQ11
P1403EVG_SO8 PR61
B+ PQ12
P1403EVG_SO8
VIN 8 1 1 8 2 1 1 8
7 2 2 7 2 7
6 3 3 6 0.05_1206_1% 3 6
5 5 5
1 1

5600P_0402_25V7K
PR63

4
CSIP CSIN 47K_0402_1%

2
0.1U_0603_25V7K
1 2
VIN

PC50
VMB

PC49
PR62 PD8

2
200K_0402_1% 1SS355TE-17_SOD323-2

2
1

PR66 1 2 ACOFF

2
PR64 10K_0402_1%

1
47K_0402_1%
3

PR68

1 1
PQ14 VS PR91 200K_0402_1%
2

DTA144EUA_SC70-3 340K_0402_1% 1 2 VIN

2

2
0.01U_0402_25V7K
PD11
PQ16 1SS355TE-17_SOD323-2
DTC115EUA_SC70-3 2 1 2

PC70

1
1
1

PR93

0.1U_0603_25V7K
499K_0402_1%

1
D
1

1
PC57
2 PACIN

2
8
2 PR94 PU1B G
PQ17 10K_0402_1% LM358DT_SO8 5 S PQ18

3
DTC115EUA_SC70-3 PR73 + 2N7002W-T/R7_SOT323-3
1 2 7 0
150K_0402_1% (29) BATT_OVP 6
2

G
3
1

1
D

0.01U_0402_25V7K
4

1
2 PQ20 PR95

PC71
G RHU002N06_SOT323-3 105K_0402_1%
S
3

2
2 2

2
PQ22
1

2N7002W-T/R7_SOT323-3 D
2
G
PR80 S
3

22K_0402_5% BATT+
PACIN 1 2
(32) PACIN

ACON
ACON

10U_1206_25V6M

10U_1206_25V6M
0.1U_0402_25V6

0.1U_0402_25V6
1

PQ24

1
PC148

PC147

PC66

PC67
DTC115EUA_SC70-3

2
ACOFF 2
(29) ACOFF
3

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 35 of 41
A B C D
 A B C D

+3VALW
+5VALW

4.7U_0805_6.3V6K
2

PC79
1U_0402_6.3V6K
1 1

PC77

1
2
PU6
6
5
VCNTL
VIN VOUT 3 +1.8VP
PR97 9 4
VIN VOUT

1
0_0402_5%

22U_0805_6.3V6M
(28,29,31) SUSP# 2 1 8
7
EN
2
PR103
1.5K_0402_1%
PC72
0.01U_0402_25V7K

GND
POK FB

2
1

PC73
PR98

2
PC80 47K_0402_5% APL5913-KAC-TRL_SO8

1
1U_0603_10V6K

2
1
2
PR104
1.2K_0402_1%

2
2 2

PL15
HCB1608KF-121T30_0603
1.05V_B+ 1 2 B+

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC81

PC82

PC83
PC146

5
0.1U_0402_25V6

2
PR106
300K_0402_5% 4
1 2
PR108 PQ27
PR107 0_0402_5% 2.2_0603_5% AON7408L_DFN8-5
1 2 BST_1.05V1 2
(28,29,31) SUSP#

3
2
1
1

PR109 PC84 PL7

15

14
1

30K_0402_5% @PC85
@PC85 PU7 0.1U_0603_25V7K 2.2UH_MMD-06AH-2R2M-X2A_6A_20%
0.1U_0402_16V7K BST_1.05V-1 1 2 1 2
EN_PSV

TP

VBST +VCCPP
2
2

2 13 DH_1.05V
TON DRVH

1
PR111 3 12 LX_1.05V PR110
VOUT LL

5
100_0603_1% 4.7_1206_5% 1
+5VALW 1 2 4 11 1 2 +5VALW PQ28
V5FILT TRIP PR112 + PC86

2
3 3

5 10 10K_0402_1% 330U_B2_2.5VM_R15M
VFB V5DRV
1

1
DL_1.05V PC88 2
6 PGOOD DRVL 9 4
PGND

PC87 680P_0603_50V7K
GND

4.7U_0603_6.3V6K PC89
2

2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC90
7

3
2
1
4.7U_0805_10V6K

2
AON7702L_DFN8-5
PR113
8.2K_0402_1%
1 2
1

PR114
20.5K_0402_1%
<Vo=1.05V> VFB=0.75V
2

Vo=VFB*(1+PR113/PR114)=0.75*(1+8.2K/20.5K)=1.05V
Fsw=261KHz

Cout ESR=15m ohm Rdson(max)=17.9m Rdson(min)=14.5m

Ipeak=5A, Imax=5A, Iocp=6A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=1.72A
=>1/2DeltaI=0.86A
4
Vtrip=Rtrip*10uA=12K*10uA=0.12V 4

Iocpmin=Vtrip/Rdsonmax*1.2+0.86
=0.12/(0.0179*1.2)+0.86=6.446A
Iocpmax=(0.12/(0.0145*1.2))+0.86A=7.756A
Iocp=6.446A~7.756A Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VP / +VCCPP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 36 of 41

A B C D
 A B C D

PL16
HCB1608KF-121T30_0603
1.5V_B+ 1 2 B+

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 1

0.1U_0402_25V6
1

1
PC140

PC91

PC92

PC145
5

2
PR115
300K_0402_5% 4
1 2
PR116 PR117
0_0402_5% 2.2_0603_5% PQ29
1 2 BST_1.5V 1 2 AON7408L_DFN8-5
(8,29,31) SYSON

3
2
1
1

1
PR118 PL8

15

14
1
30K_0402_5% PC94 PU8 PC93 2.2UH_MMD-06AH-2R2M-X2A_6A_20%
@0.1U_0402_16V7K BST_1.5V-1 1 2 1 2

EN_PSV

TP

VBST
+1.5VP

2
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON DRVH

1
PR120 3 12 LX_1.5V
VOUT LL

5
100_0603_1% PR119 1
+5VALW 1 2 4 11 1 2 +5VALW 4.7_1206_5%
V5FILT TRIP PR121 + PC95

2
5 10 15K_0402_1% 330U_B2_2.5VM_R15M
VFB V5DRV

1
DL_1.5V 2
6 PGOOD DRVL 9 4

PGND
PC96 PC97

GND
1

10K_0402_5%
4.7U_0603_6.3V6K PC98 680P_0603_50V7K
2

2
1
PR194
2
@ 47P_0402_50V8J 2

1 2 TPS51117RGYR_QFN14_3.5x3.5 PC99

3
2
1
4.7U_0805_10V6K

2
2
<Vo=1.5V> VFB=0.75V PQ30
PR122 AON7702L_DFN8-5
Vo=VFB*(1+PR91/PR92)=0.75*(1+28.7K/20.5K)=1.53V 10.5K_0402_1% +1.5V
Fsw=262KHz 1 2
1

Cout ESR=15m ohm Rdson(max)=17.9m Rdson(typ)=14.5m (8) DDR3_PG

Ipeak=4.5A, Imax=3.15A, Iocp=5.4A PR123
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.397A 10K_0402_1%
=>1/2Delta I=1.199A
2

Vtrip=Rtrip*10uA=14K*10uA=0.140V
Iocpmin=Vtrip/Rdsonmax*1.2+1.199
=0.140/(0.0179*1.2)+1.199=7.717A
Iocpmax=(0.140/(0.0145*1.2))+1.199A=9.245A
Iocp=7.717A~9.245A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 37 of 41

A B C D
 5 4 3 2 1

+1.5V

D
PU9 D
1 6
VIN VCNTL
+3VALW
2 GND NC 5

1
PC101

1
PC100 3 7 1U_0603_6.3V6M
4.7U_0805_6.3V6K PR130 VREF NC

2
1K_0402_1% 4 8
VOUT NC
9

2
TP
APL5336KAI-TRL SOP

0.1U_0402_16V7K
PR133
+0.75V

1
0_0402_5% PQ32 D

PC102
(31) SUSP 1 2 2 PR134

1
G 1K_0402_1%

2
1
S PC103

3
PC104 2N7002W-T/R7_SOT323-3 10U_0805_6.3V6M

2
0.1U_0402_16V7K

Ipeak=1A, Imax=0.7A

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 38 of 41

5 4 3 2 1
 A B C D E F G H

PR143
124K_0402_1%
2 1

PR144
@1_0603_5%
1 +5VS 1 2 1

1
PC108

V5FILT_GFX
1U_0603_10V6K

1
VREF_GFX
2

1
PR145 PR146
PC109 0_0402_5% 0_0402_5%
68P_0402_50V8J

2
1 2 PR149

2
1 2 1 2 GFXVR_EN (8)
PR147

0.22U_0603_10V7K
3.16K_0402_1%
0_0402_5%

2
GFX_B+

PC110

33

32

31

30

29

28

27

26

25
PU11

VREF_GFX

TP

DROOP

V5FILT

ISLEW

OSRSEL

TONSEL

TRIPSEL

PWRMON

VR_ON
1
PC111 33P_0402_50V8K PL9
1 2 HCB1608KF-121T30_0603
2 1 B+
PR148 470_0402_1%

0.1U_0402_25V6
2200P_0402_50V7K

4.7U_0805_25V6-K
1 24

4.7U_0805_25V6-K
CSN_GFX 1 VREF CLKEN#
2

1
PC115
2 23

PC114
PC113
GND DPRSLP

PC116
PC112 33P_0402_50V8K

2
1 2 3 CSN PGOOD 22

2
PR150 470_0402_1% PC117
CSP_GFX 1 2 100P_0402_50V8J 4 21 4 Load line: -6.9mV/A

1
CSP V5IN PQ37
PR151 TPS51610RHB_QFN32_5X5 AON7408L_DFN8-5 DCR: 10mohm
1 2 GND_SENSE 5 20 LGATE_GFX PL10
0_0402_5% GNDSNS DRVL
OCP: 9.6A

3
2
1
+VCCGFX 2.2UH_MMD-06AH-2R2M-X2A_6A_20%
1 2 +VCCGFX_SENSE 6 VSNS LL 19 PHASE_GFX 1 2 +VCCGFXP
PR152 0_0402_5%

330U_B2_2.5VM_R15M
2 2

1
Parellel from VCCGFX and GND underneath GMCH at Interface Power pin 7 18 BOOT_GFX 1 2 1 2 1
THERM VBST

5
PR154 PR155
+

PC119
PR156 PR153 PC118 4.7_1206_5% 137K_0402_1%

DPRSTP#
1 2 8 17 UGATE_GFX 2.2_0603_5% 0.22U_0603_10V7K PR157
20K_0402_1% VR_TT# DRVH PH3 15K_0402_1%

VID6

VID5

VID4

VID3

VID2

VID1

VID0

1 2

2
2
1 2 1 2
4 PC122
150K_0603_5%_ERTJ1VV154J

10

11

12

13

14

15

16

2
680P_0603_50V8J
+3VS PQ38 1 2

3
2
1
AON7702L_DFN8-5 PR159
10K_0402_1%
+5VS 1 2
1 PR160 2 10K_0402_5% 1 2
PC123
V5FILT_GFX 4.7U_0603_6.3V6K PC124

CSP_GFX
1000P_0402_50V8-J

CSN_GFX
PR161 1 2 0_0402_5%
(8) DFGT_VID_4
PR162 1 2 0_0402_5%
(8) DFGT_VID_3
PR163 1 2 0_0402_5%
(8) DFGT_VID_2
PR164 1 2 0_0402_5%
(8) DFGT_VID_1
PR165 1 2 0_0402_5%
(8) DFGT_VID_0

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 39 of 41
A B C D E F G H
 A B C D E F G H

PR166
124K_0402_1%
2 1

@ PR167
1_0603_5%
1 +5VS 1 2 1

1
PC125
1U_0603_10V6K Ipeak=10A

1
VREF_CPU
2

1
PR170 Iocp=18.2A
PR168 PR169 @ 0_0402_5%
PC126 0_0402_5% 0_0402_5% Choke DCR=0.007ohm(max)
27P_0402_50V8J

2
1 2

2
PMON
1 2 +3VS
VR_ON (29)
PR171

0.22U_0603_10V7K
4.12K_0402_1%

2
PC127

33

32

31

30

29

28

27

26

25

1
PU12

VREF_CPU
PR174 +CPU_B+

TP

DROOP

V5FILT

ISLEW

OSRSEL

TONSEL

TRIPSEL

PWRMON

VR_ON
1
PC128 33P_0402_50V8K 10K_0402_1% PL11
1 2 HCB2012KF-121T50_0805
@ PR172 0_0402_5% 1 2 B+

2
PR173 470_0402_1% 1 24 2 1
VREF CLKEN# CLKEN# (16)
CSN 1 2

4700P_0402_25V7K
PR175 0_0402_5%

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2

2
PC129
2 GND DPRSLP 23 2 1 PM_DPRSLPVR (8,19)

5
6
7
8

PC130

PC131

PC132
PC133 33P_0402_50V8K PQ39

1
1 2 3 22 AO4474_SO8
CSN PGOOD VGATE (8,16,19)

2
PR176 PR177 470_0402_1% PC134
100_0402_1% CSP 1 2 100P_0402_50V8J 4 21 4

1
CSP V5IN
1 2
TPS51610RHB_QFN32_5X5
(5) VSSSENSE 5 20 LGATE_CPU
GNDSNS DRVL PL12

3
2
1
0.33UH_MMD-06AH-R33M-V1_6A_20%
(5) VCCSENSE 6 19 PHASE_CPU 1 2 +CPU_CORE
VSNS LL
2 +CPU_CORE 1 2 2

1
PR178 7 18 BOOT_CPU 1 2 1 2
THERM VBST

5
100_0402_1% PR180

1
PR179 PC135 91K_0402_1%

DPRSTP#
2 1 1 2
PR181 8 17 UGATE_CPU 0_0603_5% 0.22U_0603_10V7K PR182 @ PR183
10K_0402_1% PH4 VR_TT# DRVH 6.8_1206_5% 43.2K_0402_1%

VID6

VID5

VID4

VID3

VID2

VID1

VID0

2
150K +-5% ERTJ1VV154J 0603 1 2 1 2
4

2
(4) H_PROCHOT# H_PROCHOT# PH5

10

11

12

13

14

15

16
150K +-5% ERTJ1VV154J 0603

1
PC136 @
+VCCPP 2 1 PQ40 680P_0603_50V8J 1 2

3
2
1
PR184 NTMFS4946NT1G_SO8FL-5 PR185

2
68_0402_5% 24.9K_0402_1%
+5VS 1 2
PR186 1 2 0_0402_5% 1 2
(5,8,18) H_DPRSTP#
PR187 1 2 0_0402_5% PC137
(5) CPU_VID6
PR188 1 2 0_0402_5% 4.7U_0603_6.3V6K PC138

CSP
(5) CPU_VID5
PR189 1 2 0_0402_5% 3300P_0402_50V7-K

CSN
(5) CPU_VID4
PR190 1 2 0_0402_5%
(5) CPU_VID3
PR191 1 2 0_0402_5%
(5) CPU_VID2
PR192 1 2 0_0402_5%
(5) CPU_VID1
PR193 1 2 0_0402_5%
(5) CPU_VID0

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic0.1
Date: Tuesday, October 20, 2009 Sheet 40 of 41
A B C D E F G H
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D D

1 Change PR121 to 18K modify 1.5VP OCP to 12A 0.2 44 Change PR121 to 18K 08/23 EVT2

2 Change GFXVCCP OCP Change GFXVCCP OCP to 9.1A 0.2 46 Change PR147 PR155 PH3 PR157 PR159 PC124 08/23 EVT2

3 Improve VCCP Efficiency Decrease L/S DCR value to 11m ohm 0.3 43 Change PQ28 from IRE3707 to AON7702L 09/16 DVT

4 Change VCCP OCP Change VCCP OCP to 6.8A~8.4A 0.3 43 Change PR112 from 12K to 10K 09/16 DVT

5 Delete 0.75V enable signal Delete 0.75V enable signal(reserve) 0.3 45 Delete PR131 09/16 DVT

6 Change GFXVCCP OCP Change GFXVCCP OCP to 9.1A 0.3 46 Change PR147 PR155 PH3 PR157 PR159 PC124 09/16 DVT

7 Change PR121 to 15K modify 1.5VP OCP to 10A 0.3 44 Change PR121 to 15K 09/16 DVT

C 8 C

10

11

12

13

14

15
B B

16

17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20
Date: Tuesday, October 20, 2009 Sheet 41 of 41
5 4 3 2 1