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1 1

2 Compal Confidential 2

Schematic Document
Crestline + ICH8
2007 / 11 / 14 Rev:0.2
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 1 of 49
A B C D E
A B C D E

Compal confidential http://laptopblue.vn


SMB 13.3
File Name : LA-4231P
ZZZ1

PCB Thermal Sensor Mobile Merom


1 1
ADM1032ARMZ
P.4 uFCPGA-478 CPU
P.4,5,6
CRT CK505 TSSOP-64
P.15
Fan conn Clock Generator
P.4 H_A#(3..35)
FSB ICS 9LPRS365
H_D#(0..63) 667/800MHz 1.05V
P.16
LVDS Panel Interface DDR2 667MHz 1.8V DDR2-SO-DIMM X2
P.15 BANK 0, 1, 2, 3 P.13,14

Intel Crestline MCH


nVidia Dual Channel
NB8M-GS FCBGA 1299
VRAM x 2 USB conn x 4
P.34,35,36,37 P.7,8,9,10,11,12
P.38 P.32
2 2

CardBus Controller PCI DMI X4 C-Link FingerPrinter


P.32

O2MICRO OZ129
P.40 Felica Conn
USB2.0 P.32

Intel ICH8 Azalia


BT Conn
1394 Media Card P.32

PCI-E BUS mBGA-676 SATA Master


SATA Slave
P.17,18,19,20 Camera Mic
P.32

10/100/1000 LAN Mini-Card-1 Mini-Card-2 Express Card Express Card


REALTEK P.22 (WLAN) P.28
P.24 P.24 P.28
RTL8111C-GR
3 3
Mini-Card-2 P.24

RJ45/11 CONN
LPC BUS

Audio CKT AMP & Audio Jack


ALC268 P.25 P.26
ENE KB926
TPM CONN P.29
P.29 SATA HDD Connector
P.21
Touch Pad CONN. Int.KBD BIOS(System/EC)
Power On/Off CKT.
P.31 P.31 P.29
CDROM Conn.
4
P.21 4

DC/DC Interface CKT. RTC CKT.


P.18

Security Classification Compal Secret Data Compal Electronics, Inc.


2007/1/15 2008/1/15 Title
Power Circuit DC/DC Power OK CKT. Issued Date Deciphered Date
Block diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 2 of 49
A B C D E
A B C D E

O MEANS ON X MEANS OFF


Voltage Rails
http://laptopblue.vn STATE

Full ON
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#

HIGH HIGH HIGH HIGH


+VALW

ON
+V

ON
+VS

ON
Clock

ON
+5VS
power
plane +3VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+1.8VS
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+1.5VS
+B +5VALW +3V
1
+1.25VS CLOCK S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+3VALW +1.8V
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE
State
+VCCP

Board ID Table for AD channel


Vcc 3.3V +/- 5%
S0 O O O O O Ra / Rc 100K +/- 5%
Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
S3 0 0 0 V 0 V 0 V
O O O X O
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
S5 S4/AC 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
O O X X O
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
S5 S4/ Battery only 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
O X X X X
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
S5 S4/AC & Battery 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
don't exist X X X X X
7 NC 2.500 V 3.300 V 3.300 V
2 2

BOARD ID Table BTO Option Table


O MEANS ON S3 : STR
X MEANS OFF
Board ID PCB Revision BTO Item BOM Structure
S4 : STD 0 0.1
S5 : SOFT OFF 1 0.2
External PCI Devices 2
Device IDSEL# REQ#/GNT# Interrupts
3
CardBus AD21 0 PIRQE/PIRQF/PIRQG
4
5
6
7

3 EC SM Bus1 address EC SM Bus2 address 3

Device Address Device Address


Smart Battery 0001 011X b? ADM1032 4D
EEPROM(24C16/02) 1010 000X b?
(24C04) 1011 000Xb?

ICH7 SM Bus address


Device Address

Clock Generator 1101 001Xb?


(ICS ICS9LPR310)
DDRII DIMM0 1001 000Xb?
DDRII DIMM2 1001 010Xb?

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 3 of 49
A B C D E
5 4 3 2 1

7 H_A#[3..16]
JP2A
http://laptopblue.vn XDP Reserve
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 7 +VCCP

ADDR GROUP 0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER# XDP_TDI R172 1 150_0402_1%
M3 A[7]# DEFER# H5 H_DEFER# 7 2
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY# XDP_TMS R171 1 2 39_0402_1%
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0# R89
P5 A[11]# BR0# F1 H_BR0# 7
D H_A#12 56_0402_5% D
P2

CONTROL
H_A#13 A[12]# H_IERR# XDP_BPM#5 R362 1 54.9_0402_1%
L2 A[13]# IERR# D20 2 1 +VCCP 2
H_A#14 P4 B3 H_INIT# @
A[14]# INIT# H_INIT# 18
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET# XDP_TRST# R182 1 2 560_0402_5%
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0
7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7
H_REQ#1 H2 F4 H_RS#1 XDP_TCK R170 1 2 27_0402_5%
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
A[17]# HITM# H_HITM# 7
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4 T28

ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1
A[20]# BPM[1]# T27
H_A#21 XDP_BPM#2

XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1 T48
H_A#22 Y5 AC4 XDP_BPM#3
A[22]# BPM[3]# T29
H_A#23 U1 AC2 XDP_BPM#4
A[23]# PRDY# T47
H_A#24 R4 AC1 XDP_BPM#5
H_A#25 A[24]# PREQ# XDP_TCK
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI
H_A#27 A[26]# TDI XDP_TDO
W2 A[27]# TDO AB3 T33
H_A#28 W5 AB5 XDP_TMS
H_A#29 A[28]# TMS XDP_TRST#
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET#
A[30]# DBR# XDP_DBRESET# 19
H_A#31 V4
H_A#32 A[31]#
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]# H_PROCHOT#
AB2 A[34]# 2 1 +VCCP
H_A#35 AA3 D21 R114 56_0402_5%
C H_ADSTB#1 A[35]# PROCHOT# H_THERMDA C
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
H_A20M# THERMDC
18 H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP#
18
18
H_FERR#
H_IGNNE#
H_IGNNE# C4
FERR#
IGNNE#
THERMTRIP# H_THERMTRIP# 7,18 FAN1 Control and Tachometer
H_STPCLK# D5
18 H_STPCLK# STPCLK#
H_INTR C6 H CLK
18 H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
18 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16
H_SMI# A3 A21 CLK_CPU_BCLK#
18 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 16
M4 RSVD[01]
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2 RSVD[03]
V3 Trace width / Spacing = 10 / 10 mil
RSVD[04]
RESERVED

B2 C76
RSVD[05] 10U_1206_16V4Z~N
C3 RSVD[06]
D2 RSVD[07] 2 1
+5VS
D22 RSVD[08] H_THRMTRIP# should connect C69
D3 RSVD[09]
F6 to ICH8 and GMCH without 1000P_0402_50V7K~N 1 2
RSVD[10] C77 10U_1206_16V4Z~N
T-ing (No stub) 2 1
+VCCP
Add on 1003 U3
Merom Ball-out Rev 1a 1 8
conn@ VEN GND
2 VIN GND 7
1

FAN1_POWER 3 6
R108 EN_DFAN1 VO GND
29 EN_DFAN1 4 VSET GND 5

@ 56_0402_5% +3VS RT9027BPS SO 8P


+VCCP
2 2

1
JFAN1
40mil
B

B @ R41 R61 B
1 1
54.9_0402_1% 10K_0402_5% 2 2
E

H_PROCHOT# 3 1 OCP# 1 2 H_RESET# 3


OCP# 19 3
C

@ Q11

2
MMBT3904_SOT23 4
29 FAN_SPEED1 GND
2 5 GND
C94 ACES_85205-03001
0.01U_0402_16V7K conn@
1
FAN1

Thermal Sensor EMC1402-1-ACZL-TR


+3VS

2
C424
1

0.1U_0402_16V4Z~N R354
1 @ 10K_0402_5%
U2
1 8 EC_SMB_CK2
2

VDD SCLK
H_THERMDA 2 7 EC_SMB_DA2
C423 D+ SDATA
1 2 H_THERMDC 3 6 THERM_SCI# 2 1
D- ALERT# EC_THERM# 19,29
@ R355
2200P_0402_50V7K~N THERM# 4 5 0_0402_5%
THERM# GND
A R350 A

+3VS 1 2 EMC1402-2-ACZL-TR MSOP 8P

10K_0402_5% Address:100_1100

EC_SMB_CK2
29,31,35 EC_SMB_CK2
29,31,35 EC_SMB_DA2
EC_SMB_DA2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 4 of 49
5 4 3 2 1
5 4 3 2 1

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+CPU_CORE +CPU_CORE
7 H_D#[0..15] H_D#[32..47] 7
JP2B JP2C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 D[13]# D[45]# AA23 B14 VCC[014] VCC[081] AD14
H_D#14 K22 AA24 H_D#46 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7 VCC[017] VCC[084]
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21
H_D#30 T25 AF22 H_D#62 E12 V6
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7 VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] +
H_DINV#1 N24 AC20 H_DINV#3 E18 J21 C140
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]
E20 VCC[041] VCCP[07] K21
V_CPU_GTLREF AD26 R26 COMP0 F7 M21 330U_V_2.5VM
R91 GTLREF COMP[0] VCC[042] VCCP[08] 2
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
R90 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T14 C24 Y1 F12 R21
TEST4 TEST3 COMP[3] VCC[045] VCCP[11]
T13 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
T49 AF1 E5 H_DPRSTP# 7,18,49 F15 T21
TEST5 DPRSTP# VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
T15 TEST6 A26 B5 H_DPSLP# F17 T6
TEST6 DPSLP# H_DPSLP# 18 VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
16 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 18 VCC[050] VCCP[16]

R174

R173

R87

R88
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
16 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
16 CPU_BSEL2 BSEL[2] PSI# H_PSI# 49 VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K~N
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_10V4Z~N
Merom Ball-out Rev 1a AA12
conn@ VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 49
AA15 VCC[056] VID[1] AF5 CPU_VID1 49 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 49

C412

C409
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18 VCC[058] VID[3] AF4 CPU_VID3 49
AA20 AE3 CPU_VID4 49
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
2 2
VCC[060] VID[5] CPU_VID5 49
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10 VCC[061] VID[6] AE2 CPU_VID6 49
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE 49
166 0 1 1 COMP[0,2] trace width is AB15 VCC[065] Near pin B26
AB17 VCC[066]
18 mils. COMP[1,3] trace AB18 VCC[067] VSSSENSE AE7 VSSSENSE VSSSENSE 49
B width is 4 mils. Merom Ball-out Rev 1a B
200 0 1 0
conn@ .
Length match within 25 mils.
The trace width/space/other is
20/7/25.
+VCCP
1

R86
1K_0402_1%
+CPU_CORE
2

V_CPU_GTLREF R359
100_0402_1%
1 2 VCCSENSE
1

R360
R85 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2

Close to CPU pin AD26


within 500mils. Close to CPU pin
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 5 of 49
5 4 3 2 1
5 4 3 2 1

High Frequence Decoupling


10uF 0805 X5R -> 85 degree.
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+CPU_CORE Place these caps inside
the CPU socket.
Place these caps inside 1 1 1 1 1 1 1 1 1 1 ( Left side on Top ).
the CPU socket cavity. C1150 C1151 C1152 C1153 C1154 C1155 C1156 C1157 C1158 C1159
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
( Left side on Top ). 2 2 2 2 2 2 2 2 2 2

D D

JP2D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11
A14
VSS[003] VSS[084] P24
R2
+CPU_CORE Place these caps inside
VSS[004] VSS[085]
A16 VSS[005] VSS[086] R5 the CPU socket.
A19 VSS[006] VSS[087] R22 Place these caps inside
A23 VSS[007] VSS[088] R25 1 1 1 1 1 1 1 1 1 1 ( Right side on Top ).
AF2 VSS[008] VSS[089] T1 the CPU socket cavity. C1160 C1161 C1162 C1163 C1164 C1165 C1166 C1167 C1168 C1169
B6 VSS[009] VSS[090] T4
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B8 VSS[010] VSS[091] T23 ( Right side on Top side). 2 2 2 2 2 2 2 2 2 2
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
+CPU_CORE
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16
C19
VSS[021] VSS[102] W4
W23
Place these caps inside 1 1 1 1 1 1
VSS[022] VSS[103]
C2 VSS[023] VSS[104] W26 the CPU socket cavity. C1170
10U_0805_6.3V6M
C1171
10U_0805_6.3V6M
C1172
10U_0805_6.3V6M
C1173
10U_0805_6.3V6M
C1174
10U_0805_6.3V6M
C1175
10U_0805_6.3V6M
C22 VSS[024] VSS[105] Y3
2 2 2 2 2 2
C25 VSS[025] VSS[106] Y6 ( Left side on Bottom ).
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
+CPU_CORE
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6
E8
VSS[036] VSS[117] AA25
AB1
Place these caps inside 1 1 1 1 1 1
VSS[037] VSS[118]
E11 VSS[038] VSS[119] AB4 the CPU socket cavity. C1176
10U_0805_6.3V6M
C1177
10U_0805_6.3V6M
C1178
10U_0805_6.3V6M
C1179
10U_0805_6.3V6M
C1180
10U_0805_6.3V6M
C1181
10U_0805_6.3V6M
E14 VSS[039] VSS[120] AB8
2 2 2 2 2 2
E16 VSS[040] VSS[121] AB11 ( Right side on Bottom ).
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 AC8
F19
F2
VSS[048]
VSS[049]
VSS[129]
VSS[130] AC11
AC14
ESR <= 1.5m ohm
F22
VSS[050]
VSS[051]
VSS[131]
VSS[132] AC16 Near CPU CORE regulator Capacitor > 1980uF
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
+CPU_CORE
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25 1 1 1 1
J25 VSS[064] VSS[145] AE1
K1 AE4 C190 + C429 + C207 + C426 +
VSS[065] VSS[146]
K4 VSS[066] VSS[147] AE8
K23 AE11 @
VSS[067] VSS[148] 2 2 2 2
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 330U_V_2.5VM330U_V_2.5VM330U_V_2.5VM 330U_V_2.5VM
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11 Place these inside
N1 VSS[077] VSS[158] AF13 socket cavity on L8
N4 VSS[078] VSS[159] AF16 (North side
N23 VSS[079] VSS[160] AF19
N26 AF21
Secondary)
VSS[080] VSS[161] +VCCP
P3 VSS[081] VSS[162] A25
VSS[163] AF25

Merom Ball-out Rev 1a 1


conn@ . 1 1 1 1 1 1
+ C210 C209 C208 C185 C183 C184
C212

220U_D2_4VY_R15M

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 6 of 49
5 4 3 2 1
5 4 3 2 1

U4B For Crestline: 20ohm

http://laptopblue.vn
H_A#[3..35] 4
5 H_D#[0..63] U4A For Calero: 80.6ohm
J13 H_A#3 P36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0
E2 H_D#_0 H_A#_4 B11 P37 RSVD2 SM_CK_0 AV29 M_CLK_DDR0 13
H_D#1 G2 C11 H_A#5 R35 BB23 M_CLK_DDR1 M_CLK_DDR1 13
H_D#2 H_D#_1 H_A#_5 H_A#6 RSVD3 SM_CK_1 M_CLK_DDR2
G7 H_D#_2 H_A#_6 M11 N35 RSVD4 SM_CK_3 BA25 M_CLK_DDR2 14
+1.8V

0.01U_0402_25V7K~N
2.2U_0603_106K
H_D#3 M6 C15 H_A#7 AR12 AV23 M_CLK_DDR3 M_CLK_DDR3 14
H_D#4 H_D#_3 H_A#_7 H_A#8 RSVD5 SM_CK_4
H7 H_D#_4 H_A#_8 F16 AR13 RSVD6
H_D#5 H3 L13 H_A#9 2 2 AM12 AW30 M_CLK_DDR#0
H_D#_5 H_A#_9 RSVD7 SM_CK#_0 M_CLK_DDR#0 13

1
H_D#6 G4 G17 H_A#10 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 13
H_D#7 F3 C14 H_A#11 R331 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 14

C400

RSVD
C398
H_D#8 N8 K16 H_A#12 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 1 1 RSVD10 SM_CK#_4 M_CLK_DDR#3 14
H_D#9 H2 B13 H_A#13 1K_0402_1% AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 RSVD11 DDR_CKE0_DIMMA
M10 L16 AL36 BE29 DDR_CKE0_DIMMA 13

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RSVD12 SM_CKE_0 DDR_CKE1_DIMMA
N12 H_D#_11 H_A#_15 J17 AM37 RSVD13 SM_CKE_1 AY32 DDR_CKE1_DIMMA 13
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
N9 H_D#_12 H_A#_16 B14 D20 RSVD14 SM_CKE_3 BD39 DDR_CKE2_DIMMB 14

1
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB 14
H_D#14 P13 P15 H_A#18 R332
H_D#15 H_D#_14 H_A#_18 H_A#19 3.01K_0402_1% DDR_CS0_DIMMA#
K9 H_D#_15 H_A#_19 R17 SM_CS#_0 BG20 DDR_CS0_DIMMA# 13
H_D#16 M2 B16 H_A#20 NA lead free BK16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 SM_CS#_1 DDR_CS1_DIMMA# 13
H_D#17 W10 H20 H_A#21 BG16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# 14

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SM_CS#_2 DDR_CS3_DIMMB#
Y8 H_D#_18 H_A#_22 L19 H10 RSVD20 SM_CS#_3 BE13 DDR_CS3_DIMMB# 14
H_D#19 V4 D17 H_A#23 B51

MUXING
H_D#_19 H_A#_23 RSVD21

1
2.2U_0603_106K

0.01U_0402_25V7K~N
H_D#20 M3 M17 H_A#24 BJ20 BH18 M_ODT0 M_ODT0 13
H_D#21 H_D#_20 H_A#_24 H_A#25 R333 RSVD22 SM_ODT_0 M_ODT1
J1 H_D#_21 H_A#_25 N16 1 1 BK22 RSVD23 SM_ODT_1 BJ15 M_ODT1 13
H_D#22 H_A#26 M_ODT2 +1.8V
N5 H_D#_22 H_A#_26 J19 BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 14
H_D#23 N3 B18 H_A#27 1K_0402_1% BH20 BE16 M_ODT3 M_ODT3 14
H_D#_23 H_A#_27 RSVD25 SM_ODT_3

C403

C404
H_D#24 W6 E19 H_A#28 BK18

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD26 SMRCOMP R328
W9 H_D#_25 H_A#_29 B17 BJ18 RSVD27 SM_RCOMP BL15 2 1 20_0402_1%
H_D#26 N2 B15 H_A#30 BF23 BK14 SMRCOMP# 2 1
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD28 SM_RCOMP# R329 20_0402_1%
Y7 H_D#_27 H_A#_31 E17 BG23 RSVD29
H_D#28 Y9 C18 H_A#32 BC23 BK31 SMRCOMP_VOH
H_D#29 H_D#_28 H_A#_32 H_A#33 RSVD30 SM_RCOMP_VOH SMRCOMP_VOL
P4 A19 BD24 BL31

DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 H_D#_30 H_A#_34 B19 13 DDR_A_MA14 BJ29 RSVD32
H_D#31 N1 N19 H_A#35 BE24 AR49
H_D#_31 H_A#_35 14 DDR_B_MA14 RSVD33 SM_VREF_0
H_D#32 AD12 BH39 AW4 +DDR_MCH_REF
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 H_D#_33 H_ADS# G12 H_ADS# 4 AW20 RSVD35
H_D#34 AD9
HOST H17 H_ADSTB#0 +3VS BK20
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 RSVD36
H_D#35 AC9 G20 H_ADSTB#1 R82 C48
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4 RSVD37
H_D#36 AC7 C8 H_BNR# PM_EXTTS#0 2 1 D47 B42 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# 4 RSVD38 DPLL_REF_CLK CLK_MCH_DREFCLK 16
H_D#37 AC14 E8 H_BPRI# B44 C42 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# 4 RSVD39 DPLL_REF_CLK# CLK_MCH_DREFCLK# 16
H_D#38 AD11 F12 H_BR0# 10K_0402_5% C44 H48 MCH_SSCDREFCLK
H_D#_38 H_BREQ# H_BR0# 4 RSVD40 DPLL_REF_SSCLK MCH_SSCDREFCLK 16
H_D#39 AC11 D6 H_DEFER# A35 H47 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# 4 RSVD41 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 16
H_D#40 AB2 C10 H_DBSY# R83 B37
H_D#_40 H_DBSY# H_DBSY# 4 RSVD42
H_D#41 AD7 AM5 CLK_MCH_BCLK PM_EXTTS#1 2 1 B36 K44 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK 16 RSVD43 PEG_CLK CLK_MCH_3GPLL 16

CLK
H_D#42 AB1 AM7 CLK_MCH_BCLK# B34 K45 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16 RSVD44 PEG_CLK# CLK_MCH_3GPLL# 16
H_D#43 Y3 H8 H_DPWR# 10K_0402_5% C34
C H_D#_43 H_DPWR# H_DPWR# 5 RSVD45 C
H_D#44 AC6 K7 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AE2 E4 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AC5 C6 H_HITM# AN47 DMI_TXN0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_TXN0 19
H_D#47 AG3 G10 H_LOCK# AJ38 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_TXN1 19
H_D#48 AJ9 B7 H_TRDY# AN42 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN2 19
H_D#49 AH8 AN46 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 19
H_D#50 AJ14
H_D#51 H_D#_50 DMI_TXP0
AE9 H_D#_51 DMI_RXP_0 AM47 DMI_TXP0 19
H_D#52 AE11 MCH_CLKSEL0 P27 AJ39 DMI_TXP1
+VCCP H_D#_52 16 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 19
H_D#53 AH12 K5 H_DINV#0 MCH_CLKSEL1 N27 AN41 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 5 16 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 19
H_D#54 AJ5 L2 H_DINV#1 MCH_CLKSEL2 N24 AN45 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 5 16 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 19
H_D#55 AH5 AD13 H_DINV#2 PAD T8 C21
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AJ6 AE13 H_DINV#3 PAD T9 C23 AJ46 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_RXN0 19
54.9_0402_1%

54.9_0402_1%

H_D#57 AE7 CFG5 F23 AJ41 DMI_RXN1


H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 19
1

H_D#58 AJ7 M7 H_DSTBN#0 PAD T37 N23 AM40 DMI_RXN2


H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 CFG_6 DMI_TXN_2 DMI_RXN2 19
H_D#59 AJ2 K3 H_DSTBN#1 CFG7 G23 AM44 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 9 CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 19
R325

R326

H_D#60 AE5 AD2 H_DSTBN#2 J20

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 9 CFG8 CFG_8

CFG
H_D#61 AJ3 AH11 H_DSTBN#3 CFG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 19
H_D#62 AH2 PAD T38 R24 AJ42 DMI_RXP1
DMI_RXP1 19
2

H_D#63 H_D#_62 H_DSTBP#0 CFG_10 DMI_TXP_1 DMI_RXP2


AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 5 PAD T40 L23 CFG_11 DMI_TXP_2 AM39 DMI_RXP2 19
K2 H_DSTBP#1 CFG12 J23 AM43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 5 9 CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 19
AC2 H_DSTBP#2 CFG13 E23
H_DSTBP#_2 H_DSTBP#2 5 9 CFG13 CFG_13
H_SWNG B3 AJ10 H_DSTBP#3 PAD T10 E20
H_SWING H_DSTBP#_3 H_DSTBP#3 5 CFG_14
H_RCOMP C2 PAD T4 K23
H_RCOMP H_REQ#0 CFG16 CFG_15 R678 0_0402_5% VGA@
H_REQ#_0 M14 H_REQ#0 4 9 CFG16 M20 CFG_16
H_SCOMP W1 E13 H_REQ#1 PAD T5 M24 CLK_MCH_DREFCLK 2 1
H_REQ#1 4

GRAPHICS VID
H_SCOMP# H_SCOMP H_REQ#_1 H_REQ#2 CFG_17 R679 0_0402_5% VGA@
W2 H_SCOMP# H_REQ#_2 A11 H_REQ#2 4 PAD T39 L32 CFG_18
H13 H_REQ#3 CFG19 N33 CLK_MCH_DREFCLK# 2 1
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
4 H_RESET# H_RESET# B6 B12 H_REQ#4 CFG20 L35 R680 0_0402_5% VGA@
H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20
5 H_CPUSLP# H_CPUSLP# E5 MCH_SSCDREFCLK 2 1
H_CPUSLP# H_RS#0 R681 0_0402_5% VGA@
H_RS#_0 E12 H_RS#0 4
D7 H_RS#1 H_RS#1 4 E35 MCH_SSCDREFCLK# 2 1
B H_RS#_1 GFX_VID_0 T12 PAD B
D8 H_RS#2 H_RS#2 4 19 PM_BMBUSY# PM_BMBUSY# G41 A39
H_RS#_2 PM_BM_BUSY# GFX_VID_1 T42 PAD
B9 H_DPRSTP# L39 C38
H_AVREF 5,18,49 H_DPRSTP# PM_DPRSTP# GFX_VID_2 T41 PAD
H_VREF A9 PM_EXTTS#0 L36 B39
H_DVREF 13 PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3 T16 PAD

PM
PM_EXTTS#1 J36 E36
14 PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN T11 PAD
CRESTLINE_1p0 UMA@ PM_POK_R AW49
R56 0_0402_5% PLT_RST#_R PWROK +1.25VM_AXD
layout note: AV20 RSTIN#
4,18 H_THERMTRIP# 2 1 THERMTRIP# N20
DPRSLPVR THERMTRIP#
19,49 DPRSLPVR G36 DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
AM49 CL_CLK0 R100
CL_CLK CL_CLK0 19
AK50 CL_DATA0
CL_DATA CL_DATA0 19
Layout Note: BJ51 AT43 M_PWROK 1K_0402_1%
NC_1 CL_PWROK M_PWROK 19
CL_RST#

ME
Layout Note: +DDR_MCH_REF BK51 AN49 CL_RST# 19

2
+1.8V NC_2 CL_RST# CL_VREF CL_VREF
BK50 AM50
H_RCOMP / H_VREF / H_SWNG trace width and BL50
NC_3 CL_VREF
NC_4

1
trace width and spacing is 10/20 spacing is 20/20. BL49 NC_5 1
1

BL3 C181 R99


R42 NC_6 0.1U_0402_16V4Z~N 392_0402_1%
BL2 NC_7

NC
1K_0402_1% BK1 12 mil
NC_8 2
BJ1 H35

2
+VCCP NC_9 SDVO_CTRL_CLK
E1 K36

MISC
2

+VCCP +DDR_MCH_REF NC_10 SDVO_CTRL_DATA CLKMCHREQ#


A5 NC_11 CLK_REQ# G39 CLKMCHREQ# 16
0.1U_0402_16V4Z~N

C51 G40 MCH_ICH_SYNC#


NC_12 ICH_SYNC# MCH_ICH_SYNC# 19
1
221_0603_1%
1K_0402_1%

B50 NC_13
1

1 R43 A50 NC_14


R322

1K_0402_1% A49 A37


NC_15 TEST_1
R45

C66

BK2 NC_16 TEST_2 R32


2

1
0.1U_0402_16V4Z~N 2 CRESTLINE_1p0 UMA@
2

H_VREF H_RCOMP H_SWNG 2 1 R77 R84


19,29,49 VGATE
@ R101 0_0402_5%
24.9_0402_1%

0.1U_0402_16V4Z~N

close to NB 20K_0402_5% 0_0402_5%


1

1
2K_0402_1%

100_0402_1%

A PM_POK_R A
1 1 19,29 PM_PWROK 2 1

2
R102 0_0402_5%
R46

C391

R324

R323

C386

PLT_RST# 1 2 PLT_RST#_R
2 2 17,19,22,24,28,29,34 PLT_RST#
R111 100_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


within 100 mils from NB Near B3 pin Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 7 of 49
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U4D U4E
DDR_A_D0 AR43 BB19 DDR_A_BS0 DDR_B_D0 AP49 AY17 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 13 SB_DQ_0 SB_BS_0 DDR_B_BS#0 14
DDR_A_D1 AW44 BK19 DDR_A_BS1 DDR_B_D1 AR51 BG18 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 13 SB_DQ_1 SB_BS_1 DDR_B_BS#1 14
DDR_A_D2 BA45 BF29 DDR_A_BS2 DDR_B_D2 AW50 BG36 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 13 SB_DQ_2 SB_BS_2 DDR_B_BS#2 14
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# 13 AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# 14
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] 13 SB_DQ_5 DDR_B_DM[0..7] 14
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_A_DQS[0..7] 13 DDR_B_D14 BF50
SA_DQ_14 SB_DQ_14 DDR_B_DQS[0..7] 14
DDR_A_D15 BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0

A
SA_DQ_15 SA_DQS_0 SB_DQ_15 SB_DQS_0

B
DDR_A_D16 AW43 BE48 DDR_A_DQS1 DDR_B_D16 BJ50 BD50 DDR_B_DQS1
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
DDR_A_D18 BG42 BC37 DDR_A_DQS3 DDR_B_D18 BJ43 BK39 DDR_B_DQS3
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
DDR_A_D20 BF44 BH6 DDR_A_DQS5 DDR_B_D20 BK47 BL7 DDR_B_DQS5

MEMORY
SA_DQ_20 SA_DQS_5 SB_DQ_20 SB_DQS_5

MEMORY
DDR_A_D21 BH45 BB2 DDR_A_DQS6 DDR_B_D21 BK49 BE2 DDR_B_DQS6
DDR_A_D22 SA_DQ_21 SA_DQS_6 DDR_A_DQS7 DDR_B_D22 SB_DQ_21 SB_DQS_6 DDR_B_DQS7
BG40 SA_DQ_22 SA_DQS_7 AP3 DDR_A_DQS#[0..7] 13 BK43 SB_DQ_22 SB_DQS_7 AV2 DDR_B_DQS#[0..7] 14
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
DDR_A_D25 AW40 BC41 DDR_A_DQS#2 DDR_B_D25 BL41 BL45 DDR_B_DQS#2
DDR_A_D26 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
DDR_A_D27 AW36 BA16 DDR_A_DQS#4 DDR_B_D27 BJ36 BK12 DDR_B_DQS#4
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
C DDR_A_D29 DDR_A_DQS#6 DDR_B_D29 DDR_B_DQS#6 C
AY41 SA_DQ_29 SA_DQS#_6 BC1 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
SA_DQ_30 SA_DQS#_7 DDR_A_MA[0..13] 13 SB_DQ_30 SB_DQS#_7
DDR_A_D31 AT38 DDR_B_D31 BK37 DDR_B_MA[0..13] 14
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM

DDR_A_D33 AT13 BD20 DDR_A_MA1 DDR_B_D33 BE11 BG28 DDR_B_MA1


SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1

SYSTEM
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR

DDR_A_D46 BD7 DDR_B_D46 BJ8

DDR
DDR_A_D47 SA_DQ_46 DDR_B_D47 SB_DQ_46 DDR_B_RAS#
BB9 SA_DQ_47 BJ6 SB_DQ_47 SB_RAS# AV16 DDR_B_RAS# 14
DDR_A_D48 BB5 BE18 DDR_A_RAS# DDR_B_D48 BF4 AY18 SB_RCVEN#
SA_DQ_48 SA_RAS# DDR_A_RAS# 13 SB_DQ_48 SB_RCVEN#
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 T7
DDR_A_D50 SA_DQ_49 SA_RCVEN# T6 DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# 14
DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_A_WE# 13 DDR_B_D51 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 SA_DQ_52 BK3 SB_DQ_52
DDR_A_D53 BB7 DDR_B_D53 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 SA_DQ_54 BD3 SB_DQ_54
DDR_A_D55 AR8 DDR_B_D55 BJ2
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AR9 SA_DQ_56 BA3 SB_DQ_56
DDR_A_D57 AN3 DDR_B_D57 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 SA_DQ_58 AR1 SB_DQ_58
DDR_A_D59 AN10 DDR_B_D59 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 SA_DQ_60 AY2 SB_DQ_60
B DDR_A_D61 DDR_B_D61 B
AN9 SA_DQ_61 AY3 SB_DQ_61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 8 of 49
5 4 3 2 1
5 4 3 2 1

For Crestline:2.4kohm
For Calero: 1.5Kohm

15 BIA_PWM BIA_PWM J40


U4C http://laptopblue.vn R95
24.9_0402_1% +VCCP
PEGCOMP trace width
and spacing is 20/25 mils. Strap Pin Table
GMCH_ENBKL L_BKLT_CTRL PEGCOMP
15 GMCH_ENBKL H39 L_BKLT_EN PEG_COMPI N43 1 2
+3VS R81 1 210K_0402_5% UMA@ CTRL_CLK E39 M43 010 = FSB 800MHz
R80 L_CTRL_CLK PEG_COMPO
1 210K_0402_5% UMA@ CTRL_DATA E40
L_CTRL_DATA PEG_NRX_GTX_N[0..15] 34
GMCH_EDID_CLK_LCD C37 CFG[2:0] FSB Freq select 011 = FSB 667MHz
15 GMCH_EDID_CLK_LCD L_DDC_CLK
GMCH_EDID_DAT_LCD D35 J51 PEG_NRX_GTX_N0
15 GMCH_EDID_DAT_LCD L_DDC_DATA PEG_RX#_0
15 GMCH_LVDDEN GMCH_LVDDEN K40 L51 PEG_NRX_GTX_N1 Others = Reserved
L_VDD_EN PEG_RX#_1 PEG_NRX_GTX_N2
PEG_RX#_2 N47
2 1 L41 T45 PEG_NRX_GTX_N3
R94 2.4K_0402_1% LVDS_IBG PEG_RX#_3 PEG_NRX_GTX_N4
D
L43 LVDS_VBG PEG_RX#_4 T50 0 = DMI x 2 D
N41 U40 PEG_NRX_GTX_N5 CFG5 (DMI select)
LVDS_VREFH PEG_RX#_5 PEG_NRX_GTX_N6
N40 Y44 1 = DMI x 4
15 GMCH_LVDSAC-
15 GMCH_LVDSAC+
GMCH_LVDSAC-
GMCH_LVDSAC+
D46
C45
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_6
PEG_RX#_7 Y40
AB51
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8
*
LVDSA_CLK PEG_RX#_8 PEG_NRX_GTX_N9
D44 LVDSB_CLK# PEG_RX#_9 W49 CFG6 Reserved
E42 AD44 PEG_NRX_GTX_N10
LVDSB_CLK PEG_RX#_10

LVDS
AD40 PEG_NRX_GTX_N11
GMCH_LVDSA0- PEG_RX#_11 PEG_NRX_GTX_N12
15 GMCH_LVDSA0- G51 LVDSA_DATA#_0 PEG_RX#_12 AG46 CFG7 (CPU Strap) 0 = Reserved
15 GMCH_LVDSA1- GMCH_LVDSA1- E51 AH49 PEG_NRX_GTX_N13
GMCH_LVDSA2- LVDSA_DATA#_1 PEG_RX#_13 PEG_NRX_GTX_N14
F49 AG45 1 = Mobile CPU
15 GMCH_LVDSA2- LVDSA_DATA#_2 PEG_RX#_14
AG41 PEG_NRX_GTX_N15 *

GRAPHICS
PEG_RX#_15 PEG_NRX_GTX_P[0..15] 34

15 GMCH_LVDSA0+ GMCH_LVDSA0+ G50 J50 PEG_NRX_GTX_P0 0 = Normal mode


GMCH_LVDSA1+ LVDSA_DATA_0 PEG_RX_0 PEG_NRX_GTX_P1
15 GMCH_LVDSA1+ E50 LVDSA_DATA_1 PEG_RX_1 L50 CFG8 (Low power PCIE)
GMCH_LVDSA2+ F48 M47 PEG_NRX_GTX_P2 1 = Low Power mode
15 GMCH_LVDSA2+ LVDSA_DATA_2 PEG_RX_2
PEG_RX_3 U44
T49
PEG_NRX_GTX_P3
PEG_NRX_GTX_P4
*
PEG_RX_4 PEG_NRX_GTX_P5
G44 LVDSB_DATA#_0 PEG_RX_5 T41 CFG9 0 = Reverse Lane
B47 W45 PEG_NRX_GTX_P6
LVDSB_DATA#_1 PEG_RX_6 PEG_NRX_GTX_P7
B45 W41 (PCIE Graphics Lane Reversal) 1 = Normal Operation
LVDSB_DATA#_2 PEG_RX_7
PEG_RX_8 AB50
Y48
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9
*
PEG_RX_9 PEG_NRX_GTX_P10
E44 LVDSB_DATA_0 PEG_RX_10 AC45
A47 AC41 PEG_NRX_GTX_P11 CFG[11:10] Reserved
LVDSB_DATA_1 PEG_RX_11 PEG_NRX_GTX_P12
A45 LVDSB_DATA_2 PEG_RX_12 AH47

PCI-EXPRESS
AG49 PEG_NRX_GTX_P13
PEG_RX_13
AH45 PEG_NRX_GTX_P14 00 = Reserved
PEG_RX_14 PEG_NTX_GRX_N[0..15] 34
AG42 PEG_NRX_GTX_P15 CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
PEG_RX_15
10 = All Z Mode Enabled
1 2 E27 N45 PEG_TXN0 C568 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N0 11 = Normal Operation(Default)
75_0402_1%
1
75_0402_1%
1
2 R65
2 R67
G27
K27
TVA_DAC
TVB_DAC
PEG_TX#_0
PEG_TX#_1 U39
U47
PEG_TXN1
PEG_TXN2
C537
C538
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
*
TVC_DAC PEG_TX#_2

TV
C 75_0402_1% R68 PEG_TXN3 C539 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N3 C
PEG_TX#_3 N51 1 2 CFG[15:14] Reserved
F27 R50 PEG_TXN4 C540 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N4
TVA_RTN PEG_TX#_4 PEG_TXN5 C541 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N5
J27 TVB_RTN PEG_TX#_5 T42 1 2
L27 Y43 PEG_TXN6 C542 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N6 CFG16 (FSB Dynamic ODT) 0 = Disabled
TVC_RTN PEG_TX#_6 PEG_TXN7 C543 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N7
PEG_TX#_7 W46 1 2
M35 W38 PEG_TXN8 C544 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N8 1 = Enabled
P33
TV_DCONSEL_0
TV_DCONSEL_1
PEG_TX#_8
PEG_TX#_9 AD39
AC46
PEG_TXN9
PEG_TXN10
C545
C546
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
*
PEG_TX#_10 PEG_TXN11 C547 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N11
PEG_TX#_11 AC49 1 2 CFG[18:17] Reserved
15 CRT_B CRT_B AC42 PEG_TXN12 C548 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N12
CRT_G PEG_TX#_12 PEG_TXN13 C549 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N13
15 CRT_G PEG_TX#_13 AH39 1 2
CRT_R AE49 PEG_TXN14 C550 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N14 0 = No SDVO Device Present
15 CRT_R PEG_TX#_14
PEG_TX#_15 AH44 PEG_TXN15 C551 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N15
PEG_NTX_GRX_P[0..15] 34
SDVO_CTRLDATA *
2

2
150_0402_1%

150_0402_1%

150_0402_1%

1 = SDVO Device Present


H32 M45 PEG_TXP0 C552 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P0
CRT_BLUE PEG_TX_0
UMA@

UMA@

UMA@
R74

R76

R75

G32 T38 PEG_TXP1 C553 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P1


CRT_BLUE# PEG_TX_1 PEG_TXP2 C554 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P2
K29 T46 1 2 0 = Normal Operation
J29
CRT_GREEN PEG_TX_2
N50 PEG_TXP3 C555 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P3 CFG19 (DMI Lane Reversal) (Lane number in Order) *
1

CRT_GREEN# PEG_TX_3 PEG_TXP4 C556 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P4


F29 CRT_RED PEG_TX_4 R51 1 2
VGA

E29 U43 PEG_TXP5 C557 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P5 1 = Reverse Lane


CRT_RED# PEG_TX_5 PEG_TXP6 C558 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P6
PEG_TX_6 W42 1 2
Y47 PEG_TXP7 C559 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P7
3VDDCCL PEG_TX_7 PEG_TXP8 C560 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P8
K33 Y39 1 2 0 = Only PCIE or SDVO is operational.
15
15
15
3VDDCCL
3VDDCDA
CRT_HSYNC
3VDDCDA
CRT_HSYNC
G35
F33
CRT_DDC_CLK
CRT_DDC_DATA
PEG_TX_8
PEG_TX_9 AC38
AD47
PEG_TXP9
PEG_TXP10
C561
C562
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_P9
PEG_NTX_GRX_P10
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
CRT_HSYNC PEG_TX_10 PEG_TXP11 C563 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P11
C32 CRT_TVO_IREF PEG_TX_11 AC50 1 2
15 CRT_VSYNC CRT_VSYNC E33 AD43 PEG_TXP12 C564 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P12
CRT_VSYNC PEG_TX_12 PEG_TXP13 C565 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P13
PEG_TX_13 AG39 1 2
1

AE50 PEG_TXP14 C566 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P14 R66 1 2 @ 4.02K_0402_1%


PEG_TX_14 7 CFG5
2

1.3K_0402_1%

AH43 PEG_TXP15 C567 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P15


R334 PEG_TX_15
0_0402_5% 0_0402_5% R58
7 CFG7 1 2 @ 4.02K_0402_1%
B R676 R675 CRESTLINE_1p0 B
2

VGA@ VGA@
1

R59 1 2 @ 4.02K_0402_1%
7 CFG8

R55 1 2 @ 4.02K_0402_1%
7 CFG9
For Crestline:1.3kohm
For Calero: 255ohm
R57 1 2 @ 4.02K_0402_1%
7 CFG12

R63 1 2 @ 4.02K_0402_1%
+3VS 7 CFG13

CTRL_CLK R70 1 2 @ 4.02K_0402_1%


7 CFG16
R483 UMA@
1 2 GMCH_EDID_CLK_LCD
CTRL_DATA R74 R76 R75
2.2K_0402_5% CFG[17:3] have internal pull up
R484 UMA@ CFG[19:18] have internal pull down
2

1 2 GMCH_EDID_DAT_LCD

2.2K_0402_5% 0_0402_5% 0_0402_5% +3VS


0_0402_5% 0_0402_5% 0_0402_5%
2

R684 R683 VGA@ VGA@ VGA@


VGA@ VGA@
1

0_0402_5% 0_0402_5% R72


7 CFG19 1 2 @ 4.02K_0402_1%
R682 R677
VGA@ VGA@
1

R73 1 2 @ 4.02K_0402_1%
7 CFG20

A A

Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 9 of 49
5 4 3 2 1
5 4 3 2 1

+3VS VCCSYNC

http://laptopblue.vn
+3VS_DAC_BG +3VS R92 UMA@
BLM18PG181SN1D_0603 2 1
2 1 0_0603_5% 1
UMA@

UMA@

UMA@
L10 UMA@
+1.25VS_DPLLB +1.25VS
0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N

4.7U_0805_10V4Z~N
C141 UMA@ +V1.25VS_AXF
0.1U_0402_16V4Z~N +VCCP UMA@
1 1 1 2
1 2 +1.25VS 1 2
C406

C405

C408

0.1U_0402_16V4Z~N

10U_0805_10V4Z~N
U4H L14

22U_0805_6.3VAM

1U_0603_10V4Z
10U_FLC-453232-100K_0.25A_10% R330
2 2 2 330U_V_2.5VM 0_0603_5%
J32 VCCSYNC VTT_1 U13 1 1 1 1

4.7U_0805_10V4Z~N

C174

C394

C397
VTT_2 U12

C178
+3VS_DAC_CRT A33 U11 1 1 UMA@ UMA@
VCCA_CRT_DAC_1 VTT_3
B33 VCCA_CRT_DAC_2 VTT_4 U9
+ 2 2 2 2

C384
U8 C370
VTT_5

CRT
VTT_6 U7
D A30 U5 2 D
+3VS_DAC_CRT +3VS +3VS_DAC_BG VCCA_DAC_BG VTT_7 2
VTT_8 U3
BLM18PG181SN1D_0603 B32 U2
VSSA_DAC_BG VTT_9
2 1 VTT_10 U1
0.022U_0402_16V7K~N

UMA@

UMA@

L11 UMA@ T13


VTT_11 +1.25VS_DMI +1.8V_SM_CK
0.1U_0402_16V4Z~N

VTT
+1.25VS_DPLLA B49 T11 +1.25VS +1.8V
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z~N

2.2U_0805_16V4Z
1 1 T10 R327
VTT_13
+1.25VS_DPLLB H49 VCCA_DPLLB VTT_14 T9 1 1 1 1 2 1 2
C407

C411

10U_0603_6.3V6M
0_0805_5%

0.1U_0402_16V4Z~N
VTT_15 T7

0.1U_0402_16V4Z~N

22U_0805_6.3V4Z
PLL

C56
C383

C373
+1.25VM_HPLL AL2 T6 R103 1 1
2 2 VCCA_HPLL VTT_16 0_0603_5%
VTT_17 T5 1
2 2 2

C396

C395

C399
+1.25VM_MPLL AM2 VCCA_MPLL VTT_18 T3 1

C180
VTT_19 T2
2 2
VTT_20 R3
2

A LVDS
+1.8V_TXLVDS A41 VCCA_LVDS VTT_21 R2
R1 2
1 VTT_22 +1.25VM_AXD
C413 1000P_0402_50V7K~N B41
VSSA_LVDS R60
+3VS_PEG_BG
UMA@ VCC_AXD_1 AT23 1 2 +1.25VS
R97 2 0_0805_5%
VCC_AXD_2 AU28

1U_0603_10V4Z

10U_0805_10V4Z~N
+3VS 1 2 K50 VCCA_PEG_BG VCC_AXD_3 AU24 1 1
+1.25VS_PEGPLL

C87

C88
AXD
0_0805_5% AT29 +1.25VS
VCC_AXD_4 L12 +1.5VS_TVDAC +1.5VS
1 K49 VSSA_PEG_BG VCC_AXD_5 AT25

A PEG
AT30 BLM18PG121SN1D_0603 R64
C175 VCC_AXD_6 2 2
2 1 1 2
0.1U_0402_16V4Z~N 20 mils 0_0805_5%

0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N
+1.25VS_PEGPLL U51 VCCA_PEG_PLL VCC_AXD_NCTF AR29
2

0.1U_0402_16V4Z~N

10U_0805_10V4Z~N
1 1 1 1

C176

C179
AW18 VCCA_SM_1 VCC_AXF_1 B23 +V1.25VS_AXF

C115

C114
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2

AXF
AU19 VCCA_SM_3 VCC_AXF_3 A21
2 2 2 2
+1.25VM_A_SM AU18 VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25VS_DMI
R50 0317 change value

A SM
C +1.25VS 1 2 AT22 VCCA_SM_7 C
0_0805_5% 1 AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1

SM CK
1 1 1 AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C68 + AT18 BJ24
150U_B2_6.3VM_R45M C82 C83 C72 VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
22U_0805_6.3V4Z 4.7U_0805_6.3V6K AR17 +1.25VM_HPLL
2 2 2 2 VCCA_SM_NCTF_1 +1.25VS_DPLLA L29 +1.25VS
AR16 VCCA_SM_NCTF_2 L13
1U_0603_10V4Z UMA@
R71 +1.25VM_A_SM_CK
VCC_TX_LVDS A43 +1.8V_TXLVDS 1 2 +1.25VS 2 1

A CK
2 1 BC29 MBK2012121YZF_0805

10U_0805_10V4Z~N
0_0603_5% VCCA_SM_CK_1 +3VS_HV 10U_FLC-453232-100K_0.25A_10%
BB29
22U_0805_6.3V4Z

0.1U_0402_16V4Z~N

1
1U_0402_6.3V4Z

VCCA_SM_CK_2
1U_0603_10V4Z
@

UMA@ 1 UMA@ UMA@


@ C122

VCC_HV_1 C40 1 1 1

C173

C182
C25 B40 + C380 C381
1 1 1 1 +3VS_TVDACA VCCA_TVA_DAC_1 VCC_HV_2
C103

C104

C123

C191

220U_D2_4VY_R15M
HV
B25 VCCA_TVA_DAC_2

0.1U_0402_16V4Z~N
+3VS_TVDACB C27 0.1U_0402_16V4Z~N 10U_0805_10V4Z~N
VCCA_TVB_DAC_1 2 2 2 2 2
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51 +VCC_PEG 1
2 2 2 2

C410
TV

+3VS_TVDACC B28 VCCA_TVC_DAC_1 VCC_PEG_2 W50

PEG
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
V49 0.1U_0402_16V4Z~N
VCC_PEG_4 2
2VGA@ R6741 0_0402_5% VCC_PEG_5 V50
D TV/CRT

2 1 M32 VCCD_CRT
+1.5VS_TVDAC R673 0_0402_5% UMA@ L29
VCCD_TVDAC
VCC_RXR_DMI_1 AH50 +VCCP +1.25VM_MPLL
DMI

+1.5VS_QDAC N28 VCCD_QDAC VCC_RXR_DMI_2 AH51


20mils +VCC_PEG L9 +1.25VS
+1.25VM_HPLL AN2 VCCD_HPLL
VTTLF1 A7 2 1
VTTLF

+1.25VS_PEGPLL U48 F2 MBK2012121YZF_0805


VCCD_PEG_PLL VTTLF2

10U_0805_10V4Z~N
VTTLF3 AH1 1
J41 VCCD_LVDS_1 0.47U_0603_10V7K 1 1 1

0.47U_0603_10V7K

0.47U_0603_10V7K

C416
LVDS

H42 + C63 C62


+1.8V_LVDS VCCD_LVDS_2

C417

220U_D2_4VY_R15M
1 1 1
C382

C385

C65
Take off 0ohm 0805 0.1U_0402_16V4Z~N 10U_0805_10V4Z~N
2 2 because Layout 2 2
+3VS_TVDACA +3VS CRESTLINE_1p0 UMA@
B
R54 2 2 2 B
2 1
0.022U_0402_16V7K~N

UMA@

0_0603_5%
UMA@
0.1U_0402_16V4Z~N

UMA@
1 1
C401

C402

+VCCP_D
2 2

D7 R79 R93
+VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
CH751H-40PT_SOD323-2
+3VS
+1.5VS_QDAC +1.5VS
+3VS_TVDACB +3VS R69
R62
2 1
0.022U_0402_16V7K~N

2 1 0_0603_5%
0.022U_0402_16V7K~N

UMA@

0.1U_0402_16V4Z~N

0_0603_5% UMA@
+1.8V_TXLVDS
UMA@
0.1U_0402_16V4Z~N

UMA@ 1 1 40 mils C406 C402 C95 C186 C413 U4 VGA@


1 1 R349
C97

C98
C116

C96

1000P_0402_50V7K~N 2 1 +1.8V
2 2
UMA@

0_0603_5% UMA@
2 2
UMA@

1
1 0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% 0_0402_5% CRESTLINE_1p0
C414 + VGA@ VGA@ VGA@ VGA@ VGA@
C418

220U_D2_4VY_R15M

UMA@ UMA@
2 2 C407 C96 C98 C174 C141 C173

+3VS_TVDACC +3VS +1.8V_LVDS


A R53 A
R109
2 1
0.022U_0402_16V7K~N

UMA@

UMA@ C187

0_0603_5% 2 1 +1.8V 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%


UMA@
0.1U_0402_16V4Z~N

10U_0805_10V4Z~N

UMA@ 0_0603_5% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@


1U_0603_10V4Z

1 1 1 1 UMA@
C186
C113

C95

UMA@

2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 10 of 49
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn +VCCP
U4G +VCCP

AT35 VCC_1
AT34 T17 370mil
VCC_2 VCC_AXG_NCTF_1
AH28 VCC_3 VCC_AXG_NCTF_2 T18
AC32 T19 0.1U_0402_16V4Z~N 0.47U_0603_10V7K
VCC_5 VCC_AXG_NCTF_3
AC31 VCC_4 VCC_AXG_NCTF_4 T21
AK32 VCC_6 VCC_AXG_NCTF_5 T22 1 1

1
AJ31 T23 C99 C86 C101
+VCCP VCC_7 VCC_AXG_NCTF_6
AJ28 VCC_8 VCC_AXG_NCTF_7 T25
D U4F UMA@ UMA@ UMA@ D
AH32 U15

2
VCC_9 VCC_AXG_NCTF_8 2 2

VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 AF32 U19 0.22U_0402_10V4Z~N
VCC_NCTF_2 VCC_12 VCC_AXG_NCTF_11
AB37 VCC_NCTF_3 VCC_AXG_NCTF_12 U20
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 T37 R78 U23
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 1 2 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 U28 0_0603_5% V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 VCC_NCTF_8 VSS_NCTF_5 V31 VCC_AXG_NCTF_17 V17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 VCC_AXG_NCTF_19 V20
22U_0805_6.3V4Z

0.22U_0402_10V4Z~N

0.22U_0402_10V4Z~N

0.1U_0402_16V4Z~N

AH33 VCC_NCTF_11 VSS_NCTF_8 AB17 VCC_AXG_NCTF_20 V21

VSS NCTF
1 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35 VCC_AXG_NCTF_21 V23
1 1 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19 VCC_AXG_NCTF_22 V24
1

1
C118

C143

C119

C120

+ AH37 AD37 Y15


VCC_NCTF_14 VSS_NCTF_11
POWER VCC_AXG_NCTF_23
C374

220U_D2_4VY_R15M

AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17 VCC_AXG_NCTF_24 Y16


AJ35 AF35 +1.8V Y17
2

2 2 2 VCC_NCTF_16 VSS_NCTF_13 VCC_AXG_NCTF_25


AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19
AK35 AM17 160mil AU33 Y20
VCC_NCTF_18 VSS_NCTF_15 VCC_SM_2 VCC_AXG_NCTF_27
AK36 VCC_NCTF_19 VSS_NCTF_16 AM24 AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21
AK37 VCC_NCTF_20 VSS_NCTF_17 AP26 AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23

0.01U_0402_16V7K~N
330U_V_2.5VM
AD33 VCC_NCTF_21 VSS_NCTF_18 AP28 AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24

22U_0805_6.3V4Z

22U_0805_6.3V4Z
AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15 1 AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26

VCC NCTF
AM35 VCC_NCTF_23 VSS_NCTF_20 AR19 1 1 2 AY35 VCC_SM_7 VCC_AXG_NCTF_32 Y28

C165

C147

C164
AL33 AR28 C148 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 VCC_SM_8 VCC_AXG_NCTF_33
AL35 VCC_NCTF_25 BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16
AA33 VCC_NCTF_26 BA35 VCC_SM_10 VCC_AXG_NCTF_35 AA17
2 2 2 1
AA35 VCC_NCTF_27 BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19
AP35 VCC_NCTF_29 BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16
AP36 VCC_NCTF_30 BC35 VCC_SM_14 VCC_AXG_NCTF_39 AC17

VCC SM
C C
AR35 VCC_NCTF_31 BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19
AR36 VCC_NCTF_32 BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15
Y32 VCC_NCTF_33 BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16
Y33 BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43

VCC GFX NCTF


Y35 VCC_NCTF_35 BE35 VCC_SM_19 VCC_AXG_NCTF_44 AF16
Y36 VCC_NCTF_36 BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19
Y37 VCC_NCTF_37 VSS_SCB1 A3 BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15
T30 VCC_NCTF_38 VSS_SCB2 B2 BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16
VSS SCB
T34 VCC_NCTF_39 VSS_SCB3 C1 BG33 VCC_SM_23 VCC_AXG_NCTF_48 AH17
T35 VCC_NCTF_40 VSS_SCB4 BL1 BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19
U29 VCC_NCTF_41 VSS_SCB5 BL51 BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16
U31 VCC_NCTF_42 VSS_SCB6 A51 BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17
U32 VCC_NCTF_43 BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
U33 VCC_NCTF_44 BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16
U35 VCC_NCTF_45 BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19
U36 VCC_NCTF_46 BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16
V32 VCC_NCTF_47 BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17
V33 VCC_NCTF_48 BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19
V36 VCC_NCTF_49 BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20
V37 VCC_NCTF_50 BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23
VCC_AXM_1 AT33 +VCCP AU30 VCC_SM_36 VCC_AXG_NCTF_61 AM15
VCC_AXM_2 AT31 VCC_AXG_NCTF_62 AM16
VCC AXM

+VCCP VCC_AXM_3 AK29 VCC_AXG_NCTF_63 AM19


VCC_AXM_4 AK24 VCC_AXG_NCTF_64 AM20
10U_0805_10V4Z~N

10U_0805_10V4Z~N

VCC_AXM_5 AK23 VCC_AXG_NCTF_65 AM21


1 1 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26 R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23
C162

C121

AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23 T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15


AL28 VCC_AXM_NCTF_3 W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16
AM26 +VCCP W14 AP17
2 2 VCC_AXM_NCTF_4 VCC_AXG_4 VCC_AXG_NCTF_69
VCC AXM NCTF

AM28 VCC_AXM_NCTF_5 Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19


AM29 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N AA20 AP20
B VCC_AXM_NCTF_6 VCC_AXG_6 VCC_AXG_NCTF_71 B
AM31 VCC_AXM_NCTF_7 AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21
AM32 VCC_AXM_NCTF_8 1 AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23
AM33 VCC_AXM_NCTF_9 1 1 1 1 AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24
AP29 C78 C57 + C100 C79 C80 AB21 AR20
VCC_AXM_NCTF_10 VCC_AXG_10 VCC_AXG_NCTF_75
AP31 VCC_AXM_NCTF_11 AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21
AP32 1U_0603_10V4Z AB29 AR23
VCC_AXM_NCTF_12 2 UMA@ 2 UMA@ 2 UMA@ 2 UMA@ 2 UMA@ VCC_AXG_12 VCC_AXG_NCTF_77
AP33 VCC_AXM_NCTF_13 AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24

VCC GFX
AL29 VCC_AXM_NCTF_14 AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26
AL31 330U_V_2.5VM 10U_0805_10V4Z~N AC23 V26
VCC_AXM_NCTF_15 VCC_AXG_15 VCC_AXG_NCTF_80
AL32 VCC_AXM_NCTF_16 AC24 VCC_AXG_16 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AR32 VCC_AXM_NCTF_18 AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
0.22U_0402_10V4Z~N

0.22U_0402_10V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

AR33 VCC_AXM_NCTF_19 AC29 VCC_AXG_19


1 1 1 AD20 VCC_AXG_20
1

1
C161

C144

C142

C117

C102

AD23 VCC_AXG_21
AD24 VCC_AXG_22 VCC_SM_LF1 AW45 VCCSM_LF1
AD28 BC39 VCCSM_LF2
2

2 2 2 VCC_AXG_23 VCC_SM_LF2

VCC SM LF
CRESTLINE_1p0 UMA@ AF21 BE39 VCCSM_LF3
VCC_AXG_24 VCC_SM_LF3
AF26 VCC_AXG_25 VCC_SM_LF4 BD17 VCCSM_LF4
AA31 VCC_AXG_26 VCC_SM_LF5 BD4 VCCSM_LF5
AH20 VCC_AXG_27 VCC_SM_LF6 AW8 VCCSM_LF6
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 VCCSM_LF7

C70

C71

C67

C81

C146 0.47U_0402_6.3V6K

C145 1U_0603_10V4Z

C163 1U_0603_10V4Z
AH23 VCC_AXG_29 1 1 1 1 1 1 1
AH24 VCC_AXG_30
AH26 VCC_AXG_31

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.22U_0603_10V7K~N

0.22U_0603_10V7K~N
AD31 VCC_AXG_32 2 2 2 2 2 2 2
AJ20 VCC_AXG_33
AN14 VCC_AXG_34

A A

CRESTLINE_1p0 UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 11 of 49
5 4 3 2 1
5 4 3 2 1

U4I
http://laptopblue.vn
A13 VSS_1 VSS_100 AW24
A15 VSS_2 VSS_101 AW29
A17 VSS_3 VSS_102 AW32
A24 VSS_4 VSS_103 AW5
AA21 VSS_5 VSS_104 AW7
AA24 VSS_6 VSS_105 AY10
AA29 VSS_7 VSS_106 AY24
AB20 AY37 U4J
D VSS_8 VSS_107 D
AB23 VSS_9 VSS_108 AY42 C46 VSS_199 VSS_287 W11
AB26 VSS_10 VSS_109 AY43 C50 VSS_200 VSS_288 W39
AB28 VSS_11 VSS_110 AY45 C7 VSS_201 VSS_289 W43
AB31 VSS_12 VSS_111 AY47 D13 VSS_202 VSS_290 W47
AC10 VSS_13 VSS_112 AY50 D24 VSS_203 VSS_291 W5
AC13 VSS_14 VSS_113 B10 D3 VSS_204 VSS_292 W7
AC3 VSS_15 VSS_114 B20 D32 VSS_205 VSS_293 Y13
AC39 VSS_16 VSS_115 B24 D39 VSS_206 VSS_294 Y2
AC43 VSS_17 VSS_116 B29 D45 VSS_207 VSS_295 Y41
AC47 VSS_18 VSS_117 B30 D49 VSS_208 VSS_296 Y45
AD1 VSS_19 VSS_118 B35 E10 VSS_209 VSS_297 Y49
AD21 VSS_20 VSS_119 B38 E16 VSS_210 VSS_298 Y5
AD26 VSS_21 VSS_120 B43 E24 VSS_211 VSS_299 Y50
AD29 VSS_22 VSS_121 B46 E28 VSS_212 VSS_300 Y11
AD3 VSS_23 VSS_122 B5 E32 VSS_213 VSS_301 P29
AD41 VSS_24 VSS_123 B8 E47 VSS_214 VSS_302 T29
AD45 VSS_25 VSS_124 BA1 F19 VSS_215 VSS_303 T31
AD49 VSS_26 VSS_125 BA17 F36 VSS_216 VSS_304 T33
AD5 VSS_27 VSS_126 BA18 F4 VSS_217 VSS_305 R28
AD50 VSS_28 VSS_127 BA2 F40 VSS_218
AD8 VSS_29 VSS_128 BA24 F50 VSS_219
AE10 VSS_30 VSS_129 BB12 G1 VSS_220
AE14 VSS_31 VSS_130 BB25 G13 VSS_221 VSS_306 AA32
AE6 VSS_32 VSS_131 BB40 G16 VSS_222 VSS_307 AB32
AF20 BB44 G19 AD32
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G24
G28
VSS_223
VSS_224
VSS_225
VSS_308
VSS_309
VSS_310
AF28
AF29
AF31 VSS_36 VSS_135 BC16 G29 VSS_226 VSS_311 AT27
AG2 VSS_37 VSS_136 BC24 G33 VSS_227 VSS_312 AV25
AG38 VSS_38 VSS_137 BC25 G42 VSS_228 VSS_313 H50
AG43 VSS_39 VSS_138 BC36 G45 VSS_229
AG47 VSS_40 VSS_139 BC40 G48 VSS_230
C C
AG50 VSS_41 VSS_140 BC51 G8 VSS_231
AH3 VSS_42 VSS_141 BD13 H24 VSS_232
AH40 VSS_43 VSS_142 BD2 H28 VSS_233
AH41 VSS_44 VSS_143 BD28 H4 VSS_234
AH7 VSS_45 VSS_144 BD45 H45 VSS_235
AH9 VSS_46 VSS_145 BD48 J11 VSS_236
AJ11 VSS_47 VSS_146 BD5 J16 VSS_237
AJ13 VSS_48 VSS_147 BE1 J2 VSS_238
AJ21 VSS_49 VSS_148 BE19 J24 VSS_239
AJ24 VSS_50 VSS_149 BE23 J28 VSS_240
AJ29 BE30 J33
AJ32
AJ43
VSS_51
VSS_52
VSS_53
VSS_150
VSS_151
VSS_152
BE42
BE51
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ45 VSS_54 VSS_153 BE8
AJ49 VSS_55 VSS_154 BF12 K12 VSS_245
AK20 VSS_56 VSS_155 BF16 K47 VSS_246
AK21 VSS_57 VSS_156 BF36 K8 VSS_247
AK26 VSS_58 VSS_157 BG19 L1 VSS_248
AK28 VSS_59 VSS_158 BG2 L17 VSS_249
AK31 VSS_60 VSS_159 BG24 L20 VSS_250
AK51 VSS_61 VSS_160 BG29 L24 VSS_251
AL1 VSS_62 VSS_161 BG39 L28 VSS_252
AM11 VSS_63 VSS_162 BG48 L3 VSS_253
AM13 VSS_64 VSS_163 BG5 L33 VSS_254
AM3 VSS_65 VSS_164 BG51 L49 VSS_255
AM4 VSS_66 VSS_165 BH17 M28 VSS_256
AM41 VSS_67 VSS_166 BH30 M42 VSS_257
AM45 VSS_68 VSS_167 BH44 M46 VSS_258
AN1 VSS_69 VSS_168 BH46 M49 VSS_259
AN38 VSS_70 VSS_169 BH8 M5 VSS_260
AN39 VSS_71 VSS_170 BJ11 M50 VSS_261
AN43 VSS_72 VSS_171 BJ13 M9 VSS_262
B B
AN5 VSS_73 VSS_172 BJ38 N11 VSS_263
AN7 VSS_74 VSS_173 BJ4 N14 VSS_264
AP4 VSS_75 VSS_174 BJ42 N17 VSS_265
AP48 VSS_76 VSS_175 BJ46 N29 VSS_266
AP50 VSS_77 VSS_176 BK15 N32 VSS_267
AR11 VSS_78 VSS_177 BK17 N36 VSS_268
AR2 VSS_79 VSS_178 BK25 N39 VSS_269
AR39 VSS_80 VSS_179 BK29 N44 VSS_270
AR44 VSS_81 VSS_180 BK36 N49 VSS_271
AR47 VSS_82 VSS_181 BK40 N7 VSS_272
AR7 VSS_83 VSS_182 BK44 P19 VSS_273
AT10 VSS_84 VSS_183 BK6 P2 VSS_274
AT14 VSS_85 VSS_184 BK8 P23 VSS_275
AT41 VSS_86 VSS_185 BL11 P3 VSS_276
AT49 VSS_87 VSS_186 BL13 P50 VSS_277
AU1 VSS_88 VSS_187 BL19 R49 VSS_278
AU23 VSS_89 VSS_188 BL22 T39 VSS_279
AU29 VSS_90 VSS_189 BL37 T43 VSS_280
AU3 VSS_91 VSS_190 BL47 T47 VSS_281
AU36 VSS_92 VSS_191 C12 U41 VSS_282
AU49 VSS_93 VSS_192 C16 U45 VSS_283
AU51 VSS_94 VSS_193 C19 U50 VSS_284
AV39 VSS_95 VSS_194 C28 V2 VSS_285
AV48 VSS_96 VSS_195 C29 V3 VSS_286
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 C41 CRESTLINE_1p0 UMA@
VSS_99 VSS_198

CRESTLINE_1p0 UMA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 12 of 49
5 4 3 2 1
5 4 3 2 1

Close to VREF pins of SO-DIMM


8 DDR_A_DQS#[0..7]

8 DDR_A_D[0..63]
Layout Note:
+DDR_MCH_REF
http://laptopblue.vn +1.8V
+1.8V

JDIM2
+DDR_MCH_REF1

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
8 DDR_A_DM[0..7]
trace width and 3 4 DDR_A_D6 1 1
VSS DQ4

C201

C220
spacing is 20/20. DDR_A_D4 5 6 DDR_A_D0
DQ0 DQ5

1
8 DDR_A_DQS[0..7] DDR_A_D1 7 8
R143 DQ1 VSS DDR_A_DM0
9 VSS DM0 10
1K_0402_1% DDR_A_DQS#0 2 2
8 DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 16

2
+DDR_MCH_REF1 DDR_A_D2 VSS DQ7
14 +DDR_MCH_REF1 17 DQ2 VSS 18

0.1U_0402_16V4Z~N
DDR_A_D3 19 20 DDR_A_D13
DQ3 DQ12

1
D DDR_A_D12 D
21 VSS DQ13 22
1 R144 DDR_A_D8 23 24
1K_0402_1% DDR_A_D14 DQ8 VSS DDR_A_DM1
Layout Note: 25 DQ9 DM1 26

C206
27 VSS VSS 28
Place near JDIM1 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 7

2
2 DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 7
33 VSS VSS 34
close to connector DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U 2.5V Y D2
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C105

C124

C149

C166

C169

C154

C131

C130

C108

C84
+ 53 54
DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
@ DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
Layout Note: DDR_CKE0_DIMMA
77 VSS VSS 78
DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
C Place one cap close to every 2 pullup 81 82 C
VDD VDD
resistors terminated to +0.9V 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
8 DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 7
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
+0.9VS 8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_A_V DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 M_ODT1 M_ODT1 119 120


NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D32
DDR_A_D36 DQ32 DQ36 DDR_A_D33
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C106

C125

C126

C127

C150

C151

C167

C107

C128

C129

C152

C153

C168

133 134 DDR_A_D39


DDR_A_D35 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D34 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
DDR_A_D44 DQ40 DQ45
143 DQ41 VSS 144
B DDR_A_DQS#5 B
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
Layout Note: 153 DQ43 DQ47 154
Place these resistor 155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
closely JP41,all DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
trace length Max=1.5" 161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 7
165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 172
DDR_A_V

DDR_A_D54 VSS VSS DDR_A_D51


173 DQ50 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
DQ51 DQ55
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
RP14 RP22 56_0404_4P2R_5% DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
DDR_A_MA5 1 4 4 1 DDR_A_MA12 183 184
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA DDR_A_DM7 185 DM7 DQS7# 186 DDR_A_DQS#7
187 188 DDR_A_DQS7
RP13 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D58 191 192 DDR_A_D62
DDR_A_MA3 DQ59 DQ62
2 3 3 2 DDR_A_MA6 193 VSS DQ63 194 DDR_A_D63
ICH_SM_DA 195 196
14,16,19,24 ICH_SM_DA SDA VSS
RP7 56_0404_4P2R_5% RP15 56_0404_4P2R_5% ICH_SM_CLK 197 198
14,16,19,24 ICH_SM_CLK SCL SA0
DDR_A_RAS# 1 4 4 1 DDR_A_MA9 199 200
+3VS VDDSPD SA1
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_BS#2 1

1
10K_0402_5%

10K_0402_5%
1 1
RP6 56_0404_4P2R_5% RP16 56_0404_4P2R_5% C58 C59 FOX_ASOA426-M2RN-7F
R31

R32
DDR_A_BS#0 1 4 4 1 DDR_A_MA4
A DDR_A_MA10 2 3 3 2 DDR_A_MA2 0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM A A

REVERSE
2

2
RP5 56_0404_4P2R_5% RP8 56_0404_4P2R_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0
DDR_A_WE# 2 3 3 2 DDR_A_BS#1
Bottom side
RP1 56_0404_4P2R_5% RP2 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 3 4 1 M_ODT0
M_ODT1 1 4 3 2 DDR_A_MA13
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
56_0404_4P2R_5% RP23 56_0404_4P2R_5%
DDR_CKE1_DIMMA 1 2 4 1 DDR_A_MA14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM I
R96 56_0402_5% 3 2 DDR_A_MA11 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 13 of 49
5 4 3 2 1
5 4 3 2 1

Close to VREF pins of SO-DIMM

http://laptopblue.vn
8 DDR_B_DQS#[0..7]
+1.8V
8 DDR_B_D[0..63]
+DDR_MCH_REF1 0.9v
+DDR_MCH_REF1 13
8 DDR_B_DM[0..7] JDIM1

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
8 DDR_B_MA[0..13] 5 DQ0 DQ5 6

C221

C222
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18
D DDR_B_D3 DQ2 VSS DDR_B_D12 D
Layout Note: 19 DQ3 DQ12 20
DDR_B_D13
21 VSS DQ13 22
Place near JDIM2 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 7
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U 2.5V Y D2
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C112

C139

C160

C138

C177

C109

C132

C133

C155

C189
+ 47 48
DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 7
@ DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
Layout Note: DDR_B_D30
71 VSS VSS 72
DDR_B_D29
73 DQ26 DQ30 74
Place one cap close to every 2 pullup DDR_B_D31 75 76 DDR_B_D27
DQ27 DQ31
C
resistors terminated to +0.9VS DDR_CKE2_DIMMB
77 VSS VSS 78
DDR_CKE3_DIMMB C
7 DDR_CKE2_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE3_DIMMB 7
81 VDD VDD 82
83 NC NC/A15 84
DDR_B_BS#2 85 86 DDR_B_MA14
8 DDR_B_BS#2 BA2 NC/A14 DDR_B_MA14 7
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
+0.9VS A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
DDR_B_V 111 112
DDR_B_CAS# VDD VDD M_ODT2
8 DDR_B_CAS# 113 CAS# ODT0 114 M_ODT2 7
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13


7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
7 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C110

C134

C135

C156

C157

C170

C171

C111

C136

C158

C137

C172

C159

DDR_B_DQS#4 129 130 DDR_B_DM4


DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
B DDR_B_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
Layout Note: 147 DM5 DQS5 148
Place these resistor 149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
closely JP42,all DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
trace length Max=1.5" 155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 7
165 166 M_CLK_DDR#3
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#3 7
167 168
DDR_B_V

DDR_B_DQS6 DQS6# VSS DDR_B_DM6


169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP18 RP24 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_MA3 1 4 4 1 DDR_B_MA12 177 178
DDR_B_MA1 DDR_B_MA9 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP10 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_BS#0 1 4 4 1 DDR_B_MA14 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA10 DDR_B_MA11 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP12 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_MA0 1 4 4 1 DDR_B_MA5 193 194 DDR_B_D63
DDR_B_BS#1 DDR_B_MA8 ICH_SM_DA VSS DQ63
2 3 3 2 13,16,19,24 ICH_SM_DA 195 SDA VSS 196
ICH_SM_CLK 197 198 R33
13,16,19,24 ICH_SM_CLK SCL SAO
RP11 56_0404_4P2R_5% RP21 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_RAS# 1 4 4 1 DDR_B_MA7

1
10K_0402_5%
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 1 1 10K_0402_5%

R34
C61 C60 FOX_AS0A426-NARN-7F~N
A RP9 56_0404_4P2R_5% RP20 56_0404_4P2R_5% A
DDR_B_CAS#
DDR_B_WE#
1 4 4 1 DDR_B_MA4
DDR_B_MA2
0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM B
2 3 3 2
REVERSE
2

RP3
56_0404_4P2R_5% RP4 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2 3 4 1 DDR_B_MA13 Bottom side
M_ODT3 1 4 3 2 M_ODT2

56_0404_4P2R_5% RP25 Security Classification Compal Secret Data Compal Electronics, Inc.
4 1 DDR_B_BS#2 2007/1/15 2008/1/15 Title
DDR_CKE3_DIMMB 1 DDR_CKE2_DIMMB
Issued Date Deciphered Date
2 3 2
R335 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM II
56_0404_4P2R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 14 of 49
5 4 3 2 1
A B C D E

+5VS +CRT_VCC

CRT
2
VGA@
1
http://laptopblue.vn 1.1A_6VDC_FUSE
F7
1 2 2
W=40mils
D17

RB411DT146 SOT23
1

1
W=40mils

1
34 VGA_CRT_R
R613 0_0402_5%

0.1U_0402_16V4Z
C346
VGA@ C344
2 1 0.1U_0402_16V4Z
34 VGA_CRT_G 2 2 +CRT_VCC +CRT_VCC +3VS +3VS +3VS
R614 0_0402_5%
VGA@ @
34 VGA_CRT_B 2 1 原本為4.7K 原本為10K

2
R615 0_0402_5% 29 MSEN#

2K_0402_5%

2K_0402_5%
R12 R9 R14 R13 R10

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
UMA@ JCRT1
1 2 1 CRT_R_C 1 2 CRT_R_L CRT_GND 6 1
9 CRT_R
R619 0_0402_5% L2 11

1
UMA@ BK1608LL121-T 0603 1 16
2 1 CRT_G_C 1 2 CRT_G_L 7 17
9 CRT_G

2
R620 0_0402_5% L3

G
12
UMA@ BK1608LL121-T 0603 2 UMA@
9 3VDDCDA
2 1 CRT_B_C 1 2 CRT_B_L 8 VGA_DDC_DATA_C 1 3 2 1
9 CRT_B
R621 0_0402_5% L4 13 R628 0_0402_5%

S
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

2
150_0402_1%

150_0402_1%

150_0402_1%
1 BK1608LL121-T 0603

G
1 1 3
1

1
@ @ @ 1 1 1 DDC_MD2 9 BSS138_NL_SOT23 UMA@
9 3VDDCCL
R2

R7

R8
C9 C8 C6 For EMI 14 VGA_DDC_CLK_C 1 3 2 1
C1 C2 C3 4 R629 0_0402_5%

S
2 2 2
10
2 2 2
15
2

2 Q1
CRT_GND 1 5 VGA@
BSS138_NL_SOT23 34 VGA_DDCDATA
4.7P_0402_50V8C 4.7P_0402_50V8C 4.7P_0402_50V8C C345 Q3 1

100P_0402_50V8J
2
SUYIN_070549FR015S208CR R624 0_0402_5%
+CRT_VCC HSYNC_L VGA@
1 2 CONN@
L25 0_0603_5% 2
2 1
1 2 2 1 1 VGA_DDC_DATA_C R625 0_0402_5%
C18 0.1U_0402_16V4Z R319 10K_0402_5% 1 2 VSYNC_L C349
34 VGA_DDCCLK
L24 0_0603_5% 1
5
1

100P_0402_50V8J

100P_0402_50V8J
UMA@ 2
1 1
P
OE#

CRT_HSYNC 1 2CRT_HSYNC_B 2 4 D_CRT_HSYNC C7 VGA_DDC_CLK_C


9 CRT_HSYNC A Y 2
R336 30_0402_5% C348 C347
G

U5

15P_0402_50V8J

15P_0402_50V8J
VGA@ 74AHCT1G125GW_SOT353-5 2 2
3

34 VGA_HSYNC 2 1 1
R631 0_0402_5% +CRT_VCC
VGA@ R6

100P_0402_50V8J
2 1 1 2 C4 0_0805_5%
34 VGA_VSYNC 2
R632 0_0402_5% C17 0.1U_0402_16V4Z CRT_GND 2 1
5
1

UMA@ R314
P
OE#

2 2
CRT_VSYNC 1 2CRT_VSYNC_B 2 4 D_CRT_VSYNC 0_0805_5%
9 CRT_VSYNC A Y
R337 30_0402_5% 2 1
G

U6
74AHCT1G125GW_SOT353-5
3

Close to GMCH Close to VGA

LVDSAC+ UMA@ R508 1 2 0_0402_5% GMCH_LVDSAC+


LCD +3VS
LVDSAC- UMA@ R510

LVDSA0+ UMA@ R544


1 2 0_0402_5%

0_0402_5%
GMCH_LVDSAC-

GMCH_LVDSA0+
GMCH_LVDSAC+ 9
GMCH_LVDSAC- 9
1 2
EC_ENBKL LVDSA0- UMA@ R570 1 2 0_0402_5% GMCH_LVDSA0- GMCH_LVDSA0+ 9
29 EC_ENBKL

1
+3VS +LCDVDD GMCH_LVDSA0- 9
W=60mils U53 W=60mils R21 LVDSA1+ UMA@ R595 0_0402_5% GMCH_LVDSA1+
1 2
6 1 +LCDVDD LVDSA1- UMA@ R596 1 2 0_0402_5% GMCH_LVDSA1- GMCH_LVDSA1+ 9
IN OUT D26 4.7K_0402_5% GMCH_LVDSA1- 9
1
3 4 1 1 CH751H-40_SC76 LVDSA2+ UMA@ R597 1 2 0_0402_5% GMCH_LVDSA2+

2
C372 EN NC C363 C369 BKOFF# DISPOFF# LVDSA2- UMA@ R598 0_0402_5% GMCH_LVDSA2- GMCH_LVDSA2+ 9
29 BKOFF# 1 2 1 2
0.1U_0402_16V7K~N D25 GMCH_LVDSA2- 9
0.1U_0402_16V7K~N

5 2
4.7U_0805_6.3V6K~N

2 GND GND @ CH751H-40_SC76


D9 AOZ1320CI-04_SOT23-6 2 2
9 GMCH_ENBKL 2 R655 1 EC_ENBKL 1 2
9 GMCH_LVDDEN GMCH_LVDDEN 2 1 UMA@ 0_0402_5% EDID_CLK_LCD UMA@ R599 1 2 0_0402_5% GMCH_EDID_CLK_LCD
GMCH_EDID_CLK_LCD 9
CH751H-40PT_SOD323-2 UMA@ EDID_DAT_LCD UMA@ R600 1 2 0_0402_5% GMCH_EDID_DAT_LCD
GMCH_EDID_DAT_LCD 9
D8
1

34 VGA_LVDDEN VGA_LVDDEN 2 1 34 G7X_ENBKL 2 R651 1 R652 R652


CH751H-40PT_SOD323-2 VGA@ R15 VGA@ 0_0402_5% 2.2K_0402_5%
10K_0402_5% VGA@
29 LCD_VCC_TEST_EN LCD_VCC_TEST_EN 2 R662 1
0_0402_5%
2

100K_0402_5%
3 UMA@ 3

VGA_LVDSAC+ R630 1 2 0_0402_5% VGA@ LVDSAC+


35 VGA_LVDSAC+ VGA_LVDSAC- R633 1 2 0_0402_5% VGA@ LVDSAC-
BIA_PWM 2 1 INVT_PWM 35 VGA_LVDSAC-
9 BIA_PWM
@ R20 10_0402_5% VGA_LVDSA0+ R634 1 2 0_0402_5% VGA@LVDSA0+
JP4 35 VGA_LVDSA0+ VGA_LVDSA0- R635 1 2 0_0402_5% VGA@ LVDSA0-
1
LCD_CBL_DET# 1 2 LCD_TST 35 VGA_LVDSA0-
+3VS 29 LCD_CBL_DET# 1 2 LCD_TST 29
C36 3 4 VGA_LVDSA1+ R601 1 2 0_0402_5% VGA@ LVDSA1+
@ 1U_0603_10V4Z 3 4 LVDSAC+ 35 VGA_LVDSA1+ VGA_LVDSA1- R602 0_0402_5% VGA@ LVDSA1-
5 5 6 6 1 2
2 LVDSAC- 35 VGA_LVDSA1-
+LCDVDD 7 7 8 8
1 9 10 VGA_LVDSA2+ R603 1 2 0_0402_5% VGA@ LVDSA2+
9 10 LVDSA0+ 35 VGA_LVDSA2+ VGA_LVDSA2- R604 0_0402_5% VGA@ LVDSA2-
+3VS 11 11 12 12 1 2
C38 EDID_CLK_LCD 13 14 LVDSA0- 35 VGA_LVDSA2-
@ 0.1U_0402_16V4Z EDID_DAT_LCD 13 14
15 15 16 16
2 LVDSA1+
17 17 18 18
19 20 LVDSA1-
MIC_DIAG 19 20
29 MIC_DIAG 21 21 22 22
+3VS 23 24 LVDSA2+ VGA_CLK_LCD R644 1 2 0_0402_5% VGA@ EDID_CLK_LCD
+3VS 23 24 34 VGA_CLK_LCD
MIC_SIG 25 26 LVDSA2- VGA_DAT_LCD R645 1 2 0_0402_5% VGA@ EDID_DAT_LCD
25 MIC_SIG 25 26 34 VGA_DAT_LCD
MIC_CLK 27 28
25 MIC_CLK 27 28
29 30 DISPOFF#
29 30 DAC_BRIG
31 31 32 32 DAC_BRIG 29
+5VS 33 34 INVT_PWM
33 34 INVT_PWM 29
19 USB20_N8 35 35 36 36
37 38 INVPWR_B+ 1 2 B+
19 USB20_P8 37 38
39 39 40 40
41 42 L5 FBMA-L11-201209-221LMA30T_0805
GND GND
2 2
2

ACES_88242-4001~N C32 C34


C195
220P_0402_50V7K 0.1U_0603_50V4Z 0.1U_0603_50V4Z
1

1 1
4 4
2

C251

220P_0402_50V7K
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN/LCD CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 15 of 49
A B C D E
5 4 3 2 1

http://laptopblue.vn
+3VM_CK505
FSLC FSLB FSLA CPU SRC PCI
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +3VS 1
R397
2
0_1206_5% 1 1 1 1 1 1 1
C479 C480 C478 C476 C464 C463 C460
0 1 0 200 100 33.3
10U_0805_10V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N
2 2 2 2 2 2 2
0 1 1 166 100 33.3

FSB Frequency Selet: +1.25VS


Place close to U7
D +1.25VM_CK505 D
CPU Driven Stuff R1107 R1135 R1083
R261 0_1206_5%
1 2 0.1U_0402_16V4Z~N 22U_0805_6.3V4Z 0.1U_0402_16V4Z~N
*(Default) No Stuff R1074 R1086 R1098 R1113 R1128 R1139 1 1 1 1 1 1 1
C474 C475
C462 C461 C477 C473
Stuff R1086 R1139 R1135 R1074 R1139 R1135 C459
2 2 2 2 2 2 2
667MHz 22U_0805_6.3V4Z 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N
No Stuff R1083 R1107 R1128
R1113 R1098
Stuff
R1135 R1139
+3VM_CK505 U7
800MHz
No Stuff R1083 R1086 R1098 R1128 2 VDDPCI NC 48
9 VDD48
R1074 R1107 R1113 16 VDDPLL3
61 VDDREF
SCLK 64
39 63 ICH_SM_CLK 13,14,19,24
VDDSRC SDATA ICH_SM_DA 13,14,19,24
55 VDDCPU
PCI_STOP# 38
37 H_STP_PCI# 19
CPU_STOP# H_STP_CPU# 19
+1.25VM_CK505 12 VDD96_IO
R402 20
2.2K_0402_5% VDDPLL3_IO R202
26 VDDSRC_IO
FSA 2 1 1 2 54 R_CPU_BCLK 1 2 0_0402_5%
MCH_CLKSEL0 7 CPU0 CLK_CPU_BCLK 4
36 53 R_CPU_BCLK# 1 2 0_0402_5%
VDDSRC_IO CPU0# CLK_CPU_BCLK# 4
1 2 R411 49 R203
C 5 CPU_BSEL0 VDDCPU_IO C
R410 1K_0402_5%
0_0402_5% R204
+VCCP 51 R_MCH_BCLK 1 2 0_0402_5%
CPU1_F CLK_MCH_BCLK 7
50 R_MCH_BCLK# 1 2 0_0402_5%
CPU1#_F CLK_MCH_BCLK# 7
+3VS 2 1 R205
2

10K_0402_5% R235 R208


R379 +3VS 2 1 47 R_PCIE_LAN 1 2 0_0402_5%
SRC8/CPU2_ITP CLK_PCIE_LAN 22
10K_0402_5% R234 46 R_PCIE_LAN# 1 2 0_0402_5%
SRC8#/CPU2_ITP# CLK_PCIE_LAN# 22
1K_0402_5% R209
475_0402_1% 1 2 R237 SATA_REQ1
19 CLKSATAREQ#
1

FSB PCI0/CR#_A R213


1 2 MCH_CLKSEL1 7
475_0402_1% 1 2 R233 MCH_REQ 3 34 R_PCIE_EXPR 1 2 0_0402_5%
7 CLKMCHREQ# PCI1/CR#_B SRC10 CLK_PCIE_EXPR 28
1 2 R377 35 R_PCIE_EXPR# 1 2 0_0402_5%
5 CPU_BSEL1 SRC10# CLK_PCIE_EXPR# 28
@ R378 1K_0402_5% 40 CLK_PCI_CB 33_0402_5% 1 2 R257 PCI2_TME 4 R212
0_0402_5% 12_0402_5% 2 PCI2/TME
29 CLK_PCI_TPM 1 R239 1 2 +3VS
24 CLK_DEBUG_PORT 12_0402_5% 1 2 R258 PCI_CLK3 5 R396 R374 10K_0402_5%
PCI3 R_CLKREQ#_H 475_0402_1%
SRC11/CR#_H 33 2 1 EXPR_CARD_REQ# 28
33_0402_5% 1 2 R259 27_SEL 6 32 R_CLKREQ#_G 2 1 475_0402_1%
29 CLK_PCI_EC PCI4/27_Select SRC11#/CR#_G MCARD_REQ#G 24
R375
33_0402_5% 1 2 R260 ITP_EN 7 1 2 +3VS
17 CLK_PCI_ICH PCI_F5/ITP_EN R251 R395 10K_0402_5%
30 R_CLK_PCIE_MCard 1 2 0_0402_5%
SRC9 CLK_PCIE_MCARD 24
R200 31 R_CLK_PCIE_MCard# 1 2 0_0402_5%
SRC9# CLK_PCIE_MCARD# 24
10K_0402_5% CLK_XTAL_IN 60 R252
FSC X1
2 1 1 2 MCH_CLKSEL2 7 1 2 +3VS
CLK_XTAL_OUT 59 R398 R385 10K_0402_5%
R185 X2 R_CLKREQ#_F 475_0402_1%
5 CPU_BSEL2 1 2 SRC7/CR#_F 44 2 1 MCARD_REQ#F 22
@ R184 1K_0402_5% 43 R_CLKREQ#_E 2 1 475_0402_1%
SRC7#/CR#_E MCARD_REQ#E 24
0_0402_5% R386
1

1 2 +3VS
R199 R399 10K_0402_5%
R210
B 0_0402_5% R_CLK_Rob 0_0402_5% B
SRC6 41 1 2 CLK_PCIE_Rob 24
33_0402_5% 1 2 R401 FSA 10 40 R_CLK_Rob# 1 2 0_0402_5%
CLK_PCIE_Rob# 24
2

19 CLK_48M_ICH USB_48MHZ/FSLA SRC6# R211

FSB 57 FSLB/TEST_MODE R_MCH_3GPLL


SRC4 27 CLK_MCH_3GPLL 7
28 R_MCH_3GPLL#
SRC4# CLK_MCH_3GPLL# 7
33_0402_1% 1 2 R201 FSC 62
19 CLK_14M_ICH REF0/FSLC/TEST_SEL
R247
24 R_PCIE_ICH 1 2 0_0402_5%
SRC3/CR#_C CLK_PCIE_ICH 19
+1.25VM_CK505 45 25 R_PCIE_ICH# 1 2 0_0402_5%
VDDSRC_IO SRC3#/CR#_D CLK_PCIE_ICH# 19
R248

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#


21 R_PCIE_SATA
SRC2/SATA CLK_PCIE_SATA 18
For 27_SEL, 0 = Enable DOT96 & SRC1, 42 22 R_PCIE_SATA#
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# 18
1 = Enable SRC0 & 27MHz 8 GNDPCI R243
For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed 11 17 SSCDREFCLK 1 2UMA@ 0_0402_5%
GND48 SRC1/SE1/27MHz_NonSS MCH_SSCDREFCLK 7
18 SSCDREFCLK# 1 2UMA@ 0_0402_5%
SRC1#/SE2/27MHz_SS MCH_SSCDREFCLK# 7
1 = Overclocking of CPU and SRC NOT allowed 15 R244
GND
19 R241
CLK_XTAL_OUT GND R_MCH_DREFCLK
SRC0/DOT96 13 1 2UMA@ 0_0402_5% CLK_MCH_DREFCLK 7
+3VM_CK505 52 14 R_MCH_DREFCLK# 1 2UMA@ 0_0402_5%
+3VM_CK505 GNDCPU SRC0#/DOT96# CLK_MCH_DREFCLK# 7
CLK_XTAL_IN R242
23 R344 1 2VGA@ 0_0402_5%
GNDSRC CLK_PCIE_VGA 34
2

R493 1 2VGA@ 0_0402_5% CLK_PCIE_VGA# 34


2

14.31818MHZ_16P R236 29
R492 GNDSRC
10K_0402_5% CK_PWRGD/PD# 56
A CK_PWRGD 19 A
Y3 Placed 10K_0402_5% 58 GNDREF
VGA@ 1 2
within 500
1

2 1 ICS9LPRS365BGLFT_TSSOP64 @ R376 0_0402_5% CLK_EN# 49


1

mils of ITP_EN 27_SEL PCI2_TME


CK505M
2 2
2

C265 C257 R240 R268 R238


18P_0402_50V8J~N
1 1
18P_0402_50V8J~N 10K_0402_5% 10K_0402_5% 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
UMA@ 2007/1/15 2008/1/15 Title
@ Issued Date Deciphered Date
Clock generator
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 16 of 49
5 4 3 2 1
5 4 3 2 1

+3VS
http://laptopblue.vn
1 2 PCI_DEVSEL#
R190 8.2K_0402_5%
1 2 PCI_STOP#
R191 8.2K_0402_5% 40 PCI_AD[0..31]
1 2 PCI_TRDY# U8B
R221 8.2K_0402_5% PCI_AD0 D20 A4 PCI_REQ0#
AD0 REQ0# PCI_REQ0# 40
PCI_FRAME# PCI_AD1 PCI_GNT0#
D
1
R192
2
8.2K_0402_5% PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ1#
PCI_GNT0# 40 D
PCI_PLOCK# PCI_AD3 AD2 REQ1#/GPIO50
1 2 A20 AD3 GNT1#/GPIO51 C18
R218 8.2K_0402_5% PCI_AD4 D17 B19 PCI_REQ2#
PCI_IRDY# PCI_AD5 AD4 REQ2#/GPIO52
1 2 A21 AD5 GNT2#/GPIO53 F18
R220 8.2K_0402_5% PCI_AD6 A19 A11 PCI_REQ3#
PCI_SERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C19 AD7 GNT3#/GPIO55 C10
R166 8.2K_0402_5% PCI_AD8 A18
PCI_PERR# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 AD9 C/BE0# C17 PCI_CBE#0 40
R219 8.2K_0402_5% PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 40
PCI_AD11 E16 F16 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 40
PCI_AD12 A14 E17 PCI_CBE#3
+3VS AD12 C/BE3# PCI_CBE#3 40
PCI_AD13 G16
PCI_AD14 AD13 PCI_IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# 40
PCI_AD15 B6 D9 PCI_PAR
AD15 PAR PCI_PAR 40
1 2 PCI_PIRQA# PCI_AD16 C11 G6 PCI_PCIRST#
R165 8.2K_0402_5% PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 AD17 DEVSEL# D16 PCI_DEVSEL# 40
1 2 PCI_PIRQB# PCI_AD18 D11 A7 PCI_PERR#
AD18 PERR# PCI_PERR#
R217 8.2K_0402_5% PCI_AD19 B12 B7 PCI_PLOCK#
PCI_PIRQC# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 C12 AD20 SERR# F10 PCI_SERR#
R216 8.2K_0402_5% PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# 40
1 2 PCI_PIRQD# PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# 40
R389 8.2K_0402_5% PCI_AD23 F13 A17 PCI_FRAME#
AD23 FRAME# PCI_FRAME# 40
1 2 PCI_PIRQE# PCI_AD24 E11
R164 8.2K_0402_5% PCI_AD25 AD24 PCI_PLTRST#
E13 AD25 PLTRST# AG24
1 2 PCI_PIRQF# PCI_AD26 E12 B10 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH 16
R167 8.2K_0402_5% PCI_AD27 D8 G7 EC_PME#
AD27 PME# EC_PME# 29
1 2 PCI_PIRQG# PCI_AD28 A6
R168 8.2K_0402_5% PCI_AD29 AD28
E8 AD29
2 1 PCI_PIRQH# PCI_AD30 D6
R214 8.2K_0402_5% PCI_AD31 AD30
A3 AD31

C
1 2 PCI_REQ0# PCI_PIRQA# F9
Interrupt I/F F8 PCI_PIRQE# C
R215 8.2K_0402_5% PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
B5 PIRQB# PIRQF#/GPIO3 G11 PCI_PIRQF#
1 2 PCI_REQ1# PCI_PIRQC# C5 F12 PCI_PIRQG#
PIRQC# PIRQG#/GPIO4 PCI_PIRQG# 40
R178 8.2K_0402_5% PCI_PIRQD# A10 B3 PCI_PIRQH#
PCI_REQ2# PIRQD# PIRQH#/GPIO5
1 2
R193 8.2K_0402_5% ICH8M REV 1.0
1 2 PCI_REQ3#
R388 8.2K_0402_5%

PCI_GNT3#
Check if use LPC?
1

R189
@
1K_0402_5%
Boot BIOS Strap
2

B B
+3VALW

PCI_GNT0# SPI_CS#1 Boot BIOS Location

5
@ U9
PCI_PCIRST# 2

P
B PCI_RST#
4
0 1 SPI 1 A
Y PCI_RST# 21,40

1
A16 swap override Strap MC74VHC1G08DFT2G SC70 5P R186

3
R187
1 0 PCI 0_0402_5%
100K_0402_5%
Low= A16 swap override Enble 2 1
PCI_GNT3#

2
High= Default*
1 1 LPC * +3VALW

5
@ U10
PCI_GNT0# SPI_CS1#_R PCI_PLTRST# 2

P
19 SPI_CS1#_R B
4 PLT_RST#
Y PLT_RST# 7,19,22,24,28,29,34
Place closely pin B10 1 A
1

1
MC74VHC1G08DFT2G SC70 5P R112

3
CLK_PCI_ICH @ R188 @ R179 100K_0402_5%
1K_0402_5% 1K_0402_5% R122
2

0_0402_5%
2

2
R390 2 1

@ 10_0402_5%
1

A A
1
C470

@ 8.2P_0402_50V
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 17 of 49
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn +3VS

R127
GATEA20 2 1

10K_0402_5%

R163
KB_RST# 2 1

10K_0402_5%
D +RTCVCC D

R139 330K_0402_1%
1 2 LAN100_SLP +VCCP
R156
R140 1M_0402_5% H_FERR# 2 1
1 2 SM_INTRUDER# LPC_AD[0..3] 24,29
U8A 56_0402_5%
R141 330K_0402_1% ICH_RTCX1 AG25 E5 LPC_AD0
RTCX1 FWH0/LAD0
1 2 ICH_INTVRMEN ICH_RTCX2 AF24 RTCX2 FWH1/LAD1 F5 LPC_AD1
G8 LPC_AD2
R124 1 ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTCVCC 2 AF23 RTCRST# 9(ic"27") FWH3/LAD3 F6
20K_0402_5%
SM_INTRUDER# AD22 C4 LPC_FRAME#
INTRUDER# FWH4/LFRAME# LPC_FRAME# 24,29

RTC
LPC
ICH_INTVRMEN AF25 G9 LPC_DRQ0#
INTVRMEN LDRQ0#

2
1 LAN100_SLP AD21 E6 T36 PAD
ICH_RTCX1 C188 JOPEN1 LAN100_SLP LDRQ1#/GPIO23 T35 PAD
R341 1U_0603_10V6K @ B24 AF13 GATEA20
GATEA20 29

1
ICH_RTCX2 GLAN_CLK A20GATE H_A20M#
1 2 A20M# AG26 H_A20M# 4
2
D22 LAN_RSTSYNC
10M_0402_5% AF26 H_DPRSTP_R# 2 1 H_DPRSTP#
DPRSTP# H_DPRSTP# 5,7,49
1 1 C21 AE26 R129 0_0402_5%
LAN_RXD0 DPSLP#
B21 LAN_RXD1 H_DPSLP# 5
C415 C419 C22 AD24 H_FERR#
10P_0402_50V8J~N LAN_RXD2 FERR# H_FERR# 4

LAN / GLAN
10P_0402_50V8J~N
2 2 H_PWRGOOD
D21 LAN_TXD0 CPUPWRGD/GPIO49 AG29 H_PWRGOOD 5
1

E20 LAN_TXD1
Y2 C20 AF27 H_IGNNE#
IN

OUT

LAN_TXD2 IGNNE# H_IGNNE# 4


32.768KHZ_12.5PF_1TJS125BJ4A421P within 2" from R1557
AH21 AE24 H_INIT#
GLAN_DOCK#/GPIO13 INIT# H_INIT# 4 +VCCP
AC20 H_INTR
INTR H_INTR 4

CPU
C C
R181 1 2 24.9_0402_1% GLAN_COMP KB_RST#
NC

NC

+1.5VS D25 GLAN_COMPI RCIN# AH14 KB_RST# 29


C25 GLAN_COMPO

1
AD23 H_NMI
H_NMI 4
2

R346 33_0402_5% 1 HDA_BITCLK_R NMI H_SMI# R131


25 ACZ_BITCLK 2 AJ16 HDA_BIT_CLK SMI# AG28 H_SMI# 4
R353 33_0402_5% 1 2 HDA_SYNC_R AJ15
25 ACZ_SYNC HDA_SYNC
AA24 H_STPCLK# 56_0402_5%
STPCLK# H_STPCLK# 4
R110 33_0402_5% 1 2 HDA_RST_R# AE14
25 ACZ_RST#

2
+3VS HDA_RST# THRMTRIP_ICH# R130 24_0402_1%
THRMTRIP# AE27 1 2 H_THERMTRIP# 4,7
ADC_ACZ_SDIN0 AJ17
25 ADC_ACZ_SDIN0 HDA_SDIN0
AH17 HDA_SDIN1 TP8 AA23 IDE_DD[0..15] 21
AH15 HDA_SDIN2 IDE_DD0 placed within 2" from ICH8M

IHDA
AD13 HDA_SDIN3 DD0 V1
10K_0402_5% 2 1 R135 SATA_LED# U2 IDE_DD1
R356 33_0402_5% 1 HDA_SDOUT_R DD1 IDE_DD2
25 ACZ_SDOUT 2 AE13 HDA_SDOUT DD2 V3
T1 IDE_DD3 +3VS
DD3 IDE_DD4
PAD T19 AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C AG14 T5 IDE_DD5
21 PSATA_ITX_DRX_N0 HDA_DOCK_RST#/GPIO34 DD5
C193 3900P_0402_50V7K AB2 IDE_DD6
SATA_LED# DD6 IDE_DD7 IDE_DIORDY R145 1
31 SATA_LED# AF10 SATALED# DD7 T6 2 4.7K_0402_5%
PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C T3 IDE_DD8 IDE_IRQ R146 1 2 8.2K_0402_5%
21 PSATA_ITX_DRX_P0 DD8
C192 3900P_0402_50V7K PSATA_IRX_DTX_N0_C AF6 R2 IDE_DD9
21 PSATA_IRX_DTX_N0_C SATA0RXN DD9
PSATA_IRX_DTX_P0_C AF5 T4 IDE_DD10
21 PSATA_IRX_DTX_P0_C SATA0RXP DD10
PSATA_ITX_DRX_N0_C AH5 V6 IDE_DD11
PSATA_ITX_DRX_P0_C SATA0TXN DD11 IDE_DD12
AH6 SATA0TXP DD12 V5
close ICH8 U1 IDE_DD13
DD13 IDE_DD14
AG3 SATA1RXN DD14 V2
AG4 U6 IDE_DD15
SATA1RXP DD15

IDE
AJ4 SATA1TXN
@ AJ3 AA4 IDE_DA0
SATA1TXP DA0 IDE_DA0 21
ODD_ITX_DRX_N0 1 2 ODD_ITX_DRX_N0_C AA1 IDE_DA1
ODD_ITX_DRX_N0 DA1 IDE_DA1 21

SATA
C323 3900P_0402_50V7K ODD_IRX_DTX_N0_C AF2 AB3 IDE_DA2
21 ODD_IRX_DTX_N0_C SATA2RXN DA2 IDE_DA2 21
@ ODD_IRX_DTX_P0_C AF1
B 21 ODD_IRX_DTX_P0_C SATA2RXP B
ODD_ITX_DRX_P0 1 2 ODD_ITX_DRX_P0_C ODD_ITX_DRX_N0_C AE4 Y6 IDE_DCS1#
ODD_ITX_DRX_P0 SATA2TXN DCS1# IDE_DCS1# 21
C325 3900P_0402_50V7K ODD_ITX_DRX_P0_C AE3 Y5 IDE_DCS3#
SATA2TXP DCS3# IDE_DCS3# 21
CLK_PCIE_SATA# AB7 W4 IDE_DIOR#
16 CLK_PCIE_SATA# SATA_CLKN DIOR# IDE_DIOR# 21
CLK_PCIE_SATA AC6 W3 IDE_DIOW#
16 CLK_PCIE_SATA SATA_CLKP DIOW# IDE_DIOW# 21
close ICH8 Y2 IDE_DDACK#
DDACK# IDE_DDACK# 21
R358 AG1 Y3 IDE_IRQ
SATARBIAS# IDEIRQ IDE_IRQ 21
1 2 AG2 Y1 IDE_DIORDY
SATARBIAS IORDY IDE_DIORDY 21
W5 IDE_DDREQ
DDREQ IDE_DDREQ 21
24.9_0402_1%
Within 500 mils ICH8M REV 1.0

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS
@ R357
1K_0402_5%
2 1 ACZ_SDOUT

2 1 ICH_RSVD ICH_RSVD 19
@ R352
1K_0402_5%

XOR Chain Entrance Strap

A
ICH RSVD HDA SDOUT Description A

0 0 RSVD

0 1 Enter XOR Chain

1 0 Normal Operation (Default)


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

1 1 Set PCIE port config bit 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 18 of 49
5 4 3 2 1
5 4 3 2 1

2SERIRQ +3VALW +3VALW


1 Place closely pin G5 Place closely pin AG9

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+3VS +3VS
R148 10K_0402_5%

1 2PCI_CLKRUN# CLK_48M_ICH CLK_14M_ICH

2
R348 8.2K_0402_5%
R136 R137 R106 R107 R347

1
1 2EC_THERM# 2.2K_0402_5% 2.2K_0402_5% 8.2K_0402_5%
@ R149 8.2K_0402_5% 10K_0402_5% 10K_0402_5% R175 R125
U8C

1
1 2OCP# 28 ICH_SMB_CLK
ICH_SMB_CLK AJ26 SMBCLK SATA0GP/GPIO21 AJ12 @ 10_0402_5% @ 10_0402_5%
R115 8.2K_0402_5% ICH_SMB_DATA AD19 AJ10
28 ICH_SMB_DATA

2
CL_RST#1 SMBDATA SATA1GP/GPIO19

SATA
AG21 AF11

GPIO
LINKALERT# SATA2GP/GPIO36

SMB
ME_SMB_CK AC17 AG11 1 1
ME_SMB_DA SMLINK0 SATA3GP/GPIO37 C229 C196
AE19 SMLINK1
AG9 CLK_14M_ICH
D CLK14 CLK_14M_ICH 16 D
ICH_RI#

Clocks
AF17 G5 CLK_48M_ICH @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
RI# CLK48 CLK_48M_ICH 16 2 2
PAD T30 F4 D3 ICH_SUSCLK T34 PAD
SUS_STAT#/LPCPD# SUSCLK
+3VALW 2 1ICH_LOW_BAT# 4 XDP_DBRESET#
XDP_DBRESET# AD15
SYS_RESET#
R138 8.2K_0402_5% AG23 SLP_S3#
SLP_S3# SLP_S3# 29
PM_BMBUSY# AG12 AF21 SLP_S4#
7 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SLP_S4# 29
1 2ICH_PCIE_WAKE# SLP_S5# AD18 SLP_S5#
SLP_S5# 29
R151 1K_0402_5% 29 EC_LID_OUT# EC_LID_OUT# AG22 SMBALERT#/GPIO11
S4_STATE#/GPIO26 AH27 T46 PAD R123 0_0402_5%
2ICH_RI# H_STP_PCI# M_PWROK

GPIO
1 16 H_STP_PCI# AE20 STP_PCI#/GPIO15 1 2

SYS
R119 10K_0402_5% H_STP_CPU# AG18 AE23 PM_PWROK
16 H_STP_CPU# STP_CPU#/GPIO25 PWROK PM_PWROK 7,29
1 2 R128
1 2XDP_DBRESET# 29,40 PCI_CLKRUN# AH11 CLKRUN#/GPIO32 DPRSLPVR/GPIO16 AJ14 DPRSLPVR
DPRSLPVR 7,49
10K_0402_5%

Power MGT
R150 10K_0402_5%
ICH_PCIE_WAKE# AE17 AE21 ICH_LOW_BAT#
24,28 ICH_PCIE_WAKE# WAKE# BATLOW#
1 2 CL_RST#1 29 SERIRQ SERIRQ AF12 SERIRQ
R121 10K_0402_5% EC_THERM# AC13 C2 PBTN_OUT#
4,29 EC_THERM# THRM# PWRBTN# PBTN_OUT# 29
1 2 EC_LID_OUT# 7,29,49 VGATE
VGATE 1 2 VRMPWRGD AJ20 VRMPWRGD LAN_RST# AH20 PLT_RST# 7,17,22,24,28,29,34
@ R132 10K_0402_5% R345 0_0402_5% 1 2
PAD T45 SST_CTL AJ22 AG27 PM_RSMRST# R158 10K_0402_5%
TP7 RSMRST#
OCP# AJ8 E1 CK_PWRGD_R 1 2 CK_PWRGD
4 OCP# TACH1/GPIO1 CK_PWRGD CK_PWRGD 16
AJ9 R176 0_0402_5%
TACH2/GPIO6 M_PWROK
AH9 TACH3/GPIO7 CLPWROK E3 M_PWROK 7 RSMRST# -> CLPWROK -> PWROK
+3VS 1 2SB_SPKR 29 EC_SMI#
EC_SMI# AE16 GPIO8
R134 @ 10K_0402_5% EC_SCI# AC19 AJ25 T43 PAD
29 EC_SCI# GPIO12 SLP_M#
low-->default PAD T17 AG8 TACH0/GPIO17
PAD T18 AH12 F23 CL_CLK0
GPIO18 CL_CLK0 CL_CLK0 7
High -->No boot AE11 GPIO20 CL_CLK1 AE18

GPIO
Controller Link
AG10 SCLOCK/GPIO22
AH25 F22 CL_DATA0
C QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 7 C
RP27 PAD T20 AD16 AF19
USB_OC#1 CLKSATAREQ# QRT_STATE1/GPIO28 CL_DATA1 R195 3.24K_0402_1%
+3VALW 5 4 16 CLKSATAREQ# AG13 SATACLKREQ#/GPIO35
6 3 USB_OC#2 AF9 D24 CL_VREF0_ICH 1 2 +3VS
USB_OC#3 SLOAD/GPIO38 CL_VREF0 CL_VREF1_ICH
7 2 AJ11 SDATAOUT0/GPIO39 CL_VREF1 AH23 T44 PAD

1
0.1U_0402_16V4Z~N
8 1 USB_OC#4 AD10 1
SDATAOUT1/GPIO48 C234 R180
CL_RST# AJ23 CL_RST# 7
10K_1206_8P4R_5% SB_SPKR AD9 453_0402_1%
25 SB_SPKR SPKR
MEM_LED/GPIO24 AJ27
2

MISC
RP28 MCH_ICH_SYNC# AJ13 AJ24 2 1
7 MCH_ICH_SYNC# ACIN 29,43,44

2
USB_OC#5 MCH_SYNC# ME_EC_ALERT/GPIO10
5 4 EC_ME_ALERT/GPIO14 AF22 0_0402_5% R339
6 3 USB_OC#8 ICH_RSVD AJ21 AG19
18 ICH_RSVD TP3 WOL_EN/GPIO9 LAN_WOL_EN 29
7 2 USB_OC#9
8 1 USB_OC#0 ICH8M REV 1.0
10K_1206_8P4R_5%

2 1 USB_OC#7
R118 10K_0402_5%
U8D
P27 V27 DMI_RXN0 DMI_RXN0 7
modify follow intel check list-1003 PERN1 DMI0RXN DMI_RXP0
P26 PERP1 DMI0RXP V26 DMI_RXP0 7
N29 U29 DMI_TXN0 DMI_TXN0 7
100K_0402_5% PETN1 DMI0TXN DMI_TXP0
N28 U28 DMI_TXP0 7

Direct Media Interface


PETP1 DMI0TXP
1 2 LAN_WOL_EN
R120 PCIE_RXN2 M27 Y27 DMI_RXN1 DMI_RXN1 7
28 PCIE_RXN2 PERN2 DMI1RXN
Express Card PCIE_RXP2 M26 Y26 DMI_RXP1 DMI_RXP1 7
28 PCIE_RXP2 PERP2 DMI1RXP
1 2 DPRSLPVR 28 PCIE_TXN2 0.1U_0402_16V7K~N2 1 C435 PCIE_C_TXN2 L29 W29 DMI_TXN1 DMI_TXN1 7
0.1U_0402_16V7K~N2 C436 PCIE_C_TXP2 PETN2 DMI1TXN DMI_TXP1
28 PCIE_TXP2 1 L28 PETP2 DMI1TXP W28 DMI_TXP1 7
@ R117 499_0402_1%

PCI-Express
PCIE_RXN3 K27 AB26 DMI_RXN2 DMI_RXN2 7
24 PCIE_RXN3 PERN3 DMI2RXN
100K_0402_5% Robson 24 PCIE_RXP3 K26 AB25 DMI_RXP2 DMI_RXP2 7
PCIE_RXP3 PERP3 DMI2RXP
1 2 VRMPWRGD 24 PCIE_TXN3 0.1U_0402_16V7K~N2 1 C437 PCIE_C_TXN3 J29 PETN3 DMI2TXN AA29 DMI_TXN2 DMI_TXN2 7
R342 24 PCIE_TXP3 0.1U_0402_16V7K~N2 1 C450 PCIE_C_TXP3 J28 AA28 DMI_TXP2 DMI_TXP2 7
B PETP3 DMI2TXP B
PCIE_RXN4 H27 AD27 DMI_RXN3 DMI_RXN3 7
24 PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 H26 AD26 DMI_RXP3 DMI_RXP3 7
24 PCIE_RXP4 PERP4 DMI3RXP
WLAN 24 PCIE_TXN4 0.1U_0402_16V7K~N2 1 C451 PCIE_C_TXN4 G29 PETN4 DMI3TXN AC29 DMI_TXN3 DMI_TXN3 7
24 PCIE_TXP4 0.1U_0402_16V7K~N2 1 C452 PCIE_C_TXP4 G28 PETP4 DMI3TXP AC28 DMI_TXP3 DMI_TXP3 7
GLAN_RXN F27 T26 CLK_PCIE_ICH#
22 GLAN_RXN PERN5 DMI_CLKN CLK_PCIE_ICH# 16
GLAN_RXP F26 T25 CLK_PCIE_ICH
22 GLAN_RXP PERP5 DMI_CLKP CLK_PCIE_ICH 16
GLAN 22 GLAN_TXN
0.1U_0402_16V7K~N2 1 C455GLAN_TXN_C E29 PETN5
0.1U_0402_16V7K~N2 1 C454 GLAN_TXP_C E28 Y23 R152 24.9_0402_1%Within 500 mils
22 GLAN_TXP PETP5 DMI_ZCOMP
Y24 DMI_IRCOMP 1 2 +1.5VS
DMI_IRCOMP
D27 PERN6/GLAN_RXN
D26 G3 USB20_N0
PERP6/GLAN_RXP USBP0N USB20_N0 32
C29 G2 USB20_P0 ESATA+USB
PETN6/GLAN_TXN USBP0P USB20_P0 32
C28 H5 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 32
H4 USB20_P1 USB0
USBP1P USB20_P1 32
C23 H2 USB20_N2
SPI_CLK USBP2N USB20_N2 32
B23 H1 USB20_P2 USB1
SPI_CS0# USBP2P USB20_P2 32
E22 J3 USB20_N3
17 SPI_CS1#_R SPI_CS1# USBP3N USB20_N3 32
SPI

J2 USB20_P3 USB2
USBP3P USB20_P3 32
D23 K5 USB20_N4
SPI_MOSI USBP4N USB20_N4 24
F21 K4 USB20_P4 Mini Card0 R157 0_0402_5%
SPI_MISO USBP4P USB20_P4 24
K2 USB20_N5 EC_RSMRST# 1 2 PM_RSMRST#
USBP5N USB20_N5 28 29 EC_RSMRST#
USB_OC#0 AJ19 K1 USB20_P5 Express Card
32 USB_OC#0 OC0# USBP5P USB20_P5 28
USB_OC#1 AG16 L3 USB20_N6
32 USB_OC#1 OC1#/GPIO40 USBP6N USB20_N6 32
USB_OC#2 USB20_P6 FingerPrinter
32 USB_OC#2
USB_OC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5 USB20_N7
USB20_P6 32
32 USB_OC#3 OC3#/GPIO42 USBP7N USB20_N7 32
USB_OC#4 AF15 M4 USB20_P7 BlueTooth
+3VS OC4#/GPIO43 USBP7P USB20_P7 32
USB_OC#5 AG17 M2 USB20_N8
OC5#/GPIO29 USBP8N USB20_N8 15
EC_SWI# AD12 M1 USB20_P8 Camera
29 EC_SWI# OC6#/GPIO30 USBP8P USB20_P8 15
USB_OC#7 AJ18 N3 USB20_N9
OC7#/GPIO31 USBP9N USB20_N9 32
USB_OC#8 AD14 N2 USB20_P9 Felica
OC8# USBP9P USB20_P9 32
1

A 2.2K_0402_5% USB_OC#9 A
AH18 OC9#
2.2K_0402_5% R104 R105 F2 USBRBIAS 1 2
USBRBIAS# R177 22.6_0402_1%
USBRBIAS F3
Q9
SSM3K7002FU_SC70-3 ICH8M REV 1.0 Within 500 mils
2

2
S

3 1 ICH_SMB_DATA
13,14,16,24 ICH_SM_DA
S

3 1ICH_SMB_CLK
13,14,16,24 ICH_SM_CLK Security Classification Compal Secret Data Compal Electronics, Inc.
G
2

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title


Q10
G

ICH8(3/4)_PM,USB,GPIO
2

+5VS SSM3K7002FU_SC70-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 19 of 49
5 4 3 2 1
5 4 3 2 1

+RTCVCC
20 mils
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0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
1 1

C205

C218
2 2 U8E
U8F A23 K7
0.1U_0402_16V7K~N VSS[001] VSS[099]
AD25 VCCRTC VCC1_05[01] A13 +VCCP A5 VSS[002] VSS[100] L1
VCC1_05[02] B13 AA2 VSS[003] VSS[101] L13
ICH_V5REF_RUN A16 C13 AA7 L15
V5REF[1] VCC1_05[03] VSS[004] VSS[102]
T7 V5REF[2] VCC1_05[04] C14 1 1 A25 VSS[005] VSS[103] L26
D14 C215 C227 0.1U_0402_16V4Z~N AB1 L27
L15 VCC1_05[05] VSS[006] VSS[104]
ICH_V5REF_SUS G4 E14 AB24 L4
D 10U_0805_6.3V6M V5REF_SUS VCC1_05[06] VSS[007] VSS[105] D
+1.5VS 1 2 40 mils VCC1_05[07] F14
2 2
AC11 VSS[008] VSS[106] L5
1 AA25 VCC1_5_B[01] VCC1_05[08] G14 AC14 VSS[009] VSS[107] M12
CHB1608U301_0603 1 1 1 AA26 L11 AC25 M13
+ C430 C200 C427 VCC1_5_B[02] VCC1_05[09] VSS[010] VSS[108]
AA27 VCC1_5_B[03] VCC1_05[10] L12 AC26 VSS[011] VSS[109] M14

C219

220U_D2_4VY_R15M
AB27 VCC1_5_B[04] VCC1_05[11] L14 AC27 VSS[012] VSS[110] M15
AB28 VCC1_5_B[05] VCC1_05[12] L16 AD17 VSS[013] VSS[111] M16
2 2 2 2
AB29 VCC1_5_B[06] VCC1_05[13] L17 AD20 VSS[014] VSS[112] M17
+5VS +3VS D28 L18 L16 AD28 M23
10U_0805_6.3V6M 2.2U_0603_6.3V4Z~N VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K~N 1 VSS[015] VSS[113]
D29 VCC1_5_B[08] VCC1_05[15] M11 2 +1.5VS AD29 VSS[016] VSS[114] M28

CORE
E25 M18 CHB1608U301_0603 AD3 M29
VCC1_5_B[09] VCC1_05[16] VSS[017] VSS[115]
1

E26 VCC1_5_B[10] VCC1_05[17] P11 1 1 AD4 VSS[018] VSS[116] M3


R159 D10 E27 P18 C225 10U_0805_6.3V6M AD6 N1
VCC1_5_B[11] VCC1_05[18] VSS[019] VSS[117]
F24 VCC1_5_B[12] VCC1_05[19] T11 AE1 VSS[020] VSS[118] N11
100_0402_5% CH751H-40PT_SOD323-2 F25 T18 C431 AE12 N12
VCC1_5_B[13] VCC1_05[20] 2 2 VSS[021] VSS[119]
20 mils G24 U11 AE2 N13
2

VCC1_5_B[14] VCC1_05[21] VSS[022] VSS[120]


H23 VCC1_5_B[15] VCC1_05[22] U18 AE22 VSS[023] VSS[121] N14
ICH_V5REF_RUN H24 V11 AD1 N15
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[122]
1 J23 VCC1_5_B[17] VCC1_05[24] V12 AE25 VSS[025] VSS[123] N16
C224 J24 V14 +1.25VS AE5 N17
VCC1_5_B[18] VCC1_05[25] VSS[026] VSS[124]
K24 VCC1_5_B[19] VCC1_05[26] V16 AE6 VSS[027] VSS[125] N18
0.1U_0402_16V4Z~N K25 V17 AE9 N26
2 VCC1_5_B[20] VCC1_05[27] VSS[028] VSS[126]

22U_0805_6.3V4Z
L23 VCC1_5_B[21] VCC1_05[28] V18 AF14 VSS[029] VSS[127] N27
L24 VCC1_5_B[22] 1 AF16 VSS[030] VSS[128] N4

VCCA3GP

C425
L25 VCC1_5_B[23] VCCDMIPLL R29 AF18 VSS[031] VSS[129] N5
M24 VCC1_5_B[24] AF3 VSS[032] VSS[130] N6
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AF4 VSS[033] VSS[131] P12
2
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AG5 VSS[034] VSS[132] P13
+5VALW +3VALW N24 AG6 P14
VCC1_5_B[27] VSS[035] VSS[133]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 +VCCP AH10 VSS[036] VSS[134] P15
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH13 VSS[037] VSS[135] P16
1

4.7U_0603_6.3V6M

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
P25 VCC1_5_B[30] AH16 VSS[038] VSS[136] P17
R361 D18 R24 AF29 0.1U_0402_16V4Z~N
+3VS 1 1 1 AH19 P23
VCC1_5_B[31] VCC3_3[01] VSS[039] VSS[137]

C217

C203

C204
C (DMI) C
R25 VCC1_5_B[32] 1 AH2 VSS[040] VSS[138] P28
10_0402_5% CH751H-40PT_SOD323-2 R26 AD2 0.1U_0402_16V4Z~N
+3VS AF28 P29
VCC1_5_B[33] VCC3_3[02] (SATA) C197 VSS[041] VSS[139]
R27 1 AH22 R11
2

ICH_V5REF_SUS VCC1_5_B[34] 2 2 2 VSS[042] VSS[140]


T23 VCC1_5_B[35] VCC3_3[03] AC8 +3VS AH24 VSS[043] VSS[141] R12
2

C198
20 mils T24 VCC1_5_B[36] VCC3_3[04] AD8 AH26 VSS[044] VSS[142] R13

VCCP_CORE
1 T27 VCC1_5_B[37] VCC3_3[05] AE8 AH3 VSS[045] VSS[143] R14
C438 +3VS 2
T28 VCC1_5_B[38] VCC3_3[06] AF8 AH4 VSS[046] VSS[144] R15
T29 VCC1_5_B[39] AH8 VSS[047] VSS[145] R16
0.1U_0402_16V4Z~N U24 AA3 AJ5 R17
2 VCC1_5_B[40] VCC3_3[07] VSS[048] VSS[146]
U25 VCC1_5_B[41] VCC3_3[08] U7 1 B11 VSS[049] VSS[147] R18
V23 V7 C213 B14 R28
VCC1_5_B[42] VCC3_3[09] 0.1U_0402_16V4Z~N VSS[050] VSS[148]
V24 VCC1_5_B[43] VCC3_3[10] W1 B17 VSS[051] VSS[149] R4
V25 W6 B2 T12
IDE
VCC1_5_B[44] VCC3_3[11] 2 +3VS VSS[052] VSS[150]
W25 VCC1_5_B[45] VCC3_3[12] W7 B20 VSS[053] VSS[151] T13
L30 Y25 VCC1_5_B[46] VCC3_3[13] Y7 B22 VSS[054] VSS[152] T14
0.1U_0402_16V4Z~N B8 T15
VSS[055] VSS[153]
+1.5VS 1 2 AJ6 VCCSATAPLL VCC3_3[14] A8 C24 VSS[056] VSS[154] T16
1U_0603_10V4Z

VCC3_3[15] B15 1 1 1 C26 VSS[057] VSS[155] T17


10U_0805_6.3V6M

CHB1608U301_0603 AE7 B18 C27 T2


+1.5VS VCC1_5_A[01] VCC3_3[16] VSS[058] VSS[156]

C214

C232
1 1 AF7 B4 C233 C6 U12
VCC1_5_A[02] VCC3_3[17] VSS[059] VSS[157]
ARX
C422

C421

1 AG7 B9 0.1U_0402_16V4Z~N D12 U13


C420 VCC1_5_A[03] VCC3_3[18] 2 2 2 VSS[060] VSS[158]
AH7 VCC1_5_A[04] VCC3_3[19] C15 D15 VSS[061] VSS[159] U14
AJ7 D13 D18 U15
PCI

2 2 1U_0603_10V4Z VCC1_5_A[05] VCC3_3[20] 0.1U_0402_16V4Z~N VSS[062] VSS[160]


VCC3_3[21] D5 D2 VSS[063] VSS[161] U16
2
AC1 VCC1_5_A[06] VCC3_3[22] E10 D4 VSS[064] VSS[162] U17
AC2 VCC1_5_A[07] VCC3_3[23] E7 E21 VSS[065] VSS[163] U23
ATX

AC3 VCC1_5_A[08] VCC3_3[24] F11 E24 VSS[066] VSS[164] U26


AC4 VCC1_5_A[09] E4 VSS[067] VSS[165] U27
AC5 AC12 0.1U_0402_16V4Z~N +3VS E9 U3
VCC1_5_A[10] VCCHDA VSS[068] VSS[166]
1 F15 VSS[069] VSS[167] U5
+1.5VS AC10 VCC1_5_A[11] VCCSUSHDA AD11 +3VALW E23 VSS[070] VSS[168] V13
1 AC9 1 C199 F28 V15
B C428 VCC1_5_A[12] TP_VCCSUS1.05_INT_ICH1 VSS[071] VSS[169] B
VCCSUS1_05[1] J6 F29 VSS[072] VSS[170] V28
T25 2
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 TP_VCCSUS1.05_INT_ICH2 C216 F7 VSS[073] VSS[171] V29
1U_0603_10V4Z T21
AA6 VCC1_5_A[14] G1 VSS[074] VSS[172] W2
2 2 0.1U_0402_16V4Z~N
VCCSUS1_5[1] AC16 VCCSUS1_5_ICH_1 T22 E2 VSS[075] VSS[173] W26
G12 VCC1_5_A[15] G10 VSS[076] VSS[174] W27
G17 J7 VCCSUS1_5_ICH_2 T24 G13 Y28
VCC1_5_A[16] VCCSUS1_5[2] VSS[077] VSS[175]
H7 VCC1_5_A[17] G19 VSS[078] VSS[176] Y29
C3 0.1U_0402_16V4Z~N +3VALW G23 Y4
VCCSUS3_3[01] VSS[079] VSS[177]
AC7 VCC1_5_A[18] 1 1 G25 VSS[080] VSS[178] AB4
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 G26 VSS[081] VSS[179] AB23
AC21 C202 C194 G27 AB5
VCCSUS3_3[03] VSS[082] VSS[180]
+1.5VS D1 VCCUSBPLL VCCSUS3_3[04] AC22 H25 VSS[083] VSS[181] AB6
VCCPSUS

2 2 0.1U_0402_16V4Z~N
+1.5VS VCCSUS3_3[05] AG20 H28 VSS[084] VSS[182] AD5
1 1 F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 H29 VSS[085] VSS[183] U4
USB CORE

C231 C226 L6 H3 W24


VCC1_5_A[21] VSS[086] VSS[184]
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 H6 VSS[087]
0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N M6 P7 J1 A1
2 2 VCC1_5_A[23] VCCSUS3_3[08] VSS[088] VSS_NCTF[01]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 +3VALW J25 VSS[089] VSS_NCTF[02] A2
VCCSUS3_3[10] N7 1 C258 J26 VSS[090] VSS_NCTF[03] A28
+1.5VS W23 VCC1_5_A[25] VCCSUS3_3[11] P1 J27 VSS[091] VSS_NCTF[04] A29
VCCSUS3_3[12] P2 J4 VSS[092] VSS_NCTF[05] AH1
T31 VCC_LAN1_05_INT_ICH_1 F17 P3 0.47U_0603_10V7K J5 AH29
VCCLAN1_05[1] VCCSUS3_3[13] VSS[093] VSS_NCTF[06]
VCCPUSB

+3VS 0316 change design T32 VCC_LAN1_05_INT_ICH_2 2


G18 VCCLAN1_05[2] VCCSUS3_3[14] P4 K23 VSS[094] VSS_NCTF[07] AJ1
VCCSUS3_3[15] P5 K28 VSS[095] VSS_NCTF[08] AJ2
F19 VCCLAN3_3[1] VCCSUS3_3[16] R1 K29 VSS[096] VSS_NCTF[09] AJ28
1 G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 K3 VSS[097] VSS_NCTF[10] AJ29
C230 CHB1608U301_0603 R5 K6 B1
VCCSUS3_3[18] VSS[098] VSS_NCTF[11]
1 2 A24 VCCGLANPLL VCCSUS3_3[19] R6 VSS_NCTF[12] B29
0.1U_0402_16V4Z~N +1.5VS L17 @ L32 4.7U_0805_10V4Z~N
2
GLAN POWER
10U_0805_6.3V6M

2.2U_0603_106K

1 1 +1.5VS 1 2 A26 VCCGLAN1_5[1] VCCCL1_05 G22 VCCCL1_05_ICH ICH8M REV 1.0


T26
1 A27 VCCGLAN1_5[2]
C252 CHB1608U301_0603 B26 A22 1
A C261 VCCGLAN1_5[3] VCCCL1_5 A
B27 VCCGLAN1_5[4]
2 2 @ C457 @C458
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20 +3VS
2 1U_0603_10V4Z
VCCCL3_3[2] G21
2
+3VS B25 VCCGLAN3_3
ICH8M REV 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 20 of 49
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn
CDROM CONN
IDE_DD[0..15] 18

+5VS

10U_0805_10V4Z 0.1U_0402_16V4Z

1 1 1 1
C520 47P_0402_50V8J C499
C498 C506 C503
2 1

JODD1 2 2 2 2
D D
1 1U_0603_10V4Z 1000P_0402_50V7K~N
1
2 2
PCI_RST# 1 2 3
17,40 PCI_RST# 3
R448 0_0402_5% IDE_DD8 4
IDE_DD7 4
5 5
Close to ODD Conn
IDE_DD9 6
IDE_DD6 6
7 7
IDE_DD10 8
IDE_DD5 8
9 9
IDE_DD11 10
IDE_DD4 10
11 11
IDE_DD12 12
IDE_DD3 12
13 13
IDE_DD13 14
IDE_DD2 14
15 15
IDE_DD14 16
IDE_DD1 16
17 17
IDE_DD15 18
IDE_DD0 18
19 19
18 IDE_DDREQ 20 20
21 21
+5VS 22
18 IDE_DIOR# 22
18 IDE_DIOW# 23 23
24 24
18 IDE_DIORDY 25 25
18 IDE_DDACK# 26 26
1

27 +5VS
18 IDE_IRQ 27
R429 28
18 IDE_DA1 28
100K_0402_5% @ 2 R428 1 PDIAG# 29
+5VS 29
10K_0402_5% 30 0.1U_0402_16V7K~N
18 IDE_DA0 30
18 IDE_DA2 31 1
2

C 31 C
18 IDE_DCS1# 32 32 1 1 1 1
33 + C575
18 IDE_DCS3# 33
ODD_ACT_LED# 34 C574 C296 C377 C376
31 ODD_ACT_LED# 34
35 150U_B2_6.3VM_R45M
35 2 2 2 2 2

10U_0805_10V4Z~N
36 36
+5VS 80mils 37 37 0.1U_0402_16V7K~N 1000P_0402_50V7K~N
38 38
39 39
If CDROM is Slave 40 40
41 41
then SD_CSEL= Floating 42 42
43 43
else SD_CSEL= Low 1 2 SD_CSEL 44
470_0402_5% R286 44
45 45
46 GND
Close to SATA HDD
47 GND

ACES_88512-4541

SATA HDD CONN RESERVE(SATA ODD NET)


JSATA1

B B
1 GND
PSATA_ITX_DRX_P0 2
18 PSATA_ITX_DRX_P0 A+
PSATA_ITX_DRX_N0 3
18 PSATA_ITX_DRX_N0 A-
C393 3900P_0402_50V7K 4 ODD_ITX_DRX_P0
GND 18 ODD_ITX_DRX_P0
2 1 5 ODD_ITX_DRX_N0
18 PSATA_IRX_DTX_N0_C B- 18 ODD_ITX_DRX_N0
6 B+
2 1 7 1 2 ODD_IRX_DTX_N0
18 PSATA_IRX_DTX_P0_C GND 18 ODD_IRX_DTX_N0_C
C326 3900P_0402_50V7K ODD_IRX_DTX_P0
C392 3900P_0402_50V7K @
18 ODD_IRX_DTX_P0_C 1 2
8 C327 3900P_0402_50V7K
VCC3.3 @
9 VCC3.3
10 VCC3.3 close JODD1
11 GND
12 GND
13 GND
+5VS 14 VCC5
15 VCC5
16 VCC5
17 GND
18 RESERVED
19 GND
20 VCC12
21 VCC12 GND 23
22 VCC12 GND 24

SUYIN_127043FB022G345ZR_NR
CONN@

A A

Security Classification Compal Secret Data


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 21 of 49
5 4 3 2 1
5 4 3 2 1

+3VALW

Q59 L46
FBMA-L11-322513-201LMA40T_1210 http://laptopblue.vn
+LAN_IO

D
6 1.5A

S
5 4 1 2
1 2 1 1 1 1 1 1 +LAN_VDD
C790 1 C812 C777 C787 C781 C802 C804
1U_0603_10V6K SI3456BDV-T1-E3_TSOP6 @

G
3
2 2 2 2 2 2 2

22U_1206_6.3V6M

22U_1206_6.3V6M

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
B+_BIAS LAN_DVDD15

0.1U_0402_10V7K~N C800

0.1U_0402_10V7K~N C798

0.1U_0402_10V7K~N C810

0.1U_0402_10V7K~N C803

0.1U_0402_10V7K~N C572

0.1U_0402_10V7K~N C698

0.1U_0402_10V7K~N C782

0.1U_0402_10V7K~N C780

0.1U_0402_10V7K~N C779

0.1U_0402_10V7K~N C700
2 1 1 1 1 1 1 1 1 1 1
R496
D D
470K_0402_5%
2 2 2 2 2 2 2 2 2 2
1

EN_WOL

2
+LAN_IO
1

D R906
Q58 2 @ 1.5M_0402_5% 3.6K_0402_5%
SSM3K7002FU_SC70-3 G EN_WOL# 29 U28 R494 1 2
S U43
3

1
19 GLAN_RXP 2 1 GLAN_RXP_C 29 HSOP EEDO 45 LAN_EEDO 4 DO GND 5 1
C569 0.1U_0402_16V7K~N 47 LAN_EEDI 3 6 1 R495 2 C801
EEDI/AUX DI NC
19 GLAN_RXN 2 1 GLAN_RXN_C 30 HSON EESK 48 LAN_EECLK 2 SK NC 7 0_0402_5% 0.1U_0402_16V7K~N
C570 0.1U_0402_16V7K~N 44 LAN_EECS 1 8 @ @ +LAN_IO
GLAN_TXP EECS CS VCC 2
19 GLAN_TXP 23 HSIP AT93C46-10SU-2.7 SO 8P
GLAN_TXN 24 @
19 GLAN_TXN HSIN
54 LAN_LED3
LED3 LAN_LED2
LED2 55
33 56 LAN_LED1
16 MCARD_REQ#F CLKREQB LED1
57 LAN_LED0
LED0
16 CLK_PCIE_LAN 26 REFCLK_P
27 3 LAN_MDIP0
16 CLK_PCIE_LAN# REFCLK_N MDIP0
+LAN_VDD 4 LAN_MDIN0
MDIN0 LAN_MDIP1
7,17,19,24,28,29,34 PLT_RST# 20 PERSTB MDIP1 6
7 LAN_MDIN1
L92 MDIN1 LAN_MDIP2
60mil 1 2 1
MDIP2 9
10 LAN_MDIN2
4.7UH_1098AS-4R7M_1.3A_20% SROUT12 MDIN2 LAN_MDIP3
60mil 5
MDIP3 12
13 LAN_MDIN3
+LAN_VDD FB12 MDIN3
1 1 +LAN_IO 62 ENSR
C C788 C778 C
DVDD12 21 +LAN_VDD
1 2 64 RSET DVDD12 32
R497 2.49K_0402_1% 38 +LAN_IO
2 2 DVDD12
22U_1206_6.3V6M
0.1U_0402_10V7K~N

DVDD12 43
DVDD12 49 1 1 C792
29 PCIE_PME# 19 52 C783
R498 LANWAKEB DVDD12 L56

22U_1206_6.3V6M

0.1U_0402_10V7K~N
ISOLATEB FBML10160808121LMT_0603
+3VS 1 2 36 ISOLATEB
22
30mil 2 1
2 2
EVDD12 +LAN_VDD
1K_0402_5% EVDD12 28
2

LAN_XTAL1 60 1 2
R499 CKTAL1 C637 0.1U_0402_16V7K~N
LAN_XTAL2
L92, C788, C778 15K_0402_5% 61 CKTAL2 VDD33 16
37
+LAN_IO 1
C793
2
0.1U_0402_16V7K~N
VDD33
close to U28(Pin 1) <200mil 46
1

VDD33
VDD33 53
65 EXPOSE_PAD C966,C967 close to U28(PIN63)
63 +LAN_IO L55
VDDSR FBML10160808121LMT_0603
25 EGND
2 LAN_AVDD33 2 1 +LAN_IO
Y6 AVDD33
31 EGND AVDD33 59
1 2 1 2 R315
2 2 8 +LAN_VDD C571 0.1U_0402_16V7K~N 1 2 0_0402_5%
25MHZ_12P_X8A025000FC1H-H AVDD12
15 NC AVDD12 11 1 2
C791 17 14 C789 0.1U_0402_16V7K~N
15P_0402_50V8J NC AVDD12 R316
18 NC AVDD12 58
1 C805 1 0_0402_5%
34 NC 1 2
15P_0402_50V8J 35 NC
39 NC IGPIO 50
40 51 R317
NC OGPIO 0_0402_5%
41 NC 1 2
B B
42 NC
RTL8111C-GR_QFN64_9X9 R318
1 2 0_0402_5%

JLAN2

LAN_LED0 1 R968 2 LAN_ACTIVITY# 13


220_0402_5% Yellow LED-
T51 +LAN_IO 12
RP38 Yellow LED+
C573 1 2 0.01U_0402_16V7K V_DAC 1 24 8 1 C794 RJ45_TX3- 8
LAN_MDIN3 TCT1 MCT1 RJ45_TX3- 1000P_1206_2KV7K PR4-
2 TD1+ MX1+ 23 7 2
LAN_MDIP3 3 22 RJ45_TX3+ 6 3 D41 RJ45_TX3+ 7
TD1- MX1- LAN_LED2 1 LED2_LED3 PR4+
5 4 2 1 2
C784 1 2 0.01U_0402_16V7K V_DAC 4 21 RJ45_RX1- 6
LAN_MDIN2 TCT2 MCT2 RJ45_TX2- 75_1206_8P4R_5% CH751H-40PT_SOD323-2 PR2-
5 TD2+ MX2+ 20
LAN_MDIP2 6 19 RJ45_TX2+ RJ45_TX2- 5
TD2- MX2- D42 PR3-
C807 1 2 0.01U_0402_16V7K V_DAC 7 18 LAN_LED3 1 2 RJ45_TX2+ 4
LAN_MDIN1 TCT3 MCT3 RJ45_RX1- PR3+
8 TD3+ MX3+ 17
LAN_MDIP1 9 16 RJ45_RX1+ CH751H-40PT_SOD323-2 RJ45_RX1+ 3
TD3- MX3- PR2+
C799 1 2 0.01U_0402_16V7K V_DAC 10 15 RJ45_TX0- 2
LAN_MDIN0 TCT4 MCT4 RJ45_TX0- PR1-
11 TD4+ MX4+ 14 GND 15
LAN_MDIP0 12 13 RJ45_TX0+ D43 RJ45_TX0+ 1
TD4- MX4- LAN_LED1 1 LED1_LED3 PR1+
2 GND 14
LED2_LED3 1 R969 2 LINK_10_1000# 11
CH751H-40PT_SOD323-2 220_0402_5% Green LED-
BOTH_GST5009-LF LED1_LED3 1 R970 2 LINK_100_1000# 9
D44 220_0402_5% Orange LED-
LAN_LED3 1 2 +LAN_IO 10
A Green-Orange LED+ A
CH751H-40PT_SOD323-2
C-1775553
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM5787M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 22 of 49
5 4 3 2 1
A B C D E

Mini-Express Card---WLAN
http://laptopblue.vn
Roboson
0.01U_0402_16V7K~N
+3VS

0.01U_0402_16V7K~N
+1.5VS

4.7U_0805_10V4Z~N

1 1 1 1 1
C294 C321 C298 C312 C320

2 2
4.7U_0805_10V4Z~N 2 2 2

0.1U_0402_16V4Z~N

1 1
+1.5VS +3VS
+1.5VS +3VS

JMINI1
1 1 2 2
JMINI2 3 4
ICH_PCIE_WAKE# 3 4
19,28 ICH_PCIE_WAKE# 1 1 chan cho phep ic card wifi hoat dong (1) "chan nay phai luon o muc cao" 5 5 6 6
2 2 16 MCARD_REQ#E 1 2 ROB_REQE# 7 7 8 8 1 2 LPC_FRAME# 18,29
CH_DATA @ R380 1 0_0402_5%
2 MINI_PIN3 3 R279 0_0402_5% 9 10 R280 1 0_0402_5%
2 LPC_AD3
32 CH_DATA 3 9 10
4 16 CLK_PCIE_Rob# CLK_PCIE_Rob# 11 12 R282 1 0_0402_5%
2 LPC_AD2
CH_CLK 4 11 12
32 CH_CLK 2 MINI_PIN4
@ R381 1 0_0402_5% 5 5 16 CLK_PCIE_Rob
CLK_PCIE_Rob 13 13 14 14 R281 1 0_0402_5%
2 LPC_AD1
6 15 16 R283 1 0_0402_5%
2 LPC_AD0
MCARD_REQ#G 6 PLT_RST# 1 15 16 R287 0_0402_5%
16 MCARD_REQ#G 7 7 2 17 17 18 18 LPC_AD[0..3] 18,29
8 R444 0_0402_5% 19 20
8 16 CLK_DEBUG_PORT 19 20
9 R288 0_0402_5% 21 22
9 PCIE_RXN3 1 21 22 PLT_RST# 7,17,19,22,28,29,34
10 10 19 PCIE_RXN3 2PCIE_C_RXN3 23 23 24 24
11 19 PCIE_RXP3 PCIE_RXP3 1 2PCIE_C_RXP3 25 26
16 CLK_PCIE_MCARD# 11 25 26
12 R290 0_0402_5% 27 28
12 27 28
16 CLK_PCIE_MCARD 13 13 29 29 30 30
14 PCIE_TXN3 31 32
14 19 PCIE_TXN3 31 32
15 PCIE_TXP3 33 34
15 19 PCIE_TXP3 33 34
16 16 35 35 36 36
17 17 37 37 38 38
18 18 39 39 40 40
19 41 42 DISK_BUSY T23 PAD
WL_OFF# 19 41 42
29,32 WL_OFF# 20 20 chan cho phep bat song(1),(0) tat song 43 43 44 44
21 21 45 45 46 46
7,17,19,22,28,29,34 PLT_RST#
chan reset cho card wifi 22 22 47 47 48 48
19 PCIE_RXN4 PCIE_RXN4 1 2 PCIE_C_RXN4 23 49 50
R4032 23 49 50
+3VALW 10_0402_5% 24 24 51 51 52 52
2 PCIE_RXP4 R4061 2
19 PCIE_RXP4 20_0402_5% PCIE_C_RXP4 25 25
R404 0_0402_5% 26 53 54
26 GND1 GND2
27 27
+1.5VS 28 28
29 FOX_AS0B226-S52N-7F~N
29
13,14,16,19 ICH_SM_CLK 2 1 30 30
PCIE_TXN4 R373 0_0402_5% 31
19 PCIE_TXN4 31
13,14,16,19 ICH_SM_DA 2 1 32 32
PCIE_TXP4 R343 0_0402_5% 33
19 PCIE_TXP4 33
34 34
35 35
USB20_N4 36
19 USB20_N4 36
37 37
USB20_P4 38
19 USB20_P4 38
+3VS 39 39
40 40 Power status(Left)
41 41
PAD T61 LED_WWAN# 42 42 LED1
43 43
LED_WLAN# 44 12-21-BHC-ZL1M2RY-2C BLUE +5VALW
31 LED_WLAN# 44
45 45
46 PWR_BLUE_LED# 2 1 1 R472 2
46 +3VS 29,31 PWR_BLUE_LED#
47 47
+1.5VS 48 200_0603_5%
48 0.01U_0402_16V7K~N 4.7U_0805_10V4Z~N
49 49
50 50
51 51 1 1 1
+3VS 52 C500 C489 C456
52
53 LED2 +5VALW
GND1 2 2 2 BATT_LOW_LED#
54 GND2 29 BATT_LOW_LED# 3 Y
1 1 R471 2
3 FOX_AS0B246-S50U-7F 0.1U_0402_16V4Z~N BATT_CHG_LED# 3
29 BATT_CHG_LED# 2
B 200_0603_5%
12-22/Y2BHC-A30/2C_Y/B~D
+1.5VS

0.01U_0402_16V7K~N

1 1
C488

C485
2 2

0.01U_0402_16V7K~N

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 24 of 49
A B C D E
5 4 3 2 1

40mil 40mil
http://laptopblue.vn
HD Audio Codec
+AVDD_AC97

20mil
For EMI
0_0603_5%
L94 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2
+VDDA
FBM-L11-160808-800LMT_0603 1 1 1 R877 +3VS
C862 1 1 1
C860 C861
10U_1206_16V4Z C863 C864 C865
2 2 2 10U_1206_16V4Z
0.1U_0402_16V4Z 2 2 2

D 0.1U_0402_16V4Z D

25

38

9
U49
C867 1000P_0402_50V7K~N

DVDD_IO
DVDD
AVDD1

AVDD2
C869 1000P_0402_50V7K~N

14 (1) 35 LINEL 1 2
NC (4)LINE_OUT_L AMP_LEFT 26
R881 6.8K_0603_5%
15 36 LINER 1 2 AMP_RIGHT 26
NC (4)LINE_OUT_R R884 6.8K_0603_5% +VDDA
16 39 HP_LOUT 1 2
MIC2_L (4)HP_OUT_L R885 0_0603_5%
HP_LEFT 26

1
17 41 HP_ROUT 1 2 HP_RIGHT 26
MIC_SIG_R MIC2_R (4)HP_OUT_R R886 0_0603_5% R370
23 45 C872 1000P_0402_50V7K~N 10K_0402_5%
LINE1_L NC
24 46 C873 1000P_0402_50V7K~N
C301

2
LINE1_R DMIC_CLK
2
@ 18 43 1 2 MIC_CLK MIC_CLK 15 1 2
C527 CD_L NC R415 0_0402_5%
1 2

1
220P_0402_50V7K 20 44 C526 220P_0402_50V7K
1 CD_R NC R889 2 @ 1U_0603_10V4Z
1 2 @ R367
19 CD_GND
@
10_0402_5% C875 10P_0402_50V8J~N EC Beep 10K_0402_5%
6 1 2 C302
BIT_CLK ACZ_BITCLK 18 R368
1 2 C_MIC1 21 R890 0_0402_5% 1 2 1 2
26 MIC1 29 BEEP C308

2
C876 2.2U_0603_10V6K MIC1_L
1 2 C_MIC2 22 8 1 2 0_0402_5% R369 1U_0603_10V4Z 560_0402_5% 1 2 MONO_IN
26 MIC2
C877 2.2U_0603_10V6K MIC1_R (3)SDATA_IN R891
ADC_ACZ_SDIN0 18
1 2
C MONO_IN 12 37 C
PCBEEP MONO_OUT 1U_0603_10V4Z

1
47K_0402_5% C 1 2
29 2 Q21
LINE1_VREFO B R384
(2)18 ACZ_RST# 11 RESET#
31 E 2SC2411K_SC59 2.4K_0402_5%

3
GPIO1
SPK_SEL HIGH: HARMAN 10
LOW: NO-BRAND
(2)18 ACZ_SYNC SYNC
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
ICH Beep
5 C305
39.2K _0402_1% (2)18 ACZ_SDOUT SDATA_OUT R364
HP_JD 2 MIC_SIG1 2MIC_SIG_R 2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R 19 SB_SPKR 1 2 1 2
151 MIC_SIG GPIO0

1
R892 R412 0_0402_5% 3 30 R363 1U_0603_10V4Z 560_0402_5%
SENSE_A GPIO3 MIC2_VREFO D22
26 MIC_JD 1 2 13 SENSE A 1 2
R893 20K_0402_1% AC97_VREF R371
34 SENSE B VREF 27 10mil 1
47K_0402_5% 10K_0402_5%
CH751H-40PT SOD323

EAPD R894 2 1 47 40 C879

2
26 EAPD 0_0402_5% EAPD JDREF 10U_0805_10V4Z
2
48 SPDIFO NC 33

1
R505,R504 4 26 R895
DVSS1 AVSS1 20K_0402_1%
7 42
close to PIN13 DVSS2 AVSS2
ALC268-GR_LQFP48

2
close to CODEC
DGND AGND

2 1
Sense Pin Impedance Codec Signals
B R309 0_0402_5% B

39.2K PORT-A (PIN 39, 41)


+3VS
20K PORT-B (PIN 21, 22)
SENSE A Regulator for CODEC
2

10K PORT-C (PIN 23, 24)


2

R897
R898 Adjustable Output
100K_0402_5% HP_JD +5VS
100K_0402_5% 5.1K PORT-D (PIN 35, 36) R900 U50
1

@
1

D
1 2 1 5
1

@ PLUG_IN# Q68 VIN VOUT +VDDA


39.2K PORT-E (PIN 14, 15)

4.7U_0805_10V4Z

0.1U_0402_16V7K~N
26 PLUG_IN# 2
G SSM3K7002FU_SC70-3 10K_0603_1% 2 GND
S @
3

20K PORT-F (PIN 16, 17) C881 C882


3 SHDN# BP 4
SENSE B

0.1U_0402_16V7K~N
4.7U_0805_10V4Z~N
1

D RT9198-4GPBG SOT-23 5P 4.75V


26 PLUG_IN 2 Q69 10K PORT-G (PIN 43, 44) 1 1
G SSM3K7002FU_SC70-3
S @
3

5.1K PORT-H (PIN 45, 46) 2 2

C883

C884
A
Moat Bridge A

1 2
R902 0_0603_1%
1 2
R903 0_0603_1% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2006/08/05 Deciphered Date 2007/08/05 Title
R904
1
0_0603_1%
2
HD Audio Codec_ALC268
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R905 0_0603_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4231P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 25 of 49
5 4 3 2 1
A B C D E

Speaker Connector

1
W=40Mil
1
2
R293
http://laptopblue.vn
1 +5VS
1
D12
2
INTSPK_1 1
JSPK2

3
INTSPK_2 1 G1
0_0402_5% 3 2 2 G2 4
C318 C518 +5VS
0.1U_0402_16V4Z 10U_0805_10V4Z ACES_88266-0200
2 2 SM05T1G_SOT23-3~D
U20

16
15
6
R458 1 2 10K_0402_5% @

VDD
PVDD1
PVDD2
@ R460 1 2 10K_0402_5%

4
MICROPHONE IN JACK 4
C331 1 2 7 2 R461 1 2 10K_0402_5%
0.47U_0603_10V7K RIN+ GAIN0 3K_0402_5% R463 FOX_JA6333L-B3S0-7F~N
3 @ R459 1 2 10K_0402_5% 3K_0402_5%
2 R464
1 5
GAIN1 +MIC1_VREFO_R
2 1 +MIC1_VREFO_L
C521 1 2 AMP_R 17 25 MIC_JD 4 10
25 AMP_RIGHT RIN-
0.47U_0603_10V7K 18 SPK_1 1 2 INTSPK_1 9
ROUT+ R457 0_0603_5% MIC-2
25 MIC2 2 1 1 2 3 8
C522 1 2 AMP_L R310 0_0402_5% L34 CHB2012U170_0805 6 7
25 AMP_LEFT
0.47U_0603_10V7K 14 SPK_2 1 2 INTSPK_2 25 MIC1 2 1 1 2 MIC-1 2
ROUT- R456 0_0603_5% R311 0_0402_5% L35 CHB2012U170_0805
9 LIN+ 1
1 1
LOUT+ 4
C525 JMIC1
5 220P_0402_50V7K C524
LIN-

3
2 2 220P_0402_50V7K
LOUT- 8
D16
SM05T1G_SOT23-3~D
@
12

1
NC

BYPASS 10
R298 1 2 10K_0402_5% 19 SHUTDOWN
GNDA 2

GND1
GND2
GND3
GND4
C333
0.47U_0603_16V4Z
1 HEADPHONE OUT JACK
+3VS P3017THF B0 TSSOP 20P
21

20
13
11
1
1

3 FOX_JA6333L-B3S0-7F~N 3
R450 5
100K_0402_5%
@ 25 PLUG_IN PLUG_IN 4 10
9
2

HP_OUTR R301 1 2 47_0402_5%HP_R 1 2 HPR 3 8


D14 CH751H-40_SC76 L23 CHB2012U170_0805 6 7
2 1 R451 1 2 PLUG_IN GAIN0 GAIN1 GAIN HP_OUTL R300 1 2 47_0402_5%HP_L 1 2 HPL 2
L22 CHB2012U170_0805 1
2.7K_0402_5% 2 2
1

1
D
1K_0402_1%

@
1

2 Q43 @ 0 0 6dB C330 C329 JHP1


29 EC_MUTE 470P_0402_50V7K
G SSM3K7002FU_SC70-3 R299 R305 470P_0402_50V7K
1 1
100P_0402_50V8J

R449

S @ @ 1K_0402_5% @ 1K_0402_5%
3

3
1

2
C519 0 1 10dB
*
2

D23
EAPD

2 @
SM05T1G_SOT23-3~D
1 0 15.6dB

1
+3VS
Change to 100p from 0.01u for EMI +3VS
25
EAPD

-1012 1 1 21.6dB

5
U21 Reserve the 0 ohm resistor.

1
PLUG_IN# 2

P
25 PLUG_IN# B
4 HP_MUTE# R462 for voltage filtering
EAPD Y 0_0603_5%
1 A

G
MC74VHC1G08DFT2G SC70 5P 1 2

2
@ C523 1U_0603_10V4Z
2 2

19

10
U22

PVDD

SVDD
EC_MUTE 2 1 HP_MUTE# 14 11 HP_OUTR
R302 0_0402_5% SHDNR# OUTR
18 9 HP_OUTL
SHDNL# OUTL

R307 2.2K_0402_5% 4
NC-4
25 HP_RIGHT 1 2 HP_INR 1 2 HPINR 15 INR
C339 2.2U_0603_6.3V6K 6
NC-6
25 HP_LEFT 1 2 HP_INL 1 2 HPINL 13 INL
C338 2.2U_0603_6.3V6K 8
R306 2.2K_0402_5% NC-8

NC-12 12

1 C1P NC-16 16
1

PGND

SGND
3 20

PVss

SVss
C317 C1N NC-20
1U_0603_10V4Z
2 S IC TPA4411MRTJR QFN 20P

17
1
C316
1 1U_0603_10V4Z 1
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP/Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 26 of 49
A B C D E
5 4 3 2 1

Express card http://laptopblue.vn

D JEXP1 D
+1.5VS_PEC
Express Card Power Switch 4.7U_0805_10V4Z~N 1 GND
USB20_N5 R48 1 2 0_0402_5% USB20_N5_R2
19 USB20_N5 USB_D-
+1.5VS 1 1 USB20_P5 R47 1 2 0_0402_5% USB20_P5_R 3
U11 +1.5VS_PEC 19 USB20_P5 USB_D+
EXPR_CPUSB# 4
C90 C89 CPUSB#
2 1 12 1.5Vin 1.5Vout 11 5 RSV
C91 0.1U_0402_16V4Z~N 14 13 0.1U_0402_16V4Z~N 6
1.5Vin 1.5Vout 2 2 ICH_SMB_CLK RSV
+3VS 19 ICH_SMB_CLK 7 SMB_CLK
+3VS_PEC ICH_SMB_DATA 8
19 ICH_SMB_DATA SMB_DATA
2 1 2 3.3Vin 3.3Vout 3 +1.5VS_PEC 9 +1.5V
C74 0.1U_0402_16V4Z~N 4 5 10
3.3Vin 3.3Vout +3V_PEC +1.5VS_PEC +1.5V
+3VALW 19,24 ICH_PCIE_WAKE# 1 R37 2 PCIE_PME#_R 11 WAKE#
2 1 17 15 0_0402_5% 12
C85 0.1U_0402_16V4Z~N AUX_IN AUX_OUT +3V_PEC +3V_PEC PERST# +3.3VAUX
13 PERST#
PLT_RST# 6 19 4.7U_0805_10V4Z~N 14
7,17,19,22,24,29,34 PLT_RST# SYSRST# OC# +3VS_PEC +3.3V
15 +3.3V
SYSON 20 8 PERST# 16 EXPR_CARD_REQ# EXPR_CARD_REQ# 16
29,41,46 SYSON SHDN# PERST# CLKREQ#
1 1 CPUSB# 17
SUSP# CLK_PCIE_EXPR# CPPE#
29,41,46,47,48 SUSP# 1 STBY# NC 16 16 CLK_PCIE_EXPR# 18 REFCLK-
C92 C93 CLK_PCIE_EXPR 19
16 CLK_PCIE_EXPR REFCLK+
CPUSB# 10 7 0.1U_0402_16V4Z~N 20
CPPE# GND 2 2 PCIE_RXN2 GND
19 PCIE_RXN2 21 PERn0
EXPR_CPUSB# 9 19 PCIE_RXP2 PCIE_RXP2 22
CPUSB# PERp0
23 GND
18 PCIE_TXN2 24
RCLKEN +3VS_PEC 19 PCIE_TXN2 PETn0
PCIE_TXP2 25
19 PCIE_TXP2 PETp0
P2231NF_QFN20 4.7U_0805_10V4Z~N 26 GND
C +1.5V_CARD Max. 650mA, Average 500mA 27 C
GND
1 1 28 GND
+3V_CARD Max. 1300mA, Average 1000mA 29 GND
C75 C73 30
0.1U_0402_16V4Z~N GND
2 2 FOX_1CH4312C-TB_LB

CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXPRESS CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 28 of 49
5 4 3 2 1
L18
+3VALW +EC_AVCC 2 1
+EC_AVCC
1
+3VALW
2 FBM-11-160808-601-T_0603
Board ID +3VALW

+3VALW
1 1
http://laptopblue.vn
1 1 1 1
C481
1000P_0402_50V7K~N
C482
0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
C281

0.1U_0402_16V4Z~N
C285

0.1U_0402_16V4Z~N
C277

0.1U_0402_16V4Z~N
C493

1000P_0402_50V7K~N
C269

1000P_0402_50V7K~N
C291

2
ECAGND2 1
2 1 2007-09-19 change Brd ID
FBM-11-160808-601-T_0603 L19 R232

2
2 2 2 2 2 2
Ra 47K_0402_5%

R405

1
10K_0402_5% AD_BID
1

111
125

2
EC_PME#

22
33
96

67
9
U29 R231 C272
R414 @ 0_0402_5%
Rb 15K_0402_5% 0.1U_0402_16V4Z

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
40 CB_PME# 1 2 1 2

1
1 2 R266 0_0402_5%
22 PCIE_PME#
R413 0_0402_5% GATEA20 1 21 1 2
18 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 15
KB_RST# 2 23 BEEP M/B rev:0.1; 0.2; 0.3; 1.0
18 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP 25
SERIRQ 3 26 W_DISABLE# W_DISABLE# 32
19 SERIRQ SERIRQ# FANPWM1/GPIO12 Voltage:0.0; 0.4; 0.8; 1.0
LPC_FRAME# 4 27 ACOFF
18,24 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 44
LPC_AD3 5
18,24 LPC_AD3 LAD3
LPC_AD2 7 PWM Output C273 1 2 0.01U_0402_16V7K ECAGND
18,24
18,24
LPC_AD2
LPC_AD1
LPC_AD1
LPC_AD0
8
LAD2
LAD1 BATT_TEMP/AD0/GPIO38 63 BATT_TEMP
BATT_OVP
BATT_TEMP 50 SPI Flash connect
18,24 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 50 JBIOS1
ADP_I/AD2/GPIO3A 65 ADP_I 44
CLK_PCI_EC 12 AD Input 66 AD_BID SPI_CS# 1 2 +3VALW
16 CLK_PCI_EC PCICLK AD3/GPIO3B 1 2
CLK_PCI_EC R228 PLT_RST# 13 75 MIC_DIAG SPI_SO 3 4
7,17,19,22,24,28,34 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 MIC_DIAG 15 3 4
1 2 EC_RST# 37 76 VGA_THER +3VALW 5 6 SPI_CLK_R
+3VALW ECRST# 2 SELIO2#/AD5/GPIO43 VGA_THER 34 5 6
1

EC_SCI# 20 7 8 SPI_SI
19 EC_SCI# SCI#/GPIO0E 7 8
R272 47K_0402_5% PCI_CLKRUN# 38
19,40 PCI_CLKRUN# CLKRUN#/GPIO1D
2 68 DAC_BRIG E&T_2941-G08N-00E~D
DAC_BRIG/DA0/GPIO3C DAC_BRIG 15
@ 10_0402_5% C268 70 EN_DFAN1 ME@
KSI[0..7] EN_DFAN1/DA1/GPIO3D EN_DFAN1 4
0.1U_0402_16V4Z DA Output 71 IREF
31 KSI[0..7] IREF 44
2

KSI0 IREF/DA2/GPIO3E M_PWROK_EC 1


1 55 KSI0/GPIO30 DA3/GPIO3F 72 2 CHGVADJ 44
@ C282 1 KSO[0..15] KSI1 R256 0_0402_5%
31 KSO[0..15] 56 KSI1/GPIO31
KSI2 57
15P_0402_50V8J KSI3 KSI2/GPIO32 EC_MUTE
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE 26
2 KSI4 LCD_TST
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 LCD_TST 15
KSI5 60 85 VGA_ON
KSI5/GPIO35 PSCLK2/GPIO4C VGA_ON 47
KSI6 61 PS2 Interface 86 LCD_CBL_DET#
KSI6/GPIO36 PSDAT2/GPIO4D LCD_CBL_DET# 15
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 31
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 31
KSO1 40

+5VALW
KSO2
KSO3
KSO4
41
42
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23 SDICS#/GPXOA00 97 SPI_PULLDOWN 2 R274
EN_WOL#
1 4.7K_0402_5%
SPI Flash (8Mb*1) @ C507
43 KSO4/GPIO24 SDICLK/GPXOA01 98 EN_WOL# 22
EC_SMB_DA1 R263 2 1 4.7K_0402_5% KSO5 2SPI_CLK_R
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
VGATE
1
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 7,19,49
EC_SMB_CK1 R262 2 1 4.7K_0402_5% KSO7 46 SPI Device Interface 0.1U_0402_16V4Z~N
KSO8 KSO7/GPIO27 +3VALW
47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO C314
+3VS KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI 20mils
49 120 1 2

EC_SMB_DA2 R264 2 1 4.7K_0402_5%


KSO11
KSO12
50
51
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
SPI Flash ROM 3 SPIDO/WR#
SPICLK/GPIO58
SPICS#
126
128
SPI_CLK
FSEL#SPICS# 0.1U_0402_16V4Z~N
2 R437 1
10K_0402_5%
KSO13 52 U37
EC_SMB_CK2 KSO14 KSO13/GPIO2D FSEL#SPICS# 2
R265 2 1 4.7K_0402_5% 53 KSO14/GPIO2E 1SPI_CS# 1 CS# VCC 8
KSO15 54 73 TOUCHKEY_TINT R439 15_0402_5% 2 7
KSO15/GPIO2F CIR_RX/GPIO40 TOUCHKEY_TINT 31 DO HOLD#
LCD_TST @ R269 2 1 4.7K_0402_5% BT_OFF# 81 74 MSEN# FRD#SPI_SO 1 2SPI_SO 3 6 SPI_CLK_R 1 2 SPI_CLK
BT_OFF# KSO16/GPIO48 CIR_RLC_TX/GPIO41 MSEN# 15 WP# CLK
82 89 FSTCHG 15_0402_5% R275 4 5 15_0402_5% R420
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 44 GND DIO
LCD_CBL_DET# R276 2 1 4.7K_0402_5% 90 BATT_CHG_LED# SPI_SI 1 2 FWR#SPI_SI
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# 24
91 CAPSLED# W25X80-VSSI-G_SO8 15_0402_5% R438
CAPS_LED#/GPIO53 CAPSLED# 31
MIC_DIAG R308 1 2 10K_0402_5% EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED#
50 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_LOW_LED# 24
EC_SMB_DA1 78 93 SCRLED#
50 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 SCRLED# 31
EC_FB_SDATA_R R303 2 1 4.7K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
4,31,35 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 28,41,46
4,31,35 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 49
EC_FB_SCLK_R R304 2 1 4.7K_0402_5% 127 ACIN
6 AC_IN/GPIO59 ACIN 19,43,44
For ENE
SLP_S3# 6
(8') 100 EC_RSMRST#
19 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 19
SLP_S5# 14 101 EC_LID_OUT#
+5VS 19 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 19
EC_SMI# 15 102 EC_ON
R271
19 EC_SMI#
LID_SW# EC_SMI#/GPIO08 (7')EC_ON/GPXO05 EC_SWI#
EC_ON 31
16 LID_SW#/GPIO0A 5 EC_SWI#/GPXO06 103 EC_SWI# 19
10K_0402_5% R416 1 2 0_0402_5% EC_FB_SCLK_R 17 104 ICH_PWROK
31 EC_FB_SCLK SUSP#/GPIO0B ICH_PWROK/GPXO06
TP_DATA 1 2 31 EC_FB_SDATA R417 1 2 0_0402_5% EC_FB_SDATA_R 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 15
TP_CLK 1 2 EC_PME# 19 GPIO 106 WL_OFF#
17 EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 24,32
10K_0402_5% 19 LAN_WOL_EN LAN_WOL_EN 25 107 LCD_VCC_TEST_EN
R270 FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 PSID_DISABLE# LCD_VCC_TEST_EN 15
4 FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 PSID_DISABLE# 43
29 FANFB2/GPIO15
+3VALW EC_TX_P80_DATA 30
PAD T56 EC_TX/GPIO16
PAD T57 EC_RX_P80_CLK 31 110 SLP_S4# SLP_S4# 19
ON_OFF EC_RX/GPIO17 PM_SLP_S4#/GPXID1 EC_ENBKL
31 ON_OFF 32 ON_OFF/GPIO187 ENBKL/GPXID2 112 EC_ENBKL 15
PWR_BLUE_LED# 34 114 USB_EN USB_EN 32
24,31 PWR_BLUE_LED# PWR_LED#/GPIO19 GPXID3
EC_MUTE 1 2 NUMLED# 36 GPI 115 EC_THERM#
31 NUMLED# NUMLED#/GPIO1A GPXID4 EC_THERM# 4,19
10K_0402_5% 116 SUSP#
GPXID5 SUSP# 28,41,46,47,48
R277 117 PBTN_OUT#
GPXID6 PBTN_OUT# 19
XCLKO 1 R278 2 XCLKI 118 PS_ID
@ 20M_0603_5% XCLKI GPXID7 PS_ID 43
122 XCLK1
XCLKO 123 XCLK0
4 V18R 124 C322 1 2 4.7U_0603_6.3V
AGND

0.1U_0402_16V4Z
GND
GND
GND
GND
GND

C292 C297 KB926QFA1_LQFP128


C270 2 1
TPM 1.2 Conn
11
24
35
94
113

69
1

4
15P_0402_50V8J

15P_0402_50V8J

JTPM1
IN

OUT

LPC_FRAME# 1 2 LPC_AD0
ECAGND GND1 RES0 LPC_AD1
7,17,19,22,24,28,34 PLT_RST# 3 IAC_SDATA_OUT RES1 4
SERIRQ 5 6 LPC_AD2
PCI_CLKRUN# GND2 3.3V LPC_AD3
NC

NC

7 IAC_SYNC GND3 8
+3VS 12mA 9 10 CLK_PCI_TPM 16
IAC_SDATA_IN GND4
+3VALW 11 12
2

IAC_RESET# IAC_BITCLK
X2 ICH_PWROK 1 2 PM_PWROK 7,19
R408 0_0402_5%

GND
GND
GND
GND
GND
GND
32.768KHZ_12.5P_1TJS125BJ2A251 VGATE 1 2
@ R407 0_0402_5%
ACES_88018-124L

13
14
15
16
17
18
+3VALW
U1
APX9132ATI-TRL_SOT23-3

LID_SW# 3 2
GND

VOUT VDD
Security Classification Compal Secret Data Compal
0.5A per each pinElectronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Size Document Number Rev
REED Switch AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 29 of 49
A B C D E

INT_KBD CONN.
Power Button
+3VALW http://laptopblue.vn 29

29
KSI[0..7]

KSO[0..15]
KSI[0..7]

KSO[0..15]
KSI0
KSI1
KSI2
1
2
3
JKB1

1
2
KSO8

KSI3

KSO9
C449

C239

C249
100P_0402_25V8K

100P_0402_25V8K

100P_0402_25V8K
KSI7

KSI6

KSI5
C235

C236

C237
100P_0402_25V8K

100P_0402_25V8K

100P_0402_25V8K
3

100K_0402_5%
KSI3 4
KSI4 4 KSI2 C240 100P_0402_25V8K KSO0 C441 100P_0402_25V8K
5 5

R297
KSI5 6
KSI6 6 KSI1 C241 100P_0402_25V8K KSO1 C442 100P_0402_25V8K
7 7
KSI7 8

1
D15 KSO0 8 KSO10 C248 100P_0402_25V8K KSO2 C443 100P_0402_25V8K
9 9
2 KSO1 10
ON_OFF 29 10
PWR_ON-OFF_BTN# 1 KSO2 11 KSO11 C247 100P_0402_25V8K KSI4 C238 100P_0402_25V8K
51ON# KSO3 11
3 51ON# 43 12 12
1 KSO4 KSI0 C242 100P_0402_25V8K KSO3 C444 100P_0402_25V8K 1
13 13
CHN202UPT SC-70 KSO5 14
KSO6 14 KSO12 C246 100P_0402_25V8K KSO4 C445 100P_0402_25V8K
15 15
+3VALW KSO7 16 16

1
2 KSO8 17 KSO13 C245 100P_0402_25V8K KSO5 C446 100P_0402_25V8K
KSO9 17
18 18
2

C313 D13 KSO10 19 KSO14 C244 100P_0402_25V8K KSO6 C447 100P_0402_25V8K


R296 1000P_0402_50V7K~N RLZ20A_LL34 KSO11 19
20 20
4.7K_0402_5% 1 KSO12 KSO15 C243 100P_0402_25V8K KSO7 C448 100P_0402_25V8K
21

2
@ KSO13 21
22 22

1
D KSO14 23
1

EC_ON KSO15 23
1 2 2 24
29 EC_ON
R291 G Q26 25
24
25
For EMI
0_0402_5% S SSM3K7002FU_SC70-3 26
3
26

27 GND1
28 GND2

ACES_88514-2601

Function/B CONN.

For ENE C324 1 2 4.7U_0603_6.3V


2
1 2 +3VS_FUN 2
29 EC_FB_SDATA +3VS
R611 0_0402_5%
Regulator for ENE sensor 29 EC_FB_SCLK 1
R612
2
0_0402_5%
0_0603_5%
@ 1 2 1
JFN1

R880 IDE_ACT_LED# 1
2 2
+3VALW 3 3
Adjustable Output PWR_ON-OFF_BTN# 4
+5VS LED_WLAN# 4
R901 24 LED_WLAN# 5 5
RT9198-33PBR SOT-23 5P 1 @ 2 0_0402_5% FB_SDATA 6
4,29,35 EC_SMB_DA2 6
1 2 3 4 R617
1 2 0_0402_5% FN_SCLK 7
SHDN# BP +3VS_FUN 4,29,35 EC_SMB_CK2 7
R618 @ 8
10K_0603_1% BLUETOOTH_LED# 8
2 32 BLUETOOTH_LED# 9
1U_0402_6.3V4Z

GND For Cypress 9


10 10
1 1 5 PWR_BLUE_LED# 11
VIN VOUT 24,29 PWR_BLUE_LED# 11
C250

29 TOUCHKEY_TINT TOUCHKEY_TINT 1 2 12
NUMLED# R606 0_0402_5% 12
U54 29 NUMLED# 13 13
CAPSLED# 14
2 29 CAPSLED# 14
SCRLED# 15
29 SCRLED# 15
16 16
17 GND

680P_0603_50V8J

680P_0603_50V8J
18 GND
+3VS
ACES_88512-1641

1
C287

C286
@ C55
2 1
0.1U_0402_16V4Z

2
5
U33 @ @
SATA_LED# 2

P
18 SATA_LED# B
4 IDE_ACT_LED#
ODD_ACT_LED# 1 Y
21 ODD_ACT_LED# A

G
MC74VHC1G08DFT2G SC70 5P

3
3 3

1 2
R622 0_0402_5%
@

Touch PAD/B CONN.


TP/B TO M/B ACES_88514-0441
+5VS
6 G2
5 G1
4 4
1 TP_CLK 3
29 TP_CLK 3
TP_DATA 2
29 TP_DATA 2
C300 1
0.01U_0402_16V7K 1
2 1 1
@ @ JP1

C309

100P_0402_25V8K C310

3
2 2
D24

100P_0402_25V8K
SM05T1G_SOT23-3~D
@

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/BTN/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 31 of 49
A B C D E
+5VALW http://laptopblue.vn
+USB_AS

1
0.1U_0402_16V4Z
@ L1 WCM2012F2S-900T04_0805
U12 USB20_P0 1 1
80 mils 19 USB20_P0 2 2

1
1 8 + C434 C223 USB_P0
GND OUT R155 USB_N0
2 IN OUT 7
3 6 150U_B2_6.3VM_R45M 30K_0402_5% USB20_N0 4 3
IN OUT 2 19 USB20_N0 4 3
1 USB_EN# 4 5 JUSBP2
C228 EN# OC#
1

1 2
RT9711PS SO 8P GND
D 2 1 2 D+
0.1U_0402_16V4Z R1 0_0402_5% 3
2 SUSP Q14 D-
2 2 1 +USB_AS W=60mils 4 VCC
G SSM3K7002FU_SC70-3 R3 0_0402_5%

1
USB_OC#0 19 S 5

3
R154 GND1
6 GND2
100K_0402_5% 7
@ GND3
8 GND4

2
ALLTO_C10797-10403-L

+USB_CS
+5VALW

U14
80 mils 1 GND OUT 8
2 IN OUT 7
3 IN OUT 6

1
1 USB_EN# 4 5
C253 EN# OC# R38
RT9711PS SO 8P 30K_0402_5%
0.1U_0402_16V4Z
2

2
USB_OC#3 19
1 2 USB_OC#2 19
R44 0_0402_5%

1
D
40,41,48 SUSP SUSP 2 Q13
G SSM3K7002FU_SC70-3
S

3
+USB_BS
+5VALW

U13
80 mils 1 GND OUT 8
2 IN OUT 7
3 IN OUT 6
1 USB_EN# 4 5
C64 EN# OC#
CM1293-04SO_SOT23-6

1
RT9711PS SO 8P
0.1U_0402_16V4Z R36 1 4 USB_P0
2 30K_0402_5% CH1 CH4

USB_OC#1 19

2
2 Vn Vp 5 +USB_AS
CM1293-04SO_SOT23-6 Daughter board on right side CONN@
1 4 USB20_N6 3 6 USB_N0 ACES_87213-1200G
CH1 CH4 CH2 CH3

1
D
14 GND2
SUSP 2 Q8 @ D19 +USB_CS 13
G SSM3K7002FU_SC70-3 GND1
2 5 +3VS S W=80mils

3
Vn Vp
12 12
19 USB20_N1 11 11
19 USB20_P1 10 10
3 6 USB20_P6 9
Fingerprint CH2 CH3
8
9
JFP1 @ D21 8
19 USB20_N2 7 7
19 USB20_N6 1 1 19 USB20_P2 6 6
19 USB20_P6 2 2 5 5
3 3 19 USB20_N3 4 4
+3VS 4 4 W=60mils 19 USB20_P3 3 3
5 5 +USB_BS 2 2
6 6 1 1
29 W_DISABLE#
7
8
GND Bluetooth JP3
GND
ACES_88512-0641 JBT1
1 1
19 USB20_P7 2 2
19 USB20_N7 3 3
PAD T62 BT_ACTIVE 4 4
Felica Conn 24 CH_CLK
BT_OFF#
5
6
5
BT_OFF# 6
24 CH_DATA 7 7
+3VS 8 8
ACES_88512-0641 9
+5VS 31 BLUETOOTH_LED# 9
8 GND 10 10
7 GND 11 GND
6 6 12 GND
USB20_N9 5
19 USB20_N9 5 +5VALW
USB20_P9 4 ACES_88460-1001
19 USB20_P9 4
3 3
TP1 LEC 2 2
2

1 1
1 R222
JFE1 10K_0402_5%

C315
1

10U_0805_10V4Z 2 USB_EN#
1

D
29 USB_EN USB_EN 2 Q4
G SSM3K7002FU_SC70-3
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BlueTooth/FP/Felcia
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 32 of 49
5 4 3 2 1

9 PEG_NRX_GTX_P[0..15]

9 PEG_NRX_GTX_N[0..15]
PEG_NRX_GTX_P[0..15]

PEG_NRX_GTX_N[0..15]
PEG_NTX_GRX_P0 AF1
http://laptopblue.vn
U38A

Part 1 of 5 A9
HDMI
PEG_NTX_GRX_N0 PEX_RX0 GPIO0
AG2 PEX_RX0_N GPIO1 D9
PEG_NTX_GRX_P[0..15] PEG_NTX_GRX_P1 AG3 A10 NV_INVTPWM
9 PEG_NTX_GRX_P[0..15] PEX_RX1 GPIO2 PAD T52
PEG_NTX_GRX_N1 AG4 B10 VGA_LVDDEN VGA_LVDDEN 15
PEG_NTX_GRX_N[0..15] PEG_NTX_GRX_P2 PEX_RX1_N GPIO3 G7X_ENBKL
9 PEG_NTX_GRX_N[0..15] AF4 PEX_RX2 GPIO4 C10 G7X_ENBKL 15
PEG_NTX_GRX_N2 AF5 C12
PEG_NTX_GRX_P3 PEX_RX2_N GPIO5 VGA@ R534 1
AG6 PEX_RX3 GPIO6 B12 2 2K_0402_5% +3VS
PEG_NTX_GRX_N3 AG7 A12
PEG_NTX_GRX_P4 PEX_RX3_N GPIO7 THER_ALERT# For Internal Thermal
AF7 PEX_RX4 GPIO8 A13 THER_ALERT# Sensor
PEG_NTX_GRX_N4 AF8 B13 VGA_THER
D PEX_RX4_N GPIO9 VGA_THER 29 D
PEG_NTX_GRX_P5 AG9 B15 R542 2 1 +3VS
PEG_NTX_GRX_N5 PEX_RX5 GPIO10 VGA@ 10K_0402_5%
AG10 PEX_RX5_N GPIO11 A15
PEG_NTX_GRX_P6 AF10 B16
PEG_NTX_GRX_N6 PEX_RX6 GPIO12
AF11 PEX_RX6_N
PEG_NTX_GRX_P7 AG12
PEG_NTX_GRX_N7 PEX_RX7 RAM_CFG0
AG13 PEX_RX7_N MIOBD0 G2 RAM_CFG0 37

DVO / GPIO
PEG_NTX_GRX_P8 AG15 G3 RAM_CFG1
PEX_RX8 MIOBD1 RAM_CFG1 37
PEG_NTX_GRX_N8 AG16 J2
PEG_NTX_GRX_P9 PEX_RX8_N MIOBD2 PCI_DEVID2
AF16 PEX_RX9 MIOBD3 J1 PCI_DEVID2 37
PEG_NTX_GRX_N9 AF17 K4 PCI_DEVID0
PEX_RX9_N MIOBD4 PCI_DEVID0 37
PEG_NTX_GRX_P10 AG18 K1 PCI_DEVID1
PEX_RX10 MIOBD5 PCI_DEVID1 37
PEG_NTX_GRX_N10 AG19 M2
PEG_NTX_GRX_P11 PEX_RX10_N MIOBD6 PCI_IOBAR R535 1 @ 2.2K_0402_5%
AF19 PEX_RX11 MIOBD7 M1 2
PEG_NTX_GRX_N11 AF20 N1 RAM_CFG2
PEX_RX11_N MIOBD8 RAM_CFG2 37
PEG_NTX_GRX_P12 AG21 N2 RAM_CFG3
PEX_RX12 MIOBD9 RAM_CFG3 37
PEG_NTX_GRX_N12 AG22 N3
PEG_NTX_GRX_P13 PEX_RX12_N MIOBD10 PCI_DEVID3
AF22 PEX_RX13 MIOBD11 R3 PCI_DEVID3 37
PEG_NTX_GRX_N13 AF23
PEG_NTX_GRX_P14 PEX_RX13_N PEX_CFG3
AG24 PEX_RX14 MIOB_HSYNC G4 PEX_CFG3 37
PEG_NTX_GRX_N14 AG25 F1
PEG_NTX_GRX_P15 PEX_RX14_N MIOB_VSYNC VGA termination, close chip
AG26 G1

PCI EXPRESS
PEX_RX15 MIOB_DE
PEG_NTX_GRX_N15 AF27 PEX_RX15_N MIOB_CTL3 F2 PCI_DEVID4
PCI_DEVID4 37 PCI_IOBAR NB8M
PEG_NRX_GTX_P0 C581 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P0 AD5 R2 R537 2 1 10K_0402_5% VGA_CRT_R R539 1 2 VGA@ 150_0402_1%
PEG_NRX_GTX_N0 C582 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N0 PEX_TX0 MIOB_CLKIN VGA@ VGA_CRT_G R540 1
1 2 AD6 PEX_TX0_N MIOB_CLKOUT K2 2 VGA@ 150_0402_1% 0 Disable
PEG_NRX_GTX_P1 C583 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P1 AE6 K3 VGA_CRT_B R541 1 2 VGA@ 150_0402_1%
PEG_NRX_GTX_N1 C584 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N1 PEX_TX1 MIOB_CLKOUT_N
1 2 AE7 PEX_TX1_N
PEG_NRX_GTX_P2 C585 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P2 AD7 J4 1 Enable(Default)
PEG_NRX_GTX_N2 C586 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N2 PEX_TX2 MIOB_VREF
1 2 AC7 PEX_TX2_N
PEG_NRX_GTX_P3 C587 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P3 AE9
PEG_NRX_GTX_N3 C588 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N3 PEX_TX3 VGA_HSYNC
1 2 AE10 PEX_TX3_N DACA_HSYNC AD4 VGA_HSYNC 15
PEG_NRX_GTX_P4 C589 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P4 AD10 AC4 VGA_VSYNC +3VS BAR2_SIZE NB8M
C PEX_TX4 DACA_VSYNC VGA_VSYNC 15 C
PEG_NRX_GTX_N4 C590 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N4 AC10 AE1 VGA_CRT_R VGA_CRT_R 15
PEG_NRX_GTX_P5 C591 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P5 PEX_TX4_N DACA_RED VGA_CRT_B R142 VGA@
1 2 AE12 PEX_TX5 DACA_BLUE AD2 VGA_CRT_B 15
PEG_NRX_GTX_N5 C592 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N5 AE13 AD1 VGA_CRT_G VGA_CRT_G 15 VGA_CLK_LCD 1 2 0 32Mb(Default)
PEG_NRX_GTX_P6 C593 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P6 PEX_TX5_N DACA_GREEN
1 2 AD13 PEX_TX6 DACA_IDUMP U9
PEG_NRX_GTX_N6 C594 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N6 AC13 AD3 DACA_RSET R538 1 2 124_0603_1% 2.2K_0402_5%
PEG_NRX_GTX_P7 C595 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P7 PEX_TX6_N DACA_RSET VGA@
1 2 AC15 PEX_TX7 1 16Mb
PEG_NRX_GTX_N7 C596 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N7 AD15 AB4 DACAVREF 1 2 R273 VGA@
PEG_NRX_GTX_P8 C598 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P8 PEX_TX7_N DACA_VREF C597 0.01U_0402_16V7K VGA_DAT_LCD
1 2 AE15 PEX_TX8 1 2
PEG_NRX_GTX_N8 C599 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N8 AE16 VGA@
PEG_NRX_GTX_P9 C600 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P9 PEX_TX8_N 2.2K_0402_5%
1 2 AC18 PEX_TX9 DACB_HSYNC E6
PEG_NRX_GTX_N9 C601 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N9 AD18 F5
PEX_TX9_N DACB_VSYNC

DACs
PEG_NRX_GTX_P10 C602 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P10 AE18 F4
PEG_NRX_GTX_N10 C603 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N10 PEX_TX10 DACB_RED +3VS
1 2 AE19 PEX_TX10_N DACB_BLUE D5
PEG_NRX_GTX_P11 C604 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P11 AC21 E4 R284
PEG_NRX_GTX_N11 C605 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N11 PEX_TX11 DACB_GREEN R656 2
1 2 AD21 PEX_TX11_N DACB_IDUMP L9 1 10K_0402_5% VGA@ 2.2K_0402_5% VGA@
PEG_NRX_GTX_P12 C606 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P12 AE21 D6 R648 2 1 10K_0402_5% VGA@ I2CB_SCL 1 2
PEG_NRX_GTX_N12 C607 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N12 PEX_TX12 DACB_RSET
1 2 AE22 PEX_TX12_N
PEG_NRX_GTX_P13 C608 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P13 AD22 E7 R649 2 1 10K_0402_5% VGA@
PEG_NRX_GTX_N13 C609 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N13 PEX_TX13 DACB_VREF I2CB_SDA
1 2 AD23 PEX_TX13_N 1 2
PEG_NRX_GTX_P14 C610 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P14 AF25 2.2K_0402_5%
PEG_NRX_GTX_N14 C611 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N14 PEX_TX14 VGA_DDCCLK R285 VGA@
1 2 AE25 PEX_TX14_N I2CA_SCL D10 VGA_DDCCLK 15 <---CRT
PEG_NRX_GTX_P15 C612 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P15 AE24 E10 VGA_DDCDATA VGA_DDCDATA 15
PEG_NRX_GTX_N15 C613 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N15 PEX_TX15 I2CA_SDA I2CB_SCL
1 2 AD24 PEX_TX15_N I2CB_SCL F9
F10 I2CB_SDA
CLK_PCIE_VGA I2CB_SDA VGA_CLK_LCD
AE3 E9
I2C

16 CLK_PCIE_VGA PEX_REFCLK I2CC_SCL VGA_CLK_LCD 15


16 CLK_PCIE_VGA# CLK_PCIE_VGA# AE4 D8 VGA_DAT_LCD VGA_DAT_LCD 15 <---LVDS
PEX_REFCLK_N I2CC_SDA +3VS
7,17,19,22,24,28,29 PLT_RST# PLT_RST# AC6
I2CH_SCL C7
B7
External Spread Spectrum
PEX_RST_N I2CH_SDA C618 1
HDCP 2 0.1U_0402_16V4Z
VGA@
U42
N6 IFPAB_VPROBE 2 1 C614 7 VDD
B IFPAB_VPROBE 0.01U_0402_16V7K @ REF 5 VGA@ B
IFPCD_VPROBE M5
IFPCD_VPROBE 2 1 C615 OSC_OUT 1 4 1 2 OSC_SPREAD
XTALIN 0.01U_0402_16V7K @ XIN MODOUT R554 22_0402_5%
B1 XTALIN
JTAG_TCK AE27 PAD TP56 8 XOUT NC 3
JTAG_TDI AD27 PAD TP55
CLK

JTAG_TDO AE26 PAD TP54 2 VSS PD# 6


TEST

XTALOUT C2 AD26 PAD TP53


XTALOUT JTAG_TMS ASM3P1819N-SR_SO8
JTAG_TRST_N AD25 PAD TP52
C3 D7 10K_0402_5% VGA@
2 1 R549 VGA@
XTALOUTBUFF TESTMODE
R616
Y5 AF13
PEX_TSTCLK_OUT
4 GND OUT 3 C1 XTALSSIN PEX_TSTCLK_OUT_N AF14 1 2

1 2 @ 200_0402_5%
IN GND
27MHZ_16PF_X7T027000BG1H-V~D G72M_BGA533 VGA@
1 VGA@ 1
C616 C617 R550 OSC_SPREAD
1 VGA@2 OSC_OUT
18P_0402_50V8J 18P_0402_50V8J 22_0402_5%
1

2 2 VGA@
VGA@ R552 R553

10K_0402_5% 10K_0402_5%
@
2

If External Spread Spectrum not stuff than stuff resistor

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS Main
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 34 of 49

5 4 3 2 1
5 4 3 2 1

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FBAD[0..63]
FBAD[0..63] 38

FBAA[0..11]
FBAA[0..11] 38
D D
FBBA[2..5]
FBBA[2..5] 38

FBADQS[0..7]
FBADQS[0..7] 38

FBADQS#[0..7]
FBADQS#[0..7] 38

FBADQM#[0..7]
FBADQM#[0..7] 38

U38B
FBAD0 A26 G27 FBAA3 U38C
FBAD1 FBAD0 Part 2 of 5 FBA_CMD0 FBAA0 VGA_LVDSAC+ PEX_PLL_TERM
C24 FBAD1 FBA_CMD1 D25 15 VGA_LVDSAC+ T4 IFPA_TXC MIO_A_D0 A2 PEX_PLL_TERM 37
FBAD2 B24 F26 FBAA2 15 VGA_LVDSAC- VGA_LVDSAC- U4 Part 3 of 5 B3 SUB_VENDOR
FBAD2 FBA_CMD2 IFPA_TXC_N MIO_A_D1 SUB_VENDOR 37
FBAD3 A24 F25 FBAA1 15 VGA_LVDSA0+ VGA_LVDSA0+ N4 A3
FBAD4 FBAD3 FBA_CMD3 FBBA3 VGA_LVDSA0- IFPA_TXD0 MIO_A_D2
C22 FBAD4 FBA_CMD4 G25 15 VGA_LVDSA0- N5 IFPA_TXD0_N MIO_A_D3 D4
FBAD5 A25 J25 FBBA4 15 VGA_LVDSA1+ VGA_LVDSA1+ R5 A4
FBAD6 FBAD5 FBA_CMD5 FBBA5 VGA_LVDSA1- IFPA_TXD1 MIO_A_D4
B25 FBAD6 FBA_CMD6 J27 15 VGA_LVDSA1- R4 IFPA_TXD1_N MIO_A_D5 B4
FBAD7 D23 M26 FBA_BA2 15 VGA_LVDSA2+ VGA_LVDSA2+ T5 B6 PEX_CFG0
FBAD7 FBA_CMD7 FBA_BA2 38 IFPA_TXD2 MIO_A_D6 PEX_CFG0 37
FBAD8 G22 C27 FBACS0# 15 VGA_LVDSA2- VGA_LVDSA2- T6 P4
FBAD8 FBA_CMD8 FBACS0# 38 IFPA_TXD2_N MIO_A_D7
FBAD9 J23 C25 FBAWE# R6 C6 PEX_CFG1
FBAD9 FBA_CMD9 FBAWE# 38 IFPA_TXD3 MIO_A_D8 PEX_CFG1 37
FBAD10 E24 D24 FBA_BA0 P6 G5 PEX_CFG2
FBAD10 FBA_CMD10 FBA_BA0 38 IFPA_TXD3_N MIO_A_D9 PEX_CFG2 37
FBAD11 F23 N27 FBA_CKE W5 V4
FBAD11 FBA_CMD11 FBA_CKE 38 IFPB_TXC MIO_A_D10
FBAD12 J24 G24 FBA_RST_R
R560 1 2 FBA_RST W6 C4 SLOT_CLOCK_CFG R5611 2 VGA@ 2K_0402_5%

NC
FBAD12 FBA_CMD12 FBA_RST 38 IFPB_TXC_N MIO_A_HSYNC

1
FBAD13 F24 J26 FBBA2 VGA@ 0_0402_5% W3 F11 EC_SMB_DA2 EC_SMB_DA2 4,29,31
FBAD14 FBAD13 FBA_CMD13 CMD14 R571 R562 IFPB_TXD4 I2CS_SDA
G23 FBAD14 FBA_CMD14 M27 PAD T54 W2 IFPB_TXD4_N I2CS_SCL F12 EC_SMB_CK2 EC_SMB_CK2 4,29,31
FBAD15 H24 C26 FBARAS# 10K_0402_5% 10K_0402_5% AA2 D12
FBAD15 FBA_CMD15 FBARAS# 38 IFPB_TXD5 NC_2
FBAD16 D16 M25 FBAA11 VGA@ VGA@ AA3 E12
FBAD16 FBA_CMD16 IFPB_TXD5_N GPIO14 +3VS

LVDS/TMDS
C FBAD17 FBAA10 C
E16 D26 AB1 C13

2
FBAD18 FBAD17 FBA_CMD17 FBA_BA1 IFPB_TXD6 GPIO13
D17 FBAD18 FBA_CMD18 D27 FBA_BA1 38 AA1 IFPB_TXD6_N
FBAD19 F18 K26 FBAA8 AB3 F6 1
FBAD20 FBAD19 FBA_CMD19 FBAA9 IFPB_TXD7 MIO_A_VDDQ_0 C621
E19 FBAD20 FBA_CMD20 K25 AB2 IFPB_TXD7_N MIO_A_VDDQ_1 G6
FBAD21 E18 K24 FBAA6 J6 VGA@
FBAD22 FBAD21 FBA_CMD21 FBAA5 R564 1 MIO_A_VDDQ_2
D20 FBAD22 FBA_CMD22 F27 2 @ 1K_0402_5% U6 IFPAB_RSET
0.1U_0402_16V4Z
FBAD23 FBAA7 2
D19 FBAD23 FBA_CMD23 K27 BUFRST_N A6
FBAD24 A18 G26 FBAA4 V1
FBAD25 FBAD24 FBA_CMD24 FBACAS# IFPC_TXC +3VS
B18 B27 FBACAS# 38 HDMI W1

GENERAL
FBAD26 FBAD25 FBA_CMD25 IFPC_TXC_N
A19 FBAD26 FBA_CMD26 N24 T1 IFPC_TXD0 STEREO F7
FBAD27 B19 R1
FBAD28 FBAD27 FBADQM#0 IFPC_TXD0_N
D18 FBAD28 FBADQM0 D21 T3 IFPC_TXD1 SWAPRDY A7 1 R572 2
FBAD29 C19 F22 FBADQM#1 T2 C9 VGA@ 10K_0402_5%
FBAD30 FBAD29 FBADQM1 FBADQM#2 IFPC_TXD1_N THERMDN
C16 FBAD30 FBADQM2 F20 V2 IFPC_TXD2 THERMDP B9
FBAD31 C18 A21 FBADQM#3 V3
FBAD32 FBAD31 FBADQM3 FBADQM#4 IFPC_TXD2_N
N26 FBAD32 FBADQM4 V27
FBAD33 N25 W22 FBADQM#5
FBAD34 FBAD33 FBADQM5 FBADQM#6 R565 1
R25 FBAD34 FBADQM6 V22 2 @ 1K_0402_5% J3 IFPCD_RSET
FBAD35 R26 V24 FBADQM#7 D2
FBAD36 FBAD35 FBADQM7 ROM_SCLK
R27 FBAD36 ROM_SI F3
FBAD37 FBADQS#0
FBAD38
T25
T27
FBAD37 FBADQS_RN0 A22
E22 FBADQS#1 SERIAL ROM_SO D3
D1
FBAD39 FBAD38 FBADQS_RN1 FBADQS#2 ROMCS_N
T26 FBAD39 FBADQS_RN2 F21
FBAD40 AB23 B21 FBADQS#3
FBAD41 FBAD40 FBADQS_RN3 FBADQS#4
Y24 FBAD41 FBADQS_RN4 V26
FBAD42 AB24 W23 FBADQS#5 G72M_BGA533 VGA@
FBAD43 FBAD42 FBADQS_RN5 FBADQS#6
AB22 FBAD43 FBADQS_RN6 V23
FBAD44 AC24 FBAD44 FBADQS_RN7 W27 FBADQS#7 SLOT_CLOCK_CFG SHARE REFERENCE CLOCK
FBAD45 AC22
FBAD46 FBAD45 FBADQS0 +1.8VS
AA23 FBAD46 FBADQS_WP0 B22
FBAD47 AA22 D22 FBADQS1 0 Disable
FBAD48 FBAD47 FBADQS_WP1 FBADQS2
T24 FBAD48 FBADQS_WP2 E21
B FBAD49 FBADQS3 B
T23 FBAD49 FBADQS_WP3 C21
1

FBAD50 R24 V25 FBADQS4 1 Enable(Default)


FBAD51 FBAD50 FBADQS_WP4 FBADQS5 R566
R23 FBAD51 FBADQS_WP5 W24
FBAD52 R22 U24 FBADQS6 1K_0402_1%
FBAD53 FBAD52 FBADQS_WP6 FBADQS7
T22 FBAD53 FBADQS_WP7 W26 @
FBAD54 N23
2

FBAD55 FBAD54 FB_VREF1 15mil


P24 FBAD55 FB_VREF A16
FBAD56 AA24 FBAD56
1

FBAD57 AA27 L24 1


FBAD57 FBA_CLK0 FBACLK0 38
FBAD58 C622 R567
MEMORY INTERFACE

AA26 FBAD58 FBA_CLK0_N K23 FBACLK0# 38


FBAD59 AB25 M22 @ 1K_0402_1%
FBAD59 FBA_CLK1 FBACLK1 38
FBAD60 AB26 N22 0.1U_0402_16V4Z @
FBAD60 FBA_CLK1_N FBACLK1# 38 2
FBAD61 AB27 M23
2

FBAD62 FBAD61 FBA_CMD27 R568


AA25 FBAD62 NC M24
FBAD63 W25 K22 FBA_DEBUG 1 2 FBA_RST
FBAD63 FBA_DEBUG 0_0402_5%
@
G72M_BGA533 VGA@
FB_VREF1=0.5 x FBVDD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS Memory
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 35 of 49
5 4 3 2 1
5 4 3 2 1

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+VGA_CORE +1.2VS

+VGA_CORE U38D 1400mA


J9 W17 0.1U_0402_16V4Z 1U_0402_6.3V4K 4.7U_0603_6.3V
VDD_0 Part 4 of 5 PEX_IOVDD_0
J10 VDD_1 PEX_IOVDD_1 W18
1U_0805_10V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z J11 AB10 1 1 1 1 1
VDD_2 PEX_IOVDD_2 C629 C630 C631 C632 C646
L12 VDD_3 PEX_IOVDD_3 AB11
1 1 1 1 1 1 L13 VDD_4 PEX_IOVDD_4 AB14
D C623 C624 C625 C626 C627 C628 VGA@ VGA@ VGA@ VGA@ VGA@ D
L15 VDD_5 PEX_IOVDD_5 AB15
2 2 2 2 2
L16 VDD_6 PEX_IOVDD_6 AB20
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ M9 AB21
2 2 2 2 2 2 VDD_7 PEX_IOVDD_7
M11 VDD_8 PEX_IOVDDQ_0 AA4
M12 AB5 0.1U_0402_16V4Z 1U_0402_6.3V4K
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDD_9 PEX_IOVDDQ_1
M13 VDD_10 PEX_IOVDDQ_2 AB6
M14 VDD_11 PEX_IOVDDQ_3 AB7
M15 AB8 0.1U_0402_16V4Z 1U_0402_6.3V4K 4.7U_0603_6.3V
VDD_12 PEX_IOVDDQ_4
M16 VDD_13 PEX_IOVDDQ_5 AB9 1 1 1 1 1
M17 AB12 C640 C641 C642 C643 C647
+NV_PLLVDD VDD_14 PEX_IOVDDQ_6
N9 VDD_15 PEX_IOVDDQ_7 AB13
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.1U_0402_16V4Z N11 AB16 VGA@ VGA@ VGA@ VGA@ VGA@
VDD_16 PEX_IOVDDQ_8 2 2 2 2 2
N17 VDD_17 PEX_IOVDDQ_9 AB17
C649 1 1 1 1 1 1 R9 AB18
C650 C651 C652 C635 C636 VDD_18 PEX_IOVDDQ_10
R11 VDD_19 PEX_IOVDDQ_11 AB19
R17 AC9 0.1U_0402_16V4Z 1U_0402_6.3V4K
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VDD_20 PEX_IOVDDQ_12
T9 VDD_21 PEX_IOVDDQ_13 AC11
2 2 2 2 2 2
T11 VDD_22 PEX_IOVDDQ_14 AC12
T12 VDD_23 PEX_IOVDDQ_15 AC16
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.1U_0402_16V4Z T13 AC17
VDD_24 PEX_IOVDDQ_16
T14 AC19

POWER
VDD_25 PEX_IOVDDQ_17 +1.2VS
T15 VDD_26 PEX_IOVDDQ_18 AC20
T16 VDD_27
T17 Y6 +PEX_PLLAVDD L37 VGA@
+VGA_CORE VDD_28 PEX_PLLAVDD +PEX_PLLDVDD +PEX_PLLAVDD +PEX_PLLAVDD_L 1
U12 VDD_29 PEX_PLLDVDD AA5 2
U13 1 1 1 MBK1608121YZF_0603
0.47U_0402_6.3V6K 0.47U_0402_6.3V6K VDD_30 0.1U_0402_16V4Z +3VS C653 C654 C655
U15 VDD_31 MIOB_VDDQ_0 K5
1 1 1 1 1 U16 K6 1 VGA@
C656 C657 C658 C659 VDD_32 MIOB_VDDQ_1 C662 VGA@ VGA@ 4.7U_0805_10V4Z
W13 VDD_33 MIOB_VDDQ_2 L6
C660 2 2 2
W15 VDD_34
1U_0805_10V7K VGA@ VGA@ VGA@ VGA@ 1U_0805_10V7K W16 J5 VGA@ 0.01U_0402_16V7K
2 2 2 2 2 VDD_35 MIOBCAL_PD_VDDQ 2 0.1U_0402_16V4Z
VGA@
C 0.47U_0402_6.3V6K +IFPA_IOVDD C
IFPA_IOVDD W4
W9 Y4 +PEX_PLLDVDD
VDD_LP_0 IFPB_IOVDD
W10 VDD_LP_1 IFPC_IOVDD L4 1 R113 2 VGA@ 1 1
Average to place around +VGA_CORE W11 10K_0402_5% C663 C664
plane. VDD_LP_2 +IFPAB_PLLVDD
W12 VDD_LP_3 IFPAB_PLLVDD V5
+3VS M4 1 R116 2 VGA@ VGA@
IFPCD_PLLVDD 10K_0402_5% VGA@ 2 2
+3VS F13 AE2 +DACA_VDD 0.01U_0402_16V7K
VDD33_0 DACA_VDD 0.1U_0402_16V4Z
F14 VDD33_1 DACB_VDD F8 2 1
J12 R292 10K_0402_5%
0.022U_0402_16V7K VDD33_2
J13 VDD33_3 VGA@
1 1 1 1 J15 H4 40mA +PLLVDD
C666 C667 C669
C670 VDD33_4 PLLVDD +1.8VS
J16 VDD33_5
D13 40mA +FBA_PLLAVDD L39
VGA@ VGA@ VGA@VGA@ +1.8VS FBA_PLLAVDD +1.8VS VGA@
1U_0603_10V4Z 2 2 2 2
D14 +H_PLLVDD +IFPA_IOVDD 4700P_0402_25V7K 4700P_0402_25V7K 1 2
0.1U_0402_16V4Z 0.47U_0402_6.3V6K H_PLLVDD MBK1608121YZF_0603
E15 FBVTT_0
F15 D15 1 R573 2 1 1 1 1 1
FBVTT_1 FBCAL_PD_VDDQ VGA@ 45.3_0402_1%~D +1.8VS C680 C681 C671 C672 4.7U_0603_6.3V
F16 FBVTT_2
J17 VGA@
FBVTT_3
J18 FBVTT_4 FBVDDQ_0 F17 4700P_0402_25V7K 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ VGA@ VGA@ VGA@ C673
2 2 2 2 2
L19 FBVTT_5 FBVDDQ_1 F19 1 1 1 1 1 1
N19 J19 C674 C675 C676 C677 C678 C679
FBVTT_6 FBVDDQ_2 470P_0402_50V7K 470P_0402_50V7K
R19 FBVTT_7 FBVDDQ_3 J22
+VGA_CORE U19 L22 VGA@ VGA@ VGA@ VGA@ VGA@
FBVTT_8 FBVDDQ_4 2 2 2 2 2 2 VGA@
R574 W19 FBVTT_9 FBVDDQ_5 M19
FBVDDQ_6 P22
1 2 +NV_PLLVDD T19 4700P_0402_25V7K 4700P_0402_25V7K 22U_0805_6.3V4Z +1.8VS
FBVDDQ_7
D11 NC FBVDDQ_8 U22
0_0603_5% 8mA Y22 L40
VGA@ FBVDDQ_9 +IFPAB_PLLVDD 4700P_0402_25V7K 1 2
G72M_BGA533 VGA@ 1 1 1 MBK1608121YZF_0603
B C687 C688 VGA@
4.7U_0603_6.3V B
VGA@
VGA@ VGA@ C689
2 2 2
470P_0402_50V7K

L43
MBK1608121YZF_0603 +1.2VS
VGA@
+PLLVDD 4700P_0402_25V7K 2 1
30mA
1 1 1
C693 C694 4.7U_0603_6.3V
L47 VGA@ VGA@ L42
MBK1608121YZF_0603 +1.2VS VGA@ C695 MBK1608121YZF_0603 +3VS
VGA@ 0.1U_0402_16V4Z 2 2 2 VGA@
+H_PLLVDD 2 1 +DACA_VDD 4700P_0402_25V7K 2 1

1 1 1 1 1 1
C699 C701 C702 C690 C691 4.7U_0603_6.3V
VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ 4.7U_0805_10V4Z L48 C692
0.1U_0402_16V4Z 2 2 2 MBK1608121YZF_0603 +1.2VS 2 2 2
VGA@
470P_0402_50V7K +FBA_PLLAVDD 2 1 470P_0402_50V7K

1 1
C703 C704
A VGA@ VGA@ A

2 2 2.2U_0603_6.3V6K

4700P_0402_25V7K

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 36 of 49
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn STRAPS PIN DESCRIPTION Value Value

U38E
B2 GND_0 GND_60 U17
B5 Part 5 of 5 U23
GND_1 GND_61
B8 GND_2 GND_62 U26
B11 GND_3 GND_63 V9
B14 V19 VBIOS on card (pull high)
GND_4 GND_64 SUB_VENDOR MIO_A_D1 VBIOS with system BIOS (pull down)
D
B17 GND_5 GND_65 W14 0 D
B20 GND_6 GND_66 Y2
B23 Y5 0---->Enable (Default)
GND_7 GND_67 PEX_PLL_TERM MIO_A_D0 PCI-E PLL termination 1---->Disable
B26 GND_8 GND_68 Y23 0
E2 GND_9 GND_69 Y26
E5 AC2 MIOAD
GND_10 GND_70
E8 GND_11 GND_71 AC8 PEX_CFG[3:0] [9,8,6] Recommended for G8x 0001
E11 GND_12 GND_72 AC14
E14 GND_13 GND_73 AC23 MIOBD_HSYNC
E17 GND_14 GND_74 AC26
E20 AD8 SUB_VENDOR R575 1 2 2K_0402_5%
GND_15 GND_75 35 SUB_VENDOR 0001 ---> Qimonda 16Mx32
E23 GND_16 GND_76 AD9 RAM_CFG[3:0] MIOAD0 0011
E26 AD11 VGA@ 0010 ---> Hynix 16Mx32
GND_17 GND_77 0011 ---> Samsung 16Mx32
GND_78 AD12 MIOAD1
H2 GND_19 GND_79 AD14
H6 AD16 MIOAD8
GND_20 GND_80
H23 GND_21 GND_81 AD17
H26 GND_22 GND_82 AD19 SUB_VENDOR MIOAD9
J14 GND_23 GND_83 AD20
K9 GND_24 GND_84 AC5

GND
K19 GND_25 GND_85 AF2 0 N0 VIDEO BIOS ROM
L2 GND_26 GND_86 AF3
L5 GND_27 GND_87 AF6
L11 GND_28 GND_88 AF9 1 BIOS ROM is present(Default)
L14 GND_29 GND_89 AF12
L17 GND_30 GND_90 AF15
L23 GND_31 GND_91 AF18 G73M-xxxx8
L26 AF21 PCI_DEVID[3:0] VIPD[5:3] G72M-0x01D8 0111
GND_32 GND_92
N12 GND_33 GND_93 AF24 MIOA_HSYNC NB8M-GS : 0X0427
N13 AF26 NB8M-SE : 0X0428 1000
GND_34 GND_94
N14 GND_35
N15 GND_36
G72MV-0x01D7 0111
N16 TBD/TBD
C GND_37 C
P2 GND_38
P5 GND_39 IFPAB_PLLGND V6
P9 GND_40 IFPCD_PLLGND M6
P11 GND_41
P12 GND_42
P13 GND_43 MIOBCAL_PU_GND M3 PAD T53
P14 GND_44
P15 GND_45 PEX_PLLGND AA6
P16 GND_46
P17 GND_47 PLLGND H5
P19 GND_48
P23 GND_49
P26 GND_50 FBA_PLLGND C15
R12 GND_51
R13 R576
GND_52 24.9_0402_1%
R14 GND_53
R15 E13 VGA@1 2
GND_54 FBCAL_PU_GND VGA@2
R16 GND_55 FBCAL_TERM_GND H22 1
U2 40.2_0402_1% +3VS
GND_56 R605
U5 GND_57
U11 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
GND_58 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
U14 GND_59

1
G72M_BGA533
VGA@ R577 R578 R579 R580 R581 R582 R583 R584 R585 R586 R587 R588 R589 R590
VGA@ VGA@ @ @ @ @ @ @
VGA@ VGA@ VGA@ @ @ VGA@

2
RAM_CFG0
34 RAM_CFG0
RAM_CFG1
34 RAM_CFG1
RAM_CFG2
B 34 RAM_CFG2 B
RAM_CFG3
34 RAM_CFG3
PCI_DEVID0
34 PCI_DEVID0
PCI_DEVID1
34 PCI_DEVID1
PCI_DEVID2
34 PCI_DEVID2
PCI_DEVID3
34 PCI_DEVID3
PCI_DEVID4
34 PCI_DEVID4
PEX_CFG0
35 PEX_CFG0
PEX_CFG1
35 PEX_CFG1
PEX_CFG2
35 PEX_CFG2
PEX_CFG3
34 PEX_CFG3
PEX_PLL_TERM
35 PEX_PLL_TERM

1
R591 R592 R593 R594
@ @ VGA@ VGA@

2
10K_0402_5% 10K_0402_5%
10K_0402_5% 10K_0402_5%

Bandwidth RAM Type Vendor Package


A A
FULL R17 32M R11 Samsung R20, R19 (10*12.5) Infineon GDDR2(400): SA00000S800 (HYB18T256161AFL-25) Infineon GDDR2(350): SA00000T700 (HYB18T256161AF-28)
HALF R12 16M R16 Hynix R18, R19 (11*13) Samsung GDDR2 (400): SA00000FG10 (K4N56163QF-ZC25) Samsung GDDR2 (350): SA00000TB00 (K4N56163QF-ZC2A)
Infineon R18, R21 (8*13) Hynix GDDR2 (400): SA00000FF10 (HY5PS561621AFP-25) Hynix GDDR2 (350): SA00000TJ00 (HY5PS561621AFP-28)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS GND & STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 37 of 49
5 4 3 2 1
5 4 3 2 1

+1.8VS
1 http://laptopblue.vn 35 FBAD[0..63]

35 FBADQS#[0..7]
FBAD[0..63]

FBADQS#[0..7]

FBADQS[0..7]

G11

G11
D12

D12
B12

P12

B12

P12
T12

T12
35 FBADQS[0..7]

L11

L11
G2

G2
D1
D4
D9

D1
D4
D9
R908

B1
B4
B9

P1
P4
P9

B1
B4
B9

P1
P4
P9
T1
T4
T9

T1
T4
T9
L2

L2
1.05K_0402_1% U51 U52 DQMA#[0..7]
VGA@ +VREFA2 35 FBADQM#[0..7]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBAA[0..11]
2

+VREFA0 35 FBAA[0..11]
FBAA0 K4 FBAA0 K4 FBBA[2..5]
A0 A0 35 FBBA[2..5]
1

1 FBAA1 H2 B2 FBAD1 FBAA1 H2 B2 FBAD40


R912 C886 FBAA2 A1 DQ0 FBAD3 FBBA2 A1 DQ0 FBAD41
K3 A2 DQ1 B3 K3 A2 DQ1 B3
2.49K_0402_1% 0.01U_0402_16V7K FBAA3 M4 C2 FBAD2 FBBA3 M4 C2 FBAD42 FBA_BA0
D A3 DQ2 A3 DQ2 35 FBA_BA0 D
VGA@ VGA@ FBAA4 K9 C3 FBAD5 FBBA4 K9 C3 FBAD43
2 FBAA5 A4 DQ3 FBAD7 FBBA5 A4 DQ3 FBAD44 FBA_BA1
H11 E2 H11 E2 35 FBA_BA1
2

FBAA6 A5 DQ4 FBAD4 FBAA6 A5 DQ4 FBAD45


K10 A6 DQ5 F3 K10 A6 DQ5 F3
FBAA7 L9 F2 FBAD0 FBAA7 L9 F2 FBAD46 FBA_BA2
A7 DQ6 A7 DQ6 35 FBA_BA2
FBAA8 K11 G3 FBAD6 FBAA8 K11 G3 FBAD47
FBAA9 A8/AP DQ7 FBAD16 FBAA9 A8/AP DQ7 FBAD35
M9 A9 DQ8 B11 M9 A9 DQ8 B11
FBAA10 K2 B10 FBAD17 FBAA10 K2 B10 FBAD34
+1.8VS FBAA11 A10 DQ9 FBAD18 FBAA11 A10 DQ9 FBAD32
L4 A11 DQ10 C11 L4 A11 DQ10 C11
FBA_BA0 G4 C10 FBAD19 FBA_BA0 G4 C10 FBAD33
FBA_BA1 BA0 DQ11 FBAD20 FBA_BA1 BA0 DQ11 FBAD39
G9 BA1 DQ12 E11 G9 BA1 DQ12 E11
1

F10 FBAD21 F10 FBAD36


R917 FBADQM#0 DQ13 FBAD22 FBADQM#5 DQ13 FBAD37
E3 DM0 DQ14 F11 E3 DM0 DQ14 F11
1.05K_0402_1% FBADQM#2 E10 G10 FBAD23 FBADQM#4 E10 G10 FBAD38
VGA@ +VREFA3 FBADQM#3 DM1 DQ15 FBAD27 FBADQM#6 DM1 DQ15 FBAD51
N10 DM2 DQ16 M11 N10 DM2 DQ16 M11
FBADQM#1 N3 L10 FBAD25 FBADQM#7 N3 L10 FBAD48
2

+VREFA1 DM3 DQ17 FBAD24 DM3 DQ17 FBAD53


DQ18 N11 DQ18 N11
FBADQS0 D2 M10 FBAD26 FBADQS5 D2 M10 FBAD50
WDQS0 DQ19 WDQS0 DQ19
1

1 FBADQS2 D11 R11 FBAD31 FBADQS4 D11 R11 FBAD52


R918 C887 FBADQS3 WDQS1 DQ20 FBAD28 FBADQS6 WDQS1 DQ20 FBAD49
P11 WDQS2 DQ21 R10 P11 WDQS2 DQ21 R10
2.49K_0402_1% 0.01U_0402_16V7K FBADQS1 P2 T11 FBAD30 FBADQS7 P2 T11 FBAD54
VGA@ VGA@ WDQS3 DQ22 FBAD29 WDQS3 DQ22 FBAD55
DQ23 T10 DQ23 T10
2 +VREFA0 FBAD10 +VREFA2 FBAD59
H1 M2 H1 M2
2

+VREFA1 VREF DQ24 FBAD12 +VREFA3 VREF DQ24 FBAD57


H12 VREF DQ25 L3 H12 VREF DQ25 L3
J2 N2 FBAD9 J2 N2 FBAD61
RFU1 DQ26 FBAD15 RFU1 DQ26 FBAD62
J3 RFU2 DQ27 M3 J3 RFU2 DQ27 M3
R2 FBAD8 R2 FBAD60
FBARAS# DQ28 FBAD13 FBARAS# DQ28 FBAD63
35 FBARAS# H3 RAS# DQ29 R3 H3 RAS# DQ29 R3
FBACAS# F4 T2 FBAD11 FBACAS# F4 T2 FBAD56
35 FBACAS# CAS# DQ30 CAS# DQ30
FBAWE# H9 T3 FBAD14 FBAWE# H9 T3 FBAD58
35 FBAWE# WE# DQ31 WE# DQ31
FBACS0# F9 FBACS0# F9
35 FBACS0# CS# CS#
FBA_CKE H4 A1 +1.8VS FBA_CKE H4 A1 +1.8VS
C 35 FBA_CKE CKE VDDQ CKE VDDQ C
FBACLK0 J11 A12 FBACLK1 J11 A12
FBACLK0# CK VDDQ FBACLK1# CK VDDQ
J10 CK# VDDQ C1 J10 CK# VDDQ C1
VDDQ C4 VDDQ C4
1 2 A4 ZQ VDDQ C9 1 2 A4 ZQ VDDQ C9
R919 243_0402_1% A9 C12 R920 243_0402_1% A9 C12
VGA@ MF VDDQ VGA@ MF VDDQ
VDDQ E1 VDDQ E1
FBADQS#0 D3 E4 FBADQS#5 D3 E4
FBADQS#2 RDQS0 VDDQ FBADQS#4 RDQS0 VDDQ
D10 RDQS1 VDDQ E9 D10 RDQS1 VDDQ E9
FBADQS#3 P10 E12 FBADQS#6 P10 E12
FBADQS#1 RDQS2 VDDQ FBADQS#7 RDQS2 VDDQ
P3 RDQS3 VDDQ J4 P3 RDQS3 VDDQ J4
VDDQ J9 VDDQ J9
+1.8VS A2 VDD VDDQ N1 +1.8VS A2 VDD VDDQ N1
A11 VDD VDDQ N4 A11 VDD VDDQ N4
F1 VDD VDDQ N9 F1 VDD VDDQ N9
F12 VDD VDDQ N12 F12 VDD VDDQ N12
M1 VDD VDDQ R1 M1 VDD VDDQ R1
M12 VDD VDDQ R4 M12 VDD VDDQ R4
V2 VDD VDDQ R9 V2 VDD VDDQ R9
V11 VDD VDDQ R12 V11 VDD VDDQ R12
VDDQ V1 VDDQ V1
V4 V12 +1.8VS V4 V12 +1.8VS
FBA_RST SEN VDDQ FBA_RST SEN VDDQ
35 FBA_RST V9 RESET V9 RESET
FBA_BA2 H10 K1 FBA_BA2 H10 K1
BA2 VDDA BA2 VDDA
VDDA K12 VDDA K12
1 1 1 1
J1 VSSA J1 VSSA
J12 C889 C890 J12 C891 C892
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSSA 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VGA@2 2 VGA@ VGA@2 2 VGA@
K4J52324QE-BC14_FBGA136~D K4J52324QE-BC14_FBGA136~D
A3
A10
G1
G12
L1
L12
V3
V10

A3
A10
G1
G12
L1
L12
V3
V10
VGA@ VGA@

B B

+1.8VS GDDR3 BGA MEMORY +1.8VS GDDR3 BGA MEMORY

0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0805_10V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C894 C895 C896 C897 C898 C899 C900 C901 C902 C903 C904 C905 C906 C907 C908 C909 C910 C911 C912 C913 C914 C915
VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1000P_0402_50V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M 1000P_0402_50V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M

FBACLK1
35 FBACLK1

1
R610
FBACLK0 243_0402_1%
35 FBACLK0
VGA@

2
1

A R607 FBACLK1# A
35 FBACLK1#
243_0402_1%
VGA@
2

FBACLK0#
35 FBACLK0#

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2007/02/12 Deciphered Date 2008/02/12
VRAM GDDR3 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 38 of 49
5 4 3 2 1
5 4 3 2 1

Q35

http://laptopblue.vn
+3VS
+1.8V AO3413_SOT23
+1.8VS_CB

4.7U_0805_10V4Z

0.1U_0402_10V6K
S

D
3 1
1
+3VS

0.01U_0402_25V7K~N

4.7U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

C1139

C1140
R666 +3VS_PHY

G
1 1

4.7U_0805_10V4Z

0.1U_0402_10V6K
1 2 +3VS_PHY 0_0603_5%
32,41,48 SUSP 2

C1136

C1137

C1138
100K_0402_5% 1 1 1 2
+3VS R878
2 2

C1186

C1141

C1142

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_0805_10V4Z
120
125

102
103
122
2 2

26
56

15
14
91
92

67
73
79
81
1 1

7
U46

C922

C926

C925
D D

VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8

VCC3.3
VCC3.3
VCC3.3
VCC3.3
PCI_VCC
PCI_VCC

AVCC
AVCC
AVCC
AVCC
17 PCI_AD[0..31] 2 2
PCI_AD31 19
PCI_AD30 AD31 R520 5.9K_0402_1%
20 AD30
PCI_AD29 21 78 1 2
PCI_AD28 AD29 REF
22 AD28
PCI_AD27 23 83 OZ129XI
PCI_AD26 AD27 XI OZ129XO +3VS
24 84
PCI_AD25
PCI_AD24
PCI_AD23
25
27
AD26
AD25
AD24
OZ129 XO

TPBIAS 76 IEEE1394_TPBIAS0
IEEE1394_TPAP0
29 AD23 TPA+ 75
PCI_AD22 30 74 IEEE1394_TPAN0 R942
PCI_AD21 AD22 TPA- IEEE1394_TPBP0 22K_0402_5%
31 AD21 TPB+ 72
CLK_PCI_CB PCI_AD20 32 71 IEEE1394_TPBN0
PCI_AD19 AD20 TPB-
34 AD19
PCI_AD18 35 AD18
1
10_0402_5%~D

PCI_AD17 36 4 MC_3V# Layout Note: Place close to


R832 PCI_AD16 AD17 MC_3V# SDCLK_MSCLK
37 113
@ PCI_AD15 47
AD16 SD_CLK/MS_CLK
111 SDD3 OZ129 and Shield GND.
PCI_AD14 AD15 SD_D3 SDD2
48 AD14 SD_D2 112
PCI_AD13 49 107 SDD1 C819
2

PCI_AD12 AD13 SD_D1 SDD0 OZ129XI


50 AD12 SD_D0 108 2 1
PCI_AD11 51 110 SD_CMD
PCI_AD10 AD11 SD_CMD SD_WP 15P_0402_50V8J
52 AD10 SD_WP 117

2
4.7P_0402_50V8C

PCI_AD9 53 114 SDCD#


PCI_AD8 AD9 SD_CD# X3
1 54 AD8
PCI_AD7 57
C823 PCI_AD6 AD7 XDD7_MSD1 24.576MHz_16P_1BG24576CKIA~D
58 95

1
@ PCI_AD5 AD6 MS_D1/XD_D7 XD_D6 C822
59 AD5 XD_D6 93
2 PCI_AD4 XD_D5 OZ129XO
60 AD4 XD_D5 89 2 1
PCI_AD3 61 87 XD_D4
PCI_AD2 AD3 XD_D4 XDD3_MSBS 15P_0402_50V8J
62 AD2 MS_BS/XD_D3 88
C PCI_AD1 63 90 XDD2_MSD0 C
PCI_AD0 AD1 MS_D0/XD_D2 XDD1_MSD2
64 AD0 MS_D2/XD_D1 94
96 XDD0_MSD3
MS_D3/XD_D0 XDCE#
XD_CE# 119
PCI_CBE#3 28 100 XDRB#
17 PCI_CBE#3 C/BE3# XD_RB# +3VS_CR
PCI_CBE#2 38 118 XDCLE
17 PCI_CBE#2 C/BE2# XD_CLE
PCI_CBE#1 46 109 XDALE
17 PCI_CBE#1 C/BE1# XD_ALE
PCI_CBE#0 55 105 XDWE#
17 PCI_CBE#0 C/BE0# XD_WE#
101 XDRE#
R691 XD_RE# XDWP# +3VS SDCLK
XD_WPO# 98
PCI_AD21 1 2 CBS_IDSEL 5 99 MSCD# 1
CLK_PCI_CB IDSEL MS_CD# XDCD#
16 CLK_PCI_CB 45 PCI_CLK XD_CD# 97

1
100_0402_5% PCI_DEVSEL# 42 +3VS_CR C1146
17 PCI_DEVSEL# DEVSEL#
PCI_FRAME# 39 R932 10P_0402_50V8J
17 PCI_FRAME# FRAME#

3
2
S
PCI_IRDY# 40 85 470_0402_5% @
17 PCI_IRDY# IRDY# PHY_TEST0 G
PCI_TRDY# 41 86 MC_3V# 2 Q81
17 PCI_TRDY# TRDY# PHY_TEST1
PCI_STOP# 43 AO3413_SOT23-3 1 1
17 PCI_STOP#

2
PCI_PAR STOP#
17 PCI_PAR 44 D

1
PCI_REQ0# PAR C1187 C1188
17 PCI_REQ0# 17 PCI_REQ# NC 2

1
PCI_GNT0# D 1U 10V Z Y5V 0603
17 PCI_GNT0# 18 PCI_GNT# NC 8 1U 10V Z Y5V 0603
PCI_RST# MMCD4 2 2
17,21 PCI_RST# 1 PCI_RST# NC 9 1 2 MC_3V# MSCLK
PCI_PIRQG# 11 10 MMCD5 Q82 G 1
17 PCI_PIRQG# INTA# NC
CB_PME# 3 13 C878 S SSM3K7002FU_SC70-3
29 CB_PME#

3
PME# NC MMCD6 1U 10V Z Y5V 0603 C1149
6 CLKRUN# NC 126
@ R850 2 2
1 100K_0402_5% NC 127 MMCD7 10P_0402_50V8J
@ 2
106 MEDIA_LED NC 128
R693 1 2 0_0402_5%~D
19,29 PCI_CLKRUN#

AGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

LED behave: OZ129TN_LQFP128_14X14 +3VS_CR +3VS_CR


12
16
33
66
68
104
115
116
121
123
124

82
80
77
70
69
65
Idel ---------> low
B Accress data --> always high 0_0603_5% JSD1 B
1 2 3 XD-VCC SD-VCC 21
R879 28
XDD0_MSD3 R873 0_0402_5%~D XDD0 MS-VCC
1 2 32 XD-D0
XDD1_MSD2 R874 1 2 0_0402_5%~D XDD1 10 7 IN 1 CONN 20 SDCLK R713 1 2 22_0402_5% SDCLK_MSCLK
XDD2_MSD0 R938 0_0402_5%~D XDD2 XD-D1 SD_CLK SDDAT0 R940 0_0402_5%~D SDD0
1 2 9 XD-D2 SD-DAT0 14 1 2
XDD3_MSBS R948 1 2 0_0402_5%~D XDD3 8 12 SDDAT1 R950 1 2 0_0402_5%~D SDD1
XD_D4 R957 0_0402_5%~D XDD4 XD-D3 SD-DAT1 SDDAT2 R959 0_0402_5%~D SDD2
1 2 7 XD-D4 SD-DAT2 30 1 2
IEEE1394_TPBIAS0 XD_D5 R964 1 2 0_0402_5%~D XDD5 6 29 SDDAT3 R966 1 2 0_0402_5%~D SDD3
XD_D6 R941 0_0402_5%~D XDD6 XD-D5 SD-DAT3 SDDAT4 R944 0_0402_5%~D MMCD4
1 2 5 XD-D6 SD-DAT4 27 1 2
1U_0603_10V4Z

XDD7_MSD1 R951 1 2 0_0402_5%~D XDD7 4 23 SDDAT5 R953 1 2 0_0402_5%~D MMCD5


XD-D7 SD-DAT5
1

1
56.2_0402_1%

56.2_0402_1%

1 18 SDDAT6 R962 1 2 0_0402_5%~D MMCD6


XDWE# R960 0_0402_5%~D XDWE SD-DAT6 SDDAT7 R937 0_0402_5%~D MMCD7
1 2 34 XD-WE SD-DAT7 16 1 2
R830 R831 C821 XDWP# R967 1 2 0_0402_5%~D XDWP 33
XDALE R945 0_0402_5%~D XD_ALE XD-WP SDCD R947 1
1 2 35 XD-ALE SD-CD 1 2 0_0402_5%~D SDCD#
2 XDCD# R955 0_0402_5%~D XDCD SDWP R956 1
1 2 40 2 2 0_0402_5%~D SD_WP
2

XDRB# R952 0_0402_5%~D XDRB XD-CD SD-WP SDCMD R963 1 SD_CMD


1 2 39 XD-R/B SD-CMD 25 2 0_0402_5%~D
XDRE# R961 1 2 0_0402_5%~D XDRE 38
XDCE# R936 0_0402_5%~D XDCE XD-RE MSCLK R714 1 SDCLK_MSCLK
1 2 37 XD-CE MS-SCLK 26 2 22_0402_5%
IEEE1394_TPAP0 J139A1 XDCLE R946 1 2 0_0402_5%~D XD_CLE 36 13 MSBS R939 1 2 0_0402_5%~D XDD3_MSBS
XD-CLE MS-BS MSINS R949 1
4 TPA+ GND 5 MS-INS 22 2 0_0402_5%~D MSCD#
IEEE1394_TPAN0 3 6
IEEE1394_TPBP0 TPA- GND MSDATA0 R958 0_0402_5%~D XDD2_MSD0
2 TPB+ GND 7 11 7in1-GND MS-DATA0 17 1 2
1 8 31 15 MSDATA1 R965 1 2 0_0402_5%~D XDD7_MSD1
IEEE1394_TPBN0 TPB- GND 7in1-GND MS-DATA1 MSDATA2 R943 0_0402_5%~D XDD1_MSD2
41 7in1-GND MS-DATA2 19 1 2
SUYIN_020204FR004S506ZL~D 42 24 MSDATA3 R954 1 2 0_0402_5%~D XDD0_MSD3
7in1-GND MS-DATA3
conn@
1

1
56.2_0402_1%

56.2_0402_1%

TAITW_R015-A10-LM
R833 R834

A A
2

2
270P_0402_50V7K

2 5.1K_0402_1%

2
C824 R835
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/01 Deciphered Date 2008/09/01 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OZ129_Card Reader / 1394
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Layout Note: Place close to OZ129 Chipset. Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4131P
Date: Thursday, January 10, 2008 Sheet 40 of 40
5 4 3 2 1
A B C D E

+3VALW to +3VS Transfer http://laptopblue.vn


+5VALW to +5VS Transfer
+1.8V to +1.8VS Transfer
+3VALW +3VS
B+_BIAS +5VALW +5VS +1.8V +1.8VS
B+_BIAS
4.7A
U40
8 1 10U_0805_10V4Z~N U39 U41
1 D S 10U_0805_10V4Z~N
7 D S 2 8 D S 1 8 D S 1

47K_0402_5%
R198 1 6 3 7 2 7 2
D S D S D S

R559
5 D G 4 1 1 1 6 D S 3 1 6 D S 3
330K_0402_5% C271 C465 C256 C278 5 4 1 1 VGA@ 5 4 1 1
SI4800DY_SO8 D G C284 C283 C727 D G C728 C697
2

1 2 10U_0805_10V4Z~N SI4800DY_SO8 SI4800DY_SO8 1


VGA@

1
2 2 2 10U_0805_10V4Z~N 10U_0805_10V4Z~N 2 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N
RUNON 3VS_GATE 2 2 VGA@ 2 2
1 2 VGA@ VGA@
R197 1 RUNON 1 2 1 5VS_GATE 0.1U_0402_16V4Z~N
100K_0402_5% 0.1U_0402_16V4Z~N R267 C279
C264 47K_0402_5%
1

D 0.01U_0402_25V7K~N 0.01U_0402_25V7K~N 1.8VS ON 1 1.8VS_GATE


2
SUSP 2 2 R608
2 1
G Q18 100K_0402_5%
S SSM3K7002FU_SC70-3 VGA@ C696
3

1
D 0.01U_0402_25V7K~N
VGA_PWGOD# 2 VGA@
2
G Q48
S SSM3K7002FU_SC70-3

3
SUSP 1 R665 2 VGA@
+CPU_CORE 1 2 +VCCP @ 0_0402_5%
C211 0.1U_0402_16V4Z~N

2 +3VALW 2
1

R409

100K_0402_5%
2

SYSON#
1

D
SYSON 2 Q42
28,29,46 SYSON
G SSM3K7002FU_SC70-3
S
3
2

R365
10K_0402_5%
1

+5VALW

+1.2VS +VGA_CORE +1.8VS


1

R340

1
3 3

1
100K_0402_5% R647 R609
R646
2

SUSP 470_0402_5% 470_0402_5%


32,40,48 SUSP
VGA Discharge circuit 470_0402_5%

2
1

D VGA@ VGA@

1 2
SUSP# 2 Q32 VGA@
28,29,46,47,48 SUSP#

1
G SSM3K7002FU_SC70-3 D D D
2

S SUSP 2 SUSP 2 VGA_PWGOD# 2


3

G G G
S Q61 VGA@ S Q62 VGA@ S Q65 VGA@

3
R338 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
10K_0402_5%
1

Discharge circuit-1 +1.8V +1.25VS +0.9VS +5VS +3VS +1.5VS


+1.8VS_CB
1

1
1

+5VALW +3VALW R133 R372 R351 R391 R383 R382


R536
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
1

2
1

R668
2

R551 VGA@
1

1
100K_0402_5% D D D D D D
1

100K_0402_5% D SYSON# SUSP SUSP SUSP SUSP SUSP


2 2 2 2 2 2
2

VGA_PWGOD# SUSP 2 Q50 G G G G G G


2

4 G SSM3K7002FU_SC70-3 S Q12 S Q34 S Q33 S Q39 S Q38 S Q37 4


3

3
1

D SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3


S
3

VGA_PWGOD 2 Q49
47 VGA_PWGOD
G SSM3K7002FU_SC70-3
VGA@ S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

SYSON -> SUSP# -> VGA_ON->VGA_PWGOD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 41 of 49
A B C D E
5 4 3 2 1

http://laptopblue.vn

D D

FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8


FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL
@ @ @ @ @ @ @ @
1

1
H7
H_2P5 @ HOLEA
1

H1 H2 H3 H25 H5 H6 H10 H21


@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA

H_2P8
1

1
C C

H12 H9 H11 H14 H8 H23 H13 H26


@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_2P8
1

H22 H19
H_3P3 @ HOLEA @ HOLEA
1

H4 H24
H_3P8 @ HOLEA @ HOLEA
1

B B

H15 H18 H16 H17


@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_4P3
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screws
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 42 of 49
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn ADPIN

PL17
VIN

FBMA-L11-322513-151LMA50T_1210
PJPDC1 PC156 PR188

@
1 1 2 2200P_0402_50V7K~D @ 56K_0402_5%~D
1
2 2
3 3 1 2 1 2
4 4
5 5

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
6 PR189
6

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D
7 1M_0402_1%~N
GND

1
PC287

PC157

PC159
D D
GND 8 1 2

PC286

PC158

PC160
VIN
ACES_88299-0600 VS VIN

0.01U_0402_25V7K~D
@

1
PR191 PR192

1
PC161
PR190 10K_0402_5%~D 1K_0402_5%~D
82.5K_0402_1%~D 1 2 ACIN 19,29,44

2
PR193

2
8
PL16 22K_0402_1%~D
PU12A
FBM-L11-160808-601LMT 0603~D N41 1 2 N40 3

P
+
2 1 DOCK_PSID O 1

19.6K_0402_1%~D
0.1U_0402_16V7K~D
N35 2 -

1
1

1
PC162

PR194
LM393DR_SO8 PR195

4
PC163 PD1 10K_0402_5%~D
1000P_0402_50V7K~D RLZ4.3B_LL34

2
2

2
PR198
10K_0402_5%~D
2 1
RTCVREF
3.3V

8
PU12B
5

P
VIN +
O 7
6 -

G
2

LM393DR_SO8
Vin Detector

4
C PD3 C

PJP1
PD4 @ JUMP_43X118 RLS4148_LL34-2 Max. typ. Min.
1 1

BATT+ 2 1 1 1 2 2 L-->H 18.234 17.841 17.449


CH751H-40PT_SOD323-2 PR203
33_1206_5% VS
H-->L 17.597 17.210 16.813
2

PQ50
CHGRTCP 3 TP0610K-T1-E3_SOT23-3
1
0.22U_1206_25V7K

32.8
1

PR205
PC164

100K_0402_5%~D PC165
0.1U_0603_25V7K~D
2

PR206
2

22K_0402_5%~D
31 51ON# 1 2

+5VALW +3VALW

DA204U_SOT323~D

2
PD5

2.2K_0402_5%~D
@ PR208
1

1 2

2
RTCVREF PR207 0_0402_5%~D
B 200_0805_5% B

PR209
PU14G920AT24U_SOT89-3 PR212
2

1
33_0402_5%~D

1
DOCK_PSID

S
3 OUT IN 2 1 3 1 2 PS_ID 29
1
4.7U_0805_6.3V6K~N

PQ53
1

GND
PC166

PC167 RHU002N06_SOT323-3

G
2
15K_0402_1%~D 100K_0402_1%~D
1U_0805_25V4Z~D +5VALW
2

2
1 PJP2 +5VALW
2

PR213

DA204U_SOT323~D
@ JUMP_43X118
+1.2VSP 1 1 2 2 +1.2VS

10K_0402_1%~D
1

2
PD6
1
2

PR214
C
2 PQ54
PJP3 PJP4 B MMST3904-7-F_SOT323~D @

2
@ JUMP_43X118 @ JUMP_43X118 E

2
PR215
+5VALWP 1 1 2 2 1 1 2 2

1
+5VALW +1.5VSP +1.5VS @
1
PD7 PR216
PJP5 PJP6 SM24_SOT23 1 2 PSID_DISABLE# 29

1
@ JUMP_43X118 @ JUMP_43X118
1 1 @ 10K_0402_1%~D
2 2 +0.9VSP 1 1 2 2 +0.9VS

PJP7 PJP8
@ JUMP_43X118 @ JUMP_43X118
+3VALWP 1 1 2 2 +3VALW +VCCPP 1 1 2 2 +VCCP

PJP9 PJP10
A @ JUMP_43X118 @ JUMP_43X118 A

+1.8VP 1 1 2 2 +1.8V 1 1 2 2

PJP11
@ JUMP_43X118 PJP12
1 1 @ JUMP_43X118
2 2
1 1 2 2
+VGA_COREP +VGA_CORE Security Classification Compal Secret Data
PJP13 2006/10/1 2007/5/01 Title
@ JUMP_43X118 PJP14
Issued Date Deciphered Date <Title>
1 1 @ JUMP_43X118
DCIN / Precharge
+1.25VSP 2 2 +1.25VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
1 1 2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL80 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 43 of 9
5 4 3 2 1
A B C D E

VIN

8
PQ55
FDS4435BZ_SO8

1
http://laptopblue.vn 1
PQ56
FDS4435BZ_SO8

8
PR217
0.015_2512_1%
B+

D S S D

0.01U_0402_25V7K~D
7 2 2 7 PJP15
D S S D CHG_B+
6 D S 3 3 S D 6 1 4 2 2 1 1

1
5 D G 4 4 G D 5

2
1_1210_5%~D1_1210_5%~D

PC171

PC292

PC172

PC293

PC173
2 3 @ JUMP_43X118 PR218

1
PC168 100K_0402_1%~D

2
PR339

0.01U_0402_25V7K~D

1
2

100K_0402_1%~D

CHGEN#

2
1

1000P_0402_50V7K~D

1000P_0402_50V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
PC170 PC175 PC177

1
2

5
6
7
8

1
0.01U_0603_50V7K~D

PC174

PR219
0.1U_0402_16V7K~D PU15 0.1U_0805_25V7K

1 2

1
1
1 2 1 28 1 2 PQ57 /BATDRV 1
CHGEN PVCC

2
1

4
3
2
1
PR272
PR220 FDS8884_SO8

2
PC178 PC176 2.2_0603_5%~D PQ58

S
S
S
G
0.1U_0603_25V7K~D @0.1U_0603_25V7K~D 27 1 2 4 FDS4435BZ_SO8

2
BTST

2
2

PR221

D
D
D
D
340K_0402_1%~D 2 26 DH_CHG
ACN HIDRV
2

3
2
1

5
6
7
8
PC169 ACP PR222

1
2.2U_0805_25V6K 4 25 LX_CHG PL18 0.02_2512_1%
1

ACDET ACDRV PH PD8 10UH_SIL1045RA-100PF_4.5A_30% BATT+


5 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M~D
ACSET RLS4148_LL34-2 PC179

REGN
2 3

2
PR224 0.1U_0603_25V7K~D

5
6
7
8

PC181
PR223 56.2K_0402_1%

10U_1206_25V6M~D
54.9K_0402_1% 1 2 6 PQ59
VREF

PC180
ACSET

2
24

2
REGN

1
FDS6690AS_NL_SO8
1

1
PR225 PC183

1
PC182 100K_0402_1%~D 1U_0603_10V6K~D 4
0.01U_0402_25V7K~D

2
2

2
90W adapter 1 2 7 ACOP
PR226 PC184 23 DL_CHG

3
2
1
340K_0402_1%~D 0.47U_0603_16V7K~N LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A CP setting
1

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.65A PGND 22
OVPSET 8 PC185
OVPSET 0.1U_0402_16V7K~D
Input OVP : 22.3V
1 2
2 2
Input UVP : 16.98V 9 AGND LEARN 21 ACOFF 29
2

1
Fsw : 300KHz PR227
54.9K_0402_1% VREF PC186 PC187
20 CELLS 0.1U_0603_25V7K~D @0.1U_0603_25V7K~D

2
CELLS
1

10 VREF
PQ60 3

1
SI2301BDS-T1-E3_SOT23-3 PC188
1U_0603_10V6K~D
VREF PR228 19

2
100K_0402_1%~D SRP
CELLS GND 3 Cell
1 2 2 11 VDAC SRN 18
2

VREF 4 Cell
PR229 17
BAT
1

100K_0402_1%~D

1
PC189 VADJ 12
0.1U_0603_25V7K~D VADJ PC190
1

ACSET 0.1U_0603_25V7K~D

2
CELLS 29
ACGOOD# TP
13 ACGOOD ICHG setting
1

D RTCVREF VREF
2 3cell/4cell# 50 PR231
G REGN 16 2 1 IREF 29
SRSET

2
S PQ61 /BATDRV 14 49.9K_0402_1%~D
3

BATDRV

1
SSM3K7002F_SC59-3
@

1
PR234 PR230 PR232
1

PC191 100K_0402_1%~D
100K_0402_1%~D
Cells selector PR51 IADAPT 15 1 2 100K_0402_1%~D
@0.01U_0402_25V7K~D

1
@ 0_0402_5%~D BQ24751ARHDR_QFN28_5X5 PR233

2
PR53 10_0603_5%~D ACIN 19,29,43
4.32K_0402_1%~D
2

1
3 VADJ D 3
29 CHGVADJ 1 2
29 ADP_I ACGOOD# 2 PQ62 @
1

G SSM3K7002F_SC59-3

1
PR54 S

3
10K_0402_1%~D PC192 IREF Current
100P_0402_50V8J~D

2
2

2.968V 3A
+COINCELL
PR235
PQ63 COIN RTC Battery
B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 B+_BIAS
1
470K_0402_5%~D

100_0805_5%~D 32.8 VREF


0.1U_0805_25V7M~N

PR1
2

+5VALW 1K_0402_5%~D
PR236

PC193

2
RTC_VREF
1

PR237
2

Z4012

100K_0402_1%~D
1
1
220K_0402_5%

1SS355_SOD323-2

PD9
2

1
PR238

CHGEN#
2

PJP24
2

1
+RTCVCC D
32.8 +COINCELL 1
1

1
1

PQ64 D PQ65
2 2 29 FSTCHG 2
2 3 G SSM3K7002F_SC59-3
G1
0.1U_0603_25V7K~D

G RHU002N06_SOT323-3 4 S

3
G2
220K_0402_5%

S PD2
3

1
2

BAT54CW_SOT323~D ACES_85204-02001
1
PC194

PR239

1
4 PC1 4

27.4 1U_0603_10V4Z~D
2

2
Move to power schematic

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JAL80 **** 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 44 of 9
A B C D E
5 4 3 2 1

B+ http://laptopblue.vn ISL6237_B+
ISL6237_B+

PJP20 PR240
@ JUMP_43X118 0_0805_5%
1 1 2 2 1 2

2200P_0402_50V7K~D

2200P_0402_50V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
VL

5
6
7
8
PC195

PC196

PC197

8
7
6
5

1
PC200
D D

PC198

PC199
2

1U_0603_10V6K~D
PQ67

2
2
PQ66 AO4466_SO8

2
AO4466_SO8 PC201

4.7U_0805_6.3V6K~N
4

1
PC202
4 0.1U_0603_25V7K~D

PC203
1
+5VALWP

3
2
1
1
2
3
PL21

7
PL20 PU16 PC207 2 1
1 2 1U_0603_10V6K~D 4.7UH_SIL104R-4R7PF_5.7A_30%

LDO
VIN

VCC
+3VALWP

4.7_1206_5%~D
4.7UH_SIL104R-4R7PF_5.7A_30% 33 19 1 2
TP PVCC

5
6
7
8

1
1

8
7
6
5

@ PR242
680P_0603_50V7K~D 4.7_1206_5%~D
DH3 26 15 DH5
UGATE2 UGATE1

@ PR241
PR243 PR245 PQ69
0_0402_5%~D

PQ68 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8


BOOT2 BOOT1
2

1 AO4712_SO8 0_0603_5%~D
0_0603_5%~D

2
2

2
PR244

61.9K_0402_1%~D
4

2
PC204 + 4 PC205 PC208

2
680P_0603_50V7K~D
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

1
1

PR246
330U_D3L_6.3VM_R25M LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC206

PC209
3
2
1

2
+ PC210

1
2
3
DL3 23 18 DL5 @ 330U_D3L_6.3VM_R25M

1
@ LGATE2 LGATE1
2
10K_0402_1%~D
2

PGND 22

2
PR247

C FB3 30 C
OUT2

10K_0402_1%~D
PR248
OUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC211 0.22U_0603_10V7K~D
BYP 9
8 LDOREFIN @ PR249 0_0402_5%~D
Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical) SKIP 29 2 1 VL
PR250 0_0402_5%~D
1 2
3.3VALWP PD10 PR251
20 NC POK2 28

Imax=6A VS RLZ5.1B_LL34 100K_0402_1%~D


POK
1 2 1 2 4 EN_LDO POK1 13 PR253
2
200K_0402_5%~D

255K_0402_1%
Iocp=9A
2
PR252

PC212 14 12 ILM1 2 1
0.22U_0603_25V7-K EN1 ILIM1
PR255
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2
B 255K_0402_1% B

0_0402_5%~D
@ PR254 ISL6237IRZ-T_QFN32_5X5

21
VL 0_0402_5%~D
806K_0603_1%

PR256
Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)
2

1
PR257

2VREF_ISL6237 1

PR260

1
@ 47K_0402_5%~D PR258
PR259 PC285 @
5VALWP
1

2 1 1 2 1U_0603_10V6K~D Imax=6A
2

2VREF_ISL6237 2
50 MAINPWON 0_0402_5%~D
0_0402_5%~D
0.047U_0402_16V7K~N

PC213
Iocp=9A
1

1
2

0.047U_0603_16V7K~D

PC214
2

PQ79
TP0610K-T1-E3_SOT23-3
@
1 3

PD16
1 2

1SS355TE-17_SOD323-2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
+3VALWP, +5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL80 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 45 of 9
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn PC240

1
PC239 1U_0402_6.3V6K~D

1
1U_0402_6.3V6K~D

2
2
PGOOD1 PGOOD2 串1K電組 上@ 2
PR288
1 1
PR289
2
+5VALWP +5VALWP
2.2_0603_1%~D 2.2_0603_1%~D

PJP21 +5VALWP

1
@ JUMP_43X118 PC241 PC242
D D
1 1 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
B+ 2 2
ISL6228_B+

2
1
PR290 2 PR291 2 PR292

680P_0402_50K X7R~D
470P_0402_50V8J~D
ISL6228_B+ 1 1 ISL6228_B+
1

1
PC290

PC291
1K_0402_1%~D 10_0603_1% 10_0603_1%
@
2

2
PC244
1000P_0402_50V7K~D PR294

1
PR293 18.2K_0402_1%~D
1000P_0402_25V8J 3.3K_0402_5%~D PR295 PC243 22K_0402_1%~D
90.9K_0402_1%~N 1000P_0402_50V7K~D
PR296

1
PC245
2 1 1 2

1
PR297

1
2 1
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
68K_0402_1% GND_T

2
PR298 PR300 3.3K_0402_5%~D
1 2 8 FB1 PGOOD2 28 2 PR299 1 +5VALWP 34K_0402_1% PR301
1000P_0402_25V8J
PC246
22.6K_0402_1% 1K_0402_1%~D 2 1 1 2

1
@
ISL6228_B+ PR302
9 VO1 FB2 27 1 2

68K_0402_1%
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

1
PC249

PC247

8
7
6
5

PC248 PR303
0.033U_0402_16V7K~D 10 26 1 2
2

OCSET1 VO2
1 2
PQ74 24K_0402_1%~D
C AO4466_SO8 C
2

4
PR305 VCCPP_EN 11 25
22.6K_0402_1% PR306 EN1 PU18 OCSET2 PR307
1 2 0_0402_5%~D
ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B+
1

1
2
3

PL26 0_0603_5%~D SYSON 28,29,41

+VCCPP 1 2 LX_VCCPP 12 24 0.022U_0402_16V7K~D


PHASE1 EN2 PC252

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

5
6
7
8

1
PC253

PC250
1.5UH_MPL73-1R5_9A_20% 1 2 PC254
8
7
6
5
220U_D2_4VM

1 PR308 1 2
4.7_1206_5%~D @ 0.01U_0402_25V7K~D

2
+
PC251

PQ75 UG_VCCPP 13 23 PQ76


UGATE1 PHASE2

2
AO4712_SO8 AO4466_SO8 PR309
680P_0603_50V8J~D
2

4 24K_0402_1%~D
2 PR311
4
1

PC255

0_0603_5%~D
2 1 2 1BST_VCCPP
14 22 UG_1.8V 1 2

1
BOOT1 UGATE2 PL27
2

3
2
1
PR310
LGATE1

LGATE2
PC256 LX_1.8V 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.8VP
1
2
3

1
0_0603_5%~D

220U_D2_4VM
DCR 15m ohm(max) 0.1U_0402_16V7K~D
PR312 1.5UH_MPL73-1R5_9A_20%

5
6
7
8
4.7_1206_5%~D
VCCPP 1
15

16

17

18

19

20

21
Imax=7A +

PC260
680P_0603_50V8J~D
PC259

2
PQ77
PR313 AO4712_SO8 DCR 15m ohm(max)

1
2

PC261
Iocp=11.59A +5VALWP +5VALWP BST_1.8V 1 2 1 2 4
1.8VP
2

2
0_0603_5%~D

2
0.1U_0402_16V7K~D
PC257 PC258 Imax=9A
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
1

3
2
1
Iocp=12.31A
LG_VCCPP LG_1.8V

B B
PR314
0_0402_5%~D
2 1 VCCPP_EN
28,29,41,47,48 SUSP#
0.01U_0402_25V7K~D
1

PC262
2

A A

Security Classification Compal Secret Data


Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
+1.8VP/+VCCPP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JAL80 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 46 of 9
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn PC215 PC216

1
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
VGA@

2
PGOOD1 PGOOD2 串1K電組 上@ 2
PR261
1 1
PR262
2
+5VALWP +5VALWP
2.2_0603_1%~D 2.2_0603_1%~D
VGA@

PJP22 +5VALWP
@ JUMP_43X118

1
1 1 PC217 PC218
D B+ 2 2 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D D
ISL6228_B++
VGA@

2
1
PR263 ISL6228_B++ 2 PR264 1 2 PR265 1 ISL6228_B++
1K_0402_1%~D 10_0603_1% 10_0603_1%
@ VGA@

2
PC220
1000P_0402_50V7K~D PR267

1
PR266 18.2K_0402_1%~D
1000P_0402_25V8J 3.3K_0402_5%~D PR268 PC219 22K_0402_1%~D VGA@
45.3K_0402_1%~D 1000P_0402_50V7K~D
PR269

1
PC221 VGA@
2 1 1 2

1
PR270

1
2 1
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
68K_0402_1% GND_T

2
PR271 PR273 3.3K_0402_5%~D
1 2 8 28 78.7K_0402_1%~D PR274 1000P_0402_25V8J
FB1 PGOOD2 VGA_PWGOD 41 PC222
VGA@ VGA@
17.8K_0402_1%~D 2 1 1 2 VGA@

1
ISL6228_B++ PR275
9 VO1 FB2 27 1 2

71.5K_0402_1%~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

1
PC225

PC223

VGA@
8
7
6
5

PC224
0.033U_0402_16V7K~D 10 26 1 2
2

OCSET1 VO2

2
1 2
PQ70 PR276 PR277
C AO4466_SO8 24K_0402_1%~D 10_0402_5%~D C
2

4 VGA@ VGA@
PR278 1.5V_EN 11 25

1
17.8K_0402_1%~D PR279 EN1 PU17 OCSET2 PR280
1 2 0_0402_5%~D
ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B++
1

1
2
3

PL23 0_0603_5%~D VGA@ VGA_ON 29

+1.5VSP 1 2 LX_1.5V 12 24
PHASE1 EN2 PC228

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

5
6
7
8

1
PC229

PC226
1.5UH_MPL73-1R5_9A_20% 1 2
8
7
6
5
220U_6.3V_M

1 PR281 1 2 PC230
@ 4.7_1206_5%~D VGA@ 0.01U_0402_25V7K~D 0.022U_0402_16V7K~D

2
+
PC227

PQ71 UG_1.5V 13 23 VGA@


UGATE1 PHASE2

2
AO4712_SO8 PQ72 PR282
680P_0603_50V8J~D
2

4 24K_0402_1%~D
2 PR284 AO4466_SO8
4 VGA@
1

PC231

0_0603_5%~D
2 1 2 1BST_1.5V 14 22 UG_VGA 1 2 VGA@ VGA@ VGA@

1
@ BOOT1 UGATE2 VGA@ PL24
2

3
2
1
LGATE1

LGATE2
PC232 PR283 LX_VGA 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+VGA_COREP
1
2
3

220U_D2_4VM
DCR 15m ohm(max) 0.1U_0402_16V7K~D
0_0603_5%~D
PR285 1.5UH_MPL73-1R5_9A_20%

5
6
7
8
1.5VP VGA@
4.7_1206_5%~D VGA@ 1
15

16

17

18

19

20

21
Imax=5A +

PC233
2
PC234

680P_0603_50V8J~D
PR286
DCR 15m ohm(max)

1
2

PC237
Iocp=9.13A +5VALWP +5VALWP BST_VGA 2 1 1 2 4
+VGA (1.15V) VGA@
2

2
2.2_0603_5%~D 0.1U_0402_16V7K~D PQ73

2
PC235 PC236 VGA@ VGA@ AO4712_SO8 Imax=9A
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
1

3
2
1
VGA@ VGA@ VGA@
Iocp=12.31A
LG_1.5V LG_VGA

B B
PR287
0_0402_5%~D
2 1 1.5V_EN
28,29,41,46,48 SUSP#
0.01U_0402_25V7K~D
1

PC238

@
2

A A

Security Classification Compal Secret Data


Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
+1.5VP/+VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JAL80 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 47 of 9
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn
+5VALW +1.5VS

PJP16
VGA@

2
@ JUMP_43X118

1U_0603_10V6K~D

2
1

PC263

1
D +1.8V D

1U_0603_10V6K~D
1

PC264

1
VGA@
PJP17

1
2
@ JUMP_43X118

6
PU19

2
5

VCNTL
VIN
7

2
POK
VOUT 3 +1.2VSP
PU20

1K_0402_1%~D

1U_0603_10V6K~D

1U_0603_10V6K~D
VOUT 4 1 VIN VCNTL 6 +3VALW
PR315

1
PC266

PC267

4.7U_0805_6.3V6K~N
1 2 8 EN FB 2 2 GND NC 5

1
28,29,41,46,47 SUSP#

VGA@

PR316

PC268
PC265

GND

1
0_0402_5%~D 9 VGA@ 3 7

2
VIN VREF NC

2
VGA@ PR317 4 8

2
APL5913-KAC-TRL_SO8~N 0.01U_0402_25V7K~D 1K_0402_1%~D VOUT NC
VGA@ VGA@ 9

2
TP
1

PC269 APL5331KAC-TRL_SO8~N

2K_0402_1%~D
0.1U_0402_16V7K~D PR318
2

@ +0.9VSP

1
D

PR319
0_0402_5%~D

1U_0603_10V6K~D
VGA@ 1 2 2

1
32,40,41 SUSP

PC271
G PR320 PC270

2
S

2
1
PQ78

2
PC272
@

2
C 0.1U_0402_16V7K~D C
RHU002N06_SOT323-3 0.1U_0402_16V7K~D
1K_0402_1%~D

+5VALW +1.5VS

PJP18

2
@ JUMP_43X118
1U_0603_10V6K~D

2
1

PC273

1
2

1U_0603_10V6K~D
1

PC274
2
6

PU21
5
VCNTL

VIN
7 POK
VOUT 3 +1.25VSP
1.15K_0402_1%

1U_0603_10V6K~D
VOUT 4
PR321
1

1 2 8 2 PC276
28,29,41,46,47 SUSP# EN FB
PR322

PC275
GND

0_0402_5%~D 9
2

VIN
1

B APL5913-KAC-TRL_SO8~N 0.01U_0402_25V7K~D B
1

PC277
1

2.05K_0402_1%~D

0.1U_0402_16V7K~D
2

@
PR323
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
+1.25VSP / +0.9VSP/ +1.2VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL80 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 48 of 9
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn +5VS

2
5

5
PC112

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR142 +CPU_B+
PL13

29
VR_ON
2 1 1_0603_5%~D
FBMA-L18-453215-900LMA90T_1812
@ 1 2 B+

1
5600P_0402_25V7K
1 1

100U_25V_M

100U_25V_M
10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
1U_0603_10V6K~D
D D

1
+ +

PC114

PC115

PC116

PC113

PC155
PR143 499_0402_1%~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D
1

1
PC118

PC119
1U_0603_10V6K~D
7,19 DPRSLPVR 1 2

1
PC117

PC120

2
PR144 0_0402_5%~D @ 2 2

2
5,7,18 H_DPRSTP# 1 2

5
PR1460_0402_5%~D

PR1470_0402_5%~D

PR1480_0402_5%~D

PR1490_0402_5%~D

PR1500_0402_5%~D

PR1510_0402_5%~D

PR1520_0402_5%~D
PR145 0_0402_5%~D

1
16 CLK_EN# 1 2

1
0_0402_5%~D
+3VS PR154 0_0402_5%~D PQ43

PR153
1 2 4 SI7686DP-T1-E3_SO8

2
+3VS

1U_0603_10V6K~D
PC122

2
1.91K_0402_1%~D

1
PC121
PR155 0.22U_0603_10V7K~D P_0.36H_ETQP4LR36WFC_24A_20%

3
2
1
1 BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

PR156

4.7_1206_5%~D
PR157

5
6
7
8

5
6
7
8

1
10K_0402_1%~D
3.65K_1206_1%
2.2_0603_5%~D PL14

1
PR158

PR160
499_0402_1%~D

49

48

47

46

45

44

43

42

41

40

39

38

37

D
D
D
D

D
D
D
D

PR159
PR161
2

1_0402_5%~D

3V3
GND

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
DPRSLPVR

VR_ON
1

680P_0603_50V8J~D
PQ44 PQ45

1 2

2
G

G
S
S
S

S
S
S
7,19,29 VGATE 1 36 FDS6676AS_SO8 PR162 @ 0_0402_5%~D

2
PGOOD BOOT1

PC123
5 H_PSI# 1 2

4
3
2
1

4
3
2
1
2 35 UGATE_CPU1 VSUM PC124
1U_0603_10V6K~D PC147 PR181 10K_0402_1%~D PSI# UGATE1
1 2

2
POW_MON 1 2 1 2 3 34 PHASE_CPU1 VCC_PRM
PMON PHASE1 ISEN1
C PR164 147K_0402_1%~D 4 33 0.22U_0603_16V7K~D C
RBIAS PGND1 FDS6676AS_SO8
1 2
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
PR165 @ 4.22K_0402_1% PH2

1
1 2 1 2 6 NTC PVCC 31

PC125

PC126

PC127
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2

2
SOFT LGATE2 PQ46
1 2 @
@ 0.015U_0402_16V7K PC128 8 29 SI7686DP-T1-E3_SO8
0.068U_0603_50V7K~N PC129 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR166 11.5K_0402_1%~D 10 27 UGATE_CPU2 P_0.36H_ETQP4LR36WFC_24A_20%
COMP UGATE2 PR167 PC130
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
PC131 FB BOOT2 PL15
1 2

5
6
7
8

5
6
7
8

1
DROOP

1000P_0402_50V7K~D 12 25 2.2_0603_5%~D
0.22U_0603_10V7K~D
FB2 NC

1
VDIFF

VSUM

ISEN2

ISEN1
VSEN

10K_0402_1%~D
PR169 6.81K_0402_1%~D PR168
GND

D
D
D
D

D
D
D
D
VDD
RTN

DFB

1
VIN

4.7_1206_5%~D

3.65K_1206_1%

PR170
PR172
VO

1 2

PR171
1 2 PU11 PQ47 PQ48 1_0402_5%~D
13

14

15

16

17

18

19

20

21

22

23

24

1 2
G

G
S
S
S

S
S
S

2
PC132 1000P_0402_50V7K~D

4
3
2
1

4
3
2
1

2
29.1
ISEN1 PC133 PR173 @ 0_0402_5%~D
ISEN2 680P_0603_50V8J~D 1 2

2
PR175 97.6K_0402_1%~D PC134 470P_0402_50V7K~D 1 2 +5VS
1

1 2 2 1 VSUM PC135
1

PR174 1_0603_5%~D 1 2
PR176 PC136
B 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D B
1 2
2

FDS6676AS_SO8 FDS6676AS_SO8
2

PC137 220P_0402_50V7K~D VCC_PRM


ISEN2
PR178
PR177 PC138 1000P_0402_50V7K~D
1 2 1 2 1 2 +CPU_B+
1

255_0402_1%~D
1 2 PC139 10_0603_5%~D
2

PR179 1K_0402_1%~D 0.1U_0603_25V7K~D


PC140 0.022U_0603_25V7K
5 VCCSENSE 1 2 1 2
VSUM
1

PR180 0_0402_5%~D
1

2.61K_0402_1%~D

PC141 PC142
@0.022U_0603_25V7K
PR182

0.022U_0603_25V7K
2

1 2
5 VSSSENSE PR183 0_0402_5%~D
2
1

11K_0402_1%~D

PC143 180P_0402_50V8J~D
PR185

1 2
2

1 2 1 2 PH3
2

PR186 1K_0402_1%~D PR187 3.57K_0402_1%~D 10KB_0603_ERTJ1VR103J


PC144 0.068U_0603_50V7K~N
1

VCC_PRM 1 2

PC146 0.22U_0603_10V7K~D
A A
PC145 2 1 2 1
0.22U_0603_16V7K~D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Thursday, January 10, 2008 Sheet 49 of 9
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn +3VALWP

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

2
PD12

PD13

PD14

PD15
@

D BATT+ D
BATT++

1
@
@ @ Battery Connect/OTP
BATT+

PL28
HCB4532KF-800T90_1812
1 2 BATT++
+3VALWP

100P_0402_50V8J~D
1

1
100P_0402_50V8J~D
1

PC289
PC279
PC288

PC278 1000P_0402_50V7K~D
2

2
0.01U_0402_25V7K~D
2

PR324 Place clsoe to EC pin


47K_0402_5%~D
1 2 BATT_TEMP
BATT_TEMP 29

1
PR325
PJPB1 battery connector

2
1K_0402_5%~D
PC280
0.1U_0402_16V7K~D

1
SMART PJP19

@
1 PR326
Battery: 1
2 2
3 3cell/4cell# 1K_0402_5%~D
3 3cell/4cell# 44
4 2 1
1.BAT+
4
5 5 1 2 +3VALWP
@
2.BAT+ 6 6
7 PR327
7
3.ID 10 GND 8 8 6.49K_0402_1%~D
11 9
4.B/I GND 9

C 5.TS SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 29 C


6.SMD PR328
100_0402_5%~D
7.SMC
8.GND CPU
9.GND 1 2 EC_SMB_CK1 29 PH1 under CPU botten side :
PR329
100_0402_5%~D
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS
BATT+
1

2
PR330

1
453K_0402_1%~D PC281
0.1U_0603_25V7K~D
CPU

1
VS
2

PR331
10.7K_0402_1%~D VL

2
1
0.01U_0402_25V7K~D

PR333
PR332 147K_0402_1%~D

2
499K_0402_1%~D 1 2
1

PC282

PR334
B 205K_0402_1%~D B
2
2

PR335

1
8
61.9K_0402_1%~D
1 2 3 PD11

P
+
8

LM358ADR_SO8 1 1 2
5 1 2 2
0 MAINPWON 45
P

+ VL -

G
7 1SS355_SOD323-2
0 PR336 PU22A
6

4
-
G

1
29 BATT_OVP 150K_0402_1%~D LM358ADR_SO8
1

PH4
4

1
PU22B 100K_0603_1%_TH11-4H104FT

1
PR337
86.6K_0402_1% PC283 PR338

2
1000P_0402_50V7K~D 150K_0402_1%~D
2

2
2
PC284
1U_0603_10V6K~D

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
BATTERY CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL80 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 50 of 9
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List )


http://laptopblue.vn Page 1/1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal board rev update to 0.2 R231 change to 15K & R232 pop 0.2

D 2 40 P40-OZ129_Card Reader/1394 07/10/30 compal CardBus vendor change CardBus R5C833 change to OZ129 0.2 D

3 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Change pull up resistance Change EC pin17,18 pull up to 4.7Kohm 0.2

4 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Need pull up NET MIC_DIAG pull up R to 10Kohm 3VS 0.2

5 13,14 DDR2 SODIMM-I,II Socket 07/10/30 compal Change Capacitance Change C84,C189 to SGA00002680 330U 0.2

6 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal EC update rev EC change to 926C 0.2

7 28 P28-Express card 07/10/30 compal Express card can't detect POWER IC(U11) ADD PIN10 CPUSB# PIN9 EXPR_CPUSB#S 0.2

8 32 P32-USB/ BlueTooth/ 07/10/30 compal Bluetooth can't detect BLUETOOTH CONN USB+- change 0.2
FP/ Felica
9 42 P42-Screws 07/10/30 compal FIDUCAL no enough ADD FIDUCAL*4 0.2

10 41 P41-DC/DC Interface 07/10/30 compal Need pull down SYSON pull down 10K ohm 0.2

11 41 P41-DC/DC Interface 07/11/12 compal USB can't detect SUSP change to 5VALW(Q32) 0.2

12 06 P06-Merom(3/3)-GND/Bypass 07/11/12 compal Change CPU High Frequence Decoupling Capacitance C195 change to C1150~C1181 0.2
C C
13 41 P41-DC/DC Interface 07/11/13 compal +1.8VS Discharge error +1.8VS Discharge circuit Q65 net change to VGA_PWGOD# 0.2

14 41 P41-DC/DC Interface 07/11/16 compal Delete Remove SIM card connector 0.2

15 42 P42-Screws 07/11/16 compal Change Holea size Change Holea size 2.5 to 2.8, change 3.5 to 3.8 0.2

16 31 P31-PWR_OK/ BTN/ KB / 07/11/21 compal Change Touch PAD/B connector Touch PAD/B connector change net 0.2
TouchPad
17 15 P15-CRT Conn.& LCD Conn. 07/11/21 compal Add LCD control pin Add LCD control pin LCD_CBL_DET# & LCD_TST & LCD_VCC_TEST_EN 0.2

18

19

20

21

22

B 23 B

24

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 51 of 49
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List )


http://laptopblue.vn Page 1/1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 41 +3VALWP/+5VALWP 07/11/19 COMPAL When in the DC-mode , shut down the system ,5valwp output not turn off ADD PQ79 to turn off 5VALWP wehn shut down the system in the DC-mode

D 2 44 Charge 07/12/26 COMPAL change charge voltage can to adjust Change PR53 from 15K to 4.3K D

3 49 CPU_CORE 07/12/26 COMPAL Increase Resistor 0ohm on CPU_CORE high side gate for EMI request ADD PR163 PR184

4 45 +3VALWP/+5VALWP 07/12/26 COMPAL DEL PL19


The schematic location is wrong

10

11

12
C C
13

14

15

16

17

18

19

20

21

22

B 23 B

24 4

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PW PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3682P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 10, 2008 Sheet 52 of 9
5 4 3 2 1

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