Professional Documents
Culture Documents
1 1
KTKAA
2 Los Angeles 10/10G 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 1 of 43
A B C D E
A B C D E
Compal Confidential
Model Name : KTKAA Fan Control Intel Penryn Processor Thermal Sensor Clock Generator
page 4
File Name : LA-4571P ADT7421 SLG8SP556VTR
uPGA-478 Package page 4 page 16
1
TV (Socket P) page 4,5,6
1
page 18
CRT FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)
page 18
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
VGA/B LCD Conn. Intel Cantiga Dual Channel
page 17 BANK 0, 1, 2, 3 page 14,15
ATI/M82,64bit with 128/256MB
ATI M86,128bit with 256M/512MB PCIE-Express 16X PM45/GM45/GL40 1.8V DDRII 533/667/800
3 PCIe 1x 3
JMB380 5IN1/1394 1.5V 2.5GHz(250MB/s)
3.3V 33 MHz
PCIe port 6 page 31
Power Circuit DC/DC
LPC BUS
HD Audio 3.3V 24.576MHz/48Mhz
page 36,37,38,39 I2C from SB
40,41,42 FM tuner Conn
page 29 MDC 1.5 Conn HDA Codec
ALC272
Debug Port ENE KB926 D1 page 26 page 29
CRT/B Finger print/B
page 18 page 26 page 33 page 32
USB/B AMP.
page 26
Touch Pad SPI ROM CIR Int. TPA6017
Int.KBD MIC CONN MIC CONN HP CONN
page 34 page 33 page 33 page 32 page 30 page 30 page 30 page 30
Power/B
page 34
4 SPK CONN 4
page 30
FUN/B
page 34
Security Classification Compal Secret Data Compal Electronics, Inc.
2008/09/19 2009/09/19 Title
LED/B Issued Date Deciphered Date
SCHEMATIC MB A4571
page 32 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 2 of 43
A B C D E
A B C D E
VIN Adapter power supply (19V) ON ON ON OFF S1(Power On Suspend) LOW HIGH HIGH HIGH
1 1
B+ AC or battery power rail for power circuit. ON ON ON ON
S3 (Suspend to RAM) LOW LOW HIGH HIGH
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH
+1.05VS 1.05V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF OFF G3 LOW LOW LOW LOW
+3VALW 3.3V always on power rail ON ON ON OFF
+3VL 3.3V always on power rail ON ON ON ON
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON OFF
Function 2nd HDD LAN Mini card RJ11/FM tuner 3G SIM slot
+5VL 5V always on power rail ON ON ON ON
2 +5V_SB 5V power rail for SB ON ON OFF OFF (2H) (E) (C) (D2) (D3) (R) (M) (G) 2
description
+5VS 5V switched power rail ON OFF OFF OFF
explain 10/100M Giga Two Crads three Crads RJ11 FM
+VSB VSB always on power rail ON ON ON OFF
+RTCVCC RTC power ON ON ON ON BTO 2HDD@ 8102E@ 8111C@ WLAN@ GPS@ NAND@ MDC@ FM@ 3G@
+CPU_CORE Core voltage for VGA chip ON ON OFF OFF
+VGA_PCIE_1.1VS 1.1V switched power rail for VGA PCIE ON ON OFF OFF
Function HDMI TV-out CIR CAMERA & MIC Finger printer
+1.8VS 1.8V power rail for VRAM ON ON OFF OFF
description (Y) (S) (I) (X) (F)
External PCI Devices BTO IHDMI@ NIHDMI@ HDMI@ H@ TVOUT@ CIR@ CAM@ MIC@ FP@
need to confirm
@
7 H_A#[3..16] +3VS
JCPUA
H_A#3 J4 H1
A[3]# ADS# H_ADS# 7
ADDR GROUP_0
H_A#4 L5 E2
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 7
H_A#6
0.1U_0402_16V4Z
K5 A[6]# 1
H_A#7 M3 H5
A[7]# DEFER# H_DEFER# 7 C1
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 U1
A[9]# DBSY# H_DBSY# 7 2
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 1 8
A[12]# VDD SMCLK EC_SMB_CK2 17,32
CONTROL
D H_A#13 L2 D20 H_IERR# R1 1 2 56_0402_5% +1.05VS D
H_A#14 A[13]# IERR# H_INIT# H_THERMDA
P4 A[14]# INIT# B3 H_INIT# 21 2 DP SMDATA 7 EC_SMB_DA2 17,32
H_A#15 P1 C2
H_A#16 A[15]# H_THERMDC
R1 A[16]# LOCK# H4 H_LOCK# 7 1 2 3 DN ALERT# 6 1 2 +3VS
M1 2200P_0402_50V7K R2 10K_0402_5%
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET# CPU_THERM# 4 5 @ Reserve for source control
RESET# H_RESET# 7 THERM# GND
7 H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 7
H2 F4 R3
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
7 H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2 7 +3VS 1 2
J3 G2 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7 if use XDP,these resistor are 51ohm
7 H_REQ#4 L1 REQ[4]#
Address:0100_1100 EMC1402-1
G6 +1.05VS
7 H_A#[17..35] HIT# H_HIT# 7 Address:0100_1101 EMC1402-2
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 7
H_A#18 U5 XDP_TMS 1 2
H_A#19 A[18]# R4 54.9_0402_1%
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1
H_A#20 W6 AD3 XDP_TDI 1 2
H_A#21 A[20]# BPM[1]# R5 54.9_0402_1%
U4 AD1
H_A#22 Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4
+5VS
FAN Control Circuit
XDP/ITP SIGNALS
H_A#23 U1 AC2 XDP_TCK 1 2
H_A#24 A[23]# PRDY# R6 54.9_0402_1%
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK XDP_TRST# 1 2 1A
H_A#26 A[25]# TCK XDP_TDI R7 54.9_0402_1%
T3 A[26]# TDI AA6
H_A#27 W2 AB3
A[27]# TDO
1
H_A#28 W5 AB5 XDP_TMS +1.05VS 1 2
H_A#29 A[28]# TMS XDP_TRST# R8 @ 56_0402_5%
Y4 A[29]# TRST# AB6 1SS355_SOD323-2
H_A#30 U2 C20 XDP_DBRESET# 1 2 2
A[30]# DBR# XDP_DBRESET# 22 D1
H_A#31 V4 R9 56_0402_5%
A[31]#
2
JFAN
B
H_A#32 W3 C3
2
H_A#33 AA4 A[32]# 10U_0805_10V4Z +FAN1
A[33]# THERMAL 1
1 1
E
C H_A#34 AB2 H_PROCHOT# 3 1 2 C
A[34]# OCP# 22 2
1
C
H_A#35 AA3 D21 H_PROCHOT# Q6 2 3
A[35]# PROCHOT# H_THERMDA @ MMBT3904_SOT23 U2 3
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC PROCHOT# PU: 68Ohm near CPU and MVP6. 1 8 D2 C4 4
H_A20M# THERMDC VEN GND @ 1000P_0402_25V8J GND
21 H_A20M# A6 A20M# 56Ohm near CPU if no used. 2 VIN GND 7 5 GND
1
ICH
H_FERR# A5 C7 +FAN1 3 6
21 H_FERR# H_THERMTRIP# 8,21
2
H_IGNNE# FERR# THERMTRIP# VO GND
21 H_IGNNE# C4 IGNNE# 32 EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
1 BAS16_SOT23-3
H_STPCLK# D5 10mil G990P11U_SOP8
21 H_STPCLK# STPCLK#
H_INTR C6 H CLK C5
21 H_INTR LINT0
H_NMI B4 A22 H_THERMDA, H_THERMDC routing together, 10U_0805_10V4Z R10 10K_0402_5%
21 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16 2
H_SMI# A3 A21 2 1 +3VS
21 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 16 Trace width / Spacing = 10 / 10 mil
M4 RSVD[01] FAN_SPEED1 32
N5 RSVD[02] 2
T2 RSVD[03]
V3 C6
RSVD[04]
RESERVED
B2 RSVD[05] 0.01U_0402_16V7K
1 @
D2 RSVD[06]
D22 RSVD[07]
Reserve for D3 RSVD[08]
debug F6 RSVD[09]
close to South
Bridge
Penryn
H_FERR# 2 1
B C596 @ 180P_0402_50V8J B
H_SMI# 2 1
C597 @ 180P_0402_50V8J
H_INIT# 2 1
C598 @ 180P_0402_50V8J
H_NMI 2 1
C599 @ 180P_0402_50V8J
H_A20M# 2 1
C600 @ 180P_0402_50V8J
H_INTR 2 1
C601 @ 180P_0402_50V8J
H_IGNNE# 2 1
C602 @ 180P_0402_50V8J
H_STPCLK# 2 1
C603 @ 180P_0402_50V8J
Reserve for
debug
close to CPU
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1
@
JCPUD
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
7 H_D#[0..15] @ A16 R5
H_D#[32..47] 7 VSS[005] VSS[086]
JCPUB A19 R22
H_D#0 H_D#32 VSS[006] VSS[087]
E22 D[0]# D[32]# Y22 A23 VSS[007] VSS[088] R25
H_D#1 F24 AB24 H_D#33 AF2 T1
H_D#2 D[1]# D[33]# H_D#34 VSS[008] VSS[089]
E26 D[2]# D[34]# V24 B6 VSS[009] VSS[090] T4
DATA GRP 0
D H_D#3 G22 V26 H_D#35 B8 T23 D
DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VSS[010] VSS[091]
F23 D[4]# D[36]# V23 B11 VSS[011] VSS[092] T26
H_D#5 G25 T22 H_D#37 B13 U3
H_D#6 D[5]# D[37]# H_D#38 VSS[012] VSS[093]
E25 D[6]# D[38]# U25 B16 VSS[013] VSS[094] U6
H_D#7 E23 U23 H_D#39 B19 U21
H_D#8 D[7]# D[39]# H_D#40 VSS[014] VSS[095]
K24 D[8]# D[40]# Y25 B21 VSS[015] VSS[096] U24
H_D#9 G24 W22 H_D#41 B24 V2
H_D#10 D[9]# D[41]# H_D#42 VSS[016] VSS[097]
J24 D[10]# D[42]# Y23 C5 VSS[017] VSS[098] V5
H_D#11 J23 W24 H_D#43 C8 V22
H_D#12 D[11]# D[43]# H_D#44 VSS[018] VSS[099]
H22 D[12]# D[44]# W25 C11 VSS[019] VSS[100] V25
H_D#13 F26 AA23 H_D#45 C14 W1
H_D#14 D[13]# D[45]# H_D#46 VSS[020] VSS[101]
K22 D[14]# D[46]# AA24 C16 VSS[021] VSS[102] W4
H_D#15 H23 AB25 H_D#47 C19 W23
D[15]# D[47]# VSS[022] VSS[103]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 C2 VSS[023] VSS[104] W26
7 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 7 C22 VSS[024] VSS[105] Y3
7 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 7 C25 VSS[025] VSS[106] Y6
7 H_D#[16..31] H_D#[48..63] 7 D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
H_D#16 N22 AE24 H_D#48 D8 AA2
H_D#17 D[16]# D[48]# H_D#49 VSS[028] VSS[109]
K25 D[17]# D[49]# AD24 D11 VSS[029] VSS[110] AA5
H_D#18 P26 AA21 H_D#50 D13 AA8
H_D#19 D[18]# D[50]# H_D#51 VSS[030] VSS[111]
R23 D[19]# D[51]# AB22 Resistor placed within D16 VSS[031] VSS[112] AA11
H_D#20 L23 AB21 H_D#52 D19 AA14
D[20]# D[52]# 0.5" of CPU pin.Trace VSS[032] VSS[113]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D23 AA16
DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VSS[033] VSS[114]
L22 D[22]# D[54]# AD20 should be at least 25 D26 VSS[034] VSS[115] AA19
H_D#23 M23 AE22 H_D#55 E3 AA22
H_D#24 P25
D[23]# D[55]#
AF23 H_D#56 mils away from any other E6
VSS[035] VSS[116]
AA25
H_D#25 D[24]# D[56]# H_D#57 VSS[036] VSS[117]
P23 D[25]# D[57]# AC25 toggling signal. E8 VSS[037] VSS[118] AB1
H_D#26 P22 AE21 H_D#58 E11 AB4
C H_D#27 T24
D[26]# D[58]#
AD21 H_D#59 COMP[0,2] trace width is E14
VSS[038] VSS[119]
AB8 C
D[27]# D[59]# VSS[039] VSS[120]
+1.05VS Close to H_D#28 R24 D[28]# D[60]# AC22 H_D#60 18 mils. COMP[1,3] trace E16 VSS[040] VSS[121] AB11
CPU pin H_D#29 L25 AD23 H_D#61 E19 AB13
H_D#30 T25
D[29]# D[61]#
AF22 H_D#62 width is 4 mils. E21
VSS[041] VSS[122]
AB16
AD26 D[30]# D[62]# VSS[042] VSS[123]
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 5 of 43
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
Near CPU CORE regulator
330U_D2_2VY_R7M 330U_D2_2VY_R7M +CPU_CORE
1 1 1 1
+CPU_CORE
within 500mils.
H_A#[3..35] 4
5 H_D#[0..63] U3A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
D H_D#7 F6 R16 H_A#11 D
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12
H_D#_33 H_ADS# H_ADS# 4
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
C H_D#36 Y12 A9 C
H_D#_36 H_BNR# H_BNR# 4
HOST
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# 4
H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BR0# 4
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# 4
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK 16
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16
H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPWR# 5
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# 4
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# 4
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# 4
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
Layout Note: AA3 H_D#_52
H_D#53 AD3 J8
H_RCOMP / +H_VREF / H_SWNG H_D#_53 H_DINV#_0 H_DINV#0 5
H_D#54 AD7 L3
H_D#_54 H_DINV#_1 H_DINV#1 5
trace width and spacing is 10/20 H_D#55 AE14 Y13
H_D#_55 H_DINV#_2 H_DINV#2 5
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 5
within 100 mils from NB H_D#57 AC1
H_D#58 H_D#_57
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 5
H_D#59 AC3 M7
+1.05VS +1.05VS H_D#_59 H_DSTBN#_1 H_DSTBN#1 5
H_D#60 AE11 AA5
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5
H_D#61 AE8 AE6
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5
H_D#62 AG2 H_D#_62
1
H_D#63 AD6 L9
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5
R22 M8
B H_DSTBP#_1 H_DSTBP#1 5 B
R21 221_0402_1% AA6
H_DSTBP#_2 H_DSTBP#2 5
1K_0402_1% H_SWNG C5 AE5
H_SWING H_DSTBP#_3 H_DSTBP#3 5
H_SWING=0.3125*VCCP H_RCOMP E3
1 2
2 2 H_CPUSLP#
B6 H_RS#0 4
2
H_RS#_0
H_RS#_1 F12 H_RS#1 4
Near B3 pin +H_VREF A11 C8
H_AVREF H_RS#_2 H_RS#2 4
B11 H_DVREF
CANTIGA ES_FCBGA1329
GMR3@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 7 of 43
5 4 3 2 1
5 4 3 2 1
1
000 = FSB1067 N36 RSVD2 SA_CK_1 AT21 DDRA_CLK1 14
R33 AV24 R26
RSVD3 SB_CK_0 DDRB_CLK0 15
0 = DMI x 2 T33 AU20 1K_0402_1%
COMPENSATION
RSVD4 SB_CK_1 DDRB_CLK1 15
CFG5 Internal pull-up 1 = DMI x 4 *(Default) AH9 RSVD5
AH10 AR24 DDRA_CLK0# 14
2
RSVD6 SA_CK#_0 +SM_RCOMP_VOH
0 = iTPM Host Interface is enabled can support disble by SW. AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1# 14
CFG6 Internal pull-up 1 = iTPM Host Interface is Disabled *(Default) AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0# 15
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# 15 1 1
1
0 = Intel Management Engine Crypto Transport Layer Security AL34 2.2U_0603_6.3V6K
RSVD10 C54 C55
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0 14
(TLS) cipher suite with no confidentiality AN35 AY28 DDRA_CKE1 14
0.01U_0402_16V7K R27
D RSVD12 SA_CKE_1 2 2 3.01K_0402_1% D
CFG7 Internal pull-up AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 15 SM_DRAMRST# would be
1 = Intel Management Engine Crypto TLS cipher suite with T24 BB36 DDRB_CKE1 15 needed for DDR3 only
2
RSVD14 SB_CKE_1
confidentiality *(Default) BA17 DDRA_SCS0# 14
SA_CS#_0 +SM_RCOMP_VOL
SA_CS#_1 AY16 DDRA_SCS1# 14
0 = Lane Reversal Enable B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# 15 For Cantiga 80 Ohm
1
CFG9 Internal pull-up 1 = Normal Operation *(Default) B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# 15 1 1
RSVD
0 = PCIe Loopback Enable BD17 C56 C57 R28
SA_ODT_0 DDRA_ODT0 14
CFG10 Internal pull-up 1 = Disable*(Default) AY17 0.01U_0402_16V7K 1K_0402_1%
SA_ODT_1 DDRA_ODT1 14 2 2
AY21 BF15 DDRB_ODT0 15
2
RSVD20 SB_ODT_O +1.8V +1.8V
01 = All Z Mode Enabled SB_ODT_1 AY13 DDRB_ODT1 15
CFG[13:12] 00 = Reserved
10 = XOR Mode Enabled BG22 SMRCOMP R29 1 2 80.6_0402_1%
SM_RCOMP
2
Internal pull-up 11 = Normal Operation*(Default) BG23 BH21 SMRCOMP# R30 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R31
BF23 RSVD23
0 = Dynamic ODT Disabled BH18 BF28 +SM_RCOMP_VOH 1K_0402_1%
RSVD24 SM_RCOMP_VOH +SM_RCOMP_VOL
CFG16 Internal pull-up 1 = Dynamic ODT Enabled *(Default) BF18 RSVD25 SM_RCOMP_VOL BH28
20mil
1
0 = Normal Operation AV42 +SM_VREF
SM_VREF SM_PWROK R32
CFG19 Internal pull-down 1 = DMI Lane Reversal Enable *(Default) SM_PWROK AR36 1 2 0_0402_5%
2
BF17 SM_REXT R33 1 2 499_0402_1% 1
SM_REXT R34
CFG20 0 = Only PCIE or [SDVO/DP/HDMI] is operational. * (Default) SM_DRAMRST# BC36
C58
Internal pull-down 1K_0402_1%
(PCIE/SDVO select) 1 = PCIE/[SDVO/DP/HDMI] are operating simu. 0.1U_0402_16V4Z
CLK_DREF_96M 2 @
B38 CLK_DREF_96M 16
1
DPLL_REF_CLK CLK_DREF_96M# CLK_DREF_96M PM@
DPLL_REF_CLK# A38 CLK_DREF_96M# 16 1 2
E41 CLK_DREF_SSC R575 0_0402_5%
DPLL_REF_SSCLK CLK_DREF_SSC 16
F41 CLK_DREF_SSC# CLK_DREF_96M# 1 PM@ 2
DPLL_REF_SSCLK# CLK_DREF_SSC# 16
R576 0_0402_5%
CLK
F43 CLK_DREF_SSC 1 PM@ 2
PEG_CLK CLK_MCH_3GPLL 16
E43 R577 0_0402_5%
C PEG_CLK# CLK_MCH_3GPLL# 16 C
CLK_DREF_SSC# 1 PM@ 2
R578 0_0402_5%
1
R36 2 1 1K_0402_5% MCH_CLKSEL1 R25 AE48 +3VS
5,16 CPU_BSEL1 CFG_1 DMI_RXP_2 DMI_ITX_MRX_P2 20
R37 2 1 1K_0402_5% MCH_CLKSEL2 P25 AH40 R38
5,16 CPU_BSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 20
P20 Lane reversal 1K_0402_5%
CFG_3
P24 CFG_4 DMI_TXN_0 AE35 DMI_MTX_IRX_N0 20
1
R39 2@ 2.21K_0402_1% MCH_CFG_5
DMI
1 C25 AE43 DMI_MTX_IRX_N1 20
2
R40 MCH_CFG_6 CFG_5 DMI_TXN_1
1 2@ 2.21K_0402_1% N24 CFG_6 DMI_TXN_2 AE46 DMI_MTX_IRX_N2 20
R41 R42
R43 1 2@ 2.21K_0402_1% MCH_CFG_7 M24 AH42 54.9_0402_1% 1K_0402_5%
CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 20
2
CFG
B
E21 CFG_8
R44 1 2@ 2.21K_0402_1% MCH_CFG_9 C23 AD35 DMI_MTX_IRX_P0 20
2
CFG_9 DMI_TXP_0
E
R45 1 2@ 2.21K_0402_1% MCH_CFG_10 C24 AE44 MCH_TSATN# 3 1 MCH_TSATN_EC# 32
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 20
C
N21 AF46 Q7
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 20
R46 1 2@ 2.21K_0402_1% MCH_CFG_12 P21 AH43 MMBT3904_SOT23-3
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 20
R47 1 2@ 2.21K_0402_1% MCH_CFG_13 T21 CFG_13
R20 CFG_14
M20 CFG_15
+3VS R48 1 2@ 2.21K_0402_1% MCH_CFG_16 L21 CFG_16
H21 CFG_17
P29
GRAPHICS VID
R49 MCH_CFG_19 CFG_18
1 2 4.02K_0402_1% R28
R50 1 2@ 4.02K_0402_1% MCH_CFG_20 T28
CFG_19
CFG_20 GFX_VID_0 B33 Strap Pin Table
GFX_VID_1 B32
B GFX_VID_2 G33 SDVO_CTRLDATA 0 = SDVO interface disabled *(Default) B
GFX_VID_3 F33 (Internal pull-down) 1 = SDVO interface enabled
22 PM_SYNC# R51 1 2 0_0402_5% PM_SYNC#_R R29 E33
PM_SYNC# GFX_VID_4
+3VS 1 2 PM_EXTTS#_R 5,21,42 H_DPRSTP# B7 PM_DPRSTP# DDPC_CTRLDATA 0 = Digital display (iHDMI/DP) interface disabled
R52 10K_0402_5% (Internal pull-down) 1 = Digital display (iHDMI/DP) interface enabled
N33 PM_EXT_TS#_0 *(Default)
PM
2
BG48 AH37 R57
NC_1 CL_CLK CL_CLK0 22
Use VGATE for GMCH_PWROK BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 22
ME
1
R58 @ 0_0402_5% NC_4 CL_RST# +CL_VREF R61 PM@
BH47 NC_5 CL_VREF AH34 should be
1 2 BG47 +CL_VREF=0.355V 0_0402_5%
22,32 PM_PWROK NC_6 0.35 V
2
R59 0_0402_5% BE47 1 R62 PM@
NC_7 C59 R60 0_0402_5%
BH46 NC_8 DDPC_CTRLCLK N28
NC
1
NC_11 SDVO_CTRLDATA +3VS
BH43 NC_12 CLKREQ# K36 CLKREQ_3GPLL# 16
MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 8 of 43
5 4 3 2 1
5 4 3 2 1
D D
14 DDR_A_D[0..63] 15 DDR_B_D[0..63]
U3D U3E
DDR_A_D0 AJ38 BD21 DDR_B_D0 AK47 BC16
SA_DQ_0 SA_BS_0 DDR_A_BS0 14 SB_DQ_0 SB_BS_0 DDR_B_BS0 15
DDR_A_D1 AJ41 BG18 DDR_B_D1 AH46 BB17
SA_DQ_1 SA_BS_1 DDR_A_BS1 14 SB_DQ_1 SB_BS_1 DDR_B_BS1 15
DDR_A_D2 AN38 AT25 DDR_B_D2 AP47 BB33
SA_DQ_2 SA_BS_2 DDR_A_BS2 14 SB_DQ_2 SB_BS_2 DDR_B_BS2 15
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 14 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_B_D5 AJ48 AU17
SA_DQ_5 SA_CAS# DDR_A_CAS# 14 SB_DQ_5 SB_RAS# DDR_B_RAS# 15
DDR_A_D6 AM44 AY20 DDR_B_D6 AM48 BG16
SA_DQ_6 SA_WE# DDR_A_WE# 14 SB_DQ_6 SB_CAS# DDR_B_CAS# 15
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_WE# 15
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 DDR_A_DM[0..7] 14 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
SA_DQ_14 SA_DM_1 SB_DQ_14 DDR_B_DM[0..7] 15
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
DDR_A_D18 SA_DQ_17 SA_DM_4 DDR_A_DM5 DDR_B_D18 SB_DQ_17 SB_DM_2 DDR_B_DM3
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4
DDR_A_D20 SA_DQ_19 SA_DM_6 DDR_A_DM7 DDR_B_D20 SB_DQ_19 SB_DM_4 DDR_B_DM5
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6
B
SA_DQ_21 SB_DQ_21 SB_DM_6
A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] 14 SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] 15
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0
MEMORY
C DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1 C
MEMORY
AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48
DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 DDR_A_DQS#[0..7] 14 BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 DDR_A_DQS#1 DDR_B_D34 BH11 SB_DQ_34 DDR_B_DQS#[0..7] 15
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0
SYSTEM
DDR_A_D36
SYSTEM
AU13 SA_DQ_36 SA_DQS#_3 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 SB_DQ_36 SB_DQS#_1 AV47 DDR_B_DQS#1
DDR_A_D37 AV13 AY12 DDR_A_DQS#4 DDR_B_D37 BF11 BH41 DDR_B_DQS#2
DDR_A_D38 SA_DQ_37 SA_DQS#_4 SB_DQ_37 SB_DQS#_2
BD12 SA_DQ_38 SA_DQS#_5 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 SB_DQ_38 SB_DQS#_3 BH37 DDR_B_DQS#3
DDR_A_D39 BC12 AU9 DDR_A_DQS#6 DDR_B_D39 BG7 BG9 DDR_B_DQS#4
DDR_A_D40 SA_DQ_39 SA_DQS#_6 SB_DQ_39 SB_DQS#_4
BB9 SA_DQ_40 SA_DQS#_7 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 SB_DQ_40 SB_DQS#_5 BC2 DDR_B_DQS#5
DDR_A_D41 BA9 DDR_B_D41 BC6 AT2 DDR_B_DQS#6
DDR_A_D42 SA_DQ_41 DDR_B_D42 SB_DQ_41 SB_DQS#_6
AU10 SA_DQ_42 DDR_A_MA[0..14] 14 AY3 SB_DQ_42 SB_DQS#_7 AN5 DDR_B_DQS#7
DDR_A_D43 AV9 DDR_B_D43 AY1
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44 DDR_B_MA[0..14] 15
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0
DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 9 of 43
5 4 3 2 1
5 4 3 2 1
+3VS U3C
within 500 mils
1 2 1 GM@ 2 LCTLA_CLK L32
R499GM@ 0_0402_5% R64 10K_0402_5% L_BKLT_CTRL PEG_COMP 1
32 UMA_ENBKL G32 L_BKLT_EN PEG_COMPI T37 2 +1.05VS
1 GM@ 2 LCTLB_DATA LCTLA_CLK M32 T36 R65 49.9_0402_1%
R66 10K_0402_5% LCTLB_DATA L_CTRL_CLK PEG_COMPO
GM@ UMA_LCD_EDID_CLK
M33
UMA_LCD_EDID_CLK K33 L_CTRL_DATA 10mils
1 2 17 UMA_LCD_EDID_CLK L_DDC_CLK
R67 2.2K_0402_5% 17 UMA_LCD_EDID_DATA UMA_LCD_EDID_DATAJ33 H44 PCIE_GTX_C_MRX_N0
GM@ UMA_LCD_EDID_DATA UMA_ENVDD L_DDC_DATA PEG_RX#_0 PCIE_GTX_C_MRX_N1
1 2 1 2 17 UMA_ENVDD M29 L_VDD_EN PEG_RX#_1 J46
R500PM@ 0_0402_5% R68 2.2K_0402_5% L44 PCIE_GTX_C_MRX_N2
R69 1 GM@ PEG_RX#_2
2 LVDS_IBG C44 LVDS_IBG PEG_RX#_3 L40 PCIE_GTX_C_MRX_N3
D 2.37K_0402_1% Spacing=20mil B43 N41 PCIE_GTX_C_MRX_N4 D
R501 1 GM@ LVDS_VBG PEG_RX#_4
2 0_0402_5% E37 LVDS_VREFH PEG_RX#_5 P48 PCIE_GTX_C_MRX_N5
L_DDC_DATA R502 1 GM@ 2 0_0402_5% E38 N44 PCIE_GTX_C_MRX_N6
LVDS_VREFL PEG_RX#_6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N[0..15]
PEG_RX#_7 T43 PCIE_GTX_C_MRX_N[0..15] 17
0 = LFP Disable PCIE_GTX_C_MRX_N8
*(Default) 17 UMA_LCD_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P[0..15]
1 = LFP Card Present; PCIE disable 17 UMA_LCD_TXCLK+ C40 LVDSA_CLK PEG_RX#_9 Y43
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P[0..15] 17
17 UMA_LCD_TZCLK- B37 LVDSB_CLK# PEG_RX#_10 Y48
A37 Y36 PCIE_GTX_C_MRX_N11 PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] 17
17 UMA_LCD_TZCLK+ LVDSB_CLK PEG_RX#_11
LVDS
AA43 PCIE_GTX_C_MRX_N12
R64 PM@ PEG_RX#_12 PCIE_GTX_C_MRX_N13 PCIE_MTX_C_GRX_P[0..15]
17 UMA_LCD_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37 PCIE_MTX_C_GRX_P[0..15] 17
0_0402_5% E46 AC47 PCIE_GTX_C_MRX_N14
17 UMA_LCD_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
R66 PM@ G40 AD39 PCIE_GTX_C_MRX_N15
17 UMA_LCD_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
0_0402_5% A40
R67 PM@ LVDSA_DATA#_3 PCIE_GTX_C_MRX_P0
PEG_RX_0 H43
0_0402_5% H48 J44 PCIE_GTX_C_MRX_P1
17 UMA_LCD_TXOUT0+ LVDSA_DATA_0 PEG_RX_1
R68 PM@ D45 L43 PCIE_GTX_C_MRX_P2
17 UMA_LCD_TXOUT1+ LVDSA_DATA_1 PEG_RX_2
GRAPHICS
0_0402_5% F40 L41 PCIE_GTX_C_MRX_P3
17 UMA_LCD_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 P47
A41 N43 PCIE_GTX_C_MRX_P6
17 UMA_LCD_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
H38 T42 PCIE_GTX_C_MRX_P7
17 UMA_LCD_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
G37 U42 PCIE_GTX_C_MRX_P8
17 UMA_LCD_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 Y42 PCIE_GTX_C_MRX_P9
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 W47
B42 Y37 PCIE_GTX_C_MRX_P11
17 UMA_LCD_TZOUT0+ LVDSB_DATA_0 PEG_RX_11
G38 AA42 PCIE_GTX_C_MRX_P12
17 UMA_LCD_TZOUT1+ LVDSB_DATA_1 PEG_RX_12
F37 AD36 PCIE_GTX_C_MRX_P13
17 UMA_LCD_TZOUT2+ LVDSB_DATA_2 PEG_RX_13
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14
PCI-EXPRESS
AD40 PCIE_GTX_C_MRX_P15
C
PEG_RX_15 C
J41 PCIE_MTX_GRX_N0 C611 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
R70 PM@ PEG_TX#_0
1 GM@ 2 TV_COMPS PEG_TX#_1 M46 PCIE_MTX_GRX_N1 C612 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
0_0402_5% R70 75_0402_1% TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C613 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
R71 PM@ TVA_DAC PEG_TX#_2
1 GM@ 2 TV_LUMA TV_LUMA H25 TVB_DAC PEG_TX#_3 M40 PCIE_MTX_GRX_N3 C614 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
0_0402_5% R71 75_0402_1% TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C615 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
R72 PM@ TVC_DAC PEG_TX#_4
1 GM@ 2 TV_CRMA PEG_TX#_5 R48 PCIE_MTX_GRX_N5 C616 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
TV
0_0402_5% R72 75_0402_1% H24 N38 PCIE_MTX_GRX_N6 C617 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C618 1
PEG_TX#_7 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
U37 PCIE_MTX_GRX_N8 C619 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PEG_TX#_8 PCIE_MTX_GRX_N9 C620 1
PEG_TX#_9 U40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
C31 Y40 PCIE_MTX_GRX_N10 C621 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C622 1
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
AA37 PCIE_MTX_GRX_N12 C623 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C624 1
PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
R73 PM@ 1 2 UMA_CRT_B AD43 PCIE_MTX_GRX_N14 C625 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
0_0402_5% R73 GM@ 150_0402_1% PEG_TX#_14 PCIE_MTX_GRX_N15 C626 1
PEG_TX#_15 AC46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
R74 PM@ 1 2 UMA_CRT_G
0_0402_5% R74 GM@ 150_0402_1% UMA_CRT_B E28 J42 PCIE_MTX_GRX_P0 C627 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
18 UMA_CRT_B CRT_BLUE PEG_TX_0
R75 PM@ 1 2 UMA_CRT_R L46 PCIE_MTX_GRX_P1 C628 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
0_0402_5% R75 GM@ 150_0402_1% UMA_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 C629
18 UMA_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
M39 PCIE_MTX_GRX_P3 C630 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PEG_TX_3
VGA
UMA_CRT_R J28 M43 PCIE_MTX_GRX_P4 C631 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
18 UMA_CRT_R CRT_RED PEG_TX_4
R47 PCIE_MTX_GRX_P5 C632 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
+3VS PEG_TX_5 PCIE_MTX_GRX_P6 C633
G29 CRT_IRTN PEG_TX_6 N37 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
T39 PCIE_MTX_GRX_P7 C634 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
UMA_CRT_CLK UMA_CRT_CLK PEG_TX_7 PCIE_MTX_GRX_P8 C635
1 2 18 UMA_CRT_CLK H32 CRT_DDC_CLK PEG_TX_8 U36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
R76 GM@ 4.7K_0402_5% UMA_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C636 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
18 UMA_CRT_DATA CRT_DDC_DATA PEG_TX_9
R78 PM@ 1 2 UMA_CRT_DATA UMA_CRT_HSYNC J29 Y39 PCIE_MTX_GRX_P10 C637 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
B 18 UMA_CRT_HSYNC CRT_HSYNC PEG_TX_10 B
0_0402_5% R77 GM@ 4.7K_0402_5% 2 1UMA_CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C638 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
R78 GM@ 1.02K_0402_1% CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C639
PEG_TX_12 AA36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
1 2 UMA_CRT_HSYNC AA39 PCIE_MTX_GRX_P13 C640 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R503 PM@ 0_0402_5% UMA_CRT_VSYNC L29 PEG_TX_13 PCIE_MTX_GRX_P14 C641
18 UMA_CRT_VSYNC CRT_VSYNC PEG_TX_14 AD42 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
1 2 UMA_CRT_VSYNC AD46 PCIE_MTX_GRX_P15 C642 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
R504 PM@ 0_0402_5% PEG_TX_15
CANTIGA ES_FCBGA1329
GMR3@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 10 of 43
5 4 3 2 1
5 4 3 2 1
U3F
DDR2,667MHz,2600mA +NB_VCCAXG Extnal Graphic: 1210.34mA
DDR2,800MHz,3000mA Int. Graphic integrated Graphic: 1930.4mA
VCC_AXG_NTCF_1 W28 Intel Management Engine Link:508.12mA
+1.8V AP33 V28
VCC_SM_1 VCC_AXG_NCTF_2
DDR PWR AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26
10U_0805_10V4Z BH32 V26
VCC_SM_3 VCC_AXG_NCTF_4
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
1 1 BD32 VCC_SM_6 VCC_AXG_NCTF_7 W24
1 1 1 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
D + + BB32 W23 +1.05VS NB Core,Intel Management Engine Link U3G D
VCC_SM_8 VCC_AXG_NCTF_9
VCC
C78 C68 C69 C70 C71 BA32 V23
220U_D2_4VM_R15 VCC_SM_9 VCC_AXG_NCTF_10 220U_6.3V_M 0.22U_0402_10V4Z 0.1U_0402_16V4Z
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AG34 VCC_1
220U_6.3V_M 2 @ 2 2 2 2
AW32 AL21 1 1 AC34
VCC_SM_11 VCC_AXG_NCTF_12 VCC_2
AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21 1 1 1 1 AB34 VCC_3
AU32 W21 + + AA34
10U_0805_10V4Z 0.1U_0402_16V4Z VCC_SM_13 VCC_AXG_NCTF_14 C72 C73 C74 C75 C76 C77 VCC_4
AT32 V21 Y34
SM
VCC_SM_14 VCC_AXG_NCTF_15 GM@ VCC_5
AR32 U21 V34
VCC CORE
VCC_SM_15 VCC_AXG_NCTF_16 2 2 2 2 2 2 VCC_6
reserve for test AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20 U34 VCC_7
AN32 AK20 220U_6.3V_M 10U_0805_10V4Z 0.22U_0402_10V4Z AM33
VCC_SM_17 VCC_AXG_NCTF_18 VCC_8
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 Intel: VCC -- 220U*2, ESR 12mOhm AK33 VCC_9
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AJ33 VCC_10
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AG33 VCC_11
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AF33 VCC_12
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19 AE33 VCC_13
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19 AC33 VCC_14
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 AA33 VCC_15
BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 Y33 VCC_16
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 W33 VCC_17
GFX NCTF
POWER
AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19 V33 VCC_18
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 U33 VCC_19
AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19 AH28 VCC_20
AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19 AF28 VCC_21
AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17 AC28 VCC_22
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AA28 VCC_23
VCC_AXG_NCTF_37 AH17 AJ26 VCC_24
VCC_AXG_NCTF_38 AG17 AG26 VCC_25
VCC_AXG_NCTF_39 AF17 AE26 VCC_26
BA36 VCC_SM_36/NC VCC_AXG_NCTF_40 AE17 AC26 VCC_27
C
BB24 AC17 AH25 +1.05VS C
VCC_SM_37/NC VCC_AXG_NCTF_41 VCC_28
VCC
Could be NC for DDR2 Board.BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AG25 VCC_29
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AF25 VCC_30
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AG24 VCC_31 VCC_NCTF_1 AM32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AJ23 VCC_32 VCC_NCTF_2 AL32
AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16 AH23 VCC_33 VCC_NCTF_3 AK32
VCC_AXG_NCTF_47 AL16 AF23 VCC_34 VCC_NCTF_4 AJ32
AK16 T32 AH32
POWER
VCC_AXG_NCTF_48 VCC_35 VCC_NCTF_5
VCC_AXG_NCTF_49 AJ16 VCC_NCTF_6 AG32
VCC_AXG_NCTF_50 AH16 VCC_NCTF_7 AE32
8700mA VCC_AXG_NCTF_51 AG16 VCC_NCTF_8 AC32
VCC_AXG_NCTF_52 AF16 VCC_NCTF_9 AA32
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_10 Y32
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_11 W32
For layout placement un-mound C123 and mound C84 AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16 VCC_NCTF_12 U32
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_13 AM30
Int. Graphic AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_14 AL30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_NCTF_15 AK30
+1.05VS +NB_VCCAXG AA24 V16 AH30
VCC_AXG_7 VCC_AXG_NCTF_59 VCC_NCTF_16
Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16 VCC_NCTF_17 AG30
220U_D2_4VM_R15 10U_0805_10V4Z 0.47U_0603_10V7K 0.1U_0402_16V4Z AE23 AF30
VCC_AXG_9 VCC_NCTF_18
1 1 AC23 VCC_AXG_10 VCC_NCTF_19 AE30
1 1 1 1 1 1 AB23 AC30
NCTF
+ + VCC_AXG_11 VCC_NCTF_20
AA23 VCC_AXG_12 VCC_NCTF_21 AB30
C83 C84 C85 C86 C87 C88 C89 C90 AJ21 AA30
GM@ @ GM@ GM@ GM@ GM@ GM@ GM@ VCC_AXG_13 VCC_NCTF_22
AG21 VCC_AXG_14 VCC_NCTF_23 Y30
2 2 2 2 2 2 2 2
AE21 VCC_AXG_15 VCC_NCTF_24 W30
220U_D2_4VM_R15 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z AC21 V30
VCC_AXG_16 VCC_NCTF_25
AA21 VCC_AXG_17 VCC_NCTF_26 U30
VCC
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm Y21 VCC_AXG_18 VCC_NCTF_27 AL29
VCC
VCC_AXG_41 VCC_SM_LF1
PJ30 T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
1 1 2 2 VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5 CANTIGA ES_FCBGA1329
JUMP_43X39 @ PAD T3 AJ14 AM10 VCCSM_LF6 GMR3@
VCC_AXG_SENSE VCC_SM_LF6
PJ31 PAD T4 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7
1 1 C93 1 1 C95 1 1 C96 1
1 2 0.22U_0603_10V7K 0.47U_0603_10V7K 1U_0402_6.3V4Z
1 2
JUMP_43X39 @ C91 C92 C94 C97
0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.22U_0603_10V7K 2 2 1U_0402_6.3V4Z 2
A PJ32 A
1 2 CANTIGA ES_FCBGA1329
1 2 GMR3@
JUMP_43X39 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 11 of 43
5 4 3 2 1
5 4 3 2 1
CRT
D 10U_0805_10V4Z 10U_0805_10V4Z D
2 1 2 1 +3VS_TVCRT_DACBG A25 VCCA_DAC_BG VTT_7 U10
10U_FLC-453232-100K_0.25A_10%
1 10U_FLC-453232-100K_0.25A_10%
1 T10 Intel: VTT 270U*1 ESR 12mOhm
C110 PM@ C112 PM@ VTT_8
1 1 1 1 B25 VSSA_DAC_BG VTT_9 U9
C108 + 0_0805_5% C109 + 0_0805_5% T9
220U_B2_2.5VM C110 C111 220U_B2_2.5VM C112 C113 VTT_10
VTT_11 U8
@ GM@ GM@ Pin F47 @ GM@ GM@ Pin L48 T8
2 2 2 2 2 2 VTT_12
VTT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS_DPLLA F47 VCCA_DPLLA64.8mA VTT_13 U7
VTT_14 T7
+1.05VS_DPLLB L48 VCCA_DPLLB64.8mA VTT_15 U6
VTT_16 T6
PLL
+1.05VS +1.05VS_AHPLL +1.05VS +1.05VS_MPLL +1.05VS_AHPLL AD1 VCCA_HPLL 24mA VTT_17 U5
VTT_18 T5
R83 R84 +1.8V_TXLVDS
+1.05VS_MPLL AE1 VCCA_MPLL 139.2mA VTT_19 V3
2 1 2 1 LVDS VTT_20 U3
KC FBM-L11-160808-121LMT
1 0603 1 MBK2012121YZF_0805 1 1 13.2mA V2
VTT_21
A PEG A LVDS
1 2 C117 +1.8V_TXLVDS J48 U2
C115 C116 C114 R85 0.5_0805_1% C118 C118 PM@ VCCA_LVDS VTT_22
VTT_23 T2
4.7U_0805_10V4Z 10U_0805_10V4Z Pin AE12 1000P_0402_50V7K 0_0402_5% J47 V1
2 0.1U_0402_16V4Z
2 2 GM@ VSSA_LVDS VTT_24
Pin J48 VTT_25 U1
+1.05VS
Pin AD1 0.1U_0402_16V4Z GND to J47 414uA +1.05VS_AXF
+1.5VS_PEG_BG AD48 NB I/O R86
VCCA_PEG_BG
1 2
2 1 0_0603_5%
+1.5VS_PEG_BG +1.05VS_PEGPLL
50mA C119
PCIe&DMI +1.05VS_PEGPLL AA48 C120
VCCA_PEG_PLL 1U_0402_6.3V4Z 10U_0805_10V4Z
1 2 @
+1.5VS 1 2 1
R87 0_0603_5% 1 667MTs,480mA
C121 Pin B22
C122 0.1U_0402_16V4Z 800MTs,720mA
0.1U_0402_16V4Z
2
2
PCIe&DMI AR20 VCCA_SM_1
POWER
Pin AD48 Pin AA48 DDR2 +1.05VS_A_SM AP20 VCCA_SM_2 +1.8V_SM_CK
C +1.05VS AN20 DDR2 +1.8V C
R88 VCCA_SM_3 R89
AR17 VCCA_SM_4 Host Interface I/O and HSIO
A SM
1 2 4.7U_0805_10V4Z AP17 321.35mA 1 2
VCCA_SM_5
1 0_0805_5% 1 1 1 AN17 VCCA_SM_6 VCC_AXF_1 B22 +1.05VS_AXF 1 1 0_0805_5%
AXF
AT16 VCCA_SM_7 VCC_AXF_2 B21
C123 + C124 C125 C126 AR16 A21 C127 R90 C128
220U_D2_4VM_R15 VCCA_SM_8 VCC_AXF_3 0.1U_0402_16V4Z 1_0805_1% 10U_0805_10V4Z
AP16 VCCA_SM_9
@ 2 2 2 2 2 @
2
DDR2,667MHz,119.85mA C129
10U_0805_10V4Z 1U_0402_6.3V4Z Pin BF21
Pin AR20 DDR2,800MHz,124mA 1 2
VCC_SM_CK_1 BF21 +1.8V_SM_CK
SM CK
667MTs,24mA BH20 10U_0805_10V4Z
VCC_SM_CK_2
BG20
DDR2 800MTs,26mA VCC_SM_CK_3
BF20 +1.8V_TXLVDS +1.8V
+1.05VS +1.05VS_A_SM_CK VCC_SM_CK_4 R91 GM@
AP28 VCCA_SM_CK_1 LVDS
R92 AN28 1 2
0.1U_0402_16V4Z VCCA_SM_CK_2
1 2 AP25 VCCA_SM_CK_3 1 1 0_0603_5%
0_0603_5% 1 1 1 AN25 118.8mA
VCCA_SM_CK_4 C130 PM@ C130 C131
AN24 VCCA_SM_CK_5 VCC_TX_LVDS K47 +1.8V_TXLVDS
A CK
C132 C133 C134 AM28 0_0402_5% 1000P_0402_50V7K 10U_0805_10V4Z
VCCA_SM_CK_NCTF_1 2 GM@ 2 GM@
@
10U_0805_10V4Z AM26
2 2
2.2U_0603_6.3V4Z 2 VCCA_SM_CK_NCTF_2
AM25 VCCA_SM_CK_NCTF_3 105.3mA Pin K47
+3VS_TVCRT_DAC AL25 VCCA_SM_CK_NCTF_4 VCC_HV_1 C35 +3VS
TV +1.5VS +1.5VS_HDA Pin AP28 AM24 B35
VCCA_SM_CK_NCTF_5 VCC_HV_2
HV
R94 HDMI's HDA AL24 A35
0.01U_0402_25V4Z VCCA_SM_CK_NCTF_6 VCC_HV_3 D3
1 2 AM23 VCCA_SM_CK_NCTF_7
1 1 0_0402_5% 1 AL23 +3VS 2 R93 1 1 2 +1.05VS
IHDMI@ VCCA_SM_CK_NCTF_8 10_0603_5%
1782mA 1
C135 C136 C138 V48 +1.05VS_PEG_DMI C137 CH751H-40PT_SOD323-2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC_PEG_1 0.1U_0402_16V4Z
2 2
Pin B24 Pin A32 VCC_PEG_2 U48
IHDMI@ 2
PEG
VCC_PEG_3 V47
2
Pin C35
B
79mA VCC_PEG_4 U47
B
B24 VCCA_TV_DAC_1 VCC_PEG_5 U46
+3VS_TVCRT_DAC A24 VCCA_TV_DAC_2
TV
+1.5VS +1.5VS_TVDAC +1.5VS +1.5VS_QDAC
50mA 456mA
R95 TV R96 TV +1.5VS_HDA A32 AH48 +1.05VS_PEG_DMI +1.05VS
VCC_HDA VCC_DMI_1 +1.05VS_PEG_DMI
HDA
2 1 0.1U_0402_16V4Z 2 1 0.01U_0402_25V4Z AF48 PCIe&DMI
VCC_DMI_2
DMI
0_0603_5% 1 1 1 0_0603_5% 1 1 AH47 PJ26
VCC_DMI_3 10U_0805_10V4Z
VCC_DMI_4 AG47 1 1 2 2
C139 C140 C141 C142 C143 35mA 1 1 1
@ 10U_0805_10V4Z Pin M252 0.1U_0402_16V4Z Pin L282 +1.5VS_TVDAC M25 JUMP_43X79 @
2 2 2 VCCD_TVDAC +
D TV/CRT
C144 C145
0.01U_0402_25V4Z C146
+1.5VS_QDAC L28 VCCD_QDAC500uA 2
10U_0805_10V4Z 2 @
2
157.2mA Pin V48
+1.05VS_DHPLL AF1 220U_6.3V_M
VCCD_HPLL VTTLF1
+1.05VS +1.05VS_DHPLL
50mA VTTLF1 A8
+1.05VS_PEGPLL AA47 L1 VTTLF2
VCCD_PEG_PLL VTTLF2
VTTLF
R98
VTTLF3 AB2 VTTLF3 +1.05VS_PEG_DMI PCIe&DMI
1 2 60.31mA 1 1 1
0_0402_5% 2 M38 VCCD_LVDS_1
LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 12 of 43
5 4 3 2 1
5 4 3 2 1
U3I U3J
VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB
VSS_82 VSS_181 VSS_280 VSS_SCB_4
U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC
VSS_97 VSS_196 VSS_295 NC_35
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
GMR3@ NC_40
NC_41 C48
NC_42 B48
CANTIGA ES_FCBGA1329
GMR3@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 13 of 43
5 4 3 2 1
5 4 3 2 1
JDDRL @
+DIMM_VREF 1 VREF VSS 2 DDR_A_DQS#[0..7] 9
1 1 3 4 DDR_A_D5
DDR_A_D4 VSS DQ4 DDR_A_D0
5 DQ0 DQ5 6 DDR_A_D[0..63] 9
C155 C156 DDR_A_D1 7 8
2.2U_0603_6.3V6K 0.1U_0402_16V4Z DQ1 VSS DDR_A_DM0
9 VSS DM0 10 DDR_A_DM[0..7] 9
2 2 DDR_A_DQS#0 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_DQS[0..7] 9
15 16 DDR_A_D7
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18 DDR_A_MA[0..14] 9
DDR_A_D3 19 20 DDR_A_D13
+1.8V DQ3 DQ12 DDR_A_D12
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D14 DQ8 VSS DDR_A_DM1
D 25 DQ9 DM1 26 Layout Note: D
1
27 28 +1.8V
R101 DDR_A_DQS#1 VSS VSS Place near JP3
29 DQS1# CK0 30 DDRA_CLK0 8
DDR_A_DQS1 31 32
DQS1 CK0# DDRA_CLK0# 8
1K_0402_1% 20mils 33 34
VSS VSS
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D9 35 36 DDR_A_D11 1
2
C158
C159
C160
C161
C162
C163
C164
C165
C166
39 40 + C157
VSS VSS
1
220U_Y_4VM
R102 @
2 2 2 2 2 2 2 2 2 2
41 VSS VSS 42
1K_0402_1% DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21 4.4
45 46
2
DQ17 DQ21
47 VSS VSS 48
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS# 8,15
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28 Layout Note: Place one cap close to every 2 pullup
DDR_A_D24 DQ24 DQ28 DDR_A_D25 +0.9VS
63 DQ25 DQ29 64
65 66 resistors terminated to +0.9VS
DDR_A_DM3 VSS VSS DDR_A_DQS#3
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76 1 1 1 1 1 1 1 1 1 1 1 1 1
77 VSS VSS 78
C DDRA_CKE0 79 80 DDRA_CKE1 C
8 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 8
+1.8V 81 VDD VDD 82 +1.8V 2 2 2 2 2 2 2 2 2 2 2 2 2
83 NC NC/A15 84
C167
C168
C169
C170
C171
C172
C173
C174
C175
C176
C177
C178
C179
DDR_A_BS2 85 86 DDR_A_MA14
9 DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 Layout Note:
A10/AP BA1 DDR_A_BS1 9
DDR_A_BS0 107 108 DDR_A_RAS#
9 DDR_A_BS0
DDR_A_WE# BA0 RAS# DDRA_SCS0#
DDR_A_RAS# 9 Place these resistor
9 DDR_A_WE# 109 WE# S0# 110 DDRA_SCS0# 8
111 112 closely JP3,all
DDR_A_CAS# VDD VDD DDRA_ODT0
9 DDR_A_CAS# 113 CAS# ODT0 114 DDRA_ODT0 8 trace length Max=1.5"
DDRA_SCS1# 115 116 DDR_A_MA13
8 DDRA_SCS1# NC/S1# NC/A13 +0.9VS
117 VDD VDD 118
8 DDRA_ODT1 DDRA_ODT1 119 120
NC/ODT1 NC RP1 RP2
121 VSS VSS 122
DDR_A_D37 123 124 DDR_A_D39 DDR_A_MA8 8 1 8 1 DDR_A_MA13
DDR_A_D36 DQ32 DQ36 DDR_A_D38 DDR_A_BS2 DDRA_ODT0
125 DQ33 DQ37 126 7 2 7 2
127 128 DDR_A_MA12 6 3 6 3 DDR_A_RAS#
DDR_A_DQS#4 VSS VSS DDR_A_DM4 DDR_A_MA1 DDRA_SCS0#
129 DQS4# DM4 130 5 4 5 4
DDR_A_DQS4 131 132
DQS4 VSS DDR_A_D34 56_0804_8P4R_5% 56_0804_8P4R_5%
133 VSS DQ38 134
DDR_A_D35 135 136 DDR_A_D33
B DDR_A_D32 DQ34 DQ39 RP3 RP4 B
137 DQ35 VSS 138
139 140 DDR_A_D45 DDR_A_MA14 8 1 8 1 DDR_A_MA5
DDR_A_D40 VSS DQ44 DDR_A_D43 DDR_A_MA11 DDR_A_MA3
141 DQ40 DQ45 142 7 2 7 2
DDR_A_D44 143 144 DDR_A_MA6 6 3 6 3 DDR_A_MA9
DQ41 VSS DDR_A_DQS#5 DDR_A_MA7 DDR_A_MA10
145 VSS DQS5# 146 5 4 5 4
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5 56_0804_8P4R_5% 56_0804_8P4R_5%
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42 RP5 RP12
153 DQ43 DQ47 154
155 156 DDRA_ODT1 8 1 1 8 DDR_A_MA4
DDR_A_D49 VSS VSS DDR_A_D52 DDR_A_CAS# DDR_A_MA2
157 DQ48 DQ52 158 7 2 2 7
DDR_A_D48 159 160 DDR_A_D53 DDR_A_WE# 6 3 3 6 DDR_A_BS1
DQ49 DQ53 DDR_A_BS0 DDR_A_MA0
161 VSS VSS 162 5 4 4 5
163 NC,TEST CK1 164 DDRA_CLK1 8
165 166 56_0804_8P4R_5% 56_0804_8P4R_5%
VSS CK1# DDRA_CLK1# 8
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 172 DDRA_SCS1#R480 1 2 56_0402_5%
DDR_A_D54 VSS VSS DDR_A_D51 DDRA_CKE0 R481 1 56_0402_5%
173 DQ50 DQ54 174 2
DDR_A_D50 175 176 DDR_A_D55 DDRA_CKE1 R482 1 2 56_0402_5%
DQ51 DQ55
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D59 189 190
SUPPORT_PAD
SUPPORT_PAD
1
C180 FOX_AS0A426-M2RN-7F
0.1U_0402_16V4Z
JDDRH @
DDR_B_DQS#[0..7] 9
+DIMM_VREF 1 VREF VSS 2
1 1 3 4 DDR_B_D5 DDR_B_D[0..63] 9
DDR_B_D0 VSS DQ4 DDR_B_D4
5 DQ0 DQ5 6
C181 C182 DDR_B_D1 7 8
DQ1 VSS DDR_B_DM[0..7] 9
2.2U_0603_6.3V6K 0.1U_0402_16V4Z 9 10 DDR_B_DM0
@ 2 2 DDR_B_DQS#0 VSS DM0
11 DQS0# VSS 12 DDR_B_DQS[0..7] 9
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16 DDR_B_MA[0..14] 9
DDR_B_D2 17 18
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
21 22 DDR_B_D13 Layout Note:
DDR_B_D8 VSS DQ13 +1.8V
23 DQ8 VSS 24
1 DDR_B_D9 25 26 DDR_B_DM1 Place near JP4 1
DQ9 DM1
27 VSS VSS 28
DDR_B_DQS#1 29 30
DQS1# CK0 DDRB_CLK0 8
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_DQS1 31 32
DQS1 CK0# DDRB_CLK0# 8
33 VSS VSS 34 1 1 1 1 1 1 1 1 1
C183
C184
C185
C186
C187
C188
C189
C190
C191
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
39 VSS VSS 40
2 2 2 2 2 2 2 2 2
41 VSS VSS 42
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS# 8,14
DDR_B_DQS2 51 52 DDR_B_DM2
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
+0.9VS Layout Note: Place one cap close to every 2 pullup
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26 Resistors terminated to +0.9VS
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72 1 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
77 VSS VSS 78
2 DDRB_CKE0 DDRB_CKE1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
8 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 8
C192
C193
C194
C195
C196
C197
C198
C199
C200
C201
C202
C203
C204
+1.8V 81 VDD VDD 82 +1.8V
83 NC NC/A15 84
DDR_B_BS2 85 86 DDR_B_MA14
9 DDR_B_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100 Layout Note:
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0 Place these resistor
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 closely JP4,all
A10/AP BA1 DDR_B_BS1 9
DDR_B_BS0 107 108 DDR_B_RAS# trace length Max=1.5"
9 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 9
DDR_B_WE# 109 110 DDRB_SCS0#
9 DDR_B_WE# WE# S0# DDRB_SCS0# 8
111 VDD VDD 112
DDR_B_CAS# 113 114 DDRB_ODT0
9 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 8 +0.9VS
DDRB_SCS1# 115 116 DDR_B_MA13
8 DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 RP8 RP9
8 DDRB_ODT1 NC/ODT1 NC
121 122 DDR_B_CAS# 8 1 8 1 DDR_B_MA7
DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_WE# DDR_B_MA6
123 DQ32 DQ36 124 7 2 7 2
DDR_B_D33 125 126 DDR_B_D37 DDR_B_MA10 6 3 6 3 DDR_B_MA14
DQ33 DQ37 DDR_B_BS0 DDR_B_MA11
127 VSS VSS 128 5 4 5 4
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4 56_0804_8P4R_5% 56_0804_8P4R_5%
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38 RP10 RP11
135 DQ34 DQ39 136
3 DDR_B_D35 DDR_B_RAS# DDR_B_MA8 3
137 DQ35 VSS 138 8 1 8 1
139 140 DDR_B_D44 DDRB_SCS0# 7 2 7 2 DDR_B_MA5
DDR_B_D40 VSS DQ44 DDR_B_D45 DDRB_ODT0 DDR_B_MA1
141 DQ40 DQ45 142 6 3 6 3
DDR_B_D41 143 144 DDR_B_MA13 5 4 5 4 DDR_B_MA3
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5 56_0804_8P4R_5% 56_0804_8P4R_5%
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46 RP6 RP13
DDR_B_D43 DQ42 DQ46 DDR_B_D47 DDR_B_MA12 DDR_B_BS1
153 DQ43 DQ47 154 8 1 8 1
155 156 DDR_B_BS2 7 2 7 2 DDR_B_MA0
DDR_B_D48 VSS VSS DDR_B_D52 DDRB_CKE0 DDR_B_MA4
157 DQ48 DQ52 158 6 3 6 3
DDR_B_D49 159 160 DDR_B_D53 DDR_B_MA9 5 4 5 4 DDR_B_MA2
DQ49 DQ53
161 VSS VSS 162
163 164 56_0804_8P4R_5% 56_0804_8P4R_5%
NC,TEST CK1 DDRB_CLK1 8
165 VSS CK1# 166 DDRB_CLK1# 8
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6 DDRB_ODT1 R4831 56_0402_5%
169 DQS6 DM6 170 2
171 172 DDRB_SCS1# R4841 2 56_0402_5%
DDR_B_D51 VSS VSS DDR_B_D54 DDRB_CKE1 R4851 56_0402_5%
173 DQ50 DQ54 174 2
DDR_B_D50 175 176 DDR_B_D55
DQ51 DQ55
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D59 189 190
SUPPORT_PAD
SUPPORT_PAD
1
FOX_AS0A426-MARG-7F
Security Classification Compal Secret Data Compal Electronics, Inc.
201
202
C205
SO-DIMM B 2
0.1U_0402_16V4Z
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
STANDARD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size Document Number Rev
Bottom side AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 15 of 43
A B C D E
A B C D E F G H
+1.05VS_CK505 +3VS_CK505
R108 80mA R107 250mA
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS +3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 0_0805_5% 1
C213
1
C214
1
C215
1
C216
1
C217
1
C218
1
C219
0_0805_5% 1
C206
1
C207
1
C208
1
C209
1
C210
1
C211
1
C212
73 THERMAL_PAD USB_1/CLKREQ_A# 21
R121 R122
@ 10K_0402_5% 10K_0402_5%
4 4
PM@ SLG8SP556VTR_QFN72_10X10
2
CLK_ICH CLK_EC
1
R127 R128
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
GM@ 2008/09/19 2009/09/19 Title
Issued Date Deciphered Date
SCHEMATIC MB A4571
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 16 of 43
A B C D E F G H
5 4 3 2 1
PCIE_MTX_C_GRX_N[0..15] PCIE_GTX_C_MRX_N[0..15]
10 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
10 PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
LCD/PANEL BD. Conn.
10 PCIE_MTX_C_GRX_P[0..15] 10 PCIE_GTX_C_MRX_P[0..15]
+LCD_VDD +3V_SB
1 1 2 2
1
PCIE_MTX_C_GRX_N15 3 4 PCIE_GTX_C_MRX_N15
PCIE_MTX_C_GRX_P15 3 4 PCIE_GTX_C_MRX_P15 R621 R622 +3VS
5 5 6 6
7 8 300_0603_5% 1M_0402_5% W=60mils
PCIE_MTX_C_GRX_N14 7 8 PCIE_GTX_C_MRX_N14
9 9 10 10
PCIE_MTX_C_GRX_P14 11 12 PCIE_GTX_C_MRX_P14
6 2
2
11 12
D 13 13 14 14 D
PCIE_MTX_C_GRX_N13 15 16 PCIE_GTX_C_MRX_N13
PCIE_MTX_C_GRX_P13 15 16 PCIE_GTX_C_MRX_P13
17 17 18 18
3
S
19 20 Q17A
PCIE_MTX_C_GRX_N12 19 20 PCIE_GTX_C_MRX_N12 2N7002DW-T/R7_SOT363-6
G
Q18
21 21 22 22 2 1 2 2
PCIE_MTX_C_GRX_P12 23 24 PCIE_GTX_C_MRX_P12 R623 100K_0402_5% AO3413_SOT23
23 24
3
25 26 2
D
1
PCIE_MTX_C_GRX_N11 25 26 PCIE_GTX_C_MRX_N11 C671 +LCD_VDD
27 27 28 28
PCIE_MTX_C_GRX_P11 29 30 PCIE_GTX_C_MRX_P11 1000P_0402_50V7K W=60mils
29 30 ENVDD
31 31 32 32 10 UMA_ENVDD 1 2 5
PCIE_MTX_C_GRX_N10 PCIE_GTX_C_MRX_N10 R624 GM@ 0_0402_5% Q17B 1
33 33 34 34
PCIE_MTX_C_GRX_P10 35 36 PCIE_GTX_C_MRX_P10 VGA_ENVDD 1 2 2N7002DW-T/R7_SOT363-6 1 1
4
35 36
1
37 38 R625 PM@ 0_0402_5%
PCIE_MTX_C_GRX_N9 37 38 PCIE_GTX_C_MRX_N9 C672 C673
39 39 40 40
PCIE_MTX_C_GRX_P9 41 42 PCIE_GTX_C_MRX_P9 R626 4.7U_0805_10V4Z 0.1U_0402_16V4Z
41 42 100K_0402_5% @ 2 2
43 43 44 44
PCIE_MTX_C_GRX_N8 45 46 PCIE_GTX_C_MRX_N8
2
PCIE_MTX_C_GRX_P8 45 46 PCIE_GTX_C_MRX_P8
47 47 48 48
49 49 50 50
PCIE_MTX_C_GRX_N7 51 52 PCIE_GTX_C_MRX_N7
PCIE_MTX_C_GRX_P7 51 52 PCIE_GTX_C_MRX_P7
53 53 54 54
55 55 56 56 1.5A
PCIE_MTX_C_GRX_N6 57 58 PCIE_GTX_C_MRX_N6 JLVDS +LCDVDD_R 2 L16 1 +LCD_VDD
PCIE_MTX_C_GRX_P6 57 58 PCIE_GTX_C_MRX_P6 0_0805_5%
59 59 60 60 2 2 1 1
61 62 LCD_TXOUT0+ 4 3 LCD_TXCLK+ 1 1
PCIE_MTX_C_GRX_N5 61 62 PCIE_GTX_C_MRX_N5 LCD_TXOUT0- 4 3 LCD_TXCLK-
63 63 64 64 6 6 5 5
PCIE_MTX_C_GRX_P5 65 66 PCIE_GTX_C_MRX_P5 8 7 C674 C675
65 66 LCD_TXOUT1+ 8 7 0.1U_0402_16V4Z 4.7U_0805_10V4Z
67 67 68 68 10 10 9 9 DAC_BRIG 32
PCIE_MTX_C_GRX_N4 PCIE_GTX_C_MRX_N4 LCD_TXOUT1- 2 2
69 69 70 70 12 12 11 11 INVT_PWM 32
C PCIE_MTX_C_GRX_P4 71 72 PCIE_GTX_C_MRX_P4 14 13 C
71 72 LCD_TXOUT2+ 14 13 LCD_TZCLK+
73 73 74 74 16 16 15 15
PCIE_MTX_C_GRX_N3 75 76 PCIE_GTX_C_MRX_N3 LCD_TXOUT2- 18 17 LCD_TZCLK-
PCIE_MTX_C_GRX_P3 75 76 PCIE_GTX_C_MRX_P3 18 17 specially control signal for 16" panel by cable selection
77 77 78 78 20 20 19 19 LVDS_SEL 22
79 80 LCD_TZOUT0+ 22 21 LCD_EDID_CLK High-->one channel
PCIE_MTX_C_GRX_N2 79 80 PCIE_GTX_C_MRX_N2 LCD_TZOUT0- 22 21 LCD_EDID_DATA Low-->two channel
81 81 82 82 24 24 23 23
PCIE_MTX_C_GRX_P2 83 84 PCIE_GTX_C_MRX_P2 26 25 +3VS
83 84 LCD_TZOUT1+ 26 25 +LCDVDD_R
85 85 86 86 28 28 27 27
PCIE_MTX_C_GRX_N1 87 88 PCIE_GTX_C_MRX_N1 LCD_TZOUT1- 30 29
PCIE_MTX_C_GRX_P1 87 88 PCIE_GTX_C_MRX_P1 30 29
89 89 90 90 32 32 31 31 1
91 92 LCD_TZOUT2+ 34 33 +LCD_INV
PCIE_MTX_C_GRX_N0 91 92 PCIE_GTX_C_MRX_N0 LCD_TZOUT2- 34 33 C676
93 93 94 94 36 36 35 35
PCIE_MTX_C_GRX_P0 95 96 PCIE_GTX_C_MRX_P0 38 37 B+ 0.1U_0402_16V4Z
95 96 BKOFF# 38 37 L17 2
97 97 98 98 32 BKOFF# 40 40 39 39
99 100 LCD_TXOUT0+ 42 41 2 1
16 CLK_PCIE_VGA 99 100 GND GND
101 102 LCD_TXOUT0- FBMA-L11-201209-221LMA30T_0805
16 CLK_PCIE_VGA# 101 102
103 104 ACES_88242-4001 1 1 Rated Current MAX:3000mA
103 104 LCD_TXOUT1+
19 VGA_HDMI_TX0+ 105 105 106 106 @
107 108 LCD_TXOUT1- C677 C678
19 VGA_HDMI_TX0- 107 108 +3VS
109 110 68P_0402_50V8J 0.1U_0402_25V4Z
109 110 LCD_TXOUT2+ 2 2
19 VGA_HDMI_TX1+ 111 111 112 112
113 114 LCD_TXOUT2- 1 @ 2 BKOFF#
19 VGA_HDMI_TX1- 113 114
115 116 R627 4.7K_0402_5%
115 116 LCD_TXCLK+
19 VGA_HDMI_TX2+ 117 117 118 118
119 120 LCD_TXCLK-
19 VGA_HDMI_TX2- 119 120
121 121 122 122
123 124 LCD_TZOUT0+
19 VGA_HDMI_CLK+ 123 124 please link to VGA Conn. then link to LVDS Conn.
125 126 LCD_TZOUT0-
19 VGA_HDMI_CLK- 125 126
127 127 128 128 VGA side LVDS conn. NB side
B LCD_TZOUT1+ B
19 VGA_HDMI_CLK 129 129 130 130
19 VGA_HDMI_DATA 131 132 LCD_TZOUT1-
131 132 LCD_TXOUT0+ 0_0402_5%
19 VGA_HDMI_HPD 133 133 134 134 2 GM@ 1 R629 UMA_LCD_TXOUT0+ 10
LCD_EDID_CLK 135 136 LCD_TZOUT2+ LCD_TXOUT0- 0_0402_5% 2 GM@ 1 R631
135 136 UMA_LCD_TXOUT0- 10
LCD_EDID_DATA 137 138 LCD_TZOUT2-
VGA_ENVDD 137 138 LCD_TXOUT1+ 0_0402_5%
139 139 140 140 2 GM@ 1 R633 UMA_LCD_TXOUT1+ 10
18 VGA_CRT_CLK 141 142 LCD_TZCLK+ LCD_TXOUT1- 0_0402_5% 2 GM@ 1 R635
141 142 UMA_LCD_TXOUT1- 10
18 VGA_CRT_DATA 143 144 LCD_TZCLK-
143 144 LCD_TXOUT2+ 0_0402_5%
145 145 146 146 2 GM@ 1 R637 UMA_LCD_TXOUT2+ 10
147 148 LCD_TXOUT2- 0_0402_5% 2 GM@ 1 R639
18 VGA_CRT_R 147 148 27M_CLK 16 UMA_LCD_TXOUT2- 10
18 VGA_CRT_G 149 149 150 150 27M_SSC 16
151 152 LCD_TXCLK+ 0_0402_5% 2 GM@ 1 R641
18 VGA_CRT_B 151 152 UMA_LCD_TXCLK+ 10
153 154 LCD_TXCLK- 0_0402_5% 2 GM@ 1 R643
153 154 VGA_TV_LUMA 18 UMA_LCD_TXCLK- 10
18 VGA_CRT_HSYNC 155 155 156 156 VGA_TV_CRMA 18
18 VGA_CRT_VSYNC 157 157 158 158
159 160 LCD_TZOUT0+ 0_0402_5% 2 GM@ 1 R645
159 160 PLT_RST# 8,20,25,27,28,31,32,33 UMA_LCD_TZOUT0+ 10
161 162 EC_SMB_CK2 4,32 LCD_TZOUT0- 0_0402_5% 2 GM@ 1 R647
25,29,32,35,40 SUSP# 161 162 UMA_LCD_TZOUT0- 10
163 163 164 164 EC_SMB_DA2 4,32
+1.8VS 165 166 LCD_TZOUT1+ 0_0402_5% 2 GM@ 1 R649
165 166 VGA_ENBKL 32 UMA_LCD_TZOUT1+ 10
167 168 +5VALW LCD_TZOUT1- 0_0402_5% 2 GM@ 1 R651
167 168 UMA_LCD_TZOUT1- 10
169 169 170 170
171 172 +3VS LCD_TZOUT2+ 0_0402_5% 2 GM@ 1 R653
171 172 UMA_LCD_TZOUT2+ 10
173 174 LCD_TZOUT2- 0_0402_5% 2 GM@ 1 R655
173 174 UMA_LCD_TZOUT2- 10
175 175 176 176
177 178 +1.8VS LCD_TZCLK+ 0_0402_5% 2 GM@ 1 R657
177 178 UMA_LCD_TZCLK+ 10
179 180 LCD_TZCLK- 0_0402_5% 2 GM@ 1 R659
179 180 UMA_LCD_TZCLK- 10
181 181 182 182
183 183 184 184
185 186 LCD_EDID_CLK 0_0402_5% 2 GM@ 1 R661 UMA_LCD_EDID_CLK 10
A 185 186 A
187 188 LCD_EDID_DATA 0_0402_5% 2 GM@ 1 R663 UMA_LCD_EDID_DATA 10
187 188
189 189 190 190 B+
191 191 192 192
193 193 194 194
195 195 196 196
197 198
199
197
199
198
200 200
Security Classification Compal Secret Data Compal Electronics, Inc.
201 201 202 202 Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
203 204
205
203
205
204
206 206 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
JAE_WB3F200VD1R1000~D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401605 E
JVGA @ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 16, 2009 Sheet 17 of 43
5 4 3 2 1
A B C D E
CRT CONNECTOR
1
D55 D56 D57 +5VS +CRT_VCC_R +CRT_VCC
D58 F3 30mil
2 1 1 2
1
+3VS RB491D_SC59-3 1.1A_6V_MINISMDC110F-2
DAN217_SC59 DAN217_SC59 DAN217_SC59 If=1A C679
3
@ @ @ @ 0.1U_0402_16V4Z
2
L18 JCRTB
1 2 CRT_R 1 2 CRT_R_L CRT_B_L 1
10 UMA_CRT_R 1
1 R664 GM@ 0_0402_5% NBQ100505T-800Y_0402 2 1
CRT_G_L 2
17 VGA_CRT_R 1 2 3 3
R665 PM@ 0_0402_5% L19 4
CRT_G CRT_G_L CRT_R_L 4
10 UMA_CRT_G 1 2 1 2 5 5
R666 GM@ 0_0402_5% NBQ100505T-800Y_0402 6
VSYNC 6
17 VGA_CRT_G 1 2 7 7
R667 PM@ 0_0402_5% L20 HSYNC 8
CRT_B CRT_B_L 8
10 UMA_CRT_B 1 2 1 2 9 9
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
R668 GM@ 0_0402_5% NBQ100505T-800Y_0402 CRT_DDC_CLK 10
CRT_DDC_DAT 10
17 VGA_CRT_B 1 2 11 11 GND 13
150_0402_1%
150_0402_1%
150_0402_1%
R669 PM@ 0_0402_5% 1 1 1 1 1 1 +CRT_VCC 12 14
12 GND
1
R670 R671 R672 C680 C681 C682 C683 C684 C685
ACES_85201-1205N
2 2 2 2 2 2
@
2
+CRT_VCC +3VS
1 2 2 1
C686 0.1U_0402_16V4Z R673 10K_0402_5%
5
1
1
R674 +CRT_VCC
P
OE#
1 2 CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC 0_0402_5%
10 UMA_CRT_HSYNC A Y
R675 GM@ 0_0402_5% L21 10_0402_5%
G
U38
2
1 2 SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC 1 2 VSYNC
17 VGA_CRT_HSYNC
3
2 R676 PM@ 0_0402_5% L22 10_0402_5% R677 R678 2
10P_0402_50V8J
10P_0402_50V8J
4.7K_0402_5% 4.7K_0402_5%
2
+CRT_VCC Q19A
1 1
1
C687 C688 10 UMA_CRT_DATA 1 2 CRT_DATA 1 6 CRT_DDC_DAT
5
1
R679 GM@ 0_0402_5%
5
2 2 Q19B 2N7002DW-T/R7_SOT363-6
17 VGA_CRT_DATA 1 2
P
OE#
1 2 CRT_VSYNC 2 4 R680 PM@ 0_0402_5%
10 UMA_CRT_VSYNC A Y
R681 GM@ 0_0402_5% 10 UMA_CRT_CLK 1 2 CRT_CLK 4 3 CRT_DDC_CLK
U39 G R682 GM@ 0_0402_5% 1 1
1 2 SN74AHCT1G125GW_SOT353-5 17 VGA_CRT_CLK 1 2 1 1 2N7002DW-T/R7_SOT363-6
17 VGA_CRT_VSYNC
3
TV CONNECTOR
@ @
DAN217_SC59 DAN217_SC59
1
D59 D60
3 3
3
+3VS
C691 1 2 22P_0402_50V8J
@
L23
17 VGA_TV_LUMA 1 2 TVOUT@
FBMA-L11-160808-121LMT_0603
L24
17 VGA_TV_CRMA 1 2 TVOUT@
FBMA-L11-160808-121LMT_0603
JTV
1
4 4
1
C242 C243 C244 C245 C246 C247 C248 C249 U7 R142
IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ 4.7K_0402_5% R143
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z H@ 4.7K_0402_5%
2
2 2 2 2 2 2 2 2 +3VS OE H@
OE* 25 VGA_HDMI_CLK 17
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R141
G
2
2
20K_0402_5% 2
IHDMI@ VCC3V HDMI_SCLK
11 VCC3V SCL_SINK 28 1 3
2
D8 F2 H@ 15 Q48
2
PCIE_GTX_C_MRX_HDMI_P3 VCC3V Q47 BSH111_SOT23-3
G
+5VL 2 1 2 1 +HDMI_5V_OUT 21 VCC3V SDA_SINK 29
D 1.1A_6V_MINISMDC110F-21 26 BSH111_SOT23-3 HDMI@ D
VCC3V
1
RB161M_SOD123 H@ C250 33 HDMI_SDATA HDMI@ 1 3 VGA_HDMI_DATA 17
D53 H@ R145 VCC3V
40 VCC3V HPD_SINK 30
0.1U_0402_16V4Z 7.5K_0402_1% HDMI_HPD_R
S
+5VS 2 1 46 VCC3V
2 IHDMI@ R147 2
DDC_EN 32 1 4.7K_0402_5% +3VS
RB161M_SOD123 H@ IHDMI@
2
VGA_DVI_TXC- 1 2 R164 HDMI_R_CK- +3VS R148
1 2 @ 0_0402_5% 3 34 R149 2 1 0_0402_5% @
@ 0_0402_5% R150 FUNCTION1 FUNCTION3
1 2 @ 0_0402_5% 4 FUCNTION2 FUNCTION4 35 R151 2 1 0_0402_5% @ +3VS
L9 R152
1 IHDMI@ 2 0_0402_5% R153 1 2 0_0402_5% IHDMI@
1 2 R154
1 IHDMI@ 2 0_0402_5% R155 1 2 0_0402_5% IHDMI@
1 2 R156
2 1 6 ANALOG1(REXT)
3.9K_0402_1% IHDMI@
4 4 3 3 10 PCIE_GTX_C_MRX_HDMI_P3 7 HPD_SOURCE
H@ WCM-2012-900T_0805 8 +5VL 2 1 2 1 +3VS
8 SDVO_SDATA SDA_SOURCE
VGA_DVI_TXC+ 1 2 R166 HDMI_R_CK+ Vendor suggest un-mound for these. R570 H@ R571 HDMI@
@ 0_0402_5% 9 2.2K_0402_5% 2.2K_0402_5%
8 SDVO_SCLK SCL_SOURCE
VGA_DVI_TXC- R159 1 @ 2 1 2 VGA_DVI_TXC+ HDMI_HPD_R 1 2
32 HDMI_HPD_R VGA_HDMI_HPD 17
68_0402_5% C251 0.5P_0402_50V8B D54
VGA_DVI_TXD0- 1 2 R167 HDMI_R_D0- @ 1 IHDMI@ 2 10 CH751H-40PT_SOD323-2
@ 0_0402_5% R689 0_0402_5% ANALOG2 HDMI@
L10 VGA_DVI_TXD2- R160 1 @ 2 1 2 VGA_DVI_TXD2+
1 2 68_0402_5% C252 0.5P_0402_50V8B VGA_DVI_TXC+ 13 48
1 2 OUT_D4+ IN_D4+ PCIE_MTX_C_GRX_HDMI_P3 10
@ VGA_DVI_TXC- 14 47
OUT_D4- IN_D4- PCIE_MTX_C_GRX_HDMI_N3 10
4 3 VGA_DVI_TXD1- R161 1 @ 2 1 2 VGA_DVI_TXD1+ VGA_DVI_TXD2+ 16 45
4 3 OUT_D3+ IN_D3+ PCIE_MTX_C_GRX_HDMI_P0 10
68_0402_5% C253 0.5P_0402_50V8B VGA_DVI_TXD2- 17 44
OUT_D3- IN_D3- PCIE_MTX_C_GRX_HDMI_N0 10
H@ WCM-2012-900T_0805 @
C VGA_DVI_TXD0+ 1 2 R172 HDMI_R_D0+ VGA_DVI_TXD1+ 19 42 C
OUT_D2+ IN_D2+ PCIE_MTX_C_GRX_HDMI_P1 10
@ 0_0402_5% VGA_DVI_TXD0- R162 1 @ 2 1 2 VGA_DVI_TXD0+ VGA_DVI_TXD1- 20 41
OUT_D2- IN_D2- PCIE_MTX_C_GRX_HDMI_N1 10
68_0402_5% C254 0.5P_0402_50V8B
@ VGA_DVI_TXD0+ 22 39
OUT_D1+ IN_D1+ PCIE_MTX_C_GRX_HDMI_P2 10
VGA_DVI_TXD0- 23 38
OUT_D1- IN_D1- PCIE_MTX_C_GRX_HDMI_N2 10
VGA_DVI_TXD1- 1 2 R173 HDMI_R_D1-
@ 0_0402_5% +5VL
L11 U34 @
1 1 2 2 VCC 3 1 GND
1 5 GND
CEC_RST# 2 C593 12 +5VL
RESET# 0.1U_0402_16V4Z GND
4 4 3 3 18 GND
1 @ 24 HDMI_HPD
H@ WCM-2012-900T_0805 GND 2 GND
27 GND THERMAL_PAD 49 2
VGA_DVI_TXD1+ 1 2 R176 HDMI_R_D1+ G691L308T72UF_SOT23-3 No P/N 31 C658 2
GND
2
@ 0_0402_5% 36 H@ R572 C659
GND
1
37 0.1U_0402_16V4Z U37 100K_0402_5% H@
U33 @ GND 1 H@
43
OE#
VGA_DVI_TXD2- GND 1
1 2 R177 HDMI_R_D2- +5VL 5 Vcc NC 1 2 A Y 4 HDMI_HPD_R
@ 0_0402_5% 1 2 HDMI_CEC 0.1U_0402_16V4Z
1
A
G
L12 C592 HDMI_CECIN 4 3 STHDLS101TQTR QFN 48P HDMI SHIFTER_QFN48_7X7 74AHCT1G125GW_SOT353-5
1U_0402_6.3V4Z Y GND IHDMI@ H@
1 2
3
1 2 @ 8MHZ_20PF_X8A008000IK1H
2 TC7SET14FU_SOT353-5
CEC_XIN 2 1 2 2 CEC_XOUT
4 4 3 3
C594 Y4 @ C595
VGA_DVI_TXD2+
H@ WCM-2012-900T_0805
1 2 R178
@ 0_0402_5%
HDMI_R_D2+
22P_0402_50V8J
@ 1
22P_0402_50V8J
1 @ HDMI CEC Controller
U8
B B
CV164 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC- 1 11
17 VGA_HDMI_CLK- +5VL +3VL 32,37 EC_SMB_CK1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 CEC_INT# 32 +5VL
CV165 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0-
17 VGA_HDMI_TX0-
CV166 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1-
17 VGA_HDMI_TX1- +5VL
CV167 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2- 2 12 CEC_TEST 1 H@ 2
17 VGA_HDMI_TX2- P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R168 4.7K_0402_5%
1
17 VGA_HDMI_CLK+
CV168 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ R157 2 D9 2 1CEC_RST# 3 RESET# P1_4/TXD0 13 CEC_FSHUPD 1 H@ 2
CV169 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ 10K_0402_5% CH751H-40PT_SOD323-2 R169 4.7K_0402_5% R170 4.7K_0402_5%
17 VGA_HDMI_TX0+
CV170 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ H@ H@ H@ CEC_FSHUPD (Pin13)
17 VGA_HDMI_TX1+
CV171 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+ 2 1CEC_XOUT 4 14 Low= Force to update flash.
17 VGA_HDMI_TX2+
2
1 1
D H@ H@ 0.1U_0402_16V4Z
HDMI_R_CK+ 1 HDMI@ 2 Q49 2 2 1CEC_XIN 6 16 +5VL
2
R692 499_0402_1% D
17 DDC/CEC_GND
HDMI_R_D1+ 1 HDMI@ 2 HDMI_SDATA 16 HDMI_CECOUT 1 R163 2 2 Q50 2 1 8 18 HDMI_SDATA
R693 499_0402_1% HDMI_SCLK SDA 27K_0402_5% G 2N7002_SOT23-3 R175 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0
15 SCL
HDMI_R_D0- 1 HDMI@ 2 14 H@ S H@ C256 1 H@
3
Reserved
1
D HDMI_R_D1- 6 D1- H@
+5VS 2 Q20 5
G 2N7002_SOT23-3 HDMI_R_D1+ D1_shield
4
S HDMI@ HDMI_R_D2- 3
D1+ Security Classification Compal Secret Data Compal Electronics, Inc.
3
D2-
1 @ 2 2 D2_shield Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
R698 100K_0402_5% HDMI_R_D2+ 1 D2+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
@ TYCO_1939864-1_19P AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 19 of 43
5 4 3 2 1
5 4 3 2 1
+3VS
U9B
D11 F1 PCI_REQ#0 RP15
AD0 REQ0# PCI_REQ#0
C8 AD1 GNT0# G4 PCI_GNT#0 22 1 8
PCI_REQ#1 PCI_REQ#1
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_REQ#2
2
3
7
6
AD3 GNT1#/GPIO51 PCI_REQ#2 PCI_REQ#3
E9 AD4 REQ2#/GPIO52 F13 4 5
C9 AD5 GNT2#/GPIO53 F12
E10 E6 PCI_REQ#3 8.2K_0804_8P4R_5%
AD6 REQ3#/GPIO54 RP16
B7 AD7 GNT3#/GPIO55 F6 STRAP_A16 22
C7 PCI_IRDY# 1 8
AD8 PCI_DEVSEL#
D C5 AD9 C/BE0# D8 2 7 D
G11 B4 PCI_PERR# 3 6
AD10 C/BE1# PCI_PLOCK#
F8 AD11 C/BE2# D6 4 5
F11 AD12 C/BE3# A5
E7 8.2K_0804_8P4R_5%
AD13 PCI_IRDY# RP17
A3 AD14 IRDY# D3
D2 E3 PCI_SERR# 1 8
AD15 PAR PCI_STOP#
F10 AD16 PCIRST# R1 2 7
D5 C6 PCI_DEVSEL# PCI_TRDY# 3 6
AD17 DEVSEL# PCI_PERR# PCI_FRAME#
D10 AD18 PERR# E4 4 5
B3 C2 PCI_PLOCK#
AD19 PLOCK# PCI_SERR# 8.2K_0804_8P4R_5%
F7 AD20 SERR# J4
C3 A4 PCI_STOP#
AD21 STOP# PCI_TRDY#
F3 AD22 TRDY# F5
F4 D7 PCI_FRAME#
AD23 FRAME#
C1 AD24
G7 AD25 PLTRST# C14 PLT_RST# 8,17,25,27,28,31,32,33 C257
H7 D4 CLK_PCI_ICH R179
AD26 PCICLK CLK_PCI_ICH 16
D1 R2 CLK_PCI_ICH 2 1 1 2
AD27 PME# @ 10_0402_5%
G5 AD28
H6 @ 10P_0402_50V8J
AD29
G1 AD30
H3 AD31
+3VS +3VS
RP18 RP19
1 8 PCI_PIRQA# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# PCI_PIRQE# 1 8
PCI_PIRQB# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# PCI_PIRQF#
2 7 E1 PIRQB# PIRQF#/GPIO3 K6 2 7
3 6 PCI_PIRQC# PCI_PIRQC# J6 F2 PCI_PIRQG# PCI_PIRQG# 3 6
C PCI_PIRQD# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH# PCI_PIRQH# C
4 5 C4 PIRQD# PIRQH#/GPIO5 G2 4 5
U9D
25 PCIE_IRX_C_NEWTX_N1 N29 PERN1 DMI0RXN V27 DMI_MTX_IRX_N3 8
For Express 25 PCIE_IRX_C_NEWTX_P1 N28 PERP1 DMI0RXP V26 DMI_MTX_IRX_P3 8
25 PCIE_ITX_C_NEWRX_N1 2 1 0.1U_0402_16V7K PCIE_ITX_NEWRX_N1 P27 PETN1 DMI0TXN U29 DMI_ITX_MRX_N3 8
Card C258 2 1 0.1U_0402_16V7K PCIE_ITX_NEWRX_P1 P26 U28
PCI - Express
28 PCIE_IRX_C_LANTX_N3 J29 PERN3 DMI2RXN AB27 DMI_MTX_IRX_N1 8
For LAN 28 PCIE_IRX_C_LANTX_P3
C262 2
J28 PERP3 DMI2RXP AB26 DMI_MTX_IRX_P1 8
28 PCIE_ITX_C_LANRX_N3 1 0.1U_0402_16V7K PCIE_ITX_LANRX_N3 K27 PETN3 DMI2TXN AA29 DMI_ITX_MRX_N1 8
28 PCIE_ITX_C_LANRX_P3 C263 2 1 0.1U_0402_16V7K PCIE_ITX_LANRX_P3 K26 AA28
PETP3 DMI2TXP DMI_ITX_MRX_P1 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 20 of 43
5 4 3 2 1
5 4 3 2 1
D D
+RTCBATT C270
12P_0402_50V8J
1
2 1
10M_0402_5%
D10 32.768KHZ_12.5P_MC-306 X1
1
BAS40-04_SOT23-3 3 NC 4
OUT
R189
+RTCVCC
2 1
3
NC IN
+CHGRTC
1 C272 U9A
2
12P_0402_50V8J ICH_RTCX1 C23 K5
RTCX1 FWH0/LAD0 LPC_AD0 32,33
C271 2 1 ICH_RTCX2 C24 K4
RTCX2 FWH1/LAD1 LPC_AD1 32,33
0.1U_0402_16V4Z L6
2 FWH2/LAD2 LPC_AD2 32,33
ICH_RTCRST# A25 K2
RTCRST# FWH3/LAD3 LPC_AD3 32,33
ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST#
CMOS Setting, near DDR Door J1
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 32,33
RTC
LPC
+RTCVCC R190 1 2 ICH_RTCRST# 1 2 B22 J3
22 ICH_INTVRMEN INTVRMEN LDRQ0#
20K_0402_5% SHORT PADS A22 J1
22 LAN100_SLP LAN100_SLP LDRQ1#/GPIO23 FELICA_PWR 26
C273 1 2 EC_GA20 1 2 +3VS
1U_0402_6.3V6K E25 N7 EC_GA20 R191 @ 10K_0402_5%
GLAN_CLK A20GATE EC_GA20 32
AJ27 H_DPRSTP# 2 1 +1.05VS
A20M# H_A20M# 4
C13 R192 @ 56_0402_5%
LAN_RSTSYNC H_FERR#
ITPM Setting, near DDR Door J2 DPRSTP# AJ25 H_DPRSTP# 5,8,42 2
R193
1
56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# 5
R194 1 2ICH_SRTCRST# 1 2 G13
20K_0402_5% SHORT PADS LAN_RXD1 FERR# R195 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5%H_FERR# H_FERR# 4
LAN / GLAN
C274 1 2
C 1U_0402_6.3V6K D13 AD22 C
LAN_TXD_0 CPUPWRGD H_PWRGOOD 5
D12 LAN_TXD_1
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 4
R196 1 2 SM_INTRUDER# EC_KBRST# R197 2 @ 1 10K_0402_5% +3VS
1M_0402_5% 31 CR_CPPE# CR_CPPE# B10 AE22
GPIO56 INIT# H_INIT# 4
AG25
CPU
INTR H_INTR 4
+1.5VS 1 R198 2 GLAN_COMP B28 GLAN_COMPI RCIN# L3 EC_KBRST#
EC_KBRST# 32 2 1 +1.05VS
29 AZ_BITCLK_HD R200 1 2 33_0402_5% AZ_BITCLK_HD_R 24.9_0402_1% B27 +1.05VS 1 2 R199
R202 1 GLAN_COMPO
26 AZ_BITCLK_MD 2 33_0402_5%MDC@ NMI AF23 H_NMI 4
R201 330_0402_5% @
2
B
8 AZ_BITCLK_MCH R203 1 2 33_0402_5%IHDMI@ AZ_BITCLK AF6 AF24 56_0402_5%
HDA_BIT_CLK SMI# H_SMI# 4
AZ_SYNC AH4 @
HDA_SYNC
C
AH27 H_THERMTRIP# 3 1 2SC2411K_SOT23
STPCLK# H_STPCLK# 4
29 AZ_SYNC_HD R205 1 2 33_0402_5% AZ_RST# AE7 Q10
R206 1 HDA_RST#
26 AZ_SYNC_MD 2 33_0402_5%MDC@ THRMTRIP# AG26 THRMTRIP_ICH# 1 2 H_THERMTRIP#
H_THERMTRIP# 4,8
8 AZ_SYNC_MCH R207 1 2 33_0402_5%IHDMI@ AZ_SYNC 29 AZ_SDIN0_HD AF4 R208 54.9_0402_1%
HDA_SDIN0 TP12
26 AZ_SDIN1_MD AG4 HDA_SDIN1 TP12 AG27 PAD T5
1
8 AZ_SDIN2_MCH AH3 HDA_SDIN2
R209 1 2 33_0402_5% AE5 D50
IHDA
29 AZ_RST_HD# HDA_SDIN3
26 AZ_RST_MD# R210 1 2 33_0402_5%MDC@ AH11 DAN202UT106_SC70-3
SATA4RXN SATA_IRX_C_DTX_N4 24
8 AZ_RST_MCH# R211 1 2 33_0402_5%IHDMI@ AZ_RST# AZ_SDOUT AG5 AJ11 @
22 AZ_SDOUT HDA_SDOUT SATA4RXP SATA_IRX_C_DTX_P4 24
SATA4TXN AG12 SATA_ITX_DRX_N4 24 SATA ODD
AG7 AF12 SATA_ITX_DRX_P4 24
3
R212 1 HDA_DOCK_EN#/GPIO33 SATA4TXP
29 AZ_SDOUT_HD 2 33_0402_5% 31 CR_WAKE#
CR_WAKE# AE8 HDA_DOCK_RST#/GPIO34
26 AZ_SDOUT_MD R213 1 2 33_0402_5%MDC@
8 AZ_SDOUT_MCH R214 1 2 33_0402_5%IHDMI@ AZ_SDOUT SATA_LED# AG8 ENTRIP1 37,39
34 SATA_LED# SATALED#
SATA5RXN AH9 SATA_IRX_C_DTX_N5 25
+3VS 1 2 CR_WAKE# 24 SATA_IRX_C_DTX_N0 AJ16 AJ9 eSATA
SATA0RXN SATA5RXP SATA_IRX_C_DTX_P5 25
R220@ 10K_0402_5% 24 SATA_IRX_C_DTX_P0 AH16 AE10 ENTRIP2 37,39
SATA0RXP SATA5TXN SATA_ITX_DRX_N5 25
+3V_SB 1 2 CR_CPPE# 1ST HDD AF17 AF10
B 24 SATA_ITX_DRX_N0 SATA0TXN SATA5TXP SATA_ITX_DRX_P5 25 B
R222@ 10K_0402_5% AG17
SATA_LED# 24 SATA_ITX_DRX_P0 SATA0TXP
+3VS 1 2 SATA_CLKN AH18 CLK_PCIE_SATA# 16
SATA
R215 10K_0402_5% 24 SATA_IRX_C_DTX_N1 AH13 AJ18
SATA1RXN SATA_CLKP CLK_PCIE_SATA 16
24 SATA_IRX_C_DTX_P1 AJ13 SATA1RXP SATARBIAS# AJ7
2ND HDD AG14 AH7 SATARBIAS
24 SATA_ITX_DRX_N1 SATA1TXN SATARBIAS
24 SATA_ITX_DRX_P1 AF14 SATA1TXP
2
R216
10mils width
ICH9-M ES_FCBGA676 24.9_0402_1% less than
ICH9R3@
@ reserve for EMI request
500mils
1
+3VS 1 2
R617 0_0603_5%
+1.5VS 1 2 C275 @ U11 @
R618 5.1_0603_5% R619 2.2U_0402_X5R PCS3P73Z11BWHG
@ 10K_0402_5%
U11
AZ_BITCLK 1 8 1 2 @
R217 CLKIN VDD C275 0.1U_0402_16V4Z
10K_0402_5% 2 7
@ PD#/OE SSEXTR
3 FS DLY_CTRL6
1
2
4 GND 5AZ_BITCLK_HD_R
ModOUT
C670 R620
0.1U_0402_16V4Z 1.5M_0402_5%
R218 @ @
10K_0402_5% PCS3P73Z11BXG-08-CR_TDFN8_2X2 1
2
@
A A
AZ_BITCLK 2 1 AZ_BITCLK_HD_R
0_0402_5% R204
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 21 of 43
5 4 3 2 1
5 4 3 2 1
2
4.7K_0402_5% 2 1 +3VS 1 R262 2 LVDS_SEL
R226 10K_0402_5%
1 6 ICH_SMBDATA
14,15,16,25,27 PM_SMBDATA
CLK_14M_ICH 1 2 1 2
5
U9C R228 C276
Q4A ICH_SMBCLK @ 10_0402_5% @ 4.7P_0402_50V8C
G16 SMBCLK SATA0GP/GPIO21 AH23 SPK_SEL 29
2N7002DW-T/R7_SOT363-6 4 ICH_SMBCLK ICH_SMBDATA BIOS need to CLK_48M_ICH
14,15,16,25,27 PM_SMBCLK 3
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19 LVDS_SEL 17 1
R229
2 1
C277
2
SATA
GPIO
E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21 BT_PWR 26 set GPIO
D 2N7002DW-T/R7_SOT363-6 ME_EC_CLK1 C17 AD20 @ 10_0402_5% @ 4.7P_0402_50V8C D
Q4B SMLINK0 SATA5GP/GPIO37 BT_RST# 26
+3V_SB R230 1 2 10K_0402_5% LINKALERT# ME_EC_DATA1 B18 PM_PWROK 1 2
R232 10K_0402_5% ME_EC_CLK1 SMLINK1
1 2 CLK14 H1 CLK_14M_ICH CLK_14M_ICH 16
R231 @ 10K_0402_5%
R233 10K_0402_5% ME_EC_DATA1 ICH_RI# AF3 CLK_48M_ICH
R234
1
1
2
2 10K_0402_5% ICH_RI#
F19 RI# clocks CLK48 CLK_48M_ICH 16
S4_STATE# 1 2 +3V_SB
R236 1 2 10K_0402_5% XDP_DBRESET# R4 P1 R235 @ 10K_0402_5%
XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK ICH_LOW_BAT#
4 XDP_DBRESET# G19 SYS_RESET# 2 1
+3V_SB R238 1 2 10K_0402_5% EC_LID_OUT# C16 R237 8.2K_0402_5%
SLP_S3# PM_SLP_S3# 32
8 PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# 32
+3VS R240 1 2 8.2K_0402_5% PM_CLKRUN# G17
SYS / GPIO
SLP_S5# PM_SLP_S5# 32
32 EC_LID_OUT# EC_LID_OUT# A17 R239 2 1 @ 0_0402_5%
SMBALERT#/GPIO11 S4_STATE#
S4_STATE#/GPIO26 C10
R242 1 2 1K_0402_5% EC_SWI# A14 SB_RSMRST# 1 Q11 3
C
+3V_SB 16 H_STP_PCI# STP_PCI# EC_RSMRST# 32
E19 G20 PM_PWROK 1 2
E
16 H_STP_CPU# STP_CPU# PWROK PM_PWROK 8,32
+3VS R244 1 2 10K_0402_5% SERIRQ R241 MMBT3906_SOT23-3
R245 1 2 @ 8.2K_0402_5% EC_THERM# PM_CLKRUN# L4 M2 10K_0402_5%
B
Power MGT
PM_DPRSLPVR 8,42
2
CLKRUN# DPRSLPVR/GPIO16
THRM# not 1 2 +3V_SB
+3VS R246 1 2 10K_0402_5% OCP# used, 8.2K to 25,32 EC_SWI# EC_SWI# E20 B13 ICH_LOW_BAT# R243
WAKE# BATLOW#
1
SERIRQ M5 4.7K_0402_5%
10K PU to 32,33 SERIRQ SERIRQ
+3VS 1 2 ICH_ACIN EC_THERM# AJ23 R3 D11B D11A
+3VS. 32 EC_THERM# THRM# PWRBTN# PBTN_OUT# 32
R248 330K_0402_5% BAV99DW-7_SOT363 BAV99DW-7_SOT363
1 2 VGATE D21 D20 1 2
32,34,36 ACIN 8,32,42 VGATE VRMPWRGD LAN_RST#
D12 CH751H-40PT_SOD323-2 R247 0_0402_5%
PAD TP11 A20 D22 SB_RSMRST#
T6
6
R250 1 8.2K_0402_5% EC_SMI# TP11 RSMRST#
2 2 1
+3V_SB
R251 1 2 10K_0402_5% EC_SCI# 4 OCP# OCP#
ICH_ACIN
AG19 GPIO1 CK_PWRGD R5 CK_PWRGD 16
R249
2.2K_0402_5%
RSMRST# circuit
AH21 GPIO6
+3VS 1 R807 2 100K_0402_5% 2HDD_DET#
26 FM_I2CCLK AG21 GPIO7 CLPWROK R6 PM_PWROK
1 2 32 EC_SMI# EC_SMI# A21
C R808 2HDD@ 1K_0402_5% EC_SCI# GPIO8 +3VS C
32 EC_SCI# C12 GPIO12 SLP_M# B16
26 CAM_PWR C21 GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 8
1
R253 1 2 8.2K_0402_5% BT_DET# K1 B19
GPIO
+3VS
Controller Link
2HDD_DET# GPIO18 CL_CLK1 R252
AF8 GPIO20
BT_DET# AJ22 F22 3.24K_0402_1%
26 BT_DET# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 8
+3V_SB R255 2 1 @ 10K_0402_5% GPIO57 A9 C19
26 FM_I2CDAT GPIO27 CL_DATA1
R257 2 1 100K_0402_5% D19
26 FM_I2CINT
2
GPIO28
16 CLKREQ_SATA# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25 +CL_VREF0_ICH
LAN_DSM# AE19 A19 Width:Spacing
28 LAN_DSM# SLOAD/GPIO38 CL_VREF1
1
+3VS 1 R809 2 100K_0402_5% CIR_EN# CIR_EN# AG22 12mil:12mil 2
SDATAOUT0/GPIO39 R254
1 2 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 8
R810 CIR@ 1K_0402_5% AH24 D18 453_0402_1% C278
28 LAN_ISOLATE# GPIO49 CL_RST1#
GPIO57 A8 0.1U_0402_16V4Z
GPIO57/CLGPIO5 SB_INT_FLASH_SEL# 33 1
+3VS 1 R264@ 2 10K_0402_5% LAN_DSM# A16
2
SB_SPKR MEM_LED/GPIO24 SUS_PWR_ACK 1
29 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 2 +3V_SB
iTPM Physical Presence AJ24 C11 R256 10K_0402_5%
MISC
8 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20
TP8 TP3 WOL_EN/GPIO9
Assert = iTPM Physical Presence Enable T7 PAD AH20 TP8
CLGPIO5 TP9 AJ20 SUS_PWR_ACK Mobile Platform used only
De-assert = iTPM disable T8 PAD
TP10 TP9
Mobil Platform T9 PAD AJ21 TP10
**Only used in iAMT w/ME Firmware
GPIO57 Desktop Platform used only ICH9-M ES_FCBGA676 GPIO10 Desktop Platform used only
ICH9R3@
B
ICH9M Strap Pin Internal TPM Strap(Internal pull-down) Internal VR Enable Strap B
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) Flash Descriptor Security Override Strap
+3VS 1 2 ICH_SPI_MOSI 20 SPI_MOSI Low= Disable
R258 @ 1K_0402_5% Low= Descriptor Security override
High= iTPM enable by MCH strap*
Low = Internal VR Disabled GPIO33 High= Default* (Internal pull-up)
ICH_INTVRMEN High = Internal VR Enabled(Default)
No Reboot Strap (Internal pull-up)
+RTCVCC 1 2 ICH_INTVRMEN 21
+3VS 1 2 SB_SPKR SB_SPKR Low= *Default R259 330K_0402_5%
R261 @ 1K_0402_5% 1 2 ICH8M LAN100 SLP Strap
High= "No Reboot" R260 @ 0_0402_5%
LAN100_SLP 21
DMI Termination Voltage
(Internal VR for VccLAN1.05 and VccCL1.05) GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)
Boot BIOS Strap (Internal pull-up) Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
1 2 PCI_GNT#0 20
R263 @ 1K_0402_5%
0 0 RESERVED
1
R265
2
@ 1K_0402_5%
SPI_CS#1 20 0 1 SPI
1 0 PCI XOR Chain Entrance Strap
1 1 LPC* (Default) ICH_TP3 HDA_SDOUT Description
(Internal pull-up) (Internal pull-down)
0 0 RSVD
A16 Swap Override Strap +3VS
R266 @ 1K_0402_5%
AZ_SDOUT 21 0 1 Enter XOR Chain
A 1 2 STRAP_A16 20 A
R267 @ 1K_0402_5% Low= A16 swap override Enable 1 0 Normal Operation (Default)
PCI_GNT#3 ICH_TP3
High= Default* (Internal pull-up) R268 @ 1K_0402_5% 1 1 Set PCIE port config bit 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 22 of 43
5 4 3 2 1
5 4 3 2 1
U9F
U9E
+RTCVCC A23 VCCRTC6uA at G3 state VCC1_05[01] A15 +1.05VS
1 1 1 VCC1_05[02] B15 1 1 AA26 VSS[001] VSS[107] H5
+ICH_V5REF A6 2mA C15 AA27 J23
C279 C280 C281 V5REF VCC1_05[03] C282 C283 VSS[002] VSS[108]
VCC1_05[04] D15 AA3 VSS[003] VSS[109] J26
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
2 2 2 +ICH_V5REF_SUS VCC1_05[05] 2 2 VSS[004] VSS[110]
AE1 V5REF_SUS 2mA VCC1_05[06] F15 AB1 VSS[005] VSS[111] AC22
VCC1_05[07] L11 AA23 VSS[006] VSS[112] K28
Reserve for test 2N7002DW-T/R7_SOT363-6
AA24 VCC1_5_B[01] 646mA 1634mA VCC1_05[08] L12 AB28 VSS[007] VSS[113] K29
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB29 VSS[008] VSS[114] L13
+5V_SB 1 6 +5VALW D13 AB24 L16 AB4 L15
Q16A CH751H-40PT_SOD323-2 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AB5 VSS[010] VSS[116] L2
SBPWR_EN# STAR@ +3VS 2 1 AC24 L18 AC17 L26
Q16B VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS VSS[011] VSS[117]
AC25 M11 AC26 L27
2
VCC1_5_B[06] VCC1_05[13] VSS[012] VSS[118]
5
CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 AC3 VSS[014] VSS[120] L7 D
4 3 1 R593 2 +VSB 100_0402_5% AE25 VCC1_5_B[09] VCC1_05[16] P18 1 MBK1608121YZF_0603 AD1 VSS[015] VSS[121] M12
47K_0402_5% C284 AE26 T11 AD10 M13
VCC1_5_B[10] VCC1_05[17] VSS[016] VSS[122]
1 R594 2 STAR@ 1U_0402_6.3V4Z AE27 VCC1_5_B[11] VCC1_05[18] T18 C285 C286 AD12 VSS[017] VSS[123] M14
330K_0402_5% 2 10U_0805_10V4Z
AE28 VCC1_5_B[12] VCC1_05[19] U11 AD13 VSS[018] VSS[124] M15
STAR@ 2
AE29 VCC1_5_B[13] VCC1_05[20] U18 AD14 VSS[019] VSS[125] M16
F25 VCC1_5_B[14] VCC1_05[21] V11 AD17 VSS[020] VSS[126] M17
G25 VCC1_5_B[15] VCC1_05[22] V12 AD18 VSS[021] VSS[127] M23
D14 H24 V14 +1.05VS AD21 M28
+5VALW CH751H-40PT_SOD323-2 VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]
H25 VCC1_5_B[17] VCC1_05[24] V16 AD28 VSS[023] VSS[129] M29
+3V_SB 2 1 J24 VCC1_5_B[18] VCC1_05[25] V17 AD29 VSS[024] VSS[130] N11
VCCA3GP
Q12 J25 V18 1 AD4 N12
VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
1
S
@ PJ37 R270 2 K25 C287 AD6 N14
1
G
JUMP_43X39 100_0402_5% VCC1_5_B[21] 4.7U_0805_10V4Z VSS[027] VSS[133]
35 SBPWR_EN# 2 L23 VCC1_5_B[22] AD7 VSS[028] VSS[134] N15
@ C289 2
1 L24 VCC1_5_B[23] 23mA VCCDMIPLL R29 AD9 VSS[029] VSS[135] N16
2
VCC1_5_B[25]
@
2
Vgs=-4.5V, Id=3A,Rds<97mohm M25 VCC1_5_B[26] 48mA VCC_DMI[1]
VCC_DMI[2] Y23 +1.05VS AE14
VSS[031]
VSS[032]
VSS[137]
VSS[138] N26
N23 VCC1_5_B[27] AE16 VSS[033] VSS[139] N27
+5V_SB N24 AB23 AE17 P12
VCC1_5_B[28] V_CPU_IO[1] VSS[034] VSS[140]
N25 VCC1_5_B[29] 2mA V_CPU_IO[2] AC23 1 1 1 AE2 VSS[035] VSS[141] P13
P24 VCC1_5_B[30] AE20 VSS[036] VSS[142] P14
+1.5VS_PCIE_ICH P25 AG29 C290 C291 C292 AE24 P15
VCC1_5_B[31]
R24 VCC1_5_B[32] 308mAVCC3_3[01]
VCC3_3[02] AJ6 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z AE3
VSS[037]
VSS[038]
VSS[143]
VSS[144] P16
+1.5VS L14 2 1 10U_0805_10V4Z 2.2U_0603_6.3V6K R25 AC10 AE4 P17
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[33] VCC3_3[07] VSS[039] VSS[145]
1 R26 VCC1_5_B[34] AE6 VSS[040] VSS[146] P2
1 1 1 R27 VCC1_5_B[35] VCC3_3[03] AD19 AE9 VSS[041] VSS[147] P23
VCCP_CORE
+ T24 AF20 +3VS AF13 P28
C293 C294 C295 C296 VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27 VCC1_5_B[37] VCC3_3[05] AG24 AF16 VSS[043] VSS[149] P29
220U_D2_4VM_R15 T28 AC20 close to AG29 close to AG24 AF18 P4
2 2 10U_0805_10V4Z
2 2 VCC1_5_B[38] VCC3_3[06] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[044] VSS[150]
T29 VCC1_5_B[39] AF22 VSS[045] VSS[151] P7
C
U24 VCC1_5_B[40] 1 1 1 1 1 1 1 AH26 VSS[046] VSS[152] R11 C
U25 B9 C297 AF26 R12
VCC1_5_B[41] VCC3_3[08] C298 C299 C300 C301 C302 C303 VSS[047] VSS[153]
V24 VCC1_5_B[42] VCC3_3[09] F9 AF27 VSS[048] VSS[154] R13
V25 G3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF5 R14
+1.5VS +1.5VS_SATAPLL_ICH VCC1_5_B[43] VCC3_3[10] 2 2 2 2 2 2 2 VSS[049] VSS[155]
U23 VCC1_5_B[44] VCC3_3[11] G6 AF7 VSS[050] VSS[156] R15
PCI
W24 VCC1_5_B[45] VCC3_3[12] J2 AF9 VSS[051] VSS[157] R16
L15 1 2 W25 J7 close to AD19 close to B9, G6, K7 close to AJ6 AG13 R17
MBK1608121YZF_0603 VCC1_5_B[46] VCC3_3[13] VSS[052] VSS[158]
1 1 K23 VCC1_5_B[47] VCC3_3[14] K7 AG16 VSS[053] VSS[159] R18
Y24 +ICH_HDA AG18 R28
C304 C305 VCC1_5_B[48] NIHDMI@ VSS[054] VSS[160]
Y25 VCC1_5_B[49] AG20 VSS[055] VSS[161] T12
10U_0805_10V4Z 1U_0402_6.3V4Z 11mA AJ4 R271 0_0603_5% +3VS AG23 T13
2 2 VCCHDA VSS[056] VSS[162]
1 +1.5VS AG3 VSS[057] VSS[163] T14
47mA 11mA AJ3 R272 0_0603_5% AG6 T15
VCCSUSHDA C306 IHDMI@ VSS[058] VSS[164]
AJ19 VCCSATAPLL AG9 VSS[059] VSS[165] T16
0.1U_0402_16V4Z AH12 T17
2 VSS[060] VSS[166]
1342mA VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T10 AH14 VSS[061] VSS[167] T23
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T11 AH17 VSS[062] VSS[168] B26
1 1 AD15 VCC1_5_A[02] AH19 VSS[063] VSS[169] U12
AD16 +ICH_SUSHDA AH2 U13
C307 C308 VCC1_5_A[03] NIHDMI@ VSS[064] VSS[170]
AE15 VCC1_5_A[04] VCCSUS1_5[1] AD8 AH22 VSS[065] VSS[171] U14
ARX
1U_0402_6.3V4Z 1U_0402_6.3V4Z AF15 R273 0_0603_5% +3V_SB AH25 U15
2 2 VCC1_5_A[05] VSS[066] VSS[172]
AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 +VCCSUS1_5_ICH_INT 1 +VCCSUS1_5_ICH_INT AH28 VSS[067] VSS[173] U16
close to AE15 close to AF11 AH15 1 R274 0_0603_5% AH5 U17
VCC1_5_A[07] C310 C309 IHDMI@ VSS[068] VSS[174]
AJ15 VCC1_5_A[08] 212mA AH8 VSS[069] VSS[175] AD23
A18 0.1U_0402_16V4Z AJ12 U26
VCCSUS3_3[01] 0.1U_0402_16V4Z 2 VSS[070] VSS[176]
AC11 VCC1_5_A[09]
VCCPSUS VCCSUS3_3[02] D16 AJ14 VSS[071] VSS[177] U27
2
Symbol S0 S3 S4/S5 AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ17 VSS[072] VSS[178] U3
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 AJ8 VSS[073] VSS[179] V1
AF11 VCC1_5_A[12] B11 VSS[074] VSS[180] V13
ATX
VCCLAN1_05 VCC_1_05 VCCLAN3_3 VCCLAN3_3 AG10 VCC1_5_A[13] B14 VSS[075] VSS[181] V15
AG11 VCC1_5_A[14] B17 VSS[076] VSS[182] V23
AH10 VCC1_5_A[15] B2 VSS[077] VSS[183] V28
VCCCL1_5 VCC_1_5_A VCCCL3_3 VCCCL3_3 close to AC9 AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3V_SB B20 VSS[078] VSS[184] V29
B B23 VSS[079] VSS[185] V4 B
+1.5VS AC9 VCC1_5_A[17] 1 1 1 B5 VSS[080] VSS[186] V5
VCCCL1_05 VCC_1_05 VCCCL3_3 VCCCL3_3 B8 VSS[081] VSS[187] W26
1 1 AC18 C311 C312 C313 C26 W27
C314 C315 VCC1_5_A[18] 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19 VCC1_5_A[19] C27 VSS[083] VSS[189] W3
2 2
VCCSUS1_5 VCC_1_5_A VCCSUS3_3 VCCSUS3_3 VCCSUS3_3[06] T1 close to T1 close to AF1 2 E11 VSS[084] VSS[190] Y1
0.1U_0402_16V4Z AC21 T2 E14 Y28
2 2 VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
VCCSUS3_3[08] T3 E18 VSS[086] VSS[192] Y29
VCCSUS1_05 VCC_1_05 VCCSUS3_3 VCCSUS3_3 0.1U_0402_16V4Z G10 T4 E2 Y4
VCC1_5_A[21] VCCSUS3_3[09] VSS[087] VSS[193]
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 E21 VSS[088] VSS[194] Y5
Internal voltage regulators power these wells inside the ICH9 VCCSUS3_3[11] T6 E24 VSS[089] VSS[195] AG28
close to AC14 AC12 U6 E5 AH6
VCCPUSB
and current for this rail is accounted for in the sourcing voltage VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]
AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 E8 VSS[091] VSS[197] AF2
rail current requirements. AC14 V6 F16 B25
VCC1_5_A[25] VCCSUS3_3[14] VSS[092] VSS[198]
close to AC7 close to AJ5 VCCSUS3_3[15] V7 F28 VSS[093]
+1.5VS AJ5 VCCUSBPLL 11mA VCCSUS3_3[16] W6 F29 VSS[094]
1 1 VCCSUS3_3[17] W7 G12 VSS[095]
USB CORE
1 1 1 1 1 1 1 1
C697 C698 C699 C700 C701 C702 C703 C704
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2HDD@ 2HDD@ 2HDD@ 2HDD@
2 2 2 2 2 2 2 2
D D
SSD HDD need 400mA for 3V(PHISON) SSD HDD need 400mA for 3V(PHISON)
+3VS +3VS
+3VS rail reserve for SSD +3VS rail reserve for SSD
1 1 1 1 1 1 1
C705 C706 1 C707 C708 C709 C710 C711 C712
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ @ @ @ @ @ @ @
2 2 2 2 2 2 2
2
JHDD0 JHDD2
GND 1 GND 1
2 SATA_ITX_C_DRX_P0 C713 1 2 0.01U_0402_25V7K 2 SATA_ITX_C_DRX_P1 C714 1 2 0.01U_0402_25V7K 2HDD@
A+ SATA_ITX_DRX_P0 21 A+ SATA_ITX_DRX_P1 21
3 SATA_ITX_C_DRX_N0 C715 1 2 0.01U_0402_25V7K 3 SATA_ITX_C_DRX_N1 C716 1 2 0.01U_0402_25V7K 2HDD@
A- SATA_ITX_DRX_N0 21 A- SATA_ITX_DRX_N1 21
GND 4 GND 4
5 SATA_IRX_DTX_N0 C717 1 2 0.01U_0402_25V7K 5 SATA_IRX_DTX_N1 C718 1 2 0.01U_0402_25V7K 2HDD@
B- SATA_IRX_C_DTX_N0 21 B- SATA_IRX_C_DTX_N1 21
6 SATA_IRX_DTX_P0 C719 1 2 0.01U_0402_25V7K 6 SATA_IRX_DTX_P1 C720 1 2 0.01U_0402_25V7K 2HDD@
B+ SATA_IRX_C_DTX_P0 21 B+ SATA_IRX_C_DTX_P1 21
GND 7 GND 7
V33 8 +3VS
V33 9 VCC3.3 8 +3VS
C 10 9 C
V33 VCC3.3
GND 11 VCC3.3 10
GND 12 GND 11
GND 13 GND 12
V5 14 +5VS GND 13
V5 15 VCC5 14 +5VS
V5 16 VCC5 15
GND 17 VCC5 16
Reserved 18 GND 17
GND 19 RESERVED 18
V12 20 23 GND GND 19
24 GND V12 21 24 GND VCC12 20
23 GND V12 22 VCC12 21
VCC12 22
OCTEK_SAT-22SO1G_RV
@ SUYIN_127043FB022G208ZR_RV
the footprint is temp
PJDLC05_SOT23-3 JUSB
1 VCC GND 5
20 USB20_N2 2 D- GND 6
20 USB20_P2 3 D+ GND 7
JODD 4 8
GND GND
1 P-TWO_CU304G-A0G1G-P
GND SATA_ITX_C_DRX_P4 C729 1
A+ 2 2 0.01U_0402_25V7K SATA_ITX_DRX_P4 21
@
3 SATA_ITX_C_DRX_N4 C730 1 2 0.01U_0402_25V7K IOGND
A- SATA_ITX_DRX_N4 21
GND 4
5 SATA_IRX_DTX_N4 C731 1 2 0.01U_0402_25V7K
B- SATA_IRX_C_DTX_N4 21
6 SATA_IRX_DTX_P4 C732 1 2 0.01U_0402_25V7K
B+ SATA_IRX_C_DTX_P4 21
GND 7
DP 8
+5V 9 +5VS
A +5V 10 A
MD 11
15 GND GND 12
14 GND GND 13
SANTA_206401-1_RV
@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 24 of 43
5 4 3 2 1
5 4 3 2 1
eSATA/USB
W=60mils
+5VALW 1.4A
U40
+USB_VCCB
1 GND OUT 8
2 IN OUT 7
D 3 IN OUT 6 D
26,32 USB_EN# 4 EN# FLG 5 1 R699 2 USB_OC#2 20
0_0402_5%
G528_SO8 1
C743
4.7U_0805_10V4Z
@
2
+USB_VCCB
W=60mils
0.1U_0402_16V4Z
1 1 1
C748 +
@ C749 C750
2 2
2
150U_D_6.3VM 1000P_0402_50V7K
D62
2
1
C
3 eSATA/USB Conn C
PJDLC05_SOT23-3 JESATA
1 USB
VBUS
20 USB20_N3 2 D-
20 USB20_P3 3 D+
4 GND
5 GND
C739 1 2 0.01U_0402_25V7K SATA_ITX_C_DRX_P5 6
21 SATA_ITX_DRX_P5 A+ ESATA
C740 1 2 0.01U_0402_25V7K SATA_ITX_C_DRX_N5 7
21 SATA_ITX_DRX_N5 A-
8 GND SHIELD 12
C742 1 2 0.01U_0402_25V7K SATA_IRX_DTX_N5 9 13
21 SATA_IRX_C_DTX_N5 B- SHIELD
C744 1 2 0.01U_0402_25V7K SATA_IRX_DTX_P5 10 14
21 SATA_IRX_C_DTX_P5 B+ SHIELD
11 GND SHIELD 15
FOX_3Q318111 IOGND
@
RN4 1 23
CN7 CP_USB# GND
9 CPUSB# Thermal_Pad 21 20 PCIE_ITX_C_NEWRX_N1 24 PETn0
1
10K_0402_5% 20 PCIE_ITX_C_NEWRX_P1 25
RN5 0.1U_0402_16V4Z RCLKEN PETp0
18 RCLKEN 26 GND GND 29
5
UN2 2
30
2
A B G577NSR91U_TQFN20_4x4 GND A
4 CLKREQ_NEW# 28
CLKREQ_NEW# 16
2
Y GND
1 A SANTA_130801-5_RT
6
NC7SZ32P5X_NL_SC70-5 @
3
Q21A
2N7002DW-T/R7_SOT363-6
RCLKEN 2 another at page35 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
SCHEMATIC MB A4571
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401605 E
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 16, 2009 Sheet 25 of 43
5 4 3 2 1
5 4 3 2 1
2
C751 BT@ +5VALW +USB_VCCA +USB_VCCA
R718 0.1U_0402_16V4Z U42
1M_0402_5% 1 8 W=60mils JUSBB
BT@ GND OUT
2 IN OUT 7 1 1
3
S
R719 BT@ 3 6 2
1
G IN OUT 2
1 2 2 25,32 USB_EN# 4 EN# FLG 5 1 2 USB_OC#0 20 3 3
D 100K_0402_5% 1 R720 0_0402_5% 4 D
Q22 BT@ G528_SO8 4
2
D 5
1
5
1
D BT@ C753 AO3413_SOT23 C752
Bluetooth Connector 6 6
22 BT_PWR 2 1000P_0402_50V7K 4.7U_0805_10V4Z 20 USB20_N0 7
G JBT 2 @ 7
+BT_VCC 20 USB20_P0 8 8
BT@ Q23 1
S 1 9
3
2N7002_SOT23 1 9
20 USB20_P5 2 2 20 USB20_N1 10 10
20 USB20_N5 3 3 20 USB20_P1 11 11
27 WLAN_BT_CLK 4 4 12 12
22 BT_DET# 1 BT@ 2 5 13
5 GND
22 BT_RST# 1 BT@ 2BT_RESET# R721 0_0402_5% 6 6 14 GND
R722 100K_0402_5% 7
27 WLAN_BT_DATA 7
8 E&T_6905-E12N-00R
8
+3VS 1 2 9 9 @
R723 @ 10
4.7K_0402_5% 10
+BT_VCC
2
C754 (MAX=200mA)
1
0.1U_0402_16V4Z 11 GND1
BT@ C755 C756 BT@R724
BT@R724 12
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5% GND2
BT@ 2 BT@ ACES_87213-1000G
1
@
+3VS
FM tuner FM_I2CCLK 1 2
R725 FM@ 4.7K_0402_5%
FM_I2CDAT 1 2
C JFM R726 FM@ 4.7K_0402_5% C
1 +3VS FM_I2CINT 1 2
1 R727 FM@ 100K_0402_5%
2
Finger printer 2
3 3
4
FM_I2CCLK
FM_I2CDAT
FM_I2CCLK 22
4 FM_I2CDAT 22
5 FM_I2CINT_R 1 2FM_I2CINT
5 FM_I2CINT 22
6 FM_LINE_R 29 R728 @ 0_0402_5%
JFP 6
7 7 FM_LINE_L 29
+3VS 1 R114 2 +3VS_FP 1 1 8 8
0_0603_5% 1 2 11 9
20 USB20_N4 2 GND 9
FP@ C757 3 5 12 10
20 USB20_P4 3 GND GND 10
0.1U_0402_16V4Z 4 6
FP@ 4 GND ACES_88514-1041
1
2 ACES_85201-04051 @
2 R110 @
1 0_0603_5%
3 FP@
2
D63 FP@
PJDLC05_SOT23-3 Felica
+FLICA_VCC
+5VS
JFEL
1 +5VS
1
2
2 2 USB20_N9 20 1
3 R729 FLICA@
3 USB20_P9 20
4 C758 FLICA@ 1M_0402_5%
4 0.1U_0402_16V4Z C759 FLICA@
5 5
3
B 2 R730 FLICA@ Q24
S
0.1U_0402_16V4Z B
6 2
MDC 1.5 Conn.
1
6 G
G1 7 1 1 2 2
1
8 3 100K_0402_5%
G2
1
R131 FLICA@ Q25 D D
2
1
+MDC +3V_SB ACES_87151-06051 0_0603_5% D83 @ 2 C760 FLICA@ AO3413_SOT23-3
21 FELICA_PWR
@ FLICA@ PJDLC05_SOT23-3 G 1000P_0402_50V7K FLICA@
S
3
2N7002_SOT23-3 1
1 1 1 1 +FLICA_VCC
C761 C762 C763 C764
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 MDC@ 2 MDC@ 2 MDC@ 2 MDC@
Int. Camera
JMDC R732
W=20mils
1 2 +3V_SB
R731 NIHDMI@ 0_0603_5% 1 2+CAM_VDD 1 2 +5VS
+5VALW
1 2 +MDC 1 2 +VCCSUS1_5_ICH_INT @ 0_0603_5% C765
GND1 RES0 R733 IHDMI@ 0_0603_5% R821 0.1U_0402_16V4Z +5VS
21 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
2
5 6 +3V_SB +5VS 1 2 CAM@ 1 2 R181
GND2 3.3V CAM@ 0_0603_5% @ 0_0402_5% R734
21 AZ_SYNC_MD 7 IAC_SYNC GND3 8
AZ_SDIN1_MD_R 9 10 JCAM L26 1M_0402_5%
IAC_SDATA_IN GND4 @ C766
21 AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD 21 1 1 1 1 2 2 USB20_N11 20
3
S
USB20_N11_R R735@ 0.1U_0402_16V4Z
2 2
1
2
G
USB20_P11_R @
R736 3 3 1 2
100K_0402_5%
2
4 4 4 4 3 3
GND
GND
GND
GND
GND
GND
USB20_P11 20
1
10_0402_5% D
5 5
D
2
1
@ WCM-2012-900T_0805 C767 Q26
GND1 6 22 CAM_PWR 2
2 1 AZ_SDIN1_MD_R ACES_88018-124G
GND2 7 1 2 R182 G 1000P_0402_50V7K AO3413_SOT23-3
13
14
15
16
17
18
A 21 AZ_SDIN1_MD A
R737 33_0402_5% MDC@ MDC@ 1 @ 0_0402_5% Q27 S @ @
3
C768 ACES_88266-05001 2N7002_SOT23-3 1
+CAM_VDD
Connector for MDC Rev1.5 10P_0402_50V8J @ @
@
2
1
RM1 45 46
4.7K_0402_5% 45 46
47 47 48 48
FOX_AS0B226-S40N-7F @ 49 50
49 50
@ J3GSIM 51 51 52 52
2
+UIM_PWR +UIM_PWR 1 4 53 54
UIM_RESET VCC GND UIM_VPP GND1 GND2
2 RST VPP 5
1
1 UIM_CLK 3 6 UIM_DATA
DM1 CLK I/O FOX_AS0B226-S40N-7F
CM13 RLZ20A_LL34 7 8 1 @
NC NC
1
1
0.1U_0402_16V4Z 3G@ 1 1
3G@ 2 MOLEX_47273-0001~D CM14
2
2
+UIM_PWR
RM2 RM3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 1 2
1 1 1 1 1 1 +3V_WLAN 10K_0402_5% 100K_0402_5%
2
+3V_WLAN WIMAX@ WIMAX@
G
+3V_WLAN +1.5VS CM17 CM18 CM19 CM20 CM21 CM22
2
RM4 WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ LED_WIMAX#_R 1 3
2 2 2 2 2 2 LED_WIMAX# 34
1 2 100K_0402_5% JWLAN SW1 DM5
S
1 2 0.01U_0402_25V4Z 4.7U_0805_10V4Z 0.01U_0402_25V4Z 4.7U_0805_10V4Z 5 DAN217_SC59 QM1
32 WLAN_WAKE# 1 2 G2
26 WLAN_BT_DATA 3 4 4 @ 2N7002_SOT23-3
3 4 G1 RM5 WIMAX@
26 WLAN_BT_CLK 5 5 6 6
16 CLKREQ_WLAN# 7 8 1 2 +3V_WLAN 1 2
1
7 8 100K_0402_5% RM6 @ 0_0402_5%
9 9 10 10 3 3
16 CLK_WLAN# 11 11 12 12 2 2 KILL_SW# 32
16 CLK_WLAN 13 13 14 14 1 1
15 15 16 16
17 18 1BS003-1210L_3P
17 18 XMIT_OFF# WLAN@
19 19 20 20
21 22 PLT_RST#
21 22 PLT_RST# 8,17,20,25,28,31,32,33
20 PCIE_IRX_C_WLANTX_N4 23 23 24 24
25 26 +3V_WLAN KS@
20 PCIE_IRX_C_WLANTX_P4 25 26
27 28 CM23 0.1U_0402_16V4Z
27 28
29 29 30 30 PM_SMBCLK 14,15,16,22,25 1 2
20 PCIE_ITX_C_WLANRX_N4 31 31 32 32 PM_SMBDATA 14,15,16,22,25
5
20 PCIE_ITX_C_WLANRX_P4 33 33 34 34
35 36 2
P
35 36 USB20_N7 20 32 WL_OFF# B
WLAN/ WiFi 37 38 USB20_P7 20 4 XMIT_OFF#
37 38 KILL_SW# 1 Y
+3V_WLAN 39 39 40 40 A
G
41 42 LED_WIMAX#_R WiMax
41 42 UM1
43 44
3
43 44 NC7SZ08P5X_NL_SC70-5
45 45 46 46
47 48 KS@
47 48
49 49 50 50
51 51 52 52
53 GND1 GND2 54
ACES_88911-5204
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
@ SCHEMATIC MB A4571
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 27 of 43
5 4 3 2 1
1 2 +3V_LAN
+3V_LAN
UL1 RL1 3.6K_0402_5%
UL2 Close to Pin16,37,46,53
20 PCIE_IRX_C_LANTX_P3 CL1 1 2 0.1U_0402_16V7K PCIE_IRX_LANTX_P3 29 45 LAN_DO 4 5 2
HSOP EEDO LAN_DI DO GND CL3
EEDI/AUX 47 3 DI ORG 6
20 PCIE_IRX_C_LANTX_N3 CL2 1 2 0.1U_0402_16V7K PCIE_IRX_LANTX_N3 30 48 LAN_SK 2 7 @ 1 2
HSON EESK LAN_CS SK NC 0.1U_0402_16V4Z CL4
EECS 44 1 CS VCC 8 +3V_LAN
1
0.1U_0402_16V4Z
20 PCIE_ITX_C_LANRX_P3 23 HSIP 1 2
CAT93C46VI-GT3_SO8 0.1U_0402_16V4Z CL5
D 24 @ 1 2 D
20 PCIE_ITX_C_LANRX_N3 HSIN
54 0.1U_0402_16V4Z CL6
LED3
LED2 55 1 2
33 56 LAN_LINK# 0.1U_0402_16V4Z CL7
CLKREQB LED1 LAN_ACTIVITY#
LED0 57
16 CLK_LAN 26 REFCLK_P 1 2
RL2 0_0603_5%
27 3 LAN_MDI0+ 8102E@ +LAN_AVDD12
16 CLK_LAN# REFCLK_N MDIP0
4 LAN_MDI0-
+3V_LAN MDIN0 LAN_MDI1+ LL1
8,17,20,25,27,31,32,33 PLT_RST# 20 PERSTB MDIP1 6
7 LAN_MDI1- +LAN_CTRL18 1 2
LOM_WAKE# MDIN1 LAN_MDI2+ 4.7UH_1008HC-472EJFS-A_5%_1008
1 2 MDIP2 9
RL3 100K_0402_5% +LAN_CTRL18 1 10 LAN_MDI2- 8111C@ +LAN_DVDD12
SROUT12 MDIN2 1 2
12 LAN_MDI3+ Layout Note: LL1 must be
MDIP3 LAN_MDI3- within 500mil to Pin1 CL8 CL9
+LAN_DVDD12 5 FB12 MDIN3 13
1 CL8,CL9 must be within 22U_0805_6.3V6M 0.1U_0402_16V4Z
+3VS CL11 +3V_LAN RL4 62 500mil to L18 8111C@ 2 1
1 2
0.01U_0402_25V4Z 0_0402_5% 8111C@ ENSR 0.1U_0402_16V4Z CL10
DVDD12 21 +LAN_DVDD12
@ 1 2 64 32 1 2
RSET DVDD12
1
+3VS_DVDD RA1
Codec 10U_0805_10V4Z 30mil 2 1
1 1 0_0603_5%
+3VS
Audio regulator
CA1 CA2
1
1 1 2 2 +3VS
+AVDD RA2
2 2 @ PJ33
RA3 40mil 0.1U_0402_16V4Z
0_0603_5%
JUMP_43X79
+1.5VS_DVDIO NIHDMI@
+VDDA 2 1 10U_0805_10V4Z 0.1U_0402_16V4Z
2
0_0603_5% LA1 +1.5VS
CA3
1
CA4
1
CA5
1
CA6
1
10U_0805_10V4Z 20mil
1 2 +VDDA
FBMA-L11-160808-800LMT_0603 +5VALW
1 1
2 2 2 2
IHDMI@ 4.75V
D CA7 CA8 D
10U_0805_10V4Z 0.1U_0402_16V4Z 2 UA1
2 2 CA9 2
0.1U_0402_16V4Z
25
38
1 VIN VOUT 5
9
U49 1U_0402_6.3V4Z CA10
1 1U_0402_6.3V4Z
2
AVDD1
AVDD2
DVDD_IO
DVDD
GND CA11 1 @
17,25,32,35,40 SUSP# 1 2 3 SHDN# BP 4 2 1
RA4 0_0402_5%
14 35 0.22U_0402_10V4Z
LINE2-L LOUT1_L AMP_SPK_L 30
15 36 APL5151-475BC-TRL_SOT23-5
LINE2-R LOUT1_R AMP_SPK_R 30
1 2 MONO_IN 12 37
CA14 100P_0402_50V8J BEEP_IN MONO_OUT
Beep sound
C 6 46 C
21 AZ_BITCLK_HD BITCLK DMIC_CLK1/2
5 44
21 AZ_SDOUT_HD SDATA_OUT DMIC_CLK3/4 EC Beep RA8
21 AZ_SDIN0_HD 2 1 AZ_SDIN0_HD_R 8 SDATA_IN LINE2_VREFO 20 32 BEEP# 1 2
33_0402_5% RA7 47K_0402_5%
21 AZ_RST_HD# 11 RESET# LINE1_VREFO 18
10 28 10mil
21 AZ_SYNC_HD SYNC MIC1_VREFO
10mil
+MIC1_VREFO
PCI Beep RA9
CA15
19 +MIC2_VREFO 1 2 1 2 MONO_IN
MIC2_VREFO 22 SB_SPKR
22 SPK_SEL 2 GPIO0/DMIC_DATA1/2 47K_0402_5%
31 1 2 0.1U_0402_16V4Z
CPVEE CA16 2.2U_0603_6.3V6K
3 GPIO1/DMIC_DATA3/4
27 AC_VREF CA18 CA19
VREF
10U_0805_10V4Z
SENSE_A
0.1U_0402_16V4Z
13 SENSE A
40 AC_JDREF 1 RA10 2 1 1
SENSE_B JDREF 20K_0402_1%
34 SENSE B
1
CBN 30 1 2 1
EAPD 47 CA17 2.2U_0603_6.3V6K
32 EAPD EAPD 2 2
29 RA11 CA20
CBP 10K_0402_5%
43 NC 0.1U_0402_16V4Z
2
2
4 DVSS AVSS1 26
7 DVSS AVSS2 42
ALC272-GR_LQFP48_7X7 1 2
need to re-link ALC272
<BOM Structure> RA12 0_0603_5%
B DGND AGND 1 2
B
RA13 0_0603_5%
1 2
GPIO0-->SPK_SEL HIGH:HARMAN RA14 @ 0_0603_5%
LOW:NO-BRAND 1 2
RA15 0_0603_5%
CA23
10U_0805_10V4Z
CA24 CA25 Int. Mic
2 2 2
2 MIC@ 1 +MIC2_VREFO
4.7K_0402_5% RA24
0.1U_0402_16V4Z 10 dB MIC@ RA25 MIC@
CA26 1K_0402_5% JMIC
1U_0402_6.3V4Z 2 1 2 1 INT_MIC 1 3
+5VS 29 MIC2_L 1 NC1
1 2 2 2 NC2 4
1
1U_0402_6.3V4Z CA27
16
15
29 MIC2_R 2 1 2 1
6
UA3 RA28 RA27 1K_0402_5% 220P_0402_50V7K ACES_85204-0200N
100K_0402_5% 100K_0402_5% CA28 RA26 MIC@ @
Rin =70Kohm
VDD
PVDD1
PVDD2
MIC@
3
@ MIC@
PSOT24C_SOT23
2
2
@
7 RIN+ GAIN0 2
CA29 0.033U_0402_25V7K
3
1
GAIN1 DA3
1
29 AMP_SPK_R LINE_C_OUTR 17
CA30 0.033U_0402_25V7K RIN- SPKR+ RA30 RA29
ROUT+ 18
100K_0402_5% 100K_0402_5%
@
14 SPKR- Left Connector DA4 PJDLC05_SOT23-3
2
ROUT-
9 LIN+ 2
CA31 0.033U_0402_25V7K 1
4 SPKL+ 3
LOUT+ JSPKL
29 AMP_SPK_L LINE_C_OUTL 5 SPKL+ LA3 1 2 FBMA-L11-160808-800LMT_0603 SPK_L1 1 3
CA32 0.033U_0402_25V7K LIN- SPKL- SPKL- LA4 1 1 NC1
LOUT- 8 GAIN0 GAIN1 Av(db)Rin(ohm) 2 FBMA-L11-160808-800LMT_0603 SPK_L2 2 2 NC2 4
0 0 6 90K ACES_85204-0200N
setting 68Hz @
0_0603_5% SINGA_2SJ-A373-H01
RA32 CA34 @
100K_0402_5% 100P_0402_50V8J
1
CA35 0.1U_0402_16V4Z 2
RA33 RA34 +3VS 1 2
2
5
Ext.MIC/LINE IN JACK
2
CA36 JEXMIC
P
NC
2 1 2 2 4 0.1U_0402_16V4Z AGND 5
A RA35 10K_0402_5% A Y 2
G
74LVC1G14GW_SOT353-5 UA5 4
29 MIC_SENSE
1 UA4 1 14
3
7 08 CA39 FOX_JA6333L-B3T0-7F
CA37 CA38 GND Q2# @
3 1 1
SW_XRE094_3P 0.01U_0402_16V7K 0.01U_0402_16V7K 74LCX74MTC_TSSOP14 1
4
2 2 2 CA40 CA41
2
120P_0402_50V8K 120P_0402_50V8K
2 2
0.1U_0402_16V4Z PJDLC05_SOT23-3
ENCODER_DIR 32
ENCODER_PULSE 32
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 30 of 43
A B C D E
+1.8VS_OUT
40mil +3VALW
0.1U_0402_16V4Z 1000P_0402_50V7K
1 1 1 1 D3E mode
1
Power Circuit CC1 CC2 CC3 CC4 R129
10K_0402_5%
UC1 2 2 2 2 @
10U_0805_10V4Z 0.1U_0402_16V4Z
2
3 5 +3VS
16 CLK_5IN1# APCLKN APVDD 21 CR_CPPE#
16 CLK_5IN1 4 APCLKP APV18 10
1 1 2 1
1
CC5 0.1U_0402_16V4Z D
20 PCIE_ITX_C_5IN1RX_N6 9 APRXN
8 19 1 2 2 CPPE
20 PCIE_ITX_C_5IN1RX_P6 APRXP DV33 CC6 0.1U_0402_16V4Z G
DV33 20
20 PCIE_IRX_C_5IN1TX_N6 CC7 1 2 0.1U_0402_16V7K PCIE_IRX_5IN1TX_N6 11 44 +1.8VS_OUT S Q54
3
CC8 0.1U_0402_16V7K PCIE_IRX_5IN1TX_P6 APTXN DV33 2N7002_SOT23-3
20 PCIE_IRX_C_5IN1TX_P6 1 2 12 APTXP DV18 18
37 1 1 @
DV18
2 1 7 APREXT
CC11 22P_0402_50V8J 8.2K_0402_5% RC1 48 XD_SD_MS_D0 CC9 CC10
7mil XIN MDIO0 XD_SD_MS_D1 0.1U_0402_16V4Z
2 1 MDIO1 47
XIN XD_SD_MS_D2 2 2 +VCC_OUT
38 TXIN MDIO2 46 21 CR_WAKE# 1 2 XDCD0#_SDCD#
XOUT 39 45 XD_SD_MS_D3 0.1U_0402_16V4Z D81
TXOUT JMB380 MDIO3
1
RC10 200K_0402_5%
RC11 49
120_0402_5% GND
JMB380-QGAZ0A_QFN48_7X7 MDIO14 CR_LED CR_LED
XD_ALE 1 2 high active★ low active
2 2
RC12 10K_0402_5%
@ 2
Close to Chip
1
RC17
4.7K_0402_5% reserve for EMI
1
3 3
1
Card Reader Connector CC16 RC19 RC20 RC21
+VCC_OUT 56_0402_5% 56_0402_5%
20 mils JREAD 2 1394 Port
3 21 +VCC_OUT
2
XD-VCC SD-VCC J1394
MS-VCC 28
1 1 XD_SD_MS_D0 32 220P_0402_50V8K 4.99K_0402_1% TPB- 1 5
XD_SD_MS_D1 XD-D0 SDCLK TPB+ TPB- GND
10 XD-D1 SD_CLK 20 2 TPB+ GND 6
CC17 CC18 XD_SD_MS_D2 9 14 XD_SD_MS_D0 TPA- 3 7
10U_0805_10V4Z 0.1U_0402_16V4Z XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1 TPA+ TPA- GND
2 2
8 XD-D3 7 IN 1 CONN SD-DAT1 12 4 TPA+ GND 8
XD_SD_D4 7 30 XD_SD_MS_D2
XD-D4 SD-DAT2
3
XD_SD_D5 6 29 XD_SD_MS_D3 P-TWO_CU8047-A0G15
XD-D5 SD-DAT3
1
XD_SD_D6 5 27 XD_SD_D4 RC22 @
XD_SD_D7 XD-D6 SD-DAT4 XD_SD_D5 TPBIAS 56_0402_5% RC23 IOGND
4 XD-D7 SD-DAT5 23
CC19@ 18 XD_SD_D6 56_0402_5%
@ XDCE# SDCMD_MSBS_XDWE# 34 SD-DAT6 XD_SD_D7 D77 D78
2 1 2 1 XD-WE SD-DAT7 16 1
RC24 100_0402_5% XDWP#_SDWP# 33 1 XDCD0#_SDCD# PJDLC05_SOT23-3 PJDLC05_SOT23-3
2
100P_0402_50V8J XD_ALE XD-WP SD-CD XDWP#_SDWP# CC20
35 XD-ALE SD-WP 2
XD_CD# 40 25 SDCMD_MSBS_XDWE# 0.33U_0603_10V7K
XD_RB# XD-CD SD-CMD 2
39
1
XD_RE# XD-R/B MSCLK
38 XD-RE MS-SCLK 26 reserve for EMI
XDCE# 37 17 XD_SD_MS_D0
DC2 XD_CLE XD-CE MS-DATA0 XD_SD_MS_D1
36 XD-CLE MS-DATA1 15
XDCD1#_MSCD# 2 19 XD_SD_MS_D2 please place to BTM side
XD_CD# MS-DATA2 XD_SD_MS_D3 and close to 1394 port
1 31 7IN1-GND MS-DATA3 24
XDCD0#_SDCD# 3 1 11 22 XDCD1#_MSCD# 1 R132 2
7IN1-GND MS-INS SDCMD_MSBS_XDWE# 0_0805_5%
4 41 7IN1-GND MS-BS 13 4
DAN202UT106_SC70-3 CC21 42
270P_0402_50V7K 7IN1-GND GND IOGND
2
TAITW_R015-D10-LM_NR
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
SCHEMATIC MB A4571
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 31 of 43
A B C D E
5 4 3 2 1
+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 C771 1 1 2 2 C769 L25
C770 1 2 ECAGND 2 1
C772 C773 C774 C775 0_0603_5%
1000P_0402_50V7K1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2 2 1 1
111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z
22
33
96
67
9
U43
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
D D
CLK_PCI_EC 1 21
21 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 17
21 EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 29
1
22 PM_SLP_S5# B FANFB2/GPIO15
4 SLP_S5# 30 1 2
Y 33 E51_TXD EC_TX/GPIO16 UMA_ENBKL 10
1 31 110 R745GM@ 0_0402_5%
22 PM_SLP_S4# A 27 UWB_OFF# EC_RX/GPIO17 PM_SLP_S4#/GPXID1 ENCODER_DIR 30
G
PWR_LED#/GPIO19 GPXID3
33 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# 22 1 2
116 R747 100K_0402_5%
GPXID5 SUSP# 17,25,29,35,40
GPXID6 117 PBTN_OUT# 22
2 R772 1 0_0402_5% NEW_BOARD
GPXID7 118 LOM_WAKE# 28
CRY1 122
CRY2 XCLK1 +EC_V18R
123 XCLK0 V18R 124
2 R743 1 SYNCS@ 0_0402_5% EC_SMB_CK1
34 EC_SMB_ESB_CK
CIR
AGND
34 EC_SMB_ESB_DA
2 R759 1 ENECS@ 0_0402_5% ESB_CK CRY1 1 2CRY2 C782
2 R760 1 ENECS@ 0_0402_5% ESB_DA 4.7U_0805_10V4Z
@ 20M_0603_5% KB926QFA1_LQFP128_14X14 1 U45
11
24
35
94
113
69
R750 100_0805_5%
15P_0402_50V8J
15P_0402_50V8J
Y5 CIR_IN 4
OUT
IN
2 2 ROUT
TSOP6238-TR_4P
A A
CIR@
NC
NC
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 32 of 43
5 4 3 2 1
SPI Flash (16Mb*1) +3VL
M25P80-VMW6TP_SO8-->16Mb ROM
WIESO_G6179-100000_8P-->BIOS Conn. Please place the connector under DDR door
1 20mils
C786 U46
8 VCC VSS 4
0.1U_0402_16V4Z
2
3 W For EC JP34
1
1 +5VL
7 HOLD 2 2
3 E51_TXD
SPI_CS# 3
1 2 INT_SPI_CS# 1 S 4 4
R751 0_0402_5%
EC_SPICLK 6 @ ACES_85205-0400
32 EC_SPICLK C
32 EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO 32
SST25LF080A_SO8-200mil
EC_SPICLK 1 2 1 2
External Flash ROM R752 C787
@ 10_0402_5% @ 4.7P_0402_50V8C If these TEST@ components are mounded, please delete R751
JP35 SB_INT_FLASH_SEL H L L SB_INT_FLASH_SEL H L L
+3VL @
SPI_CS# 1 2 +3VL C788 0.1U_0402_16V4Z
32 SPI_CS# 1 2
EC_SI_SPI_SO 3 4 INT_FLASH_EN# 2 1 SPI# L L H INT_FLASH_EN# L H H
3 4 EC_SPICLK @
22 SB_INT_FLASH_SEL# 5 5 6 6
5
7 8 EC_SO_SPI_SI U47 R753 100K_0402_5%
7 8 R754 INT_FLASH_EN# 1
2 2 EXT_CS# H L H SPI# L L H
G Vcc
E&T_2941-G08N-00E~D INT_SPI_CS# B
1 2 4 Y
@ 22_0402_5% 1 SPI_CS# External
@ A
Flash ROM STOP RUN STOP INT_SPI_CS# L H H
NC7SZ32P5X_NL_SC70-5
3
@ External
Flash ROM RUN STOP STOP
6
5
C793 C792 100P_0402_50V8J
180P_0402_50V8J C794 KSO3 1 2
3
2
2 180P_0402_50V8J C795 100P_0402_50V8J
D65 2 D66 JKB KSO5 1 2
PJDLC05_SOT23-3 PJDLC05_SOT23-3 1 2 +3VS C796 100P_0402_50V8J
34 R755 300_0402_5% KSO14
33 1 2
C797 100P_0402_50V8J
32 KSO6
31 1 2
C798 100P_0402_50V8J
30 KSO7
need to relink the footprint 29 1 2 +3VS 1 2
KSO2 R756 300_0402_5% C799 100P_0402_50V8J
1
1
28 KSO1 KSO13
27 1 2
KSO0 C800 100P_0402_50V8J
26 KSO4 KSO8
25 1 2
KSO3 C801 100P_0402_50V8J
24 KSO5 KSO9
23 1 2
KSO14 C802 100P_0402_50V8J
22 KSO6 KSO10
21 1 2
KSO7 C803 100P_0402_50V8J
20 KSO13 KSO11 1 2
LPC Debug Port 19
18
KSO8
KSO9 KSO12
C804
1
100P_0402_50V8J
2
17 KSO10 C805 100P_0402_50V8J
Please place the PAD under DDR DIMM.
Lid SW 16
15
14
KSO11
KSO12
KSO15 1
C807
2
100P_0402_50V8J
H1 +3VALW KSO15 KSI7 1 2
+3VALW +3VALW 13 KSI7 C808 100P_0402_50V8J
12 KSI2 KSI2
11 1 2
1
6 5 1 2 E51_TXD KSI3 C810 100P_0402_50V8J
E51_TXD 32 10
R758 @ 0_0402_5% U48 R766 KSI4 KSI3 1 2
APX9132ATI-TRL_SOT23-3 9 KSI0 C811 100P_0402_50V8J
47K_0402_5% 8
SERIRQ 1 2 7 4 PLT_RST# KSI5 KSI4 1 2
22,32 SERIRQ PLT_RST# 8,17,20,25,27,28,31,32 7
R761 0_0402_5% KSI6 C812 100P_0402_50V8J
2
6 KSI1 KSI0
2 3 1 2
GND
CURS_LED# 1 2
@ DEBUG_PAD R764 C818 100P_0402_50V8J
22_0402_5% NUM_LED# 1 2
C819 100P_0402_50V8J
1
2
C820
1
22P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
SCHEMATIC MB A4571
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 33 of 43
5 4 3 2 1
C821
1
2
32
32
33
33
TP_CLK
TP_DATA
TP_SWL
TP_SWR
+5VS_TOUCH 1
2
3
4
5
1
2
3
4
ISPD PCB
PCB ZKU LA-4571P REV4
LAN
8102E
1 1U_0402_6.3V4Z 5 8102E@
2 2 6 6
+3VL ON/OFFBTN# 1
5 GND 3 3 7 GND
6 4 2 8 U3 U3 PJP1
GND 4 GND
1
1
2
ACES_85201-04051 3 ACES_85201-06051
R765 @ R105
D D80 0_0603_5%
NB_GL_R1 NB_PM DC-IN D
100K_0402_5% PJDLC05_SOT23-3
2
SW5 @ CANTIGA GL40 A1 CANTIGA PM PJP1
51_ON# 36
1
1 3 ON/OFFBTN# GMLR1@ PMR3@ 45@
ON/OFFBTN# 32
TOP side
2 4 U9 U3 U3
LED/B Connector
6
SMT1-05-A_4P Q28A
6
5
2N7002DW-T/R7_SOT363-6 JLED
2 another at page35 2 4
NB_GL_R1 NB_PM_R1 NB_GL
32 EC_ON +5VS 2 NC2
SW6 @ LEDB_LED# 1 3
1 NC1
2
1 3 ICH9-M ES CANTIGA PM CANTIGA GL40 A1
1
R767 ACES_85204-0200N ICH9R1@ PMR1@ GMLR3@
BTM side 2 4 10K_0402_5% @
U3 UL3
1
SMT1-05-A_4P D
6
5
1
VR_LED Q51
2
G
Trans
debug phase using S
2N7002_SOT23-3 NB_GM_R1 former
3
CANTIGA GM45 10/100M transformer
GMR1@ 8102E@
FUN/B Connector
DC-IN LED
ACIN 22,32,36
Vf=2.8V(typ),3.15V(max) +5VL_CS 2
C D67 QC1B R518 1 SYNCS@2 0_0402_5% 2 H2 H3 H4 H6 H7 H8 H9 H10 C
32 CAP_INT# 3 3
+5VALW 1 2 2 1 3 4 4 4
R768 120_0402_5% 5
32 EC_SMB_ESB_DA 5
HT-F196BP5_WHITE 2N7002DW-T/R7_SOT363-6 6 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
32 EC_SMB_ESB_CK
1
6 @ @ @ @ @ @ @ @
another at page31 1 1 1 7 GND
C854 10P_0402_50V8J
C853 10P_0402_50V8J
C852 10P_0402_50V8J
2 8 GND
1
1
BATT CHARGE/FULL
D70
LED 3
2 2 2 R104 @
ACES_85201-06051 H12 H13 H14 H15 H11
1
D72 +3VL R133 2 1 0_0603_5% @ @ @ @ @
1 2 2 1 ENECS@
BATT_FULL_LED# 32
R775 120_0402_5% +5VL R103 2 1 0_0603_5% +5VL_CS
HT-F196BP5_WHITE SYNCS@
H16 H36 H38
1
D74 @ @ @
+5VS 1
R777
2
300_0402_5%
2 1 WL_BT_LED# 32
SUSPEND LED
WLAN@ HT-110UD_1204 +3VALW
WLAN@ MINI CARD-1 H32 H34 CPU H20 H22 H19 H21
3
47K
Q29 H_3P8 H_3P8 H_3P7 H_3P8 H_3P8X4P8 H_3P8X4P8
WiMAX LED
1
WIMAX_LED_GND1 R506 2 @ @ @ @ @ @
LED_WIMAX# 27
0_0402_5% 10K 2 PWR_SUSP_LED 32
2
B @ B
1
D75 2N7002DW-T/R7_SOT363-6 1 2 2 1 @ @ @ @ @
+5VS 1 2 2 1WIMAX_LED_GND3 4 R770 120_0402_5% HT-191UD_AMBER_0603
R778 300_0402_5%
WIMAX@ HT-110NB5 1204 BLUE Q52B 2N7002DW-T/R7_SOT363-6 MINI CARD-3 H29 H24 MDC H27 H33
WIMAX@
SATA_LED# 21
POWER LED H_3P8 H_3P8 H_1P2 H_1P2
1
@ @ @ @
2
+5VALW
HDD LED
+5VS 2 R779 1 6 1
3
10K_0402_5% 47K
5
Q31A Q42
D76 2N7002DW-T/R7_SOT363-6
+5VS 1 2 2 1 3 4 10K 2 PWR_ON_LED 32
R780 120_0402_5%
HT-F196BP5_WHITE Q31B 2N7002DW-T/R7_SOT363-6
Logo LED D5
DTA114YKAT146_SOT23-3
PCB Fedical Mark PAD
1
HT-SV116BP_WHITE D68
1 2 1 2 2 1 FD1 FD2 FD3 FD4
VR_LED 32
R769 120_0402_5%
2
HT-F196BP5_WHITE @ @ @ @
A A
D71 @ 1 2 POWER_ON_LED
1
+5VS 1 R514 2 1 2 2 1 1 R516 2LOGO_LED# 6 1 R771 120_0402_5%
0_0402_5% R774 120_0402_5% 0_0402_5%
@ HT-110TW_WHITE @ Q30A
D73 @ 2N7002DW-T/R7_SOT363-6
LOGO_LED# 1 R515 2 1 2 2 1 1 R517 2 another at page39
0_0402_5% R776 120_0402_5%
HT-110TW_WHITE
0_0402_5%
+5VS Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/19 Deciphered Date 2009/09/19 Title
1 2
SCHEMATIC MB A4571
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
D6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
HT-SV116BP_WHITE E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 34 of 43
5 4 3 2 1
A B C D E
470_0805_5%
470_0805_5%
8 1 8 1 Q34 C828 C829
D S D S
470_0805_5%
7 2 7 2 8 1 PM@ PM@
D S D S D S
2
2 2 R781 2 2 R782
6 D S 3 6 D S 3 7 D S 2
2 2 R783
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4 PM@
SI4800BDY_SO8 D G
1 R784 2 +VSB SI4800BDY_SO8 1 R785 2 +VSB 1U_0402_6.3V4Z
3 1
3 1
0.022U_0402_25V7K
0.01U_0402_25V7K
47K_0402_5% 20K_0402_5% SI4856ADY_SO8 1 R786
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1 1 1 1 2 +VSB
3 1
1
6
C831 PM@ 47K_0402_5%
4.7U_0805_10V4Z
1 1
6
0.1U_0402_25V6
C830 R787 Q35A C832 C833 R788 Q36A FDS6676AS PM@
C835
330K_0402_5% Q35B 200K_0402_5% Q36B C834 R789 Q37A
2 2 SUSP 2 2 SUSP 5 PM@ 330K_0402_5% Q37B
2 5 2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 PM@ 2 PM@ SUSP 5 PM@
2
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6
4
PM@
+3VALW TO +3V_WLAN
+3VALW TO +3V_LAN
+3V_LAN +3V_WLAN
2
+5VALW
2
+5VALW
R791 R790 +3VALW
2
470_0805_5% +3VALW 470_0805_5%
2
STAR@ STAR@
6 1
R793 Vgs=-4.5V,Id=3A,Rds<97mohm R792
6 1
2
2N7002DW-T/R7_SOT363-6 STAR@ Q41 Q38A STAR@ AO3413_SOT23
1
2
3
S
2 STAR@ AO3413_SOT23 2N7002DW-T/R7_SOT363-6 STAR@ PJ34 2
2
1
3
S
STAR@ PJ35 STAR@ 2 STB_WLAN# 1 2
G
2 +3V_WLAN
JUMP_43X79
2
G
2 WOL_EN# 1 2 2 JUMP_43X79 R794 4.7K_0402_5% @
1
R795 4.7K_0402_5% @ STAR@ 2
D
1
2
+3V_LAN
1
STAR@ 2
D C836
1
1
2
3
0_0402_5% STAR@ @ 1 +5VALW
1 1
3
1
4.7U_0805_10V4Z C839
1
2
reserve for test C840 C841 1U_0402_6.3V4Z 5 Q38B @ 1U_0402_6.3V4Z
32 STB_WLAN 2 2 STAR@
5 Q39B 4.7U_0805_10V4Z STAR@ 2N7002DW-T/R7_SOT363-6 R796
32 WOL_EN
2N7002DW-T/R7_SOT363-6 @ 2 2 STAR@ 10K_0402_5%
4
1
STAR@
4
1
R797
1
R798 STAR@ SUSP
41 SUSP
100K_0402_5% 100K_0402_5%
3
STAR@
2
Q28B
2
2N7002DW-T/R7_SOT363-6
17,25,29,32,40 SUSP# 5 another at page34
4
R799
+3VALW TO +3V_SB 10K_0402_5%
+5VALW
1
+3VALW +3V_SB
2
3 PJ36 3
2 1 R800
2 1 100K_0402_5%
Q44 @ JUMP_43X79 STAR@
Vgs=10V,Id=6A,Rds=35mohm +1.5VS +0.9VS
1
D
6 SBPWR_EN#
S
23 SBPWR_EN#
1 5 4 1U_0402_6.3V4Z
2
C842 2 1 1
2
1
SI3456BDV-T1-E3_TSOP6 2 2 STAR@ reserve for test D
1
+VSB 2 1 2 Q45
32 SBPWR_EN
6 1
3
STAR@ 1 S STAR@ Q30B
3
1
R805 C845 Q46A Q21B 2N7002DW-T/R7_SOT363-6
Q46B 200K_0402_5% 0.1U_0402_25V6 STAR@ R806 2N7002DW-T/R7_SOT363-6
SBPWR_EN# 5 STAR@ STAR@ STAR@ 2 SBPWR_EN# 100K_0402_5% another at page25 5 SUSP 5 SUSP
2 STAR@ another at page34
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
4
4
4 4
PR1
VIN 1M_0402_1%
PL1 1 2
PF1 SMB3025500YA_2P VIN
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2 VS
1
PJP1
1 10A_125V_451010MRL PR3
+ 84.5K_0402_1%
1
1 1
2 PR5
+
8
PC1 PC2 PC3 PC4 PU1A 22K_0402_1%
2
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J PR4 PR2
+ 3 1 2
P
2
2
-
1 2 1 0
22,32,34 ACIN
20K_0402_1%
4 0_0402_1% 2
- -
1
G
10K_0402_1%
PR6
0.1U_0603_25V7K
@ SINGA_2DW-0005-B03 LM358DT_SO8 PC6
4
PR7 PD2 1000P_0402_50V7K
2
PC5
10K_0402_1% GLZ4.3B_LL34-2
2
2
2
VIN 1 2
RTCVREF
PR8
2
10K_0402_1%
PD3
RLS4148_LL34-2
1
BATT+ 2 1
1
PD4 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3 Vin Detector
PR11
2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS High 18.384 17.901 17.430 2
1
PC8
PR12 PC7 0.1U_0603_25V7K
100K_0402_1% 0.22U_1206_25V7K
RTC Battery
2
2
2
2
34 51_ON# 1 2
PR13
22K_0402_1%
- PBJ1 +
2 1 +RTCBATT +RTCBATT
RTCVREF
1
PR14
200_0603_5% @ MAXEL_ML1220T10
PR15 PR16 PU2 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2
1 2 1 2 3 2 N2
+CHGRTC OUT IN
SP093MX0000
1
GND
PC9 PC10
10U_0805_10V4Z 1
2
1U_0805_25V4Z
3 3
PJ3
PJ1 PJ2
+3VALWP 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V VL 2 2 1 1 +5VL
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) PJ4 (100mA,40mils ,Via NO.= 2)
2 2 1 1
PJ5
+5VALWP 2 1 +5VALW @ JUMP_43X118
2 1
(12A,480mils ,Via NO.= 24) PJ6
@ JUMP_43X118
(5A,200mils ,Via NO.= 10) +3VLP 2 2 1 1 +3VL
PJ8
2 1 @ JUMP_43X39
PJ7 2 1
(100mA,40mils ,Via NO.= 2)
+VSBP 2 1 +VSB @ JUMP_43X118
2 1
@ JUMP_43X39 PJ9
+1.05VSP 2 2 1 1 +1.05VS
(120mA,40mils ,Via NO.= 1)
@ JUMP_43X118
(10A,400mils ,Via NO.=20)
PJ10
+0.9VSP 2 1 +0.9VS PJ11
2 1 +1.5VSP +1.5VS
2 2 1 1
@ JUMP_43X79
(2A,80mils ,Via NO.= 4) @ JUMP_43X79
4
(2.0A,80mils ,Via NO.=4) 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 36 of 43
A B C D
A B C D
2
3 3 1 2 1 2 +3VLP
4 PR17 PR18 PR19
4
1
1K_0402_1% 47K_0402_1% 47K_0402_1% D
5 5
10 6 EC_SMDA PC11 PC12 PH1 PC13 2 PQ2
GND 6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR21 G SSM3K7002FU_SC70-3
11 7
1
GND 7 47K_0402_1%
12 8 S
3
GND 8
1
13 9 1 2
2
GND 9 PR20 PR22
8
@ OCTEK_BTJ-09HA1G 1K_0402_1% 13.7K_0402_1% PU3A
1 2 3
P
+
1 2 1
2
O
2
G
PR23 PR24 PD5
100_0402_1% 100_0402_1% LM393DG_SO8 RLS4148_LL34-2
4
0.22U_0805_16V7K
1
1
D
15.4K_0402_1%
1
1
PC14
PR25 2 PQ3
1000P_0402_50V7K
PR26
6.49K_0402_1% G SSM3K7002FU_SC70-3
2 1 +3VLP 2 1 VL S
3
1
PC15
PR27
2
100K_0402_1%
2
1
1
PR28
2
1K_0402_1% 2
PR29
100K_0402_1%
2
2
BATT_TEMPA 32
EC_SMB_DA1 19,32
EC_SMB_CK1 19,32
PH2 near main Battery CONN :
BAT. thermal protection at 90 degree C
Recovery at 53 degree C
VL VL
PQ4
2
TP0610K-T1-E3_SOT23-3
1
PR30
47K_0402_1%
B+ 3 1 +VSBP PH2 PR31
100K_0603_1%_TH11-4H104FT 47K_0402_1%
1
3 3
100K_0402_1%
0.22U_1206_25V7K
0.1U_0603_25V7K
1 2
2
1
1
PR32
PC16
PC17
PR33
8
13.7K_0402_1% PU3B
1 2 5
P
2
+
7 2 1
2
TM_REF1 O
6 -
G
VL PR34 PD6
1
22K_0402_1% @ @ LM393DG_SO8 RLS4148_LL34-2
4
1 2 PC18 PR35
2
0.22U_0805_16V7K 16.9K_0402_1%
2
PR36
2
100K_0402_1%
PR37
1
0_0402_5% D
1 2 2 PQ5
39 POK
G SSM3K7002FU_SC70-3
0.1U_0402_16V7K
S
3
1
PC19
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 37 of 43
A B C D
A B C D
PQ8
B+ AO4407_SO8
VIN PQ6 PQ7
1 8
AO4407_SO8 AO4407_SO8 PR38 0.01_2512_1% 2 7
8 1 1 8 1 4 3 6
7 2 2 7 5
0.01U_0402_25V7K
6 3 3 6 2 3
PR39 5 5
4
100K_0402_1%
3.3_1210_5% PJ14
1
2 1 CHG_B+
4
2 1
PC20
PR40
0.01U_0402_25V7K
2 1
PQ9
100K_0402_1%
0.01U_0603_50V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
@ JUMP_43X118
1
1
AO4407_SO8
2
PC22
PR42
PR41
CHGEN#
1 8
2
2
PC23
PC24
PC25
1
3.3_1210_5% 2 7 1
PC21
PC26 PC28 3 6
1
5
6
7
8
0.1U_0402_16V7K PU5 0.1U_0805_25V7K 5
1 1
2
1 2 1 CHGEN PVCC 28 1 2
PC29
4
1
1
2.2U_0805_25V6K PR44 /BATDRV
2 PC27 PC30 0_0603_5% PQ10
0.1U_0603_25V7K @0.1U_0603_25V7K 27 1 2 4 AO4466_SO8
2
BTST
2
PR43
340K_0402_1% 2 26
ACN HIDRV
3
3
2
1
ACP PR45
1
4 25 PL3 0.02_2512_1%
ACDET ACDRV PH PD7 10UH_SIL1045RA-100PF_4.5A_30%
5 ACDET
2 1 1 2 1 2 1 4
10U_1206_25V6M
10U_1206_25V6M
RLS4148_LL34-2 PC31 BATT+
REGN
2 3
2
1
PR46 0.1U_0603_25V7K
5
6
7
8
1
PC32
PC33
PR47 71.5K_0402_1%
54.9K_0402_1% 1 2 ACSET 6
VREF
2
ACSET PC36
24
2
REGN
1
0.1U_0402_16V7K
1
1
PR48 PC35 PQ11 1 2
PC34 100K_0402_1% 1U_0603_10V6K 4 AO4466_SO8
@ 0.01U_0402_25V7K
2
2
1
2
1 2 7 ACOP PC38 PC39
PR49 PC37 23 0.1U_0603_25V7K @0.1U_0603_25V7K
3
2
1
2
340K_0402_1% 0.47U_0603_16V7K LODRV
1
PGND 22
2
OVPSET 8 2
OVPSET
PR50
54.9K_0402_1%
VREF 20 CELLS
CELLS
1
10 VREF
PQ12
3
1
SI2301BDS-T1-E3_SOT23-3 PC40
1U_0603_10V6K
PR51 19
2
100K_0402_1% SRP
RTCVREF
1 2 2 11 VDAC SRN 18
BAT 17
1
VREF
1
PC41 VADJ 12
VREF 0.1U_0603_25V7K PR52 VADJ PC42
2
1
1
2
PR53 29
1
200K_0402_1% ACGOOD# TP
13 ACGOOD
1
D
PR55
2
1
S
2
3
1
1
D
PR57
ACOFF 1 2 2 PQ14 15 1 2 100K_0402_1% PC44
G SSM3K7002FU_SC70-3 IADAPT @0.01U_0402_25V7K
2
1
3 3
2
0.1U_0402_16V7K PR58 10_0603_5%
340K_0402_1% REGN
1
PC45
2
100P_0402_50V8J
2
1
1.484V 1.5A
PR61 3.28V 4.35V
499K_0402_1%
VMB
VREF
0V 4V
2
499K_0402_1% 340K_0402_1%
1
VS
2
PR62
CHGVADJ要接到EC DA pin
PR63
0.01U_0402_25V7K
100K_0402_1%
2
1
1
PC46
CHGEN#
PR64
2
1
D
PQ15
LI-3S :13.5V----BATT-OVP=1.5V 32 FSTCHG 2
G SSM3K7002FU_SC70-3
2
8
4
PR65 PU1B 4
BATT-OVP=0.111*BATT+ S
3
10K_0402_1%
+ 5
P
32 BATT_OVP 1 2 7 0
- 6
G
105K_0402_1%
1
0.01U_0402_25V7K
LM358DT_SO8
4
1
PR66
PC47
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 38 of 43
A B C D
5 4 3 2 1
2VREF_51125
0.22U_0603_10V7K
D D
1
PC48
2
PR67 PR68
13K_0402_1% 30K_0402_1%
1 2 1 2
PR69 PR70
B++
20K_0402_1% 20K_0402_1%
B++
1 2 1 2
PJ15
B+ 2 2 1 1 +3VLP
ENTRIP2
ENTRIP1
2200P_0402_50V7K
10U_1206_25V6M
150K_0402_1% 150K_0402_1%
1
2200P_0402_50V7K
PC49
0.1U_0402_16V7K
1 2 1 2
1
PC50
PC52
PC51
4.7U_0805_10V6K
2
2
6
5
6
7
8
PC134
PU6
8
7
6
5
1
PC53
C C
VREF
ENTRIP2
VFB2
VFB1
ENTRIP1
TONSEL
PQ16 25 PQ17
P PAD
1
AO4466_SO8
2
AO4466_SO8
7 24 POK 37 4
2
VO2 VO1
4
8 23 PR74 PC55
PR73 VREG3 PGOOD 0_0603_1% 0.1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
3
2
1
0_0603_1% VBST2 VBST1
1
2
3
8
7
6
5
5
6
7
8
1
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
DRVL2 DRVL1
PR75
PR76
SKIPSEL
220U_6.3V_M
0.1U_0402_16V7K
0.1U_0402_16V7K
PQ18 PQ19
VREG5
VCLK
1 AO4712_SO8 AO4712_SO8
GND
1
EN0
VIN
@ @
2
2
1
1
+ +
PC57
PC130
PC129
PC56 4 4
220U_D2_4VM PR77 TPS51125RGER_QFN24_4X4
13
14
15
16
17
18
1
1
680P_0603_50V8J
680P_0603_50V8J
499K_0402_1%
2
2
2 2
@ PC58
@ PC59
B+ 1 2
2
1
2
3
3
2
1
2
1
100K_0402_5%
PR78
1 2 VL
PC60
4.7U_0805_10V6K
PR79
2
B @ 0_0402_5% B
0.1U_0402_16V7K
2
ENTRIP1 21,37 ENTRIP2 21,37
B++
PC135
1
0.1U_0603_25V7K
2
2
PC61
1
D D
2VREF_51125
PQ20 2 2 PQ21
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3
VL 2 1
PR80
100K_0402_1%
1
VS 1 2 2 PQ22
G SSM3K7002FU_SC70-3
49.9K_0402_1%
0.01U_0402_16V7K
PR81 S
3
1
100K_0402_1%
1
PR82
@ PC62
A A
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 39 of 43
5 4 3 2 1
A B C D
1 1
+1.5VSP 1 2 1 2 2 1 2 1 +1.05VSP
51124_B+
2
PR87 51124_B+
2200P_0402_50V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
0_0402_5%
PJ16
1 1 2 2 B+
1
1
PC63
PC64
1
1
@ JUMP_43X118
PC65
2
4.7U_1206_25V6K
4.7U_1206_25V6K
2200P_0402_50V7K
8
7
6
5
5
6
7
8
1
PC66
PC67
PU7
1
VO2
VFB2
TONSEL
VFB1
VO1
GND
PC68
PQ23 25 PQ24
2
AO4466_SO8 P PAD AO4466_SO8
2
4 7 PGOOD2 PGOOD1 24 4
PC70
PC69 PR88 8 23 PR89
EN2 EN1 0.1U_0402_16V7K
0.1U_0402_16V7K 0_0603_1% 0_0603_1%
2
2 1 2 1 BST_1.5V 9 22 BST_1.05V 2 1 1 2 2
1
2
3
3
2
1
VBST2 VBST1
PL6 UG_1.5V 10 21 UG_1.05V PL7
+1.5VSP 1.8U_D104C-919AS-1R8N_9.5A_30% DR VH2 DR VH1 1.8U_D104C-919AS-1R8N_9.5A_30%
+1.5VSP 1 2 LX_1.5V 11 20 LX_1.05V 1 2 +1.05VSP
LL2 LL1 +1.05VSP
LG_1.5V 12 19 LG_1.05V
DR VL2 DR VL1
1
8
7
6
5
4.7_1206_5%
5
6
7
8
1
PR90
4.7_1206_5%
0.1U_0402_16V7K
0.1U_0402_16V7K
PQ25
PGND2
PGND1
1
V5FILT
TRIP2
TRIP1
PR91
220U_D2_4VM
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
AO4712_SO8 1
V5IN
D
D
D
D
1
+ PQ26
1
1
PC131
PC73
PC71
PC132
@ + PC74
2
PC72
4 TPS51124RGER_QFN24_4x4 FDS6670AS_NL_SO8 @ 220U_6.3V_M
2
13
14
15
16
17
18
2
2
4 G
2
2
1
2
680P_0603_50V8J
@ PC75
1
S
S
S
680P_0603_50V8J
2
1
2
3
@ PC76
PR93
3
2
1
13.7K_0402_1% PR92
2
1 2 13.7K_0402_1%
2
PR94 PR96
0_0402_5% 0_0402_5%
SUSP# 2 1 1 2 +5VALW 1 2
SUSP# 17,25,29,32,35
PR95
3.3_0402_5%
1
PC80
1
1
3
@ 0.1U_0402_16V7K PC77 PC78 PC79 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 40 of 43
A B C D
5 4 3 2 1
D D
PJ17
51117_B+ 2 1 B+
2 1
4.7U_1206_25V6K
4.7U_1206_25V6K
@ JUMP_43X118
1
PC81
PC82
5
6
7
8
2
PQ27
SI4686DY-T1-E3_SO8
PR97
255K_0402_1% 4
1 2
PR98 PR99
0_0402_5% 0_0603_1%
1 2 BST_1.8V 1 2
25,32 SYSON
3
2
1
1
PL8
15
14
PC84
1
PC83 PU8 1.0UH_PCMC104T-1R0MN_20A_20%
@0.1U_0402_16V7K BST_1.8V-1 1 2 1 2
EN_PSV
TP
VBST
+1.8VP
2
2 13 DH_1.8V 0.1U_0603_25V7K
TON DRVH
680P_0603_50V7K @ 4.7_1206_5%
0.1U_0402_16V7K
PR100 3 12 LX_1.8V
VOUT LL
5
6
7
8
PR102
422_0603_1% 1
+5VALW 1 2 4 11 1 2 +5VALW
V5FILT TRIP
PC133
PR101 PQ28 + PC85
2
5 10 10K_0402_1% SI4634DY-T1-E3_SO8 220U_D2_4VM
C VFB V5DRV C
2
1
1
DL_1.8V 2
6 PGOOD DRVL 9 4
PGND
PC87
PC86
GND
1U_0603_10V6K PC88
2
2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC89
7
3
2
1
4.7U_0805_10V6K
2
PR103 @
28.7K_0402_1%
1 2
1
PR104
20.5K_0402_1%
2
+1.8V
1
PJ18
1
@ JUMP_43X79
2
B PU9 B
2
1
PC90
1
4.7U_0805_6.3V6K 3 7 PC91
PR105 VREF NC 1U_0603_6.3V6M
2
2
1K_0402_1% 4 8
VOUT NC
9
2
TP
APL5331KAC-TRL_SO8
1
PR106 +0.9VSP
1
0_0402_5% D PR107
10U_0805_6.3V6M
1 2 2 1K_0402_1% PC92
35 SUSP
1
G 0.1U_0402_16V7K
2
1
PC94
0.1U_0402_16V7K
S PQ29
3
PC93 SSM3K7002FU_SC70-3
2
@ 0.1U_0402_16V7K
2
PC136
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 41 of 43
5 4 3 2 1
5 4 3 2 1
+5VS
2
6
6
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
PR108
+CPU_B+ PL9
32
VR_ON
1_0603_5%
HCB4532KF-800T90_1812
1 2 B+
1
D D
10U_1206_25V6M
10U_1206_25V6M
1 1
3300P_0402_50V7K
220U_25V_M
@ 220U_25V_M
680P_0603_50V8J
1
1
PC97
PC95
PC102
PC103
+ +
0.022U_0402_16V7K
PR110 0_0402_5%
1
PC101
PC98
PC99
2.2U_0603_6.3V6K
8,22 PM_DPRSLPVR 1 2 PC100
PC96
0.01U_0402_25V7K
2
PR109 0_0402_5% 2 2
2
PR113
PR114
PR120
PR115
PR116
PR117
PR118
PR112
5,8,21 H_DPRSTP# 1 2
5
PR111 0_0402_5% PQ30
CLK_ENABLE# 1 2 SI7686DP-T1-E3_SO8
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PR119 0_0402_5%
+3VS 1 2 4
+3VS
1U_0603_6.3V6M
PL10
2
2
1.91K_0402_1%
2.2_0603_1% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%
1
PC104
PR122 PC105
3
2
1
1
BOOT_CPU1 1 2 1 2 1 4 +CPU_CORE
2
PR121
PR123
3.65K_0805_1%
2 3
1
10K_0402_1%
499_0402_1% @PR124
@ PR124
49
48
47
46
45
44
43
42
41
40
39
38
37
5
6
7
8
5
6
7
8
PR125
PR127
4.7_1206_5% PR128
2
1_0402_5%
3V3
CLK_EN#
DPRSTP#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
GND
DPRSLPVR
VR_ON
D
D
D
D
D
D
D
D
1
1 2
1 36
2
8,22,32 VGATE PGOOD BOOT1 @PC106
@ PC106 PR129 @ 0_0603_5%
G
S
S
S
S
S
S
5 H_PSI# 2 35 UGATE_CPU1 680P_0603_50V8J VSUM 1 2
PSI# UGATE1 PQ31 PQ32 PC107
4
3
2
1
4
3
2
1
2
PGD_IN 1 2 3 34 PHASE_CPU1 SI4634DY-T1-E3_SO8 SI4634DY-T1-E3_SO8 1 2
PMON PHASE1
VCC_PRM
1 2PR130 @ 0_0402_5% 4 33 ISEN1
C PR126 147K_0402_1% RBIAS PGND1 0.22U_0603_10V7K C
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1
10U_1206_25V6M
10U_1206_25V6M
PR131 @ 4.22K_0402_1% PH3
1
1 2 1 2 6 NTC PVCC 31
PC108
PC109
PQ33
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7686DP-T1-E3_SO8
2
SOFT LGATE2
1 2
@ 0.015U_0402_16V7K PC110 8 29
0.022U_0603_25V7K PC111 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PL11
PR132 13K_0402_1% 10 27 UGATE_CPU2 0.36UH_PCMC104T-R36MN1R17_30A_20%
COMP UGATE2
1 2
3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR133
1 2
1
1000P_0402_50V7K PC113 2.2_0603_1% PC112
DROOP
12 FB2 NC 25 2 3
VDIFF
ISEN2
ISEN1
VSUM
VSEN
VDD
RTN
DFB
5
6
7
8
5
6
7
8
VIN
4.7_1206_5%
VO
1 2
D
D
D
D
D
D
D
D
3.65K_0805_1%
1 2 PU10
13
14
15
16
17
18
19
20
21
22
23
24
1 2
1
10K_0402_1%
PR136
1
PR138
PC114 1000P_0402_50V7K
G
S
S
S
S
S
S
ISEN1 @PC115
@PC115 PR142
ISEN2 680P_0603_50V8J 1_0402_5%
4
3
2
1
4
3
2
1
2
2
2
1
2
1
1K_0402_5% PC120
2
PC117 220P_0402_50V7K 1 2
B PR145 B
255_0402_1% PC119 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 +CPU_B+ 0.22U_0603_10V7K
VCC_PRM
1
PC122 0.018U_0603_50V7J
6 VCCSENSE 1 2 1 2
VSUM
1
PR147 0_0402_5%
1
2.61K_0402_1%
PC123 PC124
PR149
PR148 20_0402_5% 1 2
6 VSSSENSE PR150 0_0402_5%
2
1
11K_0402_1%
PC125 180P_0402_50V8J
PR152
PR151 1 2
2
20_0402_5% 1 2 1 2 PH4
10KB_0603_5%_ERTJ1VR103J
2
VCC_PRM 1 2
PC128 0.22U_0402_6.3V6K
PC127 2 1 2 1
0.22U_0603_10V7K
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4571
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401605
Date: Wednesday, September 16, 2009 Sheet 42 of 43
5 4 3 2 1
5 4 3 2 1
A A