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  • Compal - La-4772p - r1.0 - Schematics - Notebook Compal KHLB2 PDF

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    Rene
    106 views57 pages
    This document is a schematic for the KHLB2 mobile computer. It includes diagrams of the main components like the Intel Penryn CPU, ATI M96 graphics, DDR3 memory, thermal sensors, clock generator, USB and other ports. The document notes it contains confidential Compal Electronics information and property.

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    compal_la-4772p_r1.0_schematics__Notebook Compal KHLB2.pdf

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    This document is a schematic for the KHLB2 mobile computer. It includes diagrams of the main components like the Intel Penryn CPU, ATI M96 graphics, DDR3 memory, thermal sensors, clock generator, USB and other ports. The document notes it contains confidential Compal Electronics information and property.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    106 views57 pages

    Compal - La-4772p - r1.0 - Schematics - Notebook Compal KHLB2 PDF

    Uploaded by

    Rene
    This document is a schematic for the KHLB2 mobile computer. It includes diagrams of the main components like the Intel Penryn CPU, ATI M96 graphics, DDR3 memory, thermal sensors, clock generator, USB and other ports. The document notes it contains confidential Compal Electronics information and property.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 57

    A B C D E

    ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 ZZZ6 ZZZ7 ZZZ8 PJP1

    PCB LA-4772P LS-4773P LS-4774P LS-4775P LS-4777P LS-4778P LS-4779P 45@ DCIN
    ATIDAZ@ ATIDA@ ATIDA@ ATIDA@ ATIDA@ ATIDA@ ATIDA@ ATIDA@

    1 1

    Compal Confidential
    KHLB2 Schematics Document
    2 2

    Intel Mobile Penryn uFCPGA with Cantiga_PM + DDRIII + ICH9M

    2009-01-19
    3 3

    REV:1.0

    4 4

    Security Classification Compal Secret Data Compal Electronics,Ltd.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Cover Sheet
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLB2 MB Schematic
    Date: Monday, January 19, 2009 Sheet 1 of 56
    A B C D E
    A B C D E

    Compal Confidential
    Model Name : KHLB2
    Thermal Sensor Clock Gen.
    File Name : LA-4772P(ATI) Mobile Penryn SLG8SP556VTR
    EMC1402
    page 5 ICS9LPRS387BKLFT
    1
    uFCPGA-478 CPU page23 1

    page5,6,7

    H_A#(3..35) FSB
    H_D#(0..63) 667/800/1066MHz

    LVDS
    LCD Conn.
    page 25
    HDMI Intel Cantiga GMCH DDR3-SO-DIMM X2
    Dual Channel BANK 0, 1, 2, 3
    page 24 page 14,15
    CRT PCBGA 1329
    page 26 DDR3-800/1067(1.5V)
    page 8,9,10,11,12,13
    PCI-Express
    2 2
    VRAM 32M*32 USB conn x3 Bluetooth CMOS Camera Finger Print
    GDDR3*4 TO I/O/Bpage Conn page Conn page 45
    page 21 40 39 page 45
    DMI C-Line
    ATI M96 USB
    3.3V 48MHz
    page 16~20
    Intel ICH9-M
    PCI-Express
    3.3V 24.576MHz/48Mhz HD Audio
    mBGA-676
    S-ATA
    page27,28,29,30
    port 0 port 1
    GMCH HDA MDC 1.5 HDA Codec
    New Card MINI Card x2 Conn ALC268
    LAN(GbE) LPC BUS page 8 page 45 page 41
    Socket WLAN,
    RTL8111C/8102E Card Reader S-ATA HDD S-ATA ODD
    TV-Tuner Conn.page 31 Conn. page 31
    3
    page 36 JMB385 3

    page 35 page 33 page 32

    Audio AMP
    3 in 1 EC page 42

    RJ45 socket ENE KB926D3


    RTC CKT.
    page 34 page 32 page37
    page 28
    Function/B
    Power On/Off CKT. Power USB/B
    page 38
    page 40 Int.KBD
    page38
    Touch Pad
    page39
    USB I/O Conn.
    DC/DC Interface CKT. CIR BIOS
    page39
    page 46
    LID SW
    4 4

    Power Circuit DC/DC Debug port


    page 40
    page 46,47,48,50
    51,52,53
    TPM Security Classification Compal Secret Data Compal Electronics,Ltd.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title

    CHARGER LED MB Block Diagram


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    page 49 page 45 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 2 of 56
    A B C D E
    A B C D E

    DDR3 Voltage Rails


    1 1

    +5VS
    EC SM Bus1 address EC SM Bus2 address
    +3VS
    +1.5VS Device Address Device Address
    power
    +1.1VS Smart Battery 0001 011X b EMC 1402 100_1100X b
    plane
    +VCCP EEPROM(24C16/02) 1010 000X b ATI M96
    +5VALW +1.5V +CPU_CORE
    +B +1.8V +VGA_CORE
    +3VALW +0.75V +1.8VS

    State

    2 2

    S0
    O O O O GPIO PIN Define
    S1
    O O O O
    S3
    O O O X ID3 ID2 ID1 ID0
    JHT00(1100 ) X X R361 R357
    S5 S4/AC
    O O X X JHT01 (1101 ) X X R361 R355
    JHL90 (1110 ) X X R360 R357
    S5 S4/ Battery only
    O X X X JHL91 (1111 ) X X R360 R355
    KHLB0 (0000 ) R1052 R1150 R922 R928
    S5 S4/AC & Battery
    don't exist X X X X KHLB1( 0001 ) R1052 R1150 R922 R923
    KHLB2( 0010 ) R1052 R1150 R927 R928
    12 inch( 0011 ) X X X X
    12 inch( 0100 ) X X X X
    12 inch( 0101 ) X X X X
    3 3
    Reserve (0110 ) X X X X
    Reserve (0111 ) X X X X
    Reserve (1000 ) X X X X
    Reserve (1001 ) X X X X
    Reserve (1010 ) X X X X
    Reserve (1011 ) X X X X

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    MB Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 3 of 56
    A B C D E
    A B C D E

    VGA and DDR2 Voltage Rails (NB9M-GS) EDP at Tj = 97C*


    Power Supply Rail NB9P-GS NB9P-GE2
    VRAM POWER SQUENCE (V) GDDR3 DDR2 GDDR3 DDR2
    power +3VS
    plane GDDR3 FOR 4 UNIT = 5.4A NVVDD Variable 20.65A 16.96A 18.47A 16.06A
    State +1.8VS +VGA_CORE
    FB_DLLAVDD 1.1 10mA
    +1.1VS
    FB_PLLAVDD 1.1 10mA
    S0
    1
    O O O O IFPC_IOVDD 1.1 80mA 1
    S1
    O O O O IFPD_IOVDD 1.1 80mA
    S3
    O O X X IFPE_IOVDD 1.1 160mA
    S5 S4/AC
    O O X X IFPF_IOVDD 1.1 160mA
    S5 S4/ Battery only
    O X X X PEX_IOVDD/Q 1.1 1550mA
    S5 S4/AC & Battery
    don't exist X X X X PEX_PLLVDD 1.1 90mA
    PLLVDD 1.1 45mA
    SP_PLLVDD 1.1 45mA
    VID_PLLVDD 1.1 45mA
    GPIO I/O ACTIVE Function Description
    TOTAL 1.1 2.3A
    GPIO0 N/A N/A Available
    FBVDD/Q 1.8 3.37A 2.02A 3.21A 2.25A
    GPIO1 IN - Hot plug detect for IFP link C IFPA_IOVDD 1.8 95mA
    IFPB_IOVDD 1.8 95mA
    GPIO2 OUT H Panel Back-Light brightness(PWM)
    IFPAB_PLLVDD 1.8 70mA
    GPIO3 OUT H Panel Power Enable IFPCD_PLLVDD 1.8 25mA
    IFPEF_PLLVDD 1.8 85mA
    2
    GPIO4 OUT H Panel Back-Light On/Off (PWM) 2
    TOTAL 1.8 5.76A 3.69A 5.47A 3.96A
    GPIO5 OUT - GPU VID0
    DACA_VDD 3.3 110mA
    GPIO6 OUT - GPU VID1 DACB_VDD 3.3 120mA
    DACC_VDD 3.3 110mA
    GPIO7 OUT - GPU VID2 or MEM VID
    MIOA_VDDQ 3.3 10mA
    GPIO8 I/O L Thermal Catastrophic Overtemp MIOB_VDDQ 3.3 10mA
    VDD33 3.3 150mA
    GPIO9 OUT L FAN control and/or Thermal Alert (PWM)
    TOTAL 3.3 0.51A
    GPIO10 OUT Memory VREF switch

    GPIO11 I/O L SLI raster sync


    POWER UP/DOWN Sequence
    GPIO12 IN - AC power detect pin

    GPIO13 OUT - Power supply control

    GPIO14 OUT - Power supply control


    3 3
    GPIO15 IN - Hot plug detect for IFP link E
    BBP must ramp up before or at the same time as VDDC but not after(ensure that BBP>= VDDC at all times)
    GPIO16 IN - Dongle DVI Mode control for Primary Displayport

    GPIO17 IN - Dongle HDMI Mode control for Primary Displayport

    GPIO18 IN - Dongle DVI Mode control for Secondary Displayport BBP/N


    GPIO19 IN - Dongle HDMI Mode control for Secondary Displayport
    (+VGA_CORE) VDDC
    GPIO20 IN - Hot plug detect for IFP link D
    (1.8VS) VDD_CT
    GPIO21 IN - Hot plug detect for IFP link E
    (1.1VS) DPX_PDD10
    GPIO22 IN - SLI swap ready signal

    GPIO23 N/A N/A Available


    <20ms <20ms

    (3.3VS) VDDR3

    4 4
    Lower Voltage leading higner voltage requirement VDDR3-VDD_CT<2V Lower Voltage trialing higner voltage requirement VDDR3-VDD_CT<2V

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    VGA Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 4 of 56
    A B C D E
    5 4 3 2 1

    USE->56Ω,NOT USE->50Ω XDP Reserve


    +VCCP +3VS

    H_IERR# R1 1 2 49.9_0402_1% XDP_DBRESET# R2 1 2 @ 1K_0402_5%


    H_PROCHOT# R3 1 2 56_0402_5%
    +VCCP

    USE->68Ω,NOT USE-->56Ω XDP_TDI R4 1 2 54.9_0402_1%

    D XDP_TMS R5 1 2 54.9_0402_1% D
    CONN@
    JCPU1A XDP_TDO R6 1 2 @ 54.9_0402_1%
    H_A#3 J4 H1 H_ADS#
    <8> H_A#3 A[3]# ADS# H_ADS# <8>

    ADDR GROUP_0
    H_A#4 L5 E2 H_BNR# XDP_TRST# R7 1 2 54.9_0402_1%
    <8> H_A#4 H_A#5 A[4]# BNR# H_BPRI# H_BNR# <8>
    <8> H_A#5 L4 A[5]# BPRI# G5 H_BPRI# <8>
    H_A#6 K5 XDP_TCK R8 1 2 54.9_0402_1%
    <8> H_A#6 H_A#7 A[6]# H_DEFER#
    <8> H_A#7 M3 A[7]# DEFER# H5 H_DEFER# <8>
    H_A#8 N2 F21 H_DRDY#
    <8> H_A#8 H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <8>
    <8> H_A#9 J1 A[9]# DBSY# E1 H_DBSY# <8>
    H_A#10 N3
    <8> H_A#10 H_A#11 A[10]# H_BR0#
    <8> H_A#11 P5 A[11]# BR0# F1 H_BR0# <8>
    H_A#12 P2
    <8> H_A#12 A[12]#

    CONTROL
    H_A#13 L2 D20 H_IERR#
    <8> H_A#13 H_A#14 A[13]# IERR# H_INIT#
    <8> H_A#14 P4 A[14]# INIT# B3 H_INIT# <28>
    H_A#15 P1
    <8> H_A#15 H_A#16 A[15]# H_LOCK#
    R1 H4
    <8> H_A#16 H_ADSTB#0 M1
    A[16]# LOCK# H_LOCK# <8> 1/29 change to EMC1402 pn U1
    <8> H_ADSTB#0
    H_REQ#0 K3
    ADSTB[0]#
    RESET# C1
    F3
    H_RESET#
    H_RS#0
    H_RESET# <8> EMC1402 +3VS
    <8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8>
    H_REQ#1 H2 F4 H_RS#1 C1
    <8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8>
    H_REQ#2 K2 G3 H_RS#2 0.1U_0402_16V4Z
    <8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
    H_REQ#3 J3 G2 H_TRDY# 1 2
    <8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>
    H_REQ#4 L1 LM95245CIMMX NOPB MSOP 8P
    <8> H_REQ#4 REQ[4]# H_HIT# NS@
    HIT# G6 H_HIT# <8>
    H_A#17 Y2 E4 H_HITM#
    <8> H_A#17 H_A#18 A[17]# HITM# H_HITM# <8>
    <8> H_A#18 U5 A[18]#
    H_A#19 R3 AD4 1 U1
    <8> H_A#19 A[19]# BPM[0]#
    ADDR GROUP_1

    H_A#20 W6 AD3 1 8
    <8> H_A#20 A[20]# BPM[1]# VDD SCLK EC_SMB_CK2 <17,37>
    C H_A#21 U4 AD1 C2 C
    <8> H_A#21 H_A#22 A[21]# BPM[2]# 2200P_0402_50V7K H_THERMDA
    <8> H_A#22 Y5 A[22]# BPM[3]# AC4 2 D+ SDATA 7 EC_SMB_DA2 <17,37>
    H_A#23 2
    XDP/ITP SIGNALS

    <8> H_A#23 U1 A[23]# PRDY# AC2


    H_A#24 R4 AC1 H_THERMDC 3 6 2 1 +3VS
    <8> H_A#24 H_A#25 A[24]# PREQ# XDP_TCK D- ALERT/THERM2 R9 10K_0402_5%
    <8> H_A#25 T5 A[25]# TCK AC5
    H_A#26 T3 AA6 XDP_TDI +3VS 1 2 4 5
    <8> H_A#26 H_A#27 A[26]# TDI XDP_TDO R10 10K_0402_5% THERM GND
    <8> H_A#27 W2 A[27]# TDO AB3
    H_A#28 W5 AB5 XDP_TMS
    <8> H_A#28 H_A#29 A[28]# TMS XDP_TRST# EMC1402-1-ACZL-TR MSOP
    <8> H_A#29 Y4 A[29]# TRST# AB6
    H_A#30 U2 C20 XDP_DBRESET# Address:100_1100 SMSC@
    <8> H_A#30 A[30]# DBR# XDP_DBRESET# <29>
    H_A#31 V4
    <8> H_A#31 H_A#32 A[31]#
    <8> H_A#32 W3 A[32]#
    H_A#33 AA4 THERMAL
    <8> H_A#33 H_A#34 A[33]# H_PROCHOT#
    <8> H_A#34 AB2 A[34]#
    H_A#35 AA3 D21
    <8> H_A#35 H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
    <8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
    B25 H_THERMDC
    H_A20M# THERMDC
    A6
    <28> H_A20M# A20M#
    FAN1 Conn
    ICH

    H_FERR# A5 C7 H_THERMTRIP# 10/30 add


    <28> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,28>
    H_IGNNE# C4 @
    <28> H_IGNNE# IGNNE# EN_FAN1 C1651 2 1 100P_0402_50V8J
    H_STPCLK# D5
    <28> H_STPCLK# STPCLK#
    H_INTR C6 H CLK
    <28> H_INTR LINT0
    H_NMI B4 A22 CLK_CPU_BCLK
    <28> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <23>
    H_SMI# A3 A21 CLK_CPU_BCLK#
    <28> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <23> +5VS
    M4 C3 +5VS
    RSVD[01] 10U_0805_10V4Z 1
    N5 RSVD[02] H_THERMDA, H_THERMDC routing together, 2
    T2 RSVD[03]

    1
    B
    V3 Trace width / Spacing = 10 / 10 mil B
    RSVD[04] U2 D1
    B2
    RESERVED

    RSVD[05]
    RSVD pins on the CPU D2 RSVD[06] VEN1 GND 8 BAS16_SOT23-3
    should be left as NO D22 RSVD[07] VIN2 GND 7
    D3 +VCC_FAN1 3 6

    2
    CONNECT F6
    RSVD[08]
    1 2 EN_FAN1_R
    VO
    4
    GND
    5 D2
    RSVD[09] <37> EN_FAN1 VSET GND
    R11 1 2

    1
    330_0402_5% G990P11U_SOP8
    C4 BAS16_SOT23-3
    0.047U_0402_16V7K
    C5

    2
    Penryn

    +3VS 2.2U_0603_6.3V6K
    C6
    1 2

    1
    R12 1000P_0402_50V7K
    10K_0402_5%
    40mil JP1

    2
    +VCC_FAN1 1 1
    <37> FAN_SPEED1 2 2
    3 3
    1
    C7 4
    1000P_0402_50V7K GND
    5 GND
    2
    A A
    ACES_85205-03001

    CONN@

    Security Classification Compal Secret Data Compal Electronics,Ltd.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Penryn(1/3)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 5 of 56

    5 4 3 2 1
    5 4 3 2 1

    +CPU_CORE CONN@ +CPU_CORE


    JCPU1C
    CONN@ A7 AB20
    JCPU1B VCC[001] VCC[068]
    A9 VCC[002] VCC[069] AB7
    <8> H_D#0 H_D#0 E22 Y22 H_D#32 A10 AC7
    D[0]# D[32]# H_D#32 <8> VCC[003] VCC[070]
    D <8> H_D#1 H_D#1 F24 AB24 H_D#33 A12 AC9 D
    D[1]# D[33]# H_D#33 <8> VCC[004] VCC[071]
    <8> H_D#2 H_D#2 E26 V24 H_D#34 A13 AC12
    D[2]# D[34]# H_D#34 <8> VCC[005] VCC[072]

    DATA GRP 0
    <8> H_D#3 H_D#3 G22 V26 H_D#35 A15 AC13
    D[3]# D[35]# H_D#35 <8> VCC[006] VCC[073]

    DATA GRP 2
    <8> H_D#4 H_D#4 F23 V23 H_D#36 A17 AC15
    D[4]# D[36]# H_D#36 <8> VCC[007] VCC[074]
    <8> H_D#5 H_D#5 G25 T22 H_D#37 A18 AC17
    D[5]# D[37]# H_D#37 <8> VCC[008] VCC[075]
    <8> H_D#6 H_D#6 E25 U25 H_D#38 A20 AC18
    D[6]# D[38]# H_D#38 <8> VCC[009] VCC[076]
    <8> H_D#7 H_D#7 E23 U23 H_D#39 B7 AD7
    D[7]# D[39]# H_D#39 <8> VCC[010] VCC[077]
    <8> H_D#8 H_D#8 K24 Y25 H_D#40 B9 AD9
    D[8]# D[40]# H_D#40 <8> VCC[011] VCC[078]
    <8> H_D#9 H_D#9 G24 W22 H_D#41 B10 AD10
    D[9]# D[41]# H_D#41 <8> VCC[012] VCC[079]
    <8> H_D#10 H_D#10 J24 Y23 H_D#42 B12 AD12
    D[10]# D[42]# H_D#42 <8> VCC[013] VCC[080]
    <8> H_D#11 H_D#11 J23 W24 H_D#43 B14 AD14
    D[11]# D[43]# H_D#43 <8> VCC[014] VCC[081]
    <8> H_D#12 H_D#12 H22 W25 H_D#44 B15 AD15
    D[12]# D[44]# H_D#44 <8> VCC[015] VCC[082]
    <8> H_D#13 H_D#13 F26 AA23 H_D#45 B17 AD17
    D[13]# D[45]# H_D#45 <8> VCC[016] VCC[083]
    <8> H_D#14 H_D#14 K22 AA24 H_D#46 B18 AD18
    D[14]# D[46]# H_D#46 <8> VCC[017] VCC[084]
    <8> H_D#15 H_D#15 H23 AB25 H_D#47 B20 AE9
    D[15]# D[47]# H_D#47 <8> VCC[018] VCC[085]
    <8> H_DSTBN#0 H_DSTBN#0 J26 Y26 H_DSTBN#2 C9 AE10
    DSTBN[0]# DSTBN[2]# H_DSTBN#2 <8> VCC[019] VCC[086]
    <8> H_DSTBP#0 H_DSTBP#0 H26 AA26 H_DSTBP#2 C10 AE12
    DSTBP[0]# DSTBP[2]# H_DSTBP#2 <8> VCC[020] VCC[087]
    <8> H_DINV#0 H_DINV#0 H25 U22 H_DINV#2 C12 AE13
    DINV[0]# DINV[2]# H_DINV#2 <8> VCC[021] VCC[088]
    C13 VCC[022] VCC[089] AE15
    C15 VCC[023] VCC[090] AE17
    <8> H_D#16 H_D#16 N22 AE24 H_D#48 C17 AE18
    D[16]# D[48]# H_D#48 <8> VCC[024] VCC[091]
    <8> H_D#17 H_D#17 K25 AD24 H_D#49 C18 AE20
    D[17]# D[49]# H_D#49 <8> VCC[025] VCC[092]
    <8> H_D#18 H_D#18 P26 AA21 H_D#50 D9 AF9
    D[18]# D[50]# H_D#50 <8> VCC[026] VCC[093]
    <8> H_D#19 H_D#19 R23 AB22 H_D#51 D10 AF10
    D[19]# D[51]# H_D#51 <8> VCC[027] VCC[094]
    <8> H_D#20 H_D#20 L23 AB21 H_D#52 D12 AF12
    D[20]# D[52]# H_D#52 <8> VCC[028] VCC[095]

    DATA GRP 1
    <8> H_D#21 H_D#21 M24 AC26 H_D#53 D14 AF14
    D[21]# D[53]# H_D#53 <8> VCC[029] VCC[096]

    DATA GRP 3
    <8> H_D#22 H_D#22 L22 AD20 H_D#54 D15 AF15
    D[22]# D[54]# H_D#54 <8> VCC[030] VCC[097]
    <8> H_D#23 H_D#23 M23 AE22 H_D#55 D17 AF17
    D[23]# D[55]# H_D#55 <8> VCC[031] VCC[098]
    <8> H_D#24 H_D#24 P25 AF23 H_D#56 D18 AF18
    D[24]# D[56]# H_D#56 <8> VCC[032] VCC[099] +VCCP
    C
    <8> H_D#25 H_D#25 P23 AC25 H_D#57 E7 AF20 C
    D[25]# D[57]# H_D#57 <8> VCC[033] VCC[100]
    <8> H_D#26 H_D#26 P22 AE21 H_D#58 E9
    D[26]# D[58]# H_D#58 <8> VCC[034]
    <8> H_D#27 H_D#27 T24 AD21 H_D#59 E10 G21 R13 2 1 0_0402_5%
    D[27]# D[59]# H_D#59 <8> VCC[035] VCCP[01]
    <8> H_D#28 H_D#28 R24 AC22 H_D#60 E12 V6 R14 2 1 0_0402_5%
    D[28]# D[60]# H_D#60 <8> VCC[036] VCCP[02]
    <8> H_D#29 H_D#29 L25 AD23 H_D#61 E13 J6
    D[29]# D[61]# H_D#61 <8> VCC[037] VCCP[03]
    <8> H_D#30 H_D#30 T25 AF22 H_D#62 E15 K6
    D[30]# D[62]# H_D#62 <8> VCC[038] VCCP[04]
    <8> H_D#31 H_D#31 N25 AC23 H_D#63 E17 M6 For testing purpose only
    D[31]# D[63]# H_D#63 <8> VCC[039] VCCP[05]
    <8> H_DSTBN#1 H_DSTBN#1 L26 AE25 H_DSTBN#3 E18 J21
    DSTBN[1]# DSTBN[3]# H_DSTBN#3 <8> VCC[040] VCCP[06]
    <8> H_DSTBP#1 H_DSTBP#1 M26 AF24 H_DSTBP#3 E20 K21
    DSTBP[1]# DSTBP[3]# H_DSTBP#3 <8> VCC[041] VCCP[07]
    <8> H_DINV#1 H_DINV#1 N24 AC20 H_DINV#3 F7 M21
    DINV[1]# DINV[3]# H_DINV#3 <8> VCC[042] VCCP[08]
    F9 VCC[043] VCCP[09] N21
    +CPU_GTLREF AD26 R26 COMP0 R15 1 2 27.4_0402_1% F10 N6
    R16 GTLREF COMP[0] VCC[044] VCCP[10]
    1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 R17 1 2 54.9_0402_1% F12 VCC[045] VCCP[11] R21
    R18 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R19 1 2 27.4_0402_1% F14 R6
    T1 TEST3 TEST2 COMP[2] COMP3 R20 54.9_0402_1% VCC[046] VCCP[12]
    C24 TEST3 COMP[3] Y1 1 2 F15 VCC[047] VCCP[13] T21
    T2 TEST4 AF26 F17 T6 Near pin B26
    T3 TEST5 TEST4 H_DPRSTP# VCC[048] VCCP[14]
    AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,28,54> F18 VCC[049] VCCP[15] V21
    T4 TEST6 A26 B5 H_DPSLP# F20 W21
    TEST6 DPSLP# H_DPSLP# <28> VCC[050] VCCP[16]
    T5 TEST7 C3 D24 H_DPWR# AA7 20mils
    TEST7 DPWR# H_DPWR# <8> VCC[051]
    CPU_BSEL0 B22 D6 H_PWRGOOD AA9 B26
    <23> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <28> VCC[052] VCCA[01] +1.5VS

    0.01U_0402_16V7K
    CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
    <23> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <8> VCC[053] VCCA[02]

    10U_0805_10V4Z
    CPU_BSEL2 C21 AE6 H_PSI# AA12
    <23> CPU_BSEL2 BSEL[2] PSI# H_PSI# <54> VCC[054]
    AA13 VCC[055] VID[0] AD6 CPU_VID0 <54>
    Penryn AA15 AF5 1 1
    VCC[056] VID[1] CPU_VID1 <54>
    Trace Close CPU < 0.5' AA17 VCC[057] VID[2] AE5 CPU_VID2 <54>

    C8

    C9
    AA18 VCC[058] VID[3] AF4 CPU_VID3 <54>
    AA20 VCC[059] VID[4] AE3 CPU_VID4 <54> 2 2
    TRACE CLOSELY CPU < 0.5' AB9 VCC[060] VID[5] AF3 CPU_VID5 <54>
    B Width=4 mil , AC10 VCC[061] VID[6] AE2 CPU_VID6 <54> B
    COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB10
    Spacing: 15mil AB12
    VCC[062]
    COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms) VCC[063] VCCSENSE
    (55Ohm) AB14 VCC[064] VCCSENSE AF7 VCCSENSE <54>
    AB15 VCC[065]
    AB17 VCC[066]
    AB18 AE7 VSSSENSE
    VCC[067] VSSSENSE VSSSENSE <54>
    Penryn
    layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs .
    Layout note: Z0=55 ohm
    0.5" max for GTLREF.
    FSB BCLK BSEL2 BSEL1 BSEL0 H_DPRSTP# H_PSI#
    Length match within 25 mils. +CPU_CORE
    +VCCP 533 133 0 0 1 1 2
    C1650
    The trace width/space/other is
    C1548 18/7/25. 1 R22 2 VCCSENSE
    1

    667 166 0 1 1 470P_0402_50V7K 100P_0402_50V8J 100_0402_1%


    2 1
    R21
    1K_0402_1% 800 200 0 1 0 1 R23 2 VSSSENSE
    Layout Note: 100_0402_1%
    2

    +CPU_GTLREF
    Route VCCSENSE and VSSSENSE traces at
    1067 266 0 0 0 27.4 Ohms with 50 mil spacing.
    1

    Place PU and PD within 1 inch of CPU.


    R24 Length matched to within 25 mils.
    A
    2K_0402_1%
    Close to CPU pin A

    within 500mils.
    2

    Close to CPU pin AD26 Security Classification Compal Secret Data Compal Electronics, Inc.
    within 500mils. Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Penryn (2/3)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 6 of 56
    5 4 3 2 1
    5 4 3 2 1

    CONN@
    JCPU1D
    A4 VSS[001] VSS[082] P6
    A8 VSS[002] VSS[083] P21
    A11 VSS[003] VSS[084] P24
    A14 VSS[004] VSS[085] R2
    A16 R5 +CPU_CORE
    VSS[005] VSS[086]
    A19 VSS[006] VSS[087] R22
    A23 R25 10U_0805_6.3V6M
    VSS[007] VSS[088]
    D AF2 VSS[008] VSS[089] T1 D
    B6 VSS[009] VSS[090] T4 1 1 1 1 1 1 1 1
    B8 T23 C1605 C1606 C1607 C1608 C1609 C1610 C1611 C1612
    VSS[010] VSS[091]
    B11 VSS[011] VSS[092] T26
    B13 U3 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    VSS[012] VSS[093] 2 2 2 2 2 2 2 2
    B16 VSS[013] VSS[094] U6
    B19 U21 10U_0805_6.3V6M 10U_0805_6.3V6M
    VSS[014] VSS[095] 10U_0805_6.3V6M 10U_0805_6.3V6M
    B21 VSS[015] VSS[096] U24
    B24 VSS[016] VSS[097] V2 (Place these capacitors on South side,Secondary Layer)
    C5 VSS[017] VSS[098] V5
    C8 VSS[018] VSS[099] V22 330u
    C11 V25 +CPU_CORE
    VSS[019] VSS[100] ESR 9m ohm
    C14 VSS[020] VSS[101] W1
    C16 W4 Package(L*W*H)7.3*4.3*1.8
    VSS[021] VSS[102]
    C19 VSS[022] VSS[103] W23 Rating 2.5V
    C2 VSS[023] VSS[104] W26 1 1 1 1 1 1 1 1
    C22 Y3 C1613 C1614 C1615 C1616 C1617 C1618 C1619 C1620
    VSS[024] VSS[105] @ @
    C25 VSS[025] VSS[106] Y6
    D1 Y21 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    VSS[026] VSS[107] +CPU_CORE 2 2 2 2 2 2 2 2
    D4 VSS[027] VSS[108] Y24
    +CPU_CORE 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    D8 VSS[028] VSS[109] AA2 2 x 330uF(9mOhm/3)
    D11 VSS[029] VSS[110] AA5 2 x 330uF(9mOhm/3)
    D13 VSS[030] VSS[111] AA8 1 1 (Place these capacitors on North side,Secondary Layer)
    D16 VSS[031] VSS[112] AA11 1 1
    D19 AA14 C1601 + + C1602
    VSS[032] VSS[113] C1603 + + C1604 +CPU_CORE
    D23 VSS[033] VSS[114] AA16
    D26 AA19 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
    VSS[034] VSS[115] @ 2 2 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 10U_0805_6.3V6M
    E3 VSS[035] VSS[116] AA22
    2 2
    E6 VSS[036] VSS[117] AA25
    C E8 AB1 1 1 1 1 1 1 1 1 C
    VSS[037] VSS[118] C1621 C1622 C1623 C1624 C1625 C1626 C1627 C1628
    E11 VSS[038] VSS[119] AB4 South Side Secondary
    E14 AB8 North Side Secondary @ @
    VSS[039] VSS[120] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    E16 VSS[040] VSS[121] AB11
    2 2 2 2 2 2 2 2
    E19 VSS[041] VSS[122] AB13
    E21 AB16 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    VSS[042] VSS[123]
    E24 VSS[043] VSS[124] AB19
    F5 VSS[044] VSS[125] AB23 (Place these capacitors on South side,Primary Layer)
    F8 VSS[045] VSS[126] AB26
    F11 VSS[046] VSS[127] AC3
    F13 AC6 +CPU_CORE
    VSS[047] VSS[128]
    F16 VSS[048] VSS[129] AC8
    F19 VSS[049] VSS[130] AC11
    F2 VSS[050] VSS[131] AC14
    F22 VSS[051] VSS[132] AC16 1 1 1 1 1 1 1 1
    F25 AC19 C1629 C1630 C1631 C1632 C1633 C1634 C1635 C1636
    VSS[052] VSS[133]
    G4 VSS[053] VSS[134] AC21
    G1 AC24 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    VSS[054] VSS[135] 2 2 2 2 2 2 2 2
    G23 VSS[055] VSS[136] AD2
    G26 AD5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    VSS[056] VSS[137]
    H3 VSS[057] VSS[138] AD8
    H6 VSS[058] VSS[139] AD11 (Place these capacitors on North side,Primary Layer)
    H21 VSS[059] VSS[140] AD13
    H24 VSS[060] VSS[141] AD16
    J2 VSS[061] VSS[142] AD19
    J5 VSS[062] VSS[143] AD22 +CPU-CORE C,uF ESR, mohm ESL,nH
    J22 AD25
    J25
    VSS[063] VSS[144]
    AE1 Decoupling
    VSS[064] VSS[145]
    B
    K1 VSS[065] VSS[146] AE4 SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6 B
    K4 VSS[066] VSS[147] AE8
    K23 VSS[067] VSS[148] AE11 32X22uF 3m ohm/32 0.6nH/32
    K26 VSS[068] VSS[149] AE14 MLCC 0805 X5R
    L3 VSS[069] VSS[150] AE16 32X10uF 3m ohm/32 0.6nH/32
    L6 VSS[070] VSS[151] AE19
    L21 VSS[071] VSS[152] AE23
    L24 VSS[072] VSS[153] AE26
    M2 VSS[073] VSS[154] A2
    M5 VSS[074] VSS[155] AF6
    M22 AF8 +VCCP
    VSS[075] VSS[156]
    M25 VSS[076] VSS[157] AF11
    N1 VSS[077] VSS[158] AF13
    N4 VSS[078] VSS[159] AF16 1
    N23 VSS[079] VSS[160] AF19 1 1 1 1 1 1
    Place these inside socket cavity
    N26 AF21 +
    VSS[080] VSS[161] C48 C46 C47 C49 C50 C51 C52
    P3 VSS[081] VSS[162] A25
    VSS[163] AF25 220U_D2_4VM
    2 2
    0.1U_0402_16V4Z
    2
    0.1U_0402_16V4Z
    2
    0.1U_0402_16V4Z
    2
    0.1U_0402_16V4Z
    2
    0.1U_0402_16V4Z
    2
    0.1U_0402_16V4Z
    on L8 (North side Secondary)
    Penryn
    .

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Penryn (3/3)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 7 of 56
    5 4 3 2 1
    5 4 3 2 1

    U3B

    U3A T6 M36 AP24 M_CLK_DDR0


    H_A#3 T7 RSVD1 SA_CK_0 M_CLK_DDR1 M_CLK_DDR0 <14>
    H_A#_3 A14 H_A#3 <5> N36 RSVD2 SA_CK_1 AT21 M_CLK_DDR1 <14>
    H_D#0 H_A#4 +1.5V T8 M_CLK_DDR2
    <6> H_D#0 F2 H_D#_0 H_A#_4 C15 H_A#4 <5> R33 RSVD3 SB_CK_0 AV24 M_CLK_DDR2 <15>
    H_D#1 G8 F16 H_A#5 T9 T33 AU20 M_CLK_DDR3

    COMPENSATION
    <6> H_D#1 H_D#_1 H_A#_5 H_A#5 <5> RSVD4 SB_CK_1 M_CLK_DDR3 <15>
    H_D#2 F8 H13 H_A#6 T10 AH9
    <6> H_D#2 H_D#_2 H_A#_6 H_A#6 <5> RSVD5

    1
    H_D#3 E6 C18 H_A#7 T11 AH10 AR24 M_CLK_DDR#0
    <6> H_D#3 H_D#_3 H_A#_7 H_A#7 <5> RSVD6 SA_CK#_0 M_CLK_DDR#0 <14>
    H_D#4 G2 M16 H_A#8 T12 AH12 AR21 M_CLK_DDR#1
    <6> H_D#4 H_D#_4 H_A#_8 H_A#8 <5> RSVD7 SA_CK#_1 M_CLK_DDR#1 <14>
    H_D#5 H6 J13 H_A#9 R28 T13 AH13 AU24 M_CLK_DDR#2
    <6> H_D#5 H_D#_5 H_A#_9 H_A#9 <5> RSVD8 SB_CK#_0 M_CLK_DDR#2 <15>
    H_D#6 H2 P16 H_A#10 1K_0402_1% T14 K12 AV20 M_CLK_DDR#3
    <6> H_D#6 H_D#_6 H_A#_10 H_A#10 <5> RSVD9 SB_CK#_1 M_CLK_DDR#3 <15>
    H_D#7 F6 R16 H_A#11 T15 AL34
    H_A#11 <5>

    2
    <6> H_D#7 H_D#8 H_D#_7 H_A#_11 H_A#12 SMRCOMP_VOH T16 RSVD10 DDR_CKE0_DIMMA
    <6> H_D#8 D4 H_D#_8 H_A#_12 N17 H_A#12 <5> AK34 RSVD11 SA_CKE_0 BC28 DDR_CKE0_DIMMA <14>
    H_D#9 H3 M13 H_A#13 1 1 T17 AN35 AY28 DDR_CKE1_DIMMA
    <6> H_D#9 H_D#_9 H_A#_13 H_A#13 <5> RSVD12 SA_CKE_1 DDR_CKE1_DIMMA <14>

    1
    H_D#10 M9 E17 H_A#14 T18 AM35 AY36 DDR_CKE2_DIMMB
    <6> H_D#10 H_D#_10 H_A#_14 H_A#14 <5> RSVD13 SB_CKE_0 DDR_CKE2_DIMMB <15>
    H_D#11 M11 P17 H_A#15 C53 C54 T19 T24 BB36 DDR_CKE3_DIMMB
    <6> H_D#11 H_D#_11 H_A#_15 H_A#15 <5> RSVD14 SB_CKE_1 DDR_CKE3_DIMMB <15>
    H_D#12 J1 F17 H_A#16 0.01U_0402_25V7K 2.2U_0603_6.3V4Z R25
    <6> H_D#12 H_D#_12 H_A#_16 H_A#16 <5> 2 2
    H_D#13 J2 G20 H_A#17 3.01K_0402_1% BA17 DDR_CS0_DIMMA#
    D <6> H_D#13 H_D#_13 H_A#_17 H_A#17 <5> SA_CS#_0 DDR_CS0_DIMMA# <14> D
    H_D#14 N12 B19 H_A#18 AY16 DDR_CS1_DIMMA#
    H_A#18 <5>

    2
    <6> H_D#14 H_D#15 H_D#_14 H_A#_18 H_A#19 T20 SA_CS#_1 DDR_CS2_DIMMB# DDR_CS1_DIMMA# <14> +1.5V
    <6> H_D#15 J6 H_D#_15 H_A#_19 J16 H_A#19 <5> B31 RSVD15 SB_CS#_0 AV16 DDR_CS2_DIMMB# <15>
    H_D#16 P2 E20 H_A#20 SMRCOMP_VOL T26 B2 AR13 DDR_CS3_DIMMB#
    <6> H_D#16 H_D#_16 H_A#_20 H_A#20 <5> RSVD16

    DDR CLK/ CONTROL/


    H_D#17 H_A#21 T21 SB_CS#_1 DDR_CS3_DIMMB# <15>
    <6> H_D#17 L2 H_D#_17 H_A#_21 H16 H_A#21 <5> M1 RSVD17

    1
    RSVD
    H_D#18 R2 J20 H_A#22 1 1 BD17 M_ODT0
    <6> H_D#18 H_D#_18 H_A#_22 H_A#22 <5> SA_ODT_0 M_ODT0 <14>
    H_D#19 N9 L17 H_A#23 AY17 M_ODT1
    <6> H_D#19 H_D#_19 H_A#_23 H_A#23 <5> SA_ODT_1 M_ODT1 <14>
    H_D#20 L6 A17 H_A#24 C55 C56 R26 T22 AY21 BF15 M_ODT2 R27
    <6> H_D#20 H_D#_20 H_A#_24 H_A#24 <5> RSVD20 SB_ODT_O M_ODT2 <15>
    H_D#21 H_A#25 0.01U_0402_25V7K 2.2U_0603_6.3V4Z 1K_0402_1% M_ODT3 80.6_0402_1%
    <6> H_D#21 H_D#22
    M5 H_D#_21 H_A#_25 B17
    H_A#26
    H_A#25 <5> 2 2 SB_ODT_1 AY13 M_ODT3 <15>20mil
    J3 L16 H_A#26 <5>

    2
    <6> H_D#22 H_D#23 H_D#_22 H_A#_26 H_A#27 SMRCOMP
    <6> H_D#23 N2 H_D#_23 H_A#_27 C21 H_A#27 <5> SM_RCOMP BG22 For Crestline: 20ohm
    H_D#24 R1 J17 H_A#28 T23 BG23 BH21 SMRCOMP# 1 R29 2 80.6_0402_1% For Calero: 80.6ohm
    <6> H_D#24 H_D#_24 H_A#_28 H_A#28 <5> RSVD22 SM_RCOMP#
    H_D#25 N5 H20 H_A#29 T24 BF23 For Cantiga: 80.6ohm
    <6> H_D#25 H_D#_25 H_A#_29 H_A#29 <5> RSVD23
    H_D#26 N6 B18 H_A#30 T25 BH18 BF28 SMRCOMP_VOH
    <6> H_D#26 H_D#_26 H_A#_30 H_A#30 <5> RSVD24 SM_RCOMP_VOH
    H_D#27 P13 K17 H_A#31 T27 BF18 BH28 SMRCOMP_VOL R93 1 2 0_0402_5%
    <6> H_D#27 H_D#_27 H_A#_31 H_A#31 <5> RSVD25 SM_RCOMP_VOL 1.5V_PGOOD <51>
    H_D#28 N8 B20 H_A#32 R31 1 2 @ 12K_0402_5%
    <6> H_D#28 H_D#_28 H_A#_32 H_A#32 <5> DDR3_SM_PWROK <37>
    H_D#29 L7 F21 H_A#33 AV42 +DDR_MCH_REF
    <6> H_D#29 H_D#_29 H_A#_33 H_A#33 <5> SM_VREF
    H_D#30 N10 K21 H_A#34 AR36 SM_PWROK R32 1 2 @ 10K_0402_5%
    <6> H_D#30 H_D#_30 H_A#_34 H_A#34 <5> SM_PWROK
    H_D#31 M3 L20 H_A#35 BF17 SM_REXT R33 1 2 499_0402_1%
    <6> H_D#31 H_D#_31 H_A#_35 H_A#35 <5> SM_REXT
    H_D#32 Y3 BC36 SM_DRAMRST#
    <6> H_D#32 H_D#33 H_D#_32 H_ADS# SM_DRAMRST# SM_DRAMRST# <14,15>
    <6> H_D#33 AD14 H_D#_33 H_ADS# H12 H_ADS# <5>
    H_D#34 Y6 B16 H_ADSTB#0 DDR3
    <6> H_D#34 H_D#_34 H_ADSTB#_0 H_ADSTB#0 <5>
    H_D#35 Y10 G17 H_ADSTB#1 B38 CLK_MCH_DREFCLK
    <6> H_D#35 H_D#_35 H_ADSTB#_1 H_ADSTB#1 <5> DPLL_REF_CLK CLK_MCH_DREFCLK <23>
    H_D#36 Y12 A9 H_BNR# A38 CLK_MCH_DREFCLK#
    <6> H_D#36 H_D#_36 H_BNR# H_BNR# <5> DPLL_REF_CLK# CLK_MCH_DREFCLK# <23>
    HOST

    H_D#37 Y14 F11 H_BPRI# E41 MCH_SSCDREFCLK


    <6> H_D#37 H_D#_37 H_BPRI# H_BPRI# <5> DPLL_REF_SSCLK MCH_SSCDREFCLK <23>
    H_D#38 Y7 G12 H_BR0# F41 MCH_SSCDREFCLK#
    <6> H_D#38 H_D#_38 H_BREQ# H_BR0# <5> DPLL_REF_SSCLK# MCH_SSCDREFCLK# <23>
    H_D#39 H_DEFER#

    CLK
    <6> H_D#39 W2 H_D#_39 H_DEFER# E9 H_DEFER# <5>
    H_D#40 AA8 B10 H_DBSY# F43 CLK_MCH_3GPLL
    <6> H_D#40 H_D#_40 H_DBSY# H_DBSY# <5> PEG_CLK CLK_MCH_3GPLL <23>
    H_D#41 Y9 AH7 CLK_MCH_BCLK E43 CLK_MCH_3GPLL#
    <6> H_D#41 H_D#_41 HPLL_CLK CLK_MCH_BCLK <23> PEG_CLK# CLK_MCH_3GPLL# <23>
    H_D#42 AA13 AH6 CLK_MCH_BCLK#
    <6> H_D#42 H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <23>
    H_D#43 AA9 J11 H_DPWR#
    <6> H_D#43 H_D#_43 H_DPWR# H_DPWR# <6>
    H_D#44 AA11 F9 H_DRDY#
    <6> H_D#44 H_D#_44 H_DRDY# H_DRDY# <5>
    H_D#45 AD11 H9 H_HIT# AE41 DMI_TXN0
    <6> H_D#45 H_D#_45 H_HIT# H_HIT# <5> DMI_RXN_0 DMI_TXN0 <29>
    H_D#46 AD10 E12 H_HITM# AE37 DMI_TXN1
    <6> H_D#46 H_D#_46 H_HITM# H_HITM# <5> DMI_RXN_1 DMI_TXN1 <29>
    H_D#47 AD13 H11 H_LOCK# AE47 DMI_TXN2
    <6> H_D#47 H_D#_47 H_LOCK# H_LOCK# <5> DMI_RXN_2 DMI_TXN2 <29>
    H_D#48 AE12 C9 H_TRDY# AH39 DMI_TXN3
    <6> H_D#48 H_D#_48 H_TRDY# H_TRDY# <5> DMI_RXN_3 DMI_TXN3 <29>
    H_D#49 AE9
    <6> H_D#49 H_D#50 H_D#_49 DMI_TXP0
    <6> H_D#50 AA2 H_D#_50 DMI_RXP_0 AE40 DMI_TXP0 <29>
    C H_D#51 AD8 MCH_CLKSEL0 T25 AE38 DMI_TXP1 C
    <6> H_D#51 H_D#_51 <23> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <29>
    H_D#52 AA3 MCH_CLKSEL1 R25 AE48 DMI_TXP2
    <6> H_D#52 H_D#_52 <23> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 <29>
    H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL2 P25 AH40 DMI_TXP3
    <6> H_D#53 H_D#_53 H_DINV#_0 H_DINV#0 <6> <23> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 <29>
    H_D#54 AD7 L3 H_DINV#1 P20
    <6> H_D#54 H_D#_54 H_DINV#_1 H_DINV#1 <6> CFG_3
    H_D#55 AE14 Y13 H_DINV#2 P24 AE35 DMI_RXN0
    <6> H_D#55 H_D#_55 H_DINV#_2 H_DINV#2 <6> CFG_4 DMI_TXN_0 DMI_RXN0 <29>
    H_D#56 H_DINV#3 T86 CFG5 DMI_RXN1

    DMI
    <6> H_D#56 AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3 <6> C25 CFG_5 DMI_TXN_1 AE43 DMI_RXN1 <29>
    H_D#57 AC1 T28 CFG6 N24 AE46 DMI_RXN2
    <6> H_D#57 H_D#58 H_D#_57 H_DSTBN#0 T29 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3 DMI_RXN2 <29>
    <6> H_D#58 AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 <6> M24 CFG_7 DMI_TXN_3 AH42 DMI_RXN3 <29>

    CFG
    H_D#59 AC3 M7 H_DSTBN#1 T30 CFG8 E21
    <6> H_D#59 H_D#_59 H_DSTBN#_1 H_DSTBN#1 <6> CFG_8
    H_D#60 AE11 AA5 H_DSTBN#2 T31 CFG9 C23 AD35 DMI_RXP0
    <6> H_D#60 H_D#_60 H_DSTBN#_2 H_DSTBN#2 <6> CFG_9 DMI_TXP_0 DMI_RXP0 <29>
    H_D#61 AE8 AE6 H_DSTBN#3 T32 CFG10 C24 AE44 DMI_RXP1
    <6> H_D#61 H_D#_61 H_DSTBN#_3 H_DSTBN#3 <6> CFG_10 DMI_TXP_1 DMI_RXP1 <29>
    H_D#62 AG2 T33 CFG11 N21 AF46 DMI_RXP2
    <6> H_D#62 H_D#63 H_D#_62 H_DSTBP#0 T34 CFG12 CFG_11 DMI_TXP_2 DMI_RXP3 DMI_RXP2 <29>
    <6> H_D#63 AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 <6> P21 CFG_12 DMI_TXP_3 AH43 DMI_RXP3 <29>
    M8 H_DSTBP#1 T35 CFG13 T21
    H_DSTBP#_1 H_DSTBP#1 <6> CFG_13
    AA6 H_DSTBP#2 T36 CFG14 R20 MCH_HDA_BCLK
    H_DSTBP#_2 H_DSTBP#2 <6> CFG_14
    H_SWNG C5 AE5 H_DSTBP#3 T37 CFG15 M20 1
    H_SWING H_DSTBP#_3 H_DSTBP#3 <6> CFG_15
    H_RCOMP E3 +3VS T38 CFG16 L21 @
    H_RCOMP H_REQ#0 T39 CFG17 CFG_16 C57
    H_REQ#_0 B15 H_REQ#0 <5> H21 CFG_17
    K13 H_REQ#1 T40 CFG18 P29 10P_0402_50V8J

    GRAPHICS VID
    H_REQ#_1 H_REQ#1 <5> CFG_18 2
    F13 H_REQ#2 T41 CFG19 R28
    H_REQ#_2 H_REQ#2 <5> CFG_19
    1

    1
    B13 H_REQ#3 T42 CFG20 T28 B33
    H_REQ#_3 H_REQ#3 <5> CFG_20 GFX_VID_0
    H_RESET# C12 B14 H_REQ#4 B32 T43 PAD
    <5> H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 <5> GFX_VID_1
    H_CPUSLP# E11 R34 R35 G33 T44 PAD connect to power CPU_CORE
    <6> H_CPUSLP# H_CPUSLP# GFX_VID_2
    B6 H_RS#0 10K_0402_5% 10K_0402_5% F33 T45 PAD
    H_RS#_0 H_RS#0 <5> GFX_VID_3
    F12 H_RS#1 PM_BMBUSY# R29 E33 T46 PAD
    H_RS#1 <5> <29> PM_BMBUSY#
    2

    H_VREF H_RS#_1 H_RS#2 PM_EXTTS#0 H_DPRSTP# PM_SYNC# GFX_VID_4 T47 PAD


    A11 H_AVREF H_RS#_2 C8 H_RS#2 <5> <6,28,54> H_DPRSTP# B7 PM_DPRSTP#
    B11 PM_EXTTS#1 PM_EXTTS#0 N33
    H_DVREF <14,15> PM_EXTTS#0 PM_EXT_TS#_0

    PM
    PM_EXTTS#1 P32
    GM@ CANTIGA ES_FCBGA1329 PM_PWROK_R PM_EXT_TS#_1
    AT40 PWROK GFX_VR_EN C34 T48
    PLT_RST#_R AT11
    H_THERMTRIP# RSTIN# +VCCP
    <5,28> H_THERMTRIP# T20 THERMTRIP#
    DPRSLPVR R32
    <29,54> DPRSLPVR DPRSLPVR
    layout note: For AMT function

    1
    Route H_SCOMP and H_SCOMP# with trace width BG48 AH37 CL_CLK0
    NC_1 CL_CLK CL_CLK0 <29>
    spacing and impedance (55 ohm) same as FSB data traces BF48 AH36 CL_DATA0 R36
    NC_2 CL_DATA CL_DATA0 <29>

    ME
    BD48 AN36 1K_0402_1%
    NC_3 CL_PWROK M_PWROK <29>
    BC48 AJ35 CL_RST#

    2
    B
    R37 0_0402_5% PM_PWROK_R NC_4 CL_RST# CL_VREF CL_RST# <29> B
    <29,37> ICH_PWROK 1 2 BH47 NC_5 CL_VREF AH34
    BG47 NC_6
    Layout Note: <29,54> VGATE
    R39 1 2 @ 0_0402_5% BE47
    BH46
    NC_7
    N28 T49
    1
    NC_8 DDPC_CTRLCLK
    H_RCOMP / H_VREF / H_SWNG

    NC
    R40 1 2 100_0402_5% PLT_RST#_R BF46 M28 T50 C58 R38
    <16,27,32,33,35,45> PLT_RST_BUF# NC_9 DDPC_CTRLDATA
    BG45 G36 HDMICLK_NB 0.1U_0402_16V4Z 499_0402_1%
    HDMICLK_NB
    trace width and spacing is 10/20 BH44
    NC_10
    NC_11
    SDVO_CTRLCLK
    SDVO_CTRLDATA E36 HDMIDAT_NB
    MCH_CLKREQ#
    HDMIDAT_NB
    2
    BH43 NC_12 CLKREQ# K36 MCH_CLKREQ# <23>

    MISC
    BH6 H36 MCH_ICH_SYNC#
    NC_13 ICH_SYNC# MCH_ICH_SYNC# <29>
    BH5 NC_14 MCH_TSATN#_EC <37>
    +VCCP +VCCP BG4 NC_15 R41
    BH3 NC_16 TSATN# B12 1 2 56_0402_5% +VCCP
    Layout Note: BF3 NC_17
    1

    +1.5V H_DPRSTP# BH2 NC_18


    R42 R43
    V_DDR_MCH_REF trace BG2
    BE2
    NC_19
    B28 MCH_HDA_BCLK R44 1 2 GM@ 0_0402_5%
    1 HDA_BITCLK_NB <28>
    width and spacing is 20/20. NC_20 HDA_BCLK
    1

    1K_0402_1% 221_0603_1% BG1 B30 MCH_HDA_RST# R46 1 2 GM@ 0_0402_5%


    NC_21 HDA_RST# HDA_RST_NB# <28>
    R45 C1549 BF1 B29 MCH_HDA_SDIN2_R R47 1 2 GM@ 33_0402_5%
    2

    H_VREF H_RCOMP H_SWNG 470P_0402_50V7K NC_22 HDA_SDI MCH_HDA_SDOUT R48 GM@ 0_0402_5% HDA_SDIN2 <28>
    10K_0402_5% BD1 NC_23 HDA_SDO C29 1 2 HDA_SDOUT_NB <28>
    2 MCH_HDA_SYNC R49 GM@ 0_0402_5%

    HDA
    BC1 NC_24 HDA_SYNC A28 1 2 HDA_SYNC_NB <28>
    1

    1 1 F1
    2

    +DDR_MCH_REF NC_25
    A47 NC_26
    R50 C59 R51 R52 C60 Notice: Please check HDA power rail to select HDA controller.
    1

    2K_0402_1% 0.1U_0402_16V4Z 24.9_0402_1% 100_0402_1% 0.1U_0402_16V4Z 1 GM@ CANTIGA ES_FCBGA1329


    2 2
    2

    C61 R53
    0.1U_0402_16V4Z 10K_0402_5%
    2
    2

    within 100 mils from NB Near B3 pin


    DPRSLPVR

    1
    CHECK C1550
    470P_0402_50V7K
    A
    2 A

    1.5V_PGOOD
    1

    D
    2 Q99
    <46,52> SYSON#
    G SSM3K7002FU_SC70-3
    S
    Security Classification Compal Secret Data Compal Electronics, Inc.
    3

    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title


    Cantiga GMCH(1/6)-GTL
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    C 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 8 of 56
    5 4 3 2 1
    5 4 3 2 1

    <15> DDR_B_D[0..63]
    U3D U3E
    D <14> DDR_A_D[0..63] DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0 D
    DDR_A_D1 SA_DQ_0 SA_BS_0 DDR_A_BS1 DDR_A_BS0 <14> DDR_B_D1 SB_DQ_0 SB_BS_0 DDR_B_BS1 DDR_B_BS0 <15>
    AJ41 SA_DQ_1 SA_BS_1 BG18 DDR_A_BS1 <14> AH46 SB_DQ_1 SB_BS_1 BB17 DDR_B_BS1 <15>
    DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
    DDR_A_D3 SA_DQ_2 SA_BS_2 DDR_A_BS2 <14> DDR_B_D3 SB_DQ_2 SB_BS_2 DDR_B_BS2 <15>
    AM38 SA_DQ_3 AP46 SB_DQ_3
    DDR_A_D4 AJ36 BB20 DDR_A_RAS# DDR_B_D4 AJ46
    DDR_A_D5 SA_DQ_4 SA_RAS# DDR_A_CAS# DDR_A_RAS# <14> DDR_B_D5 SB_DQ_4 DDR_B_RAS#
    AJ40 SA_DQ_5 SA_CAS# BD20 DDR_A_CAS# <14> AJ48 SB_DQ_5 SB_RAS# AU17 DDR_B_RAS# <15>
    DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_B_D6 AM48 BG16 DDR_B_CAS#
    DDR_A_D7 SA_DQ_6 SA_WE# DDR_A_WE# <14> DDR_B_D7 SB_DQ_6 SB_CAS# DDR_B_WE# DDR_B_CAS# <15>
    AM42 SA_DQ_7 AP48 SB_DQ_7 SB_WE# BF14 DDR_B_WE# <15>
    DDR_A_D8 AN43 DDR_B_D8 AU47
    DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
    AN44 SA_DQ_9 AU46 SB_DQ_9
    DDR_A_D10 AU40 DDR_B_D10 BA48
    DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
    AT38 SA_DQ_11 AY48 SB_DQ_11
    DDR_A_D12 AN41 DDR_B_D12 AT47
    DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
    AN39 SA_DQ_13 SA_DM_0 AM37 DDR_A_DM[0..7] <14> AR47 SB_DQ_13
    DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
    DDR_A_D15 SA_DQ_14 SA_DM_1 DDR_A_DM2 DDR_B_D15 SB_DQ_14 DDR_B_DM0
    AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47 DDR_B_DM[0..7] <15>
    DDR_A_D16 AV39 AU39 DDR_A_DM3 DDR_B_D16 BC46 AY47 DDR_B_DM1
    DDR_A_D17 SA_DQ_16 SA_DM_3 DDR_A_DM4 DDR_B_D17 SB_DQ_16 SB_DM_1 DDR_B_DM2
    AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
    DDR_A_D18 BA40 AY6 DDR_A_DM5 DDR_B_D18 BG43 BF35 DDR_B_DM3
    DDR_A_D19 SA_DQ_18 SA_DM_5 DDR_A_DM6 DDR_B_D19 SB_DQ_18 SB_DM_3 DDR_B_DM4
    BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
    DDR_A_D20 AV41 AJ5 DDR_A_DM7 DDR_B_D20 BE45 BA3 DDR_B_DM5
    DDR_A_D21 SA_DQ_20 SA_DM_7 DDR_B_D21 SB_DQ_20 SB_DM_5 DDR_B_DM6
    AY43 BC41 AP1

    B
    SA_DQ_21 SB_DQ_21 SB_DM_6

    A
    DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
    DDR_A_D23 SA_DQ_22 DDR_A_DQS0 DDR_B_D23 SB_DQ_22 SB_DM_7
    BC40 SA_DQ_23 SA_DQS_0 AJ44 DDR_A_DQS[0..7] <14> BF41 SB_DQ_23
    DDR_A_D24 AY37 AT44 DDR_A_DQS1 DDR_B_D24 BG38
    DDR_A_D25 SA_DQ_24 SA_DQS_1 DDR_A_DQS2 DDR_B_D25 SB_DQ_24 DDR_B_DQS0
    BD38 SA_DQ_25 SA_DQS_2 BA43 BF38 SB_DQ_25 SB_DQS_0 AL47 DDR_B_DQS[0..7] <15>

    MEMORY
    DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1

    MEMORY
    AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48
    DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
    DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
    AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
    C DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4 C
    DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
    AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
    DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
    DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
    BD13 SA_DQ_32 BH14 SB_DQ_32 SB_DQS_7 AN6
    DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
    SA_DQ_33 SA_DQS#_0 DDR_A_DQS#[0..7] <14> SB_DQ_33
    DDR_A_D34 BC11 AT43 DDR_A_DQS#1 DDR_B_D34 BH11
    DDR_A_D35 SA_DQ_34 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D35 SB_DQ_34 DDR_B_DQS#0
    BA12 BA44 BG8 AL46

    SYSTEM
    SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0 DDR_B_DQS#[0..7] <15>
    SYSTEM

    DDR_A_D36 AU13 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 AV47 DDR_B_DQS#1


    DDR_A_D37 SA_DQ_36 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D37 SB_DQ_36 SB_DQS#_1 DDR_B_DQS#2
    AV13 SA_DQ_37 SA_DQS#_4 AY12 BF11 SB_DQ_37 SB_DQS#_2 BH41
    DDR_A_D38 BD12 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 BH37 DDR_B_DQS#3
    DDR_A_D39 SA_DQ_38 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D39 SB_DQ_38 SB_DQS#_3 DDR_B_DQS#4
    BC12 SA_DQ_39 SA_DQS#_6 AU9 BG7 SB_DQ_39 SB_DQS#_4 BG9
    DDR_A_D40 BB9 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 BC2 DDR_B_DQS#5
    DDR_A_D41 SA_DQ_40 SA_DQS#_7 DDR_B_D41 SB_DQ_40 SB_DQS#_5 DDR_B_DQS#6
    BA9 SA_DQ_41 BC6 SB_DQ_41 SB_DQS#_6 AT2
    DDR_A_D42 AU10 DDR_B_D42 AY3 AN5 DDR_B_DQS#7
    DDR_A_D43 SA_DQ_42 DDR_B_D43 SB_DQ_42 SB_DQS#_7
    AV9 SA_DQ_43 AY1 SB_DQ_43
    DDR_A_D44 BA11 BA21 DDR_A_MA0 DDR_B_D44 BF6
    DDR_A_D45 SA_DQ_44 SA_MA_0 DDR_A_MA1 DDR_A_MA[0..14] <14> DDR_B_D45 SB_DQ_44 DDR_B_MA0
    BD9 BC24 BF5 AV17

    DDR
    SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0 DDR_B_MA[0..14] <15>
    DDR

    DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1


    DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
    BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
    DDR_A_D48 AV5 BG25 DDR_A_MA4 DDR_B_D48 AV2 AU25 DDR_B_MA3
    DDR_A_D49 SA_DQ_48 SA_MA_4 DDR_A_MA5 DDR_B_D49 SB_DQ_48 SB_MA_3 DDR_B_MA4
    AV7 SA_DQ_49 SA_MA_5 BA24 AU3 SB_DQ_49 SB_MA_4 AW25
    DDR_A_D50 AT9 BD24 DDR_A_MA6 DDR_B_D50 AR3 BB28 DDR_B_MA5
    DDR_A_D51 SA_DQ_50 SA_MA_6 DDR_A_MA7 DDR_B_D51 SB_DQ_50 SB_MA_5 DDR_B_MA6
    AN8 SA_DQ_51 SA_MA_7 BG27 AN2 SB_DQ_51 SB_MA_6 AU28
    DDR_A_D52 AU5 BF25 DDR_A_MA8 DDR_B_D52 AY2 AW28 DDR_B_MA7
    DDR_A_D53 SA_DQ_52 SA_MA_8 DDR_A_MA9 DDR_B_D53 SB_DQ_52 SB_MA_7 DDR_B_MA8
    AU6 SA_DQ_53 SA_MA_9 AW24 AV1 SB_DQ_53 SB_MA_8 AT33
    DDR_A_D54 AT5 BC21 DDR_A_MA10 DDR_B_D54 AP3 BD33 DDR_B_MA9
    DDR_A_D55 SA_DQ_54 SA_MA_10 DDR_A_MA11 DDR_B_D55 SB_DQ_54 SB_MA_9 DDR_B_MA10
    AN10 SA_DQ_55 SA_MA_11 BG26 AR1 SB_DQ_55 SB_MA_10 BB16
    DDR_A_D56 AM11 BH26 DDR_A_MA12 DDR_B_D56 AL1 AW33 DDR_B_MA11
    DDR_A_D57 SA_DQ_56 SA_MA_12 DDR_A_MA13 DDR_B_D57 SB_DQ_56 SB_MA_11 DDR_B_MA12
    AM5 SA_DQ_57 SA_MA_13 BH17 AL2 SB_DQ_57 SB_MA_12 AY33
    B DDR_A_D58 DDR_A_MA14 DDR_B_D58 DDR_B_MA13 B
    AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
    DDR_A_D59 AJ8 DDR_B_D59 AH1 AU33 DDR_B_MA14
    DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59 SB_MA_14
    AN12 SA_DQ_60 AM2 SB_DQ_60
    DDR_A_D61 AM13 DDR_B_D61 AM3
    DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
    AJ11 SA_DQ_62 AH3 SB_DQ_62
    DDR_A_D63 AJ12 DDR_B_D63 AJ3
    SA_DQ_63 SB_DQ_63
    GM@ CANTIGA ES_FCBGA1329 GM@ CANTIGA ES_FCBGA1329

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Cantiga GMCH (2/6)-DDRIII
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 9 of 56
    5 4 3 2 1
    5 4 3 2 1

    PCIE_MTX_C_GRX_N[0..15]
    PCIE_MTX_C_GRX_N[0..15] <16>
    PCIE_MTX_C_GRX_P[0..15]
    PCIE_MTX_C_GRX_P[0..15] <16>
    PCIE_GTX_C_MRX_N[0..15]
    PCIE_GTX_C_MRX_N[0..15] <16>
    PCIE_GTX_C_MRX_P[0..15]
    PCIE_GTX_C_MRX_P[0..15] <16>
    Strap Pin Table
    CFG[2:0] FSB Freq select 000 = FSB 1066MHz
    D
    Place the resistor within 500mils 010 = FSB 800MHz
    011 = FSB 667MHz D
    (1.27mm)of the (G)MCH Others = Reserved
    PEGCOMP trace width CFG[4:3] Reserved
    U3C
    and spacing is 20/25 mils. CFG5 (DMI select) 0 = DMI x 2
    +VCC_PEG
    L32 1 = DMI x 4
    <25> GMCH_ENBKL
    +3VS
    GMCH_ENBKL
    R56 1
    T51

    2 10K_0402_5%
    G32
    M32
    L_BKLT_CTRL
    L_BKLT_EN PEG_COMPI T37
    T36 PEGCOMP R59 1 2 49.9_0402_1% CFG6
    *
    0 = The iTPM Host Interface is enable
    R57 1 L_CTRL_CLK PEG_COMPO
    2 10K_0402_5% M33 1 = The iTPM Host Interface is disable
    K33
    J33
    L_CTRL_DATA
    L_DDC_CLK
    H44 PCIE_GTX_C_MRX_N0 Please check Power CFG7 (Intel Management 0 =(TLS)chiper suite with no confidentiality
    *
    GM_ENVDD L_DDC_DATA PEG_RX#_0 PCIE_GTX_C_MRX_N1
    <25> GM_ENVDD M29 L_VDD_EN PEG_RX#_1 J46 source if want Engine Crypto strap) 1 =(TLS)chiper suite with confidentiality
    L44 PCIE_GTX_C_MRX_N2
    PEG_RX#_2 PCIE_GTX_C_MRX_N3 support IAMT
    1 2 C44 LVDS_IBG PEG_RX#_3 L40 CFG8 Reserved
    R58 2.37K_0402_1% B43 N41 PCIE_GTX_C_MRX_N4
    LVDS_VBG PEG_RX#_4 PCIE_GTX_C_MRX_N5
    For Cantiga:2.37kohm E37 LVDS_VREFH PEG_RX#_5 P48 CFG9 0 = Reverse Lane,15->0, 14->1
    E38 N44 PCIE_GTX_C_MRX_N6 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
    For Crestline:2.4kohm
    For Calero: 1.5Kohm C41
    LVDS_VREFL PEG_RX#_6
    PEG_RX#_7 T43
    U43
    PCIE_GTX_C_MRX_N7
    PCIE_GTX_C_MRX_N8 CFG10 (PCIE Lookback enable) 0 = Enable
    *
    LVDSA_CLK# PEG_RX#_8 PCIE_GTX_C_MRX_N9
    C40 Y43 1 = Disable
    Note: All LVDS data
    B37
    A37
    LVDSA_CLK
    LVDSB_CLK#
    PEG_RX#_9
    PEG_RX#_10 Y48
    Y36
    PCIE_GTX_C_MRX_N10
    PCIE_GTX_C_MRX_N11 CFG11 Reserved
    *
    LVDSB_CLK PEG_RX#_11

    LVDS
    AA43 PCIE_GTX_C_MRX_N12
    signals/and it's compliments PEG_RX#_12 PCIE_GTX_C_MRX_N13
    should be routed H47 LVDSA_DATA#_0 PEG_RX#_13 AD37 CFG[13:12] (XOR/ALLZ) 00 = Reserved
    E46 AC47 PCIE_GTX_C_MRX_N14 01 = XOR Mode Enabled
    Differentially LVDSA_DATA#_1 PEG_RX#_14 PCIE_GTX_C_MRX_N15
    G40 LVDSA_DATA#_2 PEG_RX#_15 AD39 10 = All Z Mode Enabled
    A40 11 = Normal Operation(Default)
    C
    T52
    H48
    LVDSA_DATA#_3
    PEG_RX_0 H43
    J44
    PCIE_GTX_C_MRX_P0
    PCIE_GTX_C_MRX_P1 CFG[15:14] Reserved
    * C
    LVDSA_DATA_0 PEG_RX_1 PCIE_GTX_C_MRX_P2
    D45 LVDSA_DATA_1 PEG_RX_2 L43

    GRAPHICS
    F40 L41 PCIE_GTX_C_MRX_P3 CFG16 (FSB Dynamic ODT) 0 = Disabled
    LVDSA_DATA_2 PEG_RX_3 PCIE_GTX_C_MRX_P4
    B40 N40 1 = Enabled
    T53
    A41
    LVDSA_DATA_3 PEG_RX_4
    PEG_RX_5 P47
    N43
    PCIE_GTX_C_MRX_P5
    PCIE_GTX_C_MRX_P6 CFG[18:17] Reserved
    *
    LVDSB_DATA#_0 PEG_RX_6 PCIE_GTX_C_MRX_P7
    H38 LVDSB_DATA#_1 PEG_RX_7 T42
    G37 U42 PCIE_GTX_C_MRX_P8 CFG19 (DMI Lane Reversal) 0 = Normal Operation
    T54 J37
    LVDSB_DATA#_2
    LVDSB_DATA#_3
    PEG_RX_8
    PEG_RX_9 Y42
    W47
    PCIE_GTX_C_MRX_P9
    PCIE_GTX_C_MRX_P10
    (Lane number in Order)
    1 = Reverse Lane
    *
    PEG_RX_10 PCIE_GTX_C_MRX_P11
    B42 LVDSB_DATA_0 PEG_RX_11 Y37
    G38 AA42 PCIE_GTX_C_MRX_P12 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.
    T55
    F37
    K37
    LVDSB_DATA_1
    LVDSB_DATA_2
    PEG_RX_12
    PEG_RX_13 AD36
    AC48
    PCIE_GTX_C_MRX_P13
    PCIE_GTX_C_MRX_P14
    1 = PCIE/SDVO are operating simu. *
    LVDSB_DATA_3 PEG_RX_14
    CLOSE TO MCH

    PCI-EXPRESS
    AD40 PCIE_GTX_C_MRX_P15
    PEG_RX_15
    J41 PCIE_MTX_GRX_N0 C62 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0
    PEG_TX#_0 PCIE_MTX_GRX_N1 C63 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N1
    PEG_TX#_1 M46 1 2
    R60 1 2 GM@ 75_0402_5% TVA_DAC F25 M47 PCIE_MTX_GRX_N2 C64 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
    R61 TVA_DAC PEG_TX#_2
    1 2 GM@ 75_0402_5% TVB_DAC H25 TVB_DAC PEG_TX#_3 M40 PCIE_MTX_GRX_N3 C65 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3
    R62 1 2 GM@ 75_0402_5% TVC_DAC K25 M42 PCIE_MTX_GRX_N4 C66 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
    TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C67 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N5
    PEG_TX#_5 R48 1 2
    TV

    H24 N38 PCIE_MTX_GRX_N6 C68 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6


    TV_RTN PEG_TX#_6
    Layout Note: Place 150 Ω termination PEG_TX#_7 T40
    U37
    PCIE_MTX_GRX_N7
    PCIE_MTX_GRX_N8
    C69
    C70
    1
    1
    2
    2
    PM@
    PM@
    0.1U_0402_10V7K
    0.1U_0402_10V7K
    PCIE_MTX_C_GRX_N7
    PCIE_MTX_C_GRX_N8
    PEG_TX#_8
    resistors close to GMCH C31
    PEG_TX#_9 U40
    Y40
    PCIE_MTX_GRX_N9
    PCIE_MTX_GRX_N10
    C71
    C72
    1
    1
    2
    2
    PM@
    PM@
    0.1U_0402_10V7K
    0.1U_0402_10V7K
    PCIE_MTX_C_GRX_N9
    PCIE_MTX_C_GRX_N10
    R63 TV_DCONSEL_0 PEG_TX#_10
    1 2 GM@ 150_0402_1% GMCH_CRT_R E32 TV_DCONSEL_1 PEG_TX#_11 AA46 PCIE_MTX_GRX_N11 C73 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
    R64 1 2 GM@ 150_0402_1% GMCH_CRT_G AA37 PCIE_MTX_GRX_N12 C74 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12
    B R65 PEG_TX#_12 B
    1 2 GM@ 150_0402_1% GMCH_CRT_B
    PEG_TX#_13 AA40 PCIE_MTX_GRX_N13 C75 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
    AD43 PCIE_MTX_GRX_N14 C76 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14
    PEG_TX#_14 PCIE_MTX_GRX_N15 C77 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N15
    PEG_TX#_15 AC46 1 2
    GMCH_CRT_B E28 J42 PCIE_MTX_GRX_P0 C78 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
    <26> GMCH_CRT_B CRT_BLUE PEG_TX_0
    L46 PCIE_MTX_GRX_P1 C79 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
    GMCH_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 C80 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
    <26> GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2
    M39 PCIE_MTX_GRX_P3 C81 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
    PEG_TX_3
    VGA

    GMCH_CRT_R J28 M43 PCIE_MTX_GRX_P4 C82 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4


    <26> GMCH_CRT_R CRT_RED PEG_TX_4
    R47 PCIE_MTX_GRX_P5 C83 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
    PEG_TX_5 PCIE_MTX_GRX_P6 C84 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
    G29 CRT_IRTN PEG_TX_6 N37 1 2
    T39 PCIE_MTX_GRX_P7 C85 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
    GMCH_CRT_CLK H32 PEG_TX_7 PCIE_MTX_GRX_P8 C86 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
    <26> GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8 U36 1 2
    <26> GMCH_CRT_DATA GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C87 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
    R66 CRT_HSYNC CRT_DDC_DATA PEG_TX_9 PCIE_MTX_GRX_P10 C88 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10
    <26> GMCH_CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39 1 2
    GM@ E29 Y46 PCIE_MTX_GRX_P11 C89 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
    CRT_TVO_IREF PEG_TX_11
    30_0402_1%
    20mil CRT_IREF PEG_TX_12 AA36
    AA39
    PCIE_MTX_GRX_P12
    PCIE_MTX_GRX_P13
    C90
    C91
    1
    1
    2
    2
    PM@
    PM@
    0.1U_0402_10V7K
    0.1U_0402_10V7K
    PCIE_MTX_C_GRX_P12
    PCIE_MTX_C_GRX_P13
    R67 GM@ CRT_VSYNC PEG_TX_13 PCIE_MTX_GRX_P14 C92 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
    <26> GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 1 2
    30_0402_1% AD46 PCIE_MTX_GRX_P15 C93 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
    PEG_TX_15
    1

    change R64,R65 from 33ohm to 30ohm @ @


    R68 R69 GM@ CANTIGA ES_FCBGA1329
    by checklist2.0 & CRB1.0 05/08/08 0_0402_5% 0_0402_5% R70
    1.02K_0402_1%
    2

    A A

    For Cantiga:1.02kohm
    For Crestline:1.3kohm
    For Calero: 255ohm
    Security Classification Compal Secret Data Compal Electronics,Ltd.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Cantiga(3/6)-VGA/LVDS/TV
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 10 of 56
    5 4 3 2 1
    5 4 3 2 1

    +3VS +3VS_DAC_CRT
    9/7 Change symbol and PCB footprint of R73/R76 from R_1210 to R_0603
    R72
    1 2
    +VCCP
    VCC_AXF: 321.35mA

    0.01U_0402_16V7K
    0_0603_5%
    (10UF*1, 1UF*1)

    0.1U_0402_16V4Z
    GM@ U3H
    +1.05VS_DPLLA
    1 1 1 +VCCP

    C103
    VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) R73 +V1.05VS_AXF
    852mA

    C102
    GM@ GM@ C838 73mA U13 1 2 +VCCP
    VTT_1

    4.7U_0805_10V4Z

    0.1U_0402_16V4Z
    @ +3VS_DAC_CRT B27 T13 1 MBK1608121YZF_0603
    2 2 2 VCCA_CRT_DAC_1 VTT_2

    220U_D2_4VM

    10U_0805_10V4Z
    A26 U12 1 GM@ 1 2
    VCCA_CRT_DAC_2 VTT_3

    10U_0805_10V4Z

    1U_0603_10V4Z
    T12 +
    VTT_4 1 1

    C106
    C104

    C105
    VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1) U11 R75
    VTT_5

    C107
    22U_0805_6.3V6M 5mA T11 @ 1 1 0_0603_5%
    VTT_6 2 2

    C108

    C109
    CRT
    +3VS_DAC_BG A25 VCCA_DAC_BG VTT_7 U10
    2 2
    +3VS_DAC_BG VTT_8 T10
    +3VS B25 U9 GM@ GM@
    D VSSA_DAC_BG VTT_9 2 2 D
    VTT_10 T9
    1R74 2 VTT_11 U8 +1.05VS_DPLLA

    0.01U_0402_16V7K
    0_0603_5% 32.4mA T8 VCC_SM_CK: 119.85mA
    VTT_12 +1.05VS_DPLLB: 64.8mA
    0.1U_0402_16V4Z

    10U_0805_10V4Z

    4.7U_0805_10V4Z
    VTT
    GM@ +1.05VS_DPLLA F47 U7
    VCCA_DPLLA VTT_13 (470UF*1, 0.1UF*1) (10UF*1, 0.1UF*1)

    C113
    1 1 1 32.4mA VTT_14 T7 1 1
    C111

    C112
    +1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6 +1.5V_SM_CK
    +1.05VS_DPLLB
    C110

    C114
    GM@ GM@ 24mA T6 +1.5V
    VTT_16

    PLL
    R76 R77

    0.47U_0402_6.3V6K
    +1.05VS_HPLL AD1 VCCA_HPLL VTT_17 U5
    2 2 2 2 2
    139.2mA VTT_18 T5 1 2 +VCCP 1 2

    0.1U_0402_16V4Z

    10U_0805_10V4Z

    10U_0805_10V4Z

    0.1U_0402_16V4Z
    GM@ +1.05VS_MPLL AE1 V3 MBK1608121YZF_0603 0_0805_5%
    VCCA_MPLL VTT_19 GM@
    VTT_20 U3 1 1
    +1.8V_TXLVDS

    C117
    10mA VTT_21 V2 1 1

    C115

    C116

    C118
    A PEG A LVDS
    1 J48 VCCA_LVDS VTT_22 U2
    VTT_23 T2
    C120 GM@ 2 2
    J47 VSSA_LVDS VTT_24 V1
    1000P_0402_50V7K 2 GM@ 2
    VTT_25 U1
    C102 C110 2 GM@
    0.41mA
    +1.5VS_PEG_BG: 0.414mA AD48 VCCA_PEG_BG
    (0.1UF*1) +1.5VS_PEG_BG
    +1.05VS_HPLL: 24mA
    R78 20 mils
    50mA +1.05VS_HPLL (4.7UF*1, 0.1UF*1)
    +1.5VS 2 1 AA48 VCCA_PEG_PLL
    0_0402_5% 0_0402_5% 0_0603_5% +1.05VS_PEGPLL
    PM@ PM@ R79 +1.5VS_TVDAC +1.5VS
    1 R80
    C122 1 2 +VCCP
    MBK1608121YZF_0603 2 1
    0.1U_0402_16V4Z 0_0603_5%
    2 POWER

    0.022U_0402_16V7K

    0.1U_0402_16V4Z

    10U_0805_10V4Z
    AR20 1 1 C126 GM@
    +VCCP VCCA_SM_1 C123 C124
    +1.05VS_A_SM AP20 VCCA_SM_2 1 1 1
    AN20 VCCA_SM_3

    C126

    C127

    C128
    R81 747.5mA AR17 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
    VCCA_SM_4 2 2

    A SM
    1 2 AP17 VCCA_SM_5 440mA 2 2 2 VCCD_TVDAC: 58.696mA
    VCCA_SM:720mA 1 0_0805_5% AN17 B22 +V1.05VS_AXF
    VCCA_SM_6 VCC_AXF_1 (0.1UF*1, 0.01UF*1)

    AXF
    (22UF*2, 4.7UF*1, 1UF*1) 1 1 1 AT16 VCCA_SM_7 VCC_AXF_2 B21 0_0402_5%
    + C129 4.7U_0805_10V4Z C131 AR16 A21
    C132 C130 VCCA_SM_8 VCC_AXF_3 PM@ GM@ GM@ GM@
    AP16 VCCA_SM_9
    C 220U_D2_4VY_R15M 10U_0805_10V4Z 1U_0603_10V4Z 9/7 Change symbol and PCB footprint of R79 from R_0805 to R_0603 C
    2 2 2 2
    149.5mA
    VCC_SM_CK_1 BF21 +1.5V_SM_CK +1.05VS_MPLL +1.8V_TXLVDS

    SM CK
    +1.05VS_A_SM_CK VCC_SM_CK_2 BH20 40 mils
    VCCA_SM_CK: 220mA R82 VCC_SM_CK_3 BG20
    R84
    37.95mA BF20 R83
    (22UF*1, 2.2UF*1, 0.1UF*1) 2 1 AP28
    VCC_SM_CK_4
    1 2 1000P_0402_50V7K 2 1
    VCCA_SM_CK_1 +VCCP +1.8V
    1U_0402_6.3V4Z

    1U_0603_10V4Z

    0_0603_5% AN28 MBK1608121YZF_0603 0_0603_5%


    VCCA_SM_CK_2
    10U_0805_10V4Z

    0.1U_0402_16V4Z

    10U_0805_10V4Z
    AP25 C140 GM@ +1.8V_TXLVDS: 118.8mA
    VCCA_SM_CK_3
    1 1 1 1 AN25 VCCA_SM_CK_4 80mA +1.8V_TXLVDS 1 1 1 1 (22UF*1, 1000PF*1)
    C133

    C137

    C141
    AN24 K47 C135 C139 C140
    VCCA_SM_CK_5 VCC_TX_LVDS
    C134

    A CK
    @ GM@ GM@
    C138

    AM28 VCCA_SM_CK_NCTF_1 +3VS_HV


    AM26 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
    2 2 2 2 VCCA_SM_CK_NCTF_2 2 2 2 2

    0.1U_0402_16V4Z
    AM25 VCCA_SM_CK_NCTF_3 105.3mA
    AL25 VCCA_SM_CK_NCTF_4 VCC_HV_1 C35 1 1.05VS_MPLL: 139.2mA 0_0402_5%
    AM24 B35 PM@
    VCCA_SM_CK_NCTF_5 VCC_HV_2 (22UF*1, 0.1UF*1)

    C142
    HV
    AL24 VCCA_SM_CK_NCTF_6 VCC_HV_3 A35
    AM23 VCCA_SM_CK_NCTF_7 2
    AL23 VCCA_SM_CK_NCTF_8 9/7 Change symbol and value from 120 ohm to 220 ohm
    +VCC_PEG
    1782mA
    +3VS_TVDAC: 40mA VCC_PEG_1 V48 +VCCP
    U48
    (0.1UF*1, 0.01UF*1 for VCC_PEG_2 +1.05VS_PEGPLL +VCC_PEG

    PEG
    VCC_PEG_3 V47
    GM@ each DAC) 79mA VCC_PEG_4 U47
    +3VS R85 +3VS_TVDAC B24 U46 L1 2 R166 1
    +3VS_TVDAC VCCA_TV_DAC_1 VCC_PEG_5
    1 2 A24 1 2 +VCCP 0_1206_5%
    VCCA_TV_DAC_2

    10U_0805_10V4Z
    TV
    MBK1608221YZF_0603 1
    +1.5VS_HDA

    0.1U_0402_16V4Z

    220U_D2_4VM
    0_0603_5% VCC_HDA: 50mA 1

    C143

    C148
    +
    1 1 (0.1UF*1) 50mA 456mA 1 1

    C146
    C144 C145 +1.5VS 1 R168 2 A32 AH48 +VCC_DMI
    0.022U_0402_16V7K 0.1U_0402_16V4Z 0_0603_5% VCC_HDA HDA VCC_DMI_1 C147
    VCC_DMI_2 AF48
    1

    2 2

    DMI
    GM@ 1 GM@ Close to A32 AH47 VCC_DMI: 456mA 2.2U_0603_6.3V4Z
    2 2 R167 0.1U_0402_16V4Z VCC_DMI_3 2 2
    AG47
    C144 GM@ GM@ 0_0402_5% C11 VCC_DMI_4 (0.1UF*1) 0316 add
    35mA +1.5VS_PEG_PLL: 50mA
    PM@ +1.5VS_TVDAC M25
    2 VCCD_TVDAC (0.1UF*1)
    D TV/CRT

    1mA
    2

    B +1.5VS_QDAC L28 VCCD_QDAC 20mils B

    157.2mA +VCCP
    0_0402_5% +1.05VS_HPLL AF1 VCCD_HPLL
    PM@ +VCC_DMI
    50mA VTTLF1 A8
    R86
    +1.05VS_PEGPLL AA47 VCCD_PEG_PLL VTTLF2 L1
    +VCCP_D
    VTTLF

    VTTLF3 AB2 2 1
    30mA 0_0805_5%

    0.47U_0402_6.3V6K

    0.47U_0402_6.3V6K

    0.47U_0402_6.3V6K

    1U_0603_10V4Z

    10U_0805_10V4Z

    10U_0805_10V4Z
    +1.8V_LVDS M38 VCCD_LVDS_1 1 1 1
    LVDS

    L37 D3 @ R87 @ R88 1 1 1


    VCCD_LVDS_2

    C150

    C151

    C152

    C153

    C154

    C155
    +VCCP 2 1 2 1 2 1 +3VS_HV
    10_0402_5% 0_0402_5%
    2 2 2 CH751H-40PT_SOD323-2 @ @
    GM@ CANTIGA ES_FCBGA1329 2 2 2
    +3VS
    U3
    0316 add

    PM
    PM@

    VCCD_QDAC: 48.363mA 1.8V_LVDS: 60.311111mA


    +1.5VS_QDAC (0.1UF*1, 0.01UF*1) +1.8V_LVDS (1UF*1)
    R89
    R90
    2 1 +1.5VS
    1U_0402_6.3V4Z

    10U_0805_10V4Z

    0_0603_5% 2 1 +1.8V
    0.1U_0402_16V4Z

    10U_0805_10V4Z

    0_0603_5%
    1U_0603_10V4Z

    1 1 1 1 1 GM@
    C160
    C156

    C157

    C158

    C159

    A @ GM@ A
    GM@
    2 2 2 2 2
    GM@
    C160

    0_0603_5%
    PM@ Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Crestline GMCH (4/6)-VCC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 11 of 56
    5 4 3 2 1
    5 4 3 2 1

    U3F
    +VCCP +AXG_CORE
    U3G
    Check : power
    AG34 W28
    VCC_1 4140mA VCC_AXG_NTCF_1
    AC34
    AB34
    VCC_2 AP33
    AN33
    VCC_SM_1 VCC_AXG_NCTF_2 V28
    W26
    7700mA 0.22U_0402_10V4Z
    VCC_3 VCC_SM_2 VCC_AXG_NCTF_3
    AA34 VCC_4 +1.5V BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
    Y34 VCC_5 BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25 1 1 1

    10U_0805_10V4Z

    0.01U_0402_16V7K
    V34 BF32 V25

    VCC CORE
    VCC_6 VCC_SM_5 VCC_AXG_NCTF_6

    220U_D2_4VM_R15
    U34 1 BD32 W24 C164 C165 C166
    VCC_7 VCC_SM_6 VCC_AXG_NCTF_7 GM@ GM@ GM@
    3060mA AM33 VCC_8 1 2 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
    2 2 2 4.7U_0603_6.3V6K

    C168

    C162

    C163
    D
    AK33 + BB32 W23 D
    VCC_9 VCC_SM_8 VCC_AXG_NCTF_9

    VCC
    AJ33 VCC_10 BA32 VCC_SM_9 VCC_AXG_NCTF_10 V23

    0.22U_0402_10V4Z

    0.22U_0402_10V4Z

    0.1U_0402_16V4Z
    AG33 AY32 AM21 0.1U_0402_16V4Z
    10U_0805_10V4Z VCC_11 2 2 1 VCC_SM_10 VCC_AXG_NCTF_11
    AF33 VCC_12 AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21
    1 1 1 1 AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21

    C170

    C171

    C172
    C167 AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21
    AT32 V21 C166

    SM
    VCC_SM_14 VCC_AXG_NCTF_15
    AE33 VCC_13 AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21
    2 2 2 2
    AC33 VCC_14 AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20
    AA33 VCC_15 AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20
    Y33 VCC_16 BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20
    W33 VCC_17 BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20
    0_0603_5%

    POWER
    V33 VCC_18 BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19
    U33 BG30 AL19 PM@
    VCC_19 VCC_SM_21 VCC_AXG_NCTF_22
    AH28 VCC_20 BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19
    AF28 VCC_21 BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
    AC28 VCC_22 BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
    AA28 VCC_23 BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19
    AJ26 VCC_24 BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19
    AG26 VCC_25 BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19
    AE26 VCC_26 BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19
    AC26 VCC_27 AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19
    +VCCP

    GFX NCTF
    AH25 VCC_28 AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19
    AG25 VCC_29 AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19
    AF25 VCC_30 AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19
    AG24 VCC_31 VCC_NCTF_1 AM32 AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19
    AJ23 VCC_32 VCC_NCTF_2 AL32 AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17
    AH23 VCC_33 VCC_NCTF_3 AK32 AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17
    AF23 VCC_34 VCC_NCTF_4 AJ32 VCC_AXG_NCTF_37 AH17
    T32 VCC_35 VCC_NCTF_5 AH32 VCC_AXG_NCTF_38 AG17
    VCC_NCTF_6 AG32 VCC_AXG_NCTF_39 AF17
    C VCC_NCTF_7 AE32
    +VCCP
    GM@ +AXG_CORE
    BA36 VCC_SM_36/NC VCC_AXG_NCTF_40 AE17
    C
    VCC_NCTF_8 AC32 BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17

    VCC
    AA32 @ BD16 AB17
    VCC_NCTF_9 J1 VCC_SM_38/NC VCC_AXG_NCTF_42
    VCC_NCTF_10 Y32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17
    VCC_NCTF_11 W32 1 1 2 2 AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17
    VCC_NCTF_12 U32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17
    VCC_NCTF_13 AM30 JUMP_43X118 AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16
    VCC_NCTF_14 AL30 VCC_AXG_NCTF_47 AL16
    AK30 AK16

    POWER
    VCC_NCTF_15 VCC_AXG_NCTF_48
    VCC_NCTF_16 AH30 VCC_AXG_NCTF_49 AJ16
    VCC_NCTF_17 AG30 VCC_AXG_NCTF_50 AH16
    VCC_NCTF_18 AF30 VCC_AXG_NCTF_51 AG16
    VCC_NCTF_19 AE30 VCC_AXG_NCTF_52 AF16
    AC30 Y26 AE16
    NCTF
    VCC_NCTF_20 VCC_AXG_1 VCC_AXG_NCTF_53
    VCC_NCTF_21 AB30 AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16
    VCC_NCTF_22 AA30 AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16
    Y30 +AXG_CORE AA25 AA16
    VCC_NCTF_23 VCC_AXG_4 VCC_AXG_NCTF_56
    VCC_NCTF_24 W30 AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16
    V30 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 W16
    VCC_NCTF_25 VCC_AXG_6 VCC_AXG_NCTF_58
    VCC_NCTF_26 U30 AA24 VCC_AXG_7 VCC_AXG_NCTF_59 V16
    VCC

    VCC_NCTF_27 AL29 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16


    AK29 GM@ 1 GM@ GM@ 1 GM@ 1 GM@ 1 AE23
    VCC_NCTF_28 C173 C174 + C175 C176 C177 VCC_AXG_9
    VCC_NCTF_29 AJ29 AC23 VCC_AXG_10
    VCC_NCTF_30 AH29 AB23 VCC_AXG_11
    AG29 1U_0603_10V4Z AA23
    VCC_NCTF_31 2 2 2 2 2 VCC_AXG_12
    VCC_NCTF_32 AE29 AJ21 VCC_AXG_13
    VCC_NCTF_33 AC29 AG21 VCC_AXG_14
    AA29 220U_D2_4VM_R15 10U_0805_10V4Z AE21
    VCC_NCTF_34 VCC_AXG_15
    VCC_NCTF_35 Y29 AC21 VCC_AXG_16
    VCC_NCTF_36 W29 AA21 VCC_AXG_17
    VCC_NCTF_37 V29 Y21 VCC_AXG_18

    VCC
    VCC_NCTF_38 AL28 AH20 VCC_AXG_19
    VCC_NCTF_39 AK28 AF20 VCC_AXG_20
    B C176 B
    VCC_NCTF_40 AL26 AE20 VCC_AXG_21
    VCC_NCTF_41 AK26 AC20 VCC_AXG_22
    VCC_NCTF_42 AK25 AB20 VCC_AXG_23
    AK24 AA20

    GFX
    VCC_NCTF_43 VCC_AXG_24
    VCC_NCTF_44 AK23 T17 VCC_AXG_25
    T16 VCC_AXG_26
    0_0805_5% AM15 VCC_AXG_27
    PM@ AL15 VCC_AXG_28
    AE15 VCC_AXG_29
    AJ15 VCC_AXG_30
    AH15 VCC_AXG_31
    AG15 VCC_AXG_32
    AF15 VCC_AXG_33
    AB15 VCC_AXG_34
    GM@ CANTIGA ES_FCBGA1329 AA15 VCC_AXG_35
    Y15 VCC_AXG_36
    V15 VCC_AXG_37
    U15 VCC_AXG_38
    AN14
    Add these caps around PCI-E bus of NB AM14
    VCC_AXG_39
    VCC_AXG_40
    U14 AV44 VCCSM_LF1

    VCC SM LF
    VCC_AXG_41 VCC_SM_LF1
    T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
    VCC_SM_LF3 AM40 VCCSM_LF3
    +VCCP AV21 VCCSM_LF4
    VCC_SM_LF4
    VCC_SM_LF5 AY5 VCCSM_LF5
    T56 AJ14 VCC_AXG_SENSE VCC_SM_LF6 AM10 VCCSM_LF6
    T57 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7

    C179 0.1U_0402_16V4Z

    C180 0.1U_0402_16V4Z

    C181 0.22U_0402_10V4Z

    C182 0.22U_0402_10V4Z

    C183 0.47U_0402_6.3V6K

    C184 1U_0402_6.3V4Z

    C185 1U_0402_6.3V4Z
    1 1 1 1 1 1 1
    1 1 1 1 1 1
    C268 C269 C270 C276 C339 C340

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2


    A 2 2 2 2 2 2 A
    GM@ CANTIGA ES_FCBGA1329

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Crestline GMCH (5/6)-VCC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 12 of 56
    5 4 3 2 1
    5 4 3 2 1

    U3I U3J

    AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8


    AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
    AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
    BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
    AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
    AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
    AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
    AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
    AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
    AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
    Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
    T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
    D D
    N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
    L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
    G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
    BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
    BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
    AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
    AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
    AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
    AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
    V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
    R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
    P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
    H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
    F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
    BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
    AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
    AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
    AA44 VSS_30 VSS_129 L33 AW17 VSS_228
    Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
    U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
    T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
    M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
    F44
    BC43
    VSS_35
    VSS_36
    VSS_134
    VSS_135
    C32
    A31
    C17 VSS_233 VSS VSS_331
    VSS_332
    P3
    F3
    AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
    AU43 VSS_38 VSS_137 T29 VSS_334 AW2
    AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
    J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
    C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
    BG42
    AY42
    VSS_42
    VSS_43
    VSS VSS_141
    VSS_142
    F29
    A29
    K16
    G16
    VSS_240
    VSS_241
    VSS_338
    VSS_339
    AJ2
    AH2
    AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
    C C
    AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
    AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
    AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
    N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
    L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
    BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
    AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
    AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
    AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
    AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
    AA41 VSS_55 VSS_154 P28
    Y41 VSS_56 VSS_155 K28 VSS_351 U24
    U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
    T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
    M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
    G41 VSS_60 VSS_159 BF26 N13 VSS_258
    B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
    BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
    BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
    AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
    AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
    H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
    E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
    AT39 BD25 AA12 U26

    VSS NCTF
    VSS_68 VSS_167 VSS_266 VSS_NCTF_8
    AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
    AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
    AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
    N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
    L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
    B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
    BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
    BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
    B B
    BA38 VSS_77 VSS_176 J25 Y11 VSS_275
    AU38 VSS_78 VSS_177 G25 N11 VSS_276
    AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
    AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
    AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
    Y38 AY24 AV10 C1

    VSS SCB
    VSS_82 VSS_181 VSS_280 VSS_SCB_4
    U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
    T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
    J38 VSS_85 VSS_184 AH24 AE10 VSS_283
    F38 VSS_86 VSS_185 AF24 AA10 VSS_284
    C38 VSS_87 VSS_186 AB24 M10 VSS_285
    BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
    BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
    AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
    AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
    AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
    AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
    H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
    C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
    BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
    BD36 Y23 AV8 C46
    NC

    VSS_97 VSS_196 VSS_295 NC_35


    AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
    AU36 VSS_99 VSS_198 A23 NC_37 B47
    VSS_199 AJ6 NC_38 A46
    NC_39 F48
    GM@ CANTIGA ES_FCBGA1329 E48
    NC_40
    NC_41 C48
    NC_42 B48

    GM@ CANTIGA ES_FCBGA1329

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Cantiga GMCH (6/6)-GND
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 13 of 56
    5 4 3 2 1
    5 4 3 2 1

    +1.5V +1.5V

    +V_DDR3_DIMM_REF
    <9> DDR_A_DQS#[0..7]
    CONN@
    <9> DDR_A_D[0..63] JP2
    1 VREF_DQ VSS1 2
    +1.5V DDR_A_D4
    <9> DDR_A_DM[0..7] 3 VSS2 DQ4 4
    DDR_A_D0 5 6 DDR_A_D5
    DDR_A_D1 DQ0 DQ5
    <9> DDR_A_DQS[0..7] 7 DQ1 VSS3 8

    1
    9 10 DDR_A_DQS#0
    R91 DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
    <9> DDR_A_MA[0..14] 11 DM0 DQS0 12
    100_0402_1% 13 14
    +V_DDR3_DIMM_REF DDR_A_D2 VSS5 VSS6 DDR_A_D6
    15 DQ2 DQ6 16
    DDR_A_D3 17 18 DDR_A_D7

    2
    D +V_DDR3_DIMM_REF DQ3 DQ7 D
    <15> +V_DDR3_DIMM_REF 19 VSS7 VSS8 20
    DDR_A_D8 21 22 DDR_A_D12
    DQ8 DQ12

    1
    0.1U_0402_16V4Z
    DDR_A_D9 23 24 DDR_A_D13
    DQ9 DQ13
    1 25 VSS9 VSS10 26
    C186 R92 DDR_A_DQS#1 27 28 DDR_A_DM1
    100_0402_1% DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST#
    29 DQS1 RESET# 30 SM_DRAMRST# <8,15>
    31 32

    2
    2 DDR_A_D10 VSS11 VSS12 DDR_A_D14
    33 DQ10 DQ14 34
    DDR_A_D11 35 36 DDR_A_D15
    DQ11 DQ15
    37 VSS13 VSS14 38
    DDR_A_D16 39 40 DDR_A_D20
    DDR_A_D17 DQ16 DQ20 DDR_A_D21
    41 DQ17 DQ21 42
    43 VSS15 VSS16 44
    DDR_A_DQS#2 45 46 DDR_A_DM2
    DDR_A_DQS2 DQS#2 DM2
    47 DQS2 VSS17 48
    49 50 DDR_A_D22
    DDR_A_D18 VSS18 DQ22 DDR_A_D23
    51 DQ18 DQ23 52
    DDR_A_D19 53 54
    DQ19 VSS19 DDR_A_D28
    55 VSS20 DQ28 56
    DDR_A_D24 57 58 DDR_A_D29
    DDR_A_D25 DQ24 DQ29
    59 DQ25 VSS21 60
    61 62 DDR_A_DQS#3
    DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
    63 DM3 DQS3 64
    65 VSS23 VSS24 66
    DDR_A_D26 67 68 DDR_A_D30
    DDR_A_D27 DQ26 DQ30 DDR_A_D31
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72

    Layout Note: DDR_CKE0_DIMMA DDR_CKE1_DIMMA


    <8> DDR_CKE0_DIMMA 73 CKE0 CKE1 74 DDR_CKE1_DIMMA <8>
    Place near JP4 75 76
    C VDD1 VDD2 C
    77 NC1 A15 78
    DDR_A_BS2 79 80 DDR_A_MA14
    <9> DDR_A_BS2 BA2 A14
    Layout Note: Place these 4 Caps near Command 81 VDD3 VDD4 82
    DDR_A_MA12 83 84 DDR_A_MA11
    and Control signals of DIMMA DDR_A_MA9 85
    A12/BC# A11
    86 DDR_A_MA7
    A9 A7
    87 VDD5 VDD6 88
    +1.5V DDR_A_MA8 89 90 DDR_A_MA6
    DDR_A_MA5 A8 A6 DDR_A_MA4
    91 A5 A4 92
    93 VDD7 VDD8 94
    DDR_A_MA3 95 96 DDR_A_MA2
    A3 A2
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    1 DDR_A_MA1 97 98 DDR_A_MA0
    A1 A0
    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    1 1 1 1 1 1 1 1 1 1 99 VDD9 VDD10 100


    C193

    C194

    C195

    C196
    C187

    C188

    C189

    C190

    C191

    C192

    + C197 M_CLK_DDR0 101 102 M_CLK_DDR1


    470U_D2_2.5VM_R15 <8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
    M_CLK_DDR#0 103 104 M_CLK_DDR#1
    <8> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <8>
    @ 105 106
    2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
    107 A10/AP BA1 108 DDR_A_BS1 <9>
    DDR_A_BS0 109 110 DDR_A_RAS#
    <9> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <9>
    111 VDD13 VDD14 112
    DDR_A_WE# 113 114 DDR_CS0_DIMMA#
    <9> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
    DDR_A_CAS# 115 116 M_ODT0
    <9> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
    117 VDD15 VDD16 118
    DDR_A_MA13 M_ODT1 +V_DDR3_DIMM_REF
    119 A13 ODT1 120 M_ODT1 <8>
    DDR_CS1_DIMMA# 121 122
    <8> DDR_CS1_DIMMA# S1# NC2
    123 124 R95
    VDD17 VDD18 DDR_VREF_CA_DIMMA
    125 NCTEST VREF_CA 126 1 2
    127 VSS27 VSS28 128
    Layout Note: DDR_A_D32 129 130 DDR_A_D36 0_0402_5%
    DDR_A_D33 DQ32 DQ36 DDR_A_D37
    131 DQ33 DQ37 132
    Place near JP4.203 & JP4.204 133 134
    VSS29 VSS30

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    DDR_A_DQS#4 135 136 DDR_A_DM4
    DDR_A_DQS4 DQS#4 DM4
    137 DQS4 VSS31 138 1 1
    139 140 DDR_A_D38
    VSS32 DQ38

    C198

    C199
    B DDR_A_D34 DDR_A_D39 B
    141 DQ34 DQ39 142
    +0.75V DDR_A_D35 143 144
    DQ35 VSS33 DDR_A_D44 2 2
    145 VSS34 DQ44 146
    DDR_A_D40 147 148 DDR_A_D45
    DDR_A_D41 DQ40 DQ45
    149 DQ41 VSS35 150
    1U_0603_10V4Z

    1U_0603_10V4Z

    1U_0603_10V4Z

    1U_0603_10V4Z

    10U_0805_6.3V6M

    151 152 DDR_A_DQS#5


    DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
    153 DM5 DQS5 154
    2 2 2 2 1 155 VSS37 VSS38 156
    DDR_A_D42 157 158 DDR_A_D46
    DDR_A_D43 DQ42 DQ46 DDR_A_D47
    159 DQ43 DQ47 160
    161 VSS39 VSS40 162
    1 1 1 1 2
    C200

    C201

    C202

    C203

    C204

    DDR_A_D48 163 164 DDR_A_D52


    DDR_A_D49 DQ48 DQ52 DDR_A_D53
    165 DQ49 DQ53 166
    167 VSS41 VSS42 168
    DDR_A_DQS#6 169 170 DDR_A_DM6
    DDR_A_DQS6 DQS#6 DM6
    171 DQS6 VSS43 172
    173 174 DDR_A_D54
    DDR_A_D50 VSS44 DQ54 DDR_A_D55
    175 DQ50 DQ55 176
    DDR_A_D51 177 178
    DQ51 VSS45 DDR_A_D60
    179 VSS46 DQ60 180
    DDR_A_D56 181 182 DDR_A_D61
    DDR_A_D57 DQ56 DQ61
    183 DQ57 VSS47 184
    185 186 DDR_A_DQS#7
    DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
    187 DM7 DQS7 188
    189 VSS49 VSS50 190
    DDR_A_D58 191 192 DDR_A_D62
    DDR_A_D59 DQ58 DQ62 DDR_A_D63
    193 DQ59 DQ63 194
    1 R96 2 195 VSS51 VSS52 196
    10K_0402_5% 197 198 PM_EXTTS#0
    SA0 EVENT# PM_EXTTS#0 <8,15>
    199 200 CLK_SMBDATA
    +3VS VDDSPD SDA CLK_SMBDATA <15,23>
    0.1U_0402_16V4Z

    201 202 CLK_SMBCLK


    SA1 SCL CLK_SMBCLK <15,23>
    1 1 203 VTT1 VTT2 204 +0.75V
    1
    10K_0402_5%

    A C206 A
    C205 205 206
    2.2U_0603_6.3V4Z R97 G1 G2
    2 2 FOX _AS0A626-U2RN-7F_RV +0.75V DDR3 SO-DIMM A
    REVERSE
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    DDRIII-SODIMM SLOT1
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 14 of 56
    5 4 3 2 1
    5 4 3 2 1

    <9> DDR_B_DQS#[0..7] +1.5V +1.5V


    <9> DDR_B_D[0..63]
    +V_DDR3_DIMM_REF
    <9> DDR_B_DM[0..7]

    <9> DDR_B_DQS[0..7] JP3 CONN@


    <14> +V_DDR3_DIMM_REF 1 VREF_DQ VSS1 2
    <9> DDR_B_MA[0..14] 3 4 DDR_B_D4
    DDR_B_D0 VSS2 DQ4 DDR_B_D5
    5 DQ0 DQ5 6
    DDR_B_D1 7 8
    DQ1 VSS3 DDR_B_DQS#0
    9 VSS4 DQS#0 10
    DDR_B_DM0 11 12 DDR_B_DQS0
    DM0 DQS0
    13 VSS5 VSS6 14
    Layout Note: DDR_B_D2 15 16 DDR_B_D6
    D DDR_B_D3 DQ2 DQ6 DDR_B_D7 D
    17 DQ3 DQ7 18
    Place near JP5 19 20
    DDR_B_D8 VSS7 VSS8 DDR_B_D12
    21 DQ8 DQ12 22
    Layout Note: Place these 4 Caps near Command DDR_B_D9 23 24 DDR_B_D13
    DQ9 DQ13
    and Control signals of DIMMA 25 VSS9 VSS10 26
    DDR_B_DQS#1 27 28 DDR_B_DM1
    DDR_B_DQS1 DQS#1 DM1 SM_DRAMRST#
    29 DQS1 RESET# 30 SM_DRAMRST# <8,14>
    +1.5V 31 32
    DDR_B_D10 VSS11 VSS12 DDR_B_D14
    33 DQ10 DQ14 34
    DDR_B_D11 35 36 DDR_B_D15
    DQ11 DQ15
    37 VSS13 VSS14 38

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    DDR_B_D16 39 40 DDR_B_D20
    DQ16 DQ20
    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M
    1 1 1 1 1 1 1 1 1 1 1 DDR_B_D17 41 42 DDR_B_D21
    DQ17 DQ21

    C213

    C214

    C215

    C216
    C207

    C208

    C209

    C210

    C211

    C212
    43 VSS15 VSS16 44
    + C217 DDR_B_DQS#2 45 46 DDR_B_DM2
    470U_D2_2.5VM_R15 DDR_B_DQS2 DQS#2 DM2
    47 DQS2 VSS17 48
    2 2 2 2 2 2 2 2 2 2 @ DDR_B_D22
    49 VSS18 DQ22 50
    2 DDR_B_D18 DDR_B_D23
    51 DQ18 DQ23 52
    DDR_B_D19 53 54
    DQ19 VSS19 DDR_B_D28
    55 VSS20 DQ28 56
    DDR_B_D24 57 58 DDR_B_D29
    DDR_B_D25 DQ24 DQ29
    59 DQ25 VSS21 60
    61 62 DDR_B_DQS#3
    DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
    63 DM3 DQS3 64
    65 VSS23 VSS24 66
    DDR_B_D26 67 68 DDR_B_D30
    DDR_B_D27 DQ26 DQ30 DDR_B_D31
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72

    DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
    C <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8> C
    75 VDD1 VDD2 76
    77 NC1 A15 78
    DDR_B_BS2 79 80 DDR_B_MA14
    <9> DDR_B_BS2 BA2 A14
    81 VDD3 VDD4 82
    DDR_B_MA12 83 84 DDR_B_MA11
    DDR_B_MA9 A12/BC# A11 DDR_B_MA7
    85 A9 A7 86
    87 VDD5 VDD6 88
    DDR_B_MA8 89 90 DDR_B_MA6
    DDR_B_MA5 A8 A6 DDR_B_MA4
    91 A5 A4 92
    93 VDD7 VDD8 94
    Layout Note: DDR_B_MA3 95 96 DDR_B_MA2
    DDR_B_MA1 A3 A2 DDR_B_MA0
    97 A1 A0 98
    Place near JP5.203 & JP5.204 99 100
    M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
    <8> M_CLK_DDR2 101 CK0 CK1 102 M_CLK_DDR3 <8>
    M_CLK_DDR#2 103 104 M_CLK_DDR#3
    <8> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <8>
    105 VDD11 VDD12 106
    DDR_B_MA10 107 108 DDR_B_BS1
    +0.75V A10/AP BA1 DDR_B_BS1 <9>
    DDR_B_BS0 109 110 DDR_B_RAS#
    <9> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <9>
    111 VDD13 VDD14 112
    DDR_B_WE# 113 114 DDR_CS2_DIMMB#
    <9> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
    DDR_B_CAS# 115 116 M_ODT2
    <9> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
    1U_0603_10V4Z

    1U_0603_10V4Z

    1U_0603_10V4Z

    1U_0603_10V4Z

    10U_0805_6.3V6M

    117 VDD15 VDD16 118


    DDR_B_MA13 M_ODT3 +V_DDR3_DIMM_REF
    119 A13 ODT1 120 M_ODT3 <8>
    2 2 2 2 1 DDR_CS3_DIMMB# 121 122
    <8> DDR_CS3_DIMMB# S1# NC2
    123 124 R98
    VDD17 VDD18 DDR_VREF_CA_DIMMB
    125 NCTEST VREF_CA 126 1 2 0_0402_5%
    127 VSS27 VSS28 128
    1 1 1 1 2
    C218

    C219

    C220

    C221

    C222

    DDR_B_D32 129 130 DDR_B_D36


    DDR_B_D33 DQ32 DQ36 DDR_B_D37
    131 DQ33 DQ37 132
    133 VSS29 VSS30 134

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    DDR_B_DQS#4 135 136 DDR_B_DM4
    DDR_B_DQS4 DQS#4 DM4
    137 DQS4 VSS31 138 1 1
    B DDR_B_D38 B
    139 VSS32 DQ38 140

    C223

    C224
    DDR_B_D34 141 142 DDR_B_D39
    DDR_B_D35 DQ34 DQ39
    143 DQ35 VSS33 144
    DDR_B_D44 2 2
    145 VSS34 DQ44 146
    DDR_B_D40 147 148 DDR_B_D45
    DDR_B_D41 DQ40 DQ45
    149 DQ41 VSS35 150
    151 152 DDR_B_DQS#5
    DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
    153 DM5 DQS5 154
    155 VSS37 VSS38 156
    DDR_B_D42 157 158 DDR_B_D46
    DDR_B_D43 DQ42 DQ46 DDR_B_D47
    159 DQ43 DQ47 160
    161 VSS39 VSS40 162
    DDR_B_D48 163 164 DDR_B_D52
    DDR_B_D49 DQ48 DQ52 DDR_B_D53
    165 DQ49 DQ53 166
    167 VSS41 VSS42 168
    DDR_B_DQS#6 169 170 DDR_B_DM6
    DDR_B_DQS6 DQS#6 DM6
    171 DQS6 VSS43 172
    173 174 DDR_B_D54
    DDR_B_D50 VSS44 DQ54 DDR_B_D55
    175 DQ50 DQ55 176
    DDR_B_D51 177 178
    DQ51 VSS45 DDR_B_D60
    179 VSS46 DQ60 180
    DDR_B_D56 181 182 DDR_B_D61
    DDR_B_D57 DQ56 DQ61
    183 DQ57 VSS47 184
    185 186 DDR_B_DQS#7
    DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
    187 DM7 DQS7 188
    189 VSS49 VSS50 190
    DDR_B_D58 191 192 DDR_B_D62
    DDR_B_D59 DQ58 DQ62 DDR_B_D63
    193 194
    1 R99 2 195
    DQ59
    VSS51
    DQ63
    VSS52 196 same with intel DDR3 CRB connection
    10K_0402_5% 197 198 PM_EXTTS#0
    SA0 EVENT# PM_EXTTS#0 <8,14>
    199 200 CLK_SMBDATA
    +3VS VDDSPD SDA CLK_SMBDATA <14,23>
    201 202 CLK_SMBCLK
    A SA1 SCL CLK_SMBCLK <14,23> A
    0.1U_0402_16V4Z

    1 2 203 204
    1
    R100
    10K_0402_5%
    VTT1 VTT2 +0.75V
    DDR3 SO-DIMM B
    205 206
    2
    C225 G1 G2
    FOX_AS0A626-UARN-7F _RV +0.75V
    REVERSE

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    DDRIII-SODIMM SLOT2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 15 of 56
    5 4 3 2 1
    5 4 3 2 1

    PCIE_MTX_C_GRX_N[0..15]
    <10> PCIE_MTX_C_GRX_N[0..15]
    PCIE_MTX_C_GRX_P[0..15]
    <10> PCIE_MTX_C_GRX_P[0..15]
    U45A PCIE_GTX_C_MRX_N[0..15]
    <10> PCIE_GTX_C_MRX_N[0..15]
    D D
    PCIE_GTX_C_MRX_P[0..15]
    <10> PCIE_GTX_C_MRX_P[0..15]

    T87 PAD PCIE_MTX_C_GRX_P0 AA38 Y33 PCIE_GTX_MRX_P0 C1258 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0
    T88 PAD PCIE_MTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N0 C1259 1
    Y37 PCIE_RX0N PCIE_TX0N Y32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N0

    PCIE_MTX_C_GRX_P1 Y35 W33 PCIE_GTX_MRX_P1 C1260 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1


    PCIE_MTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_GTX_MRX_N1 C1261 1
    W36 PCIE_RX1N PCIE_TX1N W32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N1

    PCIE_MTX_C_GRX_P2 W38 U33 PCIE_GTX_MRX_P2 C1262 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P2


    PCIE_MTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N2 C1263 1
    V37 PCIE_RX2N PCIE_TX2N U32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N2

    PCIE_MTX_C_GRX_P3 V35 U30 PCIE_GTX_MRX_P3 C1264 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3


    PCIE_MTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_GTX_MRX_N3 C1265 1
    U36 PCIE_RX3N PCIE_TX3N U29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3

    U45G
    PCIE_MTX_C_GRX_P4 U38 T33 PCIE_GTX_MRX_P4 C1266 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4
    PCIE_MTX_C_GRX_N4 PCIE_RX4P PCIE_TX4P PCIE_GTX_MRX_N4 C1267 1
    T37 PCIE_RX4N PCIE_TX4N T32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4

    PCI EXPRESS INTERFACE


    the same with M86
    LVDS CONTROL AK27 T89
    PCIE_MTX_C_GRX_P5 PCIE_GTX_MRX_P5 C1268 1 VARY_BL
    T35 PCIE_RX5P PCIE_TX5P T30 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
    DIGON AJ27 VGA_ENVDD
    VGA_ENVDD <25>
    PCIE_MTX_C_GRX_N5 R36 T29 PCIE_GTX_MRX_N5 C1269 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5
    PCIE_RX5N PCIE_TX5N
    C C
    PCIE_MTX_C_GRX_P6 R38 P33 PCIE_GTX_MRX_P6 C1270 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
    PCIE_MTX_C_GRX_N6 PCIE_RX6P PCIE_TX6P PCIE_GTX_MRX_N6 C1271 1
    P37 PCIE_RX6N PCIE_TX6N P32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N6
    TXCLK_UP_DPF3P AK35 VGA_LVDS_BCLK <25>
    TXCLK_UN_DPF3N AL36 VGA_LVDS_BCLK# <25>
    T90 PAD PCIE_MTX_C_GRX_P7 P35 P30 PCIE_GTX_MRX_P7 C1272 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P7 AJ38
    T91 PAD PCIE_MTX_C_GRX_N7 PCIE_RX7P PCIE_TX7P PCIE_GTX_MRX_N7 C1273 1 TXOUT_U0P_DPF2P VGA_LVDS_B0 <25>
    N36 PCIE_RX7N PCIE_TX7N P29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N7
    TXOUT_U0N_DPF2N AK37 VGA_LVDS_B0# <25>

    TXOUT_U1P_DPF1P AH35 VGA_LVDS_B1 <25>


    PCIE_MTX_C_GRX_P8 N38 N33 PCIE_GTX_MRX_P8 C1274 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P8 AJ36
    PCIE_MTX_C_GRX_N8 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N8 C1275 1 TXOUT_U1N_DPF1N VGA_LVDS_B1# <25>
    M37 PCIE_RX8N PCIE_TX8N N32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N8
    TXOUT_U2P_DPF0P AG38 VGA_LVDS_B2 <25>
    TXOUT_U2N_DPF0N AH37 VGA_LVDS_B2# <25>
    PCIE_MTX_C_GRX_P9 M35 N30 PCIE_GTX_MRX_P9 C1276 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9
    PCIE_MTX_C_GRX_N9 PCIE_RX9P PCIE_TX9P PCIE_GTX_MRX_N9 C1277 1
    L36 PCIE_RX9N PCIE_TX9N N29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9
    TXOUT_U3P AF35
    TXOUT_U3N AG36
    PCIE_MTX_C_GRX_P10 L38 L33 PCIE_GTX_MRX_P10 C1278 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10
    PCIE_MTX_C_GRX_N10 PCIE_RX10P PCIE_TX10P PCIE_GTX_MRX_N10 C1279 1 LVTMDP
    K37 PCIE_RX10N PCIE_TX10N L32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10

    TXCLK_LP_DPE3P AP34 VGA_LVDS_ACLK <25>


    PCIE_MTX_C_GRX_P11 K35 L30 PCIE_GTX_MRX_P11 C1280 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11 AR34
    PCIE_MTX_C_GRX_N11 PCIE_RX11P PCIE_TX11P PCIE_GTX_MRX_N11 C1281 1 TXCLK_LN_DPE3N VGA_LVDS_ACLK# <25>
    J36 PCIE_RX11N PCIE_TX11N L29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N11
    TXOUT_L0P_DPE2P AW37 VGA_LVDS_A0 <25>
    TXOUT_L0N_DPE2N AU35 VGA_LVDS_A0# <25>
    PCIE_MTX_C_GRX_P12 J38 K33 PCIE_GTX_MRX_P12 C1282 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
    PCIE_MTX_C_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N12 C1283 1
    H37 PCIE_RX12N PCIE_TX12N K32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N12
    TXOUT_L1P_DPE1P AR37 VGA_LVDS_A1 <25>
    TXOUT_L1N_DPE1N AU39 VGA_LVDS_A1# <25>
    B PCIE_MTX_C_GRX_P13 PCIE_GTX_MRX_P13 C1284 1 B
    H35 PCIE_RX13P PCIE_TX13P J33 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P13
    TXOUT_L2P_DPE0P AP35 VGA_LVDS_A2 <25>
    PCIE_MTX_C_GRX_N13 G36 J32 PCIE_GTX_MRX_N13 C1285 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N13 AR35
    PCIE_RX13N PCIE_TX13N TXOUT_L2N_DPE0N VGA_LVDS_A2# <25>

    TXOUT_L3P AN36
    PCIE_MTX_C_GRX_P14 G38 K30 PCIE_GTX_MRX_P14 C1286 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14 AP37
    PCIE_MTX_C_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_GTX_MRX_N14 C1287 1 TXOUT_L3N
    F37 PCIE_RX14N PCIE_TX14N K29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N14

    T92 PAD PCIE_MTX_C_GRX_P15 F35 H33 PCIE_GTX_MRX_P15 C1288 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15
    T93 PAD PCIE_MTX_C_GRX_N15 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N15 C1289 1
    E37 PCIE_RX15N PCIE_TX15N H32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15
    216-0729042-00 A13 M96 BGA 962P 030
    PM@

    CLOCK
    CLK_PCIE_VGA AB35
    <23> CLK_PCIE_VGA PCIE_REFCLKP
    CLK_PCIE_VGA# AA36
    <23> CLK_PCIE_VGA# PCIE_REFCLKN

    CALIBRATION R1213 1.27K_0402_1%


    AJ21 NC#1 PCIE_CALRP Y30 PCIE_CALRP 1 2
    AK21 PM@
    NC#2
    AH16 NC_PWRGOOD PCIE_CALRN Y29 PCIE_CALRN 1 2 +1.1VS
    R1174 2K_0402_1%
    PM@
    PLT_RST_BUF# AA30
    <8,27,32,33,35,45> PLT_RST_BUF# PERSTB

    216-0729042-00 A13 M96 BGA 962P 030


    A A
    PM@

    Security Classification Compal Secret Data Compal Electronics,Ltd.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    M96- PCIE Interface
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 16 of 56
    5 4 3 2 1
    5 4 3 2 1

    Strap Name Pin Straps description Default Value


    U45B
    TX_PWRS_ENB GPIO0 Transmitter Power Saving Enable 1
    0: 50% Tx output swing for mobile mode External VGA Thermal Sensor
    1: full Tx output swing (Default setting for Desktop)
    TX_DEEMPH_EN GPIO1 PCI Express Transmitter De-emphasis Enable 1 AU24 VGA_HDMI_CLK+ +3VS_DELAY +3VS_DELAY
    0: Tx de-emphasis diabled for mobile mode TXCAP_DPA3P VGA_HDMI_CLK- VGA_HDMI_CLK+ <24>
    TXCAM_DPA3N AV23 VGA_HDMI_CLK- <24>
    1: Tx de-emphasis enabled (Defailt setting for desktop)
    BIF_GEN2_EN GPIO2 0= Advertises the PCI-E device as 2.5 GT/s capable at power-on 0 AT25 VGA_HDMI_TX0+ 2
    TX0P_DPA2P VGA_HDMI_TX0+ <24>

    1
    1= Advertises the PCI-E device as 5.0 GT/s capable at power-on MUTI GFX AR24 VGA_HDMI_TX0- C1290 R1175 R1176
    5.0 GT/s capability will be controlled by software DPA TX0M_DPA2N VGA_HDMI_TX0- <24>
    STRAP_BIF GPIO22 Enable CLKREQ# Power Management 0 AU26 VGA_HDMI_TX1+ 0.1U_0402_16V4Z
    0: CLKREQ# power management capability is disabled TX1P_DPA1P VGA_HDMI_TX1- VGA_HDMI_TX1+ <24> PM@ 1 4.7K_0402_5% 4.7K_0402_5%
    _CLK_PM_EN TX1M_DPA1N AV25 VGA_HDMI_TX1- <24>
    1: CLKREQ# power management capability is enabled U46 @ @

    2
    GPIO13,12,11 (config 2,1,0) : 001 AR8 AT27 VGA_HDMI_TX2+ 1 EC_SMB_CK2
    memory apertures DVPCNTL_MVP_0 TX2P_DPA0P VGA_HDMI_TX2- VGA_HDMI_TX2+ <24> VDD SCLK 8 EC_SMB_CK2 <5,37>
    CONFIG[2] GPIO13 AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 VGA_HDMI_TX2- <24>
    CONFIG[1] GPIO12 a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0] AP8 D+ 2 7 EC_SMB_DA2
    DVPCNTL_0 D+ SDATA EC_SMB_DA2 <5,37>
    CONFIG[0] GPIO11 the ROM type. 128 MB 000 AW8 AR30 2200P_0402_50V7K
    D
    b) If BIOS_ROM_EN = 0, then Config[2:0] defines DVPCNTL_1 TXCBP_DPB3P VGA_THERM# D
    256 MB 001 AR3 AT29 1 2 3 6 VGA_THERM# <37>
    the primary memory aperture size. DVPCNTL_2 TXCBM_DPB3N C1291 D- ALERT#
    64 MB 010 AR1 DVPCLK
    AU1 AV31 D- PM@ 4 5
    DVPDATA_0 TX3P_DPB2P THERM# GND
    BIOS_ROM_EN GPIO22 Enable external BIOS ROM device 0 AU3 DVPDATA_1 TX3M_DPB2N AU30
    0: Diable, 1: Enable AW3 DPB PM@
    00: No audio function; 10: Audio for DisplayPort only; DVPDATA_2 ADM1032ARMZ-2REEL_MSOP8
    AUD[1] HSYNC 1 AP6 DVPDATA_3 TX4P_DPB1P AR32
    AUD(0) VSYNC 01: Audio for DisplayPort and HDMI if adapter is detected; 1 AW5 DVPDATA_4 TX4M_DPB1N AT31
    11: Audio for both DisplayPort and HDMI AU5 DVPDATA_5
    AR6 DVPDATA_6 TX5P_DPB0P AT33
    CCBYPASS GENERICC 0 AW6 DVPDATA_7 TX5M_DPB0N AU32
    SMS_EN_HARD H2SYNC AU6 DVPDATA_8
    0 AT7 DVPDATA_9 TXCCP_DPC3P AU14
    VIP_DEVICE V2SYNC If VIP_DEVICE_STRAP_EN is set to ?? then this pin is used to AV7 AV13
    DVPDATA_10 TXCCM_DPC3N
    _STRAP_DIS sense whether a VIP slave device is connected to the VIP Host AN7 DVPDATA_11
    interface. If VIP_DEVICE_STRAP_EN is set to ?? then this pin 0 AV9 DVPDATA_12 TX0P_DPC2P AT15
    is not used as a strap at all (i.e. its value during reset is AT9 DVPDATA_13 TX0M_DPC2N AR14 11/12 Add by Vivian
    unimportant), and it can be used as a regular GPIO AR10 DVPDATA_14
    AW10 DPC AU16 Location MEM_ID1 MEM_ID2 MEM_ID3
    DVPDATA_15 TX1P_DPC1P
    AU10 DVPDATA_16 TX1M_DPC1N AV15 MEM_ID0
    +1.8VS AP10 VRAM (R1179) (R1181) (R1183) (R1184)
    +3VS_DELAY DVPDATA_17
    AV11 DVPDATA_18 TX2P_DPC0P AT17
    X76_QIM@ AT11 AR16 Samsung O O O O
    R1177 1 PM@ 10K_0402_5% VGA_GPIO0 R1179 10K_0402_5% MEM_ID0 DVPDATA_19 TX2M_DPC0N
    2 1 2 AR12 DVPDATA_20
    R1178 1 PM@ 2 10K_0402_5% VGA_GPIO1 R1181 1 @ 2 10K_0402_5% MEM_ID1 AW12 AU20 Qimonda 1 O O O
    @ R1180 1 10K_0402_5% VGA_GPIO2 R1183 MEM_ID2 DVPDATA_21 TXCDP_DPD3P
    2 1 @ 2 10K_0402_5% AU12 DVPDATA_22 TXCDM_DPD3N AT19
    @ R1182 1 2 10K_0402_5% SOUT_GPIO8 R1184 1 @ 2 10K_0402_5% MEM_ID3 AP12 DVPDATA_23
    for use SBIOS TX3P_DPD2P AT21
    @ R1185 1 2 10K_0402_5% SIN_GPIO9 +3VS_DELAY AR20
    R1186 1 PM@ 10K_0402_5% VGA_GPIO11 TX3M_DPD2N
    2

    1
    @ R1187 1 2 10K_0402_5% VGA_GPIO12 DPD AU22
    @ R1188 1 2 10K_0402_5% VGA_GPIO13 R1191 R1189 TX4P_DPD1P
    TX4M_DPD1N AV21 +3VS_DELAY
    R1190 1 PM@ 2 10K_0402_5% VGA_VSYNC 4.7K_0402_5% 4.7K_0402_5% I2C
    R1192 1 PM@ VGA_HSYNC
    CRB recommend 4.7Kohm TX5P_DPD0P AT23
    +3VS_DELAY
    2 10K_0402_5% PM@ PM@ AR22 Q93

    2
    VGA_LVDS_SCL TX5M_DPD0N
    @ R1193 1 V2SYNC
    <25> VGA_LVDS_SCL
    VGA_LVDS_SDA
    AK26 SCL 100mA
    2 10K_0402_5%

    S
    AJ26 1 3

    D
    <25> VGA_LVDS_SDA SDA +3VS
    @ R1194 1 2 10K_0402_5% H2SYNC R1196 150_0402_1%

    2
    C @ R1195 1 2 10K_0402_5% ROMSE_GPIO22 AD39 VGA_CRT_R VGA_CRT_R 1 2 SI2301BDS_SOT23 C
    GENERAL PURPOSE I/O R VGA_CRT_R <26> PM@ PM@ R1198
    AD37

    G
    2
    @ R1197 1 GENERICC VGA_GPIO0 RB
    2 10K_0402_5% AH20 GPIO_0
    R1200 150_0402_1%
    10/22 Add by Vivian VGA_GPIO1 AH18 AE36 VGA_CRT_G VGA_CRT_G 1 2 100K_0402_5%
    @ R1199 1 VGA_AC_DET_R VGA_GPIO2 GPIO_1 G VGA_CRT_G <26>
    2 10K_0402_5% AN16 AD35 PM@ PM@

    1
    EC_SMB_DA2 R1316 1 GPIO_2 GB
    @ 2 0_0402_5% SMB_DA AH23 GPIO_3_SMBDATA
    R1201 150_0402_1%
    EC_SMB_CK2 R1315 1 @ 2 0_0402_5% SMB_CLK AJ23 AF37 VGA_CRT_B VGA_CRT_B 1 2
    GPIO_4_SMBCLK B VGA_CRT_B <26>

    1
    @ R1202 2 VGA_ENBKL VGA_AC_DET 1 VGA_AC_DET_R D
    1 10K_0402_5% <37> VGA_AC_DET 2 AH17 GPIO_5_AC_BATT BB AE38 PM@ R1203 100K_0402_5%
    @ R1306 0_0402_5% AJ17 DAC1 PCIE_OK 1 2 2 Q94
    GPIO_6 <53> PCIE_OK
    Risk for EC control <25> VGA_ENBKL AK17 AC36 VGA_HSYNC 1 G
    VGA_ENBKL GPIO_7_BLON HSYNC VGA_HSYNC <26>
    Pull Low at LVDS side SOUT_GPIO8 AJ13 AC38 VGA_VSYNC PM@ C1293 S SSM3K7002FU_SC70-3

    3
    SIN_GPIO9 GPIO_8_ROMSO VSYNC VGA_VSYNC <26> PM@
    AH15 GPIO_9_ROMSI
    AJ16 R1204 PM@ 0.1U_0402_16V4Z
    VGA_GPIO11 GPIO_10_ROMSCK PM@ 2
    AK16 GPIO_11 RSET AB34 1 2
    +3VS_DELAY VGA_GPIO12 499_0402_1% L81
    VGA_GPIO13
    AL16 GPIO_12 AVDD
    70mA AVDD 0.1U_0402_16V4Z
    AM16 GPIO_13 AVDD AD34 AVDD 2 1 +1.8VS
    1 @ 2 VGA_THERM# AM14 AE34 1 1 1 BLM18PG121SN1D_0603
    GPIO_14_HPD2 AVSSQ

    C1294

    C1295

    C1296
    R1205 10K_0402_5% GPU_VID0 AM13 42mA PM@
    <53> GPU_VID0 GPIO_15_PWRCNTL_0
    1 2 AK14 AC33 VDD1DI VDD1DI
    @ R1206 10K_0402_5% VGA_THERM# GPIO_16_SSIN VDD1DI
    AG30 GPIO_17_THERMAL_INT VSS1DI AC34
    AN14 PM@ 2 PM@ 2 PM@ 2
    GPIO_18_HPD3 1U_0402_6.3V4Z 10U_0603_6.3V6M
    AM17 GPIO_19_CTF
    1 2 CLKREQ_GPIO23 GPU_VID1 AL13 AC30
    @ R1207 10K_0402_5%
    <53> GPU_VID1
    <19> VGA_GPIO21
    VGA_GPIO21 AJ14
    GPIO_20_PWRCNTL_1
    GPIO_21_BB_EN
    R2
    R2B AC31 L82 PWR Sequence
    ROMSE_GPIO22 AK13 VDD1DI 0.1U_0402_16V4Z 2 1 +1.8VS
    CLKREQ_GPIO23 GPIO_22_ROMCSB BLM18PG121SN1D_0603
    M96 can not support AN13 GPIO_23_CLKREQB G2 AD30 1 1

    C1297

    C1298
    Check AM23 AD31 PM@
    JTAG_TRSTB G2B
    AN23 JTAG_TDI VGA_CORE (VDDC)
    AK23 JTAG_TCK B2 AF30
    100P_0402_50V8J 1 2 C1662 GPU_VID1 AL24 AF31 PM@ 2 2 PM@
    +1.8VS
    JTAG_TMS B2B 1U_0402_6.3V4Z
    10/31 Add AM24 JTAG_TDO
    AJ19 GENERICA +3VS_DELAY
    GENERICB AK19 AC32
    <20> GENERICB GENERICB C
    XTALIN XTALOUT GENERICC AJ20 AD32 VDD2DI L83 PM@ 0_0603_5% +1.8VS
    GENERICC Y
    AK20 GENERICD COMP AF32
    AJ24 GENERICE_HPD4
    R1208 1M_0603_5% AH26 DAC2
    PM@ GENERICF H2SYNC
    B
    AH24 GENERICG H2SYNC AD29 B
    AC29 V2SYNC
    V2SYNC
    1

    Y4 HDMI_DETECT_VGA AK24 40mA


    <24> HDMI_DETECT_VGA HPD1
    R1209 4 3 AG31 VDD2DI VDD2DI
    @ GND OUT VDD2DI A2VDD L84 PM@ 0_0603_5%
    Change R1211 part number from SD034499080 to SD034249080 VSS2DI AG32 +3VS_DELAY
    1 IN GND 2
    75_0402_1% C1302 +1.8VS 1 PM@ 2 65mA
    2

    27MHz_16PF_6P27000126 R1210 499_0402_1% AG33 A2VDD A2VDD


    C1303 PM@ 18P_0402_50V8J A2VDD
    1 PM@ 2
    PM@ R1211 249_0402_1% AD33 A2VDDQ A2VDDQ
    18P_0402_50V8J VGA_VREF A2VDDQ
    1 2 AH13 VREFG
    PM@ C1307 0.1U_0402_16V4Z AF33
    PM@ A2VSSQ
    +1.8VS A2VDDQ L85 PM@ 0_0603_5% +1.8VS
    BLM18PG121SN1D_0603 120mA AA29 1 2
    0.1U_0402_16V4Z DPLL_PVDD R2SET R1212 715_0402_1%
    2 1
    PM@ L86 1 1 1 PM@
    C1310

    C1311

    C1312

    DDC/AUX AM26 VGA_DDC_CLK


    PLL/CLOCK DDC1CLK VGA_DDC_DATA
    PM@ 2 PM@ 2 PM@ 2 DDC1DATA AN26 CRT
    AM32 DPLL_PVDD
    10U_0603_6.3V6M 1U_0402_6.3V4Z AN32 AM27
    +1.1VS DPLL_PVSS AUX1P
    AUX1N AL27
    BLM18PG121SN1D_0603 300mA
    2 1 0.1U_0402_16V4Z DPLL_VDDC AN31 AM19 VGA_HDMI_SCL
    PM@ L87 DPLL_VDDC DDC2CLK VGA_HDMI_SDA
    1 1 1 DDC2DATA AL19 HDMI
    C1313

    C1314

    C1315

    XTALIN AV33 AN20


    XTALOUT XTALIN AUX2P
    AU34 XTALOUT AUX2N AM20
    PM@ 2 PM@ 2 PM@ 2
    10U_0603_6.3V6M 1U_0402_6.3V4Z AL30
    DDCCLK_AUX3P
    DDCDATA_AUX3N AM30
    +3VS_DELAY +3VS_DELAY
    DDCCLK_AUX4P AL29
    D+ AF29 AM29
    D- DPLUS THERMAL DDCDATA_AUX4N
    AG29 DMINUS
    1

    1
    DDCCLK_AUX5P AN21
    +1.8VS R1216 R1217 R1218 R1219
    A
    BLM18PG121SN1D_0603
    20mA DDCDATA_AUX5N AM21 A
    AK32 TS_FDO
    2 1 1U_0402_6.3V4Z TSVDD AJ32 AJ30 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    PM@ L88 TSVDD DDC6CLK PM@ PM@ PM@ PM@
    1 1 AJ33 AJ31
    2

    2
    TSVSS DDC6DATA
    C1318

    C1319

    VGA_DDC_CLK VGA_HDMI_SCL
    VGA_DDC_CLK <26> VGA_HDMI_SCL <24>
    AK30 VGA_DDC_DATA VGA_HDMI_SDA
    NC_DDCCLK_AUX7P VGA_DDC_DATA <26> VGA_HDMI_SDA <24>
    NC_DDCDATA_AUX7N AK29
    PM@ 2 PM@ 2
    10U_0603_6.3V6M

    216-0729042-00 A13 M96 BGA 962P 030 Security Classification Compal Secret Data Compal Electronics, Inc.
    PM@ 2008/07/15 2009/07/15 Title
    Issued Date Deciphered Date
    M96 PCIE,LVDS,GPIO,CLK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    C 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 17 of 56
    5 4 3 2 1
    5 4 3 2 1

    U45C U45D
    MDB[0..63]
    MDA[0..63] <22> MDB[0..63]
    <21> MDA[0..63]
    MDA0 C37 G24 MAA0 MAA[0..12] MDB0 C5 P8 MAB0
    DQA_0 MAA_0 MAA[0..12] <21> DQB_0 MAB_0
    D MDA1 C35 J23 MAA1 MDB1 C3 T9 MAB1 D

    MEMORY INTERFACE A

    MEMORY INTERFACE B
    MDA2 DQA_1 MAA_1 MAA2 MDB2 DQB_1 MAB_1 MAB2
    A35 DQA_2 MAA_2 H24 E3 DQB_2 MAB_2 P9
    MDA3 E34 J24 MAA3 A_BA[0..2] MDB3 E1 N7 MAB3
    DQA_3 MAA_3 A_BA[0..2] <21> DQB_3 MAB_3
    MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
    MDA5 DQA_4 MAA_4 MAA5 MDB5 DQB_4 MAB_4 MAB5
    D33 DQA_5 MAA_5 J26 F3 DQB_5 MAB_5 N9
    MDA6 F32 H21 MAA6 DQMA#[0..7] MDB6 F5 U9 MAB6
    DQA_6 MAA_6 DQMA#[0..7] <21> DQB_6 MAB_6
    MDA7 E32 G21 MAA7 MDB7 G4 U8 MAB7
    MDA8 DQA_7 MAA_7 MAA8 MDB8 DQB_7 MAB_7 MAB8
    D31 DQA_8 MAA_8 H19 H5 DQB_8 MAB_8 Y9
    MDA9 F30 H20 MAA9 RDQSA[0..7] MDB9 H6 W9 MAB9
    DQA_9 MAA_9 RDQSA[0..7] <21> DQB_9 MAB_9
    MDA10 C30 L13 MAA10 MDB10 J4 AC8 MAB10
    MDA11 DQA_10 MAA_10 MAA11 MDB11 DQB_10 MAB_10 MAB11
    A30 DQA_11 MAA_11 G16 K6 DQB_11 MAB_11 AC9
    MDA12 F28 J16 MAA12 WDQSA[0..7] MDB12 K5 AA7 MAB12
    DQA_12 MAA_12 WDQSA[0..7] <21> DQB_12 MAB_12
    MDA13 C28 H16 A_BA2 MDB13 L4 AA8 B_BA2
    MDA14 DQA_13 MAA_13/BA2 A_BA0 MDB14 DQB_13 MAB_13/BA2 B_BA0
    A28 DQA_14 MAA_14/BA0 J17 M6 DQB_14 MAB_14/BA0 Y8
    MDA15 E28 H17 A_BA1 MAB[0..12] MDB15 M1 AA9 B_BA1
    DQA_15 MAA_15/BA1 MAB[0..12] <22> DQB_15 MAB_15/BA1
    MDA16 D27 MDB16 M3
    MDA17 DQA_16 DQMA#0 MDB17 DQB_16 DQMB#0
    F26 DQA_17 DQMA_0 A32 M5 DQB_17 DQMB_0 H3
    MDA18 C26 C32 DQMA#1 B_BA[0..2] MDB18 N4 H1 DQMB#1
    DQA_18 DQMA_1 B_BA[0..2] <22> DQB_18 DQMB_1
    MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
    MDA20 DQA_19 DQMA_2 DQMA#3 MDB20 DQB_19 DQMB_2 DQMB#3
    F24 DQA_20 DQMA_3 E22 P5 DQB_20 DQMB_3 T5
    MDA21 C24 C14 DQMA#4 DQMB#[0..7] MDB21 R4 AE4 DQMB#4
    DQA_21 DQMA_4 DQMB#[0..7] <22> DQB_21 DQMB_4
    MDA22 A24 A14 DQMA#5 MDB22 T6 AF5 DQMB#5
    MDA23 DQA_22 DQMA_5 DQMA#6 MDB23 DQB_22 DQMB_5 DQMB#6
    E24 DQA_23 DQMA_6 E10 T1 DQB_23 DQMB_6 AK6
    MDA24 C22 D9 DQMA#7 RDQSB[0..7] MDB24 U4 AK5 DQMB#7
    +1.8VS DQA_24 DQMA_7 RDQSB[0..7] <22> DQB_24 DQMB_7
    MDA25 A22 MDB25 V6
    MDA26 DQA_25 RDQSA0 MDB26 DQB_25 RDQSB0
    F22 DQA_26 QSA_0/RDQSA_0 C34 V1 DQB_26 QSB_0/RDQSB_0 F6
    MDA27 D21 D29 RDQSA1 WDQSB[0..7] MDB27 V3 K3 RDQSB1
    DQA_27 QSA_1/RDQSA_1 WDQSB[0..7] <22> DQB_27 QSB_1/RDQSB_1
    MDA28 A20 D25 RDQSA2 MDB28 Y6 P3 RDQSB2
    DQA_28 QSA_2/RDQSA_2 DQB_28 QSB_2/RDQSB_2
    2

    MDA29 F20 E20 RDQSA3 MDB29 Y1 V5 RDQSB3


    C R1220 MDA30 DQA_29 QSA_3/RDQSA_3 RDQSA4 +1.8VS MDB30 DQB_29 QSB_3/RDQSB_3 RDQSB4 C
    D19 DQA_30 QSA_4/RDQSA_4 E16 Y3 DQB_30 QSB_4/RDQSB_4 AB5
    MDA31 E18 E12 RDQSA5 MDB31 Y5 AH1 RDQSB5
    40.2_0402_1% MDA32 DQA_31 QSA_5/RDQSA_5 RDQSA6 MDB32 DQB_31 QSB_5/RDQSB_5 RDQSB6
    C18 DQA_32 QSA_6/RDQSA_6 J10 AA4 DQB_32 QSB_6/RDQSB_6 AJ9
    PM@ MDA33 A18 D7 RDQSA7 MDB33 AB6 AM5 RDQSB7
    1

    DQA_33 QSA_7/RDQSA_7 DQB_33 QSB_7/RDQSB_7

    2
    MVREFDA MDA34 F18 MDB34 AB1
    MDA35 DQA_34 WDQSA0 R1221 MDB35 DQB_34 WDQSB0
    D17 DQA_35 QSA_0B/WDQSA_0 A34 AB3 DQB_35 QSB_0B/WDQSB_0 G7
    1

    1 MDA36 A16 E30 WDQSA1 MDB36 AD6 K1 WDQSB1


    R1222 C1320 MDA37 DQA_36 QSA_1B/WDQSA_1 WDQSA2 40.2_0402_1% MDB37 DQB_36 QSB_1B/WDQSB_1 WDQSB2
    F16 DQA_37 QSA_2B/WDQSA_2 E26 AD1 DQB_37 QSB_2B/WDQSB_2 P1
    MDA38 D15 C20 WDQSA3 PM@ MDB38 AD3 W4 WDQSB3

    1
    100_0402_1% 0.1U_0402_16V4Z MDA39 DQA_38 QSA_3B/WDQSA_3 WDQSA4 MVREFDB MDB39 DQB_38 QSB_3B/WDQSB_3 WDQSB4
    E14 DQA_39 QSA_4B/WDQSA_4 C16 AD5 DQB_39 QSB_4B/WDQSB_4 AC4
    PM@ 2 PM@ MDA40 WDQSA5 MDB40 WDQSB5
    F14 C12 AF1 AH3
    2

    DQA_40 QSA_5B/WDQSA_5 DQB_40 QSB_5B/WDQSB_5

    1
    MDA41 D13 J11 WDQSA6 1 MDB41 AF3 AJ8 WDQSB6
    MDA42 DQA_41 QSA_6B/WDQSA_6 WDQSA7 MDB42 DQB_41 QSB_6B/WDQSB_6 WDQSB7
    F12 DQA_42 QSA_7B/WDQSA_7 F8 AF6 DQB_42 QSB_7B/WDQSB_7 AM3
    MDA43 A12 R1223 C1321 MDB43 AG4
    MDA44 DQA_43 100_0402_1% 0.1U_0402_16V4Z MDB44 DQB_43
    D11 DQA_44 ODTA0 J21 AH5 DQB_44 ODTB0 T7
    MDA45 PM@ 2 PM@ MDB45
    F10 G19 AH6 W7

    2
    +1.8VS MDA46 DQA_45 ODTA1 MDB46 DQB_45 ODTB1
    A10 DQA_46 AJ4 DQB_46
    MDA47 C10 H27 CLKA0 MDB47 AK3 L9 CLKB0
    DQA_47 CLKA0 CLKA0 <21> DQB_47 CLKB0 CLKB0 <22>
    MDA48 G13 G27 CLKA0# MDB48 AF8 L8 CLKB0#
    DQA_48 CLKA0B CLKA0# <21> DQB_48 CLKB0B CLKB0# <22>
    MDA49 H13 MDB49 AF9
    DQA_49 DQB_49
    2

    MDA50 J13 J14 CLKA1 MDB50 AG8 AD8 CLKB1


    DQA_50 CLKA1 CLKA1 <21> +1.8VS DQB_50 CLKB1 CLKB1 <22>
    R1224 MDA51 H11 H14 CLKA1# MDB51 AG7 AD7 CLKB1#
    DQA_51 CLKA1B CLKA1# <21> DQB_51 CLKB1B CLKB1# <22>
    MDA52 G10 MDB52 AK9
    40.2_0402_1% MDA53 DQA_52 RASA0# MDB53 DQB_52 RASB0#
    G8 DQA_53 RASA0B K23 RASA0# <21> AL7 DQB_53 RASB0B T10 RASB0# <22>
    PM@ MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
    RASA1# <21> RASB1# <22>
    1

    DQA_54 RASA1B DQB_54 RASB1B

    2
    MVREFSA MDA55 K10 MDB55 AM7
    MDA56 DQA_55 CASA0# R1225 MDB56 DQB_55 CASB0#
    G9 DQA_56 CASA0B K20 CASA0# <21> AK1 DQB_56 CASB0B W10 CASB0# <22>
    1

    1 MDA57 A8 K17 CASA1# MDB57 AL4 AA10 CASB1#


    DQA_57 CASA1B CASA1# <21> DQB_57 CASB1B CASB1# <22>
    R1226 C1322 MDA58 C8 40.2_0402_1% MDB58 AM6
    B MDA59 DQA_58 CSA0#_0 PM@ MDB59 DQB_58 CSB0#_0 B
    E8 K24 CSA0#_0 <21> AM1 P10 CSB0#_0 <22>

    1
    100_0402_1% 0.1U_0402_16V4Z MDA60 DQA_59 CSA0B_0 CSA0#_1 MVREFSB MDB60 DQB_59 CSB0B_0 CSB0#_1
    A6 DQA_60 CSA0B_1 K27 CSA0#_1 <21> AN4 DQB_60 CSB0B_1 L10 CSB0#_1 <22>
    PM@ 2 PM@ MDA61 MDB61
    C6 AP3
    2

    DQA_61 DQB_61

    1
    MDA62 E6 M13 CSA1#_0 1 MDB62 AP1 AD10 CSB1#_0
    DQA_62 CSA1B_0 CSA1#_0 <21> DQB_62 CSB1B_0 CSB1#_0 <22>
    MDA63 A5 K16 CSA1#_1 R1227 C1323 MDB63 AP5 AC10 CSB1#_1
    DQA_63 CSA1B_1 CSA1#_1 <21> DQB_63 CSB1B_1 CSB1#_1 <22>
    MVREFDA L18 K21 CKEA0 100_0402_1% 0.1U_0402_16V4Z U10 CKEB0
    MVREFDA CKEA0 CKEA0 <21> 2 PM@ CKEB0 CKEB0 <22>
    MVREFSA L20 J20 CKEA1 PM@ MVREFDB Y12 AA11 CKEB1
    CKEA1 <21> CKEB1 <22>

    2
    MVREFSA CKEA1 MVREFSB AA12 MVREFDB CKEB1
    R1228 1 M97@ MVREFSB
    +1.8VS 2 243_0402_1% L27 NC_MEM_CALRN0 WEA0B K26 WEA0#
    WEA0# <21> WEB0B N10 WEB0#
    WEB0# <22>
    R1229 1 M97@ 2 243_0402_1% N12 L15 WEA1# AB11 WEB1#
    NC_MEM_CALRN1 WEA1B WEA1# <21> WEB1B WEB1# <22>
    R1230 1 M97@ 2 243_0402_1% AG12 NC_MEM_CALRN2 +3VS_DELAY
    RSVD#1 AF28
    R1231 1 2 243_0402_1% M12 AG28 TESTEN AD28
    R1232 1 M97@ MEM_CALRP1 RSVD#2 TESTEN
    2 243_0402_1% M27 NC_MEM_CALRP0 RSVD#3 AL31
    1
    R1233 1 M97@ 2 243_0402_1% AH12 TEST_MCLK AK10
    NC_MEM_CALRP2 R1234 TEST_YCLK CLKTESTA
    RSVD#5 H23 AL10 CLKTESTB DRAM_RST AH11 MEM_RST <21,22>
    RSVD#6 J19

    1
    T8 4.7K_0402_5% R1235 R1236
    2

    RSVD#9

    1
    For M97 Only W8 @ 1
    RSVD#11 TESTEN C1324 R1237 R1238
    4.7K_0402_5% 4.7K_0402_5%

    2
    2

    PM@ PM@ 216-0729042-00 A13 M96 BGA 962P 1U_0402_6.3V4Z


    030 4.7K_0402_5% 4.7K_0402_5%
    216-0729042-00 A13 M96 BGA 962P 030 R1239 PM@ PM@ 2 @ PM@

    2
    PM@

    1K_0402_5%
    1

    PM@ +1.8VS
    A A
    ref134-0 schematic suggested

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    M96 Memory
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 18 of 56
    5 4 3 2 1
    5 4 3 2 1

    U45F U45E

    MEM I/O 220 Ohm@100Mhz,3A


    PCIE
    1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    500mA PCIE_VDDR 1U_0402_6.3V4Z 10U_0805_6.3V6M L89 2
    AB39 PCIE_VSS#1 GND#1 A3 +1.8VS AC7 VDDR1#1 PCIE_VDDR#1 AA31 1 +1.8VS
    E39 A37 AD11 AA32 KC FBM-L11-201209-221LMAT_0805
    PCIE_VSS#2 GND#2 VDDR1#2 PCIE_VDDR#2
    F34 PCIE_VSS#3 GND#3 AA16 1 1 1 1 1 1 1 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 1 1 1 PM@ 12/23 Change C20 from 220u to 330u

    C1334

    C1335

    C1325

    C1326

    C1336

    C1337

    C1327

    C1338

    C1328

    C1339

    C1329
    F39 PCIE_VSS#4 GND#4 AA18 AG10 VDDR1#4 PCIE_VDDR#4 AA34
    G33 PCIE_VSS#5 GND#5 AA2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1/19 Change C20 from 330u to 470u(SGA00001U00)
    G34 PCIE_VSS#6 GND#6 AA21 AK8 VDDR1#6 PCIE_VDDR#6 W29
    H31 AA23 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 AL9 W30
    2 2 2 2
    PCIE_VSS#7 GND#7 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDR1#7 PCIE_VDDR#7 PM@ PM@ PM@ PM@
    H34 PCIE_VSS#8 GND#8 AA26 G11 VDDR1#8 PCIE_VDDR#8 Y31
    H39 AA28 G14 10U_0805_6.3V6M 1U_0402_6.3V4Z
    PCIE_VSS#9 GND#9 VDDR1#9 +VGA_CORE
    J31 PCIE_VSS#10 GND#10 AA6 G17 VDDR1#10 2A PCIE_VDDC
    J34 AB12 G20 G30 0.1U_0402_16V4Z 1U_0402_6.3V4Z +1.1VS
    PCIE_VSS#11 GND#11 VDDR1#11 PCIE_VDDC#1
    K31 PCIE_VSS#12 GND#12 AB15 G23 VDDR1#12 PCIE_VDDC#2 G31
    D K34 AB17 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z G26 H29 1 D
    PCIE_VSS#13 GND#13 VDDR1#13 PCIE_VDDC#3
    K39 PCIE_VSS#14 GND#14 AB20 G29 VDDR1#14 PCIE_VDDC#4 H30 1 1 1 1 1
    +

    C1343

    C1344

    C1345

    C1346

    C1347
    L31 AB22 1 1 1 1 1 1 1 H10 J29 C20
    PCIE_VSS#15 GND#15 VDDR1#15 PCIE_VDDC#5

    C1330

    C1340

    C1341

    C1331

    C1332

    C1342

    C1333
    L34 AB24 J7 J30 470U_D2E_2.5VM_R9
    PCIE_VSS#16 GND#16 VDDR1#16 PCIE_VDDC#6
    M34 PCIE_VSS#17 GND#17 AB27 J9 VDDR1#17 PCIE_VDDC#7 L28
    2 2 2 2 2 PM@ 2
    M39 PCIE_VSS#18 GND#18 AC11 K11 VDDR1#18 PCIE_VDDC#8 M28
    N31 AC13 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 K13 N28 PM@ PM@ PM@ PM@ PM@
    PCIE_VSS#19 GND#19 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0805_6.3V6M VDDR1#19 PCIE_VDDC#9 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0805_6.3V6M
    N34 PCIE_VSS#20 GND#20 AC16 K8 VDDR1#20 PCIE_VDDC#10 R28
    P31 PCIE_VSS#21 GND#21 AC18 L12 VDDR1#21 PCIE_VDDC#11 T28
    P34 PCIE_VSS#22 GND#22 AC2 L16 VDDR1#22 PCIE_VDDC#12 U28
    P39 PCIE_VSS#23 GND#23 AC21 L21 VDDR1#23
    R34 AC23 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z L23
    PCIE_VSS#24 GND#24 VDDR1#24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    T31 PCIE_VSS#25 GND#25 AC26 L26 VDDR1#25 VDDC#1 AA15 +VGA_CORE
    T34 AC28 1 1 1 1 1 1 1 1 1 L7 CORE AA17
    PCIE_VSS#26 GND#26 VDDR1#26 VDDC#2

    C1348

    C1349

    C1350

    C1351

    C1352

    C1353

    C1354

    C1355

    C1356
    T39 PCIE_VSS#27 GND#27 AC6 M11 VDDR1#27 VDDC#3 AA20 1 1 1 1 1 1 1 1 1 1

    C1357

    C1358

    C1359

    C1360

    C1361

    C1362

    C1363

    C1364

    C1365

    C1366
    U31 PCIE_VSS#28 GND#28 AD15 N11 VDDR1#28 VDDC#4 AA22
    U34 PCIE_VSS#29 GND#29 AD17 P7 VDDR1#29 VDDC#5 AA24
    2 2 2 2 2 2 2 2 2
    V34 PCIE_VSS#30 GND#30 AD20 R11 VDDR1#30 VDDC#6 AA27
    V39 AD22 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ U11 AB13 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
    PCIE_VSS#31 GND#31 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1#31 VDDC#7 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    W31 PCIE_VSS#32 GND#32 AD24 U7 VDDR1#32 VDDC#8 AB16
    W34 PCIE_VSS#33 GND#33 AD27 Y11 VDDR1#33 VDDC#9 AB18
    Y34 PCIE_VSS#34 GND#34 AD9 Y7 VDDR1#34 VDDC#10 AB21
    Y39 AE2 L90 AB23
    PCIE_VSS#35 GND#35 1U_0402_6.3V4Z VDDC#11
    GND#36 AE6 +1.8VS 2 1 VDDC#12 AB26
    AF10 BLM18PG121SN1D_0603 AB28 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    GND#37 PM@ VDDC#13
    GND#38 AF16 1 1 1 VDDC#14 AC12

    C1367

    C1368

    C1369
    LEVEL
    GND#39 AF18 136mA VDDC#15 AC15 1 1 1 1 1 1 1 1 1 1

    C1370

    C1371

    C1372

    C1373

    C1374

    C1375

    C1376

    C1377

    C1378

    C1379
    AF21 TRANSLATION AC17
    GND GND#40 VDDC#16

    POWER
    AG17 VDD_CT AF26 AC20
    GND#41 PM@ 2 PM@ 2 PM@ 2 VDD_CT#1 VDDC#17
    F15 GND#101 GND#42 AG2 AF27 VDD_CT#2 VDDC#18 AC22
    F17 AG20 AG26 AC24 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
    GND#102 GND#43 10U_0805_6.3V6M 0.1U_0402_16V4Z VDD_CT#3 VDDC#19 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    F19 GND#103 GND#44 AG22 AG27 VDD_CT#4 VDDC#20 AC27
    F21 AG6 L91 AD13
    GND#104 GND#45 1U_0402_6.3V4Z VDDC#21
    F23 GND#105 GND#46 AG9 +3VS_DELAY 2 1 VDDC#22 AD16
    BLM18PG121SN1D_0603 I/O
    C
    F25 GND#106 GND#47 AH21 1 1 1 60mA VDDC#23 AD18 C

    C1380

    C1381

    C1384
    F27 AH29 PM@ VDDR3 AF23 AD21 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    GND#107 GND#48 VDDR3#1 VDDC#24
    F29 GND#108 GND#49 AJ10 AF24 VDDR3#2 VDDC#25 AD23
    F31 GND#109 GND#50 AJ11 AG23 VDDR3#3 VDDC#26 AD26 1 1 1 1 1 1 1 1 1 1
    PM@ 2 PM@ 2 PM@ 2

    C1385

    C1386

    C1387

    C1388

    C1389

    C1390

    C1391

    C1392

    C1393

    C1394
    F33 GND#110 GND#51 AJ2 AG24 VDDR3#4 VDDC#27 AF17
    F7 GND#111 GND#52 AJ28 VDDC#28 AF20
    F9 AJ6 10U_0805_6.3V6M 0.1U_0402_16V4Z 170mA AF22
    GND#112 GND#53 VDDC#29 <53> +VGASENSE
    G2 AK11 VDDR4_5 AF13 AG16 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
    GND#113 GND#54 L92 VDDR5#1 VDDC#30 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    G6 GND#114 GND#55 AK31 AF15 VDDR5#2 VDDC#31 AG18
    H9 AK7 +1.8VS 1 2 1U_0402_6.3V4Z AG13 AG21
    GND#115 GND#56 MBK1608121YZF_0603 VDDR5#3 VDDC#32 C1398
    J2 GND#116 GND#57 AL11 1 1
    C1395 1 AG15 VDDR5#4 VDDC#33 AH22

    C1396

    C1397
    J27 AL14 120Ohm@100MHz, 600mA M16 1 2
    GND#117 GND#58 VDDC#34
    J6 GND#118 GND#59 AL17 PM@ VDDC#35 M18
    J8 AL2 VDDR4_5 AD12 M23 1U_0402_6.3V4Z
    GND#119 GND#60 PM@ 2 PM@ 2 PM@ 2 VDDR4#1 VDDC#36 PM@
    K14 GND#120 GND#61 AL20 AF11 VDDR4#2 VDDC#37 M26
    K7 AL21 10U_0805_6.3V6M 0.1U_0402_16V4Z AF12 N15 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    GND#121 GND#62 VDDR4#3 VDDC#38
    L11 GND#122 GND#63 AL23 AG11 VDDR4#4 VDDC#39 N17
    L17 GND#123 GND#64 AL26 VDDC#40 N20 1 1 1 1 1 1 1

    C1399

    C1400

    C1401

    C1402

    C1403

    C1404

    C1405
    L2 GND#124 GND#65 AL32 VDDC#41 N22
    L22 GND#125 GND#66 AL6 VDDC#42 N24
    MEM CLK
    L24 GND#126 GND#67 AL8
    VDDRHA
    20mA VDDC#43 N27
    PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
    L6 GND#127 GND#68 AM11 M20 VDDRHA VDDC#44 R13
    M17 AM31 M21 R16 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    GND#128 GND#69 VSSRHA VDDC#45
    M22 GND#129 GND#70 AM9 VDDC#46 R18
    M24 GND#130 GND#71 AN11
    VDDRHB
    20mA VDDC#47 R21
    N16 GND#131 GND#72 AN2 V12 VDDRHB VDDC#48 R23
    N18 AN30 L93 U12 R26
    GND#132 GND#73 0.1U_0402_16V4Z VSSRHB VDDC#49
    N2 GND#133 GND#74 AN6 +1.8VS 2 1 VDDC#50 T15
    N21 AN8 BLM18PG121SN1D_0603 1 1 T17
    GND#134 GND#75 VDDC#51
    C1406

    C1407

    N23 AP11 PM@ T20


    GND#135 GND#76 VDDC#52
    N26 GND#136 GND#77 AP7 68mA PLL VDDC#53 T22
    N6 GND#137 GND#78 AP9 VDDC#54 T24
    R15 AR5 PM@ 2 PM@ 2 PCIE_PVDD AB37 T27 220 Ohm@100Mhz, 3A
    GND#138 GND#79 1U_0402_6.3V4Z PCIE_PVDD VDDC#55
    R17 GND#139 GND#80 AW34
    L94 MPV18
    ??mA VDDC#56 U16
    R2 GND#140 GND#81 B11 H7 NC_MPV18#1 VDDC#57 U18
    B R20 B13 2 1 0.1U_0402_16V4Z H8 U21 B
    GND#141 GND#82 BLM18PG121SN1D_0603 1 NC_MPV18#2 VDDC#58 L95
    R22 GND#142 GND#83 B15 1 VDDC#59 U23 2A
    C1408

    C1409

    R24 B17 PM@ ??mA U26 VDDC1 1U_0402_6.3V4Z 10U_0805_6.3V6M 2 1


    GND#143 GND#84 SPV18 VDDC#60 KC FBM-L11-201209-221LMAT_0805
    R27 GND#144 GND#85 B19 AM10 NC_SPV18 VDDC#61 V15
    R6 B21 120mA V17 1 1 1 PM@
    GND#145 GND#86 2 2 VDDC#62

    C1410

    C1411

    C1412
    T11 B23 SPV10 AN9 V20
    GND#146 GND#87 PM@ PM@ SPV10 VDDC#63
    T13 GND#147 GND#88 B25 VDDC#64 V22
    T16 B27 1U_0402_6.3V4Z AN10 V24
    GND#148 GND#89 SPVSS VDDC#65 PM@ 2 PM@ 2 PM@ 2
    T18 GND#149 GND#90 B29 VDDC#66 V27
    T21 GND#150 GND#91 B31 VDDC#67 Y16
    T23 B33 Y18 10U_0805_6.3V6M
    GND#151 GND#92 VDDC#68
    T26 GND#152 GND#93 B7 VDDC#69 Y21
    U15 B9 BACK BIAS Y23
    GND#153 GND#94 VDDC#70
    U17 GND#154 GND#95 C1 VDDC#71 Y26 CRB recommend 470 Ohm, 1A
    U2 GND#155 GND#96 C39 AA13 BBP#1 VDDC#72 Y28
    U20 E35 +BBP 0.1U_0402_16V4Z Y13 AH27
    GND#156 GND#97 BBP#2 VDDC#73
    U22 GND#157 GND#98 E5 1 1 VDDC#74 AH28
    C1413

    C1414

    U24 GND#158 GND#99 F11


    U27 F13 M15 L96 +1.8VS L97
    GND#159 GND#100 ISOLATED VDDCI#1 0.1U_0402_16V4Z PCIE_PVDD 0.1U_0402_16V4Z MPV18
    U6 GND#160 N13 +1.8VS 2 1 2 1
    V11 PM@ 2 PM@ 2 CORE I/O VDDCI#2 R12 BLM18PG121SN1D_0603 2 2 2 KC FBM-L11-201209-221LMAT_0805 1 1
    GND#161 VDDCI#3

    C1415

    C1416

    C1417

    C1418

    C1419
    V16 1U_0402_6.3V4Z T12 PM@ PM@
    GND#162 VDDCI#4
    V18 GND#163 +1.8VS OR +VGA_CORE @ 120mA +BBP
    V21 GND#164
    V23 PM@ 1 PM@ 1 PM@ 1 PM@ 2 PM@ 2
    GND#165 +VGA_CORE +BBP +1.8VS 216-0729042-00 A13 M96 BGA 962P 030 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    V26 GND#166
    W2 PM@
    GND#167 L98
    W6 GND#168
    1

    Y15 2 1 1 L99 +1.8VS L100


    GND#169 BLM18PG121SN1D_0603 C1420 R1240 0.1U_0402_16V4Z SPV10 0.1U_0402_16V4Z SPV18
    Y17 GND#170 +VGA_CORE 2 1 2 1
    Y20 @ BLM18PG121SN1D_0603 1 1
    GND#171

    C1424

    C1425
    Y22 A39 Q96 1U_0402_6.3V4Z 10_0402_5% KC FBM-L11-201209-221LMAT_0805 2 2 2 PM@
    GND#172 VSS_MECH#1 PM@ 2

    C1421

    C1422

    C1423
    Y24 AW1 Q95 PM@ VGA_GPIO21= 0V FOR BACK BIASING DISABLED PM@
    2

    GND#173 VSS_MECH#2
    S

    Y27 AW39 1 3 N FET A = OFF, P FET B = OFF, N FET C = ON


    D

    GND#174 VSS_MECH#3 PM@ 2 PM@ 2


    S

    A
    U13 GND#175 3 1 +BBP = +VGA_CORE A
    V13 SI2301BDS_SOT23 220 Ohm@100Mhz, 3A PM@ 1 PM@ 1 PM@ 1 1U_0402_6.3V4Z
    GND#176 SSM3K7002FU_SC70-3 PM@ +5VS
    G
    2

    PM@ VGA_GPIO21= +3.3V FOR BACK BIASING ENABLED CRB recommend 470 Ohm, 1A 10U_0603_6.3V6M 1U_0402_6.3V4Z
    G
    2

    216-0729042-00 A13 M96 BGA 962P 030


    PM@ 2 R1241 1
    N FET A = ON, P FET B = ON, N FET C = OFF (DNI For M96/M92)
    Q97 100K_0402_5% +BBP = +1.8VS
    10/22 Modify to NC by Vivian
    1

    D
    PM@
    VGA_GPIO21 2
    <17> VGA_GPIO21
    G
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2

    S
    3

    R1242 SSM3K7002FU_SC70-3 2008/07/15 2009/07/15 Title


    PM@
    Issued Date Deciphered Date
    10K_0402_5% M96 Power,GND
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PM@ Size Document Number Rev
    1

    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 19 of 56
    5 4 3 2 1
    5 4 3 2 1

    U45H
    D D
    DP C/D POWER DP A/B POWER

    AP20 NC_DPC_VDD18#1 NC_DPA_VDD18#1 AN24


    AP21 NC_DPC_VDD18#2 NC_DPA_VDD18#2 AP24

    200mA 200mA L103


    +1.1VS R1243 PM@ 0_0603_5% DPC_VDD10 AP13 AP31 DPA_VDD10 0.1U_0402_16V4Z 2 1 +1.1VS
    DPC_VDD10#1 DPA_VDD10#1 BLM18PG121SN1D_0603
    AT13 DPC_VDD10#2 DPA_VDD10#2 AP32 1 1 1

    C1430

    C1433

    C1431
    PM@

    AN17 DPC_VSSR#1 DPA_VSSR#1 AN27


    AP16 AP27 PM@ 2 PM@ 2 PM@ 2
    DPC_VSSR#2 DPA_VSSR#2 10U_0603_6.3V6M 1U_0402_6.3V4Z
    AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
    AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
    AW16 DPC_VSSR#5 DPA_VSSR#5 AW26

    AP22 NC_DPD_VDD18#1 NC_DPB_VDD18#1 AP25


    AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26

    200mA
    R1244 PM@ 0_0603_5% DPD_VDD10
    200mA
    +1.1VS AP14 DPD_VDD10#1 DPB_VDD10#1 AN33
    AP15 AP33 DPB_VDD10 R1245 0_0603_5% +1.1VS
    DPD_VDD10#2 DPB_VDD10#2 PM@

    AN19 DPD_VSSR#1 DPB_VSSR#1 AN29


    AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
    C C
    AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
    AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
    AW22 AW32 L106
    DPD_VSSR#5 DPB_VSSR#5 0.1U_0402_16V4Z 2 1 +1.8VS
    1 2 2 BLM18PG121SN1D_0603

    C1440

    C1441

    C1442
    R1246 R1247 150_0402_1% PM@
    2 1 AW18 DPCD_CALR DPAB_CALR AW28 1 2
    150_0402_1% PM@
    PM@ 20mA PM@ 2 PM@ 1 PM@ 1
    40mA DP E/F POWER DP PLL POWER 10U_0603_6.3V6M 1U_0402_6.3V4Z
    DPF_VDD18 AH34 AU28 DPA_PVDD
    DPE_VDD18#1 DPA_PVDD
    AJ34 DPE_VDD18#2 DPA_PVSS AV27
    0.1U_0402_16V4Z R1248 PM@ 0_0603_5%
    20mA 2

    C1444
    DPE_VDD10
    100mA DPB_PVDD
    AL33 DPE_VDD10#1 DPB_PVDD AV29
    AM33 DPE_VDD10#2 DPB_PVSS AR28
    L107 PM@ 1
    +1.1VS 2 1 0.1U_0402_16V4Z 20mA
    BLM18PG121SN1D_0603 1 1 1
    C1446

    C1447

    C1448

    PM@ AN34 AU18 DPC_PVDD


    DPE_VSSR#1 DPC_PVDD 0.1U_0402_16V4Z R1249 PM@ 0_0603_5%
    AP39 DPE_VSSR#2 DPC_PVSS AV17
    AR39 DPE_VSSR#3 1
    PM@ 2 PM@ 2 PM@ 2

    C1450
    10U_0603_6.3V6M 1U_0402_6.3V4Z
    AU37 DPE_VSSR#4 20mA
    AW35 DPE_VSSR#5
    +1.8VS AV19 DPD_PVDD
    L108 DPD_PVDD PM@ 2
    DPD_PVSS AR18
    R1250 0_0603_5% 2 1 0.1U_0402_16V4Z 200mA
    A13@ BLM18PG121SN1D_0603 1 1 1 DPF_VDD18 AF34 20mA
    DPF_VDD18#1
    C1452

    C1453

    C1454

    PM@ AG34 DPF_VDD18#2 DPE_PVDD R1251 PM@ 0_0603_5%


    DPE_PVDD AM37
    DPE_PVSS AN38 1
    B Q98 PM@ 2 PM@ 2 PM@ 2 100mA C1456 B
    10U_0603_6.3V6M 1U_0402_6.3V4Z DPE_VDD10 AK33 DPF_VDD10#1
    S

    0.1U_0402_16V4Z
    D

    3 1 AK34 DPF_VDD10#2 DPF_PVDD 2 PM@


    NC_DPF_PVDD AL38
    2

    SI2301BDS_SOT23 AM35
    R1252 A12@ NC_DPF_PVSS
    G
    2

    AF39 L109
    DPF_VSSR#1 0.1U_0402_16V4Z
    AH39 DPF_VSSR#2 2 1
    10K_0402_5% AK39 1 1 2 BLM18PG121SN1D_0603
    1

    DPF_VSSR#3

    C1457

    C1458

    C1459
    A12@ AL34 PM@
    GENERICB DPF_VSSR#4
    GENERICB <17> AM34 DPF_VSSR#5
    PM@ 2 PM@ 2 PM@ 1
    Issue for A12 R1253 10U_0603_6.3V6M 1U_0402_6.3V4Z
    2 1 AM39 L110
    DPEF_CALR
    2 1

    10U_0603_6.3V6M
    150_0402_1% BLM18PG121SN1D_0603

    1U_0402_6.3V4Z
    PM@ 216-0729042-00 A13 M96 BGA 962P 030 1 1 2 PM@

    C1546

    C1545
    PM@ C1460

    0.1U_0402_16V4Z
    PM@ 2 PM@ 2 PM@ 1

    There is no use on DPB/DPC/DPD,DPB_VDD10, DPC_VDD10,


    DPD_VDD10, DPB_PVDD, DPC_PVDD and DPD_PVDD can be
    A
    powered without filter A

    Security Classification Compal Secret Data Compal Electronics,Ltd.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    M96
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 20 of 56
    5 4 3 2 1
    5 4 3 2 1

    MAA[0..12]
    <18> MAA[0..12]
    BGA 84 ADR/CMND MAPPING

    G11

    G11
    D12

    D12
    B12

    P12

    B12

    P12
    T12

    T12
    L11

    L11
    G2

    G2
    D1
    D4
    D9

    D1
    D4
    D9
    B1
    B4
    B9

    P1
    P4
    P9

    B1
    B4
    B9

    P1
    P4
    P9
    T1
    T4
    T9

    T1
    T4
    T9
    L2

    L2
    WDQSA[0..7] U9 U8
    <18> WDQSA[0..7]
    DATA Bus

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    RDQSA[0..7]
    <18> RDQSA[0..7]

    <18> DQMA#[0..7]
    DQMA#[0..7] MAA0 K4
    Address 0..31 32..63
    MAA0 K4
    MAA1 A0 MDA21 MAA1 A0 MDA36
    H2 A1 DQ0 B2 CMD0 A4 H2 A1 DQ0 B2
    MDA[0..63] MAA2 K3 B3 MDA22 MAA2 K3 B3 MDA38
    <18> MDA[0..63] A2 DQ1 A2 DQ1
    MAA3 M4 C2 MDA20 CMD1 RAS* BA2 MAA3 M4 C2 MDA37
    A_BA[0..2] MAA4 A3 DQ2 MDA23 MAA4 A3 DQ2 MDA39
    <18> A_BA[0..2] K9 A4 DQ3 C3 K9 A4 DQ3 C3
    MAA5 H11 E2 MDA18 CMD2 A5 MAA5 H11 E2 MDA35
    MEM_RST MAA6 A5 DQ4 MDA19 MAA6 A5 DQ4 MDA33
    <18,22> MEM_RST K10 A6 DQ5 F3 K10 A6 DQ5 F3
    D
    MAA7 L9 F2 MDA17 CMD3 BA1 BA0 MAA7 L9 F2 MDA34 D
    MAA8 A7 DQ6 MDA16 MAA8 A7 DQ6 MDA32
    K11 A8/AP DQ7 G3 K11 A8/AP DQ7 G3
    MAA9 M9 B11 MDA11 CMD4 A6 MAA9 M9 B11 MDA48
    MAA10 A9 DQ8 MDA10 MAA10 A9 DQ8 MDA49
    K2 A10 DQ9 B10 K2 A10 DQ9 B10
    MAA11 L4 C11 MDA8 CMD5 A0 MAA11 L4 C11 MDA51
    A_BA0 A11 DQ10 MDA9 A_BA0 A11 DQ10 MDA50
    G4 BA0 DQ11 C10 G4 BA0 DQ11 C10
    A_BA1 G9 E11 MDA12 CMD6 A9 A_BA1 G9 E11 MDA52
    BA1 DQ12 MDA14 BA1 DQ12 MDA53
    DQ13 F10 DQ13 F10
    DQMA#2 E3 F11 MDA13 CMD7 CS1* CKE CS1* DQMA#4 E3 F11 MDA54
    DQMA#1 DM0 DQ14 MDA15 DQMA#6 DM0 DQ14 MDA55
    E10 DM1 DQ15 G10 E10 DM1 DQ15 G10
    +1.8VS DQMA#3 N10 M11 MDA29 CMD8 CS0* CAS* DQMA#7 N10 M11 MDA59
    DQMA#0 DM2 DQ16 MDA30 DQMA#5 DM2 DQ16 MDA58
    N3 DM3 DQ17 L10 N3 DM3 DQ17 L10
    N11 MDA28 CMD9 A11 A11 N11 MDA60
    RASA0# PM@ WDQSA2 DQ18 MDA27 WDQSA4 DQ18 MDA57
    <18> RASA0# D2 WDQS0 DQ19 M10 D2 WDQS0 DQ19 M10
    R1254 121_0402_1% WDQSA1 D11 R11 MDA31 CMD10 CAS* CS* WDQSA6 D11 R11 MDA61
    RASA1# PM@ WDQSA3 WDQS1 DQ20 MDA25 WDQSA7 WDQS1 DQ20 MDA56
    <18> RASA1# P11 WDQS2 DQ21 R10 P11 WDQS2 DQ21 R10
    R1255 121_0402_1% WDQSA0 P2 T11 MDA24 CMD11 WE* CKE* WDQSA5 P2 T11 MDA62
    WDQS3 DQ22 MDA26 WDQS3 DQ22 MDA63
    DQ23 T10 DQ23 T10
    CASA0# PM@ +VREFA0 H1 M2 MDA7 CMD12 BA0 BA1 +VREFA2 H1 M2 MDA47
    <18> CASA0# VREF DQ24 VREF DQ24
    R1256 121_0402_1% +VREFA1 H12 L3 MDA6 +VREFA3 H12 L3 MDA45
    CASA1# PM@ MAA12 VREF DQ25 MDA4 MAA12 VREF DQ25 MDA46
    <18> CASA1# J2 RFU1 DQ26 N2 CMD13 A1 J2 RFU1 DQ26 N2
    R1257 121_0402_1% CSA0#_1 J3 M3 MDA5 CSA1#_1 J3 M3 MDA44
    RFU2 DQ27 MDA2 RFU2 DQ27 MDA41
    DQ28 R2 CMD14 A12 A12 DQ28 R2
    WEA0# PM@ RASA0# H3 R3 MDA3 RASA1# H3 R3 MDA43
    <18> WEA0# RAS# DQ29 RAS# DQ29
    R1258 121_0402_1% CASA0# F4 T2 MDA1 CMD15 RST/ODT RST/ODT CASA1# F4 T2 MDA42
    WEA1# PM@ WEA0# CAS# DQ30 MDA0 WEA1# CAS# DQ30 MDA40
    <18> WEA1# H9 WE# DQ31 T3 H9 WE# DQ31 T3
    R1259 121_0402_1% CSA0#_0 F9 CMD16 A7 A7 CSA1#_0 F9
    CS# +1.8VS CS# +1.8VS
    CSA0#_0 PM@ CKEA0 H4 A1 CMD17 A10 A10 CKEA1 H4 A1
    <18> CSA0#_0 CKE VDDQ CKE VDDQ
    R1260 121_0402_1% CLKA0 J11 A12 CLKA1 J11 A12
    CSA1#_0 PM@ CLKA0# CK VDDQ CLKA1# CK VDDQ
    <18> CSA1#_0 J10 CK# VDDQ C1 CMD18 CKE WE# J10 CK# VDDQ C1
    R1261 121_0402_1% C4 C4
    VDDQ VDDQ
    1 PM@ 2 A4 ZQ VDDQ C9 FOR N10 CMD19 A0 A0 1 PM@ 2 A4 ZQ VDDQ C9
    CKEA0 PM@ R1262 243_0402_1% A9 C12 R1263 243_0402_1% A9 C12
    <18> CKEA0 MF VDDQ MF VDDQ
    R1264 121_0402_1% E1 CMD20 A9 A9 E1
    CKEA1 PM@ RDQSA2 VDDQ RDQSA4 VDDQ
    C <18> CKEA1 D3 RDQS0 VDDQ E4 D3 RDQS0 VDDQ E4 C
    R1265 121_0402_1% RDQSA1 D10 E9 CMD21 A6 A6 RDQSA6 D10 E9
    RDQSA3 RDQS1 VDDQ RDQSA7 RDQS1 VDDQ
    P10 RDQS2 VDDQ E12 P10 RDQS2 VDDQ E12
    CLKA0 2 PM@ 1 RDQSA0 P3 J4 CMD22 A2 RDQSA5 P3 J4
    <18> CLKA0 RDQS3 VDDQ RDQS3 VDDQ
    R1266 60.4_0402_5% J9 J9
    CLKA0# +1.8VS VDDQ +1.8VS VDDQ
    <18> CLKA0# 2 PM@ 1 A2 VDD VDDQ N1 CMD23 A8 A8 A2 VDD VDDQ N1
    R1267 64.4_0402_5% A11 N4 A11 N4
    VDD VDDQ VDD VDDQ
    F1 VDD VDDQ N9 CMD24 A3 F1 VDD VDDQ N9
    CLKA1 2 PM@ 1 F12 N12 F12 N12
    <18> CLKA1 VDD VDDQ VDD VDDQ
    R1268 60.4_0402_5% M1 R1 CMD25 A1 A1 M1 R1
    CLKA1# VDD VDDQ VDD VDDQ
    <18> CLKA1# 2 PM@ 1 M12 VDD VDDQ R4 M12 VDD VDDQ R4
    R1269 60.4_0402_5% V2 R9 CMD26 A13 A13 V2 R9
    VDD VDDQ VDD VDDQ
    V11 VDD VDDQ R12 V11 VDD VDDQ R12
    CSA0#_1 PM@ V1 CMD27 BA2 RAS# V1
    <18> CSA0#_1 VDDQ +1.8VS VDDQ +1.8VS
    R1270 121_0402_1% V4 V12 V4 V12
    CSA1#_1 PM@ MEM_RST SEN VDDQ PM@ L111 MEM_RST SEN VDDQ PM@ L112
    <18> CSA1#_1 V9 RESET CMD28 RFU0 RFU0 V9 RESET
    R1271 121_0402_1% A_BA2 H10 K1 1 2 A_BA2 H10 K1 1 2
    BA2 VDDA MBK1608121YZF_0603 BA2 VDDA MBK1608121YZF_0603
    VDDA K12 CMD29 RFU1 CS0* RFU1 VDDA K12
    L113 PM@ L114
    R121_0402_1% CIS download J1 VSSA 1 2 CMD30 RFU2 RFU2 J1 VSSA 1 2
    J12 MBK1608121YZF_0603 J12 MBK1608121YZF_0603
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS

    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSSA PM@ VSSA 120Ohm@100MHz, 600mA
    1 1 1 1
    X76_QIM@
    C1461 C1462 120Ohm@100MHz, 600mA
    MIRROR X76_QIM@
    C1463 C1464
    A3
    A10
    G1
    G12
    L1
    L12
    V3
    V10

    A3
    A10
    G1
    G12
    L1
    L12
    V3
    V10
    HYB18H1G321AF-11 0.1U_0402_16V4Z 0.1U_0402_16V4Z HYB18H1G321AF-11 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    PM@ 2 2 PM@ U8 PM@ 2 2 PM@
    CRB use BLM15BD1231SN1 P/N :SM010009U9L
    120Ohm@100MHz, 300mA
    U9
    CRB use BLM15BD1231SN1 P/N :SM010009U9L
    K4J10324QD-HC12 120Ohm@100MHz, 300mA
    X76_SAM@

    B B
    K4J10324QD-HC12 +1.8VS +1.8VS +1.8VS
    +1.8VS X76_SAM@
    10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    2

    2
    10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 1 1 1 1 1 1
    1 1 1 1 1 1 1 1 R1272 R1273
    C1473 C1474 C1475 C1476 C1477 C1478 C1479 C1480
    C1465 C1466 C1467 C1468 C1469 C1470 C1471 C1472 2.37K_0402_1% 2.37K_0402_1% PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
    PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ 2 2 2 2 2 2 2 2
    1

    1
    2 2 2 2 2 2 2 2 +VREFA1 +VREFA3 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    1 1
    C1481 R1274 C1482 R1275

    0.1U_0402_16V4Z 5.49K_0402_1% 0.1U_0402_16V4Z 5.49K_0402_1% +1.8VS


    +1.8VS 2 PM@ PM@ 2 PM@ PM@
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 1 1 1 1 1 1 1 1
    1 1 1 1 1 1 1 1
    C1491 C1492 C1493 C1494 C1495 C1496 C1497 C1498
    C1483 C1484 C1485 C1486 C1487 C1488 C1489 C1490 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
    PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ 2 2 2 2 2 2 2 2
    2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K +1.8VS +1.8VS
    2

    R1276 R1277

    2.37K_0402_1% 2.37K_0402_1%
    PM@ PM@
    1

    +VREFA0 +VREFA2
    +1.8VS
    1 1
    C1499 R1278 C1500 R1279
    A 1 A
    0.1U_0402_16V4Z 5.49K_0402_1% 0.1U_0402_16V4Z 5.49K_0402_1%
    + C21 2 PM@ PM@ 2 PM@ PM@

    220U_D2_4VM_R15
    2 @

    Security Classification Compal Secret Data Compal Electronics, Inc.


    10/22 Add C1554 and close to U8 and U9 Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    VRAM DDRA
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 21 of 56
    5 4 3 2 1
    5 4 3 2 1

    MAB[0..12]
    <18> MAB[0..12]

    G11

    G11
    D12

    D12
    B12

    P12

    B12

    P12
    T12

    T12
    L11

    L11
    BGA 84 ADR/CMND MAPPING

    G2

    G2
    D1
    D4
    D9

    D1
    D4
    D9
    B1
    B4
    B9

    P1
    P4
    P9

    B1
    B4
    B9

    P1
    P4
    P9
    T1
    T4
    T9

    T1
    T4
    T9
    L2

    L2
    WDQSB[0..7] U11 U10
    <18> WDQSB[0..7]

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ

    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    <18> RDQSB[0..7]
    RDQSB[0..7]
    DATA Bus
    <18> DQMB#[0..7]
    DQMB#[0..7] MAB0
    MAB1
    K4
    H2
    A0
    B2 MDB22 Address 0..31 32..63 MAB0
    MAB1
    K4
    H2
    A0
    B2 MDB41
    MDB[0..63] MAB2 A1 DQ0 MDB20 MAB2 A1 DQ0 MDB40
    <18> MDB[0..63] K3 A2 DQ1 B3 CMD0 A4 K3 A2 DQ1 B3
    MAB3 M4 C2 MDB19 MAB3 M4 C2 MDB42
    B_BA[0..2] MAB4 A3 DQ2 MDB21 MAB4 A3 DQ2 MDB43
    <18> B_BA[0..2] K9 A4 DQ3 C3 CMD1 RAS* BA2 K9 A4 DQ3 C3
    MAB5 H11 E2 MDB18 MAB5 H11 E2 MDB46
    MAB6 A5 DQ4 MDB23 MAB6 A5 DQ4 MDB45
    K10 A6 DQ5 F3 CMD2 A5 K10 A6 DQ5 F3
    MEM_RST MAB7 L9 F2 MDB16 MAB7 L9 F2 MDB47
    <18,21> MEM_RST A7 DQ6 A7 DQ6
    D
    MAB8 K11 G3 MDB17 CMD3 BA1 BA0 MAB8 K11 G3 MDB44 D
    MAB9 A8/AP DQ7 MDB11 MAB9 A8/AP DQ7 MDB49
    M9 A9 DQ8 B11 M9 A9 DQ8 B11
    MAB10 K2 B10 MDB10 CMD4 A6 MAB10 K2 B10 MDB48
    MAB11 A10 DQ9 MDB9 MAB11 A10 DQ9 MDB51
    L4 A11 DQ10 C11 L4 A11 DQ10 C11
    B_BA0 G4 C10 MDB8 CMD5 A0 B_BA0 G4 C10 MDB50
    B_BA1 BA0 DQ11 MDB12 B_BA1 BA0 DQ11 MDB52
    G9 BA1 DQ12 E11 G9 BA1 DQ12 E11
    F10 MDB13 CMD6 A9 F10 MDB53
    DQMB#2 DQ13 MDB14 DQMB#5 DQ13 MDB55
    E3 DM0 DQ14 F11 E3 DM0 DQ14 F11
    DQMB#1 E10 G10 MDB15 CMD7 CS1* CKE CS1* DQMB#6 E10 G10 MDB54
    +1.8VS DQMB#3 DM1 DQ15 MDB31 DQMB#7 DM1 DQ15 MDB58
    N10 DM2 DQ16 M11 N10 DM2 DQ16 M11
    DQMB#0 N3 L10 MDB28 CMD8 CS0* CAS* DQMB#4 N3 L10 MDB57
    DM3 DQ17 MDB30 DM3 DQ17 MDB60
    DQ18 N11 DQ18 N11
    RASB0# PM@ WDQSB2 D2 M10 MDB27 CMD9 A11 A11 WDQSB5 D2 M10 MDB56
    <18> RASB0# WDQS0 DQ19 WDQS0 DQ19
    R1280 121_0402_1% WDQSB1 D11 R11 MDB29 WDQSB6 D11 R11 MDB61
    RASB1# PM@ WDQSB3 WDQS1 DQ20 MDB25 WDQSB7 WDQS1 DQ20 MDB59
    <18> RASB1# P11 WDQS2 DQ21 R10 CMD10 CAS* CS* P11 WDQS2 DQ21 R10
    R1281 121_0402_1% WDQSB0 P2 T11 MDB24 WDQSB4 P2 T11 MDB62
    WDQS3 DQ22 MDB26 WDQS3 DQ22 MDB63
    DQ23 T10 CMD11 WE* CKE* DQ23 T10
    CASB0# PM@ +VREFB0 H1 M2 MDB6 +VREFB2 H1 M2 MDB36
    <18> CASB0# VREF DQ24 VREF DQ24
    R1282 121_0402_1% +VREFB1 H12 L3 MDB7 CMD12 BA0 BA1 +VREFB3 H12 L3 MDB37
    CASB1# PM@ MAB12 VREF DQ25 MDB5 MAB12 VREF DQ25 MDB39
    <18> CASB1# J2 RFU1 DQ26 N2 J2 RFU1 DQ26 N2
    R1283 121_0402_1% CSB0#_1 J3 M3 MDB4 CMD13 A1 CSB1#_1 J3 M3 MDB38
    RFU2 DQ27 MDB0 RFU2 DQ27 MDB35
    DQ28 R2 DQ28 R2
    WEB0# PM@ RASB0# H3 R3 MDB3 CMD14 A12 A12 RASB1# H3 R3 MDB34
    <18> WEB0# RAS# DQ29 RAS# DQ29
    R1284 121_0402_1% CASB0# F4 T2 MDB1 CASB1# F4 T2 MDB33
    WEB1# PM@ WEB0# CAS# DQ30 MDB2 WEB1# CAS# DQ30 MDB32
    <18> WEB1# H9 WE# DQ31 T3 CMD15 RST/ODT RST/ODT H9 WE# DQ31 T3
    R1285 121_0402_1% CSB0#_0 F9 CSB1#_0 F9
    CS# +1.8VS CS# +1.8VS
    CMD16 A7 A7
    CSB0#_0 PM@ CKEB0 H4 A1 CKEB1 H4 A1
    <18> CSB0#_0 CKE VDDQ CKE VDDQ
    R1286 121_0402_1% CLKB0 J11 A12 CMD17 A10 A10 CLKB1 J11 A12
    CSB1#_0 PM@ CLKB0# CK VDDQ CLKB1# CK VDDQ
    <18> CSB1#_0 J10 CK# VDDQ C1 J10 CK# VDDQ C1
    R1287 121_0402_1% C4 CMD18 CKE WE# C4
    VDDQ VDDQ
    1 PM@ 2 A4 ZQ VDDQ C9 1 PM@ 2 A4 ZQ VDDQ C9
    CKEB0 PM@ R1288 243_0402_1% A9 C12 FOR N10 CMD19 A0 A0 R1289 243_0402_1% A9 C12
    <18> CKEB0 MF VDDQ MF VDDQ
    R1290 121_0402_1% E1 E1
    CKEB1 PM@ RDQSB2 VDDQ RDQSB5 VDDQ
    <18> CKEB1 D3 RDQS0 VDDQ E4 CMD20 A9 A9 D3 RDQS0 VDDQ E4
    C R1291 121_0402_1% RDQSB1 D10 E9 RDQSB6 D10 E9 C
    RDQSB3 RDQS1 VDDQ RDQSB7 RDQS1 VDDQ
    P10 RDQS2 VDDQ E12 CMD21 A6 A6 P10 RDQS2 VDDQ E12
    CLKB0 2 PM@ 1 RDQSB0 P3 J4 RDQSB4 P3 J4
    <18> CLKB0 RDQS3 VDDQ RDQS3 VDDQ
    R1292 60.4_0402_5% J9 CMD22 A2 J9
    CLKB0# +1.8VS VDDQ +1.8VS VDDQ
    <18> CLKB0# 2 PM@ 1 A2 VDD VDDQ N1 A2 VDD VDDQ N1
    R1293 60.4_0402_5% A11 N4 CMD23 A8 A8 A11 N4
    VDD VDDQ VDD VDDQ
    F1 VDD VDDQ N9 F1 VDD VDDQ N9
    CLKB1 2 PM@ 1 F12 N12 CMD24 A3 F12 N12
    <18> CLKB1 VDD VDDQ VDD VDDQ
    R1294 60.4_0402_5% M1 R1 M1 R1
    CLKB1# VDD VDDQ VDD VDDQ
    <18> CLKB1# 2 PM@ 1 CRB recommend 60.4 ohm M12 VDD VDDQ R4 CMD25 A1 A1 M12 VDD VDDQ R4
    R1295 60.4_0402_5% V2 R9 V2 R9
    VDD VDDQ VDD VDDQ
    V11 VDD VDDQ R12 CMD26 A13 A13 V11 VDD VDDQ R12
    CSB0#_1 PM@ V1 V1
    <18> CSB0#_1 VDDQ +1.8VS VDDQ
    R1296 121_0402_1% V4 V12 CMD27 BA2 RAS# V4 V12
    CSB1#_1 PM@ MEM_RST SEN VDDQ PM@ L115 MEM_RST SEN VDDQ PM@ L116 +1.8VS
    <18> CSB1#_1 V9 RESET V9 RESET
    R1297 121_0402_1% B_BA2 H10 K1 1 2 CMD28 RFU0 RFU0 B_BA2 H10 K1 1 2
    BA2 VDDA MBK1608121YZF_0603 BA2 VDDA MBK1608121YZF_0603
    VDDA K12 VDDA K12
    L117 CMD29 RFU1 CS0* RFU1 PM@ L118
    R121_0402_1% CIS download J1 VSSA 1 2
    MBK1608121YZF_0603
    J1 VSSA 1 2
    MBK1608121YZF_0603
    J12 CMD30 RFU2 RFU2 J12
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS

    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    VSSA PM@ 120Ohm@100MHz, 600mA VSSA 120Ohm@100MHz, 600mA
    1 1 1 1
    C1501 C1502 C1503 C1504
    X76_QIM@
    MIRROR X76_QIM@
    A3
    A10
    G1
    G12
    L1
    L12
    V3
    V10

    A3
    A10
    G1
    G12
    L1
    L12
    V3
    V10
    HYB18H1G321AF-11 0.1U_0402_16V4Z 0.1U_0402_16V4Z HYB18H1G321AF-11 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    PM@ 2 2 PM@ PM@ 2 2 PM@

    CRB use BLM15BD1231SN1 P/N :SM010009U9L U10

    120Ohm@100MHz, 300mA
    U11 CRB use BLM15BD1231SN1 P/N :SM010009U9L
    120Ohm@100MHz, 300mA
    K4J10324QD-HC12
    X76_SAM@
    +1.8VS +1.8VS
    B K4J10324QD-HC12 B
    X76_SAM@
    2

    2
    +1.8VS
    R1298 R1299
    10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    +1.8VS 2.37K_0402_1% 2.37K_0402_1%
    PM@ 1 1 1 1 1 1 1 1 1 1
    PM@
    1

    1
    10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z +VREFB1 +VREFB3 C1505 C1506 C1507 C1508 C1509 C1510 C1511 C1512 C1513 C1514
    1 1 1 1 1 1 1 1 1 1 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
    2 2 2 2 2 2 2 2 2 2
    1 1
    C1515 C1516 C1517 C1518 C1519 C1520 C1521 C1522 C1524 C1525 C1523 R1300 C1526 R1301 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
    2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 5.49K_0402_1% 0.1U_0402_16V4Z 5.49K_0402_1%
    10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 PM@ PM@ 2 PM@ PM@

    +1.8VS

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K


    +1.8VS
    1 1 1 1 1 1 1 1
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K C1527 C1528 C1529 C1530 C1531 C1532 C1533 C1534
    +1.8VS +1.8VS PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
    1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2
    C1535 C1536 C1537 C1538 C1539 C1540 C1541 C1542 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
    2

    PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@


    2 2 2 2 2 2 2 2 R1302 R1303
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
    2.37K_0402_1% 2.37K_0402_1%
    PM@ PM@
    1

    +VREFB0 +VREFB2

    1 1
    C1543 R1304 C1544 R1305

    +1.8VS 0.1U_0402_16V4Z 5.49K_0402_1% 0.1U_0402_16V4Z 5.49K_0402_1%


    2 PM@ PM@ 2 PM@ PM@
    A A

    1
    + C22

    220U_D2_4VM_R15
    2 @

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    10/22 Add C1555 and close to U10 and U11 VRAM DDRA
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 22 of 56
    5 4 3 2 1
    5 4 3 2 1

    +3VSM_CK505 +3VS
    FSC FSB FSA CPU SRC PCI REF DOT_96 USB
    CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS R178 1 2 0_0805_5%
    1 1 1 1 1 1 1

    0 0 0 266 100 33.3 14.318 96.0 48.0 C441 C442 C443 C444 C445 C446 C447 R235 1 2 0_0402_5%
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ R179 R180
    2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
    0 0 1 133 100 33.3 14.318 96.0 48.0 2N7002DW-T/R7_SOT363-6
    +1.5VS R181 1 2 @ 0_0805_5% <29,35,36> ICH_SMBDATA 6 1 CLK_SMBDATA
    +VDD_CK505
    0 1 0 200 100 33.3 14.318 96.0 48.0 Q1A
    +VCCP R182 1 2 0_0805_5%

    2
    1 1 1 1 1 1 1 +3VS
    D D
    0 1 1 166 100 33.3 14.318 96.0 48.0

    5
    C448 C449 C450 C451 C452 C453 C454
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Q1B
    2 2 2 2 2 2 2 CLK_SMBCLK
    1 0 0 333 100 33.3 14.318 96.0 48.0 <29,35,36> ICH_SMBCLK 3 4

    2N7002DW-T/R7_SOT363-6
    1 0 1 100 100 33.3 14.318 96.0 48.0
    *SA000020H10 (ICS : ICS9LPRS387BKLFT) R234 1
    @
    2 0_0402_5%

    1 1 0 400 100 33.3 14.318 96.0 48.0 SA000020K00 (Silego : SLG8SP556VTR )


    +3VSM_CK505 U16
    1 1 1 Reserved 9 CLK_SMBDATA
    SDA CLK_SMBDATA <14,15>
    55 VDD_SRC
    10 CLK_SMBCLK
    SCL CLK_SMBCLK <14,15>
    6 VDD_REF
    +VCCP 12 71 CLK_CPU_BCLK
    VDD_PCI CPU_0 CLK_CPU_BCLK <5>
    72 70 CLK_CPU_BCLK#
    VDD_CPU CPU_0# CLK_CPU_BCLK# <5>
    2

    @ 19 68 CLK_MCH_BCLK
    R183 VDD_48 CPU_1 CLK_MCH_BCLK <8>
    56_0402_5% 27 67 CLK_MCH_BCLK#
    +VDD_CK505 VDD_PLL3 CPU_1# CLK_MCH_BCLK# <8>
    1

    FSA R184 2 1 2.2K_0402_5% R185 1 2 1K_0402_5% MCH_CLKSEL0 <8> R_CLK_DOT R186 GM@ 0_0402_5%
    66 VDD_CPU_IO SRC_0/DOT_96 24 1 2 CLK_MCH_DREFCLK <8>
    R187 1 2 0_0402_5% R188 1 2 PM@ 0_0402_5%
    <6> CPU_BSEL0 CLK_PCIE_VGA <16>
    C1224 31 25 R_CLK_DOT# R189 1 2 GM@ 0_0402_5%
    VDD_PLL3_IO SRC_0#/DOT_96# CLK_MCH_DREFCLK# <8>
    1

    CLK_ICH_48M R191 1 2 PM@ 0_0402_5%


    @ <EMI> @ 33P_0402_50V8J CLK_PCIE_VGA# <16>
    62 VDD_SRC_IO
    C R190 28 C
    1K_0402_5% C1225 LCDCLK/27M MCH_SSCDREFCLK <8>
    52 VDD_SRC_IO
    CLK_ICH_14M 29
    SRC PORT LIST
    2

    <EMI> @ 33P_0402_50V8J LCDCLK#/27M_SS MCH_SSCDREFCLK# <8>


    23 VDD_IO
    38 VDD_SRC_IO SRC_2 32 CLK_MCH_3GPLL
    CLK_MCH_3GPLL <8> PORT DEVICE
    +VCCP 33 CLK_MCH_3GPLL#
    SRC_2# CLK_MCH_3GPLL# <8>
    R193 1 2 33_0402_5% FSA 20
    SRC0 MCH_DREFCLK
    <29> CLK_ICH_48M USB_0/FS_A
    1

    CLK_PCIE_EXP
    @ FSB 2
    SRC_3 35 CLK_PCIE_EXP <36> SRC2 MCH_3GPLL
    R194 FS_B/TEST_MODE CLK_PCIE_EXP#
    1K_0402_5%
    <29> CLK_ICH_14M
    R195 1 2 33_0402_5% FSC 7
    SRC_3# 36 CLK_PCIE_EXP# <36> SRC3 PCIE_EXP#
    REF_0/FS_C/TEST_
    SRC4 PCIE_CARD
    2

    FSB R196 1 2 1K_0402_5% 8 39 CLK_PCIE_CARD


    MCH_CLKSEL1 <8> REF_1 SRC_4 CLK_PCIE_CARD <32>

    <6> CPU_BSEL1
    R198 1 2 0_0402_5% 40 CLK_PCIE_CARD# SRC6 PCIE_WLAN
    CK_PWRGD SRC_4# CLK_PCIE_CARD# <32>
    <29> CK_PWRGD 1 CKPWRGD/PD# SRC7 PCIE_3G
    1

    @ CLK_PCIE_WLAN
    R199
    11 NC SRC_6 57 CLK_PCIE_WLAN <35> SRC8
    0_0402_5% CLK_PCIE_WLAN#
    SRC_6# 56 CLK_PCIE_WLAN# <35> SRC9 PCIE_LAN
    2

    PM_STP_CPU#
    <29> PM_STP_CPU# 53 CPU_STOP#
    61 CLK_PCIE_3G SRC10 PCIE_ICH
    PM_STP_PCI# SRC_7 CLK_PCIE_3G <35>
    <29> PM_STP_PCI# 54 PCI_STOP#
    60 CLK_PCIE_3G# SRC11 PCIE_SATA
    +VCCP SRC_7# CLK_PCIE_3G# <35>
    CLK_XTAL_IN 5 XTAL_IN
    SRC_8/CPU_ITP 64
    1

    CLK_XTAL_OUT 4 +3VS
    B @ XTAL_OUT B
    SRC_8#/CPU_ITP# 63
    R200 SATA_CLKREQ#_R R201 2 1 10K_0402_5%
    1K_0402_5% EXP_CLKREQ# R202 2 1 10K_0402_5%
    R802 1 2 33_0402_5% PCI_EC 13 44 CLK_PCIE_LAN 3G_CLKREQ# R203 2 1 10K_0402_5%
    <37> CLK_PCI_EC
    2

    FSC R204 1 PCI_1 SRC_9 CLK_PCIE_LAN <33> MCH_CLKREQ#_R


    2 10K_0402_5% R205 1 2 1K_0402_5% MCH_CLKSEL2 <8>
    R206 2 1 10K_0402_5%
    R207 1 2 33_0402_5% PCI2_TME 14 45 CLK_PCIE_LAN# LAN_CLKREQ# R208 2 1 10K_0402_5%
    <40> CLK_PCI_DB PCI_2 SRC_9# CLK_PCIE_LAN# <33>
    R209 1 2 0_0402_5% @ WLAN_CLKREQ# R210 2 1 10K_0402_5%
    <6> CPU_BSEL2
    15 PCI_3
    1

    50 CLK_PCIE_ICH
    SRC_10 CLK_PCIE_ICH <29>
    <BOM Structure> @
    R212
    <45> CLK_PCI_TPM
    R213 1 2 33_0402_5% PCI4_SEL 16 PCI_4/SEL_LCDCL
    51 CLK_PCIE_ICH# REQ PORT LIST
    0_0402_5% R214 1 33_0402_5% ITP_EN SRC_10# CLK_PCIE_ICH# <29>
    <27> CLK_PCI_ICH 2 17 PCIF_5/ITP_EN
    PORT DEVICE
    2

    48 CLK_PCIE_SATA
    SRC_11 CLK_PCIE_SATA <28>
    18 VSS_PCI SRC_11# 47 CLK_PCIE_SATA#
    CLK_PCIE_SATA# <28> REQ_3# PCIE_EXP#
    EMI C1226
    3 VSS_REF REQ_4#
    +3VS +3VS +3VS CLK_PCI_EC EXP_CLKREQ#
    <EMI> @ 33P_0402_50V8J
    22 VSS_48 CLKREQ_3# 37 EXP_CLKREQ# <36> REQ_6# PCIE_WLAN
    C1227 26 VSS_IO CLKREQ_4# 41 REQ_7# PCIE_3G
    1

    CLK_PCI_DB
    @ PM@ <EMI> @ 33P_0402_50V8J WLAN_CLKREQ#
    R215 R216 R217 C1228
    69 VSS_CPU CLKREQ_6# 58 WLAN_CLKREQ# <35> REQ_9# PCIE_LAN
    10K_0402_5% 10K_0402_5% 10K_0402_5% CLK_PCI_TPM 3G_CLKREQ#
    <EMI> @ 33P_0402_50V8J
    30 VSS_PLL3 CLKREQ_7# 65 3G_CLKREQ# <35> REQ_10#
    2

    ITP_EN PCI4_SEL PCI2_TME C455 22P_0402_50V8J CLK_XTAL_IN C1229 LAN_CLKREQ#


    CLK_PCI_ICH
    34 VSS_SRC CLKREQ_9# 43 LAN_CLKREQ# <33> REQ_11# PCIE_SATA
    1

    <EMI> @ 33P_0402_50V8J
    GM@ @ Y2
    59 VSS_SRC SLKREQ_10# 49 REQ_A# MCH_3GPLL
    R218 R219 R220 14.31818MHZ_16PF_DSX840GA 42 46 SATA_CLKREQ#_R R221 1 2 0_0402_5%
    A VSS_SRC CLKREQ_11# SATA_CLKREQ# <29> A
    10K_0402_5% 10K_0402_5% 10K_0402_5%
    2

    C456 22P_0402_50V8J CLK_XTAL_OUT 73 21 MCH_CLKREQ#_R R222 1 2 0_0402_5% MCH_CLKREQ# <8>


    2

    VSS USB_1/CLKREQ_A#

    Routing the trace at least 10mil ICS9LPRS387AKLFT_MLF72_10x10

    For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#


    For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
    Security Classification Compal Secret Data Compal Electronics,Ltd.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Pin28/29 : LCDCLK / LCDCLK#
    1 = Pin24/25 : SRC_0 / SRC_0#
    Clock Generator CK505
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    Pin28/29 : 27M/27M_SS AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    5 4 3 2 Date: Monday, January 19, 2009 1 Sheet 23 of 56
    5 4 3 2 1

    D D

    +5VS +5VS

    3 3

    1 HDMIDAT_R 1 HDMICLK_R C461 1 2 PM@ 0.1U_0402_16V7K HDMI_CLK-


    <17> VGA_HDMI_CLK-
    C462 1 2 PM@ 0.1U_0402_16V7K HDMI_CLK+
    <17> VGA_HDMI_CLK+
    2 @ 2 @
    D7 D8 C463 1 2 PM@ 0.1U_0402_16V7K HDMI_TX0-
    <17> VGA_HDMI_TX0-
    BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 C464 1 2 PM@ 0.1U_0402_16V7K HDMI_TX0+
    <17> VGA_HDMI_TX0+
    C C465 1 2 PM@ 0.1U_0402_16V7K HDMI_TX1- C
    <17> VGA_HDMI_TX1-
    C466 1 2 PM@ 0.1U_0402_16V7K HDMI_TX1+
    <17> VGA_HDMI_TX1+
    C467 1 2 PM@ 0.1U_0402_16V7K HDMI_TX2-
    <17> VGA_HDMI_TX2-
    C468 1 2 PM@ 0.1U_0402_16V7K HDMI_TX2+
    <17> VGA_HDMI_TX2+
    +3VS
    +3VS

    1
    TMDS pull down (500ohm) resistors G9x only R1160 R1161
    2.2K_0402_5% 2.2K_0402_5%

    2
    HDMI_CLK+_CONN 1 2 @ @ 2N7002DW-T/R7_SOT363-6
    R236 PM@ 499_0402_1%

    2
    HDMI_CLK-_CONN HDMIDAT_R
    R237
    1 2
    PM@ 499_0402_1%
    9/14 Modify for <17> VGA_HDMI_SDA
    PM@
    1 6

    5
    HDMI_TX0+_CONN 1 2 UMA used Q5A
    R238 PM@ 499_0402_1%
    HDMI_TX0-_CONN 1 2 <17> VGA_HDMI_SCL 4 3 HDMICLK_R
    R239 PM@ 499_0402_1%
    HDMI_TX1+_CONN 1 2 2N7002DW-T/R7_SOT363-6 Q5B PM@ 1 1
    R240 PM@ 499_0402_1%
    1

    HDMI_TX1-_CONN D NV@ 2 R1166


    1 2 1 0_0402_5% +3VS C469 C470
    R241 PM@ 499_0402_1% 2 2 1 0_0402_5% +5VS @ @
    +5VS 2 2 12P_0402_50V8J
    HDMI_TX2+_CONN 1 2 G ATI@ R1168 12P_0402_50V8J
    R242 PM@ 499_0402_1% S PM@
    3

    HDMI_TX2-_CONN 1 2 Q2
    R243 PM@ 499_0402_1% RB491D_SC59-3
    2N7002W-T/R7_SOT323-3 0_0805_5%
    B
    NEAR CONNECT D4
    R1167 @
    B
    WCM-2012-900T_4P 9/14 Reserve for VGA 2 1 CHECK
    HDMI_CLK+ 4 4 3 3 HDMI_CLK+_CONN used;check pin name +VCC_HDMI 1 2 +5VS_HDMI
    R244 @ 1
    0_0805_5% F2
    HDMI_CLK- 1 2 HDMI_CLK-_CONN +5VS_HDMI 1.1A_6VDC_FUSE C471
    1 2 0.1U_0402_16V4Z

    1
    L17 2
    +5VS R245 R246
    WCM-2012-900T_4P 2.2K_0402_5% 2.2K_0402_5% JHDMI1
    HDMI_TX0+ 4 3 HDMI_TX0+_CONN HP_DET 19
    4 3 HP_DET
    18

    2
    +5V

    2
    17 DDC/CEC_GND
    HDMI_TX0- 1 2 HDMI_TX0-_CONN +3VS_DELAY HDMIDAT_R 16
    1 2 HDMICLK_R SDA
    15 SCL
    L18 14
    D5 Reserved
    13 CEC
    WCM-2012-900T_4P @ BAT54S-7-F_SOT23-3 HDMI_CLK-_CONN 12 20

    1
    CK- GND
    1

    HDMI_TX1+ 4 3 HDMI_TX1+_CONN C 11 21
    4 3 Q4 CK_shield GND
    2 1 R1169 2 HP_DET HDMI_CLK+_CONN 10 CK+ GND 22
    MMBT3904_SOT23-3 B 150K_0402_5% HDMI_TX0-_CONN 9 23
    HDMI_TX1- HDMI_TX1-_CONN ATI@ E ATI@ 1 D0- GND
    1 2 8
    3

    1 2 HDMI_DETECT_VGA2 R125 R1171 HDMI_TX0+_CONN D0_shield


    <17> HDMI_DETECT_VGA 1 7 D0+
    L20 ATI@ 0_0402_5% @ 340K_0402_1% HDMI_TX1-_CONN 6 D1-
    2

    5 D1_shield
    WCM-2012-900T_4P R1314 HDMI_TX1+_CONN 4
    2

    HDMI_TX2+ HDMI_TX2+_CONN HDMI_TX2-_CONN D1+


    4 4 3 3 10K_0402_5% 3 D2-
    2 D2_shield
    HDMI_TX2+_CONN 1
    1

    A D2+ A
    HDMI_TX2- 1 2 HDMI_TX2-_CONN
    1 2 TYCO_1775040-6
    L21 12/17 Change foorptint of JHDMI1 to SUYIN_100042MR019S153ZL_19P-T CONN@

    HDMI_CLK+ @ R251 1 2 0_0402_5% HDMI_CLK+_CONN


    HDMI_CLK- @ R252 1 2 0_0402_5% HDMI_CLK-_CONN
    HDMI_TX0+ @ R253 1 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics,Ltd.
    HDMI_TX0- @ R254 1 2 0_0402_5% HDMI_TX0-_CONN 2008/07/15 2009/07/15 Title
    HDMI_TX1+ @ R255 0_0402_5% HDMI_TX1+_CONN
    Issued Date Deciphered Date
    HDMI_TX1- @ R256
    1
    1
    2
    2 0_0402_5% HDMI_TX1-_CONN Level Shiftter_PS8101T
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDMI_TX2+ @ R257 1 2 0_0402_5% HDMI_TX2+_CONN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    HDMI_TX2- @ R258 0_0402_5% HDMI_TX2-_CONN Custom 1.0
    1 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 24 of 56
    5 4 3 2 1
    5 4 3 2 1

    10/31 Add +3VS

    LCD POWER CIRCUIT BKOFF# C1649 2 1 100P_0402_50V8J

    1
    +3VALW +3VS INVT_PWM
    +LCDVDD R259
    W=60mils DAC_BRIG
    4.7K_0402_5%
    D9

    1
    1 DISPOFF#

    2
    1
    R1153 2 C1230 BKOFF# 1 2 DISPOFF#
    <37> BKOFF#
    300_0603_5% R1154 C1231
    100K_0402_5% 4.7U_0805_10V4Z CH751H-40PT_SOD323-2 1 1 1 @
    0.1U_0402_10V7K 2 ENBKL C475 C476 C477
    <10> GMCH_ENBKL 2 1

    1 2
    1 R260 GM@ 0_0402_5% ENBKL <37>

    3
    D S
    470P_0402_50V7K
    <17> VGA_ENBKL 2 1

    2
    Q90
    G
    Q91 R261 PM@ 0_0402_5% 2 2 2
    2 2 1 2
    D SSM3K7002FU_SC70-3 G R1155 100K_0402_5% SI2301BDS_SOT23 R262 470P_0402_50V7K 470P_0402_50V7K D
    S 100K_0402_1%

    3
    D

    1
    1
    GM@ D +LCDVDD change from 10K to 100K
    R1156 1 2 0_0402_5% Q92 5/8 by checklist For EMI
    <10> GM_ENVDD
    PM@
    2
    G SSM3K7002FU_SC70-3
    W=60mils
    <16> VGA_ENVDD R1157 1 2 0_0402_5% S

    3
    1
    @
    1
    C1232
    1
    C1233 CHECK
    R1158
    100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
    2 2

    Change PCB footprint of L22 from L_0805 to R_0805

    +LEDVDD

    C C

    Change PCB footprint of L37 from L_0805 to R_0805


    Change PCB footprint of L23 from L_0805 to R_0805
    VGA LCD/PANEL BD. Conn. +LEDVDD
    JLVDS2
    +LCDVDD 1 2 +LEDVDD
    L24 +LCDVDD_CONN 1 2 L37
    (60 MIL)
    3 3 4 4 +LCDVDD_CONN 400mA
    2 1 5 5 6 6 2 1 B+
    +3VS FBMA-L11-201209-221LMA30T_0805 7 8 +3VS
    7 8 VGA_LVDS_B2#
    9 9 10 10 VGA_LVDS_B2# <16> 1
    11 12 VGA_LVDS_B2 FBMA-L11-201209-221LMA30T_0805
    11 12 VGA_LVDS_B2 <16>
    13 14 VGA_LVDS_BCLK# C364
    @ <37> INVT_PWM 13 14 VGA_LVDS_BCLK# <16>
    1 DISPOFF# 15 16 VGA_LVDS_BCLK 4.7U_0805_25V6-K
    680P_0402_50V7K 15 16 VGA_LVDS_BCLK <16> 2
    17 18 VGA_LVDS_B1#
    C836 <37> DAC_BRIG 17 18 VGA_LVDS_B1# <16>
    19 20 VGA_LVDS_B1
    19 20 VGA_LVDS_B1 <16>
    21 22 VGA_LVDS_A0#
    2 21 22 VGA_LVDS_A0# <16>
    23 24 VGA_LVDS_A0
    23 24 VGA_LVDS_A0 <16>
    25 26 VGA_LVDS_B0
    25 26 VGA_LVDS_B0 <16>
    27 28 VGA_LVDS_B0#
    27 28 VGA_LVDS_B0# <16>
    29 30 VGA_LVDS_A1
    29 30 VGA_LVDS_A1 <16>
    31 32 VGA_LVDS_A1#
    31 32 VGA_LVDS_A1# <16>
    33 34 VGA_LVDS_A2#
    33 34 VGA_LVDS_A2# <16>
    35 36 VGA_LVDS_A2
    35 36 VGA_LVDS_A2 <16>
    <17> VGA_LVDS_SCL VGA_LVDS_SCL 37 38 VGA_LVDS_ACLK#
    37 38 VGA_LVDS_ACLK# <16>
    <17> VGA_LVDS_SDA VGA_LVDS_SDA 39 40 VGA_LVDS_ACLK
    39 40 VGA_LVDS_ACLK <16>
    41 GND GND 42

    ACES_87142-4041
    B CONN@ B

    C484
    +LCDVDD_CONN 1 2
    0.1U_0402_16V4Z @ <EMI>

    Plac C484 close to JLVDS2

    C482
    2 1 +LCDVDD_CONN
    <EMI> @ 0.1U_0402_16V4Z
    C483
    2 1 +3VS
    <EMI> @ 0.1U_0402_16V4Z

    Place C483 and C482 close to JLVDS3


    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    LVDS & DVI Connector
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 25 of 56
    5 4 3 2 1
    A B C D E

    +5VS

    Checklist recommend: 2-pole filter on R/G/B signals


    CRT Connector C-L-C-L-C D11 D12 D13
    Change PCB footprint of L43 from L_0805 to R_0805

    2
    @ @ @
    DAN217_SC59 DAN217_SC59 DAN217_SC59 L43
    10p - 47 Ohm/100MHz - 22p - 47 Ohm/100MHz - 10p KC FBM-L11-201209-221LMAT_0805

    1
    +R_CRT_VCC +CRT_VCC
    W=40mils
    12/15 Modified. Note L26~L30 are 0 Ohm resisters

    1
    D14 F1 W=40mils
    +L_CRT_VCC 2
    (IFTXX) 1 1 2

    3
    RB491D_SC59-3 1.1A_6VDC_FUSE
    +3VS 1
    1 1
    Place closed to chipset Change PCB footprint of L45/ L47/ L49 from L_0603 to R_0603
    C892
    0.1U_0402_16V4Z
    2
    R803 1 2 PM@ 0_0402_5% VGA_CRT_R1 CRT_R_1 L45 1 2 CRT_R_2 JCRT1
    <17> VGA_CRT_R
    R804 1 2 GM@ 0_0402_5% L44 0_0603_5% FBMA-L10-160808-800LMT_0603 6
    <10> GMCH_CRT_R
    11
    R805 1 2 PM@ 0_0402_5% VGA_CRT_G1 CRT_G_1 L47 1 2 CRT_G_2 1
    <17> VGA_CRT_G
    R806 1 2 GM@ 0_0402_5% L46 0_0603_5% FBMA-L10-160808-800LMT_0603 7
    <10> GMCH_CRT_G
    12
    R807 1 2 PM@ 0_0402_5% VGA_CRT_B1 CRT_B_1 L49 1 2 CRT_B_2 2
    <17> VGA_CRT_B
    R808 1 2 GM@ 0_0402_5% L48 0_0603_5% FBMA-L10-160808-800LMT_0603 8
    <10> GMCH_CRT_B

    1
    13

    1
    R809 R810 1 1 1 1 1 1 3
    R811 C893 C894 C895 C896 C898 C899 1 1 1 9
    @ @ @ 14
    150_0402_1% C897 C900 C901 4

    2
    2 2 2 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10 16

    2
    150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 2 2 2
    15 17
    150_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 5
    10P_0402_50V8J
    SUYIN_070546FR015S233CR
    +CRT_VCC CRT_HSYNC_2 C902
    1 2
    L50 FCM1608C-121T_0603 <EMI> 2
    1 2 2 1 <EMI> 100P_0402_50V8J DSUB_12
    C903 0.1U_0402_16V4Z R812 10K_0402_5% 1 2 CRT_VSYNC_2
    L51 FCM1608C-121T_0603 1

    1
    U19 <EMI> C904
    1 1 <EMI>

    OE#
    1 2 VGA_HSYNC_R 2 4 CRT_HSYNC_0 1 2 CRT_HSYNC_1 C906 68P_0402_50V8K
    <17> VGA_HSYNC A Y 2
    R813 PM@ 0_0402_5% R814 39_0402_1% C905

    G
    1 2 10P_0402_50V8J 10P_0402_50V8J DSUB_15
    2 <10> GMCH_CRT_HSYNC 2 2 <EMI> 2
    R815 GM@ 0_0402_5% TC7SET125FUF_SC70 <EMI>

    3
    +CRT_VCC 1
    C908
    Place closed to chipset 68P_0402_50V8K
    1 2
    C907 0.1U_0402_16V4Z 2

    1
    U20
    <EMI>

    OE#
    1 2 VGA_VSYNC_R 2 4 CRT_VSYNC_0 1 2 CRT_VSYNC_1 12/22 Change to SE071680J80
    <17> VGA_VSYNC A Y
    R816 PM@ 0_0402_5% R817 39_0402_1%

    G
    <10> GMCH_CRT_VSYNC 1 2 (IFTXX)

    1
    R818 GM@ 0_0402_5% TC7SET125FUF_SC70

    3
    D15 D16 Add IFTXX
    <EMI> <EMI>
    DAN217_SC59 DAN217_SC59
    Andy_1102
    Change PCB footprint of L50/L51 from L_0603 to R_0603
    @ @

    3
    +5VS

    +3VS
    +CRT_VCC

    1
    R819

    +3VS 2.2K_0402_5%

    1
    3 B0@ 3

    2
    R820 R821
    VGA_DDC_DATA <17>
    2.2K_0402_5% 2.2K_0402_5%

    2
    DSUB_12 6 1 2 1 GMCH_CRT_DATA <10>
    R822 GM@ 0_0402_5%
    Q64A

    5
    2N7002DW-T/R7_SOT363-6

    DSUB_15 3 4 2 1 GMCH_CRT_CLK <10>


    R823 GM@ 0_0402_5%
    Q64B
    2N7002DW-T/R7_SOT363-6
    VGA_DDC_CLK <17>

    1
    10/5 Change to SB00000AR00 R824

    2.2K_0402_5%
    B0@

    2
    R819 R824
    +3VS

    4 4
    2.2K_0402_5% 2.2K_0402_5%
    B1@ B1@

    10/22 Add by Vivian

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CRT Connector
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 26 of 56
    A B C D E
    5 4 3 2 1

    +3VS

    DMI for ESI-compatible operation


    RP27
    1 8 PCI_FRAME# Low= DMI for ESI-compatible operation
    2 7 PCI_DEVSEL# PCI_GNT#1 High= Default* (Internal pull-up)
    3 6 PCI_REQ#1
    4 5 PCI_REQ#2
    9/18 Change U21 from SA00002JH00 to SA00002JH80
    D 8.2K_1206_8P4R_5% D

    RP28 U21B
    1 8 PCI_TRDY# D11 F1 PCI_REQ#0
    PCI_REQ#3 AD0 REQ0# PCI_GNT#0
    2 7 C8 AD1 GNT0# G4
    PCI_PERR# PCI_REQ#1
    3
    4
    6
    5 PCI_PIRQB#
    D9
    E12
    AD2 PCI REQ1#/GPIO50 B6
    A7 PCI_GNT#1 @
    AD3 GNT1#/GPIO51 PAD T69
    E9 F13 PCI_REQ#2
    8.2K_1206_8P4R_5% AD4 REQ2#/GPIO52 PCI_GNT#2 @
    C9 AD5 GNT2#/GPIO53 F12 PAD T70
    E10 E6 PCI_REQ#3
    AD6 REQ3#/GPIO54 PCI_GNT#3
    B7 AD7 GNT3#/GPIO55 F6
    C7 AD8
    C5 AD9 C/BE0# D8
    +3VS G11 B4
    AD10 C/BE1#
    F8 AD11 C/BE2# D6
    RP29 F11 A5
    PCI_PIRQE# AD12 C/BE3#
    1 8 E7 AD13
    2 7 PCI_PIRQC# A3 D3 PCI_IRDY#
    PCI_PIRQG# AD14 IRDY#
    3 6 D2 AD15 PAR E3
    4 5 PCI_REQ#0 F10 R1 PCIRST# Place closely pin D4
    AD16 PCIRST# PCI_DEVSEL#
    D5 AD17 DEVSEL# C6
    8.2K_1206_8P4R_5% D10 E4 PCI_PERR#
    AD18 PERR# PCI_PLOCK# CLK_PCI_ICH
    B3 AD19 PLOCK# C2
    RP30 F7 J4 PCI_SERR#
    AD20 SERR#

    2
    1 8 PCI_PIRQF# C3 A4 PCI_STOP#
    PCI_SERR# AD21 STOP# PCI_TRDY#
    2 7 F3 AD22 TRDY# F5
    3 6 PCI_PIRQA# F4 D7 PCI_FRAME# R825
    PCI_PIRQH# AD23 FRAME# 10_0402_5%
    4 5 C1 AD24
    G7 C14 PLT_RST# @

    1
    C 8.2K_1206_8P4R_5% AD25 PLTRST# CLK_PCI_ICH C
    H7 AD26 PCICLK D4 CLK_PCI_ICH <23>
    D1 R2 PCI_PME# 1
    AD27 PME# PCI_PME# <37>
    RP31 G5 C909
    PCI_PIRQD# AD28 10P_0402_50V8J
    1 8 H6 AD29
    2 7 PCI_PLOCK# G1 @
    PCI_IRDY# AD30 2
    3 6 H3 AD31
    4 5 PCI_STOP#

    8.2K_1206_8P4R_5%
    PCI_PIRQA# J5
    Interrupt I/F H4 PCI_PIRQE#
    PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
    E1 PIRQB# PIRQF#/GPIO3 K6
    PCI_PIRQC# J6 F2 PCI_PIRQG#
    PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
    C4 PIRQD# PIRQH#/GPIO5 G2
    ICH9-M ES_FCBGA676

    R826 1 2 1K_0402_5% PCI_GNT#3 +3V_AND1 1 2 +3VS


    @ R827 @ 0_0402_5%
    1 2 +3VALW
    R829 1 2 1K_0402_5% PCI_GNT#0 R828 @ 0_0402_5%
    @ 1 2
    C910 @ 0.1U_0402_16V4Z
    R830 1 2 1K_0402_5% U22
    SPI_CS#1 <29>

    5
    @ NC7SZ08P5X_NL_SC70-5
    PLT_RST# 2 @

    P
    B B B
    Y 4 PLT_RST_BUF# <8,16,32,33,35,45>
    1 A

    1
    3
    R831

    100K_0402_5%
    1 2 @
    A16 Swap Override Strap

    2
    R832 0_0402_5%
    Low= A16 swap override Enable
    PCI_GNT#3 High= Default* Update Footprint +3V_AND2 1 2 +3VS
    R833 @ 0_0402_5%
    1 2 +3VALW
    R834 @ 0_0402_5%
    1 2
    C911 @ 0.1U_0402_16V4Z
    U23

    5
    NC7SZ08P5X_NL_SC70-5
    PCIRST# 2 @

    P
    B
    CRB: GNT#0 and SPI_CS#1 have a weak internal pull up Y 4 PCI_RST# <36,37,40>
    1 A

    G
    Boot BIOS Strap

    1
    3
    R835
    PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction 100K_0402_5%
    1 2 @

    2
    R836 0_0402_5%
    A 0 1 SPI A

    1 0 PCI

    1 1 LPC* Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    ICH9M(1/4)-PCI
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 27 of 56
    5 4 3 2 1
    5 4 3 2 1

    ICH9M Internal VR Enable Strap


    +RTCVCC 12/7 Modified X4 to SJ100001U00 10ppm (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
    C912 Low = Internal VR Disabled
    15P_0402_50V8J ICH_INTVRMEN High = Internal VR Enabled(Default)
    1 2 SM_INTRUDER# 2 1 ICH_RTCX1
    R837 1M_0402_5% ICH9M LAN100 SLP Strap

    10M_0402_5%
    X1
    (Internal VR for VccLAN1.05 and VccCL1.05)

    1
    2 NC IN 1

    R839
    1 2 ICH_INTVRMEN Low = Internal VR Disabled
    R838 330K_0402_1% 3 4 ICH_LAN100_SLP High = Internal VR Enabled(Default)
    NC OUT
    32.768KHZ_12.5P_1TJS125BJ2A251 U21A

    2
    D 1 2 LAN100_SLP C23 RTCX1 FWH0/LAD0 K5 LPC_AD0
    LPC_AD0 <37,40,45> D
    R840 330K_0402_1% 1 2 ICH_RTCX2 C24 K4 LPC_AD1
    RTCX2 FWH1/LAD1 LPC_AD1 <37,40,45> +VCCP
    C914
    15P_0402_50V8J L6 LPC_AD2
    FWH2/LAD2 LPC_AD2 <37,40,45>
    +RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
    +3VS RTCRST# FWH3/LAD3 LPC_AD3 <37,40,45>
    R841 +RTCVCC 1 2 ICH_SRTCRST# F20 H_DPRSTP# 2 1
    20K_0402_5% R842 SM_INTRUDER# SRTCRST# LPC_FRAME# R843 @ 56_0402_5%
    C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <37,40,45>
    180K_0402_5% H_DPSLP# 2 1

    RTC

    LPC
    close to RAM door close to RAM door ICH_INTVRMEN B22 J3 R844 @ 56_0402_5%
    SATA_LED# LAN100_SLP INTVRMEN LDRQ0# H_FERR#
    1 2 A22 LAN100_SLP LDRQ1#/GPIO23 J1 2 1
    R845 10K_0402_5% 2 1 1 @ 2 R848 2 1 8.2K_0402_5% +3VS R846 56_0402_5%

    1
    J2 @ JOPEN R847 E25 N7 GATEA20
    +3VALW GLAN_CLK A20GATE GATEA20 <37>
    10K_0603_5% R849 R850 AJ27 H_A20M#
    A20M# H_A20M# <5>
    C915 C913 @ @ C13
    1U_0603_10V4Z 0.1U_0402_16V4Z 0_0402_5% 0_0402_5% LAN_RSTSYNC DPRSTP# R851 1 0_0402_5% H_DPRSTP#
    DPRSTP# AJ25 2 H_DPRSTP# <6,8,54>
    1 2 1 2 F14 AE23 DPSLP# R852 1 2 0_0402_5% H_DPSLP#
    H_DPSLP# <6>

    2
    LAN_RXD0 DPSLP#
    1 2 GPIO56 G13 LAN_RXD1
    R853 10K_0402_5% D14 AJ26 FERR# 1 2 H_FERR#
    LAN_RXD2 FERR# H_FERR# <5>

    LAN / GLAN
    R854 56_0402_5%
    D13 AD22 H_PWRGOOD
    LAN_TXD_0 CPUPWRGD H_PWRGOOD <6>
    1 2 GPIO33 D12 LAN_TXD_1
    R855 @ 20K_0402_5% E13 AF25 H_IGNNE#
    LAN_TXD_2 IGNNE# H_IGNNE# <5>
    1 2 HDA_SDIN1 Need check GPIO56 B10 AE22 H_INIT# R856 2 1 10K_0402_5%
    GPIO56 INIT# H_INIT# <5> +3VS
    C916 100P_0402_50V8J AG25 H_INTR

    CPU
    INTR H_INTR <5>
    @ +1.5VS 1 2 GLAN_COMP B28 L3 KB_RST#
    GLAN_COMPI RCIN# KB_RST# <37>
    R857 24.9_0402_1% B27
    HDA_BITCLK_ICH GLAN_COMPO H_NMI
    <45> HDA_BITCLK_MDC 1 2 NMI AF23 H_NMI <5>
    R858 33_0402_5% AF6 AF24 H_SMI#
    HDA_BIT_CLK SMI# H_SMI# <5>
    1 2 HDA_SYNC_ICH AH4 R308 need to place within 2" of ICH9M
    <45> HDA_SYNC_MDC HDA_SYNC
    C SW1 R859 33_0402_5% AH27 H_STPCLK# R310 must be place within 2" of R308 w/o stub. C
    STPCLK# H_STPCLK# <5>
    6
    5

    A@ 1 2 HDA_RST_ICH# AE7
    <45> HDA_RST_MDC# HDA_RST#
    2 4 +RTCVCC R860 33_0402_5% AG26 THRMTRIP_ICH# R861 1 2 54.9_0402_1% H_THERMTRIP#
    THRMTRIP# H_THERMTRIP# <5,8>
    HDA_SDIN0 AF4
    <41> HDA_SDIN0 HDA_SDIN0
    1 3 HDA_SDIN1 AG4 AG27 2 1 +VCCP
    <45> HDA_SDIN1 HDA_SDIN1 TP12
    CHECK HDA_SDIN2 AH3 SATA ODD R862 56_0402_5%
    <8> HDA_SDIN2 HDA_SDIN2
    SMT1-05_4P HDA_SDIN3 AE5

    IHDA
    HDA_SDIN3 HDA_SDIN3
    AH11 SATA_DTX_C_IRX_N4 T71 PAD @
    SATA4RXN
    2 1 <45> HDA_SDOUT_MDC 1 2 HDA_SDOUT_ICH AG5 HDA_SDOUT SATA4RXP AJ11 SATA_DTX_C_IRX_P4 T72 PAD @
    J3 JOPEN R863 33_0402_5% AG12 SATA_ITX_DRX_N4 T73 PAD @
    @ @ GPIO33 SATA4TXN SATA_ITX_DRX_P4 T75 PAD @
    T74 PAD AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12 MAINPWON <48,50>
    2 1 AE8 HDA_DOCK_RST#/GPIO34
    J9 JOPEN
    @ SATA_LED# AG8 R864
    <45> SATA_LED# SATALED#

    1
    12/8 Add by Vivian AH9 @ 330_0402_5% C
    SATA_DTX_C_IRX_N0 SATA5RXN Q65
    12/8 Close to RAM socket. <31> SATA_DTX_C_IRX_N0 AJ16 SATA0RXN SATA5RXP AJ9 1 2 2
    SATA_DTX_C_IRX_P0 B
    SATA HDD <31> SATA_DTX_C_IRX_P0
    SATA_ITX_DRX_N0
    AH16 SATA0RXP SATA5TXN AE10 +VCCP
    E 2SC2411K_SOT23
    AF17 AF10

    3
    SATA_ITX_DRX_P0 SATA0TXN SATA5TXP @
    AG17 SATA0TXP
    SATA ODD AH18 CLK_PCIE_SATA#
    <31> SATA_DTX_C_IRX_N1 SATA_CLKN CLK_PCIE_SATA# <23>

    SATA
    SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA H_THERMTRIP#
    <31> SATA_DTX_C_IRX_P1 SATA1RXN SATA_CLKP CLK_PCIE_SATA <23>
    1 2 HDA_BITCLK_ICH SATA_DTX_C_IRX_P1 AJ13 AJ7 SATARBIAS
    <41> HDA_BITCLK_AUDIO SATA1RXP SATARBIAS#
    R865 33_0402_5% SATA_ITX_DRX_N1 AG14 AH7 R866 2 1 24.9_0402_1%
    HDA_SYNC_ICH SATA_ITX_DRX_P1 SATA1TXN SATARBIAS
    <41> HDA_SYNC_AUDIO 1
    R867
    2
    33_0402_5%
    AF14 SATA1TXP 4mils width less than 500mils
    1 2 HDA_RST_ICH#
    <41> HDA_RST_AUDIO#
    R868 33_0402_5% ICH9-M ES_FCBGA676
    1 2 HDA_SDOUT_ICH
    <41> HDA_SDOUT_AUDIO
    R869 33_0402_5% close ICH9
    B B

    1 2 HDA_BITCLK_ICH SATA_ITX_C_DRX_N0 1 2 SATA_ITX_DRX_N0 SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1


    HDA_BITCLK_VGA <31> SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_N1 <31>
    R870 PM@ 33_0402_5% C917 0.01U_0402_16V7K C918 0.01U_0402_16V7K
    1 2 HDA_SYNC_ICH SATA_ITX_C_DRX_P0 1 2 SATA_ITX_DRX_P0 SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
    HDA_SYNC_VGA <31> SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P1 <31>
    R871 PM@ 33_0402_5% C919 0.01U_0402_16V7K C920 0.01U_0402_16V7K
    1 2 HDA_RST_ICH#
    HDA_RST_VGA#
    R872 PM@ 33_0402_5%
    1 2 HDA_SDOUT_ICH
    HDA_SDOUT_VGA
    R873 PM@ 33_0402_5%

    1 2 HDA_BITCLK_ICH
    <8> HDA_BITCLK_NB
    R874 GM@ 33_0402_5% Change BATT1 P/N : SP093PA0200 (Panasonic)
    <8> HDA_SYNC_NB 1
    R875
    2 HDA_SYNC_ICH
    GM@ 33_0402_5%
    RTC Battery SP093MX0000 (MAXELL)
    1 2 HDA_RST_ICH#
    <8> HDA_RST_NB#
    R876 GM@ 33_0402_5% H_DPRSTP# HDA_BITCLK_ICH
    1 2 HDA_SDOUT_ICH 9/29 modified to follow ISKAA
    <8> HDA_SDOUT_NB

    2
    R877 GM@ 33_0402_5%
    D17
    +RTC_BATT
    Need check R878
    10_0402_5%
    @ - BATT1 + R879
    2 +CHGRTC
    Flash Descriptor Security Override Strap 1
    1
    2 1 +RTCBATT 1 2 1
    +3VS C921
    Low= Descriptor Security override 511_0603_1% 3
    GPIO33 High= Default* (Internal pull-up) 100P_0402_50V8J C922
    1 +RTCVCC
    2 10P_0402_50V8J @ ML1220T13RE 1
    R880 @ @ BAS40-04_SOT23 C923
    1K_0402_5% 2
    XOR Chain Entrance Strap 0.1U_0402_16V4Z
    A @ A
    2
    HDA_SDOUT_ICH
    ICH_TP3 HDA_SDOUT Description
    0 0 RSVD 9/29 Checked. Same as HEL80's
    <29> ICH_TP3
    0 1 Enter XOR Chain
    R881 1 0 Normal Operation
    Security Classification Compal Secret Data Compal Electronics, Inc.
    1K_0402_5% 2008/07/15 2009/7/15 Title
    Issued Date Deciphered Date
    @ 1 1 Set PCIE port config bit 1 ICH9M(2/4)-LAN,IDELPC,RTC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 28 of 56
    5 4 3 2 1
    5 4 3 2 1

    +3VS R882 1 2 2.2K_0402_5%


    8.2K_0402_5%
    +3VALW 12/13 Add 10K_0402_5% Place closely pin AC1
    R883 1 2 PM_CLKRUN# R884 1 2 2.2K_0402_5% R885 1 2
    +3VS R892 C925
    U21C SINGLE@
    8.2K_0402_5% ICH_SMBCLK G16 AH23 PROJECT_ID1 R888 CLK_ICH_14M 1 2 1 2
    <23,35,36> ICH_SMBCLK SMBCLK SATA0GP/GPIO21
    R887 1 EC_THERM# ICH_SMBDATA PROJECT_ID0 MIC_ID
    2 <23,35,36> ICH_SMBDATA
    LINKALERT#
    A13 SMBDATA SMB SATA1GP/GPIO19 AF19
    MIC_ID
    1 2
    DUAL@ 10K_0402_5%

    SATA
    GPIO
    E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21 10_0402_5% 10P_0402_50V8J
    10K_0402_5% ICH_SMLINK0 C17 AD20 R889 1 2 10K_0402_5%
    R890 1 @ PM_STP_PCI# ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 @ @
    2 B18 SMLINK1
    H1 CLK_ICH_14M
    10K_0402_5% ICH_RI# CLK14 CLK_ICH_48M CLK_ICH_14M <23>
    R893 1 @ 2 PM_STP_CPU#
    F19 RI# clocks CLK48 AF3 CLK_ICH_48M <23> Place closely pin B2
    R891 C924
    SUS_STAT# R4 P1 SUS_CLK PAD
    <45> SUS_STAT# SUS_STAT#/LPCPD# SUSCLK T76
    10K_0402_5% XDP_DBRESET# G19 @ CLK_ICH_48M 1 2 1 2
    <5> XDP_DBRESET# SYS_RESET#
    R894 1 @ 2 PM_BMBUSY# C16 PM_SLP_S3# 10_0402_5%
    D 10K_0402_5% PM_BMBUSY# SLP_S3# PM_SLP_S4# PM_SLP_S3# <37> @ 10P_0402_50V8J D
    <8> PM_BMBUSY# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# <37>
    R886 1 2 GPIO7 G17 PM_SLP_S5# CHECK @

    SYS / GPIO
    RP32 EC_LID_OUT# SLP_S5# PM_SLP_S5# <37>
    <37> EC_LID_OUT# A17 SMBALERT#/GPIO11
    5 4 C10 0_0402_5%
    OCP# PM_STP_PCI# S4_STATE#/GPIO26 R895 2
    6 3
    D_ACIN
    <23> PM_STP_PCI#
    PM_STP_CPU#
    A14 STP_PCI# ICH_PWROK
    1 M_PWROK <8> 08/27 Modified
    7 2 <23> PM_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWROK <8,37>
    8 1 CR_WAKE# by Vivian
    PM_CLKRUN# L4 M2 PM_DPRSLPVR_D
    1 2 10K_0402_5% @

    Power MGT
    +3VS <37,45> PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR <8,54>
    10K_1206_8P4R_5% R896 0_0402_5% 2 1 R943 +3VS
    ICH_PCIE_WAKE# E20 B13 PM_BATLOW#
    <33,35,36> ICH_PCIE_WAKE# WAKE# BATLOW#
    SERIRQ M5 10K_0402_5%
    <37,45> SERIRQ SERIRQ
    1 R30 2 SERIRQ EC_THERM# AJ23 R3 PBTN_OUT# PROJECT_ID2 2 1 R1150
    <37> EC_THERM# THRM# PWRBTN# PBTN_OUT# <37>
    10K_0402_5%
    1 2 GPIO48 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2
    <8,54> VGATE VRMPWRGD LAN_RST#
    R94 R897 0_0402_5% R898 0_0402_5% 10K_0402_5% @
    10K_0402_5% PAD @ ICH_TP11 A20 D22 EC_RSMRST#R 2 1 R1159
    +3VALW T77 TP11 RSMRST# +3VS
    RP34 CH751H-40PT_SOD323-2 @ OCP# AG19 R5 CK_PWRGD 10K_0402_5%
    ICH_RI# D18 1 D_ACIN GPIO1 CK_PWRGD CK_PWRGD <23> PROJECT_ID3
    5 4 <37,47> ACIN 2 AH21 GPIO6 2 1 R1052
    6 3 ICH_SMLINK1 GPIO7 AG21 R6 M_PWROK 1 2
    GPIO7 CLPWROK VGATE <8,54>
    7 2 ICH_SMLINK0 EC_SMI# A21 R899 @ 0_0402_5%
    <37> EC_SMI# GPIO8
    8 1 LINKALERT# C12 B16 PM_SLP_M# PAD
    GPIO12 SLP_M# T78
    <37> EC_SCI# EC_SCI# C21 @ CHECK
    10K_1206_8P4R_5% GPIO13
    AE18 GPIO17 CL_CLK0 F24 CL_CLK0 <8>
    GPIO18 K1 B19

    GPIO
    Controller Link
    <32> GPIO18 GPIO18 CL_CLK1
    RP35 ICH_GPIO20 AF8
    T79 PAD GPIO20
    5 4 CR_WAKE# AJ22 F22
    <32> CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8>
    6 3 GPIO14 A9 C19
    GPIO10 GPIO27 CL_DATA1 DPRSLPVR C926 1
    7 2 D19 GPIO28 2 @
    8 1 XDP_DBRESET# SATA_CLKREQ# L1 C25 CL_VREF0_ICH 100P_0402_50V8J
    <23> SATA_CLKREQ# SATACLKREQ#/GPIO35 CL_VREF0
    follow iTPM spec PROJECT_ID2 AE19 A19 CL_VREF1_ICH
    10K_1206_8P4R_5% PROJECT_ID3 SLOAD/GPIO38 CL_VREF1 ICH_PCIE_WAKE# C927 1
    AG22 SDATAOUT0/GPIO39 2 @
    C GPIO48 100P_0402_50V8J C
    AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST# <8>
    10K_0402_5% ICH_GPIO49 AH24 D18
    R900 1 @ ICH_GPIO57 ICH_GPIO57 GPIO49 CL_RST1# VGATE C928 1
    2 A8 GPIO57/CLGPIO5 2
    +3VS R901 1 @ 2 1K_0402_5% A16 100P_0402_50V8J
    1K_0402_5% SB_SPKR MEM_LED/GPIO24 GPIO10
    <41> SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
    R902 1 2 ICH_PCIE_WAKE# MCH_ICH_SYNC# AJ24 C11 GPIO14 ICH_SMBCLK C929 1 2 @

    MISC
    <8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
    ICH_TP3 B21 C20 100P_0402_50V8J
    <28> ICH_TP3 TP3 WOL_EN/GPIO9
    8.2K_0402_5% AH20
    R903 2 1 PM_BATLOW# AJ20
    TP8 DMI Termination Voltage ICH_SMBDATA C930 1 2 @
    No Reboot Strap AJ21
    TP9
    TP10 Low= Desktop used 100P_0402_50V8J
    Low= Default* GPIO49
    SB_SPKR ICH9-M ES_FCBGA676 High= Mobile* (Internal pull-up)
    100K_0402_5%
    R904 1 @ ICH_GPIO57
    High= "No Reboot" RSMRST circuit
    2
    U21D
    10K_0402_5% PCIE_PTX_C_IRX_N1 N29 V27 DMI_RXN0 R910 0_0402_5%
    <32> PCIE_PTX_C_IRX_N1 PERN1 DMI0RXN DMI_RXN0 <8>
    R909 1 @ 2 ICH_GPIO49 For CardReader PCIE_PTX_C_IRX_P1 N28 V26 DMI_RXP0 1 2
    <32> PCIE_PTX_C_IRX_P1 PERP1 DMI0RXP DMI_RXP0 <8>
    C932 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N1 P27 U29 DMI_TXN0 <EMI>
    <32> PCIE_ITX_C_PRX_N1 PETN1 DMI0TXN DMI_TXN0 <8>
    100K_0402_5% C933 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P1 P26 U28 DMI_TXP0 Q66

    Direct Media Interface


    <32> PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_TXP0 <8>
    R905 1 @ DPRSLPVR EC_RSMRST#R

    C
    2 <37> EC_RSMRST# 3 1
    PCIE_PTX_C_IRX_N2 DMI_RXN1

    E
    <35> PCIE_PTX_C_IRX_N2 L29 PERN2 DMI1RXN Y27 DMI_RXN1 <8>
    100K_0402_5% PCIE_PTX_C_IRX_P2 L28 Y26 DMI_RXP1 @ BAV99DW-7_SOT363 @ MMBT3906_SOT23
    <35> PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_RXP1 <8>
    R906 1 ICH_VGATE For 3G card C934 2 0.1U_0402_10V7K PCIE_ITX_PRX_N2 DMI_TXN1

    B
    2 <35> PCIE_ITX_C_PRX_N2 1 M27 W29 DMI_TXN1 <8> 1 2 +3VALW

    1 2
    C935 2 0.1U_0402_10V7K PCIE_ITX_PRX_P2 PETN2 DMI1TXN DMI_TXP1 R907 @ 4.7K_0402_5%
    <35> PCIE_ITX_C_PRX_P2 1 M26 PETP2 DMI1TXP W28 DMI_TXP1 <8>

    2
    PCI - Express
    PCIE_PTX_C_IRX_N3 J29 AB27 DMI_RXN2 R908 D19B D19A @
    <35> PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN DMI_RXN2 <8>
    For Wireless LAN PCIE_PTX_C_IRX_P3 J28 AB26 DMI_RXP2 @ 2.2K_0402_5% BAV99DW-7_SOT363
    +3VALW <35> PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_RXP2 <8>
    C931 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_TXN2
    <35> PCIE_ITX_C_PRX_N3 PETN3 DMI2TXN DMI_TXN2 <8>
    C936 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_TXP2
    <35> PCIE_ITX_C_PRX_P3 DMI_TXP2 <8>

    1
    RP36 PETP3 DMI2TXP
    R911

    6
    5 4 USB_OC#3 PCIE_PTX_C_IRX_N4 G29 AD27 DMI_RXN3 1 2
    <33> PCIE_PTX_C_IRX_N4 PERN4 DMI3RXN DMI_RXN3 <8>
    6 3 USB_OC#2 For PCIE LAN PCIE_PTX_C_IRX_P4 G28 AD26 DMI_RXP3
    B <33> PCIE_PTX_C_IRX_P4 PERP4 DMI3RXP DMI_RXP3 <8> B
    7 2 USB_OC#10 C937 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N4 H27 AC29 DMI_TXN3 @ 2.2K_0402_5%
    <33> PCIE_ITX_C_PRX_N4 PETN4 DMI3TXN DMI_TXN3 <8>
    8 1 USB_OC#1 C938 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P4 H26 AC28 DMI_TXP3
    <33> PCIE_ITX_C_PRX_P4 PETP4 DMI3TXP DMI_TXP3 <8>
    10K_1206_8P4R_5% PCIE_PTX_C_IRX_N5 E29 T26 CLK_PCIE_ICH#
    <36> PCIE_PTX_C_IRX_N5 PERN5 DMI_CLKN CLK_PCIE_ICH# <23>
    PCIE_PTX_C_IRX_P5 E28 T25 CLK_PCIE_ICH
    <36> PCIE_PTX_C_IRX_P5 PERP5 DMI_CLKP CLK_PCIE_ICH <23>
    RP37 For Express Card C939 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N5 F27
    5 4
    <36>
    <36>
    PCIE_ITX_C_PRX_N5
    PCIE_ITX_C_PRX_P5
    C940 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P5 F26
    PETN5
    PETP5 DMI_ZCOMP AF29 R913 24.9_0402_1% Within 500 mils Internal TPM Strap
    USB_OC#6 DMI_IRCOMP
    6
    7
    3
    2 USB_OC#8 C29
    DMI_IRCOMP AF28 1 2 +1.5VS_PCIE_ICH Low= Disable
    8 1 USB_OC#9 C28
    PERN6/GLAN_RXN
    PERP6/GLAN_RXP USBP0N AC5 USB20_N0
    USB20_N0 <40>
    SPI_MOSI High= iTPM enable by MCH strap*
    D27 AC4 USB20_P0 USB(IO/B)
    PETN6/GLAN_TXN USBP0P USB20_P0 <40>
    10K_1206_8P4R_5% D26 AD3 USB20_N1
    PETP6/GLAN_TXP USBP1N USB20_N1 <45>
    follow iTPM spec AD2 USB20_P1 FP
    USBP1P USB20_P1 <45>
    1 2 ICH_SPI_MOSI ICH_SPI_CLK_R R916 @ 15_0402_5% ICH_SPI_CLK D23 AC1 USB20_N2 ICH_PWROK 1 2
    <39> ICH_SPI_CLK_R SPI_CLK USBP2N USB20_N2 <45>
    R915 @ 20K_0402_5% ICH_SPI_CS0#_R R917 @ 15_0402_5% ICH_SPI_CS0# D24 AC2 USB20_P2 CAMERA R912 10K_0402_5%
    <39> ICH_SPI_CS0#_R SPI_CS0# USBP2P USB20_P2 <45>
    1 2 ICH_SPI_MOSI F23 AA5 USB20_N3
    <27> SPI_CS#1 SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 <35>
    R918 10K_0402_5% AA4 USB20_P3 TV EC_RSMRST#R 1 2
    USBP3P USB20_P3 <35>
    ICH_SPI_MOSI_R R919 @ 15_0402_5% ICH_SPI_MOSI R914 10K_0402_5%
    <39> ICH_SPI_MOSI_R
    ICH_SPI_MISO
    D25
    E23
    SPI_MOSI SPI USBP4N AB2
    AB3
    <39> ICH_SPI_MISO SPI_MISO USBP4P
    AA1 USB20_N5
    USBP5N USB20_N5 <40>
    USB_OC#04 N4 AA2 USB20_P5 USB(IO/B)
    <40> USB_OC#04 OC0#/GPIO59 USBP5P USB20_P5 <40> +3VS +3VALW
    USB_OC#1 N5 W5 USB20_N6
    OC1#/GPIO40 USBP6N USB20_N6 <39>
    USB_OC#2 USB20_P6
    USB_OC#3
    N6 OC2#/GPIO41 USB USBP6P W4 USB20_P6 <39> BT
    08/27 Modified P6 OC3#/GPIO42 USBP7N Y3
    M1 OC4#/GPIO43 USBP7P Y2
    by Vivian <40> USB_OC#511 N2 W1 USB20_N8
    USB20_N8 <35>
    R920 R921
    R922 R923 USB_OC#6 OC5#/GPIO29 USBP8N USB20_P8 @
    CP_PE#
    M4 OC6#/GPIO30 USBP8P W2
    USB20_N9
    USB20_P8 <35> WLAN 3.24K_0402_1% 3.24K_0402_1%
    <36> CP_PE# M3 OC7#/GPIO31 USBP9N V2 USB20_N9 <40>
    USB_OC#8 N3 V3 USB20_P9 USB 2(IO/B)
    OC8#/GPIO44 USBP9P USB20_P9 <40>
    USB_OC#9 N1 U5 USB20_N10 CL_VREF0_ICH CL_VREF1_ICH
    <40> USB_OC#9 OC9#/GPIO45 USBP10N USB20_N10 <36>
    USB_OC#10 P5 U4 USB20_P10 New Card
    OC10#/GPIO46 USBP10P USB20_P10 <36>
    P3 U1 USB20_N11 1 1
    A OC11#/GPIO47 USBP11N USB20_N11 <40> A
    10K_0402_5% 10K_0402_5% U2 USB20_P11 USB(IO/B) C942 R925
    USBP11P USB20_P11 <40>
    @ 10K_0402_5% B1@ B1@ USBRBIAS AG2 C941 R924 @ @
    R923 1 USBRBIAS 0.1U_0402_16V4Z 453_0402_1% 0.1U_0402_16V4Z 453_0402_1%
    +3VS 2 2 1 AG1 USBRBIAS#
    R929 2 2
    B0@10K_0402_5% 22.6_0402_1% ICH9-M ES_FCBGA676
    R928 1 2 PROJECT_ID0 R927 R928 Within 500 mils

    @ 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.


    R927 1 2 Issued Date 2008/07/15 2009/07/15 Title
    +3VS Deciphered Date
    B0@10K_0402_5% 10K_0402_5% 10K_0402_5% ICH9M(3/4)-USB,GPIO,PCIE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    R922 1 2 PROJECT_ID1 B2@ B2@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 29 of 56
    5 4 3 2 1
    5 4 3 2 1

    +5VS +3VS U21F U21E


    (1UF*1, 0.1UF*2) 1634mA (0.1UF*2) 220u
    +RTCVCC A23 VCCRTC VCC1_05[01] A15 +VCCP ESR 15m ohm AA26 VSS[001] VSS[107] H5
    1 1 VCC1_05[02] B15 1 AA27 VSS[002] VSS[108] J23

    2
    +ICH_V5REF A6 C15 1 1 Package(L*W*H)7.3*4.3*1.9 AA3 J26
    R933 D21 C946 C943 V5REF VCC1_05[03] C949 C947 C944 + VSS[003] VSS[109]
    2mA VCC1_05[04] D15 Rating 4V AA6 VSS[004] VSS[110] J27
    E15 @ AB1 AC22
    100_0402_5% CH751H-40PT_SOD323-2 2 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z 220U_D2_4VM_R15 VSS[005] VSS[111]
    AE1 V5REF_SUS VCC1_05[06] F15 AA23 VSS[006] VSS[112] K28
    1U_0402_6.3V4Z 0.1U_0402_16V4Z 2 2 2
    2mA L11 AB28 K29

    1
    +ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[007] VSS[113]
    AA24 VCC1_5_B[01] VCC1_05[08] L12 AB29 VSS[008] VSS[114] L13
    2
    C948
    (0.1UF*1) AA25 VCC1_5_B[02] VCC1_05[09] L14 AB4 VSS[009] VSS[115] L15
    AB24 VCC1_5_B[03] VCC1_05[10] L16 AB5 VSS[010] VSS[116] L2
    AB25 VCC1_5_B[04] VCC1_05[11] L17 Change PCB footprint of L52 from L_0603 to R_0603 AC17 VSS[011] VSS[117] L26
    0.1U_0402_16V4Z AC24 L18 AC26 L27
    1 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS_DMIPLL_R VSS[012] VSS[118]
    AC25 VCC1_5_B[06] VCC1_05[13] M11 AC27 VSS[013] VSS[119] L5
    AD24 VCC1_5_B[07] VCC1_05[14] M18 AC3 VSS[014] VSS[120] L7
    L52 1 R936 0_0603_5%

    CORE
    D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 +1.5VS AD1 VSS[015] VSS[121] M12 D
    +5VALW +3VALW MBK1608121YZF_0603
    AE25 VCC1_5_B[09] VCC1_05[16] P18 AD10 VSS[016] VSS[122] M13
    AE26 VCC1_5_B[10] VCC1_05[17] T11 1 (10UF*1, 0.01UF*1) AD12 VSS[017] VSS[123] M14
    AE27 T18 C950 C951 AD13 M15
    VCC1_5_B[11] VCC1_05[18] VSS[018] VSS[124]
    2

    AE28 U11 0.01U_0402_16V7K AD14 M16


    R934 D20 VCC1_5_B[12] VCC1_05[19] VSS[019] VSS[125]
    AE29 VCC1_5_B[13] VCC1_05[20] U18 10U_0805_10V4Z AD17 VSS[020] VSS[126] M17
    2
    220u F25 VCC1_5_B[14] VCC1_05[21] V11 AD18 VSS[021] VSS[127] M23
    10_0402_5% CH751H-40PT_SOD323-2 G25 V12 AD21 M28
    ESR 15m ohm VCC1_5_B[15] VCC1_05[22] VSS[022] VSS[128]
    H24 V14 AD28 M29
    1

    +ICH_V5REF_SUS Package(L*W*H)7.3*4.3*1.9 VCC1_5_B[16] VCC1_05[23] VSS[023] VSS[129]


    H25 VCC1_5_B[17] VCC1_05[24] V16 AD29 VSS[024] VSS[130] N11
    2 Rating 4V J24 V17 VCC_DMI R935 0_0603_5% +VCCP AD4 N12
    VCC1_5_B[18] VCC1_05[25] VSS[025] VSS[131]

    VCCA3GP
    C945 (0.1UF*1) J25 V18 AD5 N13
    VCC1_5_B[19] VCC1_05[26] VSS[026] VSS[132]
    K24 VCC1_5_B[20] 1 (22UF*1) AD6 VSS[027] VSS[133] N14
    0.1U_0402_16V4Z K25 C952 AD7 N15
    1 VCC1_5_B[21] VSS[028] VSS[134]
    +1.5VS_PCIE_ICH
    646mA L23 VCC1_5_B[22] 23mA AD9 VSS[029] VSS[135] N16
    L24 R29 4.7U_0805_10V4Z AE12 N17
    VCC1_5_B[23] VCCDMIPLL 2 VSS[030] VSS[136]
    L53 2
    (220UF*1, 22UF*2, 2.2UF*1) L25 VCC1_5_B[24] 48mA AE13 VSS[031] VSS[137] N18
    +1.5VS 1 M24 VCC1_5_B[25] VCC_DMI[1] W23 AE14 VSS[032] VSS[138] N26
    KC FBM-L11-201209-221LMAT_0805
    1 M25 Y23 AE16 N27
    VCC1_5_B[26] VCC_DMI[2] VSS[033] VSS[139]
    +
    1 1 N23 VCC1_5_B[27] 2mA AE17 VSS[034] VSS[140] P12
    10/22 CRB use 330 Ohm@100Mhz, C953 C954 C955 C956 N24 AB23 +VCCP AE2 P13
    VCC1_5_B[28] V_CPU_IO[1] VSS[035] VSS[141]
    N25 VCC1_5_B[29] V_CPU_IO[2] AC23 1 1 AE20 VSS[036] VSS[142] P14
    We use 220 Ohm 3A check! 220U_D2_4VM_R15 10U_0805_10V4Z P24 C957 C958 C959(4.7UF*1, 0.1UF*2) AE24 P15
    2 2 2 VCC1_5_B[30] VSS[037] VSS[143]
    P25 VCC1_5_B[31] VCC3_3[01] AG29 AE3 VSS[038] VSS[144] P16
    10U_0805_10V4Z 2.2U_0603_6.3V6K R24 AJ6 4.7U_0805_10V4Z 0.1U_0402_16V4Z AE4 P17
    VCC1_5_B[32] VCC3_3[02] 2 2 VSS[039] VSS[145]
    R25 VCC1_5_B[33] VCC3_3[07] AC10 AE6 VSS[040] VSS[146] P2
    R26 0.1U_0402_16V4Z AE9 P23
    VCC1_5_B[34] VSS[041] VSS[147]
    R27 VCC1_5_B[35] VCC3_3[03] AD19 AF13 VSS[042] VSS[148] P28

    VCCP_CORE
    Change PCB footprint of L53 from L_0805 to R_0805 T24 VCC1_5_B[36] VCC3_3[04] AF20 AF16 VSS[043] VSS[149] P29
    T27 VCC1_5_B[37] VCC3_3[05] AG24 close to AG29 close to AC20 close to G6 308mA AF18 VSS[044] VSS[150] P4
    T28 VCC1_5_B[38] VCC3_3[06] AC20 AF22 VSS[045] VSS[151] P7
    T29 VCC1_5_B[39] +3VS AH26 VSS[046] VSS[152] R11
    +1.5VS_SATAPLL_R +1.5VS_SATAPLL_ICH U24 AF26 R12
    C VCC1_5_B[40] VSS[047] VSS[153] C
    (10UF*1, 1UF*1) U25 VCC1_5_B[41] VCC3_3[08] B9 1 1 1 1 1 1 AF27 VSS[048] VSS[154] R13
    +1.5VS L54 1 2 V24 F9 C960 C961 C962 C963 C964 C965 (0.1UF*6) AF5 R14
    R937 MBK1608121YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[049] VSS[155]
    V25 VCC1_5_B[43] VCC3_3[10] G3 AF7 VSS[050] VSS[156] R15
    0_0603_5% 1 1 U23 G6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF9 R16
    VCC1_5_B[44] VCC3_3[11] 2 2 2 2 2 2 VSS[051] VSS[157]

    PCI
    C966 C967 W24 J2 AG13 R17
    1U_0402_6.3V4Z VCC1_5_B[45] VCC3_3[12] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[052] VSS[158]
    W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[053] VSS[159] R18
    Change PCB footprint of L54 from L_0603 to R_0603 10U_0805_10V4Z
    2 2
    K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[054] VSS[160] R28
    Y24 VCC1_5_B[48] close to AD19 close to B9 close to K7 AG20 VSS[055] VSS[161] T12
    (10UF*1, 1UF*1) Y25 VCC1_5_B[49] 11mA +VCC_HDA_ICH
    AG23 VSS[056] VSS[162] T13
    VCCHDA AJ4 AG3 VSS[057] VSS[163] T14
    11mA +3VALW
    AG6 VSS[058] VSS[164] T15
    47mA AJ3 PM@ +3VS AG9 T16
    VCCSUSHDA R938 0_0603_5% VSS[059] VSS[165]
    AJ19 VCCSATAPLL (0.1UF*1) 1 AH12 VSS[060] VSS[166] T17
    C968 GM@ +1.5VS AH14 T23
    VSS[061] VSS[167]
    VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T80
    R939 0_0603_5% AH17 VSS[062] VSS[168] B26

    2
    +1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T81
    0.1U_0402_16V4Z AH19 VSS[063] VSS[169] U12
    2 R940
    AD15 VCC1_5_A[02] AH2 VSS[064] VSS[170] U13
    AD16 TP_VCCSUS1_5_ICH_1 180_0402_1% AH22 U14
    1 VCC1_5_A[03] VSS[065] VSS[171]
    C969 AE15 AD8 TP_VCCSUS1_5_ICH_1 @ +VCCSUS_HDA_ICH @ AH25 U15
    VCC1_5_A[04] VCCSUS1_5[1] PAD T82 VSS[066] VSS[172]

    ARX
    AF15 1 GM@ 2 AH28 U16

    1
    1U_0402_6.3V4Z VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 R941 0_0402_5% VSS[067] VSS[173]
    AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 AH5 VSS[068] VSS[174] U17
    2
    AH15 VCC1_5_A[07] 1 (0.1UF*1) 1 AH8 VSS[069] VSS[175] AD23

    2
    AJ15 (0.1UF*1) C970 C971 AJ12 U26
    VCC1_5_A[08] R942 VSS[070] VSS[176]
    1342mA VCCSUS3_3[01] A18 AJ14 VSS[071] VSS[177] U27
    +1.5VS AC11 D16 0.1U_0402_16V4Z 0.1U_0402_16V4Z 150_0402_1% AJ17 U3

    VCCPSUS
    VCC1_5_A[09] VCCSUS3_3[02] 2 2 @ VSS[072] VSS[178]
    AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ8 VSS[073] VSS[179] V1
    1 AE11 E22 B11 V13

    1
    C972 VCC1_5_A[11] VCCSUS3_3[04] VSS[074] VSS[180]
    AF11 VCC1_5_A[12] B14 VSS[075] VSS[181] V15
    ATX

    AG10 VCC1_5_A[13] B17 VSS[076] VSS[182] V23


    1U_0402_6.3V4Z AG11 B2 V28
    2 VCC1_5_A[14] VSS[077] VSS[183]
    AH10 VCC1_5_A[15] (0.1UF*1, 0.022UF*2) B20 VSS[078] VSS[184] V29
    AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3VALW B23 VSS[079] VSS[185] V4
    B 1 B5 VSS[080] VSS[186] V5 B
    AC9 212mA 1 C974 R940 B8 W26
    VCC1_5_A[17] C973 VSS[081] VSS[187]
    10/22 follow common design 0928 0.1U_0402_16V4Z
    C26 VSS[082] VSS[188] W27
    AC18 VCC1_5_A[18] C27 VSS[083] VSS[189] W3
    0.1U_0402_16V4Z 2
    AC19 VCC1_5_A[19] E11 VSS[084] VSS[190] Y1
    2
    VCCSUS3_3[06] T1 E14 VSS[085] VSS[191] Y28
    AC21 VCC1_5_A[20] VCCSUS3_3[07] T2 E18 VSS[086] VSS[192] Y29
    +1.5VS VCCSUS3_3[08] T3 0_0402_5% E2 VSS[087] VSS[193] Y4
    1 G10 T4 PM@ E21 Y5
    C975 VCC1_5_A[21] VCCSUS3_3[09] VSS[088] VSS[194]
    G9 VCC1_5_A[22] VCCSUS3_3[10] T5 +3VALW E24 VSS[089] VSS[195] AG28
    VCCSUS3_3[11] T6 E5 VSS[090] VSS[196] AH6
    0.1U_0402_16V4Z AC12 U6 E8 AF2
    VCCPUSB

    2 VCC1_5_A[23] VCCSUS3_3[12] C976 VSS[091] VSS[197]


    AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 F16 VSS[092] VSS[198] B25
    AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F28 VSS[093]
    +1.5VS 11mA V7 4.7U_0805_10V4Z F29
    VCCSUS3_3[15] VSS[094]
    1 AJ5 VCCUSBPLL VCCSUS3_3[16] W6 G12 VSS[095]
    C977 11mA W7 G14 A1
    VCCSUS3_3[17] VSS[096] VSS_NCTF[01]
    USB CORE

    AA7 VCC1_5_A[26] VCCSUS3_3[18] Y6 G18 VSS[097] VSS_NCTF[02] A2


    0.1U_0402_16V4Z AB6 Y7 G21 A28
    2 VCC1_5_A[27] VCCSUS3_3[19] VSS[098] VSS_NCTF[03]
    (0.1UF*1) AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G24 VSS[099] VSS_NCTF[04] A29
    AC6 VCC1_5_A[29] G26 VSS[100] VSS_NCTF[05] AH1
    +3VS (0.1UF*1) AC7 VCC1_5_A[30] G27 VSS[101] VSS_NCTF[06] AH29
    1 G8 VSS[102] VSS_NCTF[07] AJ1
    C978 2 1 +VCCLAN1_05_INT_ICH A10 VCCLAN1_05[1] H2 VSS[103] VSS_NCTF[08] AJ2
    C979 0.1U_0402_16V4Z A11 VCCLAN1_05[2] VCCCL1_05 G22 +VCCCL1_05_INT_ICH H23 VSS[104] VSS_NCTF[09] AJ28
    19mA VCCCL1_5 G23 +VCCCL1_5_INT_ICH H28 VSS[105] VSS_NCTF[10] AJ29
    2
    A12 VCCLAN3_3[1] H29 VSS[106] VSS_NCTF[11] B1
    0.1U_0402_16V4Z B12 1 1 1 B29
    VCCLAN3_3[2] C980 C982 C981 VSS_NCTF[12]
    L55
    23mA VCCCL3_3[1] A24 +3VS
    @ @
    (0.1UF*1)
    VCCCL3_3[2] B24
    GLAN POWER

    +1.5VS +VCC_GLANPLL_R 1 2 +VCC_GLANPLL_ICH A27 19mA 1U_0402_6.3V4Z 0.1U_0402_16V4Z ICH9-M ES_FCBGA676


    R944 MBK1608121YZF_0603 1 VCCGLANPLL 2 2 2
    0_0603_5% C984 D28 0.1U_0402_16V4Z
    A
    C983 VCCGLAN1_5[1] A
    D29 VCCGLAN1_5[2]
    10U_0805_10V4Z E26 VCCGLAN1_5[3]
    2
    (2.2UF*1, 10UF*1) E27 VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
    2.2U_0603_6.3V6K
    Change PCB footprint of L55 from L_0603 to R_0603 80mA A26 VCCGLAN3_3
    +1.5VS_PCIE_ICH
    ICH9-M ES_FCBGA676
    (4.7UF*1) C985 +3VS
    1mA
    Security Classification Compal Secret Data Compal Electronics, Inc.
    4.7U_0805_10V4Z 2008/07/15 2009/07/15 Title
    Issued Date Deciphered Date
    ICH9M(4/4)-POWER&GND
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 30 of 56
    5 4 3 2 1
    A B C D E F G H

    SATA ODD Conn. SATA HDD Conn.

    1 1

    +5VS +3VS

    0.1U_0402_16V4Z 10U_0805_10V4Z

    1 1 1 1 1 1
    C986 C987 C988 C989 C990 C991
    1000P_0402_50V7K 0.1U_0402_16V4Z
    2 2 2 2 2 2 @
    Copy JAL90 Symbol 1U_0603_10V4Z 10U_0805_10V4Z

    JSATA1

    1 GND
    SATA_ITX_C_DRX_P1 2
    +5VS <28> SATA_ITX_C_DRX_P1 A+
    SATA_ITX_C_DRX_N1 3
    <28> SATA_ITX_C_DRX_N1 A-
    4 GND
    0.1U_0402_16V4Z SATA_DTX_IRX_N1 5
    SATA_DTX_IRX_P1 B-
    6 B+
    1 1 1 7 GND
    C992 C993 C994
    1000P_0402_50V7K 10U_0805_10V4Z R945 1 @ 2 1K_0402_1% 8
    2 2 2 DP JSATA2
    +5VS 9 +5V
    10 +5V 1 GND
    2 SATA_ITX_C_DRX_P0 2
    11 MD <28> SATA_ITX_C_DRX_P0 2 A+
    12 15 SATA_ITX_C_DRX_N0 3
    GND GND <28> SATA_ITX_C_DRX_N0 A-
    13 GND GND 14 4 GND
    SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0 5
    <28> SATA_DTX_C_IRX_N0 B-
    C995 0.01U_0402_16V7K 6
    SANTA_206401-1_13P SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0 B+
    <28> SATA_DTX_C_IRX_P0 1 2 7 GND
    CONN@ C996 0.01U_0402_16V7K

    Change ODD connector from OCTEK_SLS-13SB1G +3VS 8 V33


    9 V33
    to SANTA_206401-1_13P 10 V33
    11 GND
    12 GND
    SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1 13
    <28> SATA_DTX_C_IRX_N1 GND
    C997 0.01U_0402_16V7K 14
    +5VS V5
    15 V5
    SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1 16
    <28> SATA_DTX_C_IRX_P1 V5
    C998 0.01U_0402_16V7K 17 GND
    18 Reserved
    19 GND
    20 V12
    21 V12 GND 25
    22 26
    Need check layout !! V12 GND
    FOX_LD2122H-S43_NR
    CONN@

    9/4 Change symbol follow KSWXX by Vivian


    (NEW)
    3
    Change Library 3

    Update Symbol
    SP01000G800
    FOX_LD2122H-S43_NR
    Manually update pin number

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    HDD & ODD Connector
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 31 of 56
    A B C D E F G H
    5 4 3 2 1

    SD,MMC,MS muti-function pin define


    Active High EN MDIO SD/MMC Card MS Card
    11/24 Andy PIN Name PIN Name PIN Name
    40mil MDIO00 SD1_DAT0 MS1_DAT0
    +3VS +VCC_OUT MDIO01
    +VCC_3IN1
    SD1_DAT1 MS1_DAT1
    Use 0805 type and over 20 mils U24 MDIO02 SD1_DAT2 MS1_DAT2
    trace width on both side
    3 VIN VOUT 1 MDIO03 SD1_DAT3 MS1_DAT3
    4 VIN/CE VOUT 5
    +VCC_OUT +VCC_3IN1 MDIO04 SD1_CMD MS1_BS

    1U_0603_10V4Z
    1

    2
    C999 2 1
    GND

    C1000
    @ R947 MDIO05 SD1_CLK MS1_CLK
    D 1 2 0.1U_0402_16V4Z RT9701-PB_SOT23-5 D
    R946 2 150K_0402_5%
    @
    2
    MDIO06 SD1_WP
    0_0805_5% 1 1 @

    1
    C1002 MDIO07
    C1001
    10U_0805_10V4Z 0.1U_0402_16V4Z reserved power circuit MDIO08 MMC_DAT4 MS1_DAT4
    2 2
    mount JMB suggest MDIO09 MMC_DAT5 MS1_DAT5
    MDIO10 MMC_DAT6 MS1_DAT6
    +VCC_3IN1
    MDIO11 MMC_DAT7 MS1_DAT7
    MDIO12
    1 2 SDWP#_MMCWP# MDIO13
    R948 10K_0402_5% +1.8VS_CR
    20mil Refer JMB suggest 11/14 MDIO14
    1 2 XD_RB# 0.1U_0402_16V4Z 1 2 +1.8VS_CRR
    R949 10K_0402_5% 1 1 1 1 R950 @ 0_0805_5% CR1_LEDN SD1_LED# MS1_LED#
    C1003 C1004 C1005 C1006 CR1_PCTLN SD1_PCTL# MS1_PCTL#
    0.1U_0402_16V4Z
    2 2 2 2
    CR1_CD0 SD1_CD#
    10U_0805_10V4Z 1000P_0402_50V7K 10/23 Change net name to +3VS_CR by Vivian
    CR1_CD1 MS1_CD#
    U25
    40 mil
    +3VS_CR
    1 1 1 1
    3 5 C1009 C1010 C1011 C1007
    <23> CLK_PCIE_CARD# APCLKN APVDD
    <23> CLK_PCIE_CARD 4 APCLKP APV18 10
    30 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    TAV33 2 2 2 2 +3VS
    <29> PCIE_ITX_C_PRX_N1 9 APRXN 10/23 Add by Vivian
    <29> PCIE_ITX_C_PRX_P1 8 APRXP DV33 19 W=40mils
    C DV33 20 C
    C1008 1 2 0.1U_0402_10V7K PCIE_PTX_IRX_N1 11 44
    <29> PCIE_PTX_C_IRX_N1 APTXN DV33

    1
    C1012 1 2 0.1U_0402_10V7K PCIE_PTX_IRX_P1 12 18 +1.8VS_CR 1
    <29> PCIE_PTX_C_IRX_P1 APTXP DV18 C1642 C1643 R1356
    R951 1 2 8.2K_0402_5% APREXT 7
    DV18 37 12mil 1 1
    @ @ 0_0603_5%
    APREXT SDDATA0_MSDATA0 C1013 C1014 0.1U_0402_16V4Z 1U_0603_10V4Z
    12mil,length <250 mil MDIO0 48

    3
    2
    S
    +3VS 47 SDDATA1_MSDATA1 0.1U_0402_16V4Z

    2
    MDIO1 SDDATA2_MSDATA2 2 2 G
    1 2 38 PCIES_EN MDIO2 46 <37> CR_ON# 1 2 2
    R952 0_0402_5% 39 45 SDDATA3_MSDATA3 0.1U_0402_16V4Z R1355 @ 100K_0402_5% Q6
    Refer JMB suggest 11/09
    PCIES JMB385 MDIO3
    MDIO4 43 SDCMD_MSBS SI2301BDS_SOT23
    42 SDCLK_MSCLK R953 1 2 22_0402_5% SDCLK @
    MDIO5 SDWP#_MMCWP#
    D
    R1357
    41

    1
    MDIO6 XD_CLE R954 1 MSCLK +3VS_CR_R 1 +3VS_CR
    Change Pin definition for Rev:B MDIO7 40 2 22_0402_5% 2 +3VS_CR
    29 0_0603_5% W=40mils
    MDIO8 @
    <8,16,27,33,35,45> PLT_RST_BUF# 1 XRSTN MDIO9 28
    2 XTEST MDIO10 27 Damping need to close to IC
    <29> GPIO18 1 2 MDIO11 26
    R955 @ 0_0402_5% 25 XD_RE#
    +3VS MDIO12 XD_RB#
    @
    13
    14
    D3E_WAKEN MDIO13 23
    22 XD_ALE
    Strap pin for JMicro
    T83 PAD NC MDIO14
    34 +3VS
    R956 MSCD#_XDCD1 NC
    1 2 4.7K_0402_5% 15 CR1_CD1N NC 35
    R957 1 2 4.7K_0402_5% SDCD#_XDCD0# 16 36 1 2 XD_CLE
    CR1_CD0N NC R958 10K_0402_5%
    1 2 6
    <29> CR_WAKE#
    R959 @ 0_0402_5% +VCC_OUT 17 CR1_PCTLN
    APGND
    200K_0402_5%
    2 1
    R960
    XD_RE# 3 in 1 Card Reader
    40 mil GND 24
    31 2 1 XD_ALE
    GND 200K_0402_5% R961 JREAD1
    21 CR1_LEDN GND 32
    GND 33 +VCC_3IN1 6 VDD_SD
    SDDATA0_MSDATA0 9
    SDDATA1_MSDATA1 DAT0_SD
    10 DAT1_SD
    SDDATA2_MSDATA2
    JMB385-LGEZ0A_LQFP48_7X7
    Refer JMB suggest 11/09 SDDATA3_MSDATA3
    2
    3
    DAT2_SD
    SDCLK CD/DAT3_SD
    B 7 CLK_SD
    B
    SDWP#_MMCWP# 11
    Rev :B SDCMD_MSBS
    SDCD#_XDCD0#
    4
    WP_SD
    CMD_SD
    D22 1 CD_SD
    5 VSS_SD
    C1015 3 SDCD#_XDCD0# 8 VSS_SD
    2 1 1
    2 MSCD#_XDCD1
    270P_0402_50V7K SDDATA1_MSDATA1 19
    @ VCC_MS
    DAN202UT106_SC70-3 13 VCC_MS
    MSCLK 14
    @ MSCD#_XDCD1 SCLK_MS
    16 INS_MS
    SDDATA0_MSDATA0 18
    SDCMD_MSBS SDIO_MS
    20 BS_MS
    SDDATA3_MSDATA3 15
    SDDATA2_MSDATA2 RESERVED_MS
    17 RESERVED_MS
    21 VSS_MS
    12 VSS_MS
    22 GND
    23 GND
    +1.8V
    PROCO_MDR019-C0-1202
    CONN@

    1
    C1016
    @
    10/17 add for
    1U_0603_10V4Z JMB380
    3

    2
    S
    R962 1 2 100K_0402_5% 2
    G
    @
    The circuit need reserve for JMB385?
    <46,52> SUSP
    @ Q67 SDCLK 1 2 1 2
    C1018 SI2301BDS_SOT23
    @ D R963 C1017
    0.1U_0402_16V4Z W=40mils @ 100_0402_5% @ 100P_0402_50V8J
    1

    A +1.8VS_CRR A

    MSCLK 1 2 1 2

    R964 C1019
    @ 100_0402_5% @ 100P_0402_50V8J

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    JMB385 CardReader
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 32 of 56
    5 4 3 2 1
    5 4 3 2 1

    Max 340mA
    width > 60mil SROUT12
    R965 8102E@ 0_0603_5%
    AVDD12 Length < 200mil to Pin1 FB12
    L56 8111C@
    AVDD12 0.1U_0402_16V4Z R966 0_0603_5% 1 2
    1 1 1 1 1 1 4.7UH_1008HC-472EJFS-A_5%_1008 1
    C1020 C1021 C1022 C1023 C1024 C1025 C1026
    +3VALW VDD33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @
    8111C@ 8111C@ 0.1U_0402_16V4Z 22U_0805_6.3V6M
    Max 541mA R967 width > 40mil
    2 2 2 2 2 2
    22U_0805_6.3V6M
    8111C@
    2
    0.1U_0402_16V4Z VDD33
    D Bead current rating:600mA D
    0_0603_5% EVDD12

    0.1U_0402_16V4Z
    1 1 1 1 1 1 Inductor=4.7uH,600mA
    C1027 C1028 C1029 C1030 C1031 C1032 L57 SHI00004C00
    @ EVDD12 1 2
    22U_0805_6.3V6M 0.1U_0402_16V4Z 8111C@ MBK1608121YZF_0603

    D
    6 1 1 1
    2 2 2 2 2 2 C1033 C1034 C1035 Change PCB footprint of L56 from L_1008 to DELTA_1008HC-472EJFS-A_2P
    S

    4 5
    Q68 2 0.1U_0402_16V4Z 8102E@ 8111C@
    SI3445ADV-T1-E3_TSOP6 1 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R968 @ 0_0603_5% Change PCB footprint of L57 from L_0603 to R_0603
    @ AVDD33 2 2 2
    G

    width > 40mil R969


    3

    0_0603_5%
    @ R970 0_0603_5% AVDD33
    R971 1 210K_0402_5% 1 1
    8111C@ Max 340mA
    EN_WOL# <37>
    2 C1037 C1038
    C1036 CTRL12
    @ 0.1U_0402_16V4Z DVDD12
    0.1U_0402_16V4Z 2 2 8111C@
    1 0.1U_0402_16V4Z DVDD12 0.1U_0402_16V4Z 0.1U_0402_16V4Z R972 8102E@ 0_0603_5% CTRL12
    For soft start
    Andy 11/24 1 1 1 1 1 1
    C1039 C1040 C1041 C1042 C1043 C1044

    0.1U_0402_16V4Z
    2 2 2 2 2 2

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


    8111C@

    U26

    C
    <29> PCIE_PTX_C_IRX_P4 2 1 PCIE_PTX_IRX_P4 29 HSOP EEDO 45 EEDO C
    C1045 0.1U_0402_10V7K 47 EEDI
    EEDI/AUX
    <29> PCIE_PTX_C_IRX_N4 2 1 PCIE_PTX_IRX_N4 30 HSON EESK 48 EESK
    C1046 0.1U_0402_10V7K 44 EECS
    PCIE_ITX_C_PRX_P4 EECS
    <29> PCIE_ITX_C_PRX_P4 23 HSIP
    PCIE_ITX_C_PRX_N4 24
    <29> PCIE_ITX_C_PRX_N4 HSIN
    LED3 54
    55 LINK10 R973 1 2 0_0402_5%
    LAN_CLKREQ# R974 1 LED2
    <23> LAN_CLKREQ# 2 0_0402_5% CKREQB 33 CLKREQB LED1 56 LINKLED#
    LINKLED# <34>
    57 ACTIVITY#
    LED0 ACTIVITY# <34>
    CLK_PCIE_LAN 26
    <23> CLK_PCIE_LAN REFCLK_P
    CLK_PCIE_LAN# 27 3 MDI0+ VDD33
    <23> CLK_PCIE_LAN# REFCLK_N MDIP0 MDI0+ <34>
    4 MDI0-
    MDIN0 MDI0- <34>
    PLT_RST_BUF# 20 6 MDI1+
    <8,16,27,32,35,45> PLT_RST_BUF# PERSTB MDIP1 MDI1+ <34>

    1
    7 MDI1-
    MDIN1 MDI1- <34> VDD33
    width > 60mil 9 MDI2+ R975
    MDIP2 MDI2+ <34>
    SROUT12 1 10 MDI2- U27
    SROUT12 MDIN2 MDI2- <34>
    12 MDI3+ 3.6K_0402_5% EECS 1 8
    MDIP3 MDI3+ <34> CS VCC
    2 1 FB12 5 13 MDI3-
    MDI3- <34>
    EESK 2 7 1

    2
    C1047 0.01U_0402_16V7K FB12 MDIN3 EEDI SK NC C1048
    3 DI NC 6
    +3VS VDD33 R976 1 2 8111C@ 0_0402_5% ENSR 62 EEDO 4 5 @
    R977 1 ENSR DO GND
    2 @ 0_0402_5% DVDD12 21 DVDD12 0.1U_0402_16V4Z
    R978 2.49K_0402_1% RSET AT93C46-10SI-2.7_SO8 2
    64 RSET DVDD12 32
    1

    38 @
    R979 DVDD12
    DVDD12 43
    1K_0402_5% 49
    ICH_PCIE_WAKE# DVDD12
    <29,35,36> ICH_PCIE_WAKE# 19 LANWAKEB DVDD12 52
    B B
    2

    ISOLATEB ISOLATEB 36 ISOLATEB EVDD12


    EVDD12 22
    1

    R980 LAN_XTAL_IN 60
    EVDD12 28 Pin 11,14,32,38,52,59 are NC pins when use 8102E
    CKTAL1
    15K_0402_5% LAN_XTAL_OUT 61 16 VDD33
    CKTAL2 VDD33
    37
    2

    VDD33
    VDD33 46
    53 width > 40mil CTRL12
    VDD33
    65 EXPOSE_PAD
    10/09 change to SJ125P0M200 Length < 200mil R981 8111C@ 0_0603_5% VDD33
    VDDSR 63
    25 EGND
    LAN_XTAL_IN 2 AVDD33 1
    AVDD33 C1050
    31 EGND AVDD33 59 1
    C1049
    Y3 8 AVDD12 8111C@ 0.1U_0402_16V4Z
    LAN_XTAL_OUT DVDD12 R982 8102E@ 0_0603_5% AVDD12 22U_0805_6.3V6M 2
    1 2 15 NC AVDD12 11
    2 8111C@
    17 NC AVDD12 14
    18 58 R983 8111C@ 0_0603_5%
    NC AVDD12 R984 8102E@ 0_0603_5% DVDD12
    25MHz_20pF_6X25000017 34 NC
    1 1 35 NC
    AP 39 NC IGPIO 50
    C1051 C1052 40 51 U26
    NC OGPIO
    27P_0402_50V8J 27P_0402_50V8J 41 NC
    2 2
    42 NC
    RTL8111C-GR_QFN64_9X9
    A A
    8111C@
    8102E
    8102E@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    LAN-RTL8111C/RTL8102E
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 33 of 56
    5 4 3 2 1
    5 4 3 2 1

    D D

    T84 8111C@
    C1053 1 2 0.01U_0402_16V7K V_DAC 1 24 MCT3 R985 2 1 75_0402_5%
    MDI3- TCT1 MCT1 MDO3-
    <33> MDI3- 2 TD1+ MX1+ 23
    MDI3+ 3 22 MDO3+ 8111C@
    <33> MDI3+ TD1- MX1-
    C1054 1 2 0.01U_0402_16V7K 4 21 MCT2 R986 2 1 75_0402_5%
    8111C@ MDI2- TCT2 MCT2 MDO2-
    <33> MDI2- 5 TD2+ MX2+ 20
    MDI2+ 6 19 MDO2+
    <33> MDI2+ TD2- MX2-
    C1055 1 2 0.01U_0402_16V7K 7 18 MCT1 R987 2 1 75_0402_5%
    MDI1- TCT3 MCT3 MDO1-
    <33> MDI1- 8 TD3+ MX3+ 17
    MDI1+ 9 16 MDO1+
    <33> MDI1+ TD3- MX3-
    C1056 1 2 0.01U_0402_16V7K 10 15 MCT0 R988 2 1 75_0402_5% RJ45_PR
    8111C@ MDI0- TCT4 MCT4 MDO0-
    <33> MDI0- 11 TD4+ MX4+ 14
    MDI0+ 12 13 MDO0+
    <33> MDI0+ TD4- MX4-
    GSL5009LF
    C 8111C@ C

    9/18 Change T84 Value from 350uH_GSL5009LF to GSL5009LF


    Change T84 P/N fromSP050003T00 to SP050003T10

    Lan Conn.
    2 1 <EMI> JP16
    T85 C1057 470P_0402_50V7K 12
    VDD33 Amber LED+
    MDI1- 1 16 MDO1- ACTIVITY# 1 2 LAN_ACT# 11
    MDI1+ RD+ RX+ MDO1+ <33> ACTIVITY# Amber LED-
    2 RD- RX- 15 R989 300_0402_5% 10mil 16
    V_DAC 3 14 MCT1 MDO3- SHLD2
    CT CT 8 PR4-
    4 NC NC 13 15
    5 12 MDO3+ SHLD1
    NC NC 7 PR4+
    V_DAC 6 11 MCT0
    MDI0- CT CT MDO0-
    7 TD+ TX+ 10 MDO1- 6
    B MDI0+ 8 9 MDO0+ PR2- B
    TD- TX-
    MDO2- 5 PR3-
    NS0013LF MDO2+ 4
    8102E@ PR3+
    MDO1+ 3 PR2+
    Change T85 Value from 350uH_NS0013LF to NS0013LF MDO0- 2 PR1-
    SHLD2 14
    MDO0+ 1 PR1+
    10mil SHLD1 13
    LINKLED# 1 2 LAN_LINK# 10
    <33> LINKLED# Green LED-
    R990 300_0402_5%
    VDD33 9 Green LED+
    2 1 <EMI>
    C1058 470P_0402_50V7K TYCO_3-440470-4
    CONN@
    C1059
    RJ45_PR 1 2 <EMI> LANGND
    1 1
    1000P_1206_2KV7K
    C1060 C1061
    0.1U_0402_16V4Z 4.7U_0805_10V4Z
    2 2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    LAN CONNECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 34 of 56
    5 4 3 2 1
    A B C D E

    Mini-Express Card for TV Tuner +3VS +1.5VS +3VS

    1 1 1 1 1 1
    C1062 C1063 C1064 C1065 C1066 C1067
    @ @
    4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 2

    1 JMIN1 1
    ICH_PCIE_WAKE# 1 2 +3VS
    <29,33,36> ICH_PCIE_WAKE# 1 2
    WLAN_ACTIVE 3 4
    <39> WLAN_ACTIVE 3 4
    BT_ACTIVE 5 6 +1.5VS
    <39> BT_ACTIVE 5 6
    +3VS 1 2 3G_CLKREQ# 7 7 8 8
    R991 10K_0402_5% 9 10
    <23> 3G_CLKREQ# 9 10
    <23> CLK_PCIE_3G# 11 11 12 12
    <23> CLK_PCIE_3G 13 13 14 14
    15 15 16 16
    11/3 Change signal of EC_TX_P80_DATA from <37> EC_TX_P80_DATA EC_TX_P80_DATA 17 18
    17 18 MINI2_OFF#
    pin 49 to pin 17 19 19 20 20
    21 22 PLT_RST_BUF#
    21 22 PLT_RST_BUF# <8,16,27,32,33,45>
    PCIE_PTX_C_IRX_N2 23 24 +3VS
    <29> PCIE_PTX_C_IRX_N2 23 24
    PCIE_PTX_C_IRX_P2 25 26
    <29> PCIE_PTX_C_IRX_P2 25 26
    27 27 28 28
    29 30 ICH_SMBCLK
    PCIE_ITX_C_PRX_N2 29 30 ICH_SMBDATA
    <29> PCIE_ITX_C_PRX_N2 31 31 32 32
    PCIE_ITX_C_PRX_P2 33 34
    <29> PCIE_ITX_C_PRX_P2 33 34
    Vcc 3.3V +/- 8% 35 36 USB20_R_N3
    35 36 USB20_R_P3
    37 37 38 38
    Peak Icc 2750mA 39 40
    39 40
    with max supply droop 50mA +3VS 41 41 42 42
    (WWAN_LED#)
    43 43 44 44 WLAN_LED# <45>
    Average Icc 1000mA 45 45 46 46
    47 47 48 48
    49 49 50 50
    <37> EC_RX_P80_CLK EC_RX_P80_CLK 51 52
    +3VS 51 52
    53 GND1 GND2 54
    11/4 Change signal from EC_TX_P80_CLK to
    1

    R992
    EC_RX_P80_CLK FOX_AS0B226-S56N-7F
    2 2
    CONN@
    10K_0402_5%
    @
    2

    WCM2012F2SF-121T04_0805
    MINI2_OFF# USB20_R_N3 4 USB20_N3
    4 3 3 USB20_N3 <29>
    1

    D
    Q69 2 TV_ON# USB20_R_P3 1 2 USB20_P3
    TV_ON# <37> 1 2 USB20_P3 <29>
    SSM3K7002FU_SC70-3 G
    S L58 <EMI> <EMI>
    3

    1 2 R993 0_0402_5%
    1 2 R994 0_0402_5%
    <EMI>

    Mini-Express Card for WLAN


    MINI_VCC +1.5VS +3VS
    Change PCB footprint of L59 from L_0805 to R_0805
    JMIN2 L59
    ICH_PCIE_WAKE# 1 2 MINI_VCC 1 2
    <29,33,36> ICH_PCIE_WAKE# 1 2
    WLAN_ACTIVE 3 4 KC FBM-L11-201209-221LMAT_0805
    <39> WLAN_ACTIVE 3 4
    BT_ACTIVE 5 6
    <39> BT_ACTIVE 5 6
    WLAN_CLKREQ# 7 8
    <23> WLAN_CLKREQ# 7 8
    9 9 10 10
    CLK_PCIE_WLAN# 11 12 +3VS
    <23> CLK_PCIE_WLAN# 11 12
    CLK_PCIE_WLAN 13 14
    3 <23> CLK_PCIE_WLAN 13 14 3
    15 15 16 16
    <37> EC_TX_P80_DATA EC_TX_P80_DATA 17 18
    17 18

    1
    19 20 MINI_RF_OFF#
    19 20 PLT_RST_BUF# R995
    10/31 Add signal of EC_TX_P80_DATA 21 21 22 22
    23 24 MINI_VCC
    <29> PCIE_PTX_C_IRX_N3 23 24
    25 26 10K_0402_5%
    <29> PCIE_PTX_C_IRX_P3 25 26
    27 28

    2
    27 28 ICH_SMBCLK
    29 29 30 30 ICH_SMBCLK <23,29,36>
    31 32 ICH_SMBDATA MINI_RF_OFF#
    <29> PCIE_ITX_C_PRX_N3 31 32 ICH_SMBDATA <23,29,36>
    <29> PCIE_ITX_C_PRX_P3 33 33 34 34

    1
    USB20_R_N8 D
    35 35 36 36
    37 38 USB20_R_P8 Q70 2 RF_ON#
    37 38 RF_ON# <37>
    MINI_VCC 39 40 SSM3K7002FU_SC70-3 G
    39 40
    41 42 S

    3
    41 42 WLAN_LED#
    43 43 44 44 WLAN_LED# <45>
    45 45 46 46
    47 47 48 48
    @ 49 49 50 50
    <37> EC_RX_P80_CLK EC_RX_P80_CLK 51 52
    WCM2012F2SF-121T04_0805 51 52
    USB20_R_P8 4 USB20_P8 10/31 Add signal of EC_TX_P80_CLK R996
    4 3 3 USB20_P8 <29> 53 GND1 GND2 54
    1 2 +5VS
    11/4 Change signal from EC_TX_P80_CLK to
    USB20_R_N8 1 2 USB20_N8 FOX_AS0B226-S56N-7F 100K_0402_5%
    1 2 USB20_N8 <29> EC_RX_P80_CLK
    CONN@
    L60 <EMI> <EMI> +3VS
    1 2 R997 0_0402_5% Please place these caps between JMIN1 and JMIN2
    1 2 R998 0_0402_5%
    <EMI>
    1 ICH_SMBCLK C1068 1 2 @ 100P_0402_50V8J
    C1069
    ICH_SMBDATA C1070 1 2 @ 100P_0402_50V8J
    4 MINI_VCC +1.5VS 0.1U_0402_16V4Z 4
    2

    1 1 1 1 1 1
    C1071 C1072 C1073 C1074 C1075 C1076
    @ @
    0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
    2 2 2 2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Mini-Card/Kill SWITCH
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 35 of 56
    A B C D E
    A B C D E

    New Card Power Switch

    New Card +3VS_CARD1

    1 1
    +1.5VS C1077 C1078
    1 C1079 U29 @ 1
    2 1 0.1U_0402_16V4Z 12 1.5Vin 1.5Vout 11 +1.5VS_CARD1 0.1U_0402_16V4Z 4.7U_0805_10V4Z
    2 2
    14 1.5Vin 1.5Vout 13
    +3VS
    C1080
    2 1 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_CARD1
    4 5 +1.5VS_CARD1
    3.3Vin 3.3Vout
    2 1 0.1U_0402_16V4Z
    +3VALW C1081 17 15 +3VALW_CARD1
    AUX_IN AUX_OUT
    1 1
    SYSON PCI_RST# 6 19 C1082 C1083
    <27,37,40> PCI_RST# SYSRST# OC# @
    1 SYSON 20 8 PERST1# 0.1U_0402_16V4Z 4.7U_0805_10V4Z
    <37,46,51,52> SYSON SHDN# PERST# 2 2
    @
    C1551 SUSP# 1 16
    <37,46,51,53> SUSP# STBY# NC
    100P_0402_50V8J
    2 CP_PE#
    +3VALW 2 1 10 CPPE# GND 7
    R999 100K_0402_5%
    2 1 CP_USB# 9
    R1000 100K_0402_5% CPUSB#
    18 +3VALW_CARD1
    RCLKEN
    G577NSR91U TQFN 20P
    internal pull high to 3.3Vaux-in 1 1
    C1084 C1085
    EC need setting at Hi-Z & output Low @
    0.1U_0402_16V4Z 4.7U_0805_10V4Z
    2 2
    10/20 Change to value to G577NSR91U TQFN 20P
    2 2

    New Card Socket (Left/TOP)


    Copied from HAL10
    JEXP1

    1 GND
    <29> USB20_N10 2 USB_D-
    <29> USB20_P10 3 USB_D+
    CP_USB# 4 CPUSB#
    5 RSV
    6 RSV
    <23,29,35> ICH_SMBCLK 7 SMB_CLK
    <23,29,35> ICH_SMBDATA 8 SMB_DATA
    +1.5VS_CARD1 9 +1.5V
    10 +1.5V
    3 3
    <29,33,35> ICH_PCIE_WAKE# 11 WAKE#
    +3VALW_CARD1 12 +3.3VAUX
    PERST1# 13 PERST#
    +3VS_CARD1 14 +3.3V
    15 +3.3V
    EXP_CLKREQ# 16
    <23> EXP_CLKREQ# CLKREQ#
    CP_PE# 17
    <29> CP_PE# CPPE#
    <23> CLK_PCIE_EXP# 18 REFCLK-
    <23> CLK_PCIE_EXP 19 REFCLK+
    20 GND
    <29> PCIE_PTX_C_IRX_N5 21 PERn0
    <29> PCIE_PTX_C_IRX_P5 22 PERp0
    23 GND
    <29> PCIE_ITX_C_PRX_N5 24 PETn0
    <29> PCIE_ITX_C_PRX_P5 25 PETp0
    26 GND
    27
    28
    GND
    GND
    Need checking layout !!
    SANTA_131851-1_LT
    CONN@

    Change connector from SANTA_130810-1 to SANTA_13185-1_LT

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    NEW CARD
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 36 of 56
    A B C D E
    5 4 3 2 1

    +3VALW +EC_DVCC +3VALW +3VALW


    10/12 Add MB2 ID need check
    L61

    1
    1 2 +EC_AVCC
    +3VALW 1 2 FBM-11-160808-601-T_0603 +EC_AVCC
    FBM-11-160808-601-T_0603 R1001 R1002
    L62 @
    C1086
    2 1
    C1087 1 1 1 1 1 1
    RC 100K_0402_5%
    Rb 47K_0402_5%

    0.1U_0402_16V4Z
    C1088

    0.1U_0402_16V4Z
    C1089

    0.1U_0402_16V4Z
    C1090

    0.1U_0402_16V4Z
    C1091

    1000P_0402_50V7K
    C1092

    1000P_0402_50V7K
    C1093
    RB@

    2
    0.1U_0402_16V4Z 1000P_0402_50V7K MB2_ID MB_ID
    1 ECAGND 2
    1 2

    1
    L63 FBM-11-160808-601-T_0603 2 2 2 2 2 2
    1 1
    C1094 R1003 C1095 R1004
    @ @ @ @
    D
    0.1U_0402_16V4Z
    Rd 0_0402_5% 0.1U_0402_16V4Z
    Ra 0_0402_5%
    D

    111
    125
    2 2

    22
    33
    96

    67

    2
    9
    U30

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AVCC
    1 2
    R1005 0_0402_5%
    +5VS
    GATEA20 1 21 INVT_PWM
    <28> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <25>
    KB_RST# 2 1 2 23 BEEP# TP_CLK R1007 1 2 4.7K_0402_5%
    <28> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <41>
    D23 @ <29,45> SERIRQ SERIRQ 3 26 VGA_THERM#
    SERIRQ# FANPWM1/GPIO12 VGA_THERM# <17>
    CH751H-40PT_SOD323-2 LPC_FRAME# 4 27 ACOFF TP_DATA R1008 1 2 4.7K_0402_5%
    <28,40,45> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <49>
    <28,40,45> LPC_AD3 LPC_AD3 5
    C1096 LPC_AD2 LAD3 ECAGND
    <28,40,45> LPC_AD2 7 LAD2 PWM Output 1 2
    2 1 2 @ 1 <28,40,45> LPC_AD1 LPC_AD1 8 63 BATT_TEMP C1097 0.01U_0402_16V7K
    LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <48>
    R1009 10_0402_5% LPC_AD0 BATT_OVP
    @ 22P_0402_50V8J
    <28,40,45> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
    ADP_I
    BATT_OVP <49>
    ADP_I/AD2/GPIO3A 65 ADP_I <49>
    CLK_PCI_EC 12 AD Input 66 +3VALW
    <23> CLK_PCI_EC PCICLK AD3/GPIO3B
    PCI_RST# 13 75 MB2_ID
    <27,36,40> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42
    R1011 1 2 EC_RST# 37 76 MB_ID
    +3VALW ECRST# SELIO2#/AD5/GPIO43
    47K_0402_5% EC_SCI# 20 CIR_DET# R1012 2 1 10K_0402_5%
    <29> EC_SCI# SCI#/GPIO0E
    1 1 @ 2 38
    <29,45> PM_CLKRUN# CLKRUN#/GPIO1D
    C1098 R1006 0_0402_5% 68 DAC_BRIG P_USB# R1013 2 1 10K_0402_5%
    DAC_BRIG/DA0/GPIO3C DAC_BRIG <25>
    1 2 70 EN_FAN1
    +3VS <45> FP_ON# EN_DFAN1/DA1/GPIO3D EN_FAN1 <5>
    0.1U_0402_16V4Z R1353 0_0402_5% DA Output 71 IREF RCIRRX R1014 1 2 10K_0402_5%
    2 IREF/DA2/GPIO3E IREF <49>
    KSI0 55 72 CHGVADJ
    KSI0/GPIO30 DA3/GPIO3F CHGVADJ <49>
    1 @ 2 PM_CLKRUN# 10/23 Add by Vivian KSI1 56 TP_DISABLE# R1015 1 2 10K_0402_5%
    R1016 8.2K_0402_5% KSO[0..15] KSI2 KSI1/GPIO31
    <38> KSO[0..15] 57 KSI2/GPIO32
    KSI3 58 83 CLK_GUEST_R L64 1 2 0_0402_5% CLK_GUEST
    KSI[0..7] KSI3/GPIO33 PSCLK1/GPIO4A CLK_GUEST <38>
    KSI4 59 84 DATA_GUEST_R L65 1 2 0_0402_5% DATA_GUEST
    <38> KSI[0..7] KSI4/GPIO34 PSDAT1/GPIO4B DATA_GUEST <38>
    +3VALW 2 1 KSI5 60 85 WOW_VIDEO_LED# PCI_RST# R1017 1 2 100K_0402_5%
    KSI5/GPIO35 PSCLK2/GPIO4C WOW_VIDEO_LED# <38>
    R1018 10K_0402_5% KSI6 61 PS2 Interface 86 POWER_USB_LED#
    C KSI6/GPIO36 PSDAT2/GPIO4D POWER_USB_LED# <38> C
    EC_PME# KSI7 62 87 TP_CLK KB926 SPI STRAP PIN CLK_GUEST
    KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <39>
    KSO0 TP_DATA
    <27> PCI_PME# 1 2 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <39> No stuff when use KB926C0
    R1021 0_0402_5% +3VALW KSO1 40 1 2 DATA_GUEST
    KSO1/GPIO21 KILL_SW# <38>
    KSO2 41 R1019 1 2 0_0402_5% 1 1
    KSO3 KSO2/GPIO22 R1020 100P_0402_50V8J C1099 C1100
    42 KSO3/GPIO23 SDICS#/GPXOA00 97
    1 2 KSO1 KSO4 43 98 EN_WOL# @ @
    KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# <33>
    R1351 47K_0402_5% KSO5 TP_DISABLE#_LED 22P_0402_50V8J 22P_0402_50V8J
    +5VALW KSO2 KSO6
    44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
    LID_SW# <EMI> 2 2 <EMI>
    Need Check 1 2 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# <40>
    R1352 47K_0402_5% KSO7 46 SPI Device Interface
    KSO8 KSO7/GPIO27
    47 KSO8/GPIO28
    KSO9 48 119 FRD#SPI_SO
    KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <39>
    1 2 EC_SMB_CK1 L66 1CYPRESS@
    2 0_0402_5% CLK_GUEST KSO10 49 120 FWR#SPI_SI EC_RSMRST#
    R1023 4.7K_0402_5% KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK BEEP#
    50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126
    1 2 EC_SMB_DA1 L67 1CYPRESS@
    2 0_0402_5% DATA_GUEST KSO12 51 128 FSEL#SPICS# SYSON
    R1024 4.7K_0402_5% KSO13 KSO12/GPIO2C SPICS# EC_SCI#
    52 KSO13/GPIO2D
    1 2 CLK_GUEST_R KSO14 53 EC_THERM#
    R1025 10K_0402_5% KSO15 KSO14/GPIO2E RCIRRX SERIRQ
    54 KSO15/GPIO2F CIR_RX/GPIO40 73 RCIRRX <40>

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J
    1 2 DATA_GUEST_R DDR3_SM_PWROK 81 74 MCH_TSATN#_EC
    <8> DDR3_SM_PWROK KSO16/GPIO48 CIR_RLC_TX/GPIO41 MCH_TSATN#_EC <8>
    R1026 10K_0402_5% TP_DISABLE# 82 89 FSTCHG
    KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <49>
    1 2 ACK_GUEST_R 90 CHARGE_LED0#
    BATT_CHGI_LED#/GPIO52 CHARGE_LED0# <45>
    R1027 10K_0402_5% 91 CAPS_LED# 1 1 1 1 1 1
    CAPS_LED#/GPIO53 CAPS_LED# <38>
    <39,48> EC_SMB_CK1 EC_SMB_CK1 77 GPIO 92 CHARGE_LED1#
    SCL1/GPIO44 BATT_LOW_LED#/GPIO54 CHARGE_LED1# <45>
    +3VS <39,48> EC_SMB_DA1 EC_SMB_DA1 78 93 PWR_LED#
    SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED# <38,45>
    <5,17> EC_SMB_CK2 EC_SMB_CK2 79 SM Bus 95 SYSON
    SCL2/GPIO46 SYSON/GPIO56 SYSON <36,46,51,52> 2 2 2 2 2 2
    1 2 EC_SMB_CK2 <5,17> EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
    SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <54>
    R1028 2.2K_0402_5% 127 ACIN
    AC_IN/GPIO59 ACIN <29,47>
    1 2 EC_SMB_DA2 C1103 C1104 C1105 C1101 C1102 C1106
    R1029 2.2K_0402_5% 1 1 @ @ @ @ @ @
    C1107 C1108 PM_SLP_S3# 6 100 EC_RSMRST#
    <29> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <29>
    @ @ PM_SLP_S5# 14 101 EC_LID_OUT# ICH_PWROK
    <29> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <29>
    100P_0402_50V8J 100P_0402_50V8J EC_SMI# 15 102 EC_ON PBTN_OUT#
    2 2 <29> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <40>
    B WOW_AUDIO_LED# 16 103 TV_ON# EN_FAN1 B
    <38> WOW_AUDIO_LED# LID_SW#/GPIO0A EC_SWI#/GPXO06 TV_ON# <35>
    CR_ON# 17 104 ICH_PWROK EC_ON
    <32> CR_ON# SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_PWROK <8,29>
    CAM_ON# 18 GPO 105 BKOFF# ON/OFF#
    <45> CAM_ON# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <25>
    <38> P_USB# P_USB# 19 GPIO 106 RF_ON# TV_ON#
    EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_ON# <35>

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J
    10/23 Add outpu signals of CR_ON# and CAM_ON# USB2_ON# 25 107 BT_ON#
    <40> USB2_ON# EC_THERM#/GPIO11 GPXO10 BT_ON# <39>
    FAN_SPEED1 28 108 VGA_AC_DET
    <5> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 VGA_AC_DET <17>
    ACK_GUEST_R 29
    EC_TX_P80_DATA FANFB2/GPIO15
    <35> EC_TX_P80_DATA 30 EC_TX/GPIO16 1 1 1 1 1 1
    <35> EC_RX_P80_CLK EC_RX_P80_CLK 31 110 PM_SLP_S4#
    EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# <29>
    1 2 SUSP# ON/OFF# 32 112 ENBKL
    <40> ON/OFF# ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <25>
    C1109 100P_0402_50V8J SM_KEY_LED# 34 114 CIR_DET#
    <38> SM_KEY_LED# PWR_LED#/GPIO19 GPXID3 CIR_DET# <40> 2 2 2 2 2 2
    @ NUM_LED# 36 GPI 115 EC_THERM#
    <38> NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <29>
    116 SUSP# C1110 C1111 C1112 C1113 C1114 C1115
    GPXID5 SUSP# <36,46,51,53>
    117 PBTN_OUT# @ @ @ @ @ @
    GPXID6 PBTN_OUT# <29>
    118 EC_PME#
    ACK_GUEST 1 GPXID7
    <38> ACK_GUEST 2 ACK_GUEST_R XCLKI 122 XCLK1
    SMT1-05_4P
    R1030 0_0402_5% XCLKO 123 124 SW6 BATT_TEMP C1116 1 2 @ 100P_0402_50V8J
    XCLK0 V18R TP_DISABLE#
    2 2 1 3
    AGND

    @ 12/8 Add by Vivian BATT_OVP C1117 1 2 @ 100P_0402_50V8J


    GND
    GND
    GND
    GND
    GND

    SPI_CS# 1 2 FSEL#SPICS# C1118 C1665 2 4


    <39> SPI_CS#
    R1031 0_0402_5% R1033 ACIN C1119 1 2 100P_0402_50V8J
    SPI_CLK_R 1 2 SPI_CLK XCLKO 1 @ 2 XCLKI KB926QFD3 LQFP 128P 4.7U_0805_10V4Z 1 1 0.1U_0402_16V4Z
    <39> SPI_CLK_R
    11
    24
    35
    94
    113

    69

    6
    5
    R1032 0_0402_5% 20M_0603_5% VR_ON C1120 1 2 @ 100P_0402_50V8J
    SPI_SI 1 2 FWR#SPI_SI
    <39> SPI_SI
    ECAGND

    R1034 0_0402_5% ENBKL C1121 1 2 470P_0402_50V7K

    1 1 R1170 FSTCHG C1122 1 2 @ 100P_0402_50V8J


    820_0402_5%
    EC DEBUG PORT
    4

    C1123 C1124 +5VS 1 2 2 1 LED7 TP_DISABLE#_LED ACK_GUEST C1125 1 2 @ 100P_0402_50V8J


    15P_0402_50V8J 15P_0402_50V8J 1/15 Use KB926D3
    OSC

    OSC

    JP17 2 2 HT-191NB_BLUE_0603 ADP_I C1126 1 2 @ 100P_0402_50V8J


    A +3VALW 1 X2 10/30 add A
    EC_TX_P80_DATA 1 EC_SMB_DA1 C1127
    2 2 1 2 @ 100P_0402_50V8J
    EC_RX_P80_CLK VGA_THERM# C1648 1 470P_0402_50V7K
    NC

    NC

    3 3 2
    4 EC_SMB_CK1 C1128 1 2 @ 100P_0402_50V8J
    4 FAN_SPEED1 C1652 2 1 470P_0402_50V7K
    3

    ACES_85205-0400
    DBCONN@
    32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ENE-KB926
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 37 of 56
    5 4 3 2 1
    5 4 3 2 1

    KSI[0..7]
    INT_KBD Conn. KSO[0..15]
    KSI[0..7] <37>

    KSO[0..15] <37>

    JP4
    KSI1 1
    KSI7 1
    2 2
    KSI6 3
    KSO9 3
    4 4
    KSI4 5 KSI4 C1234 1 2 100P_0402_50V8J KSO6 C1246 1 2 100P_0402_50V8J
    KSI5 5 KSI5 C1235 100P_0402_50V8J KSO3 C1247 100P_0402_50V8J
    6 6 1 2 1 2
    D KSO0 7 KSO0 C1236 1 2 100P_0402_50V8J KSO12 C1248 1 2 100P_0402_50V8J D
    KSI2 7 KSI2 C1237 100P_0402_50V8J KSO13 C1249 100P_0402_50V8J
    8 8 1 2 1 2
    KSI3 9
    KSO5 9
    10 10
    KSO1 11
    KSI0 11
    12 12
    KSO2 13 KSI1 C1238 1 2 100P_0402_50V8J KSI3 C1250 1 2 100P_0402_50V8J
    KSO4 13 KSI7 C1239 100P_0402_50V8J KSO5 C1251 100P_0402_50V8J
    14 14 1 2 1 2
    KSO7 15 KSI6 C1240 1 2 100P_0402_50V8J KSO1 C1252 1 2 100P_0402_50V8J
    KSO8 15 KSO9 C1241 100P_0402_50V8J KSI0 C1253 100P_0402_50V8J
    16 16 1 2 1 2
    KSO6 17
    KSO3 17
    18 18
    KSO12 19
    KSO13 19
    20 20
    KSO14 21 KSO2 C1242 1 2 100P_0402_50V8J KSO14 C1254 1 2 100P_0402_50V8J
    KSO11 21 KSO4 C1243 100P_0402_50V8J KSO11 C1255 100P_0402_50V8J
    22 22 1 2 1 2
    KSO10 23 KSO7 C1244 1 2 100P_0402_50V8J KSO10 C1256 1 2 100P_0402_50V8J
    KSO15 23 KSO8 C1245 100P_0402_50V8J KSO15 C1257 100P_0402_50V8J
    24 24 1 2 1 2
    25 25
    GND 27
    GND 26

    ACES_88502-2501
    CONN@

    C C

    Power USB Board Conn Fun conn Kill SWITCH


    @
    C485
    +3VALW R1162 0_0603_5%
    2 1 +5VALW
    +5VALW R1163 0_0603_5% W=40milsJP5 <EMI> @ 0.1U_0402_16V4Z

    +PWR_VCC 1
    ON/OFFBTN# 1
    <40> ON/OFFBTN#
    D_P_USB#
    2 2 W=40mils
    3 3
    PWR_LED# 4 +3VALW R1035 2 @ 1 0_0603_5% +FUN_VCC
    <37,45> PWR_LED# 4
    POWER_USB_LED# 5 +5VALW R1036 2 1 0_0603_5%
    <37> POWER_USB_LED# 5
    6 6
    7 JP6 +3VALW
    GND
    8 GND 1 1
    CLK_GUEST 2
    <37> CLK_GUEST 2
    ACES_85201-06051 DATA_GUEST 3
    <37> DATA_GUEST 3
    ACK_GUEST 4
    <37> ACK_GUEST 4

    2
    WOW_AUDIO_LED# 5
    <37> WOW_AUDIO_LED# 5
    WOW_VIDEO_LED# 6 D37 +3VALW
    <37> WOW_VIDEO_LED# 6
    7 DAN217_SC59
    7

    2
    B SM_KEY_LED# @ B
    <37> SM_KEY_LED# 8 8
    +3VALW 9 R1151
    GND
    10

    1
    GND 100K_0402_5%
    1

    ACES_85201-08051

    1
    R1037 CONN@ KILL_SW#
    KILL_SW# <37>
    10K_0402_5%
    2

    D24
    2 P_USB#
    P_USB# <37>

    3
    D_P_USB# 1
    3 51_ON#

    3
    51_ON# <40,47>
    ACK_GUEST C1129 1 2 @ 100P_0402_50V8J
    DAN202UT106_SC70-3
    SW5
    1BS003-1211L_3P

    LED Board Conn


    @
    +3VS R1164 0_0603_5%

    +5VS R1165 0_0603_5% W=40mils


    A A
    JP10
    +LED_VCC 1 5
    CAPS_LED# 15
    <37> CAPS_LED# 2 26 6
    NUM_LED# 3
    <37> NUM_LED# 3
    4 4
    ACES_85201-0405 Security Classification Compal Secret Data Compal Electronics, Inc.
    CONN@ 2008/07/15 2009/07/15 Title
    Issued Date Deciphered Date
    KB/SW/PW/Fun Conn
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 38 of 56
    5 4 3 2 1
    +3VALW +5VALW
    16M SPI ROM 8M SPI ROM
    2 @ 1 EEPROM_VCC
    For EC+BIOS+VBIOS For iTPM+HDCP
    R1038 0_0603_5% +3VALW

    2 @ 1
    R1039 0_0603_5% 1 20mils
    +3VALW C1131 U31 @
    @ 8 4
    0.1U_0402_16V4Z VCC VSS
    20mils 2
    1 3 W
    EEPROM_VCC EEPROM_VCC EEPROM_VCC C1133 U32
    8 VCC VSS 4 7 HOLD
    @ 0.1U_0402_16V4Z

    1
    C1132 1 2 ICH_SPI_CS0#_R
    2 0.1U_0402_16V4Z 3 W <29> ICH_SPI_CS0#_R 1 S
    1 @ 2 EC_SMB_CK1 R1042
    R1040 4.7K_0402_5% @ 7 ICH_SPI_CLK_R 6
    HOLD <29> ICH_SPI_CLK_R C
    1 @ 2 EC_SMB_DA1 100K_0402_5%
    R1041 4.7K_0402_5% U33 @ SPI_CS# 1 ICH_SPI_MOSI_R 5 2 ICH_SPI_MISO_R @
    <37> SPI_CS# <29> ICH_SPI_MOSI_R ICH_SPI_MISO <29>

    2
    S D Q R1043 15_0402_5%
    8 VCC A0 1
    7 2 SPI_CLK_R 6 SST25LF080A_SO8-200mil
    WP A1 <37> SPI_CLK_R C
    12/28 Add <37,48> EC_SMB_CK1 6 SCL A2 3
    SPI_SI SPI_SO 2
    <37,48> EC_SMB_DA1 5 SDA GND 4 <37> SPI_SI 5 D Q 2 1 FRD#SPI_SO <37>
    R1044 0_0402_5%
    AT24C16AN-10SU-2-7_SO8 MX25L1605AM2C-12G SO8

    10/20 Change value of U32 to MX25L1605AM2C-12G SO8 follow CRB Check

    1
    R1045 12/15 change from 15 to 0 ohm' SD028150A80
    @
    100K_0402_5%

    2
    0206 => change PN to SA00001N800
    12/19 change pn to SA00001MP00 ( original part EOL )
    12/25 change back to SA024160140 ( Samples can not on time )

    Bluetooth Conn. To TP/B Conn.


    Need to check BT pin definition again!
    9/20 modified this block JP7
    +5VS 1 1
    <37> TP_CLK TP_CLK 2
    TP_DATA 2
    <37> TP_DATA 3 3
    +5VS SWL# 4
    SWR# 4
    5 5
    @ 6 6
    7 GND
    1

    WCM2012F2SF-121T04_0805 8
    R1046 GND
    4 4 3 3
    ACES_85201-06051
    10K_0402_5% +BT_VCC 10/17 modify pin define,need check.
    1 2
    2

    1 2 JP8
    BT_LED# L70 <EMI> 1
    <45> BT_LED# 1 +5VS
    BT_ACTIVE 2
    <35> BT_ACTIVE 2
    <29> USB20_P6 USB20_P6 1 <EMI> 2 USB20_R_P6 3 SWR# TP_DATA
    3
    1

    D R1047 1
    <29> USB20_N6 USB20_N6 2 0_0402_5% USB20_R_N6 4 4
    Q71 2 BTON_LED R1048 <EMI> 0_0402_5% 5 SWL# TP_CLK C1134
    G WLAN_ACTIVE 5
    SSM3K7002FU_SC70-3 <35> WLAN_ACTIVE 6 6

    3
    S 7 0.1U_0402_16V4Z
    3

    7
    1

    8 8
    9 D25 D39
    R1049 GND1 @ @
    10 GND2
    10K_0402_5% PSOT24C_SOT23 PSOT24C_SOT23
    MOLEX_53780-0870
    2

    1
    CONN@

    C486 Update Footprint


    2 1 +BT_VCC
    <EMI> @ 0.1U_0402_16V4Z
    SW2

    6
    5
    SWL# 2 4

    Left Switch 1 3

    SMT1-05_4P

    +3VALW

    1
    C1135 C1136 SW3

    6
    5
    0.1U_0402_16V4Z 1U_0603_10V4Z SWR# 2 4
    3

    2
    S
    G
    <37> BT_ON# 1
    R1050
    2
    100K_0402_5%
    2
    Q72
    Right Switch 1 3

    SI2301BDS_SOT23 SMT1-05_4P
    D
    W=40mils
    1

    +BT_VCC

    1
    C1137 C1138
    @
    4.7U_0805_10V4Z
    2
    0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    BIOS, TP & BT Connector
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 39 of 56
    A B C D E

    ON/OFF switch FOR LPC DEBUG PORT USB IO 2 Conn. +USB_VCCA


    TOP Side
    12/4 Change D14 to correct symbols
    2 1
    J4 @ JOPEN
    2 1
    J5 @ JOPEN +3VALW JP18
    Bottom Side +3VS
    1 1
    <29> USB20_N9 2 2
    <29> USB20_P9 3 3 G1 5

    2
    4 4 G2 6
    R1051
    ACES_88266-04001
    100K_0402_5% CONN@
    1 JP9 +USB_VCCA 1
    W=40mils

    1
    D26 1
    ON/OFF# 1 CLK_PCI_DB +USB_VCCA
    2 ON/OFF# <37> 2 2 CLK_PCI_DB <23>
    ON/OFFBTN# 1 3
    <38> ON/OFFBTN# 3
    3 51_ON# 51_ON# <38,47> 4 LPC_AD0 1 1
    4 LPC_AD0 <28,37,45>
    5 LPC_AD1 C1641 C1637
    5 LPC_AD1 <28,37,45>
    DAN202UT106_SC70-3 6 LPC_AD2
    6 LPC_AD2 <28,37,45>
    7 LPC_AD3 470P_0402_50V7K 10U_0805_10V4Z
    Power Button 7
    8 8 LPC_FRAME#
    LPC_AD3 <28,37,45>
    LPC_FRAME# <28,37,45>
    2 2

    9 9
    10 PCI_RST# 10/27 Remove C1640 by Vivian
    10 PCI_RST# <27,36,37>

    1
    2 GND 11
    C1139 D27 12 1
    GND C1140
    1000P_0402_50V7K RLZ20A_LL34 ACES_85201-1005N @ +5VALW +USB_VCCA
    1 DBCONN@ 0.1U_0402_16V4Z

    2
    2
    SMT1-05_4P
    SW4
    A@ U47
    1 3ON/OFFBTN# 1 GND OUT 8
    2 IN OUT 7
    2 4 3 6 R1354
    IN OUT

    1
    D
    1 4 EN# FLG 5 2 1 USB_OC#9 <29>
    EC_ON 2
    <37> EC_ON
    6
    5

    G C1638 G528P1UF_SOP8 0_0402_5%


    2
    S 4.7U_0805_10V4Z 1

    3
    Q73 2 C1639
    R1053 SSM3K7002FU_SC70-3 @
    10K_0402_5% 0.1U_0402_16V4Z
    2
    10/09 add for debug <37> USB2_ON#
    1

    2 2

    10/30 add
    CIR 11/03 Modify symbol to SCR00000H00 by Vivian USB2_ON# C1663 2 1 100P_0402_50V8J
    USB IO Conn. +USB_VCCC

    JP11
    IR1 W=20mils R1054
    RCIRRX +CIR_VCC 1
    <37> RCIRRX 1 Vout Vcc 2 +3VALW 2
    C1142 3 4 100_0402_5% CIR@
    GND1GND2 USB20_N0 3
    2 1 <29> USB20_N0 4
    FM-2136SC-5CN(REV)_4P C1141 <29> USB20_P0 USB20_P0
    1000P_0402_50V7K CIR@ 4.7U_0603_6.3V6K 5
    @ CIR@ 6
    7
    USB20_N5 8
    <29> USB20_N5 9
    <29> USB20_P5 USB20_P5
    10
    11
    12
    13
    150u 14
    <29> USB20_N11 USB20_N11
    R1055 0_0402_5% ESR 0.9 ohm USB20_P11 15
    <29> USB20_P11 16
    <37> CIR_DET# 2 1 Package(L*W*H)7.3*4.3*2.9
    17
    Rating 6.3V 18
    CIR@
    CHECK 19
    3 20 3
    ACES_85201-20051

    +USB_VCCC
    W=80mils
    +USB_VCCC
    1 1
    1 C1145
    Lid Switch + C1143
    @
    C1144
    10U_0805_10V4Z
    150U_D_6.3VM 470P_0402_50V7K 2
    2 2

    11/29 change this symbol's footprint as


    ADT7421ARMZ-REEL_MSOP8
    +3VALW 1 2 +VCC_LID R1057 1 2 100K_0402_5%
    R1056 0_0402_5% +5VALW +USB_VCCC +3VALW
    copy LM75CIMMX-3_MSOP8
    2

    footprint

    2
    VDD

    R1058
    1 U35
    C1146 3 1 8 10K_0402_5%
    OUTPUT LID_SW# <37> GND OUT
    2 7 R1059 0_0402_5%

    1
    0.1U_0402_16V4Z IN OUT
    2 3 6 2 1
    GND

    2 IN NC USB_OC#04 <29>
    C1147 1 4 5
    EN# OC USB_OC#511 <29>
    C1148
    U34 10P_0402_50V8J G545A2P8U MSOP 8P
    1

    A3212ELHLT-T_SOT23W-3 1 4.7U_0805_10V4Z
    2 1
    C1149 10/30 add
    4 4
    0.1U_0402_16V4Z USB2_ON# C1664 2 1 100P_0402_50V8J
    2 @
    <37> USB2_ON#

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Power OK/Lid/Front,IO,DB Conn
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 40 of 56
    A B C D E
    5 4 3 2 1

    +3VS_DVDD Change PCB footprint of L71 from L_0603 to R_0603


    HD Audio Codec 10mil 1 1
    L71 1 2
    FBMA-L11-160808-800LMT_0603
    +3VS
    +VDDA

    C1150 C1151

    1
    @
    4.7U_0805_10V4Z R1060
    2 2 @
    0.1U_0402_16V4Z 10K_0402_5%
    +AVDD_AC97
    10/03 add +1.5VS

    2
    L72 +1.5VS_DVDD
    0.1U_0402_16V4Z 40mil R1061 PM@ 0_0603_5% C1152 1 2 0.1U_0402_16V4Z
    +VDDA +3VS

    1
    D 0_0603_5% 1 1 1 1 L73 1 2 +1.5VS D
    C1153 C1154 C1155 C1156 FBMA-L11-160808-800LMT_0603 R1062
    @ 10mil 1
    C1157
    1
    C1158 GM@
    10U_0805_10V4Z 100P_0402_50V8J @ 0_0402_5%
    2 2 2 2 4.7U_0805_10V4Z EC Beep

    2
    2 2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 R1063 2 1 R1064 2 MONO_IN_1 1 2 MONO_IN
    <37> BEEP#
    10K_0402_5% 0_0402_5% C1159 0.1U_0402_16V4Z

    25

    38

    9
    U36

    1
    1/15 Change PN of U36 from SA00001GD00 to Change PCB footprint of L73 from L_0603 to R_0603 C R1065 1 @ 2

    AVDD1

    AVDD2

    DVDD_IO
    DVDD
    SA00001GD10 <29> SB_SPKR 1 R1067 2 2 Q74 2.4K_0402_5%
    10K_0402_5% B @
    E 2SC2411K_SOT23
    PCI Beep

    3
    14 35 AMP_LEFT
    NC LINE_OUT_L AMP_LEFT <42>
    Need Update Footprint

    1
    15 36 AMP_RIGHT
    NC LINE_OUT_R AMP_RIGHT <42>
    R1068 D28
    1 2 MIC2_R_L C1160 2.2U_0603_6.3V6K MIC2_C_L 16 39 AMP_LEFT_HP @
    <43> MIC2_L MIC2_L HP_OUT_L AMP_LEFT_HP <42>
    R1066 1K_0402_5% 10K_0402_5% CH751H-40PT_SOD323-2
    1 2 MIC2_R_R C1161 2.2U_0603_6.3V6K MIC2_C_R 17 41 AMP_RIGHT_HP 9/19 Realtek suggest
    <43> MIC2_R AMP_RIGHT_HP <42>

    2
    R1069 1K_0402_5% MIC2_R HP_OUT_R
    Add bypass schematic.
    23 LINE1_L NC 45

    24 LINE1_R DMIC_CLK 46

    18 CD_L NC 43
    2/01 Let them floating
    20 CD_R NC 44
    C 19 C
    CD_GND HDA_BITCLK_AUDIO
    1 2 MIC1_R_L C1162 2.2U_0603_6.3V6K MIC1_C_L 21
    BIT_CLK 6 HDA_BITCLK_AUDIO <28> Sense Pin Impedance Codec Signals Funnction
    <42> MIC1_L MIC1_L
    R1070 1K_0402_5%
    MIC1_R_R C1163 2.2U_0603_6.3V6K MIC1_C_R SDIN0 39.2K PORT-A (PIN 39, 41)
    <42> MIC1_R 1
    R1071
    2
    1K_0402_5%
    22 MIC1_R SDATA_IN 8 1
    R1072
    2
    33_0402_5%
    HDA_SDIN0 <28> HP
    C1164 1 2 100P_0402_50V8J MONO_IN 12 37
    @ PCBEEP MONO_OUT
    20K PORT-B (PIN 21, 22) MIC
    LINE1_VREFO 29 SENSE A / B
    <28> HDA_RST_AUDIO# 11 RESET#
    GPIO1 31 10K PORT-C (PIN 23, 24) LINE IN
    <28> HDA_SYNC_AUDIO 10 SYNC
    MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
    <28> HDA_SDOUT_AUDIO 5 SDATA_OUT 5.1K PORT-D (PIN 35, 36) LINE OUT
    2
    MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
    GPIO0
    SENSE_A
    3 GPIO3 MIC2_VREFO 30 10mil +MIC2_VREFO 39.2K PORT-E (PIN 14, 15) HP
    SENSE_B
    13
    34
    SENSE A
    27 ACZ_VREF 10mil
    SENSE B VREF
    ACZ_JDREF
    20K PORT-F (PIN 16, 17) MIC
    <42> EAPD 47 EAPD JDREF 40 SENSE B

    1
    48 SPDIFO NC 33 1 1 10K PORT-G (PIN 43, 44) LINE IN
    2

    10/31 Remove SPDIF schematic R1075 C1165 C1166


    R1074 4 26
    DVSS1 AVSS1 20K_0402_1% 10U_0805_10V4Z 100P_0402_50V8J
    10_0402_5%
    7 DVSS2 AVSS2 42
    2 2 5.1K PORT-H (PIN 45, 46) LINE OUT

    2
    @ ALC268-GR_LQFP48
    1

    B
    1 B
    C1167 DGND AGND
    15P_0402_50V8J
    2 @

    ESD
    +3VS +1.5VS

    SENSE FOR Ext. Mic. HDA_BITCLK_AUDIO


    1

    Regulator for CODEC


    2

    R1010 R1022
    4.7K_0402_5% 4.7K_0402_5% R1076
    1 2 SENSE_A @ @
    <42> MIC_SENSE
    R1077 20K_0402_1% 10_0402_5%
    2

    HDA_RST_AUDIO# @
    40mil
    1

    L74 U37 +VDDA


    1 1 +5VS
    60mil +5VS_VDDA 1 IN (Max output = 300 mA)
    C1168 5
    C1301 0_0603_5% OUT
    2
    SENSE FOR Solo Int. Mic. 0.01U_0402_16V7K
    2
    10P_0402_50V8J
    2 @
    C1169
    1 1
    C1170 GND
    1 4.75V
    @ 3 4 C1171
    SHDN BYP
    10U_0805_10V4Z 2 2 0.1U_0402_16V4Z G9191-475T1U_SOT23-5 1 4.7U_0805_10V4Z
    @ C1172 2 @

    1 2 SENSE_B 0.01U_0402_16V7K
    R1078 20K_0402_1% 2
    A Moat Bridge 10/2 change circuit A

    10/17 Change GND to digital


    SENSE FOR HP 1 2
    U8 change footprint
    R1173 0_0805_5%
    1 2
    SENSE_A
    R1172 0_0805_5% Security Classification Compal Secret Data Compal Electronics, Inc.
    <42> HP_SENSE 2 1 1 2 Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    R1079 39.2K_0402_1% R1080 0_0805_5%
    1 2
    HD Audio Codec ALC268
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    R1081 0_0805_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 41 of 56
    5 4 3 2 1
    A B C D E

    +MIC1_VREFO_R

    APA2057 SPK/HP Amplifier 10/2 U6 APA2057A P/N:SA00001QD00


    +MIC1_VREFO_L Change PCB footprint of L75/ L76 from L_0603 to R_0603

    10mil 10mil MICROPHONE

    1
    +5VALW R1082 R1083
    IN JACK
    W=40mil 2.2K_0402_5% 2.2K_0402_5%
    JP13

    2
    680P_0402_50V7K

    10U_0805_10V4Z
    0.1U_0402_16V4Z
    1 1 2 MIC_SENSE 5
    <41> MIC_SENSE
    C1173 C1174 C1175 C1176
    4 10
    +3VALW 1U_0603_10V4Z 9
    2 2 1 MIC1_R L75 1
    <41> MIC1_R 2 <EMI> MIC1_R_1 3 8
    1 KC FBM-L11-160808-121LMT 0603 1
    6 7
    MIC1_L L76 1 2 <EMI> MIC1_L_1 2
    <41> MIC1_L
    R1084 @ 1.5K_0402_1% KC FBM-L11-160808-121LMT 0603

    11

    19

    20
    10
    1 1 1

    1
    fo=1/(2*3.14*R*C)=106Hz 1 2 U38 C1178 C1179

    3
    R=1.5K / C= 1uF R1086 @ 1.5K_0402_1% <EMI> <EMI> SINGA_2SJ-B351-S01

    CVDD

    HVDD

    PVDD
    PVDD

    VDD
    1 2 220P_0402_50V7K 220P_0402_50V7K CONN@
    2 2
    1 2 AMPR
    <41> AMP_RIGHT
    C1180 1U_0603_10V4Z SPKR+
    AMPL
    3 INR_A ROUT+ 22
    SPKR- @ RED
    <41> AMP_LEFT 1 2 5 21
    Trace width/spacing/other=8/6/50

    1
    C1177 1U_0603_10V4Z INL_A ROUT- D29
    R1085 1 2 100K_0402_5% AMP_EN# 27 8 SPKL+ PSOT05C-LF-T7 SOT-23-3
    /AMP EN LOUT+ SPKL- <EMI>
    LOUT- 9
    +5VS R1087 1 @ 2 100K_0402_5% HP_EN 24 HP EN HP_R
    HP_R 17
    1 2 AMP_RHPIN 1 2 INR_H 4 18 HP_L 9/3 Change PCB footprint of JP12/JP13 from FOX_JA6033L-B5S3-7F_6P to SINGA_2SJ-B351-S01_6P
    <41> AMP_RIGHT_HP INR_H HP_L
    C1181 4.7U_0805_10V4Z R1088 39K_0402_5% 6
    AMP_LHPIN INL_H INL_H
    <41> AMP_LEFT_HP 1 2 1 2 12/8 Change value conn location of JP13 and JP12.
    C1182 4.7U_0805_10V4Z R1089 39K_0402_5% 26
    AMP_SD# /SD CVSS
    CVSS 15
    1 2 1 2 1 2 AMP_BEEP 28
    R1090 0_0402_5% C1183 0.47U_0603_16V4Z R1091 0_0402_5% BEEP
    16
    HEADPHONE
    AMP_CP+ 12 CP+
    VSS 10mil Change PCB footprint of L77/ L78 from L_0603 to R_0603 OUT JACK
    1 2 AMP_CP- 14 2
    CP- GND

    1
    C1184 1U_0603_10V6K 23 C1186
    AMP_BIAS PGND 1U_0603_10V6K JP12
    25 BIAS PGND 7
    C1185 2.2U_0603_6.3V6K 13 HP_SENSE 5
    <41> HP_SENSE

    2
    CGND
    2 1 GND 29
    C1187 0.1U_0402_16V4Z 4 10
    APA2057A_TSSOP28 9
    HP_R L77 1 2 <EMI> HPR 3 8
    9/5 If implement AMP BEEP, Swap C641 and R524. KC FBM-L11-160808-121LMT 0603 6 7
    2 IN_A Gain = 10dB (Internal Speaker) HP_L L78 1 2 <EMI> HPL 2 2
    R524 change from 0 Ohm to 47K KC FBM-L11-160808-121LMT 0603 1
    IN_H Gain = 0dB (Headphone)

    1
    1 1

    3
    R1092 R1093 C1188 C1189 SINGA_2SJ-B351-S02
    @ @ <EMI> <EMI> CONN@
    0_0402_5% 0_0402_5%
    11/28 Modified to X5R 10P_0402_50V8J2 2 10P_0402_50V8J

    2
    11/28 Change to SE080105K80 @

    1
    D30
    PSOT05C-LF-T7 SOT-23-3 BLUE
    Trace width/spacing=15/9 <EMI>

    Add below circuit for APA2057 gain tunning use


    +5VALW

    1
    R1094 10/30 add @
    10K_0402_1% SPK_L1- C1654 2 1 100P_0402_50V8J
    +3VALW 2 @
    SPK_L1+ C1653 2 1 100P_0402_50V8J
    AMP_SD# R1095 1 2 10K_0402_5% HP_EN @
    2

    SPK_R1- C1655 2 1 100P_0402_50V8J


    3 R1096 3
    1
    1

    1 C1191
    10K_0402_5% C1190 R1097
    1

    D 0.1U_0402_16V4Z
    1

    22K_0402_1% 2
    2
    G 0.01U_0402_16V7K 2
    2

    S
    3
    1

    D
    EAPD 2 1 2 Q75
    <41> EAPD
    R1098 0_0402_5% G 1/8 change JSPK1 following JAW91
    Q76 S SSM3K7002FU_SC70-3
    3

    9/3 Change footprint from ACES_88266-04001_N to ACES_88266-04001


    SSM3K7002FU_SC70-3

    JSPK1
    Gain= 10dB SPKL- R1099 1 2 <EMI> 0_0603_5% SPK_L1- 1 1
    SPKL+ R1100 1 2 <EMI> 0_0603_5% SPK_L1+ 2
    SPKR- R1101 1 <EMI> 0_0603_5% SPK_R1- 2
    2 3 3 G1 5
    SPKR+ R1102 1 2 <EMI> 0_0603_5% SPK_R1+ 4 6
    4 G2
    20mil ACES_88266-04001
    Gain (dB) Low (V) High (V) Recommended (V) Speaker Conn. CONN@

    3
    10 3.45 3.51 3.48 D31 D32
    @ @
    11 3.56 3.62 3.59 PSOT24C_SOT23 PSOT24C_SOT23
    <EMI> <EMI>

    1
    4 4

    12 3.68 3.73 3.70

    13 3.80 3.85 3.82


    +5VALW assume equal 5.1V
    10 dB ---> 5.1 x 220 / 320 = 3.5 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    AMP/VR/Audio Jack
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 42 of 56
    A B C D E
    SINGLE INT MIC/DUAL INT MIC
    +3VS

    1
    R1103
    10K_0402_5%
    @

    2
    +MIC2_VREFO +MIC2_VREFO 1 2 +MIC2_VREF_R
    R1104 0_0402_5%

    1
    1
    C1192 R1105
    27K_0402_5%
    0.1U_0402_16V4Z @
    @ 2

    2
    9/18 Add D34 for INT MIC use( PN:SCD0T05CA20 )
    D34 is a modified symbol
    2 R1106 1
    @ 0_0402_5%

    D33 DUAL@
    +MIC2_VREF_R 2 1 1 R1107 2 DUAL@
    2.2K_0402_5%
    RLS4148_LL34-2
    JMIC1
    1 MIC2_L_OUT 1 2 <EMI> MIC2_L
    1 MIC2_L <41>
    2 2 1 R1108 0_0402_5%
    2 C1193 220P_0402_50V7K
    3 <EMI> DUAL@
    GND
    GND 4
    D34

    1
    ACES_88231-02001 @
    DUALCONN@ R1109 3
    1
    0_0402_5% 2
    SINGLE@

    2
    PSOT05C-LF-T7 SOT-23-3

    R1110
    0_0402_5%
    2 1

    SINGLE@ D35
    +MIC2_VREF_R 2 1 1 R1111 2
    2.2K_0402_5%
    RLS4148_LL34-2
    JMIC2 DUAL@
    1 MIC2_R_OUT 1 2 <EMI> MIC2_R
    1 MIC2_R <41>
    2 2 1 R1112 0_0402_5%
    2 C1194 220P_0402_50V7K
    3 <EMI>
    GND
    4
    GND 9/18 Place these parts close to CODEC (U36)
    ACES_88231-02001
    CONN@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    MIC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 43 of 56
    A B C D E

    11/27 Add screw for layout request

    1 1
    H1 H2 H3 H4 H9 H10 H11 H12 H13 H14 H15 H16
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

    H_3P0

    1
    9/7 Change H9 from GND to AGND
    H17 H18 H19 H20
    HOLEA HOLEA HOLEA HOLEA

    H_3P2
    1

    1
    H21 H22 H23
    HOLEA HOLEA HOLEA
    H_4P0
    1

    2 H24 H26 H27 H33 2


    HOLEA HOLEA HOLEA HOLEA
    H_4P2
    1

    FD1 FD2 FD3 FD4 FD5 FD6

    @ @ @ @ @ @

    1
    H28
    HOLEA
    H_5P0
    1

    H29 H30 H34 H35 H36 H37


    H_2P3 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
    1

    9/7 Change H36 from GND to AGND

    3 3

    M1 M2 M3
    HOLEA HOLEA HOLEA
    1

    H_2P8N H_3P0N H_3P0N

    M4 M5
    HOLEA HOLEA
    1

    H_4P8X2P8N H_3P8X2P8N

    4 4

    11/27 Add screw for layout request


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    Screw
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 44 of 56
    A B C D E
    +5VS R1113 2 1 0_0603_5%
    +CAM_VCC
    +5VALW
    R1114
    2
    @
    1
    0_0603_5% +CAM_VCCA
    W=20mils

    MDC Conn.

    1
    C1644 1
    @
    20mil 0.1U_0402_16V4Z 1U_0603_10V4Z C1645 R1359 1 1

    3
    S
    @ 0_0603_5% C1195 C1196
    G 2
    <37> CAM_ON# 1 2 2

    2
    PM@ R1358 @ 100K_0402_5% Q7 4.7U_0805_10V4Z 0.1U_0402_16V4Z
    JMDC1 2 2
    1 R1115 2 0_0402_5% +3VS W=20mils
    GM@ SI2301BDS_SOT23 D R1360
    1 2 +VCC_MDC 1 R1116 2 0_0402_5% +1.5VS @ 0_0603_5%

    1
    HDA_SDOUT_MDC GND1 RES0 +CAM_VCC_R 1 @ JP14
    <28> HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
    +3V_MDC
    10/23 Add by Vivian 2 +CAM_VCC
    5 GND2 3.3V 6 1 R1117 2 0_0402_5% +3VS 1 1
    HDA_SYNC_MDC 7 8 <29> USB20_N2 USB20_N2 R1119 1 2 0_0402_5% USB20_R_N2 2
    <28> HDA_SYNC_MDC IAC_SYNC GND3 2
    SDIN1_MDC 9 10 <29> USB20_P2 USB20_P2 R1118 1 2 0_0402_5% USB20_R_P2 3
    HDA_RST_MDC# IAC_SDATA_IN GND4 HDA_BITCLK_MDC 3
    <28> HDA_RST_MDC# 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC <28> 4 4
    1 D38 5
    C1197 5
    @ 2 I/O I/O 3 6 GND1
    7

    GND
    GND
    GND
    GND
    GND
    GND
    22P_0402_50V8J WCM2012F2SF-121T04_0805 GND2
    2 @ ACES_88266-05001
    4 4 3 3 1 GND VCC 4
    CAMCONN@

    13
    14
    15
    16
    17
    18
    PJLCR05 SOT143
    1 2 @
    Connector for MDC Rev1.5 Camera Conn 1
    L79
    2

    ACES_88018-124G W=20mils R1365 2 1 @ 0_0603_5% +5VS


    CONN@ 10/23 Add by Vivian +FP_VCCA R1366 2 1 @ 0_0603_5%
    R1120 1
    +3VS
    Finger Print board

    1
    HDA_SDIN1 1 2 SDIN1_MDC C1646
    <28> HDA_SDIN1
    @ 1U_0603_10V4Z C1647 @ Modify symbol
    33_0402_5% +VCC_MDC +3V_MDC 0.1U_0402_16V4Z @ R1362

    3
    2
    S
    G 0_0603_5% 12/23 change D36 from SC300000K00 to SC300000100
    @
    Please add these caps close to JMDC1 as close as possible, <37> FP_ON# 1 2 2

    2
    R1361 100K_0402_5% Q8 12/23 change D36 value from PJLCR05 SOT143 to PRTR5V0U2X
    HDA_SDOUT_MDC C1198 1 2 @ 100P_0402_50V8J 1 1
    C1200 C1201 SI2301BDS_SOT23
    D W=20mils SOT143 EMI Request
    HDA_SYNC_MDC C1199 1 2 @ 100P_0402_50V8J @

    1
    0.1U_0402_16V4Z 0.1U_0402_16V4Z +FP_VCC_R 1 @ 2 0_0603_5% +FP_VCC D36
    HDA_RST_MDC# C1202 2 2 @ +5VS
    1 2 @ 100P_0402_50V8J @ R1364 3 I/O I/O 2
    L80 @
    HDA_SDIN1 C1203 1 2 @ 100P_0402_50V8J 4 3
    4 3
    4 VCC GND 1

    WCM2012F2SF-121T04_0805 1 2 PRTR5V0U2X SOT143


    1 2 JP15
    0_0402_5% 1
    USB20_P1 R1121 2 USB20_R_P1 1
    <29> USB20_P1 1 2 2
    <29> USB20_N1 USB20_N1 1 2 USB20_R_N1 3
    R1122 0_0402_5% 3
    4
    TPM X76 Information 5
    4
    5
    +3VS 6 6
    7 GND
    X76 P/N Vendor Location Bom Structure C487 8 GND
    2 1 +5VS 1 1 ACES_85201-06051
    X7611630L07 Infineon C717,C718,R698,R702,R703,U32,X3 IN_TPM@ <EMI> @ 0.1U_0402_16V4Z C1204 C1205 FPCONN@

    4.7U_0805_10V4Z 0.1U_0402_16V4Z
    X7611630L08 Winbond C724,U32 WB_TPM@ @ 2 2

    Let C715 close pin 24 Let C724 close pin 10


    TPM 1.2 +3VS Copy IFT
    LED +3VALW
    C1206
    1 1
    C1207
    C488 +3VS WB_TPM@
    2 1 +3VALW 0.1U_0402_16V4Z 1U_0402_6.3V4Z
    R1123 <EMI> @ TPM@ 2 2
    820_0402_5%
    +3VS
    +5VS 1 2 2 1 LED1 SATA_LED# <28>
    0.1U_0402_16V4Z
    HT-191NB_BLUE_0603

    24
    19
    10

    1
    U39
    R1125 Base I/O Address R1124

    VSB
    VDD
    VDD
    VDD
    820_0402_5% 0 = 02Eh 4.7K_0402_5%
    +5VALW 1 2 2 1 LED2 PWR_LED# <37,38> * 1 = 04Eh TPM@
    <28,37,40> LPC_AD0 LPC_AD0 26 28 SUS_STAT#
    SUS_STAT# <29>

    2
    HT-191NB_BLUE_0603 LPC_AD1 LAD0 LPCPD#
    <28,37,40> LPC_AD1 23 LAD1 TESTB1/BADD 9
    <28,37,40> LPC_AD2 LPC_AD2 20 8 TPM_TEST1 R1126 1 2 0_0402_5%
    LAD2 TEST1

    1
    <28,37,40> LPC_AD3 LPC_AD3 17 IN_TPM@
    LAD3 TPM_XTALO R1127
    XTALO 14
    R1128 HT-191UD_AMBER_0603 13 TPM_XTALI 4.7K_0402_5%
    820_0402_5% TPM XTALI @
    Amber
    +5VALW 1 2 2 1 LED3 CHARGE_LED0# <37> <23> CLK_PCI_TPM
    CLK_PCI_TPM 21 SLB 9635 TT 1.1

    2
    LPC_FRAME# LCLK
    <28,37,40> LPC_FRAME# 22 LFRAME# GPIO2 2
    R1129 Blue PLT_RST_BUF# 16 6
    <8,16,27,32,33,35> PLT_RST_BUF# LRESET# GPIO
    +5VALW 1 2 2 1 LED4 CHARGE_LED1# <37> <29,37> SERIRQ
    SERIRQ 27 SERIRQ
    820_0402_5% PM_CLKRUN# 15
    <29,37> PM_CLKRUN# CLKRUN#
    +3VS 1 2 7 PP NC 1
    HT-191NB_BLUE_0603 R1130 4.7K_0402_5% 3
    IN_TPM@ NC C1208 IN_TPM@
    12

    GND
    GND
    GND
    GND
    R1131 NC 15P_0402_50V8J
    HT-191UD_AMBER_0603
    820_0402_5% Amber TPM_XTALI
    +5VS 1 2 2 1 LED5 WLAN_LED# <35>
    SLB-9635-TT-1.2_TSSOP28

    4
    11
    18
    25

    10M_0402_5%
    IN_TPM@ X3

    1
    R1132 Blue 1 2
    IN NC

    IN_TPM@
    +5VS 1 2 2 1 LED6 BT_LED# <39>
    CLK_PCI_TPM
    820_0402_5% 4 3
    OUT NC
    2

    R1133
    HT-191NB_BLUE_0603 R1134 32.768KHZ_12.5P_1TJS125BJ2A251

    2
    10/30 add @ 10_0402_5% U39 IN_TPM@
    @ TPM_XTALO
    BT_LED# C1657 2 1 100P_0402_50V8J
    1

    @ 2 C1209 IN_TPM@
    WLAN_LED# C1658 2 1 100P_0402_50V8J 15P_0402_50V8J
    @ C1210
    CHARGE_LED0# C1659 2 1 100P_0402_50V8J @ 15P_0402_50V8J S IC WPCT200AA0WG TSSOP 28P TPM
    @ 1 WB_TPM@
    CHARGE_LED1# C1660 2 1 100P_0402_50V8J
    @
    PWR_LED# C1661 2 1 100P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title

    12/7 Modified LED footprint to LED_HT-297UD-CB_4P


    MDC/LED/Camera/FP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    12/15 Modified to correct LED symbol! B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 45 of 56
    A B C D E

    +1.5V TO +1.5VS
    CHECK

    +1.5V
    +5VALW TO +5VS J7
    +3VALW TO +3VS PAD-OPEN 3x3m
    +5VALW +5VS 1 2
    +3VALW +3VS +1.5VS
    U41 @
    8 1 U42 U43
    1 D S 1
    7 D S 2 8 D S 1 8 D S 1

    2
    6 D S 3 1 1 7 D S 2 7 D S 2

    2
    5 4 C1211 C1212 R1135 6 3 1 1 6 3 1 1
    D G D S C1213 C1214 R1136 D S
    5 D G 4 5 D G 4
    AO4468_SO8 10U_0805_10V4Z 470_0603_5% 470_0603_5% C1215 C1216
    @ 2 2
    1U_0603_10V4Z @ AO4468_SO8 10U_0805_10V4Z AO4468_SO8 @

    1
    @ 2 2
    1U_0603_10V4Z @ 2 2

    1
    1
    Q77
    D

    1
    @ Q78
    2 SUSP D @ 10U_0805_10V4Z 1U_0603_10V4Z
    +VSB 5VS_GATE G 2 SUSP B0@
    R1137 S SSM3K7002FU_SC70-3 +VSB 1 2 G +VSB 1 2

    3
    33K_0402_5% 1 R1138 S SSM3K7002FU_SC70-3 R1139
    1

    3
    C1217 47K_0402_5% 1 47K_0402_5% 1

    1
    SUSP D D C1219
    2
    G 0.1U_0603_25V7K SUSP 2 C1218 SUSP 2 10/22 Add by Vivian
    Q79 S 2 G 0.1U_0603_25V7K G 0.1U_0603_25V7K
    3

    SSM3K7002FU_SC70-3 Q81 S 2 Q80 S 2

    3
    SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 R1139 R1139

    47K_0402_5% 300K_0402_5%
    B1@ B2@

    +5VALW

    +5VALW
    CHECK
    +1.8V TO +1.8VS
    2

    2 2

    2
    R1140 +1.8V
    100K_0402_5% R1141 J8
    100K_0402_5% PAD-OPEN 3x3m
    1

    1 2
    SYSON# +1.8VS
    <8,52> SYSON#

    1
    SUSP @
    SUSP <32,52>
    1

    D
    U44
    SYSON 2 Q82 8 1
    <36,37,51,52> SYSON D S

    1
    G SSM3K7002FU_SC70-3 D
    7 D S 2
    S 2 Q83 6 3 1 1
    <36,37,51,53> SUSP#
    3

    D S
    1

    10/31 Remove R1367 G SSM3K7002FU_SC70-3


    1 5 D G 4
    R1142 S C1221 C1222

    3
    1
    C1220 AO4468_SO8 @ PM@
    10K_0402_5% R1143 100P_0402_50V8J PM@ 2 2
    2
    2

    3/14 Change R16 from 100K to 10K 10K_0402_5%

    2
    B1@ 10U_0805_10V4Z 1U_0603_10V4Z
    R1144
    +VSB 1 2
    150K_0402_5%
    1

    1
    SYSON D PM@
    SUSP 2 C1223
    1 G 0.1U_0603_25V7K
    @ Q84 S 2

    3
    C1552 SSM3K7002FU_SC70-3
    100P_0402_50V8J PM@
    2 R1144

    3 3

    300K_0402_5%
    B2@

    10/22 Add by Vivian


    +1.8VS +1.5VS +1.1VS +0.75V +1.8V
    2

    2
    R1145 R1147 R1146 R1148 R1149
    470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
    @ @ @ @ @
    1

    Q85 Q87 Q86 Q88 Q89


    1

    @ @ @ @ @
    D D D D D
    2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SYSON#
    G G G G G
    S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3
    3

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    DC Interface
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 46 of 56
    A B C D E
    A B C D

    1 1

    PR102
    1M_0402_1%
    DC301001Y00 VINDE-2
    1 2
    VIN
    PL1 VIN VS
    @ SINGA_2DW-0268-B16 ADPIN HCB4532KF-800T90_1812 VIN

    0.01U_0402_25V7K
    1 1 1 2

    10K_0805_5%
    2 2

    1
    3 3

    PC105

    PR104
    4 4

    0.01U_0402_50V7K

    0.01U_0402_50V7K

    0.01U_0402_50V7K

    0.01U_0402_50V7K
    PR103 PR105
    PJP1 84.5K_0402_1% 10K_0402_1%

    2
    1

    1
    1 2

    2
    ACIN <29,37>

    PC1

    PC2

    PC3

    PC4
    PR106

    8
    22K_0402_1%

    2
    VINDE-1 1 2 3

    P
    +

    0.068U_0603_16V7K
    O 1
    VINDE-3 2 -

    G
    20K_0402_1%

    10K_0402_1%
    0.1U_0402_16V7K

    RLZ4.3B_LL34
    PU102A

    1
    LM393DG_SO8

    4
    PC106

    PR107

    PC107

    PR108
    PD102
    2

    2
    2
    PR109

    2
    10K_0402_1%
    2 1 RTCVREF
    3.3V

    2 2

    Vin Detector

    High 18.384 17.901 17.430


    PJ402
    Low 17.728 17.257 16.976
    +3VALWP 2 2 1 1 +3VALW
    @ JUMP_43X118

    SP093MX0000 VIN
    PJ403 BOM structure comment
    +5VALWP 2 2 1 1 +5VALW

    2
    @ JUMP_43X118 @ ==>unpop PD103
    RLS4148_LL34-2

    65@==> UMA only

    1
    PJ503 PD101 51ON-1
    +VCCPP 2 2 1 1 +VCCP BATT+ 2 1

    1
    90@==>DIS only
    @ JUMP_43X118 RLS4148_LL34-2 PR110 PR111
    PQ101 68_1206_5% 68_1206_5%
    NV@==>Nvidia sku only TP0610K-T1-E3_SOT23-3
    PR101

    2
    200_0603_5%
    M96@==>ATI sku only CHGRTCP 1 2 51ON-2 3 1
    VS
    3 3

    0.22U_0603_25V7K
    PJ504

    1
    +1.5VP 2 2 1 1 +1.5V 65NV@==>UMA and NV sku only

    1
    PC108
    PR112 PC109
    @ JUMP_43X118 100K_0402_1% 0.1U_0603_25V7K

    2
    PJ608 @ PR113

    2
    2 1 22K_0402_1%
    2 1 51ON-3
    1 2
    JUMP_43X118 <38,40> 51_ON#

    PJ505
    +0.75VP 2 2 1 1 +0.75V
    RTCVREF

    1
    @ JUMP_43X79
    PR114
    PJ604 +CHGRTC PU101 200_0603_5%
    +1.1VSP 2 1 +1.1VS PR115 PR116 G920AT24U_SOT89-3
    2 1 560_0603_5% 560_0603_5% 3.3V

    2
    @PJ602
    @ PJ602
    JUMP_43X79 1 2RTCVREF-1
    1 2 3 OUT IN 2CHGRTCIN
    +VGA_COREP 2 2 1 1 +VGA_CORE

    1
    JUMP_43X118 PJ606 @ GND PC111
    @
    2 2 PC110 1U_0805_25V4Z
    +1.8VP 1 1 +1.8V 10U_0805_10V4Z 1

    2
    @PJ603
    @ PJ603 JUMP_43X118
    2 2 1 1

    JUMP_43X118
    4
    PJ611 4

    PJ610
    2 2 1 1
    +VSBP 2 2 1 1 +VSB
    @ JUMP_43X118

    @ JUMP_43X79

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    DCIN & DETECTOR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 47 of 56
    A B C D
    A B C D

    1 1

    PH1 under CPU botten side :


    CPU thermal protection at 89 degree C
    Recovery at 70 degree C
    BATT++ PJ8 VS
    DC040003600 PAD-OPEN 3x3m
    1 2 BATT+
    VL

    0.1U_0603_25V7K
    PJP2 VL

    PC15
    1 BATT++ 1 2
    1 +3VALWP

    150K_0402_1%
    2 2

    2
    1000P_0402_50V7K

    1000P_0402_50V7K

    10K_0402_1%
    3 CNT1 PR19 @ PR18
    @PR18

    2
    3

    PR23
    0.01U_0402_50V7K
    4 CNT2 1 2 100K_0402_5%
    4 +3VALWP

    PR22
    5 EC_SMCA PR24
    5

    1
    PC12

    PC13

    PC14
    6 EC_SMDA @ 100K_0402_5% 1 442K_0603_1%
    2
    2 6 TS_A 2
    7

    1
    7

    2
    1K_0402_1%
    8 GND

    2
    8
    2

    9 PR21 PR27
    9

    8
    10 78.7K_0603_1%
    G1
    11 PR20 1 2 5

    P
    G2 1K_0402_1% +
    7 MAINPWON <28,50>
    1

    SUYIN_200275MR009G180ZR TM_REF1 O
    6
    1

    G
    100K_0603_1%_TH11-4H104FT
    <BOM Structure> PU102B

    1
    LM393DG_SO8

    4
    PH1
    1000P_0402_50V7K
    100_0402_1%
    1

    1
    100_0402_1%

    1U_0603_6.3V6M
    2
    1
    PR25

    PR26

    PC16

    PC17
    PR28
    2 150K_0402_1%
    1 VL

    2
    2

    150K_0402_1%
    1
    EC_SMB_CK1 <37,39>

    PR31
    EC_SMB_DA1 <37,39>

    2
    1 2 +3VALWP
    PR29
    1K_0402_1%

    6.49K_0402_1%
    1
    PR30

    3 3
    2

    BATT_TEMP <37>

    PQ816
    TP0610K-T1-E3_SOT23-3

    B+ 3 1 +VSBP
    0.22U_1206_25V7K

    0.1U_0603_25V7K
    1

    100K_0402_1%

    1
    PR904

    PC871

    PC872
    2

    PR905
    2

    22K_0402_1%
    VL 1 2
    10K_0402_1%
    2
    PR906

    PR907
    1

    0_0402_5% D
    4
    1 2 2 PQ817 4

    <50> SPOK
    G SSM3K7002F_SC59-3
    0.1U_0402_16V7K

    S
    3
    1

    PC873
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    BATTERY CONN / OTP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 48 of 56
    A B C D
    A B C D

    65W, Iadapter=0~3.42A, Current sense=0.015ohm, PR45=110K, CP=3.175A


    90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR45=54.9K, CP=4.303A
    PQ301

    24751_PVCC

    PQ301 65@ PQ302 65@ B+


    FDS4435BZ_SO8 FDS4435BZ_SO8
    AO4407A_SO8 8 PR302
    90@ VIN D S 1 1 S D 8 0.015_1206_1%
    7 D S 2 2 S D 7 PL809
    6 D S 3 3 S D 6 B+_IN
    5 CHG_B+
    D G 4 4 G D 5 1 4 1 2

    1
    2

    2
    1 1

    4.7U_1206_25V6K

    4.7U_1206_25V6K

    4.7U_1206_25V6K
    PQ302 2 3 FBMA-L11-201209-121LMA50T_0805 PR303

    10U_1206_25V6M
    PR301 100K_0402_1%

    1
    0.01U_0402_25V7K
    3.3_1210_5% PC302

    CHGEN#

    1
    PC303

    PC304

    PC305

    PC819
    0.01U_0402_25V7K
    PC310

    2
    2

    100K_0402_1%
    PC307 0.01U_0402_25V7K

    2 1

    2
    2

    5
    6
    7
    8

    3
    2
    1
    PC301

    PC306

    @ 0.1U_0603_25V7K
    0.1U_0402_16V7K PU301 0.1U_0603_25V7K

    BK-1

    0.1U_0603_25V7K
    AO4407A_SO8 1 2 1 28 1 2 @ PQ304

    1
    90@ PR305 CHGEN PVCC AO4407A_SO8

    1
    /BATDRV

    PR304
    3.3_1210_5% PR307 4 <BOM Structure>

    PC308

    PC309
    2.2_0603_5% PQ303
    1 1 27 24751_BTST-1
    1 2 4 AO4466_SO8

    2
    BTST

    2
    BK-2
    PC311 PR306
    2.2U_0805_25V6K 340K_0402_1% 24751_ACN 2 26 24751_HIDRV
    24751_ACP 3 ACN HIDRV
    2

    3
    2
    1

    5
    6
    7
    8
    ACP

    1
    24751_ACDRV#4 25 24751_PH PL202 PR308
    ACDET 5 ACDRV PH PD301 10U_LF919AS-100M-P3_4.5A_20%
    ACDET BATT+
    2 124751_BTST
    1 2 1 224751_SW-1 1 4

    5
    6
    7
    8

    10U_1206_25V6M

    10U_1206_25V6M

    10U_1206_25V6M
    RLS4148_LL34-2 PC312

    REGN
    2 2 3

    1
    PR311 0.1U_0603_25V7K

    1
    PC331

    PC314
    PR310 65@ 110K_0402_1%

    1
    Icharge=(Vsrset/Vvdac)*(0.1/PR44) PR309 54.9K_0402_1% 24751_VREF 1 2 ACSET 6 PQ305 PR312 0.02_1206_1%
    ACSET

    PC313
    340K_0402_1% 24 AO4466_SO8 4.7_1206_5%

    2
    REGN

    100K_0402_1%
    Iadapter=(Vacset/Vvdac)*(0.1/PR36) 4
    1

    2
    1

    1
    PC316

    24751_SNB
    1

    PR313
    Input OVP : 22.3V 1U_0603_10V6K
    PC315

    2
    Input UVP : 17.26V @ 0.01U_0402_25V7K

    3
    2
    1
    1 224751_ACOP
    7 ACOP

    1
    2
    Fsw : 300KHz PC317 23 24751_LODRV 2

    0.47U_0603_16V7K LODRV
    CP setting PC318

    2
    2

    PR314 22 680P_0603_50V8J
    54.9K_0402_1% 24751_OVPSET PGND PC319
    8 OVPSET 0.1U_0402_16V7K
    PR311 1 2
    9 21 ACOFF
    ACOFF <37>
    1

    AGND LEARN

    1
    PC320 PC321

    1
    24751_VREF 20 CELLS 0.1U_0603_25V7K @0.1U_0603_25V7K

    2
    54.9K_0402_1% CELLS
    90@ 10 PR334
    PQ306 VREF 0_0402_5%
    3

    1
    SI2301BDS-T1-E3_SOT23-3 PC322

    2
    1U_0603_10V6K
    PR316 19 24751_SRP

    2
    100K_0402_1% RTCVREF SRP
    1 2 2 11 18 24751_SRN
    VDAC SRN
    100K_0402_1%
    1

    BAT 17
    PR317

    1
    VADJ 12 VADJ PC323
    1

    24751_VREF ACSET 0.1U_0603_25V7K


    2

    2
    TP 29
    24751_VREF 24751_OCP-3 1 24751_ACGOOD#
    2 13 ACGOOD ICHG setting
    1

    PC324
    PR318 PR319
    200K_0402_1% 0.1U_0603_25V7K SRSET
    SRSET 16 2 1 IREF <37>
    1

    /BATDRV 14 49.9K_0402_1%
    BATDRV
    1

    1
    3 3
    D
    2

    1
    PR320 24751_OCP-2 2 PR322
    100K_0402_1% G 15 IADAPT
    1 2 100K_0402_1% PC325
    PQ307 IADAPT @0.01U_0402_25V7K
    S
    2

    2
    1

    D 2N7002W-T/R7_SOT323-3 BQ24751ARHDR_QFN28_5X5 PR321

    2
    ACOFF 1 2 24751_OCP-1 2 10_0603_5%
    G REGN
    1

    1
    PC326 S PQ308
    3

    0.1U_0402_16V7K 2N7002W-T/R7_SOT323-3 PC327


    PR323 100P_0402_50V8J 24751_VREF

    2
    1

    340K_0402_1% IREF Current


    PR324 ADP_I <37>
    2

    2
    0_0402_5%
    BATT++ @PR326
    @ PR326 2.968V 3A PR325
    8

    210K_0402_1% 100K_0402_1%
    2
    499K_0402_1% 340K_0402_1%

    5 1 2 VADJ
    P

    + <37> CHGVADJ
    1

    7 VS

    1
    0
    1000P_0402_50V7K
    PR327

    - 6 CHGVADJ Pre Cell


    1
    G

    499K_0402_1%

    CHGEN#
    1
    PR328
    0.01U_0402_25V7K

    PU302B
    4

    1
    D
    PC328

    LM358DR_SO8 3.3V 4.35V


    OVP-1 2

    <37> FSTCHG 2
    2
    1

    PC329

    @ G
    2
    1

    OVP-4 @ 0V 4V S PQ309

    3
    PR329

    2N7002W-T/R7_SOT323-3
    2

    "CHGVADJ" connect to EC DA pin


    2
    8

    PR330
    10K_0402_1% 3 OVP-2
    P

    +
    2 1 1
    4 <37> BATT_OVP 0
    2 4

    -
    G

    105K_0402_1%

    A/D
    1

    0.01U_0402_25V7K

    PU302A
    LI-3S :13.5V----BATT-OVP=1.5V
    4

    1
    PR331

    LM358DR_SO8
    PC330

    BATT-OVP=0.1112*BATT+
    2
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    OVP-3
    CHARGER
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 49 of 56
    A B C D
    5 4 3 2 1

    Iocp=Iv+I/2; Iv=(5uA*301K)/(10*18m)=8.36A
    I=(19-3.3)3.3/19*4.7UH*300K=1.93AIocp=8.36+1.93/2=9.32A

    ISL6237_B+ Iocp=(Iv+I/2)/1.3;
    ISL6237_B+ Iv=(5uA*301K)/(10*18m)=8.36A ;
    B+
    I=(19-5)5/19*4.7UH*400K=1.96A;
    PR401 Iocp=(8.36+1.96/2)=9.34A
    PL808
    0_0402_5%
    1 2 1 2

    2200P_0402_50V7K
    10U_1206_25V6M
    FBMA-L11-453215-121LMA90T_2

    2200P_0402_50V7K
    10U_1206_25V6M
    D D

    5
    6
    7
    8

    1
    PC401

    PC403

    PC406
    8
    7
    6
    5

    PC404
    1U_0603_10V6K
    VL

    2
    2
    2

    PC408
    PQ401 PC407

    4.7U_0805_6.3V6K
    AO4466_SO8 0.1U_0603_25V7K 4

    3/5V_VCC
    1

    1
    3/5V_VIN
    4

    PC409
    PQ402 +5VALWP

    2
    AO4466_SO8

    3
    2
    1
    PL402

    1
    2
    3
    PL401 4.7UH_SIL104R-4R7PF_5.7A_30%

    7
    4.7UH_SIL104R-4R7PF_5.7A_30% PU401 PC410 2 1
    1 2 1U_0603_10V6K

    VIN

    V5FILT

    LDO
    +3VALWP 33 19 1 2
    TP V5DRV

    5
    6
    7
    8

    1
    PQ404

    8
    7
    6
    5
    UG3 26 15 HG5 AO4712_SO8
    PR402 DRVH2 DRVH1 PR404
    0_0402_5%

    @ 4.7_1206_5% PQ403 BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 @ 4.7_1206_5% 1


    VBST2 VBST1
    2

    AO4712_SO8 PR403 PR405

    15V_SNB
    1

    2
    2

    2
    PR406

    61.9K_0402_1%
    0_0402_5% 0_0402_5% +

    13V_SNB
    4

    2
    + 4 PC411

    2
    0.1U_0603_25V7K PC413

    1
    2 150U_D2_6.3VY_R15M

    @ PR407
    SW3 25 16 SW5
    1

    PC421 2 PC414 LL2 LL1 PC412

    3
    2
    1
    150U_D2_6.3VY_R15M @ 680P_0603_50V8J 0.1U_0603_25V7K PC415

    1
    2
    3

    2
    LG3 23 18 LG5 @ 680P_0603_50V8J

    1
    DRVL2 DRVL1
    @ 10K_0402_1%
    2

    PGND 22

    2
    C C
    PR408

    FB3 30 VOUT2

    0_0402_5%
    PR409
    VOUT1 10
    VL 32
    1

    REFIN2

    1
    11 FB5
    2VREF_ISL6237 FB1

    1 2 1 VREF2
    PC416
    0.22U_0603_25V7K 9
    VSW
    8 LDOREFIN
    PD401
    RB751V-40TE17_SOD323-2 29 5V_SKIP 2 1
    SKIPSEL PR410
    VL
    1 2
    @ 0_0402_5%
    1 2
    20 28 PR411
    PD402 PR412 NC PGOOD2 0_0402_5%
    VS RLZ5.1B_LL34 100K_0402_1%
    EN_LDO-1 EN_LDO SPOK <48>
    1 2 1 2 4 EN_LDO PGOOD1 13
    2
    200K_0402_5%

    2
    PR413

    PC417 3/5V_EN1 14 12 ILM1 2 1


    0.22U_0603_25V7K EN1 TRIP1 PR414
    301K_0402_1%

    TONSE
    VREF3
    1

    3/5V_EN2 27 31 ILIM2 2 1

    GND
    1

    EN2 TRIP2
    PR415

    2
    SN0806081RHBR_QFN32_5X5 301K_0402_1%

    21
    B PD403 VL B
    806K_0603_1%

    13/5V_NC
    @ RB751V-40TE17_SOD323-2
    2

    1 2 PR416

    13/5V_TON
    @ PR417

    0_0402_5%
    2VREF_ISL6237 1
    @

    1U_0603_10V6K
    PR419

    PC418
    47K_0402_5%
    PR418
    1

    2 1 1 2

    2
    <28,48> MAINPWON
    0.047U_0402_16V7K

    @ 0.047U_0402_16V7K

    0_0402_5% PR420
    0_0402_5%
    1

    2
    PC419

    PC420
    2

    2VREF_ISL6237

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    3VALW/5VALW
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 50 of 56
    5 4 3 2 1
    5 4 3 2 1

    UMA Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/11.5m+1.64/2= 13.7A

    D DIS Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+1.64/2= 10.72A D

    PL806
    PR526
    VCCP_IN 1 2 B+

    FBMA-L11-201209-121LMA50T_0805

    5
    6
    7
    8

    10U_1206_25V6M
    1
    150K_0402_5%
    M96@

    PC534
    PR525

    2
    240K_0402_5% 4
    VCCP_TON 1 2 PQ507
    PR526 PR527 AO4466_SO8
    PC535
    0_0402_5% 0_0603_5%
    1 2 VCCP_EN BST_VCCP1 2BST_VCCP-1
    1 2
    <36,37,46,53> SUSP#

    3
    2
    1
    65NV@ 0.1U_0603_25V7K

    1
    PL502

    15

    14
    1
    PC536 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
    0.1U_0402_16V7K 1 2

    EN_PSV

    TP

    VBST
    +VCCPP

    2
    M96@

    4.7_1206_5%
    2 13 UG_VCCP
    TON DRVH

    PR528
    PR529 3 12 SW_VCCP PC537
    VOUT LL

    5
    6
    7
    8

    10U_0805_6.3V6M
    220U_6.3VM_R15
    422_0603_1% 1
    +5VS 1 2 VCCP_V5FILT 4 11 VCCP_TRIP
    1 2 +5VS

    1 VCCP_SNB2
    V5FILT TRIP

    1
    90@ PC537

    PC538
    PR530 +

    AO4712_SO8
    VCCP_FB 5 10 16.5K_0402_1%
    VFB V5DRV

    2
    1

    LG_VCCP 2 330U_6.3V_M
    6 PGOOD DRVL 9 4

    PGND
    C C

    90@ PQ508
    PC539 65@

    GND

    1
    1U_0603_10V6K PC540
    2

    680P_0603_50V7K
    @ 47P_0402_50V8J PC541

    PC542
    1 2 4.7U_0805_10V6K

    3
    2
    1
    PU503 PQ508

    2
    TPS51117RGYR_QFN14_3.5x3.5

    PR531
    13.7K_0402_1%
    1 2
    S TR FDS6670AS_NL 1N SO8
    1

    65@

    PR532
    VFB=0.75V
    31.6K_0402_1%
    2

    PL807
    1.5V_IN 1 2 B+

    FBMA-L11-201209-121LMA50T_0805

    5
    6
    7
    8

    10U_1206_25V6M
    1
    PC501
    PR501

    2
    240K_0402_5% 4
    1.5V_TON 1 2 PQ501 Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+2.28/2= 11.04A
    PR518 PR519 AO4466_SO8
    PC525
    0_0402_5% 0_0603_5%
    1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
    1 2
    <36,37,46,52> SYSON

    3
    2
    1
    B B
    0.1U_0603_25V7K
    1

    PL501
    15

    14
    1

    PC526 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
    @0.1U_0402_16V7K 1 2
    EN_PSV

    TP

    VBST

    +1.5VP
    2

    4.7_1206_5%
    2 13 UG_1.5V
    TON DRVH

    PR520
    PR521 SW_1.5V

    220U_D2_4VY_R15M
    3 VOUT LL 12

    5
    6
    7
    8

    10U_0805_6.3V6M
    422_0603_1% 1
    +5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
    1 2 +5VALW

    1 1.5V_SNB 2
    V5FILT TRIP

    1
    PC527

    PC528
    PR522 +

    AO4712_SO8
    1.5V_FB 5 10 16.5K_0402_1%
    VFB V5DRV

    2
    1

    LG_1.5V 2
    6 PGOOD DRVL 9 4
    PGND

    PQ506
    PC529
    GND

    1U_0603_10V6K PC530
    2

    680P_0603_50V7K
    @ 47P_0402_50V8J PR909

    PC532
    1 2 100K_0402_1% PC531
    7

    3
    2
    1
    1 2 PU501 4.7U_0805_10V6K
    +1.5VP
    2

    2
    TPS51117RGYR_QFN14_3.5x3.5

    PR523
    1.5V_PGOOD <8>
    22.1K_0402_1%
    1 2
    1

    PR524
    21K_0402_1% VFB=0.75V
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    1.5V/VCCP/0.75V
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 51 of 56
    5 4 3 2 1
    5 4 3 2 1

    Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=13k*9u/15m+1/2*2.7=9.15A

    D
    PJ601 D
    1.8V_IN 2 1 B+
    2 1
    @ JUMP_43X79

    5
    6
    7
    8

    10U_1206_25V6M
    1
    PC601
    90@ PR601

    2
    240K_0402_5% 4
    1.8V_TON 1 2 PQ601
    90@ PR602 90@
    PR603 AO4466_SO8 90@
    0_0402_5% 0_0603_5% 90@
    1 2 1.8V_EN BST_1.8V 1 2BST_1.8V-1
    1 2
    <36,37,46,51> SYSON

    3
    2
    1
    PC603
    0.1U_0603_25V7K

    15

    14
    1

    1
    90@ 90@ PL601
    PC604 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

    EN_PSV

    TP

    VBST
    @ 0.1U_0402_16V7K 1 2 +1.8VP

    2
    2 13 UG_1.8V
    TON DRVH

    @ 4.7_1206_5%
    3 12 SW_1.8V
    VOUT LL

    PR604
    90@ PR605

    5
    6
    7
    8

    10U_0805_6.3V6M
    422_0603_1% 1.8V_V5FILT 1.8V_TRIP

    220U_D2_4VY_R15M
    4 V5FILT TRIP 11 1 2 1
    +5VALW 1 2 90@ PR606 +5VALW

    1 1.8V_SNB 2

    1
    90@ PC605

    90@ PC606
    1.8V_FB 5 10 13K_0402_1% +
    VFB V5DRV

    AO4712_SO8
    6 9 LG_1.8V

    2
    PGOOD DRVL
    1
    2

    PGND
    4

    GND

    PQ602

    @ 680P_0603_50V7K
    90@ PC607
    1U_0603_10V6K PC609
    2

    1
    @ 47P_0402_50V8J

    8
    C C

    PC608
    1 2 90@ PU601 PC610

    3
    2
    1
    TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K

    2
    90@
    90@
    PR607 90@
    30.1K_0402_1%
    1 2
    1

    PR608
    20.5K_0402_1% VFB=0.75V
    90@
    2

    +1.5V

    +3VALW
    1

    PJ502
    1

    @ JUMP_43X79

    1
    2

    PJ609

    1
    B PU502 @ JUMP_43X79 B
    2

    1 VIN VCNTL 6 +3VALW

    2
    2 5 PU604 65@

    2
    GND NC
    1

    PC519 LDO_1.8V_IN 1 6 +5VALW


    VIN VCNTL
    1

    4.7U_0805_6.3V6K 3 7 PC520
    PR515 VREF NC 1U_0603_6.3V6M 2 5
    2

    GND NC

    1
    1K_0402_1% 4 8 PC623
    VOUT NC

    1
    <32,46> SUSP 1 PR910 2 4.7U_0805_6.3V6K 3 VREF NC 7 PC624
    0_0402_5% 9 65@ PR623 1U_0603_6.3V6M
    2

    2
    TP 1K_0402_1% 65@
    4 VOUT NC 8
    APL5331KAC-TRL_SO8 65@
    9

    2
    TP
    1

    @ PR516
    @PR516 +0.75VP
    1

    0_0402_5% D PR517 LDO_1.8V_REF APL5331KAC-TRL_SO8


    1 2 2 1K_0402_1% PC521
    <8,46> SYSON#
    1

    1
    G 0.1U_0402_16V7K PR626 +1.8VP
    2
    1

    1
    PC523 65@ 0_0402_5% D PR628
    S
    3

    PC522 10U_0805_6.3V6M 1 2LDO_1.8V_EN


    2 1.24K_0402_1% PC627
    <8,46> SYSON#
    2

    1
    @ 0.1U_0402_16V7K G 65@ 0.1U_0402_16V7K
    2

    2
    1
    S 65@ PC629

    2
    PC631 10U_0805_6.3V6M

    2
    PQ505 @ 0.1U_0402_16V7K 65@

    2
    2N7002W-T/R7_SOT323-3

    PQ609 65@
    2N7002W-T/R7_SOT323-3

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    VGA_CORE/1.8V/1.1V
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 52 of 56
    5 4 3 2 1
    5 4 3 2 1

    PL805

    B+ 1 2

    FBMA-L11-201209-121LMA50T_0805 Iocp=(Iv+I/2)/1.3; Iv=(19uA*5.1K)/(1.3*1.75m)=42.59A ;


    D 90@ I=(19-0.9)0.9/19*1UH*231K=3.71A; Iocp=(42.59+3.71/2)=44.44A D
    LX_VCORE

    10U_1206_25VAK

    10U_1206_25VAK
    @
    PT3 PAD

    10U_1206_25VAK
    DH_VCORE

    1
    PR868 90@

    PC838

    PC839

    PC853
    BST_VCORE
    1 2 1 2
    2.2_0603_5%

    2
    90@ PC840 0.1U_0603_25V7K
    90@ 90@ 90@ +5VS

    5
    PR869 90@
    0_0603_5% PQ807
    TPCA8030-H_SOP

    16

    15
    8

    1
    PU500 90@

    2
    1 PR8702 6268_VCORE

    PHASE
    GND

    PGOOD

    UG

    BOOT
    90@ 4
    4.7_0603_5%
    3 VIN PVCC 14 1 2 PC841 DCR=1.1m OHM
    +3VS 90@
    2.2U_0603_6.3V6K

    3
    2
    1
    90@
    6268_VCORE 4 13 DL_VCORE PL804
    VCC LG S COIL 0.36UH +-20% SF-I104-R36 23A
    2

    PC842 1 2 +VGA_COREP
    PR871 2.2U_0603_6.3V6K

    1
    @ 10K_0402_5% 90@ 12
    2

    PGND PR875

    2
    4.7_1206_5%

    330U_D2E_2.5VM_R9M

    330U_D2E_2.5VM_R9M
    PR873 1 1
    1

    0_0402_5%
    PR874 90@

    90@
    PR876
    SUSP# 1 2 5 11 ISEN_VCORE
    1 2 + +
    <36,37,46,51> SUSP#

    1 2
    EN ISEN

    90@ PC847

    90@ PC843
    4 4

    COMP
    C 0_0402_5% 5.1K_0402_1% PC844 C

    FSET

    1
    90@ 90@ 2 2

    VO
    FB
    1

    680P_0603_50V7K

    2
    6

    10

    3
    2
    1

    3
    2
    1
    PC845 ISL6268CAZ-T_SSOP16
    PR878
    2

    2
    0.1U_0402_16V7K @ 90@
    @ PQ808 90@ 1 2 +VGASENSE <19>
    TPCA8028-H_SOP-ADVANCE8-5 PQ809 90@
    TPCA8028-H_SOP-ADVANCE8-5
    PR877 10_0402_1%

    1
    1
    90@

    1
    22P_0402_50V8J

    90@ VFB=0.6V 3K_0402_1%


    Rds=3.2mOHM
    1

    1
    PR879
    2200P_0402_25V7K

    90@
    90@ PC846

    PR880
    49.9K_0402_1% PC500
    0.01U_0402_25V7K
    2

    2
    +3VS
    90@ PC848

    ZZZ @ PR881 NV@

    2
    12.1K_0402_1%
    1

    1
    44.2K_0402_1%
    PQ810 90@ PR911
    2

    2N7002W-T/R7_SOT323-3 10K_0402_1%

    1 1
    1
    GROUP PARTS ISL6268CAZ PR883 M96@
    90@ D 10K_0402_1%

    2
    PR882 2 1 2
    GPU_VID0 GPU_VID1 NB9P N10P 90@ G M96@ PR888

    1
    5.62K_0402_1% D 10K_0402_1%
    PR881=12.1K S

    1
    0 0 0.9V 0.9V 2 1 2 GPU_VID1 <17>
    NV 1 1 PR882=5.62K G M96@

    2
    X 1.1V S

    3
    PR885=34.8K PR892
    +1.5VS
    0 1 1.05V X 10K_0402_1%
    90@

    1
    B PQ812 M96@ B

    1
    1

    PR885 90@ PC849 2N7002W-T/R7_SOT323-3


    PJ607 @ GPU_VID0 GPU_VID1 VGA_CORE 34.8K_0402_1% 0.22U_0402_10V4Z NV@ PR890
    1

    JUMP_43X79 +5VS 90@ 1 2


    0 0 1.2V

    2
    10K_0402_1%+3VS
    2

    @M96 PR881=7.15K
    1.15V
    2

    PC167 90@ 1 0 PR882=5.62K

    1
    1U_0603_6.3V6M 1.0V
    0 1 PR885=34.8K PR912
    2
    1

    0.9V 10K_0402_1%
    90@ PC850
    90@PC850 PU603 1 1 M96@

    1
    4.7U_0805_6.3V6K D M96@ PR886
    6 +1.1VSP
    2

    2
    VCNTL
    5 VIN VOUT 3 2 1 2
    1

    PR268 9 4 90@ PQ811 G 10K_0402_1% PR889


    VIN VOUT
    1

    1
    D
    22U_0805_6.3V6M

    0_0402_5% PR269 2N7002W-T/R7_SOT323-3 S 10K_0402_1%

    1
    90@ PC852

    <36,37,46,51> SUSP# 1 90@ 2 8 90@ PC170 2 1 2 GPU_VID0 <17>


    2

    EN 1.15K_0402_1% 90@ G M96@


    7 2
    GND

    POK FB
    S
    2

    3
    1

    2
    PC171 APL5912-KAC-TRL_SO8 0.01U_0402_25V7K
    1

    @ 0.1U_0402_16V7K +3VS 90@ PR893


    PR908
    2

    PR881 10K_0402_1%
    1 2 PR270 PQ813 M96@ 90@
    90@ 3K_0402_1% 90@ PC851
    90@PC851 2N7002W-T/R7_SOT323-3

    1
    90@ 0.22U_0402_10V4Z
    2

    4.7K_0402_5% NV@ PR887


    PCIE_OK <17> 1 2
    7.15K_0402_1% 10K_0402_1%
    M96@

    A
    VFB=0.8V A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    VGA_CORE/1.1VSP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 53 of 56
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    @ 10K_0402_5%
    1.91K_0402_1%
    1

    1
    D D

    PR830

    PR831
    2

    2
    <8,29> VGATE
    @ CLK_ENABLE#
    1 2
    PT1 PAD

    <8,29>
    DPRSLPVR
    PR832 +CPU_B+ PL801
    @ 0_0402_5% +5VS FBMA-L11-453215-121LMA90T_2

    <37>
    VR_ON
    +3VS

    @ PT2 PAD
    1 2 B+

    2200P_0402_50V7K
    10U_1206_25V6M

    10U_1206_25V6M
    1 PR913 2 1 PR834 2 1

    220U_25V_M
    PC808

    PC804

    PC809
    @ 0_0402_5% 0_0402_5%
    +

    PC805
    2

    2
    PMON
    2

    0_0402_5%
    1CPU_VREF

    499_0402_1%

    5
    0_0402_5%
    124K_0402_1%

    0_0402_5%

    0_0402_5%
    PQ801

    2
    TPCA8030-H_SOP

    1
    1

    1
    4

    CPU_DPRSLPVR
    CPU_CLK_EN#
    CPU_TRIPSEL

    CPU_VR_ON 2

    1
    CPU_OSRSEL

    CPU_TONSEL

    PR837

    PR838
    CPU_V5FILT

    CPU_ISLEW

    2
    PR865
    S COIL 0.36UH +-20% SF-I104-R36 23A

    2
    PR833

    PR835

    PR836
    2 1

    3
    2
    1
    PC824 4 1 +CPU_CORE
    1U_0402_6.3V6K

    5
    6
    7
    8

    1
    3 2
    +5VS PL802

    SI4634DY-T1-E3_SO8
    PR819

    1
    C C

    17.8K_0402_1%
    4.7_1206_5%
    41

    40

    39

    38

    37

    36

    35

    34

    33

    32

    31

    1CPU1_SNB

    PR801
    2
    CPU_VREF
    1 2 ISLEW

    OSRSEL

    TONSEL

    TRIPSEL

    CLK_EN#
    GND

    V5FILT

    PWRMON

    VR_ON

    DPRSLPVR

    PGOOD

    2
    PR839 PD801 4 4 PR840

    @ PQ803
    4.75K_0402_1% 1SS355_SOD323-2 69.8K_0402_1%

    2
    1 2CPU_DROOP 1 30 UGATE_CPU1 1 2
    PC825 68P_0402_50V8J DROOP DRVH1

    1
    CPU_CSP1 2 1 1 2CPU_VREF 2 29 BOOT_CPU1
    1 PR841 2BOOT_CPU1-1
    1 2 PC815

    3
    2
    1

    3
    2
    1
    VREF VBST
    PR861 470_0402_1% PC826 0.22U_0603_10V7K 2.2_0603_5% PC827 680P_0603_50V8J 1 2CPU_SN-1
    1 2

    2
    2

    3 28 PHASE_CPU1 0.22U_0603_10V7K PR842 PH801


    GND LL1

    CPU_CSN1
    CPU_CSP1
    PC836 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT
    100P_0402_50V8J 1 2 CPU_CSP1-2 4 27 LGATE_CPU1 +CPU_B+ 1 2
    1

    CPU_CSN1 2 PC828 33P_0402_50V8K CSP1 DRVL1 PQ802 PC829


    1 +5VS

    10U_1206_25V6M

    10U_1206_25V6M
    PR862 470_0402_1% 1 2 CPU_CSN1-1 5 CSN1 V5IN 26 1 2 TPCA8028-H_SOP-ADVANCE8-5 0.033U_0402_16V7K

    1
    CPU_CSN2 2 1 PC830 33P_0402_50V8K PC831 10U_0603_6.3V6M

    PC817

    PC818
    PR863 470_0402_1% 1 2 CPU_CSN2-1 6 CSN2
    PU801
    PGND 25
    2

    PC832 33P_0402_50V8K TPS51620RHAR_QFN40_6X6

    2
    PC837 1 2 CPU_CSP2-2 7 CSP2 DRVL2 24 LGATE_CPU2
    100P_0402_50V8J PC833 33P_0402_50V8K 4
    1

    CPU_CSP2 2 1 CPU_GNDSNS 8 23 PHASE_CPU2


    PR864 470_0402_1% GNDSNS LL2 PQ804
    CPU_VSNS 9 22 BOOT_CPU2
    1 PR846 2BOOT_CPU2-1
    1 2 TPCA8030-H_SOP S COIL 0.36UH +-20% SF-I104-R36 23A
    VSNS VBST2 2.2_0603_5% PC834

    3
    2
    1
    CPU_THERM UGATE_CPU2 0.22U_0603_10V7K
    DPRSTP#

    10 THERM DRVH2 21 4 1
    1

    VR_TT#

    1
    0_0402_5%

    0_0402_5%

    1 2 3 2
    VID6

    VID5

    VID4

    VID3

    VID2

    VID1

    VID0
    PSI#

    +5VS

    5
    6
    7
    8
    PL803

    SI4634DY-T1-E3_SO8
    1

    1
    PR844

    PR845

    17.8K_0402_1%
    PD802 PR829

    PR848
    1SS355_SOD323-2 4.7_1206_5%
    2

    11

    12

    13

    14

    15

    16

    17

    18

    19

    20

    1CPU2_SNB
    PR849

    2
    20K_0402_5% PR850
    1CPU_DPRSTP#

    B 4 4 69.8K_0402_1% B
    2

    2
    VID6

    VID5

    VID4

    VID3

    VID2

    VID1

    VID0
    PSI#

    @ PQ806
    1 2
    1

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%

    1 2CPU_SN-2
    1 2 PH803

    3
    2
    1

    3
    2
    1
    PC823 PR851 100K_0603_1%_TH11-4H104FT

    2
    1

    CPU_CSN2
    CPU_CSP2
    PR843 PR847 680P_0603_50V8J 28.7K_0402_1%
    100_0402_5% 100_0402_5% 1 2
    2

    PC835
    0.033U_0402_16V7K
    PR852

    PR853

    PR854

    PR855

    PR856

    PR857

    PR858

    PR859

    PR860
    2

    1
    <6>

    <6>
    VSSSENSE

    VCCSENSE

    PQ805
    +CPU_CORE

    TPCA8028-H_SOP-ADVANCE8-5
    CPU_VID3<6>

    CPU_VID2<6>
    <6,8,28>
    H_DPRSTP#

    H_PSI#

    CPU_VID6

    <6>

    <6>

    <6>

    <6>

    <6>

    <6>
    CPU_VID5

    CPU_VID4

    CPU_VID1

    CPU_VID0

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    +CPU_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 54 of 56
    5 4 3 2 1
    5 4 3 2 1

    Page Reason for change Modify list


    DVT Change Diode 4148 vendor for layout footprint PD101,PD103,PD301
    Change PR874 to 5.9K
    modify VGA_core OCP to 29A
    D Remove PC845 & change PR873 to 0 ohm D
    modify VGA_core sequence for NV and ATI
    Change PR526 to 150K ohm and PC536 to 0.1U
    modify 1.05V sequence for ATI
    PQ810 & PQ811 for DIS, PQ812 & PQ813 for M96
    Change 2N06 to 2N7002 for costdown

    Add snubber & bead at cpu_core for EMI request Add PR819 & PR829 to 4.7 OHM , PC815 & PC823 to 680pF,
    Change PL801 to 120 ohm bead & change PR841 & PR846 to 2.2 OHM

    Add snubber & bead at VGA_core for EMI request Add PR875 to 4.7 OHM , PC844 to 680pF,
    Change PJ605 to 120 ohm bead and change PR868 to 2.2 OHM
    Add snubber & bead at VCCP & 1.5VP for EMI request Add PR528 & PR520 to 4.7 OHM , PC542 & PC532 to 680pF
    change PJ506 and PJ501 to 120 ohm bead

    C Add boost res. & bead & snubber at charger for EMI request Change PJ301 to 120 Ohm bead and Changer PR307 to 2.2 OHM, C

    Add PR312 to 4.7 Ohm & PC318 to 680P


    Change 1.8UH vender to mgalaer for ZIZI nosie PL502,PL501,PL601(DIS)
    Modify 1.05V OCP for UMA(12A~19A) & DIS for (8A~12A) Change PR530 to 16.5K & PQ508 to FDS6670

    Modify CPU loadline Change PR839 to 4.64K

    Modify VGA CHOKE to 4mm high PL804

    Modify 1.1V to APL5912 for over loading PU603

    Change VCCP output cap to 330U for reduce ripper PC537


    Change PU500 & PC500 to X76 group for 2nd Del PU500 & PC500 in 90W SKU

    B
    Add 10UF in charger output for unstable PC331 B

    Modify 1.5V OCP to 8A~12A Change PR522 to 16.5K

    PVT Modify ATI VGA_core from 1.1 to 1.15V Change PR881 to 7.15K
    Modify 220U/25V vender to SANYO from PPM suggest
    Add 10UF in VGA B+ for over current(VGA B+ about 5.6A) Add PC853 to 10U
    Modify CPU loadline Change PR839 to 4.75K
    Change VGA frquency to 300K, reduse △I Change PR880to 44.2K
    Change VGA FB cap for better response Change PC848 to 2200pF
    Change VGA OCP set to around 41A Change PR874 to 8.66K
    Change VGA output choke for rating. Change PL804 to 0.36U

    A
    Add extra VGA Low Side MOS Add PQ809 A

    Change VGA high mos for cost down. Change PQ807 to S TR TPCA8030-H 1N SOP-ADV
    Change CPU high mos for cost down. Change PQ801 and PQ804 to S TR TPCA8030-H 1N SOP-ADV
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    PIR (PWR)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 55 of 56
    5 4 3 2 1
    5 4 3 2 1

    Page Reason for change Modify list


    PVT Change VGA response Change PR876 to 0 and PR878 to10
    Change VGA OCP set Change PR876 to 0 and PR874 to 5.1K

    D D

    C C

    B B

    PVT

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
    PIR (PWR)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    KHLBX MB Schematic
    Date: Monday, January 19, 2009 Sheet 56 of 56
    5 4 3 2 1
    www.s-manuals.com

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