Acer Iconia Tab A701 - Schematics PDF

A B C D E
ZZZ0
PCB
MB
1 1
Compal Confidential
PICASSO M Schematics Document
2 2
Nvdia(T30S) + LPDDRII
QAJ70-LA-8022P
2012-03-28 REV: 1.0
3
The content in this document contains confidential information of Compal Electronics, Inc. 3
that is protected under all applicable trade secrets laws and regulations.
If you are not the intended recipient or otherwise authorized to receive such information,
please do not copy, distribute or otherwise use the information contained herein and please
destroy this communication accordingly.
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4019FQ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SCHEMATIC MB A8022
Date: Tuesday, July 10, 2012 Sheet 1 of 38
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A B C D E
Compal Confidential
Model Name : NVIDIA T30S System Block Diagram
26MHz
32KHz
1
LPDDR2 1
512MB/1GB
PMIC CORE_PWR_REQ P.9
TPS659110
Power ON CPU_PWR_REQ JTAG Debug
Test Point
P.7
VIN SYS_RESET_N I2S
Audience Audio Codec Audio AMP Speaker x 2
PMU_32K_IN UART4 eS305 WM8903 APA2010 (1W)
P.14 P.15 P.15 P.15
PWR_I2C
P.31~P.33
GPS Antenna MIC & Audio Jack
P.15
UART2 Broadcom
2 2
HDMI_DDC BCM47511
Micro HDMI HDMI Switch Nvidia P.21
P.19 (1.8V/3.3V) BT/WLAN Antenna
P.13 T30S
UART3
Touch Panel SDIO AzureWave
Control AW-AH662
P.13 DAP
P.22
10.1" LCD LVDS Transmitter 3G Modem Antenna
1920*1200 (V105A)
P.12
USB2 3G Modem Module SIM Card
Client P.18 P.18
Micro USB Signal Switch Host

P.20 P.20
3
P-Senser 3
IQS12800100TSR
CAMERA Dock/B
CIS(MIPI)
5M(CJAA525) I2C
2M(CBFA152) CAM_I2C
P.17
CAM_I2C CAM_I2C CAM_I2C
SDIO4 SDIO1
EEPROM (1.8V) (3.3V) GYRO Sensor Light Sensor E-Compass
MPU-3050 STK2203 AKM8975
P.10
eMMC Micro SD slot P.16 Func/B Dock/B
P.11 P.20
IME
4
G-Sensor 4
KXTF9-4100
P.16

4019FQ
C B
SCHEMATIC MB A8022
A B C D E
5 4 3 2 1
Board ID
Voltage Rails
Power Plane Description
VIN Adapter power supply (19V)
PICASSO 2
B+ AC or battery power rail for power circuit.
+VDD_1V2_RTC_TEGRA Power for RTC and always-on core logic.
VDD_1V2_SOC Power for remainder of core logic
D D
+AVDD_1V1_PLL_TEGRA AVDD_PLL power rail
+VDD_1V8_PMU_VRTC RTC power rail
+VDD_1V8_SYS_TEGRA System power rail
+AVDD_3V3_USB_TEGRA USB power rail
+VDD_2V85_EMMC Core voltage for EMMC
+VDD_1V8_CAM_TEGRA Core voltage for CAMERA
+AVDD_3V3_HDMI_S HDMI power rail
VDD_1V8_GEN 1.8V switched power rail for standby mode
+VDD_3V3_DDR_RX_TEGRA DDR RX power rail
+3VS 3.3V switched power rail for standby mode
+5VS 5V switched power rail for standby mode
+VDD_LED_BL LED power rail
+VDD_3V3_SDMMC1_TEGRA Micro SD power rail
+VDD_VCM_3V3 CAMERA power rail
+VDD_1V2_DDR_MEM DDR power rail
C C
GEN1_I2C <+VDD_1V8_SENSOR >

Device Address<Write,Read>
Gyro 0xD0 , 0xD1

E Compass 0x18 , 0x19
Light Senser 0x38 , 0x39
PICASSO M
LPDDR2
B GEN2_I2C / TS_I2C < +VDD_3V3_GMI_TEGRA > B
Touch Screen 0x98 , 0x99
CAM_I2C < +VDD_1V8_CAM_TEGRA >

LVDS strap pin
Camera 5M 0x78 , 0x79
Camera 2M 0x20 , 0x21
Flash LED 0x66 , 0x67
PWR_I2C < +VDD_1V8_SYS_TEGRA>

Thermal Senser 0x98 , 0x99

A
ES305 0x3E A
Codec 0x34 , 0x35

PMU 0x2D
TPS62361 0x60
BATT Conn 0xAA , 0xAB
EEPROM (Low level) 0xA0 , 0xA1
EEPROM (High level) 0xA2 , 0xA3
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
+VDD_3V3_GMI_TEGRA
+VDD_3V3_GMI_TEGRA
R453 L49 27NH_LQG15HS27NJ02D_5%_0402
NV_LCD_PCLK 2 1 LCD_PCLK_R 1 2 U1E
LCD_PCLK <12>
47_0402_5% 1 1 NAND_D0 R1 2 1 100K_0201_5%
C165 C164
4/21 GMI BOOT_PD R2 2 1 100K_0201_5%
12P_0201_50V8J 12P_0201_50V8J (1.8/3.3V)
2 2
P12 VDDIO_GMI_1 GMI_AD00 J7 Z NAND_D0
RF T12 VDDIO_GMI_2 GMI_AD01 K6 Z BOOT_PD 8/22 Change BOM structure to LPDDR2 & EMMC
J3 Z
3300P_0201_16V6K
0.1U_0201_10V6K
GMI_AD02
2 1 2 GMI_AD03 H2 Z
P4 Z NAND_D4 +VDD_3V3_GMI_TEGRA
4.7U_0402_6.3V6M
+VDD_3V3_LCD_TEGRA GMI_AD04
P6 Z
C3
U1I C147 C4 NAND_D5
GMI_AD05
8/21 LCD
GMI_AD06 N3 Z NAND_D6 X76_SAM_1GB@
1 2 1
GMI_AD07 R3 Z NAND_D7 NAND_D4 R38 2 1 100K_0201_5%
(1.8/3.3V) GMI_AD08 G3 PD LCD_PWM_OUT <13>
AG23 AN21 PD NV_LCD_PCLK E1 PD NAND_D5 R43 2 @ 1 100K_0201_5%
VDDIO_LCD_1 LCD_PCLK GMI_AD09 DISPOFF# <13,31>
D
AH24 VDDIO_LCD_2 GMI_AD10 J5 PD EN_T30S_FUSE_3V3 <23> D
PU J1 PD NAND_D6 R84 @ 1 100K_0201_5%
0.1U_0201_10V6K
LCD_WR* AK24 GMI_AD11 LCD_DCR <13> 2

1 2 AR19 PD F2 Z PCB_ID0
LCD_DE PU LCD_DE <12> GMI_AD12
F4 Z PCB_ID1 NAND_D7 R85 @ 1 100K_0201_5%
4.7U_0402_6.3V6M
LCD_HSYNC AK20 LCD_HSYNC <12> GMI_AD13 2

PU P2 Z
C1
C2 AL17 PCB_ID2
LCD_VSYNC LCD_VSYNC <12> GMI_AD14
GMI_AD15 R5 Z EN_SENSOR_3V3 <23>
2 1 PD X76_ELP_1GB@
LCD_D00 AR17 LCD_D00 <12>
AP26 PD 11/6 Add for COMPAL EMI request. NAND_D4 R5 2 1 100K_0201_5%
LCD_D01 PD LCD_D01 <12>
LCD_D02 AM18 LCD_D02 <12>
AN19 PD P8 NAND_D5 R6 2 1 100K_0201_5%
LCD_D03 PD LCD_D03 <12> GMI_A16 VIB_EN_T30S <20>
LCD_D04 AJ23 LCD_D04 <12> GMI_A17 M8 TS_PWR_EN <13>
AR23 PD N9 NAND_D6 R7 2 1 100K_0201_5%
LCD_D05 PD LCD_D05 <12> GMI_A18 EN_VDDLCD_T30S <13>
LCD_D06 AK16 LCD_D06 <12> GMI_A19 R9 EN_WIFI_VDD <22>
AK22 PD NAND_D7 R8 2 1 100K_0201_5%
LCD_D08 AU21
PD LCD_D08 <12> PU
02/17 Change to 0201 shortpad
LCD_D09 AM26 LCD_D09 <12> GMI_CS0* R11 TS_INT# <13>
AR21 PD P10 PU EN_SENSOR_3V3
LCD_D10 PD LCD_D10 <12> GMI_CS1* 1 CHARGER_STAT <27>
AU27 G5 BOARD_ID0 R158 0_0201_5%
LCD_D11 PD LCD_D11 <12> GMI_CS2* 1 +VDD_3V3_GMI_TEGRA
AT18 K8 BOARD_ID1 2 @ 1 EN_P_SENSOR EN_P_SENSOR <20> 8/22 Change BOM structure
LCD_D12 LCD_D12 <12> GMI_CS3*
1
AJ17 PD H4 PU
LCD_D13 PD LCD_D13 <12> GMI_CS4* PU POUT_3G_1 <20>
AH18 M10 R18
LCD_D14 PD LCD_D14 <12> GMI_CS6* PU TEMP_ALERT# <7>
AL21 L9 100K_0201_5% PCB_ID0 R63 2 1 100K_0201_5%
LCD_D15 PD LCD_D15 <12> GMI_CS7* POUT_WIFI <16>
AM22 QAJ70@
AJ19 PCB_ID1 R87 2 1 100K_0201_5%
LCD_D17 <12>
2
LCD_D17 PD
LCD_D18 AT20 LCD_D18 <12> GMI_ADV* M4 1 BOOT_PD NH660@
AT24 PD PCB_ID2 R100 2 1 100K_0201_5%
LCD_D20 AN27 LCD_D20 <12> GMI_CLK L1 0 LTE@
AU23 PD BOARD_ID0 R78 2 1 100K_0201_5%
LCD_D22 AR27 LCD_D22 <12> GMI_RST* L5 0 EN_HDMI_5V0 <19>
AM24 PD N5 PU TS_PWR_EN BOARD_ID1 R88 2 1 100K_0201_5%
LCD_D23 LCD_D23 <12> GMI_WAIT 3G_DISABLE# <18>
GMI_WP* L3 PU 3G_WAKE# <18>
1
GMI_IORDY R7 PU POUT_3G <20>
PCB_ID0 R152 2 1 100K_0201_5%
AM20 PD R12 QAJ50@
LCD_M1
GMI_OE* M2 1 FORCE_RECOVERY# 100K_0201_5% PCB_ID1 R153 2 1 100K_0201_5%
GMI_WR* M6 1 NOR_BOOT AH663@
AN17 PD PCB_ID2 R154 2 1 100K_0201_5%
2
LCD_PWR0 PD NONLTE@
LCD_PWR1 AP20
C AN25 PD L7 Z BOARD_ID0 R79 2 1 100K_0201_5% C
LCD_PWR2 LVDS_SHTDN# <12> GMI_DQS TS_RST# <13>
@
AK26 PU BOARD_ID1 R89 2 1 100K_0201_5%
LCD_SCK PU @
LCD_CS0* AL23
AP18 PU EN_WIFI_VDD
LCD_CS1* PU
LCD_SDOUT AM28
AR25 PU
LCD_SDIN
1
R17 +VDD_3V3_GMI_TEGRA
AL27 PD 100K_0201_5%
LCD_DC0 PD
LCD_DC1 AP24 GEN2_I2C_SCL D2 Z GEN2_I2C_SCL <13>
NOR_BOOT R22 2 1 100K_0201_5%
E3 Z
2
GEN2_I2C_SDA GEN2_I2C_SDA <13>
AK18 PU
CRT_HSYNC
CRT_VSYNC AJ21 PU 9/15 Modify R23 from 100K to 47K.
9/15 Add R90 for FORCE_RECOVERY issue
DDC_SCL AH20 Z
DDC_SCL_R <19> 9/19 Modify Q44 part number to SB00000J500 .
AT26 Z
DDC_SDA DDC_SDA_R <19> +VDD_3V3_GMI_TEGRA
T30S-R-A3-1.4G_FCCSP681
AN23 Z
HDMI_INT HDMI_DET_T30S <19>
1
+VDD_3V3_GMI_TEGRA R23
47K_0201_1% T21 PAD
+VDD_1V8_SYS_TEGRA @
2
1
1
T30S-R-A3-1.4G_FCCSP681 9/29 Leakage Issue
@ R11 R10 @ R90 47K_0201_1%
Modify R10&R11 from mount to unmount 1 2 FORCE_RECOVERY#
5
2.2K_0201_1% 2.2K_0201_1% U55
D
1
U1K 1
G Vcc
<7,20> VOL_UP#
2
GEN2_I2C_SCL B Q44
Y 4 2
1
+AVDD_3V3_HDMI_S GEN2_I2C_SDA 2 G S TR DMN3150LW-7 1N SOT-323-3
<7,20> VOL_DOWN# A
L1 10/21 HDMI R54 S
3
1M_0201_1% Vth=1.4V
3
1 2 AVDD_HDMI_R AP8 AR9 74AUP1G02GW_TSSOP5
B AVDD_HDMI HDMI_TXCN HDMI_TXCN <19> B
MPZ1005S300CT_2P AN9
(3.3V) HDMI_TXCP <19>
2
HDMI_TXCP
2
HDMI_TXD0N AP12 HDMI_TXD0N <19>
C7
HDMI_TXD0P AN13 HDMI_TXD0P <19> 08/16 Change U55 footprint
0.1U_0201_10V6K
1
AR13
08/16 Delete U56 footprint
HDMI_TXD1N HDMI_TXD1N <19> Add
HDMI_TXD1P AP14 HDMI_TXD1P <19>
VDD_1V8_GEN AU11
HDMI_TXD2N HDMI_TXD2N <19>
L2 HDMI_TXD2P AT12 HDMI_TXD2P <19>
1 2 AVDD_HDMI_PLL AT8
MPZ1005S300CT_2P AVDD_HDMI_PLL HDMI_PROBE +VDD_1V8_SDMMC4_TEGRA
AR11 U1F
2
(1.8V) HDMI_PROBE @ PAD T1 SDMMC4 : eMMC
C8 AM8 HDMI_RSET 5/21 SDMM4
0.1U_0201_10V6K HDMI_RSET
1 Z
E7 VDDIO_SDMMC4 SDMMC4_DAT0 B6 EMMC_DA0 <11>
1
G9 Z
R26 SDMMC4_DAT1 Z EMMC_DA1 <11>
(1.2/1.8V) SDMMC4_DAT2 C5 EMMC_DA2 <11>
T30S-R-A3-1.4G_FCCSP681 Z
0.1U_0201_10V6K
1K_0201_1% SDMMC4_DAT3 B4 EMMC_DA3 <11>
Z
10/03 Co-lay SOT-23 and SC-70 1 2 SDMMC4_DAT4 A5
D6 Z EMMC_DA4 <11>
2
C5 C6 SDMMC4_DAT5 Z EMMC_DA5 <11>

SDMMC4_DAT6 C7 EMMC_DA6 <11>
U1J Z
SB93413000000 and SB000009O00 4.7U_0402_6.3V6M
2 1 SDMMC4_DAT7 D8 EMMC_DA7 <11>
Q6
9/21 VDAC
SDMMC4_CLK F8 PU EMMC_CLK <11>
AO3413_SOT23-3 (2.8V) SDMMC4_CMD H10 PU EMMC_CMD <11>
AD2 AVDD_VDAC VDAC_R AH14
D
1 3 VDAC_G AJ13
AH12 B8 Z
VDAC_B SDMMC4_RST* EMMC_RST# <11>
G
2
+3VS Q2 +AVDD_3V3_HDMI_S
@
NTS4101PT1G_SC70-3
D
A 1 3 VDAC_VREF AN11 A
10MIL
1
0.1A 3.3V
R27 AM12
G
2
1M_0201_1% VDAC_RSET
2
EN_HDMI_3V3# T30S-R-A3-1.4G_FCCSP681
VDD_1V8_GEN
D Security Classification Compal Secret Data Compal Electronics, Inc.
1
2 Q3 2011/06/20 2012/06/20 Title

G BSS138W-7-F_SOT323-3
Issued Date Deciphered Date
S 4019FQ
3
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
Acer request
VDD_1V2_MEM
U1D
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VDD_1V2_MEM
1 1 1 1
3/21 DDR MEMORY
D D
C10
C11
C12
C13
(1.2/1.25/1.35/1.5V)
M14 VDDIO_DDR_01 DDR_DQ00 E29 DDR_A_D0 <9>
2 2 2 2
M16 VDDIO_DDR_02 DDR_DQ01 F28 DDR_A_D1 <9>
M18 VDDIO_DDR_03 DDR_DQ02 B30 DDR_A_D2 <9>
M20 E25
SDMMC1 : SD card M22
VDDIO_DDR_04
VDDIO_DDR_05
DDR_DQ03
DDR_DQ04 A29
DDR_A_D3
DDR_A_D4
<9>
<9>
M24 VDDIO_DDR_06 DDR_DQ05 C25 DDR_A_D5 <9>
U1P N15 D24
+VDD_3V3_SDMMC1_TEGRA VDDIO_DDR_07 DDR_DQ06 DDR_A_D6 <9>
N17 VDDIO_DDR_08 DDR_DQ07 F24 DDR_A_D7 <9>
17/21 SDMMC1 N19 VDDIO_DDR_09 DDR_DQ08 F14 DDR_A_D8 <9>
(1.8/2.8~3.3V) N21 VDDIO_DDR_10 DDR_DQ09 C15 DDR_A_D9 <9>
PU
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
R1 VDDIO_SDMMC1 SDMMC1_DAT0 U7 SDMMC_DAT0 <20> N23 VDDIO_DDR_11 DDR_DQ10 D14 DDR_A_D10 <9>
W11 PU 1 1 1 1 P26 H14
SDMMC1_DAT1 PU SDMMC_DAT1 <20> VDDIO_DDR_12 DDR_DQ11 DDR_A_D11 <9>
C14
C22
C15
C16
C17 1 U1 R25 C13
SDMMC1_DAT2 PU SDMMC_DAT2 <20> VDDIO_DDR_13 DDR_DQ12 DDR_A_D12 <9>
4.7U_0402_6.3V6M
SDMMC1_DAT3 Y10 SDMMC_DAT3 <20> T26 VDDIO_DDR_14 DDR_DQ13 C11 DDR_A_D13 <9>
DDR_DQ14 D12 DDR_A_D14 <9>
PU 2 2 2 2
SDMMC1_CLK T6 SDMMC_CLK <20> DDR_DQ15 A9 DDR_A_D15 <9>
2 PU
SDMMC1_CMD T8 SDMMC_CMD <20> DDR_DQ16 D30 DDR_A_D16 <9>
DDR_DQ17 K24 DDR_A_D17 <9>
DDR_DQ18 G27 DDR_A_D18 <9>
DDR_DQ19 H24 DDR_A_D19 <9>
DDR_DQ20 E27 DDR_A_D20 <9>
+VDD_3V3_SDMMC1_TEGRA DDR_DQ21 G29 DDR_A_D21 <9>
+VDD_3V3_DDR_RX_TEGRA H28
DDR_DQ22 DDR_A_D22 <9>
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
(2.8/3.3V) DDR_DQ23 J25 DDR_A_D23 <9>
AF10 SDMMC1_COMP_PU R29 1 2 33.2_0402_1% 1 1 1 1 A15 K14
SDMMC1_COMP_PU VDD_DDR_RX DDR_DQ24 DDR_A_D24 <9>
C18
C19
C20
C21
DDR_DQ25 F10 DDR_A_D25 <9>
SDMMC1_COMP_PD R30 2 33.2_0402_1%
4.7U_0402_6.3V6M
SDMMC1_COMP_PD U9 1 DDR_DQ26 L15 DDR_A_D26 <9>
1 DDR_DQ27 J15 DDR_A_D27 <9>
2 2 2 2
DDR_DQ28 H12 DDR_A_D28 <9>
C23
DDR_DQ29 G11 DDR_A_D29 <9>
DDR_DQ30 C9 DDR_A_D30 <9>
Z 2
GPIO_PV2 Y6 DDR_DQ31 E9 DDR_A_D31 <9>
W9 Z
GPIO_PV3
U3 PD F26
CLK2_OUT Z CP_GPIO <27> DDR_DM0 DDR_A_DM0 <9>
CLK2_REQ U5 DDR_DM1 E13 DDR_A_DM1 <9>
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
C
DDR_DM2 C29 DDR_A_DM2 <9> C
1 1 1 1 (1.05V) DDR_DM3 J13 DDR_A_DM3 <9>
C30
C108
C109
C110
+VDD_1V0_DDR_HS_TEGRA K12 VDD_DDR_HS_1
T30S-R-A3-1.4G_FCCSP681 L23 VDD_DDR_HS_2
9/22 2 2 2 2 DDR_DQS0N B26 DDR_A_DQS#0 <9>
Add U1.U3 GPIO to control Power CP function. DDR_DQS0P A27 DDR_A_DQS0 <9>
4.7U_0402_6.3V6M
1 DDR_DQS1N A11 DDR_A_DQS#1 <9>
DDR_DQS1P B12 DDR_A_DQS1 <9>
C24
DDR_DQS2N K26 DDR_A_DQS#2 <9>
2
DDR_DQS2P H26 DDR_A_DQS2 <9>
E11
SDMMC3 : WIFI 2 2
DDR_DQS3N
F12
DDR_A_DQS#3 <9>
33P 50V J NPO 0201
33P 50V J NPO 0201

DDR_DQS3P DDR_A_DQS3 <9>
C205
C215
U1O J23
+VDD_1V8_SDMMC3_TEGRA DDR_A00 DDR_A_MA0 <9>
DDR_A01 C23 DDR_A_MA1 <9>
1 1
DDR_A02 E21 DDR_A_MA2 <9>
6/21 SDMMC3
DDR_A03 A23 DDR_A_MA3 <9>
DDR_A04 E23 DDR_A_MA4 <9>
M36 N33 PU B18
VDDIO_SDMMC3 SDMMC3_DAT0 PU WFMMC_DAT0 <22> DDR_A05 DDR_A_MA5 <9>
L37 A17 DDR_A_MA6 <9>
(1.8/2.8~3.3V) SDMMC3_DAT1 PU WFMMC_DAT1 <22> DDR_A06
0.1U_0201_10V6K
SDMMC3_DAT2 M34 WFMMC_DAT2 <22> DDR_A07 F18 DDR_A_MA7 <9>

1 C26 1 P34 PU B14
SDMMC3_DAT3 PU WFMMC_DAT3 <22> DDR_A08 DDR_A_MA8 <9>
C25
4.7U_0402_6.3V6M
SDMMC3_DAT4 J37 @ PAD T17 DDR_A09 C17 DDR_A_MA9 <9>

N29 PU F16
SDMMC3_DAT5 PU DDR_A10
SDMMC3_DAT6 M32 DDR_A11 G17
2 2 PU
SDMMC3_DAT7 M28 9/26 Modify BOARD_ID3 from U1.J37 to U1.R37 DDR_A12 J17
DDR_A13 H18
DDR_A14 J19
SDMMC3_CLK J35 PU WFMMC_CLK <22>
SDMMC3_CMD M30 PU WFMMC_CMD <22> DDR_RAS* J21
+VDD_1V8_SDMMC3_TEGRA DDR_CAS* H20
<BOM Structure>
<BOM Structure> L35 SDMMC3_COMP_PU R31 1 2 33.2_0402_1% H22
SDMMC3_COMP_PU DDR_WE*
N35 SDMMC3_COMP_PD R32 1 2 33.2_0402_1%
B SDMMC3_COMP_PD B
DDR_BA0 F20
DDR_BA1 G21
DDR_BA2 F22
DDR_CS0* C21 M_CS#0 <9>
DDR_CS1* D20 M_CS#1 <9>
<BOM Structure>
DDR_ODT0 G23
DDR_ODT1 L19
DDR_CKE0 B20 M_CKE0 <9>

U1M E19
DDR_CKE1 M_CKE1 <9>
15/21 HSIC
DDR_CLK* D18 M_CLK_DDR#0 <9>
C19 M_CLK_DDR0 <9>
Y2
(1.2V) AC5
DDR_CLK
VDDIO_HSIC HSIC_DATA
HSIC_STROBE AD6
K20 DDR_RESET
DDR_RESET @ PAD T3
AD10 C27 QUSE0 R33 1 2 0_0201_5%
HSIC_REXT DDR_QUSE0 QUSE1
DDR_QUSE1 D26
G15 QUSE2 R34 1 2 0_0201_5%
DDR_QUSE2 QUSE3
DDR_QUSE3 H16
VDD_1V2_MEM
DDR_COMP_PU E17 DDR_COMP_PU R35 1 2 49.9_0402_1%
U1N
DDR_COMP_PD E15 DDR_COMP_PD R36 1 2 49.9_0402_1%
16/21 IC_USB
AB8 AVDD_IC_USB IC_USB_DN AD4
AE3 T30S-R-A3-1.4G_FCCSP681
(1.8/3.0V) IC_USB_DP
A A
IC_USB_REXT AD8

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
A B C D E
U1L
11/21 USB
U1Q is not place on grid , need check connection +AVDD_3V3_USB_TEGRA
USB1_VBUS AF8 +T30S_USB1

(3.3V)
AB6 AVDD_USB
USB1_DN AL5 USB1_DN <20>
USB1_DP AM4 USB1_DP <20>
1 1 1
4.7U_0402_6.3V6M
C27
+VDD_1V8_AUDIO_TEGRA USB1_ID AU5 USB1_ID <20>
U1Q 2
RF note
13/21 AUDIO
(1.8/3.3V)
G33 E35 AUDIO_CLK R37 1 2 0_0201_5%
VDDIO_AUDIO CLK1_OUT AUDIO_CLK_R <15>
0.1U_0201_10V6K
1
PD
C28
DAP1_SCLK L29 AUDIO_SEL <14>

B34 PD
DAP1_FS PD AUDIO_RST# <14> +AVDD_1V8_USB_PLL_TEGRA
DAP1_DOUT D32 ES305_INT_R <14>
2 PD
DAP1_DIN A33 ENABLE_USB_HOST <20,27>
(1.8V)
8/24 Modify Off-Page type. V2 AVDD_USB_PLL
PD
0.1U_0201_10V6K
DAP2_SCLK H34 AUDIO_SCLK2 <14>
K30 PD 1
DAP2_FS PD AUDIO_FS2 <14>
C29
DAP2_DOUT F34 AUDIO_DOUT2 <14> USB2_VBUS AH6
C33 PD
DAP2_DIN AUDIO_DIN2 <14>
2
USB2_DN AG3 3G_USB_DN <18>
USB2_DP AG1 3G_USB_DP <18>
SPDIF_IN L31 PU
SPDIF_OUT J31 PU 10/24 Add BATT_LEARN GPIO to Power request.
USB2_ID AJ7
10/03 Add D18 on +T30S_USB1 to protect CPU.
SPI1_SCK G35 PU 10/19 Modify D18 from +T30S_USB1 to VBUS_USB
H36 PU
SPI1_CS0* PU BATT_LEARN <27> 12/2 Modify D18 from moun to @,Add Zener on samll board.
SPI1_MOSI L33
F36 PD
SPI1_MISO COMPASS_DRDY <20>
SC400003Z00
2 2
VBUS_USB
PU +T30S_USB1 Q18
SPI2_SCK K32
J33 PU AO3413_SOT23-3
SPI2_CS0* PU LIGHT_INT <20>
SPI2_CS1* B32 HP_DET# <20>
PU
S
SPI2_CS2* F30 CDC_IRQ# <15> 1 3
D36 PD 10MIL
1
SPI2_MOSI EN_ES305_OSC <14>
1
E37 PD 0.1A 3.3V
SPI2_MISO GYRO_INT_R <16> D18 @ AR5
G
+T30S_USB1
2
R42 USB3_VBUS
1M_0201_1% BZT52-B5V6S_SOD323-2
AF4
2
2
USB3_DN USB_HOST_DN <20>
EN_T30S_USB1 USB3_DP AE5 USB_HOST_DP <20>
T30S-R-A3-1.4G_FCCSP681 +AVDD_3V3_USB_TEGRA
D USB3_ID AK12
1
2 Q5
R39
S
3
AE9 USB_REXT 2 1
USB_REXT
1K_0201_1%
+AVDD_1V2_DSI_CSI_TEGRA U1H
USB VBUS overvoltage protection
7/21 DSI/CSI
(1.2V)
AF2 AVDD_DSI_CSI CSI_CLKAN AP2 5M_CAM_CLK#_R <17>
AN3 +VDD_1V8_CAM_TEGRA
CSI_CLKAP 5M_CAM_CLK_R <17>
CAM_I2C_SCL CAM_I2C_SDA
0.1U_0201_10V6K
CSI_D1AN AJ5 5M_CAM_DA1#_R <17>

1 1 CSI_D1AP AJ3 5M_CAM_DA1_R <17> 1 1
C32
C186 C187
4.7U_0402_6.3V6M
C31
CSI_D2AN AL9 5M_CAM_DA2#_R <17>
1
3 3
39P_0201_50V8J
39P_0201_50V8J
CSI_D2AP AK10 5M_CAM_DA2_R <17>
2 2 R40 R41 2 2
U1G 2.2K_0201_1% 2.2K_0201_1%
+VDD_1V8_CAM_TEGRA
18/21 CAM
2
(1.8/2.8 ~ 3.3V) Z
AL11 VDDIO_CAM CAM_I2C_SCL AK14
AN15 Z CAM_I2C_SCL <17,26,35> RF note
CAM_I2C_SDA CAM_I2C_SDA <17,26,35>
Z R72 2 0_0201_5%
0.1U_0201_10V6K
CSI_CLKBN AR7 2M_CAM_CLK#_R <17> CAM_MCLK AG15 1 CAM_MCLK <17>
CSI_CLKBP AN7 2M_CAM_CLK_R <17> 1 1 1
C35
C372
4.7U_0402_6.3V6M
Z
C34
CSI_D1BN AK4 2M_CAM_DA1#_R <17> GPIO_PBB0 AM10 2M_CAM_RST# <17>

Z
10P_0201_50V8J
CSI_D1BP AL3 2M_CAM_DA1_R <17> GPIO_PBB3 AM14 5M_CAM_PWDN <17>
2 2 Z 2
GPIO_PBB4 AL15 5M_CAM_RST# <17>
AT6 AJ15 Z
CSI_D2BN 2M_CAM_DA2#_R <17> GPIO_PBB5 Z 2M_CAM_PWDN <17>
CSI_D2BP AP6 2M_CAM_DA2_R <17> GPIO_PBB6 AM16 DOCK_DET# <20>
AT14 Z
GPIO_PBB7
AU15 PU
GPIO_PCC1 PU
GPIO_PCC2 AR15 9/26 Swap U1.AM16 to U1.AM10 for WAKE UP issue
DSI_CLKAN AJ1
DSI_CLKAP AK2
+AVDD_1V2_DSI_CSI_TEGRA
DSI_D1AN AN1
DSI_D1AP AM2
1
DSI_D2AN AH8
AG9 R44
DSI_D2AP 453_0402_1%
4 4
2
AG7 DSI_CSI_RUP
DSI_CSI_RUP
AT4 DSI_CSI_RDN
DSI_CSI_RDN
1
T30S-R-A3-1.4G_FCCSP681 R45
49.9_0402_1%
2
4019FQ
C B
SCHEMATIC MB A8022
A B C D E
A B C D E
8/25 Modify C36&C37 from 12P to 8P.

+VDD_1V8_SENSOR BT_RST# GPS_RESET# 10/11 Modify C36&C37 from 8P to 10P.
+VDD_1V8_SYS_TEGRA C36
Y1
1
1 2 T30S_XTAL_IN 1 2
<32> PMU_OSC32KIN PMU_OSC32KOUT <32>
R56 R75
1
+VDD_1V8_UART_TEGRA 10P_0201_50V8J
R46 R47 100K_0201_5% 100K_0201_5% 32.768KHZ_12.5P_1TJF125DP1A000D
2
U1R
1
2.2K_0201_1% 2.2K_0201_1% R50 Y10
G
Open Drain R48 R49 26MHZ_10PF_7M26000039
4 G
2
2
14/21 UART
For PMU RTCCLK , Load BOM HW. 10K_0201_5% 100K_0201_5% 2M_0201_5%
3
(1.8/3.3V)
2
AC37 AH30 Z
GEN1_I2C_SCL <16,20> C37
2
VDDIO_UART GEN1_I2C_SCL Z CORE_PWR_REQ
GEN1_I2C_SDA AE29 GEN1_I2C_SDA <16,20> T30S_XTAL_OUT
0.1U_0201_10V6K
1
1 2 1
1 AN35 PU CPU_PWR_REQ
UART2_TXD PU GPS_UART_TXD <21>
C38
UART2_RXD AG29 GPS_UART_RXD <21> 10P_0201_50V8J

UART2_RTS* AG31 PU
PU GPS_UART_RTS# <21> 12/29 Modify R48 from 100K to 10K to meet Voltage level.
2 UART2_CTS* AJ31 GPS_UART_CTS# <21> 9/22
PU U1C
UART3_TXD AE33
AJ35 PU BT_UART_TXD <22> Change EN_3V3_MODEM from AE35 to AF36.
UART3_RXD PU BT_UART_RXD <22> VDD_1V8_GEN
UART3_RTS* AK36
AJ37 PU BT_UART_RTS# <22> 9/26 2/21 OSC, PLL & SYS
UART3_CTS* BT_UART_CTS# <22> L3
Change BT_PD# from Y36 to AJ33 09/15 Add for Acer request.
AK34 Z 1 2 AVDD_OSC P36 R33 T30S_XTAL_IN
GPIO_PU0 Z BT_RST# <22> AVDD_OSC XTAL_IN
AF36 MPZ1005S300CT_2P
GPIO_PU1 Z EN_3V3_MODEM <18,30> +VDD_1V8_SYS_TEGRA
GPIO_PU2 AN37 GPS_PWRON <21> (1.8V)
AG33 Z 1
GPIO_PU3 Z GPS_RESET# <18,21>
U1T
4.7U_0402_6.3V6M
GPIO_PU4 AM36
Z DEBUG_UART1_RX_R
C39
GPIO_PU5 AG37 1 R149 2 DEBUG_UART1_RX <20> 19/21 PEX Deep Sleep : OFF
AJ33 Z 0_0201_5% R35 T30S_XTAL_OUT
GPIO_PU6 BT_PD# <22> XTAL_OUT
1
2
R91
AF34 PD (1.05V)
DAP4_DIN PD BT_PCM_IN <22>
AG35 AN29 AT30 100K_0201_5%
DAP4_DOUT PD BT_PCM_OUT <22> AVDD_PEXB PEX_L5_TXN
AF28 BT_PCM_SYNC <22> AU29
2
DAP4_FS PD PEX_L5_TXP
DAP4_SCLK AL35 BT_PCM_CLK <22> +AVDD_1V1_PLL_TEGRA LINE_OUT_DET#
(1.05V)
AM30 VDD_PEXB
0 PLL_S_PLL_LF
CLK3_OUT AH32
Z CLK_12M_ES305 <14> B24 AVDD_PLLA_P_C_S(1.1V) PLL_S_PLL_LF R27
CLK3_REQ AF32 (1.05V)
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
AN31 AVDD_PEX_PLL PEX_L5_RXN AP30
PEX_L5_RXP AR29 1 1 K18 AVDD_PLLX (1.1V) 1
C41
C42
C40
2 2
A21 AVDD_PLLM (1.1V) 2
T30S-R-A3-1.4G_FCCSP681 +VDD_1V8_BB_TEGRA 10/19 Modify R51 and R52 to 1K ohm @
AG5 (1.1V) +VDD_1V8_SYS_TEGRA

AVDD_PLLU_D
1
2 2
R77
1
100K_0201_5% AF30 (1.05V)
AVDD_PLLE
AT34
2
PEX_CLK3N
2
AR33 R51 R52
PEX_CLK3P R53 1K_0201_1% 1K_0201_1%
+VDD_1V8_BB_TEGRA
EN_SENSOR_1V8#
2
0_0201_5%
U1S V36 Z
1
PWR_I2C_SCL PWR_I2C_SCL <10,14,15,26,32,34>
(3.3V) PWR_I2C_SDA V30 Z PWR_I2C_SDA <10,14,15,26,32,34>
12/21 BB AL29 HVDD_PEX
AR31 Z U31
PEX_L2_CLKREQ* SYS_RESET* PMU_RESET_OUT_1V8# <32>
V6 VDDIO_BB ULPI_DATA0 AA7 PU DEBUG_UART1_TX <20> PEX_L2_PRSNT* AT32 Z
(1.8/3.3V) ULPI_DATA1 AC7 PU DEBUG_UART1_RX <20> PEX_L2_RST* AU33 Z +VDD_1V8_SYS_TEGRA
V8 PU
0.1U_0201_10V6K
ULPI_DATA2
1 ULPI_DATA3 AC3 PU WAKE_UP_ACIN <27> (1.8V) PWR_INT* P28 PMU_INT# <32>
V4 PU Z
C43
ULPI_DATA4 SIM_DET <18> PEX_WAKE* AP32 Y32 VDDIO_SYS

ULPI_DATA5 AC11PU CORE_PWR_REQ T32 CORE_PWR_REQ <27,32>
ULPI_DATA6 AF6 PU CPU_PWR_REQ Y34 CPU_PWR_REQ <32>
2
AA9 PU
0.1U_0201_10V6K
ULPI_DATA7
(3.3V) 1 Deep Sleep : ON SYS_CLK_REQ W27 Z SYS_CLK_REQ
@ PAD T2
C44
ULPI_CLK AC1 AUDIO_UART4_TX <14> AK28 VDDIO_PEX_CTL
ULPI_DIR W3 Z AUDIO_UART4_RX <14> CLK_32K_IN T30 PMU_CLK_32K <32>
ULPI_NXT AC9 Z EN_VDD_GPS <21> PEX_TERMP AP36 CLK_32K_OUT AB32 0 CLK_32K_OUT <22>
2
ULPI_STP V10 Z EN_SENSOR_1V8# <23>
KB_COL00 U37 PU SC_LOCK# <20>

KB_COL01 U29 PU VOL_UP# <4,20>
KB_COL02 AD32PU VOL_DOWN# <4,20>
AA1 PD AD36PU +VDD_1V8_SYS_TEGRA
DAP3_DIN PD CAM_LED_EN_NV <35> KB_COL03 EN_CAM_2V8 <17>
DAP3_DOUT W5 WF_RST# <22>
U1U T30S-R-A3-1.4G_FCCSP681
KB_COL04 AC31PU BOARD_ID_WP <10>
2
PD Y30 PU
10K_0201_5%
DAP3_FS Y4 BT_WAKEUP <22> KB_COL05
PD AD30PU
PICASSO_M@
DAP3_SCLK AA3 EN_SENSOR_3V3_2 <23> 20/21 SPARE
KB_COL06
W35 PU 9/22 Swap AD36 & W29 GPIO function.
R195
KB_COL07
9/27 SPARE_1 AC27 Default pull up& pull down swap
AD28
1
SPARE_2
3 GPIO_PV0 Y8 Z ON_KEY# ADD EN_SENSOR_3V3_2 to U1.AA3 SPARE_3 AG19 KB_ROW00 AC33 PD WAKEUP_LED <27> 3
GPIO_PV1 AA5 Z WAKE_UP_VBUS <27> SPARE_4 AL33 KB_ROW01 R37 PD PCB_ID3
AM34 W29 PD
SPARE_5 KB_ROW02 PD EN_CAM_1V8# <23>
KB_ROW03 R31
2
we not
PD use Audio LDO
10K_0201_5%
KB_ROW04 U35
PD
PICASSO_2@
KB_ROW05 V34 UART_SW <20>
PD 9/22 Change EN_3V3_MODEM to AF36
R163
KB_ROW06 U33
+VDD_1V8_BB_TEGRA
KB_ROW07 AE35 PD @ PAD T10
AA35 PD SHORT_DET <15>
1
KB_ROW08
+VDD_1V8_SYS_TEGRA
KB_ROW09 AA37 PD08/12 Delete EN_ACER_USB_CHARGE
KB_ROW10 AA29 PD WF_WAKE# <22>
1
@ PAD T14 9/26 Change BT_PD# to AJ33

T30S-R-A3-1.4G_FCCSP681 JDBUG1 Y36 PD
R164 KB_ROW11 PD
1 1 KB_ROW12 P30 SD_DET# <20>
100K_0201_5% JTAG_TRST# 2 2 KB_ROW13 AC29 PD G_ACC_INT <16>
JTAG_TDI 3 P32 PD
3 KB_ROW14 LINE_OUT_DET# <20>
JTAG_TMS 4 AB30 PD BT_IRQ# <22>
2
D20 JTAG_TCK 4 KB_ROW15

5 5
RB751V-40_SOD323-2 JTAG_RTCK 6
ON_KEY# T30S-R-A3-1.4G_FCCSP681 JTAG_TDO 6
2 1 ONKEY# <20> 7 7
8 AA31 JTAG_TCK
<20> HOT_RST# 8 JTAG_TCK @ PAD T4
ONKEY# 9 AC35 JTAG_TDI
9 JTAG_TDI @ PAD T5
10 Y28 JTAG_TDO
10 JTAG_TDO @ PAD T6
11 AA33 JTAG_TMS
GND JTAG_TMS @ PAD T7
12 W33 JTAG_TRST#
GND JTAG_TRST* @ PAD T8
AD34 JTAG_RTCK
JTAG_RTCK @ PAD T9
ACES_87036-1001-CP
R57 CONN@
+3VS_TH NV_THERM_DN
0.1U_0201_10V6K
+3VS 1 2 THERM_DN E31

1 C31 NV_THERM_DP
VDD_1V8_PMU_VRTC THERM_DP
C45
49.9_0402_1%
+VDD_1V8_SYS_TEGRA R29
OWR
max current is 350uA 2
V32 Z
+3VS JTAG_TDI R155 HDMI_CEC HDMI_CEC <19>
VR1 =17mV 1 2
10K_0201_5% V28 TEST_MODE_EN
JTAG_TMS R159 TEST_MODE_EN
1 2
1
10K_0201_5% 9/26 Change from J37 to R37.

1
2
0_0201_5%
R59 100_0201_1% R58 JTAG_RTCK R160 1 2
R62
4 NV_THERM_DP 2 1 THERMD_F_P R60 10K_0201_5% 4
U4 100K_0201_5% JTAG_TCK R161 2 1 100K_0201_5% PICASSO_M PICASSO_2
1
C46 2 1 100K_0201_5% T30S-R-A3-1.4G_FCCSP681

2
1000P_0201_16V7K D+ VDD JTAG_TRST# R162 2 @

3 1 100K_0201_5%
2
1
R61 100_0201_1% D-
4 AP_OVERHEAT# <32> PCB_ID3 H L
2
NV_THERM_DN THERMD_F_N THERM#

2 1 ALERT# 6 TEMP_ALERT# <4>
PWR_I2C_SCL 8
<10,14,15,26,32,34> PWR_I2C_SCL PWR_I2C_SDA SCL
<10,14,15,26,32,34> PWR_I2C_SDA 7 SDA GND 5
9/28 Change Net name from Board_ID3 to PCB_ID3
NCT1008CMT3R2G_WDFN8_2X2
Compal Secret Data Compal Electronics, Inc.
Thermal Security Classification
4019FQ
C B
SCHEMATIC MB A8022
A B C D E
5 4 3 2 1
U1B
U1A +VDD_1V2_RTC_TEGRA 21/21 GND
1/21 CORE POWER

(1.0 ~ 1.2V) AU7 GND_100 GND_1 A13
VDD_RTC_1 AH26 B10 GND_101 GND_2 A19
VDD_RTC_2 AJ25 B16 GND_102 GND_3 A25
0.1U_0201_10V6K
B2 GND_103 GND_4 A3
1 B22 GND_104 GND_5 A31
C47
B28 GND_105 GND_6 A35
B36 GND_106 GND_7 A7
C1 GND_107 GND_8 AA11
2
D
C3 GND_108 GND_9 AA13 D
VDD_1V0_GEN C35 AA15
GND_109 GND_10
Acer request 07/04 C37 GND_110 GND_11 AA17
D10 GND_111 GND_12 AA19
D16 GND_112 GND_13 AA21
D22 GND_113 GND_14 AA23
D28 GND_114 GND_15 AA25
(0.9 ~ 1.0V) D34 GND_115 GND_16 AA27
VDD_CPU_01 AB12 D4 GND_116 GND_17 AB10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
VDD_CPU_02 AB14 E33 GND_117 GND_18 AB2
VDD_CPU_03 AB16 1 1 1 1 1 1 1 1 1 E5 GND_118 GND_19 AB28
C88
C101
C102
C103
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VDD_CPU_04 AB18 F32 GND_119 GND_20 AB34
C49
C50
C51
C52
C48
VDD_CPU_05 AB20 F6 GND_120 GND_21 AB36
VDD_CPU_06 AD12 G1 GND_121 GND_22 AB4
2 2 2 2 2 2 2 2 2
VDD_CPU_07 AD14 G13 GND_122 GND_23 AC13
VDD_CPU_10 AF14 G31 GND_125 GND_26 AC19
VDD_CPU_11 AF16 G37 GND_126 GND_27 AC21
VDD_CPU_12 T20 G7 GND_127 GND_28 AC23
VDD_CPU_13 V18 H30 GND_128 GND_29 AC25
VDD_CPU_14 V20 H32 GND_129 GND_30 AE1
0.1U_0201_10V6K
0.1U_0201_10V6K
VDD_CPU_15 Y18 H6 GND_130 GND_31 AE11
VDD_CPU_16 Y20 1 1 1 1 1 1 H8 GND_131 GND_32 AE13
C53
C54
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
J11 GND_132 GND_33 AE15
C55
C56
C57
C58
J27 GND_133 GND_34 AE17
(1.0 ~ 1.2V) 2 2 2 2 2 2
J29 GND_134 GND_35 AE19
VDD_CORE_01 AB22 J9 GND_135 GND_36 AE21
VDD_CORE_02 AB24 K10 GND_136 GND_37 AE23
VDD_CORE_03 AB26 K16 GND_137 GND_38 AE25
VDD_CORE_04 AD20 K2 GND_138 GND_39 AE27
VDD_CORE_07 AD26
VDD_1V2_SOC
Acer request 07/04 K34 GND_141 GND_42 AE7
VDD_CORE_08 AF18 K36 GND_142 GND_43 AF12
VDD_CORE_09 AF20 K4 GND_143 GND_44 AF26
VDD_CORE_10 AF22 L11 GND_144 GND_45 AG11
VDD_CORE_11 AF24 L13 GND_145 GND_46 AG13
C
VDD_CORE_12 P14 L17 GND_146 GND_47 AG17 C
0.1U_0201_10V6K
VDD_CORE_13 P16 L21 GND_147 GND_48 AG21
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
VDD_CORE_14 P18 1 1 1 1 1 1 L25 GND_148 GND_49 AG25
C64
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VDD_CORE_15 P20 C59 1 1 1 1 L27 GND_149 GND_50 AG27
C60
C61
C62
C63
C104
C105
C106
C107
VDD_CORE_16 P22 M12 GND_150 GND_51 AH10
VDD_CORE_17 T14 M26 GND_151 GND_52 AH16
2 2 2 2 2 2
VDD_CORE_18 T16 N1 GND_152 GND_53 AH2
2 2 2 2
VDD_CORE_22 V12 N27 GND_156 GND_57 AH36
VDD_CORE_23 V14 N31 GND_157 GND_58 AH4
VDD_CORE_24 V16 N37 GND_158 GND_59 AJ11
VDD_CORE_25 V22 N7 GND_159 GND_60 AJ27
VDD_CORE_26 V24 P24 GND_160 GND_61 AJ29
VDD_CORE_27 V26 R13 GND_161 GND_62 AJ9
VDD_CORE_28 W25 R15 GND_162 GND_63 AK30
VDD_CORE_29 Y12 R17 GND_163 GND_64 AK32
VDD_CORE_32 Y22 R23 GND_166 GND_67 AL1
VDD_CORE_33 Y24 T10 GND_167 GND_68 AL13
VDD_CORE_34 Y26 T2 GND_168 GND_69 AL19
T28 GND_169 GND_70 AL25
T34 GND_170 GND_71 AL31
T36 GND_171 GND_72 AL37
T4 GND_172 GND_73 AL7
+VDD_3V3_FUSE_TEGRA U11 AM32
GND_173 GND_74
U13 GND_174 GND_75 AM6
U15 GND_175 GND_76 AN33
U17 GND_176 GND_77 AN5
(3.3V) VPP_FUSE AU17 U19 GND_177 GND_78 AP10
AU9 VPP_KFUSE U21 AP16
(3.3V) VPP_KFUSE GND_178 GND_79
U23 GND_179 GND_80 AP22
0.1U_0201_10V6K
U25 GND_180 GND_81 AP28

1
2
1 U27 GND_181 GND_82 AP34

C65
R64 R65 W1 AP4

10K_0201_5% GND_182 GND_83
B
W13 GND_183 GND_84 AR1 B
10K_0201_5% W15 AR3
2 GND_184 GND_85
T30S-R-A3-1.4G_FCCSP681 12/12 Modify R65 from @ to mount. W17 AR35
2
GND_185 GND_86
1
W19 GND_186 GND_87 AR37

W21 GND_187 GND_88 AT10
W23 GND_188 GND_89 AT16
W31 GND_189 GND_90 AT2
W37 GND_190 GND_91 AT22
W7 GND_191 GND_92 AT28
GND_93 AT36
GND_94 AU13
GND_95 AU19
GND_96 AU25
GND_97 AU3
GND_98 AU31
GND_99 AU35
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
Follow NV design +VDD_1V2_DDR_MEM

NET NAME BALL NAME +VDD_1V8_DDR_MEM +VDD_1V8_DDR_MEM
A0 P3
1
A1 N3
R66
A2 M3 +VDD_1V2_DDR_MEM +VDD_1V2_DDR_MEM 100K_0201_5%
A3 M2 U7
+VRAM_VREDQ
A4 M1
2
A1 J8
A5 G2 A2
NU VSS
J9
NU VREFDQ
A6 F2
0.1U_0201_10V6K
A9 NU CKE0 K1 M_CKE0 <5>
1
D A7 F3 A10 NU CKE1 K2 M_CKE1 <5> 1 D
C66
B1 K3 R67
A8 E3 B2
NU NC
K5 DDR_A_DM0 <5> 100K_0201_5%
NC DM0
A9 E2 B3 NC VDDQ K6
2
F1,H1,N2 are the NC pins which assembled/embedded
CKE0 K1 B5 L1 M_CS#0 <5> the interconnection into ELP Vdd sources already.
2
VDD2 /CS0
B6 L2 M_CS#1 <5>
CKE1 K2 <5> DDR_A_D29 B7
VDD1 /CS1
L3 due to co-layout the LPDDR2,
DQ31 NC
CLK J3 <5> DDR_A_D25 B8 DQ29 /DQS0 L5 DDR_A_DQS#0 <5> it is need to apply 1.2 volt on F1, H1 and N2 pins.
B9 L6
CLK# H3 <5> DDR_A_D31
B10
DQ26 DQS0
L7
DDR_A_DQS0 <5>
NU DQ5 DDR_A_D5 <5>
CS0 L1 C1 VDD1 DQ6 L8 DDR_A_D6 <5>
CS1 L2 1 R70 2
C2
C3
VSS DQ7 L9
L10
DDR_A_D4 <5>
DM0 K5 240_0402_1% C5
ZQ1 VSS
M1
Vss CA4 DDR_A_MA4 <5>
DM1 H5 C6 VSS CA3 M2 DDR_A_MA3 <5>
C7 M3
DQ0 M9 C8
VDDQ CA2
M5
DDR_A_MA2 <5>
<5> DDR_A_D30
DQ1 N8 C9
DQ25
VSS
VSS
DQ4 M6 DDR_A_D7 <5>
DQ10 F7 C10 VDDQ DQ2 M7 DDR_A_D3 <5>
D1
DQ11 F9 D2
VSS
VDD2
DQ12 F6 1 R71 2 D3 ZQ0
240_0402_1%
DQ13 G9 D5 VDDQ DQ1 M8 DDR_A_D2 <5>
D6 M9
DQ14 F8 <5> DDR_A_D24
<5> DDR_A_D28 D7
DQ30 DQ3
M10
DDR_A_D0 <5>
DQ27 VDDQ
DQ15 E8 <5> DDR_A_DQS3 D8 DQS3 VSS N1
D9 N2
DQ2 M8 <5> DDR_A_DQS#3
D10
/DQS3 NC
N3
DQ3 M7 VSS CA1
DQ19 N5
DDR_A_MA1 <5>
DDR_A_D19 <5>
DQ4 L9 DQ23 N6 DDR_A_D17 <5>
DQ5 L7 E1 VSS
DQ6 L8 <5> DDR_A_MA9 E2 CA9
DQ7 M6 <5> DDR_A_MA8 E3 CA8
N7
DQ8 G7 DM2
N8
DDR_A_DM2
DDR_A_D1
<5>
<5>
DQ0
DQ9 G8 <5> DDR_A_D26 E5 DQ28 VDDQ N9
E6 N10
C
DQS0 L6 <5> DDR_A_D27
E7
DQ24 VSS
P1 C
<5> DDR_A_DM3
DQS0# L5 <5> DDR_A_D15 E8
DM3
DQ15
VSS
VDD2 P2
DQS1 G6 E9 VDDQ CA0 P3 DDR_A_MA0 <5>
E10 P5
DQS1# G5 F1
VSS VDDQ
P6 Acer request
NC DQ17 DDR_A_D23 <5>
<5> DDR_A_MA6 F2 CA6 DQ20 P7 DDR_A_D18 <5>
Layer 2)) <5> DDR_A_MA7 F3 CA7 DQS2 P8 DDR_A_DQS2 <5>
F5 P9
)) <5> DDR_A_D12 F6
VSS /DQS2
P10
DDR_A_DQS#2 <5> +VDD_1V2_DDR_MEM
DQ11 VSS
DM2 N7 <5> DDR_A_D10 F7 DQ13 VDD1 R1
R2
DM3 E7 VSS
R3 +VDD_1V8_DDR_MEM
DQ16 T8 NC
VSS R5
DQ17 N6 0.1U_0201_10V6K
0.01U_0201_16V7
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VSS R6
F8 R7 C69 1 1 1 1 1 1 1 1
DQ18 P7 +VDD_1V2_DDR_MEM <5> DDR_A_D14 DQ14 VDDQ
R8
DQ22 DDR_A_D22 <5>
DQ19 N5
C73
C74
C75
C76
F9 C70 C71 C72
<5> DDR_A_D11 DQ12 0.1U_0201_10V6K
DQ20 T7 VSS R9
1
2 2 2 2 2 2 2 2
F10 R10
DQ21 T9 R68 VDDQ VDDQ
T1 1U_0402_6.3V4Z
NU
DQ22 R8 100K_0201_5%
+VRAM_VREFA
G1 VDD2 NC T2
T3
DQ23 P6 G2
NC
T5
2
DQ24 D6 <5> DDR_A_MA5 CA5 VDD2

VDD1 T6
DQ25 B8 G3 VREFCA DQ16 T7 DDR_A_D20 <5>
G5
DQ26 E5 <5> DDR_A_DQS#1 /DQS1
1
1
DQ27 E6 R69
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
C68
DQ28 D7 100K_0201_5% DQ18 T8 DDR_A_D16 <5> +VDD_1V8_DDR_MEM
1 1 1 1
C81
C82
C83
C84
0.1U_0201_10V6K T9
DQ29 B7 2
G6
DQ21 DDR_A_D21 <5>
2
<5> DDR_A_DQS1 DQS1

DQ30 C8 0.1U_0201_10V6K
0.01U_0201_16V7
<5> DDR_A_D8 G7 DQ10 C77 1 2 2 2 2
DQ31 B9 <5> DDR_A_D9 G8
G9
DQ9 1 1 1
<5> DDR_A_D13
DQS2 P8 DQ8
NU T10 C78 C79 C80
DQS2# P9 G10 VSS NU U1
2 2 2 2
0.1U_0201_10V6K
H1
DQS3 D8 H2
NC 1U_0402_6.3V4Z
VSS
B
DQS3# D9 <5> M_CLK_DDR#0 H3 /CK
B
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
NU U2
<5> DDR_A_DM1 H5 DM1 NU U9 1 1 1 1
C178
C89
C90
C91
H6 VDDQ
J1 VSS
J2 NC 2 2 2 2
NU U10
<5> M_CLK_DDR0 J3 CK +VDD_1V8_DDR_MEM

J5 VSS 0.1U_0201_10V6K
0.01U_0201_16V7
C85 1 1 1 1
J6 VDDQ C86 C92 C87
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K 1 1 1 1
2 2 2 2
C97
C98
C99
C100
J7 VDD2 1U_0402_6.3V4Z
2 2 2 2
EDB8132B2MA-6D-F_FBGA134
X76_ELP_512M@
U7
X76_SAM_1GB@
( 1GB Samsung ) +VDD_1V8_DDR_MEM
SA00004YY20 0.1U_0201_10V6K
0.01U_0201_16V7
2 2
33P 50V J NPO 0201
33P 50V J NPO 0201

C260
C252
C93 1 1 1 1
C94 C95 C96
U7 0.1U_0201_10V6K 1 1
2 2 2 2
X76_ELP_1GB@
( 1GB Elpida ) 1U_0402_6.3V4Z
A
SA000050Z10 A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
D D
C C
Remove EC
+VDD_1V8_SYS_TEGRA
0.1U_0201_10V6K
PN:SA00004KS00 2
2k bit C115
U54
1
need check with WC of GPIO
1 A0 VCC 8
2 A1 WP 7 BOARD_ID_WP <7>
B
3 A2 SCL 6 PWR_I2C_SCL <7,14,15,26,32,34> B
4 GND SDA 5 PWR_I2C_SDA <7,14,15,26,32,34>
AT24C02C-XHM-T_TSSOP8
need check with SW Roger
08/04 Change U54 and C115 to @
08/12 Change U54 to SA000056G00
08/12 Change U54 footprint to AT24C64A-10TQ-2P7_TSSOP8
08/12 Change U54 footprint to AT24C64A-10TQ-2P7_TSSOP9
08/20 Change U54 to SA00004KS00
11/30 Change U54 to SA00005GV00
12/16 Change U54 to SA00004KS00(2K).
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
+VDDIO_1V8_EMMC
+VDD_2V85_EMMC
EMMC_CLK_R
@ C148 C149 @ C150 C117 C118

1
C122
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
C119
0.1U_0201_10V6K
1 1 1 2 2 1 1
1
12P_0201_50V8J
2
2.2U_0402_6.3VM
2
D 2 2 2 1 1 2 2 D
C120 C121
+VDDIO_1V8_EMMC 0.1U_0201_10V6K 0.1U_0201_10V6K
close U13 +VDD_2V85_EMMC
11/23 Reserver C148,C149 and C150 for Acer HW request.

11/23 Modify C117 from 2.2U 0402 to 10U 0402.
12/7 Modify C148,C149,C150 from @ to mount
12/16 Modify C148 and c150 from mount to @ for LDO solution.
AA3
AA5
T10
W4
M6
N5
U9
K6
Y4
U13
A4
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCC
VCC
VCC
VCC
NC +VDDIO_1V8_EMMC
A6 NC
A9 NC
A11 W5 EMMC_CMD_R 1 2
NC CMD R102 33_0201_1% EMMC_CMD <4>
B2 NC
B13 NC
D1 NC
D14 NC
2
H1 NC
H2 R113 R114
NC
4.7K_0201_5%
4.7K_0201_5%
H6 W6 EMMC_CLK_R R103 1 2 0_0201_5%
NC CLK EMMC_CLK <4>
H7 NC
H8
1
NC
H9 NC
H10 NC
H11 NC
H12 H3 EMMC_DAT0_R R104 1 2 33_0201_1%
NC DAT0 EMMC_DAT1_R R105 33_0201_1% EMMC_DA0 <4> EMMC_CMD_R
H13 NC DAT1 H4 1 2 EMMC_DA1 <4>
H14 H5 EMMC_DAT2_R R106 1 2 33_0201_1%
NC DAT2 EMMC_DAT3_R R107 33_0201_1% EMMC_DA2 <4> MMC_RST#
J1 NC DAT3 J2 1 2 EMMC_DA3 <4>
J7 J3 EMMC_DAT4_R R108 1 2 33_0201_1%
NC DAT4 EMMC_DAT5_R R109 33_0201_1% EMMC_DA4 <4>
C J8 NC DAT5 J4 1 2 EMMC_DA5 <4>
C
J9 J5 EMMC_DAT6_R R110 1 2 33_0201_1%
NC DAT6 EMMC_DAT7_R R111 33_0201_1% EMMC_DA6 <4>
J10 NC DAT7 J6 1 2 EMMC_DA7 <4>
J11 NC
J12 NC
J13 K2 C123 1 2 U13
NC VDDi
J14 NC 0.1U_0201_10V6K
KING16GB@
K1 NC NC U1
K3
K5
NC NC U2
U3 R112 0_0201_5% SA00004O610
NC NC MMC_RST# @
K7 NC RSTN U5 1 2 EMMC_RST# <4>
K8 NC NC U6
K9 U7 U13
NC NC
K10 NC NC U10 02/17 Change to 0201 shortpad SAND16GB@
K11 NC NC U12
K12
K13
NC NC U13
U14 SA00004XA00
NC NC
K14 NC NC V1
L1 NC NC V2
L2 V3 U13
NC NC
L3 NC NC V12 SAM16GB@
L4 NC NC V13
L12
L13
NC NC V14
W1
SA00004FN20
NC NC
L14 NC NC W2
M1 NC NC W3
M2 NC NC W7
M3 NC NC W8
M5 NC NC W9
M8 NC NC W10
M9 NC NC W11
M10 NC NC W12
M12 NC NC W13
M13 NC NC W14
M14 NC NC Y1
N1 Y3 U13
NC NC
N2 NC NC Y6 KING32GB@
B
N3 NC NC Y7 B
N10
N12
NC NC Y8
Y9
SA00004TD00
NC NC
N13 NC NC Y10
N14 NC NC Y11
P1 Y12 U13
NC NC
P2 NC NC Y13 SAM32GB@
P3 NC NC Y14
P10
P12
NC NC AA1
AA2 SA00004FO40
NC NC
P13 NC NC AA7
P14 NC NC AA8
R1 AA9 U13
NC NC
R2 NC NC AA10 SAND32GB@
R3 NC NC AA11
R5
R12
NC NC AA12
AA13
SA000052910
NC NC
R13 NC NC AA14
R14 NC NC AE1
T1 NC NC AE14
T2 NC NC AG2
T3 AG13 U13
NC NC
T5 NC NC AH4 SAND432GB@
T12 NC NC AH6
T13
T14
NC NC AH9
AH11 SA000042X20
NC NC
U13
13 NC SAND64GB@
14 NC NC 1
15
16
NC NC 2
3
SA00004XQ10 -*
NC NC
17 NC NC 4
18 NC NC 5
19 NC NC 6
20 NC NC 7
21 8
22
NC
NC
NC
NC 9 8/26 ADD for SKU control.
A 23 NC NC 10 A
24 NC NC 11
NC 12
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
AA6
AA4
Y5
Y2
K4
U8
R10
P5
M7
SAND64GB@
SDIN5F1-64G_TFBGA169
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
10/03 Modify C125,C126,C128,C129,C132,C139,C140,C141 and C142 from +VDD_LVDS to LB_VCC power domain.
08/09 Add C139-C140 for +VDD_LVDS
LB_VCC C131 C134 C124 C125 C126 C128 C129 C132 C139 C140 C141 C142 C127 C130 C133
PLLVCC
33P_0201_50V8J
33P_0201_50V8J
33P_0201_50V8J
33P_0201_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_16V7
0.01U_0201_16V7
0.01U_0201_16V7
0.01U_0201_16V7
1 2 1 1 1 1 1 2 1 1 2
1
2
2
2 1 2 2 2 2 2 1 2 2 1
D D
+VDD_LVDS
10/19 Modify U20 PN from SA000050500 to SA000059A00 U20
A2 LB_VCC 1 R192 2 R122 2 1 0_0402_5% +LCDVDD
VCC_1
B36 TA10 VCC_2 A7 0_0402_5% 09/26
A43 TA11 VCC_3 B39 Change R122 & R156 package from 0201 to 0402
R0 B37 B44 R156 2 @ 1 0_0402_5%
<4> LCD_D22 TA12 VCC_4 +3VS
R1 A44 B49
<4> LCD_D23 R2 TA13 VCC_5
<4> LCD_D12 B38 TA14 VCC_6 A63
R3 A45 B59
<4> LCD_D13 R4 TA15 VCC_7
<4> LCD_D14 B40 TA16 VCC_8 A76
R5 A47 (3.3V)
<4> LCD_D15 R6 TA17
<4> LCD_D16 A48 TA18 LVCC_1 A24
R7 B41 B23
<4> LCD_D17 TA19 LVCC_2
A49 TB10 LVCC_3 B26
B42 TB11 LVCC_4 B29 09/21 Isolated LB_VCC and PLLVCC.
G0 A50 A37
<4> LCD_D20 G1 TB12 LVCC_5
<4> LCD_D21 B43 TB13
G2 A51 CH 1 Input A19 PLLVCC 1 R189 2
<4> LCD_D06 G3 TB14 PVCC_1
B45 B35 0_0402_5%
<4> LCD_D07 G4 TB15 PVCC_2
<4> LCD_D08 A53 TB16
G5 B46 LVDS_ACLK2 R125 1 2 0_0201_5% LVDS_ACLK1 R126 1 2 0_0201_5%
<4> LCD_D09 TB17 LVDS_ACLK2_R <13> LVDS_ACLK1_R <13>
G6 A54 @ @
<4> LCD_D10 G7 TB18
A55 L5 L6
<4> LCD_D11 TB19
B47 B33 LVDS_A0 4 3 4 3
TC10 TXA1+ LVDS_A0# 4 3 4 3
A56 TC11 TXA1- A39
B0 B48 SM070002I00 SM070002I00
<4> LCD_D18 B1 TC12
A57 B32 LVDS_A1 1 2 1 2
<4> LCD_D19 B2 TC13 TXB1+ 1 2 1 2
B50 A38 LVDS_A1#
<4> LCD_D00 B3 TC14 TXB1-
A59 S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
<4> LCD_D01 B4 TC15
B51 B30 LVDS_A2 LVDS_ACLK2# R123 1 2 0_0201_5% LVDS_ACLK2#_R <13> LVDS_ACLK1# R124 1 2 0_0201_5% LVDS_ACLK1#_R <13>
<4> LCD_D02 B5 TC16 LVDS CH1 TXC1+
B52 A36 LVDS_A2# @ @
<4> LCD_D03 B6 TC17 TXC1-
<4> LCD_D04 A62 TC18
B7 B53 A32 LVDS_A3 LVDS_A4 R127 1 2 0_0201_5% LVDS_A0 R128 1 2 0_0201_5%
<4> LCD_D05 TC19 TXD1+ LVDS_A4_R <13> LVDS_A0_R <13>
B8 B28 LVDS_A3# @ @
RES11 TXD1- L8 L7
A10 RES12
C
TXE1+ A31 2 1 4 4 3 3 4 4 3 3 C
A64 B27 R73 100_0201_1%
TA20 TXE1-
09/21 swap LCD_D00~LCD_D23 for colay. B55 TA21 SM070002I00 SM070002I00
A65 TA22 1 1 2 2 1 1 2 2
B56 A29 LVDS_A4
TA23 TXA2+ LVDS_A4# S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
A66 TA24 TXA2- B25
A67 LVDS_A4# R129 1 2 0_0201_5% LVDS_A4#_R <13> LVDS_A0# R130 1 2 0_0201_5% LVDS_A0#_R <13>
TA25 LVDS_A5 @ @
B57 TA26 TXB2+ A28
A68 B24 LVDS_A5#
TA27 TXB2-
B58 TA28
A69 B22 LVDS_A6 LVDS_A5 R131 1 2 0_0201_5% LVDS_A5_R <13> LVDS_A1 R132 1 2 0_0201_5% LVDS_A1_R <13>
TA29 LVDS CH2 TXC2+ LVDS_A6# @ @
B60 TB20 TXC2- A26
+VDD_LVDS A71 L10 L9
TB21 LVDS_A7
B61 TB22 TXD2+ B19 4 4 3 3 4 4 3 3
A72 A23 LVDS_A7#
TB23 CH 2 Input TXD2-
B62 TB24 SM070002I00 SM070002I00
2
A73 TB25 TXE2+ B18 2 1 1 1 2 2 1 1 2 2

R139 B63 A22 R74 100_0201_1%
TB26 TXE2- S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
10K_0201_5% A74 TB27
A75 LVDS_A5# R133 1 2 0_0201_5% LVDS_A5#_R <13> LVDS_A1# R134 1 2 0_0201_5% LVDS_A1#_R <13>
PICASSO_M@ TB28 LVDS_ACLK1 @ @
B64 A34
1
LVDS_MAP TB29 TCLK1+ LVDS_ACLK1#

A77 TC20 TCLK1- A35
B66 LVDS_A6 R135 1 2 0_0201_5% LVDS_A6_R <13> LVDS_A2 R136 1 2 0_0201_5% LVDS_A2_R <13>
TC21
2
A78 B21 LVDS_ACLK2 @ @

R193 TC22 TCLK2+ LVDS_ACLK2# L11 L12
B67 TC23 TCLK2- A25
10K_0201_5% A79 TC24 4 4 3 3 4 4 3 3
B68 TC25 1 1 1 1
10P_0201_50V8J
C328
10P_0201_50V8J
C338
10P_0201_50V8J
C360
10P_0201_50V8J
C364
PICASSO_2@ A1 SM070002I00 SM070002I00
1
TC26
B1 TC27 TEST A17 1 1 2 2 1 1 2 2
A3 TC28 2 2 2 2
09/21 Add R165 select pin for Picasso M. B3 TC29
S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
B9 LVDS_A6# R137 1 2 0_0201_5% LVDS_A6#_R <13> LVDS_A2# R138 1 2 0_0201_5% LVDS_A2#_R <13>
RES21 @ @
A11 RES22 NC_1 B5
NC_2 A6
LVDS_MAP configuration: <4> LCD_VSYNC B4 VSYNC NC_3 B6
A4 A9 LVDS_A7 R249 1 2 0_0201_5% LVDS_A7_R <13> LVDS_A3 R247 1 2 0_0201_5% LVDS_A3_R <13>
High: Picasso M <4> LCD_HSYNC HSYNC Input control NC_4
A5 B11 @ @
<4> LCD_DE DE NC_5
B
Low: Picasso 2 NC_6 B13 L45 L46
B
<4> LCD_PCLK B7 CLKIN NC_7 A16 4 4 3 3 4 4 3 3
NC_8 B15 SM070002I00 SM070002I00
LVDS_MAP A13 A18
LVDS_CTRL0 MAP NC_9
A14 CTRL0 NC_10 A60 1 1 2 2 1 1 2 2
LVDS_CTRL1 B12 A61
LVDS_CTRL2 CTRL1 NC_11 S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
A15 CTRL2 NC_12 A80
LVDS_A7# R252 1 2 0_0201_5% LVDS_A7#_R <13> LVDS_A3# R250 1 2 0_0201_5% LVDS_A3#_R <13>
LVDS_RF B10 @ @
R/F
GND_PAD
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
LGND_1
LGND_2
LGND_3
LGND_4
LGND_5
LGND_6
LGND_7
LGND_8
LVDS_RS A12 11/11 Add C328,C338,C360 and C364 for Acer RF request.
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
RS
<4> LVDS_SHTDN# B14 PD# 1RLP105ANQG8_QFN148_11X11 08/05 Change L5-L12,L45,L46 to mount

B2
A8
A46
A52
A58
B54
A70
B65
A42
A41
A20
B17
B16
A21
B20
A27
A30
A33
B31
B34
A40
Z1
2
need check for single in single out 08/12 Change L5-L12,L45,L46 to SM070002N00
R148
10K_0201_5% @ 10/17 Chanfe Bead P/N from SM070002N00 to SM070002I00
+VDD_LVDS +VDD_LVDS +VDD_LVDS
Close LVDS Transmitter (U20)

1
2
R144 @ R140 R147 PICASSO_M@

10K_0201_5% 10K_0201_5% 10K_0201_5% 08/12 Add R148 PD LVDS_SHTDN# to GND
1
LVDS_CTRL2 LVDS_CTRL1 LVDS_CTRL0

2
+VDD_LVDS LVDS
R143 R141 PICASSO_2@ +VDD_LVDS RS Input Voltage Output Swing CMOS/TTL Input Configuration ( Input Voltage Swing
10K_0201_5% 10K_0201_5%
1
VCC 350 mV Standard Input and Output Configuration

1
R146
R188 200K _0201_1%
10K_0201_5% 0.6 ~ 1.4 V 350 mV Small Input Swing, Standard Output Swing Configuration
2
A A
1
CTRL[2:0] = LHL Single-In, Dual-Out (DDR Off) LVDS_RF C135 LVDS_RS GND 200 mV Standard Input Swing, Reduced Output Swing Configuration
2
0.1U_0201_10V6K
R145 @ 1
CTRL[2:0] = HHL Single-In, Dual-Out (DDR On) 0_0201_5% R142 @
100K_0201_5% 10/14 Modify LVDS_RS from pull up to pull down to reduce power consumption.
1
2
11/1 Modify LVDS_RS from pull down to pull up to meet SPEC
2
CTRL[2:0] = LHH Single-In, Single-Out (Distribution Off) Security Classification Compal Secret Data Compal Electronics, Inc.
CTRL[2:0] = HHH Single-In, Single-Out (Distribution On) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
08/01 Change L13 to SM010031680

08/01 Change L13 footprint to +LCDVDD
KC_FBMA-L11-160808-121LMT_2P
U21 L13
1 +LCDVDD_L 1 2
VOUT FBMA-L11-160808-301LMA20T_0603~D
+3VS 5 VIN
2 1 1 1 C188 1
R279 0_0201_5% GND C180 C181 C182
3300P_0201_16V6K
39P_0201_50V8J
@
0.1U_0201_10V6K
4.7U_0402_6.3V6M
<4> EN_VDDLCD_T30S 1 2 4 EN
OCB 3
2 2 2 2
D D
+LCDVDD
APL3511CBI-TRG_SOT23-5
1
R150
100K_0201_5%
1 1
C179 C185
2
0.1U_0201_10V6K 1U_0402_6.3V4Z
2 2 11/06 Add for COMPAL EMI request.
LCD POWER CIRCUIT
JLVDS1
1 1
2 2 +LCDVDD
3 3
Panel SPEC 4 4
5 5
6
2 VDD Power Supply +3.3V 6
Remove LVDS I2C
3 VDD Power Supply +3.3V
7 7
8 10/19 Add for Discharge +5VS
8
9
4 VDDEDID EDID +3.3V 9
10
LVDS_A0#_R <12>
10 LVDS_A0_R <12> B+ +5VS
11 11
12 12 LVDS_A1#_R <12>
C
13 13 LVDS_A1_R <12> C
14 14
1
38 DCR_EN (CABC_EN) Dynamic backlight control 15 15 LVDS_A2#_R <12>
R95 R96
39 PWM_IN System PWM signal input for dimming 16 16
17
LVDS_A2_R <12>
100K_0201_5% 1K_0201_1%
40 PWM_OUT Panel PWM signal output to system 17
18 LVDS_ACLK1#_R <12>
18
19 LVDS_ACLK1_R <12>
2
19 Q48
20
43 LED_CA5 LED Cathode 5 20
21 5 4
21 LVDS_A3#_R <12> G1 S1
44 LED_CA4 LED Cathode 4 22 22 LVDS_A3_R <12> D1 3
45 LED_CA3 LED Cathode 3 23 23 D2 6
24 2 1
46 LED_CA2 LED Cathode 2 24
25
LVDS_A4#_R <12> <28,32> EN_5V0_BUCKBOOST G2 S2
25 LVDS_A4_R <12>
47 LED_CA1 LED Cathode 1 26 26 02/22 Change to 0201 shortpad DMN2004DWK-7_SOT363-6
27 27 LVDS_A5#_R <12>
28 8/25 Acer request
49 VLED Output LED Backlight power 28
29
LVDS_A5_R <12>
29
50 VLED Output LED Backlight power 30 30 LVDS_A6#_R <12> Add R86,R83&R82 to panel back light.
31 31 LVDS_A6_R <12>
32 32
33 33 LVDS_ACLK2#_R <12>
34 R86 0_0201_5%
34 LVDS_ACLK2_R <12>
35 LCD_PWM_OUT 2 1 INVTPWM
35
36 36 LVDS_A7#_R <12>
37 37 LVDS_A7_R <12>
38 38
39 39 LCD_DCR <4>
40 40 R83 2 @ 1 0_0201_5% LCD_PWM_OUT <4> 40 . to LED power IC
41 41 R82 2 @ 1 0_0201_5% INVTPWM <31> 41 . For Picasso 1 Pannel backlight
42 42 DISPOFF# <4,31>
43 43 FB5 <31>
44 44 FB4 <31>
45 45 FB3 <31>
51 46 +5VS
GND 46 FB2 <31>
52 GND 47 47 FB1 <31>
53 GND 48 48
54 49 +VDD_LED_BL L14
GND 49
B 50 50 1 2 B
MPZ1005S300CT_2P
STARC_300E50-0010RA-G3
CONN@ 1 1 1 1
C169 C184 C168 C183
Remove C188 , due to PC57,PC55 is close to pin 48 2 2 2 2
0.1U_0201_10V6K
LTCX003KB00
07/28 Change JLVDS1 footprint 4.7U_0402_6.3V6M 0.1U_0201_10V6K 4.7U_0402_6.3V6M
JTP1
1 1
<4> GEN2_I2C_SCL 2 2
<4> GEN2_I2C_SDA 3 3
<4> TS_INT# 4 4
5 5
<4> TS_RST# 6 6
7 7
<4> TS_PWR_EN 8 8
T15 PAD @ 9 9
T16 PAD @ 10 10
10/02 Modify R166 BOM Structure from Mount to Unmount
11 GND1
12 GND2
+3VS TS_INT# GEN2_I2C_SCL
TS_RST# GEN2_I2C_SDA ACES_50506-01041-001
CONN@
1
R166
2
LTCX003HG00
100K_0201_5% D12 @ D13 @
@ TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
2
A TS_RST# SCA00001W00 SCA00001W00 A

1
1
Touch Panel

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
+VDD_1V8_AUDIO
R168
1 2 VDD_IO_305
0_0201_5% 1 1
C193 C194
1U_0402_6.3V4Z 0.1U_0201_10V6K
2 2
D D
VDD_DAL_305 +VDD_1V8_AUDIO
1 1
C196 C197
1
1U_0402_6.3V4Z 0.1U_0201_10V6K
2 2 R167 @
10K_0201_5%
2
R169 0_0201_5% U23 +VDD_1V8_AUDIO
1 @ 2 AUDIO_SEL_R 1 10 CODEC_IN
<6> AUDIO_SEL IN1 COM1
AUDIO_DOUT2 2 9
VDD_P_305 NO1 NC1
3 GND V+ 8
1 1 AUDIO_DIN2 4 7 1
NO2 NC2
2
C198 C199 5 6 CODEC_OUT C195
R170 IN2 COM2
1U_0402_6.3V4Z 0.1U_0201_10V6K 470K_0402_5% TS5A23157RSER_QFN10_2X1P5 0.1U_0201_10V6K
2 2 2
+VDD_1V8_AUDIO SA000039100
1
1
R180 @ R177
10K_0201_5% AUDIO_DOUT2_R 1 2 AUDIO_DOUT2 <6>
0_0201_5%
2
UART_SOUT R178 0_0201_5% 02/17 Change to 0201 shortpad
AUDIO_DIN2_R 1 @ 2 AUDIO_DIN2 <6>
+VDD_1V8_AUDIO Support for input clock frequencies of 24 MHz and 26 MHz
requires a 10k pull-up resistor on the UART_SOUT pin. R171
<15> AUDIO_SCLK2_VOICE 1 2 AUDIO_SCLK2 <6>
0_0201_5%
1 ES305_INT
C380 R174
C 0.01U_0201_16V7 1 2 C
<15> AUDIO_FS2_VOICE AUDIO_FS2 <6>
1
2
0_0201_5%
R187 2 R205
@ R184 0_0201_5% 470K_0402_5%
10K_0201_5%
20110823 Modify for Acer request
2
1
AUDIO_FS2_VOICE connect to portA and CODEC,
R182 0_0201_5% X5
1 @ 2 1 4 AUDIO_FS2 connect to portB, portC and CPU.
<6> EN_ES305_OSC OE VDD
2 3 ES305_CLK_12M AUDIO_SCLK2_VOICE connect to portA and CODEC
GND OUTPUT
2
R183 12MHZ_15PF_FK1200007 AUDIO_SCLK2 connect to portB, portC and CPU.

470K_0402_5%
Vcount Output
SJ000004400
1
H OSC out 07/27 Change X5 footprint

OPEN OSC out
L High Z Active --> 17 mA
Sleep --> 35 uA 20110823 Modify for Acer request
U24
VDD_IO_305 D6 A2
VDD_IO PORTA_DI CODEC_OUT <15>
VDD_DAL_305 C6 B2 CODEC_IN <15>
VDD_DAL PORTA_DO
B6 A1 AUDIO_SCLK2_VOICE
VDD_DPD PORTA_CLK
VDD_P_305 A6 B1 AUDIO_FS2_VOICE
VDD_P PORTA_FS
R185 1 @ 2 0_0201_5%
<7> CLK_12M_ES305
SW ES305_CLK_12M R186 1
R172 1
2 0_0201_5% ES305_CLK_IN
UART_SIN
A4 CLK_IN 12M ~ 16M PORTB_DI F3 AUDIO_DOUT2_R
<7> AUDIO_UART4_TX 2 0_0201_5% A3 UART_SIN PORTB_DO F4 R173 2 1 100K_0201_5%

B B
R175 1 2 0_0201_5% UART_SOUT B4 E4 AUDIO_SCLK2
<7> AUDIO_UART4_RX UART_SOUT PORTB_CLK
R176 1 2 0_0201_5% ES305_INT B3 E3 AUDIO_FS2
<6> ES305_INT_R GPIO_A PORTB_FS
02/22 Change to 0201 shortpad ES305_I2C_SDA B5 I2C_DATA
ES305_I2C_SCL C5 F2 AUDIO_DOUT2_R
R179 0_0201_5% I2C_CLK PORTC_DI
AUDIO_DIN2 CODEC_OUT @ AUDIO_RST#_R AUDIO_DIN2_R
DAP2_DIN C_DO A_DI ADC <6> AUDIO_RST# 1 2 D5 RESET_ low active PORTC_DO E2
02/17 Change to 0201 shortpad F5 E1 AUDIO_SCLK2

TEST PORTC_CLK
AUDIO_DOUT2 CODEC_IN AUDIO_FS2
DAP2_DOUT C_DI A_DO DAC PORTC_FS F1
AUDIO_SCLK2 AUDIO_SCLK2_VOICE
DAP2_SCLK C_CLK A_CLK CLK A5 GND_P PORTD_DI D1
E5 GND PORTD_DO C1
DAP2_FS C_FS A_FS LRC E6 GND PORTD_CLK C2
2
AUDIO_FS2 AUDIO_FS2_VOICE F6 GND PORTD_FS D2
T30S ES305 WM8903 ES305_BGA32 R181

100K_0201_5%
B_DO D_DO
1
10/11 Change P/N from SA00004Y400 to SA00004Y410
B_DI D_DI
R226 1 2 0_0201_5% ES305_I2C_SDA

B_CLK D_CLK <7,10,15,26,32,34> PWR_I2C_SDA
R246 1 2 0_0201_5% ES305_I2C_SCL
<7,10,15,26,32,34> PWR_I2C_SCL
A A
B_FS D_FS

Audio Block Diagram Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
AUDIO_CLK_R AUDIO_SCLK2_VOICE
+VDD_1V8_AUDIO +VDD_1V8_AUDIO +CPVDD +AVDD_CDC
1
R190 @ R191 @
0_0201_5% 0_0201_5% 1 1 1 1
C213 C214 C212 C216
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2
C217 R194
2 2 2 2
2 2 1 2 2 1
1
C236 C218 C219 0.1U_0201_10V6K 20_0402_5%
33P_0201_50V8J 68P_0201_25V8 68P_0201_25V8 Close U113.40 Close U113.39 Close U113.10 Close U113.24
2
1 1
@ @
C220 R196
1 2 2 1
D D
08/09 Add C236 for AUDIO_CLK_R +VDD_1V8_AUDIO
0.1U_0201_10V6K 20_0402_5%
R256 1 2 0_0201_5% CODEC_I2C_SDA +VDD_1V8_AUDIO Audio Codec 3/28 Change R443 from 0ohm(@) to 33pF (mount).
<7,10,14,26,32,34> PWR_I2C_SDA U25
R322 1 2 0_0201_5% CODEC_I2C_SCL 39 16 CDC_HP_R
9/19 Modify Value from 1u to 0.1u Acer Request.
<7,10,14,26,32,34> PWR_I2C_SCL DCVDD HPOUTR
L41 40 18 CDC_HP_L R199
L17 +CPVDD DBVDD HPOUTL R443 1
1 2 10 CPVDD HPGND 17 2 33P 50V J NPO 0201 C221 1 2 0.1U_0402_10V7K 1 2
1 2 FBMA-10-100505-121T_0402 +AVDD_CDC 24
FBMA-10-100505-121T_0402 AVDD R446 10_0201_5% 2 20_0402_5%
HPGND <20>
CODEC_I2C_SCL 37 19 L43 2 1
SCLK LINEOUTR LINE_DOCK_R <20>
CODEC_I2C_SDA 36 21 L42 2 1
SDIN LINEOUTL LINE_DOCK_L <20>
EN_SPEK 5 20 R447 10_0201_5% 2 @ S SUPPRE_ KC FBMA-11-100505-601T 0402
<6> CDC_IRQ# INTERRUPT LINEGND S SUPPRE_ KC FBMA-11-100505-601T 0402
2 R452 10_0201_5% 2
<6> AUDIO_CLK_R MCLK LINEGND <20>
1
6 22 CDC_LEFT_P C222 1 2 0.1U_0402_10V7K 1 2

R457 <14> AUDIO_SCLK2_VOICE BCLK LOP CDC_LEFT_N
300K_0201_1%
8/24 Modify Net Name for Acer request. <14> AUDIO_FS2_VOICE 8 LRC LON 23
28 CDC_RIGHT_P 20_0402_5%
ROP CDC_RIGHT_N R204
<14> CODEC_IN 7 DACDAT RON 27
<14> CODEC_OUT 9
2
ADCDAT CFB1 C223 1

02/17 Change to 0201 shortpad CFB1 11 2 2.2U_0402_6.3VM
R430 0_0201_5% EN_SPEK 38 13 CFB2 +MIC_BIAS +VMID_CDC +VPOS_CDC +VNEG_CDC
@ SHORT_DETECT GPIO3/ADDR CFB2
<7> SHORT_DET 1 2 3 DMIC_DAT/GPIO2
4 DMIC_LR/GPIO1 MICBIAS 29 +MIC_BIAS
C226 C227
10/13 Modify R392 from 0 ohm to 1K for noise issue. CDC_COM_MIC C230 1 2 1U_0402_10V6K
1 1
C228
1
C229
1
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
32 IN1R VMID 25 +VMID_CDC
C231 1 2 1U_0402_10V6K 35 14 +VPOS_CDC
R392 1 CDC_COM_MIC IN1L VPOS
2 1K_0402_5%
2.2U_0402_6.3VM
2.2U_0402_6.3VM
<20> COM_MIC VNEG 15 +VNEG_CDC
AMIC_RIGHT+ C224 1 2 2 2 2
2 1U_0402_10V6K 31 IN2R
2 AMIC_LEFT+ C225 1 2 1U_0402_10V6K 34 12
C209 IN2L CPGND
AGND 26
AMIC_RIGHT- C269 1 2 1U_0402_10V6K 30 41
100P_0201_25V8J AMIC_LEFT- C258 1 IN3R GNDPAD
2 1U_0402_10V6K 33 IN3L DGND 1
1
WM8903LGEFK-RV_QFN40_5X5
CDC_HP_R 1 R409 2 HP_R

HP_R <20> 8/25 Modify Value for Acer request. SA00003MP00
C 68NH_5% LQG15HS68NJ02D C
CDC_HP_L 1 R423 2 HP_L
HP_L <20>
10/2 Modify C398&C399 from 1u to 2.2u for Acer AUDIO
68NH_5% LQG15HS68NJ02D
+VDD_1V8_AUDIO 10/2 Modify C257&C270 from 1u to 10u for Acer AUDIO
9/22 Add R151&R165 for MIC noise issue
2
C210 C211
33P_0201_50V8J 33P_0201_50V8J
R151 1 2 0_0402_5% +VDD_1V8_MIC S SUPPRE_ KC FBMA-11-100505-601T 0402
1
NONLDO@ S SUPPRE_ KC FBMA-11-100505-601T 0402

+VDD_1V8_AUDIO_LDO
R165 1 2 0_0402_5%
LDO@ Main MIC Second MIC AMIC_RIGHT+ L18 2 1 AMIC_R+ <20>
2
AMIC_RIGHT- L19 2 1 AMIC_R- <20>
R243 R212
11/17 Modify C210&C211 form 100P to 33P for Acer AUDIO request. 620_0402_5% 620_0402_5%
C234 2 C235 from Docking/B
12/2 Modify R409 and R423 from 0ohm to 68nH for Acer AUDIO request. 2
100P_0201_25V8J
100P_0201_25V8J
C232 2 2 C233
100P_0201_25V8J
100P_0201_25V8J
C270 1 2 C257 1 2
R265 C399 2.2U_0402_6.3VM R213 C398 2.2U_0402_6.3VM
MIC_GND 2 MIC_GND 2 1 1
1 1 2 1 1 2
1 1
620_0402_5% 620_0402_5%
MIC_GND 10U_0402_6.3V6M 10U_0402_6.3V6M
D
1
4.7U_0402_6.3V6M
2
+MIC_BIAS 2 Q23
G BSS138W-7-F_SOT323-3 NONLDO@ 1 C237 R260 R221 R209 R206
S NONLDO@ LDO@ 620_0402_5% 620_0402_5% 620_0402_5% 620_0402_5% S SUPPRE_ KC FBMA-11-100505-680T 0402
3
C237
S SUPPRE_ KC FBMA-11-100505-680T 0402

Vth (Max) = 1.5 SD028000080
1
1
2 AMIC_LEFT+ AMIC_RIGHT+ AMIC_LEFT+ L50 AMIC_L+
2 1
AMIC_LEFT- L51 2 1 AMIC_L-
0_0402_5% AMIC_LEFT- AMIC_RIGHT-
47P 25V J NPO 0201
47P 25V J NPO 0201

2 2
47P 25V J NPO 0201
47P 25V J NPO 0201

10/04 Add R269,C206 and C207 for Main Mic issue. referece to Acer
2 2
C2551 C2561
B
Int. Speaker Conn. JSPK1
03/28 Unmount C207,Change C206 to 0.1uF 0201.
R269 620_0402_5% JMIC1
C2531
1 1
C2541 1 1
B
SPKR_LEFT# L20 2 1 FBMA-101_0402 SPK_L# 1 AMIC_L+ 2 1 AMIC_L+_R 1
SPKR_LEFT L21 FBMA-101_0402 SPK_L 1 AMIC_L- 1
2 1 2 2 2 2
SPKR_RIGHT# L22 2 1 FBMA-101_0402 SPK_R# 3 5
SPKR_RIGHT L23 FBMA-101_0402 SPK_R 3 G1 C206
2 1 4 4 G2 6
2 2 1
3
C240 C241 C242 C243 ACES_50281-0040N-001 @ 3
08/01 Change L20-L23 to SM01000DI00 2 2 2 2 CONN@ C207 0.1U_0201_10V6K 4
GND1
GND2 10/7 Change L51 and L50 from 60ohm to 68 ohm.
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
33P 50V J NPO 0201

SP02000SC00
1
TVNST52302AB0_SOT523-3
ACES_50281-0020N-001 10/7 Change C2531,C2541,C2551 and C2561 from 100P to 47P
SPK_R# SPK_L# 1 1 1 1 D8
SPK_R SPK_L
SCA00001W00
1 CONN@
SP02000S000
9/22 Add for MIC noise issue
2
D6
TVNST52302AB0_SOT523-3
D7
TVNST52302AB0_SOT523-3 B+ +AMP_VDD +MIC_BIAS
Must change to correct symbol&footprint
R445 1 2 0_0402_5% +3VS
SCA00001W00 SCA00001W00
1
+VDD_1V8_AUDIO_LDO
+AMP_VDD
2
1 U8
R197 C202 +MIC_BIAS
+AMP_VDD
1 VIN VOUT 5
0_0201_5% 3 EN
2 1 4 BP GND 1 2 2
C238 10U_0402_6.3V6M 2 LDO@ LDO@
1
1 2 C143 C116
2 1 1 2 4.7U_0402_6.3V6M LDO@ LDO@ LDO@ 1U_0402_6.3V4Z 0.1U_0201_10V6K
C261 10U_0402_6.3V6M C239 1U_0402_6.3V4Z C145 C144 RP114Q182D-TR-FE SC-88A 5P 2 1
1
1U_0402_6.3V4Z 0.1U_0201_10V6K
R198 2 1
2.2K_0201_1%
B1
B2
B1
B2
1U_0402_6.3V4Z U2 U5
SA000059P00
2
C250 150K_0201_5% C248 1U_0402_6.3V4Z 150K_0201_5%

VDD
PVDD
VDD
PVDD
CDC_LEFT_P 1 2 1 2 A1 CDC_RIGHT_P 1 2 1 2 A1 COM_MIC

CDC_LEFT_N 1 IN+ CDC_RIGHT_N IN+
A 2 1 R259 2 C1 IN- 1 2 1 R267 2 C1 IN-
A
C251 R263 C249 1U_0402_6.3V4Z R268
1U_0402_6.3V4Z 150K_0201_5% C3 SPKR_LEFT 150K_0201_5% C3 SPKR_RIGHT
VO+ SPKR_LEFT# VO+ SPKR_RIGHT#
VO- A3 VO- A3 2 1
R200 0_0201_5% EAR_JACK_GND <20>
EN_SPEK C2 EN_SPEK C2
SHUTDOWN# SHUTDOWN#
resistor is for gain setting resistor is for gain setting close to 8903 for psudo differential
GND
GND
GND
GND

A2
B3
A2
B3
APA2010HAI-TRG WLCSP 9P CLASS D AMP APA2010HAI-TRG WLCSP 9P CLASS D AMP

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
GYRO_CLKIN GYRO_FSYNC
V_logic must be <= VDD at all time
1
R253 @ R255 @
10K_0201_5% 10K_0201_5%
2
D +VDD_3V3_SENSOR D
GYRO
U29
GYRO_CLKIN 1 13 C253 1 2 0.1U_0201_10V6K

IME_DA CLKIN VDD
6 IME_DA
IME_CL 7 10 C254 1 2 0.1U_0201_10V6K
IME_CL REGOUT GYRO_FSYNC R220
+VDD_1V8_SENSOR 8 VLOGIC FSYNC 11
AD0 9 12 GYRO_INT 1 2 GYRO_INT_R <6>
AD0 INT 0_0201_5%
CPOUT 20 1 2
1 22 C255 2200P_0201_50V7K
CLKOUT
07/28 Change C255 to SE00000TE00
C256 2 NC
0.1U_0201_10V6K 3 NC SCL 23 GEN1_I2C_SCL <7,20>
2
4 NC SDA 24 GEN1_I2C_SDA <7,20>
5 NC
14 NC GND 18
15 NC
16 NC RESV 19
17 NC RESV 21
MPU-3050_QFN24_4X4
AD0
G Sensor
1
R224
10K_0201_5%
U31
2
+VDD_1V8_SENSOR 1 10 IME_DA
IO VDD SDA IME_CL
1 2 DNC SCL 9
C 3 DNC DNC 8 C
C259 4 7 G_INT 1 2 G_ACC_INT <7>
GND INT R231 0_0201_5%
0.1U_0201_10V6K 5 VDD DNC 6
2
07/28 Change R224 to 10K
KXTF9-4100_LGA10_3X3
B
P Sensor 08/09 Change PAD2 to CLIP_1P8X3P2
08/12 Change PAD2 footprint to EMIST_SQ-21G_1P B
+VDD_3V3_SENSOR TP
2
PAD2
C111 @ CONN@
2
2P_0402_50V8C
R14 @ 1
1
4.7K_0402_5%
R16 @ +VDD_3V3_SENSOR
U6 @ 470_0402_5%
1
2 1 POUTL_R 1 6 2 1 CAP3
<4> POUT_WIFI OUT CX
2 VSS VDDHI 5
R15 @ CTRL 3 4 CAP_VREG
0_0402_5% CTRL VREG
2
IQS12800100TSR_TSOT23-6 @
2
D11
R13
1 2 1
SCA00001W00
10K_0402_5% @ C114 C112 @ C113 @ TVNST52302AB0_SOT523-3
@ 1U_0402_6.3V4Z 100P_0402_50V8J 1U_0402_6.3V4Z
2 1 2
close to PAD2
1
9/15 Add D11 to Compal ESD request.
10/13 Modify R14,U6,C111,R16,D11,C113,C112 and C114 from WIFI @ to @ .
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
U39
1 +VDD_VCM_3V3 +VDD_CAM_2V8_R +VDD_CAM_1V8_R
+3VS VIN
1 VOUT 5 +VDD_CAM_2V8
2 GND 1 1 1
C276 1 1 1
1
2.2U_0402_6.3VM 4 C281 C282 C283
2 NC 0.1U_0201_10V6K C277 C278 C279 C280 0.1U_0201_10V6K 2.2U_0402_6.3VM
<7> EN_CAM_2V8 3 EN 2 0.1U_0201_10V6K 2.2U_0402_6.3VM 0.1U_0201_10V6K 47U_0805_4V6 2 2
2
1
2 2 2
@ R257 APL5603-28BI-TRG_SOT23-5
D D
100K_0201_5% SA00004BW00
Vth=1.6V
2
10/17 Change L24-L28,L34 to 0 ohm 11/3 Modify R257 to unmount for panel garbage issue.
08/05 Change L24-L28,L34 to mount
08/05 Change L24-L28,L34 to SM070002N00
R258
1 2 5M_CAM_CLK#
<6> 5M_CAM_CLK#_R
0_0201_5%
L24 @
4 4 3 3
SM070002N00
1 1 2 2
OCF1210900YZF_4P JCAM1
2M_CAM_DA2 1 2
R261 2M_CAM_DA2# 1 2
3 3 4 4
1 2 5M_CAM_CLK 5 6
<6> 5M_CAM_CLK_R 2M_CAM_CLK 5 6
7 7 8 8 2M_CAM_PWDN <6>
0_0201_5% 2M_CAM_CLK# 9 10 +VDD_CAM_2V8_R +VDD_CAM_2V8
9 10
11 11 12 12
2M_CAM_DA1# 13 14 1 2
R262 2M_CAM_DA1 13 14 R274 0_0402_5%
15 15 16 16
1 2 5M_CAM_DA1# 17 18 2M_CAM_RST# <6>
<6> 5M_CAM_DA1#_R 17 18
08/09 Add C373,C374,R271 for CAM_MCLK 19 19 20 20 CAM_I2C_SCL <6,26,35>
0_0201_5% 21 22
R271 21 22 CAM_I2C_SDA <6,26,35>+VDD_CAM_1V8_R +VDD_CAM_1V8
23 23 24 24
L25 @ 1 2 CAM_MCLK_R 25 26
<6> CAM_MCLK 25 26
4 4 3 3 27 27 28 28 1 2
SM070002N00 1 0_0201_5% 5M_CAM_DA2 29 30 R275 0_0402_5%
29 30
1
5M_CAM_DA2# 31 32 5M_CAM_RST# <6>
C373 C374 31 32
C 1 1 2 2 33 33 34 34 CAM_LED_EN <35> C
22P_0201_25V8 33P_0201_50V8J 5M_CAM_CLK 35 36 5M_CAM_PWDN <6>
2
OCF1210900YZF_4P 2 5M_CAM_CLK# 35 36
37 37 38 38
39 39 40 40
R264 5M_CAM_DA1 41 42
5M_CAM_DA1 5M_CAM_DA1# 41 42
<6> 5M_CAM_DA1_R 1 2 43 43 44 44 +VDD_VCM_3V3
45 GND GND 46
0_0201_5% 47 48
GND GND
PANAS_AXK8L44124BG
R266 CONN@
1 2 5M_CAM_DA2#
<6> 5M_CAM_DA2#_R
0_0201_5%
LTCX003I300
L26 @
4 3
1
4
1
3
2 2
SM070002N00
Camera Board reference Acer schematic
CAM_LED_EN
OCF1210900YZF_4P 5M_CAM_RST#
CAM_I2C_SCL
R270 CAM_I2C_SDA
1 2 5M_CAM_DA2 5M_CAM_PWDN
<6> 5M_CAM_DA2_R
0_0201_5% 1 1 1 1 1
C321 C327 C334 C361 C362
10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J
2 2 2 2 2
R277
1 2 2M_CAM_CLK#
<6> 2M_CAM_CLK#_R
0_0201_5%
B B
L27 @
4 4 3 3
SM070002N00
1 1 2 2
OCF1210900YZF_4P reference Acer schematic

R280
1 2 2M_CAM_CLK
<6> 2M_CAM_CLK_R 2M_CAM_RST#
0_0201_5% 2M_CAM_PWDN
R281
1 2 2M_CAM_DA1# 1 1
<6> 2M_CAM_DA1#_R C363 C366
0_0201_5% 10P_0201_50V8J 10P_0201_50V8J
L28 @ 2 2
4 4 3 3
SM070002N00
1 1 2 2
OCF1210900YZF_4P
R283
1 2 2M_CAM_DA1
<6> 2M_CAM_DA1_R
0_0201_5%
R425
1 2 2M_CAM_DA2#
<6> 2M_CAM_DA2#_R
0_0201_5%
A A
L34 @
4 4 3 3
SM070002N00
1 1 2 2
OCF1210900YZF_4P
R386
1 2 2M_CAM_DA2
<6> 2M_CAM_DA2_R Security Classification Compal Secret Data Compal Electronics, Inc.
0_0201_5% 2011/06/20 2012/06/20 Title
Issued Date Deciphered Date
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
12/16 Modify R454 from 3G@ to LTE@ to meet SPEC.

8/23 Modify for Leakage issue.
+VDD_1V8_BB_TEGRA +UIM_PWR
UIM_DATA
UIM_RST
SIM_DET
UIM_CLK
2
2
R285 R454
2
100K_0201_5% 15K_0201_5%
D D
D14 @ D15 @
3G@ LTE@ TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 Q15
1
1
AO3413_SOT23-3
D
+UIM_PWR_R 3 1 +UIM_PWR
3G@
1
SIM_DET UIM_DATA
SCA00001W00 SCA00001W00
G
2
T30 internal PU , reserve V_MINCARD_3V3
2
R287
JSIM1 100K_0201_5%
4 1 +UIM_PWR 3G@
GND VCC UIM_RST
5 2
1
UIM_DATA VPP RST UIM_CLK
6 I/O CLK 3
7 R286 3G@
<7> SIM_DET DET
1 2
8 47K_0201_1%
D+
1 1 9 D- 1 1 1 1 1
3G@ C285 3G@ C297 10 3G@ C287 3G@ C286
10P_0201_50V8J 10P_0201_50V8J GND 39P_0201_50V8J 10P_0201_50V8J @ C288 C289 3G@ C290 3G@
GND 11
1U_0402_6.3V4Z 0.1U_0201_10V6K 0.047U_0201_10V6K
D
1
2 2 2 2 2 2 R76 3G@ 2
SIM_DET 1 2 2 Q21
1 S 3G@
3
TAITW_PMPAT7-08GLBS1N14H0 10K_0201_5%
CONN@ C301 3G@
1U_0402_6.3V4Z
SP07000NX00 2
Detect pin
C
Normal : short GND
Insert Card : Open SIM CARD C
SGA00006500
V_MINCARD_3V3 V_MINCARD_3V3 V_MINCARD_3V3 V_MINCARD_3V3
V_MINCARD_3V3
1 1 1 1
+ C296 3G@ + C305 3G@ + C307 3G@ + C306 3G@
0.1U_0201_10V6K 2200P_0201_16V7K 100U_A_6.3VM_R70M 100U_A_6.3VM_R70M 100U_A_6.3VM_R70M 100U_A_6.3VM_R70M
2 1 1 2
1
2 2 2 2
C293 C292 C295 C291 C294 10/04 Modify R55 from 2.2K to 1K.
3G@ 3G@ 3G@ @ 3G@
2
1 2 2 1
10U_0402_6.3V6M 0.01U_0201_16V7 22P_0201_25V8 8/23 Add for Discharge V_MINCARD_3V3
8/25 Modify part form SB00000EO10 to SB00000IV00
change Cap value to 100U +3VS V_MINCARD_3V3
1
R80 R55
100K_0201_5% 1K_0201_1%
3G@ 3G@
2
Q45 3G@
B V_MINCARD_3V3 B
5 G1 S1 4
V_MINCARD_3V3 3
D1
D2 6
V_MINCARD_3V3 2 1
<7,30> EN_3V3_MODEM G2 S2
1
DMN2004DWK-7_SOT363-6
1
R288 @
100K_0201_5% R291 R81
100K_0201_5% 1M_0201_1%
2
T30 internal PU , reserve C298 3G@ @ 3G@

22P_0201_25V8
2
JMIN1
1 2 2 1 3G_DISABLE#
<4> 3G_WAKE# 1 2
3 3 4 4
5 5 6 6 need check module internal PU or not , All vender.
7 7 8 8 +UIM_PWR_R
9 10 UIM_DATA
9 10 UIM_CLK
11 11 12 12
13 14 UIM_RST
13 14
15 15 16 16
17 17 18 18
19 19 20 20 3G_DISABLE# <4>
21 22 @
21 22 R292
23 23 24 24
25 26 USB2_N2_COMM 1 2
25 26 0_0402_5% 3G_USB_DN <6>
27 27 28 28
29 29 30 30
31 32 WCM-2012-900T_4P
31 32
33 33 34 34 2 2 1 1
35 35 36 36
37 38 3G@
37 38
V_MINCARD_3V3 39 39 40 40 3 3 4 4
41 41 42 42
43 44 L29
43 44
45 45 46 46
47 48 USB2_P2_COMM 1 2
47 48 0_0402_5% 3G_USB_DP <6>
49 49 50 50
A LTE_GPS_RESET 51 52 A
51 52 R295
53 GND GND 54
@
ACES_50709-0524W-001
D
CONN@ 08/05 Change L29 to mount
1
R92 LTE@ LTE@

2 1 2
<7,21> GPS_RESET# G Q49 LTCX003HC00
0_0201_5% S S TR DMN3150LW-7 1N SOT-323-3
WWAN Card
3
Vth=1.4V
Add R92 and Q49 to GPS_RESET of LTE module . THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
8/25 Modify R451&R455 from 47K 1% to 4.7K 5%

+VDD_3V3_LCD_TEGRA +VDD_3V3_LCD_TEGRA +VDDIO_HDMI
C299 2 1
0.1U_0201_10V6K
2
C300 2 1
R449 R450
D
R451 R455 4.7K_0201_5% 4.7K_0201_5% Reserved U40 0.1U_0201_10V6K D
4.7K_0402_5% 4.7K_0402_5% +5VS 6 1 +VDDIO_HDMI
IN OUT
2
2
1
G
5 IN GND 2
R420 0_0402_5% 4 3 1 R323 2

<4> EN_HDMI_5V0 EN DIS
1 6 DDC_SCL 1 @ 2 HDMI_DDC_SCL 0_0201_5%
<4> DDC_SCL_R 3.3V Vth=2.0
D
S
7
5
TMLPAD
G
G5287RR1U_TDFN6_1P6X1P6
Q43A R426 0_0402_5%
4 3 2N7002KDWH 2N SOT363-6 DDC_SDA 1 @ 2 HDMI_DDC_SDA
<4> DDC_SDA_R
D
S
1 1
Q43B
08/04 Change U40 to SA000055200 (TDFN6)
C400 C401
2N7002KDWH 2N SOT363-6 4.7P_0402_50V8C 4.7P_0402_50V8C
2 2
07/28 Change C400,C401 to SE07147AC80
JHDMI1
+3VS +VDD_3V3_LCD_TEGRA
HDMI_DET 1 HP_DET
2 Utility
HDMI_TXD2P_R 3
12/2 Modify Q1 from SB503010010 to SB503010020 for HF request. 4
D2+
D2_Shield
HDMI_TXD2N_R 5
HDMI_TXD1P_R D2-
6 D1+
1
1
7 D1_Shield
R24 R436 HDMI_TXD1N_R 8 20
32.4K_0402_1% 1M_0201_1% HDMI_TXD0P_R D1- GND0
9 D0+ GND1 21
1
C 10 D0_Shield GND2 22 C
2
2
G
Q1 HDMI_TXD0N_R
G
11 23
2
2
R25 FDV301N_G 1N SOT23-3 HDMI_TXCP_R D0- GND3
12 CK+
162K_0402_1% 3 1 HDMI_DET 1 3 HDMI_DET_T30S <4> 13 CK_Shield
2
HDMI_TXCN_R
S
SC100000S00 14
S
2
D1 HDMI_CEC_CON CK-
15 CEC
RB751S40T1_SOD523-2~D Q39 16 DDC/CEC_GND
1
HDMI_DDC_SCL 17 SCL
1
D2 @ C67 R448 SSM3K7002FU_SC70-3 HDMI_DDC_SDA 18
1
HDMI_CEC_CON 1000P_0201_16V7K 100K_0201_5% SDA

<7> HDMI_CEC 2 1 +VDDIO_HDMI 19 +5V
2
RB751S40T1_SOD523-2~D BELLW_80082-5021
2
CONN@
SC100000S00
DC232001M10
HDMI Type D Connector
08/05 Change L30-L33 to SM070002N00
1 R310 2 HDMI_TXD0P_R 1 R311 2 HDMI_TXD1P_R

<4> HDMI_TXD0P <4> HDMI_TXD1P
@ 0_0201_5% @ 0_0201_5%
L30 L31
4 4 3 3 4 4 3 3
SM070002N00 SM070002N00
1 1 2 2 1 1 2 2
OCF1210900YZF_4P OCF1210900YZF_4P
B B
1 R312 2 HDMI_TXD0N_R 1 R313 2 HDMI_TXD1N_R

<4> HDMI_TXD0N <4> HDMI_TXD1N
@ 0_0201_5% @ 0_0201_5%
1 R314 2 HDMI_TXCP_R 1 R315 2 HDMI_TXD2P_R

<4> HDMI_TXCP <4> HDMI_TXD2P
@ @ 0_0201_5%
0_0201_5%
L32 L33
4 4 3 3 4 4 3 3
SM070002N00 SM070002N00
1 1 2 2 1 1 2 2
OCF1210900YZF_4P OCF1210900YZF_4P
1 R317 2 HDMI_TXCN_R 1 R318 2 HDMI_TXD2N_R

<4> HDMI_TXCN <4> HDMI_TXD2N
@ 0_0201_5% @ 0_0201_5%
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
08/09 Add C381,C382 for VBUS_USB +3VS

33P_0201_50V8J 2 1 C383 C382 1 2 33P_0201_50V8J
0.1U_0201_10V6K 2 1 C377 C381 1 2 0.1U_0201_10V6K VDD_1V8_PMU_VRTC VDD_1V8_PMU_VRTC
1
JDOCK1
1A (Max) 1 2 1A (Max) R316
+5VS 1 2 VBUS_USB
08/09 Add C377,C383 for +5VS 3 3 4 4 0_0201_5%
1
5 5 6 6
1
7 8 08/09 Add C385,C386 for DC_IN R433
2
7 8
<6> USB1_ID 9 9 10 10 1.5 A
DC_IN 08/12 Delete C385 R432 56K_0201_1%
<6,27> ENABLE_USB_HOST 11 12 100K_0201_5% +3VS_VB
11 12 C386
13 14 1 2 33P_0201_50V8J
2
13 14
15 16 HDRST <32>
2
<6> USB_HOST_DN 15 16
<6> USB_HOST_DP 17 17 18 18 D 2
1
19 19 20 20
21 22 LINE_OUT_DET# <7> <7> HOT_RST# 2 Q4 C303
<6> USB1_DN 21 22 DEBUG_UART1_RX G BSS138W-7-F_SOT323-3
<6> USB1_DP 23 23 24 24 DEBUG_UART1_RX <7> 0.1U_0201_10V6K
S 1
25 26
3
D 25 26 D
<6> COMPASS_DRDY 27 27 28 28 for IR function
<7,16> GEN1_I2C_SCL GEN1_I2C_SCL 29 30
GEN1_I2C_SDA 29 30
<7,16> GEN1_I2C_SDA 31 31 32 32
33 34 VDD_1V8_PMU_VRTC +VDD_1V8_CAM_TEGRA
+VDD_1V8_SENSOR 33 34 LINE_DOCK_L <15>
HOT_RST# 35 36 LINEGND <15>
35 36 VB_N
<27> DOCK_DET_R# 37 37 38 38 LINE_DOCK_R <15>
+VDD_3V3_SENSOR 39 39 40 40 02/17 Change to 0201 shortpad
1
<4> POUT_3G_1 41 41 42 42 AMIC_R+ <15>
43 43 44 44 AMIC_R- <15> R429 R431
45 GND GND 46 100K_0201_5% 100K_0201_5% D
1
47 48 02/22 Change to 0201 shortpad R320 @ 0_0201_5%
GND GND Q20 2 2 1 VIB_EN_T30S <4>
2
PANAS_AXK8L44124BG BSS138W-7-F_SOT323-3 G
D21
CONN@ R324 0_0201_5% S
Docking / Board
1
LTCX003I300 DOCK_DET_R# 1 2 1 2 DOCK_DET# <6>
R321
2 RB751V-40_SOD323-2 100K_0201_5%
27P_0201_25V8 2 1 C376 08/09 Add C375,C376 for B+
08/13 Add EN_P_SENSOR for P-sensor PWR Switch C146
VIBRATOR
2
0.1U_0201_10V6K 2 1 C375 4.7U_0402_6.3V6M
JFUN1 +VDD_1V8_AUDIO 1
1
B+ <27> O_LED_CTL 2
1
2
1
<27> W_LED_CTL 3 3 SP01000QQ00 10/19 Add R324 and C146 to Dock_DET# for debouncing.
4 R9 10/19 Change power domain from +VDD_1V8_CAM_TEGRA to VDD_1V8_PMU_VRTC
+3VS_VB VB_N 5
4
100K_0201_5% 10/31 Modify C146 from 0.1U to 4.7U for Acer HW request. 0208 Add R327 and R328 to HP RIGHT& LEFT to reduce cost.
EN_P_SENSOR 5
<4> EN_P_SENSOR 6 6 11/7 Add D21 R431 to DOCK_DET_R# leakage issue. 0208 Unmont U3 for cost down.
7 R28 0315 Mount U3 and unmount R327&R328 for Debug.
2
7
remove POUT_WIFI net on JFUN1 T19
@ PAD
T20
@ PAD 8 8
HP_IN 1 2 HP_DET# <6> 0328 unmount U3 and mount R327&R328 for cost down.
<4,7> VOL_UP# 9 1K_0201_1% 2
9
<4,7> VOL_DOWN# 10 10
+VDD_3V3_SENSOR 11 C9
11 0.1U_0201_10V6K
<4> POUT_3G 12 12 1 +VDD_3V3_GMI_TEGRA
13 13
14 +VDD_1V8_BB_TEGRA HP_R 1 2 HP_RIGHT
<7> ONKEY# 14
15 R327 0_0201_5%
15
<7> SC_LOCK# 16 16
C +VDD_1V8_SENSOR 17 HP_L 1 2 HP_LEFT C
17 R328 0_0201_5%
<6> LIGHT_INT 18
19
18 Flash LED / Board 1
19
1
GEN1_I2C_SDA 20 JLED1 C397
GEN1_I2C_SCL 20 R234 0.1U_0201_10V6K
21 21 <35> LED+ 1 1
For debug port leakage 2
22 22 <35> LED- 2 2 100K_0201_5%
HP_IN 23 23
24
2
HP_LEFT 24 D19 U3 @
25 25
26 3 RB751V-40_SOD323-2 A2 A1
26 GND1 V+ NO2 DEBUG_UART1_TX <7>
3
HP_RIGHT 27 4 DEBUG_UART1_RX 2 1 A3 B1 HP_RIGHT
27 GND2 <7> DEBUG_UART1_RX NO1 COM2
28 D16 HP_LEFT B3 C1
<15> COM_MIC 28 COM1 NC2 HP_R <15>
29 ACES_50281-0020N-001 C3 D1
29 <15> HP_L NC1 IN2
30 CONN@ D3 D2
<15> EAR_JACK_GND 30 <7> UART_SW IN1 GND
31 G1 close to JLED1 SP02000S000
32 TS5A22362YZPR_DSBGA10
1
G2 TVNST52302AB0_SOT523-3
ACES_88196-3041
SCA00001W00
1
CONN@
SA00005AE00
HPGND <15>
1
R347
9/15 Add D16 to Compal ESD request. 9/29 Modify U3 from TS5A22364 to TS5A22362.
1
0_0201_5% R210
@
Function / Board
100K_0201_5%
SA00004ON00------>SA00005AE00
2
R345 @
0_0201_5%
HP Switch
2
2
10/13 Modify R345 from mount to @ for Acer AUDIO request.

02/02 Add AND gate/RC delay schematics for ONKEY# function.
Micro SD +VDD_3V_SD
+VDD_3V_SD
02/17 Add C402 to B+.
B
reference NV schematic 02/21 Change U57 from AND gate to Rest IC. B
03/28 Change C327 from 22nF to 18nF for Acer request.
@
1
47K_0402_1%
2
R337
C311
Remove R332 0.01U_0201_16V7 C312
B+ B+
1U_0402_6.3V4Z
1
2
2
2
reference PBJ20
R273
reserve for 33 0hm 100K_0201_5%
JMSD1 U57
1
R343 2 1 0_0201_5% SDMMC_DAT2_R 1 1 6 R403 0_0201_5%
<5> SDMMC_DAT2 R342 2 SDMMC_DAT3_R DAT2 MRDLY VCC
<5> SDMMC_DAT3 1 0_0201_5% 2 DAT3 2 GND RESET 5 1 2 A_ONKEY# <32>
R341 2 1 0_0201_5% SDMMC_CMD_R 3 3 4 ONKEY#
<5> SDMMC_CMD CMD CD MR
Detect pin
0.018U_0402_25V7K
4 VDD G1 11
R368 2 1 0_0201_5% SDMMC_CLK_R G677L308A31U_ADFN6_1P5x1P5
Normal : Open <5> SDMMC_CLK 5
6
CLK G2 12
13
1 1
1 R400 2
1
Insert Card : Short GND R340 2 1 0_0201_5% SDMMC_DAT0_R 7
Vss G3
14 @ 0_0201_5%
<5> SDMMC_DAT0 R339 2 SDMMC_DAT1_R DAT0 G4
<5> SDMMC_DAT1 1 0_0201_5% 8 DAT1 G5 15 C392 C404 C402 @
2 2 0.1U_0201_10V6K 0.1U_0201_10V6K
<7> SD_DET# 9 DETECT1 2
2 1 10 DETECT2
R344
1 0_0201_5% PROCO_879S-R010-00A0
C325 CONN@
10P_0201_50V8J
reference Acer schematic 2
11/28 Change JMSD1 form SP07000GQ00 to SP07000TV00
SDMMC_CLK_R
SDMMC_DAT0_R
SDMMC_DAT1_R
SDMMC_DAT2_R
A SDMMC_DAT3_R A
SDMMC_CMD_R
1 1 1 1 1 1
C367 C368 C369 C370 C371 C310
10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J
2 2 2 2 2 2

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
+2V8_GPS
9/02 Modify C315 from GPS@ to @ for RF team request.

C313
GPS@
1
9/10 Modify C315 from 1.8P to 2.2P for RF team request. L35 1 2 BLM15AG601SN1D_2P 1 2
1
C322 L39 9/14 Modify L38 from 6.2NH to 7.5P for RF team request.
GPS@ GPS@ 2.2U_0402_6.3V6M
0.1U_0201_10V6K 2 47NH_LQG15HN47NJ02D_5% 12/7 Modify L38 from 7.5P to 0 ohm for RF team request. GPS@
Antenna 12/7 Modify C315 from 2.2P to 5.1nH for RF team request.U47
H10
J10
L37 GPS@
K7
K6
2
GPSANT SAFFB1G58KA0F0AR14_5P
2 C314 GPS@ L38 GPS@
GPS_VDDLNA
Ground
GPS_VDDIF
VDD1P2_GRF
GPS_VDDPL
3 1 GPS_ANT1 1 2 GPS_ANT2 1 4 GPS_ANT3 1 2 GPS_ANT4 K9
Input Output GPS_RFIP
4
22P_0402_50V8J 1 0_0201_5%
D D
I-PEX_20429-001E 2 2
GND
GND
GND
CONN@ C315
D9 @ 5.1NH_0.3NH_LQG15HN5N1S02D D17 @
SP060004L00 1P_0402_50V NPO 2 GPS@ 1P_0402_50V NPO J8
RF
2
3
5
1 1 GPS_VSSIF
07/27 Change GPSANT from J9 GPS_VSSPLL GPS_AUXOP J7
LTCX003HH00 to SP060004L00 K8
K10
GPS_VSSLNA
H8
GPS_VSSLNA GPS_AUXON
close to GPSANT E10 GND_IFP

+GPS_AUX_OUT +1V8_GPS
A4 GPS_CAL CLK IF
GPS_CLK_26M_R G10 TCXO
1 CAL_REQ B7
1 C316 remove reserve 32K from T30S GPS_CLK_32K_R K2 LPO_IN
0.01U_0201_16V7 H9
C379 GPS@ NC
F10 NC NC F9
0.1U_0201_10V6K 2
GPS@ 2
F8 NC
GPS@
6
4
X2 X3 G9
GPS_CLK_26M 1 NC
4 2 GPS_CLK_26M_R GPS@
VCC
VDD
OUTPUT R352 GPS@ 0_0402_5%
1 OE Clock Output 3 GPS_CLK_32K R351 1 GPS@ 2 0_0402_5% GPS_CLK_32K_R
SYS IF AUX_HI K4
GPS@
2 H6 +GPS_AUX_OUT C318 2 1 0.22U_0201_6.3V6M
ENABLE/DISABLE 26MHZ_10PF_TX5651 VDD_AUX_O
5 NC VDD_AUX_IN H7 +3V3_GPS
1
GND
GND
NC
HOST_REQ A6
A8 GPS_SYNC/PPS_OUT
02/17 Change to 0201 shortpad B6
3
2
32.768KHZ_15PF_KK3270032 LNA_EN
A7 IFVALID
C C
R383 1 @ 2 0_0201_5% GPS_RESET#_R A5 A3
<7,18> GPS_RESET# RST_N C_GPIO_6
C_GPIO_7 B5
R416 1 @ 2 0_0201_5% GPS_PWRON_R J4
<7> GPS_PWRON REGPU
D_GPIO_5 A2
H2 TM1 D_GPIO_6 H1 C317
K1 TM2
GPS_PWRON_R B3 J6 GPS_REF_CAP 1 2
TM3 REF_CAP
UART/I2C IF 0.01U_0201_16V7
1
R348 GPS@ D2 GPS@
C_GPIO_2
100K_0201_5% C1 C_GPIO_3
E1 R417 1 2 0_0201_5%
SCL2/UART_TX GPS_UART_RXD <7>
SB00000SM00 D1 R421 1 2 0_0201_5%
GPS_UART_TXD <7>
2
+1V8_GPS SDA2/UART_RX R434 0_0201_5%
UART_nRTS B2 1 2 GPS_UART_CTS# <7>
VDD_1V8_GEN Q28 Acer request UART_nCTS A1 R435 1 2 0_0201_5%
GPS_UART_RTS# <7>
4 3
MEMORY
2 F2 NC NC E5
1
5 1 2 1 F7 NC NC B1
1
C323 H3 E6
GPS@ R303 C332 C326 C353 C324 NC NC
6 H4 D4
2
1U_0402_6.3V4Z 1M_0402_1% 0.1U_0201_10V6K 4.7U_0402_6.3V6M NC NC

1 1U_0402_6.3V4Z 68P_0201_25V8 J2 C4
2
GPS@ GPS@ 2 GPS@ 1 2 GPS@ NC NC

GPS@ G8 NC NC E3
FDG6331L_SC70-6 G7 F6 9/25 Modify R346 from @ to mount for leakage issue.
2
NC NC
GPS@ J1 NC NC E7
G6 NC NC C2
G4 D10 +1V8_GPS
<7> EN_VDD_GPS Vth = 1.5 NC NC
G1 NC NC B4
1
F1 NC NC A9
1.8V G5 A10
NC NC
1
R304 C10 B9
1M_0402_5% NC NC R346
C8 NC NC C9
D5 B10
2
B NC NC 100K_0201_5% B
10/06 Modify R304 from @ to mount. D8 F5
2
NC NC
D6 NC NC E4
D9 E2 GPS_UART_RXD
NC NC
+3V3_GPS J5 VDD_BAT
R428 1 GPS@ 2 VDD_PRE H5 E8
VDD_PRE NC
0_0402_5%
GPS_VDDC E9 VDDIFP
PWR AVSS J3
G2 VDDC AVSS K3
C7 VDDC
C3 VDDC
K5 VDD1P2_CORE VSSC G3
VSSC F4
+1V8_GPS C6 VDDIO VSSC B8
SB00000SM00 +3V3_GPS
D7 VDDIO VSSC C5
F3 VDDIO VSSC D3
+3VS Q29
4 3 BCM47511IFBG_FBGA100
2 GPS@
5 SA00004YJ00
1
+3V3_GPS
1 2
1
C330 R305 6 U50

1U_0402_6.3V4Z 1M_0402_1% 1 C331 C333 C347
2
GPS@ GPS@ 1U_0402_6.3V4Z 2.2U_0402_6.3V6M 68P_0201_25V8 1

2
FDG6331L_SC70-6 GPS@ 2 GPS@ 1 VIN

GPS@
2
GPS@ 1 VOUT 5 +2V8_GPS

C329 2
VDD_PRE GPS_VDDC GND C335
1
EN_VDD_GPS 1U_0402_6.3V4Z 4 GPS@
GPS@ 2 GPS_PWRON_R NC
1 1 3 EN
A 1.8V Vth = 1.5 2.2U_0402_6.3V6M A
C319 C320 Vth=1.6V 2
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M APL5603-28BI-TRG_SOT23-5
2 2 GPS@
@ GPS@
SA00004BW00
For Antenna circuit

2011/06/20 2012/06/20 Title
GPS POWER SOURCE Issued Date Deciphered Date
4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
+3VS
SB00000SM00 +3VS_WIFI
Q31
4 3
dual-Band wifi RF matching , Reserve " 2 Pi " filter
2
9/10 Modify C136 from 100P to 1P for RF request.
1
5 1 1 2 WIFANT
1
C337 C342
2
Ground
1U_0402_6.3V4Z R308 6 C339 C341 C340
2 2.4RF_IN_L R375 1 WIFI@2 0_0402_5% 2.4RF_IN_R R387 1 WIFI@2 0_0402_5% 2.4RF_IN 1 3
WIFI@ 1M_0402_1% 1 1U_0402_6.3V4Z 4.7U_0402_6.3V6M 0.1U_0201_10V6K 68P_0201_25V8
2
WIFI@ WIFI@ 2 WIFI@ 2 WIFI@ 1 4
WIFI@ 2 2 2
FDG6331L_SC70-6
I-PEX_20429-001E
2
WIFI@ C136 @ C137 @ C138 @ CONN@
1P_0402_50V NPO 100P_0402_50V8J 100P_0402_50V8J
D
1 1 1 SP060004L00 D
<4> EN_WIFI_VDD Vth = 1.5 07/27 Change WIFANT from
1
LTCX003HH00 to SP060004L00
R307
1M_0402_5%
@
2
SB00000SM00 AH662 use 1U, AH663 use 0.1U
VDD_1V8_GEN +1.8VS_WIFI
Q32 8/23 Add for AH663.
+SR_PA_OUT +VDD_WL_PA 9/21 Add D10 to Compal ESD request.
4 3 2.4RF_IN
C356
2
2 AH663@
1
C356 C359
5 2
1
C348 1U_0402_6.3V4Z 1U_0402_6.3V4Z

SE070104Z80
1
1 1 2
1
1U_0402_6.3V4Z R319 6 NH660@ WIFI@ D10 @
2
WIFI@ 1M_0402_1% 1 C349 C354 C352 C351 1P_0402_50V NPO

WIFI@ 0.1U_0201_10V6K 4.7U_0402_6.3V6M 0.1U 16V V4Z 1
1U_0402_6.3V4Z 68P_0201_25V8
2
FDG6331L_SC70-6 WIFI@ 2 WIFI@ 2 WIFI@ 1
WIFI@
close to H2 close to G9
2
WIFI@ close to WIFANT
EN_WIFI_VDD
Vth = 1.5 +SR_PA_OUT +VDD_LN
+3VS +3VS_WIFI +3VS_WIFI +VDD_WL_PA

10/19 Add for Discharge +3VS_WIFI reserve
1
1
C R361 1 @ C
R93 R94 2 0_0402_5%
100K_0201_5% 1K_0201_1% +VDD_CORE
B+
2
2
Q47 +VDD1P4_WIFI
Q37
5 G1 S1 4 1
3 VDD
D1 VOUT 5
D2 6 2
EN_WIFI_VDD 1 1 GND
2 G2 S2 1 4
+1.8VS_WIFI VFB
2
C343 C350 3 1 1
DMN2004DWK-7_SOT363-6 4.7U_0402_6.3V6M 0.1U_0201_10V6K CE R356
WIFI@ 2 WIFI@ 2 RP111N331D-TR-FE_SOT23-5 0_0201_5% C378 C346
WIFI@ WIFI@
WIFI@ 2 2 WIFI@
1
0.1U_0201_10V6K
4.7U_0402_6.3V6M
+CBUCK_OUT
+3VS_WIFI
+VDD_WL_PA
+VDD_WL_PA
+VDD_LN
1
FM power <4> EN_WIFI_VDD R456 @
1
15K_0402_5%
R389
G9
2
H9
H2
C1
C2
D1
H1
A2
A3
B9
B1
B4
B3
E2
J3
U53 1M_0201_1%
+1.8VS_WIFI WIFI@
VDD_WL_PA_A_MODE
VDD_CORE
SR_PA_OUT
VDDIO_RF
VDD_BT_PA
VDD_WL_PA
CBUCK_OUT
VOUT_2P5_OUT
VDD_LN_OUT
VIN_LDO
VDD1P2_CLDO_OUT
VDDIO
VBAT_IN
VOUT_2P5_IN
VDD_LN_IN
2
FM_AUDIO_L A8
WFMMC_CMD_R R367 1 @ 2 100K_0201_5% A7
FM_AUDIO_R
F1,F2,F3,G2,G3 internal weak pull up resister to VDDIO
R272 A6
WFMMC_CLK_R ANT_FM_TX
<5> WFMMC_CLK 1 2 G1 SDIO_CLK_SPI_CLK ANT_FM_RX A5
R373 1 WIFI@ 2 0_0201_5% WFMMC_CMD_R G3
B <5> WFMMC_CMD SDIO_CMD_SPI_DI B
1 0_0201_5% R374 1 WIFI@ 2 0_0201_5% WFMMC_DAT0_R F2 J7 2.4RF_IN_L
<5> WFMMC_DAT0 SDIO_DATA0_SPI_DO ANT_2G4_5G
1
R376 1 WIFI@ 2 0_0201_5% WFMMC_DAT1_R F1

<5> WFMMC_DAT1 SDIO_DATA1_SPI_IRQ
@ C387 @ C388 R377 1 WIFI@ 2 0_0201_5% WFMMC_DAT2_R G2 H4 +1.8VS_WIFI
<5> WFMMC_DAT2 SDIO_DATA2_SPI_NC ANT_MAIN_EN
22P_0201_25V8 33P_0201_50V8J R378 1 WIFI@ 2 0_0201_5% WFMMC_DAT3_R F3 H6
<5> WFMMC_DAT3
2
2 SDIO_DATA3_SPI_CS ANT_AUX_EN
3/28 Change R366 from unmount to mount.
BT_I2S_DI D7
1
BT_I2S_DO D5
08/09 Add C387,C388,R272 for WFMMC_CLK E6 WL_GPIO_1 BT_I2S_WS C7 R366
08/25 Modify C387&C388 from mount to unmount E4 WL_GPIO_2 BT_I2S_CLK B6 100K_0201_5%
D6
2
WL_GPIO_5
C6 WL_GPIO_6 BT_PCM_SYNC G4 BT_PCM_SYNC <7>
R382 0_0201_5% F5 BT_UART_RXD
BT_PCM_CLK BT_PCM_CLK <7>
1 @ 2 WF_RST#_R D2 F4
<7> WF_RST# WL_SHUTDOWN#_RST# BT_PCM_IN BT_PCM_OUT <7>
TP36 F6 G5
<7> WF_WAKE# WL_HOST_WAKE BT_PCM_OUT BT_PCM_IN <7>
TP34 E3 02/17 Change to 0201 shortpad
TP35 WL_UART_TX
G7 WL_UART_RX BT_DEVICE_WAKE C8 @ PAD T11 BT_WAKEUP <7>
C345 WIFI@ 0.01U_0201_16V7 BT_HOST_WAKE B7 @ PAD T12 BT_IRQ# <7>
1 2 C3 R381 0_0201_5%
+SR_PA_OUT BT_SHUTDOWN# @ PAD T13 BT_PD# <7>
H3 C4 1 @ 2
HSIC_DATA BT_RST# BT_RST# <7>
C344 WIFI@ 4.7U_0402_6.3V6M J2 HSIC_STROBE
1 2
E7 R365 1 WIFI@ 2 0_0201_5%
BT_UART_RTS# BT_UART_CTS# <7>
F7 R370 1 WIFI@ 2 0_0201_5%
BT_UART_CTS# BT_UART_RTS# <7>
R384 1 WIFI@ 2 0_0402_5% RTC_32K_WIFI D3
<7> CLK_32K_OUT RTC_CLK
F8 R371 1 WIFI@ 2 0_0201_5%
BT_UART_TXD BT_UART_RXD <7>
E8 R369 1 WIFI@ 2 0_0201_5%
BT_UART_RXD BT_UART_TXD <7>
H8 NC
8/22 Change BOM structure
C355 WIFI@ D9 NC
+VDD_LN 1 2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U53
4.7U_0402_6.3V6M
8/22 Change BOM structure NH660@
A1
A4
A9
B2
B5
B8
C5
C9
D4
D8
E1
E5
E9
F9
G6
G8
H5
H7
J1
J4
J5
J6
J8
J9
A10
C10
E10
G10
J10
A C358 WIFI@ 0.01U_0201_16V7

AH663@ AW-AH663_86P PK29S003400 A
+VDD_CORE 1 2
L40 WIFI@
PK29S003200
+VDD1P4_WIFI 1 2 +CBUCK_OUT
Footprint use AH662 co-lay
C357 WIFI@ 4.7U_0402_6.3V6M
1 2 C336 WIFI@ 2.2UH_VLS252012T-2R2M1R3_1.8A_20%
2 1
10U_0402_6.3V6M

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
R395 1 2 0_0201_5% 10mA R391 1 2 0_0201_5% 110mA

From PMU VDD_1V8_GEN +VDD_1V8_SDMMC3_TEGRA +3VS +VDD_3V3_GMI_TEGRA
From PMU VDD_PMU_LDO3 R442 1 2 0_0402_5% +VDD_3V3_SDMMC1_TEGRA
10mA
R397 1 2 0_0201_5% 10mA R396 1 2 0_0201_5% 130mA
+VDD_1V8_AUDIO_TEGRA +AVDD_3V3_USB_TEGRA
R412 1 2 0_0402_5% 30mA
VDD_PMU_LDO8 +VDD_1V0_DDR_HS_TEGRA
R399 1 2 0_0201_5% 10mA R419 1 2 0_0201_5% 50mA
+AVDD_1V8_USB_PLL_TEGRA +VDD_3V3_DDR_RX_TEGRA
VDD_PMU_LDO6 R410 1 2 0_0402_5% 56mA
+AVDD_1V2_DSI_CSI_TEGRA
R401 1 2 0_0201_5% 10mA R418 1 2 0_0201_5% +VDD_3V3_LCD_TEGRA 10mA
+VDD_1V8_CAM_TEGRA
VDD_PMU_LDO7 R411 1 2 0_0402_5% 54mA
+AVDD_1V1_PLL_TEGRA
R404 1 2 0_0201_5% 10mA
+VDD_1V8_BB_TEGRA
R407 1 2 0_0402_5% 20mA
VDD_PMU_LDO4 +VDD_1V2_RTC_TEGRA
R406 1 2 0_0201_5% 10mA
+VDD_1V8_SYS_TEGRA
R422 1 @ 2 0_0402_5% 200mA
VDD_PMU_LDO1 +VDD_2V85_EMMC
R398 1 2 0_0402_5% 20mA
+VDD_1V8_DDR_MEM
VDD_PMU_LDO5 R408 1 2 0_0402_5% 135mA
+VDD_VCM_3V3
R101 1 2 0_0402_5% 200mA
+VDDIO_1V8_EMMC
R441 1 2 0_0402_5% 45mA
D VDD_PMU_LDO2 +VDD_3V_SD D
R157 1 2 0_0402_5% 33mA
+VDD_1V8_AUDIO
VDD_1V2_MEM R444 1 2 0_0402_5% 475mA
+VDD_1V2_DDR_MEM
R390 1 2 0_0201_5% 10mA
+VDD_1V8_SDMMC4_TEGRA
R402 1 2 0_0201_5% 10mA
+VDD_1V8_UART_TEGRA 12/08 Add U51, C365 , C385 and R437 for EMMC drop issue.
12/16 Modify U51, C365 , C385 and R437 from @ to mount.
Must change to correct symbol&footprint
+3VS
+VDD_2V85_EMMC
U51
1 VIN R437
1 VOUT 5 1 2
C385 2
2.2U_0402_6.3V6M GND 0_0402_5%
2
NC 4
2 VDD_PMU_LDO1 C365
3 EN
1U_0402_6.3V4Z
1
G9001-300TO1U TSOT-23 5P LDO H1 H2 H5 H6
H_2P3 H_2P3 H_2P3 H_2P3
SA00005II00
H_2P3 *6
1
@ @ @ @
Q26 close to Camera Conn.
H8
VDD_1V8_GEN +VDD_CAM_1V8
H_2P0N *1
H_2P0N
Q26
ME2301A-G_SOT23-3
C
10/04 Add R19 and Q46 to Discharge +VDD_CAM_1V8. @
C
1
S
3 1
Q33 close to T30S
FD1 FD2 FD3 FD4
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
G
1
2
SB00000JL00 C33 +3VS +VDD_3V3_FUSE_TEGRA

1U_0402_6.3V4Z Q33
ME2301A-G_SOT23-3 @ @ @ @
1
2 R19
2.2K_0201_1%
D
3 1
2
D
12/19 Del all CLIP for ME request.
1
G
1
9/2 Add CLP22~CLP27
2
2
Q46 B+ SB00000JL00 C159
G 1U_0402_6.3V4Z
S
S TR DMN3150LW-7 1N SOT-323-3 9/2 Add CLP28,CLP29
3
2
11/8 Del CLP22~CLP27 for ME request
1
R300
2 1 R326
<7> EN_CAM_1V8#
100K_0201_5% 1
200K _0201_1%
TOP Clip type conn BOTTOM
R325
2
C384 2 1
0.1U_0201_10V6K
2 100K_0201_5%
3 1
C389
Q25B 0.1U_0201_10V6K
DMN2004DWK-7_SOT363-6 2
<4> EN_T30S_FUSE_3V3 5
3.3V
4
SB00000IV00
9/29 Modify Q25 from 2N7002KDWH to DMN2004DWK-7

B B
VDD_1V8_GEN +VDD_1V8_SENSOR
Q35
ME2301A-G_SOT23-3
S
3 1
G
1
2
SB00000JL00 C160
1U_0402_6.3V4Z
9/2 Modify R330 to meet SPEC sequence 2 +3VS +VDD_3V3_SENSOR
Q38
ME2301A-G_SOT23-3
S
R330 3 1
<7> EN_SENSOR_1V8# 2 1
G
1
2
1
B+ SB00000JL00 C163
47K_0201_1% C390 @ 1U_0402_6.3V4Z
0.1U_0201_10V6K 2
1
2
R414
10/07 Modify C390 from mount to @. 200K _0201_1%
R415
2
2 1
100K_0201_5% 1
6
C391
Q25A 0.1U_0201_10V6K
R427 1 @ 2
2 0_0201_5% DMN2004DWK-7_SOT363-6
9/27 Add EN_SENSOR_3V3_2 from U1.AA3 <4> EN_SENSOR_3V3 2
3.3V
A
9/29 Modify R424 from unmout to mount A
1
R424 0_0201_5%
@
9/29 Modify R427 from mout to unmount <7> EN_SENSOR_3V3_2 1 2
1.8V

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
AC Mode
PU7 T30S-R-A1-1.4G
PTPS659110A2ZRCR Core Power
PU1 T30 PWR RAIL VDD_PMU_LDO4 20mA R407_0_0402 +VDD_1V2_RTC_TEGRA
1.0V~1.2V VDD_RTC
VIN ChargerIC PMU IC VDD_1V0_GEN 6100mA
DC_IN VDD_1V8_GEN 0.9V~1.0V VDD_CPU
BQ24171 VDD_1V2_SOC 2500mA
D 1.0V~1.2V VDD_CORE D
+3VS 40mA +VDD_3V3_FUSE_TEGRA

PU2 Q33 3.3V VPP_FUSE
TPS63020DSJR DDR
GPS
VDD_1V2_MEM 475mA
PL3 SYSTEM +3VS 1.2V VDDIO_DDR
Boost-Buck IC Q28
0.37mA +1V8_GPS
1.8V VDD_PMU_LDO8 30mA R412_0_0402 +VDD_1V0_DDR_HS_TEGRA
Batt. Mode 1.05V VDD_DDR_HS
+2V8_GPS
U50 2.8V +3VS 50mA R419_0_0201 +VDD_3V3_DDR_RX_TEGRA
B+
3.3V VDD_DDR_RX
BATT+ Q29
250mA +3V3_GPS
3.3V
LCD
Battery PR19 +3VS 10mA R418_0_0201 +VDD_3V3_LCD_TEGRA
1S2P PU4 3.3V VDDIO_LCD
WIFI/BT
Charge G5910-50RBU_TDFN6 HDMI
800mA +1.8VS_WIFI +3VS 15mA Q2 +AVDD_3V3_HDMI_S
Charge PUMP VDD_5V0_SBY Q32 1.8V 3.3V AVDD_HDMI
Boost IC 80mA L2 AVDD_HDMI_PLL
20mA +3VS_WIFI 3.3V 1.8V AVDD_HDMI_PLL
Q31
SD Card
VDD_PMU_LDO3 10mA R442_0_0402 +VDD_3V3_SDMMC1_TEGRA
3.3V VDDIO_SDMMC1
PU3 WiFi
Touch Panel
TPS61030RSAR 10mA R395_0_0201 +VDD_1V8_SDMMC3_TEGRA
C
1.8V VDDIO_SDMMC3 C
SYSTEM +5VS L14 5V
Buck IC Audio
10mA R397_0_0201 +VDD_1V8_AUDIO_TEGRA
1.8V VDDIO_AUDIO
Camera
VDD_PMU_LDO6 56mA R410_0_0402 +AVDD_1V2_DSI_CSI_TEGRA
PU2 1.2V AVDD_DSI_CSI
3G CARD 10mA R401_0_0201 +VDD_1V8_CAM_TEGRA
TPS63020DSJR 1.8V VDDIO_CAM
BATT+ 2750mA
3G V_MINCARD_3V3 3.3V
USB
Boost-Buck IC +3VS 130mA R396_0_0201 +AVDD_3V3_USB_TEGRA
3.3V AVDD_USB
+3VS 10mA R399_0_0201 +AVDD_1V8_USB_PLL_TEGRA
1.8V AVDD_USB_PLL
PU6
OSC
OZ9979LN-A3-0-TR LVDS Panel L3
10mA AVDD_OSC
20mA 1.8V AVDD_OSC
BACK LIGHT +VDD_LED_BL 12V
Boost IC eMMC
10mA R390_0_0201 +VDD_1V8_SDMMC4_TEGRA
1.8V VDDIO_SDMMC4
PU9 SYSTEM
AMP
TPS61050YZGR LED Board 10mA R406_0_0201 +VDD_1V8_SYS_TEGRA
1.8V VDDIO_SYS
R445_0_0402 LED+ 1500mA
B 5V LED flash B
LED- 3V VDD_PMU_LDO7 54mA R411_0_0402 +AVDD_1V1_PLL_TEGRA

+AMP_VDD 400mA Boost IC 1.1V AVDD_PLL
10mA R404_0_0201 +VDD_1V8_BB_TEGRA
Camera 1.8V VDDIO_BB
G Sensor Light Sensor 180mA
R275_0_0402 +VDD_CAM_1V8 10mA R402_0_0201 +VDD_1V8_UART_TEGRA
NCT1008CMT3R2G 1.8V Q26 1.8V VDDIO_UART
1.8V 1.8V
+VDD_CAM_1V8_R 110mA R391_0_0201 +VDD_3V3_GMI_TEGRA
THERMAL 2.8V 1.8V VDDIO_GMI
0.10mA 0.4mA
Gyro Sensor
+3VS_TH
3.3V VDD 0.67mA 180mA
1.8V +VDD_CAM_2V8_R MT46H64M32L2JG
3.3V R274_0_0402
DDR
6.5mA
20mA R398_0_0402 +VDD_1V8_DDR_MEM
1.8V VDD1
+VDD_CAM_2V8
P Sensor VDD_1V2_MEM 180mA R444_0_0402 +VDD_1V2_DDR_MEM
+VDD_3V3_SENSOR 1.2V VDD2
U39
3.3V
Q38
+VDD_1V8_SENSOR
0.07mA Q35 eMMC
R57_49.9_0201
VDD_PMU_LDO1 200mA R422_0_0402 +VDD_2V85_EMMC
0.35mA 2.85V VCC
R157_0_0402
+3VS
200mA R101_0_0402 +VDDIO_1V8_EMMC
+VDD_1V8_AUDIO 44mA 1.8V VCCQ
U21 LCD Panel
A
300+171mA A
ES305 Codec
3.3V VDD_PMU_LDO2 45mA R441_0_0402 +VDD_3V_SD Micro SD
DS90C387AVJD 1.8V 1.8V
3.3V
LVDS Transmitter
300mA 171mA
+LCDVDD R122_0_0201 +VDD_LVDS
3.3V LVDSVCC

4019FQ
Custom B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
TPS61030
Charger IC SYSTEM +5VS
VIN BQ24171
AC=12V Boost-Buck IC
D D
SWITCH B+
+VIN_USB TPS63020
USB=5V Battery SYSTEM +3VS
1S2P Boost-Buck IC
G5910
Charge PUMP +VDD_5V0_SBY
Boost IC
TPS63020
3G +V_MINICARD_3V3
C
Boost-Buck IC C
Oz9979
BACK LIGHT +VDD_LED_BL
Boost IC
TPS61050
LED flash LED+
Boost IC
B B
PTPS6591102AA2ZRC T30
T30 PWR RAIL CHIP
PMU IC
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
SP02000V310
ACES_88231-09001
GND 11
10 BATT+
D GND D
9 9
8 8
7 7
6 6 BATT_TEMP <27>
5 5
1000P_0402_50V7K
33P_0402_50V8J
4 4
2200P_0402_50V7K
0.033U_0402_16V7K
0.01UF_0402_25V7K
3 3
1
2 PR1 100_0402_1%
2
1
PC8
PC9
PC11
1 1 1 2 PWR_I2C_SCL <7,10,14,15,32,34>
PC1
PC2
2
2
@ PJP1 @ PR2 0_0402_5%
2
1 2 CAM_I2C_SCL <6,17,35>
PR3 100_0402_1%
2 1 PWR_I2C_SDA <7,10,14,15,32,34>
@ PR12 0_0402_5%
1 2 CAM_I2C_SDA <6,17,35>
Battery I2C reserve CAM_I2C-10/31
VIN
C PL1 C
DC_IN FBMA-L11-160808-301LMA20T
1 2
1000P_0402_50V7K
1000P_0402_50V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.01UF_0402_25V7K
1
1
PC6
PC4
PC5
PC7
PC120
2
B B
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
OVPUVPRangesetting:
##OVPSETvoltageisbetween0.497~1.6V## CHARGER BQ24171 AC Insert or remove --> Wake up T30S
USB Insert or remove --> Wake up T30S
SW to check if Acer USB --> Change charge current to 1A
VDD_1V8_GEN VDD_1V8_GEN
1
1.6V*(768+100)/100=13.888V
100K_0402_5% 100K_0402_5%
PD1 IF=3A VF=0.5V VR=40V 0.497V*(768+100)/100=4.314V PD2 PR5 PR6
PD3
VIN 2 1 Setting"OVP13.888V"&"UVP4.314V" VIN PR136 RB751V-40_SOD323-2 VBUS_USB
2
2 1 1 2 WAKE_UP_ACIN <7> 1 2 WAKE_UP_VBUS <7>
SBR3U40P1-7_POWERDI123-2
Max Rds(on) 16.5mohm 4.02K_0402_1% RB751V-40_SOD323-2
2
Max Rds(on) 36mohm
1K_0402_1%
PR8
0.01UF_0402_25V7K
1
1
PQ17 P3 PQ3
PR131
PC125
PQ1 PQ2 SI7716ADN-T1-GE3_POWERPAK8-5 SI7716ADN-T1-GE3_POWERPAK8-5 PC12 10K_0402_1% PC13
AON7403L_DFN8-5 AON7403L_DFN8-5 P2 1 1 0.01UF_0402_25V7K 0.01UF_0402_25V7K
PR9
2
1 1 2 2
1
VBUS_USB 5 2 2 5 5 3 3 5 1 4 Charge_in @
100K_0402_1%
2.2U_0402_6.3V6M
D 3 3 D
2
2 3
4
1
PC89
1 PR16
PR10 BATT+ BATT+
4
4
100K_0402_1% 0.05_1206_1%
2
3.3_1206_5% PD4
@ @
PC14
1
PR11
38.3K_0402_1%
1 2 CHARGER_LED#
2
1 2 Battery OVP protect
2
806K_0402_1%
PR67
RB751V-40_SOD323-2
2
Change 0.22U*2 for VBUS_USB issue 10/19 SB000005N00 PR62

10K_0402_5%
1U_0603_25V6K
2
1
PC15 0.1U_0402_25V6 PU17
PC121
1
PC101
PR13
0.01U_0603_50V7K PC16
D
1
1
PC17 0.1U_0402_25V6 1 2 1
1
2
VBUS_USB BTB_OFF VDD
SSM3K7002FU_SC70-3
0.1U_0402_25V6 2 2
1
2
VDD_3V3_BQ24171_VREF D RESET/RESET
2
G
200K_0402_1%
@ PQ23A
0.1U_0402_16V4Z
2.2U_0603_16V6K GND 3
PR68
BTB_OFF 1@ PR14 S
BQ24171_ACN
2 2
3
2
806K_0402_1%
PQ27
G 499K_0402_1%
2
1
PR114
PC118
10U_0805_25V6K
S SI1034CX-T1-GE3_SC89-6 PR127
0.01UF_0402_25V7K
1
2 PR40 1DOCK_CP 1M_0201_1% RT9818A-36PV_SOT23-3
1
PU1
1
PR15
2
PC19
PC20
100K_0402_1% 100K_0402_1% PC18
D
1
3
SI1034CX-T1-GE3_SC89-6
SI1034CX-T1-GE3_SC89-6 PQ26B 1 2 5 2
1
2
ACN PVCC
3
PQ4B 5
D
6
5 <20> DOCK_DET_R# G 0.047U_0402_25V7K

PVCC 3
G 2 S SI1034CX-T1-GE3_SC89-6 B+
D
4
6
PQ4A S G
BattOVP:
4
1M_0201_1%
2 S BQ24171_ACP 6
1
ACP
PQ26A
PR124
G
ENABLE_USB_HOST S SI1034CX-T1-GE3_SC89-6 19 BATDRV# Batt+over4.4V
1
BATDRV#
22U_0603_6.3V6M
0.01UF_0402_25V7K
PR17 4.02K_0402_1% PD5 Backtobackwillturnoff
2
2
1 2 7 CMSRC 2 1
PC25
PC24
VBUS_USB PR18 4.02K_0402_1% SBR3U40P1-7_POWERDI123-2
VDD_3V3_BQ24171_VREF
1
PR20 2
SH00000OD00
21K_0402_1%
1 2 BATT+
PJ7
100K_0402_1%
8 1 PL3 PR19 @
ACDRV SW
2
BQ24171_SW 1 2 1 4 charger_out 1 2
2.2UH_PCME051E-2R2MS_3.3A_20% 1 2
24
1
SW
BQ24171 internal regulator
PR23
22U_0603_6.3V6M
2 3 JUMP_43X118
1
267K_0402_1%
DMN66D0LDW-7_SOT363-6
D
3
1
C 2.5V 1 2 12 21 BQ24171_BTSTPR98 PC22 C
1
VREF BTST 0.01_1206_1%
1
PR22
USB500MA 5 PR21 1 2 1 2
G PR123 PC21 2.2_0603_5%
PC26
2
PC23
100K_0402_1%
57.6K_0402_1% 1U_0402_6.3V6K 0.047U_0402_25V7K BQ24171_SRP

0.1U_0402_25V6
16
2
2
SRP
2
S 100K_0402_1% 1 2
4
2
PQ6B
PC29
1 PR24
BQ24171_ISET 13 ISET BQ24171_SRN

15
1
BQ24171_ACSET SRN 0.1U_0402_16V4Z

17 ACSET VDD_3V3_BQ24171_VREF
1
PC30
73.2K_0402_1%
1U_0603_25V6K PC27 PC28

PR48 1
PR28 PC31
BATT+ 2 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
1
1
11K_0402_1%
10_0805_1% 20 BQ24171_REGN 1 2 PR29

D REGN
6
PR26
1 1 2 2.43K_0402_1% @PR27
@ PR27 PR35
ACIN_12V_OFF 2 @ PR25 P2 1U_0402_16V6K 82K_0402_0.1% 82K_0402_0.1%
G 73.2K_0402_1% 3 PD6 BQ24171_AVCC 4 PR30
2
BAT54CW_SOT323-3 AVCC 7.68K_0402_1%

2
2
PQ6A
S 10 BQ24171_TS 1 2
1
TS
1
SI1034CX-T1-GE3_SC89-6 SI1034CX-T1-GE3_SC89-6
0_0402_5%
PR135 49.9K_0402_1%
PR31 PR32
2
PR1009
768K_0402_1% 0_0402_5%
D
6
4.99K_0402_1%
14 BQ24171_FB 1 2
FB BATT_TEMP <26>
1
2 BQ24171_OVPSET 18
2
OVPSET
Charging 0-58C
PR1010
G
2
<7,32> CORE_PWR_REQ
PQ24A
S
ChargeCurrentsetting: VDD_3V3_BQ24171_VREF 22 LNJT103F011-20
1
VIN BQ24171_TTC PGND

D 11 TTC
3
PQ23B
ICHG=VISET/(20*PR352) 23
2
PGND
2
470K_0201_1%
@ 5 PR33
D
1
G @ PR34
<<ACadaptorcharge>> 100K_0402_1%
PR105
5 S SI1034CX-T1-GE3_SC89-6 10K_0201_1% CHARGER_LED# 9 25

4
STAT THERMALPAD
VISET=VREF*[PR26/(PR26+(PR22//PR46))] G Vbat=2.1*(1+R27/R37)
2
1
S
LEDstatus:(AC/Dockstation)
4
1
PQ24B
=3.3*[11/(11+267//47.5)]=0.707V @ BQ24171RGYR_VQFN24_3P5X5P5 PR37

2
2.39V @ PR36 82.5K_0402_0.1%

ICHG=0.707/(20*0.01)=3.536A 1 2 VDD_3V3_BQ24171_VREF
Nocharge:LEDoff
@ 2 1 10K_0402_5%
Fullycharged:StaticWhiteLED
2
1
BATT_LEARN <6>
<<USBcharge>>
0_0201_5%
100K_0201_1%
PR129
0_0201_5% PR1012
Charging:StaticOrangeLED
PR1331
VISET=VREF*[PR26/(PR26+PR22)]
0_0201_5%
PR93
PC32
SSM3K7002FU_SC70-3
0.1U_0402_25V6 1 2 W_LED_CTL <20>

D BATDRV# Chargingerror:Blink
1
=3.3*[11/(11+267)]=0.131V @ @ PR1013
2
+3VS
PQ28
@ TTC_PRECH 2 51K_0402_1%
B
ICHG=VISET/(20*0.01)=0.653A G 2 PR38 1 VDD_3V3_BQ24171_VREF White LED B
2
S @
3
100K_0402_1%
O_LED_CTL <20>
LEDstatus:(USB)
<4> CHARGER_STAT
##VISETvoltageisbetween0.12~0.8V## @ PR130
D AllLEDoff TTCsetting:
6
0_0201_5% 2 1
2 1 DOCK_CP PR119
100K_0201_1%
Orange LED 2
High:Disablechargetimer,allowtermination.
G
D PQ21A D
3
D
PR132 PQ21B
D
S SI1034CX-T1-GE3_SC89-6 Boot:StaticWhiteLED5sec Low:Disablechargetermination&timer.
1
3
3
0_0201_5% 5 2 PQ7A
PQ22B G
5 2 1 G
G 5
G PQ7B
Wakeup:StaticWhiteLED5sec Connectcapacitor:Setfastchargetimer.
S <5> CP_GPIO S SDMN66D0LDW-7_SOT363-6 S SI1034CX-T1-GE3_SC89-6
4
4
SI1034CX-T1-GE3_SC89-6
Pre-Charge reserved circuit
PD9
2
1
26.1K_0402_1%
0.022U_0402_25V7K
1 1
BATT+
PR126
PC124
51K_0402_5%
3
D D D
6
PR45
3
2 WAKEUP_LED 2 USB500MA USB500MA <7> WAKEUP_LED
2.2U_0402_6.3V6M
4.7U_0402_6.3V6M
2 5 @
2
BAT54CW_SOT323-3
1
G G G @ PR75@ 2 1 2 PQ5
2
0_0402_5%
0_0402_5%
PC126
PC127
SI1034CX-T1-GE3_SC89-6 S 100K_0402_5% @ PR86 2SA1037AK_SC59-3~D

1
2
PQ29A
PR125
PR92
PQ22A S S
2
1
300_0402_1%
PQ29B
@ PQ9
2
AON7403L_DFN8-5
@ @ 1 BATT+
1
charger_out 2 5
1
3
VDD_3V3_BQ24171_VREF @PR61
@ PR61
1
L: charge in progress 100K_0402_5%
H : charge is complete or in sleep mode PU18 @ @
4
100K_0402_5%
1
Blink (0.5Hz): fault occur (charge suspend, input over-voltage, timer fault and battery absent)
2
IN+
2
5 PR7
VCC+
2
SB00000SP00 use BSS8402DW footprint PR44 2 @ PR41
2
PR47 10K_0201_1% GND 0_0201_5%
10K_0201_1% CPsetting: 3
OUT 4
2 1 TTC_PRECH
IN-
1
VIN
1M_0402_1%
Idpm=Vacset/(20*PR9)
4 1
PR39
A LMV331IDCKRG4_SC70-5 A
1
4
402K_0402_1%
PQ18 PQ19
<<ACadaptor>> BATT+under3.3V,
1
1
5 5
PR42
PR79@
Vacset=3.3*PR25/(PR21+PR25)=1.395V Prechargewillstart
2
3 3 BQ24171_TTC 100K_0402_5%
1 1 Iin=Vacset/(20*PR9)=1.395A @ PR82
100K_0402_5%
2
2
2.39V ACIN_12V_OFF 2 6 USB500MA 2 6
<<USB>> 1 2 BATT+
Vacset=3.3*(PR25//PR20)/(PR21+PR25//PR20)=0.463V
0.1U_0402_16V4Z
1
100K_0402_5%
BSS8402DW_SOT363-6 BSS8402DW_SOT363-6
Iin=Vacset/(20*PR9)=0.463A
PR43

1
PC33
<<Dockin>> Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

PR46 4019FQ
2
BQ24171_ISET 1
Vacset=3.3*(PR25//PR23)/(PR21+PR25//PR123)=0.804V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
47.5K_0402_1%
Iin=Vacset/(20*PR9)=0.804A DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2005/4/21
A2
SCHEMATIC MB A8022 B
5 4 3 2 1
5 4 3 2 1
@ PR113 63020_B+
1 2 <32> EN_3V3_SYS
10K_0402_1%
0_0201_5%
PR50
1
PR49
0.1U_0402_25V6
PR51
1 2 0_0402_5%
PC34
2 1
100K_0402_1% PU2
PR52
2
1 14 0_0201_5% @
@ PD11 VINA PG PR53 1M_0201_1%
2 GND PS/SYNC 13 1 2
2 1 +3VS_FB 3 12 1 2 PL4
FB EN 63020_B+
D Vfb = 0.5V 4 VOUT VIN 11 1 2
B+ D
1SS355_UMD2-2 5 10
PR54 VOUT VIN
6 9 HCB2012KF-121T50_0805
L2 L1
PGND
1 2 7 8 PC35 PC36
L2 L1
1
560K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
PC56 2 1 TPS63020DSJR_QFN14_4X3
15
@ 0.1U_0402_25V6
2
PC113
+3VS 33P_0402_50V8K
PL5
1 2
1.5UH_TMPC0412HP-1R5M-Z02_3A_20%
PC37 PC38
Imax=1A
1
22U_0603_6.3V6M
22U_0603_6.3V6M
<Vo=3.3 VS> VFB=0.5V
Vo=VFB(1+R12/R14)
2
3.3=0.5(1+560/100)
C C
1
PR55
2.05K_0402_1%
2
Vout = 0.5* (1+PR56/PR55) = 5.158V
+5VS_FB FB: 0.5V
1
PR56
19.1K_0402_1% PC1007
1000P_0402_25V8J
5.045V
2
13
14
15
16
17
H/W maxloading:2A
2
PU3
FB
VOUT
VOUT
GND
PADGND
spec: Ven >0.8*VBAT

12 1
LBO VOUT +5VS
VBAT=5V-->Ven>4V
100U_B3_6.3VM_R45M
<13,32> EN_5V0_BUCKBOOST 11 EN NC 2
22U_0603_6.3V6M
1
1
B B
PC40
+
PC39
1
10 3
2
SYNC SW
1
PC41
PR57
0.1U_0402_25V6
1M_0402_1% 2
2
@ 9 4
2
LBI SW
2
PGND
PGND
PGND
0_0402_5%
0_0402_5%
VBAT
Change C_B3 footprint

PR96
PR58
@
1
PL6
2.2UH_PCMB041B-2R2MS_2.75A_20%
SYNC High : disable power saving TPS61030RSAR_QFN16_4X4
SYNC low : enable power saving
2
PL7
1 2
B+
HCB2012KF-121T50_0805 PC42
1
10U_0603_6.3V6M
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
B+ VDD_5V0_SBY
D D
PU4
PL8 G5910_CP 4 C+
VOUT 3
HCB1608KF-121T30_0603 5
PC43 VIN
1 2 GND 2
1
G5910_CP 1 2 G5910_CN 6 C- PC44
7 TP SHDN 1
1U_0603_25V6K 10U_0603_6.3V6M
Imax=110mA
2
1
G5910-50RBU_TDFN6_2X2
PC45
10U_0603_6.3V6M
Iocp(min)=250mA
2
PR59
<32,34> EN_5V_CHARGEPUMP 2 1
0_0201_5%
1
@
@ PR60 PC46
100K_0201_1% 0.1U_0201_6.3V6K
2
2
C C
B B
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
D D
BATT+
@ PR89
1 2
EN_3V3_MODEM <7,18>
10K_0201_1% 3G@ PR85
3G@ PR63
2
0_0402_5%
0.1U_0402_25V6
1 2
3G@ PC47
2 1 PR65 3G@
1
100K_0201_1% PU5 3G@ 100K_0402_5%
@ PR64
1 14 0_0201_5% 1U_0402_6.3V6K 3G@ PL16
PC1006
1
@ PD10 VINA PG 3G@
2 GND PS/SYNC 13 1 2
2 1 3G_FB 3 12 1 2 HCB1608KF-121T30_0603
FB EN
4 11 1 2
1SS355_UMD2-2 5
VOUT VIN
10
BATT+
PR66 VOUT VIN
3G@ 6 9
L2 L1
PGND
1 2 7 L2 L1 8
560K_0402_1%
10U_0603_6.3V6M
47U_0805_6.3V6M
2
PC119
10U_0603_6.3V6M
1
1
PC49 3G@
PC50 3G@
PC48 TPS63020DSJR_QFN14_4X3
15
@ 0.1U_0201_10V6K 2 1
1
PJ8 @
2
@ JUMP_43X79 PC114 3G@
33P_0402_50V8K
2 2 1 1
V_MINCARD_3V3 PL9
3G@
C 1 2 C
1.5UH_TMPC0412HP-1R5M-Z02_3A_20%
Imax=1A PC51 PC52
1
22U_0603_6.3V6M
22U_0603_6.3V6M
<Vo=3.3 VS> VFB=0.5V
Vo=VFB(1+R12/R14)
2
3.3=0.5(1+560/100)
3G@ 3G@
B B
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
D D
VISHAY use DII footprint

Use other footprint
PL10 PD8
1 2 SW 2 1
B+ 4.7UH_PCME051E-4R7MS_3A_20% +VDD_LED_BL
33P_0402_50V8J
SBR3U40P1-7_POWERDI123-2
0.1U_0603_25V7K
4.7U_0805_50V6K
4.7U_0805_50V6K
4.7U_0603_6.3V6M
1
1
1
PC53
PC117
PC57
PC55
PC54
1
2
2 PR107
PC61 1M_0201_1%
0.01UF_0402_25V7K
2 1
2
9979_OVP
2 1 2 1
1
PR100 100_0402_1% PC110 0.47U_0402_10V4Z
2
P2@PR112
P2@ PR112 PM@ PR112
1
PR94 9979_OVP 93.1K_0201_1% 76.8K_0201_1%
C PR69 C
0_0201_5% PC1005
1 2 100P_0201_25V8J
+5VS
2
FB1 <13>
1
0.1U_0402_25V6
10_0402_1% 1
SA000051D00
PC58
21
20
19
18
17
16
PU6
2
SSTCMP
OVP
ISEN1
PAD
SW
SYNC
Picasso M: PR112 76.8K OVP :35.05V
2
@ PR97 1 15
Picasso II : PR112 93.1K OVP :29.35V
0_0201_5% VIN ISEN2 FB2 <13>
DCTRL 2 14
1
0_0201_5% PC1004 PWM ISEN3 FB3 <13>
PR70 1U_0402_6.3V6K OZ9979LN-A3-0-TR_QFN20_4X4
1 2 9979_EN 1 2 9979_VREF 3 13
<4,13> DISPOFF# PR1007 VREF GNDA
0_0201_5%
@
100K_0201_1%
1000P_0201_50V7K
1 2 4 ADIM ISEN4 12
2
PR1008 FB4 <13>

1
PC59
PR103
100K_0201_1%
1 2 5 RT ISEN5 11
B
FB5 <13> B
2
ISEN6
ISET
ENA
1
LRT
LPF
6
10
PWM dimming frequency: 6K(TYP)
TP2
9979_EN
1K_0201_1%
24K_0402_1%
56K_0201_1%
PR71
PAD
2
DCTRL
1U_0402_6.3V6K
1 2
2
<13> INVTPWM
PR72
PR99
PC60
100K_0201_1%
1000P_0201_50V7K
1
2
PR73
1
1
@PC62
2
1
A A

4019FQ
B B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
a. GP0: EN_5V_CP Follow ACER circuit 6/22
PMU-TPS65911 1/3 b.
c.
d.
e.
GP2:
GP6:
GP7:
GP8:
EN_SOC
EN_3V3_SYS
EN_DDR (Optional on Cardhu S since we are using VDD2 for memory)
EN_5V0
VDD_5V0_SBY
PU7A VDD_1V8_PMU_VRTC
PMU_OSC32KOUT
F7 PMU_OSC32KIN <7>PMU_OSC32KOUT <7>

OSC32KOUT
1
22P_0402_50V8J
22P_0402_50V8J
PR74 1 2 0_0201_5% M4 PR78 PR80
<7,10,14,15,26,34> PWR_I2C_SCL SCL
PC63
PC64
PMU_OSC32KIN
F8
OSC32KIN
100K_0201_1%
100K_0201_1%
100K_0201_1%
PR76 1 2 0_0201_5% M5
2
<7,10,14,15,26,34> PWR_I2C_SDA SDA
1
D D
PR77
@
PR81 1 2 0_0201_5% M7
<7> CPU_PWR_REQ
2
TP1 EN1
PAD M6 L5
EN2 GPIO0 EN_5V_CHARGEPUMP <29,34>
VDD_1V8_GEN L4
GPIO7
K5 TP_PMU_GPIO8
GPIO8 EN_5V0_BUCKBOOST <13,28>
1
PR83
10K_0402_5% PR84 1 2 0_0201_5% F1
<7,27> CORE_PWR_REQ SLEEP
GPIO2 L2 EN_VDD_SOC <34>
G3 EN_3V3_SYS <28>
2
GPIO6
<7> PMU_INT# L3 INT1
GPIO1 F6
TP4 B7
PAD POWERHOLD GPIO3 TP5
N1 PWRHOLD PAD
PR88 0_0201_5% F4 1 2
CLK32KOUT PMU_CLK_32K <7>
<7> AP_OVERHEAT# 1 2 N2 PWRDN TP7
PR87 33_0402_1%
PAD
HDRST L6 PR91 0_0201_5%

<20> HDRST HDRST
NRESPWRON H4 1 2 PMU_RESET_OUT_1V8# <7>
NRESPWRON2 C7
TP6 PAD 1@ PR134 2 VDD_1V8_GEN
C C
100K_0402_5%
D7 PMU_VBACKUP
VBACKUP
1
PC65
1U_0402_6.3V6K
VDD_1V8_GEN
2
TP12
PAD H7 GPIO4
TP11
PAD G6 N7
GPIO5 VDDIO
B+
1
PC66 B+
4.7U_0402_6.3V6M
2
VCC7 B6
1
VDD_1V8_PMU_VRTC
<20> A_ONKEY#
PR95 1 2 0_0201_5% PMU_ONKEY# E4 PWRON
PC67
4.7U_0402_6.3V6M
Always on
2
2 PR4 1 1.8V
0_0402_5%
0.05A
1
10MIL
PC181 B5
1U_0402_6.3V6K VDD_1V8_PMU_VRTC VRTC
2
1
PMU_VCCS E8 VCCS PC68 VDD_0V85_PMU_VREF
4.7U_0402_6.3V6M
2
2
0 = Hardcode 0.85V
PR90
B B
0_0201_5% 1 = EEPROM 10MIL 0.05A
VREF G8
1
PMU_BOOT1 J5 BOOT1
1
PC69
0.1U_0402_25V6
2
REFGND G7
B8 TESTV
D6 AGND1
E6 AGND2
E5 AGND3
F5 AGND4
G4 AGND5
H6 AGND6
J3 AGND7
J4 AGND8
J6 AGND9
K3 AGND10
H5 AGND11
M8 AGND21
N8 AGND22
A1 DGND1
B1 DGND2
B2 DGND3
PTPS659110A2ZRCR_BGA98
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
PMU-TPS65911 2/3
D D
PU7B Note: LDO1 & LDO2 need 4.7uF cap according to TI on July 6th
VDD_PMU_LDO1
2.85V
+3VS N5 VCC6 LDO1 N6 VDD_PMU_LDO1
0.5A
30MIL
1
N4 VDD_PMU_LDO2
LDO2 VDD_PMU_LDO2
1
PC70
1
4.7U_0402_6.3V6M 3V
1
PC72 PC122
PC71 1U_0402_6.3V6K 1M_0402_5%
0.2A
2
4.7U_0402_6.3V6M
2
VDD_PMU_LDO3
30MIL
B+ D8 VCC5 LDO3 E7 VDD_PMU_LDO3 3V
20MIL 0.2A
1
C8 VDD_PMU_LDO4
LDO4 VDD_PMU_LDO4
1
PC73
1
4.7U_0402_6.3V6M 1.2V PC75
2
PC74
2
0.1A 2.2U_0402_6.3V6M
2
2.2U_0402_6.3V6M
C C
30MIL
PR110
B+ L1 VCC4 20MIL
LDO5 K1 1 2 VDD_PMU_LDO5 2.8V
5V 0_0402_5% 0.2A
1
0.2A PC76
1
4.7U_0402_6.3V6M
2
PC77
2
2.2U_0402_6.3V6M
VDD_PMU_LDO6
10MIL
B VDD_1V8_GEN N3 VCC3 LDO6 M2 VDD_PMU_LDO6 B
10MIL 1.2V
1
M3 VDD_PMU_LDO7
PC78 LDO7 VDD_PMU_LDO7
4.7U_0402_6.3V6M
0.1A
1.2V
2
M1 VDD_PMU_LDO8
LDO8 VDD_PMU_LDO8
0.05A
1.0V
0.02A
1
PC79 PC80 PC81
2
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
A A

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
B+
FOR VDD_1V2_CORE_TEGRA
PMU-TPS65911 3/3 PC82

10U_0603_6.3V6M 1
1
<29,32> EN_5V_CHARGEPUMP
PC83
0.1U_0402_25V6 VDD_1V2_SOC
2
2
2 PU8
PL11
PR101
2
PR102 100K_0201_5% A4 B3 TPS62361_SW1 2
VIN SW 2.2UH_PCMB041B-2R2MS_2.75A_20%
0.1U_0402_25V6
A1 AVIN SW B4
100K_0201_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
<32> EN_VDD_SOC B2 EN
PC84
PC85
PC100
PC112
1
PU7C
PC111
D1 B1 VDD_1V2_SOC
2
D
PC88 PR104 0_0201_5% VDD SENSE+ 2 D
20MIL VDD_1V8_GEN PWR_I2C_SDA <7,10,14,15,26,32>
1
B+ E1 VCCA1 SWA1 D2 1 2 D2 SDA SENSE - C1
0.1U_0402_25V6
SWA2 D1 1 2 D3 SCL
0.1U_0402_25V6 F2 E2 PWR_I2C_SCL <7,10,14,15,26,32>
2
VCCA2 SWA3 PR106 0_0201_5%
10U_0603_6.3V6M
C2 VSEL0 Close to CPU

1
F3 VCCA3 A3 VSEL1 PGND D4

PC86
PC108
PGND C3
A2 C4
2
AGND PGND
C2
Ipeak =2.5A( 6us)
TPS62361YZHR_XBGA16
GNDSWA1
GNDSWA2 C1 Imax = 1.8A(60us) sustained
GNDSWA3 D3
VFB1 D4
TPS62361B
TPS62361YZHR_XBGA16
B+
2.2UH_VLS252012T-2R2M1R3_1.8A_20%
50MIL PL13 50MIL
30MIL G2 H2 1 2
VCCBB1 SWB1 VDD_1V2_MEM
1.2V 2A
10U_0603_6.3V6M
0.1U_0402_25V6
G1 VCCB2 SWB2 H1 1.2V

1
2A
PC90
PC87
10U_0603_6.3V6M
0.1U_0402_25V6
2
1
1
2
PC91
PC102
PR108
0_0402_5%
J2
2
GNDSWB1 2
2
J1 50OHM_NETCLASS1
GNDSWB2
C K2 PMU_VFB2 C
VFB2
VDD_5V0_SBY
PC92
A5 V5IN B+
A2 PMU_VBST 1 2
VBST
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
1U_0402_16V6K
0.1U_0402_25V6
1 4.5 ~ 6.5V 0.1U_0402_25V6
1
1
PC94
PC95
PC107
1
PC93
PC103
PR109
2
2
2
PMU_DRVH PMU_DRVH_R 2
DRVH A3 1 2
PMU_DRVH_R
0_0402_5% Tj<90 degree ==>6.1A
Tj<70 degree ==>5.1A
1
D1
D1
D1
G1
PL14
2.2UH_MMD-06AE-2R2M-M1L_6A_20% 200MIL
A4 PMU_SW 10 9 PMU_SW 1 2
SW D1 D2/S1 VDD_1V0_GEN
1V Change C_B3 footprint
G2
S2
S2
S2
8A
220U_A_2.5VM_R35M
220U_A_2.5VM_R35M
150U_B_6.3VM_R35M
FDMC7200_POWER33-8-10
0.1U_0402_25V6
1 1 1
8
PQ16 1
+ + +
PC104
PC96
PC109
PC123
A6 PMU_DRVL
DRVL
1
PMU_DRVL
PR121 2 2 @ 2 @ 2 @ ZZZ
0_0402_5% X76376BOL11
2
B B
B4 PMU_VOUT
VOUT
X76 control
PC97 X76376BOL11: NEC 220U_R35*2
C5 1 2 X76376BOL12: NEC 220U_R70*2+Sanyo 100U_R45*1
VFB
330P_0402_50V7K 50OHM_NETCLASS1
C4 PMU_PGOOD PAD TP8
PGOOD
A8 GNDC1 EN D5
A7 GNDC2 TRAN C6
B3 PMU_TRIP 1 2
TRIP PR111
90.9K_0402_1%
B+
2.2UH_VLS252012T-2R2M1R3_1.8A_20%
L8 PL15 50MIL
VCCIO1 PMU_SWIO
10U_0603_6.3V6M
0.1U_0402_25V6
SWIO1 K8 1 2 VDD_1V8_GEN
1 L7 VCCIO2
1
PC98
PC106
SWIO2 K7 1.8V
10U_0603_6.3V6M
0.1U_0402_25V6
2A
2
2
1
1
PC99
PC105
PR122
A J7 0_0402_5% A
GNDIO1
2
2
J8
2
GNDIO2
50OHM_NETCLASS1
VFBIO H8

4019FQ
C B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
D D
0_0402_5%
P2@ PR118
<7> CAM_LED_EN_NV 1 2
2
<17> CAM_LED_EN 1 2 @ PR120 +3VS
@ PR117 1M_0402_1%
0_0201_5%
PC115 PU9
100K_0402_1%
PR115
P2@10U_0805_25V6K
1 2 A1 FLASH_SYNC PGND C1
<20> LED+ A2 C2 @
VOUT PGND
C PR116 P2@
indicator for TPS61050 C
1
<6,17,26> CAM_I2C_SDA 1 2 A3 SDA ENVM C3
0_0201_5%
B+ 2 1 B1 SW AGND D1
P2@PL17
P2@ PL17
2.2UH_VLS252012T-2R2M1R3_1.8A_20% B2 D2
SW LED LED- <20>
<6,17,26> CAM_I2C_SCL 1 2 B3 SCL AVIN D3 B+
P2@PR128
P2@PR128
0_0201_5%
1
10U_0603_6.3V6M
TPS61050YZGR_DSBGA12
P2@
PC116
2
P2@
B B
A A

4019FQ
A3 B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List)
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
01 28 change PL5, PL9 from PCMB041B-2R2MS 2.75A to EVT

D
1 Ripple un-stable Loop stable for TPS63020
30
PCMB041B-1R5MS 3A,
20110806 (QAJ70) D
20110809 DVT
change PR9 form 0.01_1206_1% to 0.05_1206_1%
change PR25 form 10K to 73.2K
2 charger CP setting for adaptor protect 02 26 change
Remove
PR20 form 3.83K to 21K
ACER USB setting circuit (QAJ50)
3 Net name error 02 35 change net name from VDD_1V8_SYS to VDD_1V8_GEN 20110809 DVT
(QAJ50)
4 Material version change 02 35 change PQ16 from FDMC7200 2N POWER33-8 to FDMC7200S 2N POWER33-8 20110809 DVT
(QAJ50)
5 GPIO only support 1.8V Use low Vth dual N TR 02 26 change PQ4,PQ6,PQ7,PQ21,PQ21 from DMN66D0LDW-7_SOT363 to SI1034CX 20110809 DVT
(QAJ50)
6 material change for common use 02 26 change PQ18 from BSS8402DW 1P/1N SOT363-6 to SI1553CDL-T1-GE3
1P/1N SC70-6 20110809 DVT
C
(QAJ50) C
7
No support Acer USB, delete related 02 26 Delete PQ19, PR40, PR44, PR47, PR41.
20110809 DVT
control circuit (QAJ50)
8 Back-to-back MOS can't The BATDRV# pull low 1K will cause ACDRV 02 26 Change PR16, PR12, PD4 to reserve
20110809 DVT
fully turn on abnormal (QAJ50)
Charger will terminate The TTC pull high 100K will cause wrong 02 26 DVT
9 voltage level
Change PR34 from 100K to 10K
20110809 (QAJ50)
10 02 26 DVT
Orange LED can't turn off STAT pull high 100K can't drive TR Change PR36 from 100K to 10Kohm
20110809 (QAJ50)
11 Modify Battery OVP circuit to avoid AC

02 26 Add PC118, PR144,PQ23. Delete PD7 20110809 DVT
turn off when Battery over discharge (QAJ50)
B B
12 Pre-charge circuit can't DVT

work normally Modify Pre-charge circuit 02 26 Change PR86,PR92,PR93 to PNP 2SA1037K
20110816 (QAJ50)
13 Sub/B +5VS will drop to Modify +5VS voltage setting to 5.15V 02 28 Change PU3 to TPS61030, PR56 to 19.1K, PR55 to 2.05K 20110824 DVT
under 4.75V (QAJ50)
14 TPS63020 add 33P on feedback resistor 02 28 Add PC113, PC114 33P 20110824 DVT
for loop stable
30 (QAJ50)
15 V_MINCARD_3V3 sequence 02 30
Change PR65 from 1M_0402_1% to 100K_0402_1%
Add PC1006 1U_0402_6.3V6K 20110824 DVT
(QAJ70)
16 modify crystal cap 02 32 Change PC63, PC64 from 12P_0402_50V8J to 22P_0402_50V8J 20110825 DVT
(QAJ70)
A
Add LED control circuit for wake up/boot 02 26 DVT A
17 define
Add PQ22 to turn off O_LED
20110825 (QAJ70)
4019FQ
Custom B
SCHEMATIC MB A8022
5 4 3 2 1
5 4 3 2 1
Add for pre-charge and fast charge timeout 02 27 DVT

D
1
Add PQ19 ,PR44,PR47
20110826 (QAJ70) D
2 BOM control 02 27,31

Modify PD1, PD5, PD8 from SS3P4-M3-84A_SMP2 DVT
to SBR3U40P1 20110826 (QAJ70)
3 footprint control 02 34,35

Modify PL13, PL15, PL17 footprint to DVT
TOKO_1239AS-H-2R2N-P2_2P 20110826 (QAJ70)
4 Change CP setting for adaptor protect 02 27 Add PQ23 DVT

20110826 (QAJ70)
5
Add VDD_1V0_GEN and VDD_1V8_GEN
02 34 Add PR121, PR122 DVT
Fb resistor for test request 20110826 (QAJ70)
03 27 Change PL1 to 300ohm bead, add PC120, PR11, PC15, DVT2
6 EMI request PC20, PR98, PC1,PC2 for EMI request 20110920 (QAJ50)
C C
7 Cancel the function 03 27 Delete PR12, PR16, PD4 20110920 DVT2

(QAJ50)
8 Reserve the CP control for thermal improve 03 27 Add PR48, PQ24 for reserve 20110920 DVT2
(QAJ50)
DVT2
9 Dock in CP setting 03 27 Add PQ26 PR93 PR96 PR124 PR123 PR40 20110920 (QAJ50)
10 Solve White LED flash issue when AC

03 27 Add PD4,PC121,PR126,PR127,PQ27 20110920 DVT2
plug in (QAJ50)
11 Battery OTP change to 55C 03 27 Change PR29 to 2.74K, PR30 to 8.87K 20110920 DVT2
(QAJ50)
B B
12 remove pre-charge function 03 Reserved PU18, PQ9, PR7, PR61, PR79, PR86, PR41 20111006 DVT2
(QAJ50)
13 solve leakage current 03 27,31 Change PD1,PD5,PD8 from SBR3U40 to SS3P4; 20111006 DVT2
PR62, PR114 to 806K (QAJ50)
14 Thermal over temperature 04 28 Change PC39 to 100U_B3_6.3VM_R45 20111027 DVT2
(QAJ70)
15 VBUS leakage PQ1 will turn on when AC plug out 04 26,27

Change PC6, PC7 to 0.22U. Add PC89 2.2U 20111027 PVT
(QAJ50)
16 OTP change to 58C 04 27 Change PR29 to 2.43K, PR30 to 7.68K 20111027 PVT
(QAJ50)
A
PVT A
17 Modify battery OVP to 4.4V 04 27 Change PR67 to 38.3K 20111105 (QAJ50)

4019FQ
27
Custom
Date:
SCHEMATIC MB A8022
Tuesday, July 10, 2012 Sheet 37 of 38
B
5 4 3 2 1
5 4 3 2 1
PVT
D
1 Turn off charge LED when USB in 04 27 Add PQ29, PC126, PC127 20111210 (QAJ50) D
2
White LED can't light
Don't need the component 04 27 Change PR45 to reserve 20111210 PVT
when power on (QAJ50)
Adjust CP setting when power on for PVT
3 thermal issue 04 27 Add PQ22, PR132, PR135 20111210 (QAJ50)
4
Battery can't be charged Modify the battery capacity control for 04 27 Add PR1012, change P135 to 4.99K 20111210 PVT
when dock in EN_USB_HOST to BATT_LEARN (QAJ50)
5
T30S WAKE_UP_ACIN damage Avoid WAKE_UP_ACIN in-rush voltage 04 27 Add PR136, PR131 20111210 PVT
(QAJ50)
6
Modify charge output voltage to improve 04 27 Change PR35 to 82K and PR31 to 82.5K 20111210 PVT
C
battery capacity (QAJ50) C
7
Avoid white LED will flash 1s when AC/USB 04 27 Change PD4 to reserve, Add PR1013, PR126, PC124 20111210 PVT
plug in/out (QAJ50)
8
Modify crystal cap value 04 32 Change PC63, PC64 to 22P 20111210 PVT
(QAJ50)
9 EMMC voltage drop PMIC LDO1 compensation 04 33 Change PC72 to 1U 20111210 PVT
(QAJ50)
10
PVT
Avoid EMMC external LDO floating 04 33 Add PC122 1M 20111219 (QAJ50)
11
B B
12
13
14
15
16
A A
17

4019FQ
Custom B
SCHEMATIC MB A8022
5 4 3 2 1
www.s-manuals.com

Acer Iconia Tab A701 - Schematics PDF

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Acer Iconia Tab A701 - Schematics PDF

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

Micro USB Signal Switch Host

Security Classification Compal Secret Data Compal Electronics, Inc.

GEN1_I2C <+VDD_1V8_SENSOR >

Gyro 0xD0 , 0xD1

Touch Screen 0x98 , 0x99

CAM_I2C < +VDD_1V8_CAM_TEGRA >

PWR_I2C < +VDD_1V8_SYS_TEGRA>

Thermal Senser 0x98 , 0x99

Codec 0x34 , 0x35

LCD_WR* AK24 GMI_AD11 LCD_DCR <13> 2

LCD_HSYNC AK20 LCD_HSYNC <12> GMI_AD13 2

C5 C6 SDMMC4_DAT5 Z EMMC_DA5 <11>

2 Q3 2011/06/20 2012/06/20 Title

33P 50V J NPO 0201

33P 50V J NPO 0201

SDMMC3_DAT2 M34 WFMMC_DAT2 <22> DDR_A07 F18 DDR_A_MA7 <9>

SDMMC3_DAT4 J37 @ PAD T17 DDR_A09 C17 DDR_A_MA9 <9>

DDR_CKE0 B20 M_CKE0 <9>

DDR_COMP_PU E17 DDR_COMP_PU R35 1 2 49.9_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

USB1_VBUS AF8 +T30S_USB1

DAP1_SCLK L29 AUDIO_SEL <14>

CSI_D1AN AJ5 5M_CAM_DA1#_R <17>

CSI_D2AN AL9 5M_CAM_DA2#_R <17>

CSI_D1BN AK4 2M_CAM_DA1#_R <17> GPIO_PBB0 AM10 2M_CAM_RST# <17>

Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

8/25 Modify C36&C37 from 12P to 8P.

UART2_RXD AG29 GPS_UART_RXD <21> 10P_0201_50V8J

AG5 (1.1V) +VDD_1V8_SYS_TEGRA

ULPI_DATA4 SIM_DET <18> PEX_WAKE* AP32 Y32 VDDIO_SYS

KB_COL00 U37 PU SC_LOCK# <20>

@ PAD T14 9/26 Change BT_PD# to AJ33

D20 JTAG_TCK 4 KB_ROW15

+3VS 1 2 THERM_DN E31

10K_0201_5% 9/26 Change from J37 to R37.

C46 2 1 100K_0201_5% T30S-R-A3-1.4G_FCCSP681

1000P_0201_16V7K D+ VDD JTAG_TRST# R162 2 @

NV_THERM_DN THERMD_F_N THERM#

1/21 CORE POWER

U25 GND_180 GND_81 AP28

1 U27 GND_181 GND_82 AP34

R64 R65 W1 AP4

W19 GND_186 GND_87 AR37

Security Classification Compal Secret Data Compal Electronics, Inc.

Follow NV design +VDD_1V2_DDR_MEM

DQ24 D6 <5> DDR_A_MA5 CA5 VDD2

<5> DDR_A_DQS1 DQS1

<5> M_CLK_DDR0 J3 CK +VDD_1V8_DDR_MEM

33P 50V J NPO 0201

33P 50V J NPO 0201

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

@ C148 C149 @ C150 C117 C118

11/23 Reserver C148,C149 and C150 for Acer HW request.

A73 TB25 TXE2+ B18 2 1 1 1 2 2 1 1 2 2

LVDS_MAP TB29 TCLK1+ LVDS_ACLK1#

A78 B21 LVDS_ACLK2 @ @

<4> LVDS_SHTDN# B14 PD# 1RLP105ANQG8_QFN148_11X11 08/05 Change L5-L12,L45,L46 to mount

Close LVDS Transmitter (U20)

R144 @ R140 R147 PICASSO_M@