Scribd Logo
Upload

Welcome to Scribd!

  • Compal La-8511p r2.0 Schematics

    Uploaded by

    Cassiano Sponton Pinto
    22 views39 pages

    Original Title

    compal_la-8511p_r2.0_schematics(1)

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    22 views39 pages

    Compal La-8511p r2.0 Schematics

    Uploaded by

    Cassiano Sponton Pinto

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 39

    A B C D E

    ZZZ0

    PCB
    MB

    1 1

    Compal Confidential
    PICASSO M Schematics Document
    2 2

    Nvdia(T30S) + LPDDRII
    QAJA0-LA-8511P
    2012-03-26 REV: 2.0

    3
    ※ The content in this document contains confidential information of Compal Electronics, Inc. 3

    that is protected under all applicable trade secrets laws and regulations.
    If you are not the intended recipient or otherwise authorized to receive such information,
    please do not copy, distribute or otherwise use the information contained herein and please
    destroy this communication accordingly.

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Page
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 1 of 38
    A B C D E
    A B C D E

    Compal Confidential
    Model Name : NVIDIA T30S System Block Diagram
    26MHz
    32KHz
    1
    LPDDR2 1

    512MB/1GB
    PMIC CORE_PWR_REQ P.9
    TPS659110
    Power ON CPU_PWR_REQ JTAG Debug
    Test Point
    P.7
    VIN SYS_RESET_N I2S
    Audience Audio Codec Audio AMP Speaker x 2
    PMU_32K_IN UART4 eS305 WM8903 APA2010 (1W)
    P.14 P.15 P.15 P.15
    PWR_I2C
    P.31~P.33
    GPS Antenna MIC & Audio Jack
    P.15

    UART2 Broadcom
    2 2
    HDMI_DDC BCM47511
    Micro HDMI HDMI Switch Nvidia P.21
    P.19 (1.8V/3.3V) T30S BT/WLAN Antenna
    P.13

    UART3
    Touch Panel SDIO AzureWave
    Control AW-AH662
    P.13 DAP
    P.22
    10.1" LCD LVDS Transmitter
    1920*1200 (V105A)
    P.12

    Client
    Micro USB Signal Switch Host
    3
    P.20 P.20 3

    CAMERA CIS(MIPI)
    5M(CJAA525) I2C
    2M(CBFA152) CAM_I2C
    P.17
    CAM_I2C CAM_I2C CAM_I2C

    SDIO4 SDIO1
    EEPROM (1.8V) (3.3V) GYRO Sensor Light Sensor E-Compass
    MPU-3050 STK2203 AKM8975
    P.10
    eMMC Micro SD slot P.16 Func/B Dock/B
    P.11 P.20
    IME

    4
    G-Sensor 4

    KXTF9-4100
    P.16

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SYSTEM BLOCK
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 2 of 38
    A B C D E
    5 4 3 2 1

    Board ID
    Voltage Rails
    Power Plane Description
    VIN Adapter power supply (19V) PICASSO 2
    B+ AC or battery power rail for power circuit.
    +VDD_1V2_RTC_TEGRA Power for RTC and always-on core logic.
    VDD_1V2_SOC Power for remainder of core logic
    D D
    +AVDD_1V1_PLL_TEGRA AVDD_PLL power rail
    +VDD_1V8_PMU_VRTC RTC power rail
    +VDD_1V8_SYS_TEGRA System power rail
    +AVDD_3V3_USB_TEGRA USB power rail
    +VDD_2V85_EMMC Core voltage for EMMC
    +VDD_1V8_CAM_TEGRA Core voltage for CAMERA
    +AVDD_3V3_HDMI_S HDMI power rail
    VDD_1V8_GEN 1.8V switched power rail for standby mode
    +VDD_3V3_DDR_RX_TEGRA DDR RX power rail
    +3VS 3.3V switched power rail for standby mode
    +5VS 5V switched power rail for standby mode
    +VDD_LED_BL LED power rail
    +VDD_3V3_SDMMC1_TEGRA Micro SD power rail
    +VDD_VCM_3V3 CAMERA power rail
    +VDD_1V2_DDR_MEM DDR power rail

    C C

    GEN1_I2C <+VDD_1V8_SENSOR >


    Device Address<Write,Read>

    Gyro 0xD0 , 0xD1


    E Compass 0x18 , 0x19
    Light Senser 0x38 , 0x39
    PICASSO M
    LPDDR2
    B GEN2_I2C / TS_I2C < +VDD_3V3_GMI_TEGRA > B

    Device Address<Write,Read>

    Touch Screen 0x98 , 0x99

    CAM_I2C < +VDD_1V8_CAM_TEGRA >


    Device Address<Write,Read>
    LVDS strap pin
    Camera 5M 0x78 , 0x79
    Camera 2M 0x20 , 0x21
    Flash LED 0x66 , 0x67

    PWR_I2C < +VDD_1V8_SYS_TEGRA>


    Device Address<Write,Read>

    Thermal Senser 0x98 , 0x99


    A
    ES305 0x3E A

    Codec 0x34 , 0x35


    PMU 0x2D
    TPS62361 0x60
    BATT Conn 0xAA , 0xAB
    EEPROM (Low level) 0xA0 , 0xA1
    Security Classification Compal Secret Data Compal Electronics, Inc.
    EEPROM (High level) 0xA2 , 0xA3 2011/06/20 2012/06/20 Title
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 3 of 38
    5 4 3 2 1
    5 4 3 2 1

    +VDD_3V3_GMI_TEGRA
    +VDD_3V3_GMI_TEGRA
    R453 L49 27NH_LQG15HS27NJ02D_5%_0402
    NV_LCD_PCLK 2 1 LCD_PCLK_R 1 2 U1E
    LCD_PCLK <12>
    47_0402_5% 1 1 NAND_D0 R1 2 1 100K_0201_5%
    C165 C164
    4/21 GMI BOOT_PD R2 2 1 100K_0201_5%
    12P_0201_50V8J 12P_0201_50V8J (1.8/3.3V)
    2 2 P12 J7 Z NAND_D0
    VDDIO_GMI_1 GMI_AD00 BOOT_PD
    RF T12 K6 Z 8/22 Change BOM structure to LPDDR2 & EMMC
    VDDIO_GMI_2 GMI_AD01
    J3 Z

    3300P_0201_16V6K

    0.1U_0201_10V6K
    GMI_AD02
    2 1 2 H2 Z
    GMI_AD03 NAND_D4 +VDD_3V3_GMI_TEGRA
    P4 Z

    4.7U_0402_6.3V6M
    +VDD_3V3_LCD_TEGRA GMI_AD04

    C3
    U1I C147 C4 P6 Z NAND_D5
    GMI_AD05 NAND_D6
    8/21 LCD N3 Z X76_SAM_1GB@
    1 2 1 GMI_AD06 NAND_D7 NAND_D4
    R3 Z R38 2 1 100K_0201_5%
    GMI_AD07
    (1.8/3.3V) G3 PD LCD_PWM_OUT <13>
    PD NV_LCD_PCLK GMI_AD08 NAND_D5
    AG23 AN21 E1 PD DISPOFF# <13,31>
    R43 2 @ 1 100K_0201_5%
    VDDIO_LCD_1 LCD_PCLK GMI_AD09
    AH24 J5 PD EN_T30S_FUSE_3V3 <23>
    D VDDIO_LCD_2 PU GMI_AD10 NAND_D6 D
    AK24 J1 PD R84 2 @ 1 100K_0201_5%

    0.1U_0201_10V6K
    LCD_WR* GMI_AD11 LCD_DCR <13>
    1 2 AR19 PD F2 Z PCB_ID0
    LCD_DE PU LCD_DE <12> GMI_AD12
    AK20 F4 Z PCB_ID1 NAND_D7 R85 2 @ 1 100K_0201_5%
    4.7U_0402_6.3V6M

    LCD_HSYNC LCD_HSYNC <12> GMI_AD13


    C1

    C2 AL17 PU P2 Z PCB_ID2
    LCD_VSYNC LCD_VSYNC <12> GMI_AD14
    R5 Z EN_SENSOR_3V3 <23>
    2 1 PD GMI_AD15 X76_ELP_1GB@
    AR17 LCD_D00 <12>
    LCD_D00 PD NAND_D4 R5
    AP26 LCD_D01 <12> 11/6 Add for COMPAL EMI request. 2 1 100K_0201_5%
    LCD_D01 PD
    AM18 LCD_D02 <12>
    LCD_D02 PD NAND_D5 R6
    AN19 LCD_D03 <12> P8 VIB_EN_T30S <20> 2 1 100K_0201_5%
    LCD_D03 PD GMI_A16
    AJ23 LCD_D04 <12> M8 TS_PWR_EN <13>
    LCD_D04 PD GMI_A17 NAND_D6 R7
    AR23 LCD_D05 <12> N9 EN_VDDLCD_T30S <13> 2 1 100K_0201_5%
    LCD_D05 PD GMI_A18
    AK16 LCD_D06 <12> R9 EN_WIFI_VDD <22>
    LCD_D06 PD GMI_A19 NAND_D7 R8
    AK22 LCD_D07 <12> 2 1 100K_0201_5%
    LCD_D07 PD
    LCD_D08
    AU21
    PD LCD_D08 <12> PU
    02/17 Change to 0201 shortpad
    AM26 LCD_D09 <12> R11 TS_INT# <13>
    LCD_D09 PD GMI_CS0* PU EN_SENSOR_3V3
    AR21 LCD_D10 <12> P10 CHARGER_STAT <27>
    LCD_D10 PD GMI_CS1* 1 BOARD_ID0
    AU27 LCD_D11 <12> G5 R158 0_0201_5%
    LCD_D11 PD GMI_CS2* 1 BOARD_ID1 2 @ +VDD_3V3_GMI_TEGRA
    AT18 LCD_D12 <12> K8 1 EN_P_SENSOR EN_P_SENSOR <20> 8/22 Change BOM structure
    LCD_D12 GMI_CS3*

    1
    AJ17 PD H4 PU
    LCD_D13 PD LCD_D13 <12> GMI_CS4* PU POUT_3G_1 <20>
    AH18 M10 R18
    LCD_D14 LCD_D14 <12> GMI_CS6* TEMP_ALERT# <7>
    AL21 PD L9 PU 100K_0201_5% PCB_ID0 R63 2 1 100K_0201_5%
    LCD_D15 PD LCD_D15 <12> GMI_CS7* POUT_WIFI <16>
    AM22 QAJ70@
    LCD_D16 PD LCD_D16 <12>
    AJ19 PCB_ID1 R87 2 1 100K_0201_5%
    LCD_D17 <12>

    2
    LCD_D17 PD BOOT_PD
    AT20 LCD_D18 <12> M4 1 NH660@
    LCD_D18 PD GMI_ADV* PCB_ID2 R100 2
    AT24 LCD_D19 <12> 1 100K_0201_5%
    LCD_D19 PD
    AN27 LCD_D20 <12> L1 0 LTE@
    LCD_D20 PD GMI_CLK BOARD_ID0 R78
    AU23 LCD_D21 <12> 2 1 100K_0201_5%
    LCD_D21 PD
    AR27 LCD_D22 <12> L5 0 EN_HDMI_5V0 <19>
    @
    LCD_D22 PD GMI_RST* TS_PWR_EN BOARD_ID1
    AM24 LCD_D23 <12> N5 PU 3G_DISABLE# <18>
    R88 2 1 100K_0201_5%
    LCD_D23 GMI_WAIT
    L3 PU 3G_WAKE# <18>
    GMI_WP*

    1
    R7 PU PCB_ID0 R152 2 1 100K_0201_5%
    PD GMI_IORDY POUT_3G <20>
    AM20 R12 QAJ50@
    LCD_M1 FORCE_RECOVERY# PCB_ID1
    M2 1 100K_0201_5% R153 2 1 100K_0201_5%
    GMI_OE*
    M6 1 NOR_BOOT AH663@
    PD GMI_WR* PCB_ID2 R154 2
    AN17 1 100K_0201_5%

    2
    LCD_PWR0 PD NONLTE@
    AP20
    LCD_PWR1 PD
    C AN25 LVDS_SHTDN# <12> L7 Z TS_RST# <13>
    BOARD_ID0 R79 2 1 100K_0201_5% C
    LCD_PWR2 GMI_DQS
    AK26 PU BOARD_ID1 R89 2 1 100K_0201_5%
    LCD_SCK PU @
    AL23
    LCD_CS0* PU EN_WIFI_VDD
    AP18
    LCD_CS1* PU
    AM28
    LCD_SDOUT PU
    AR25
    LCD_SDIN

    1
    R17 +VDD_3V3_GMI_TEGRA
    AL27 PD 100K_0201_5%
    LCD_DC0 PD
    AP24 D2 Z GEN2_I2C_SCL <13>
    NOR_BOOT R22 2 1 100K_0201_5%
    LCD_DC1 GEN2_I2C_SCL
    E3 Z

    2
    GEN2_I2C_SDA GEN2_I2C_SDA <13>

    AK18 PU
    CRT_HSYNC PU
    CRT_VSYNC
    AJ21 9/15 Modify R23 from 100K to 47K.
    9/15 Add R90 for FORCE_RECOVERY issue
    AH20 Z 9/19 Modify Q44 part number to SB00000J500 .
    DDC_SCL Z DDC_SCL_R <19>
    AT26
    DDC_SDA DDC_SDA_R <19> +VDD_3V3_GMI_TEGRA
    T30S-R-A3-1.4G_FCCSP681
    AN23 Z
    HDMI_INT HDMI_DET_T30S <19>

    1
    +VDD_3V3_GMI_TEGRA R23
    47K_0201_1% T21 PAD

    +VDD_1V8_SYS_TEGRA @

    2
    1

    1
    T30S-R-A3-1.4G_FCCSP681 9/29 Leakage Issue
    @ R11 R10 @ R90 47K_0201_1%
    Modify R10&R11 from mount to unmount 1 2 FORCE_RECOVERY#

    5
    2.2K_0201_1% 2.2K_0201_1% U55

    1
    U1K D
    1

    G Vcc
    <7,20> VOL_UP#

    2
    GEN2_I2C_SCL B Q44
    4 2
    Y

    1
    +AVDD_3V3_HDMI_S GEN2_I2C_SDA 2 G S TR DMN3150LW-7 1N SOT-323-3
    <7,20> VOL_DOWN# A
    10/21 HDMI R54 S
    L1

    3
    1M_0201_1% Vth=1.4V

    3
    1 2 AVDD_HDMI_R AP8 AR9 74AUP1G02GW_TSSOP5
    B AVDD_HDMI HDMI_TXCN HDMI_TXCN <19> B
    MPZ1005S300CT_2P AN9
    (3.3V) HDMI_TXCP <19>

    2
    HDMI_TXCP
    2
    AP12 HDMI_TXD0N <19>
    HDMI_TXD0N
    C7
    HDMI_TXD0P
    AN13 HDMI_TXD0P <19> 08/16 Change U55 footprint
    0.1U_0201_10V6K
    1 AR13
    08/16 Delete U56 footprint
    HDMI_TXD1N HDMI_TXD1N <19>
    HDMI_TXD1P
    AP14 HDMI_TXD1P <19>
    Add
    VDD_1V8_GEN AU11
    HDMI_TXD2N HDMI_TXD2N <19>
    L2 AT12 HDMI_TXD2P <19>
    HDMI_TXD2P
    1 2 AVDD_HDMI_PLL AT8
    MPZ1005S300CT_2P AVDD_HDMI_PLL HDMI_PROBE +VDD_1V8_SDMMC4_TEGRA
    2
    (1.8V) HDMI_PROBE
    AR11 @ PAD T1 U1F
    SDMMC4 : eMMC
    C8 AM8 HDMI_RSET 5/21 SDMM4
    0.1U_0201_10V6K HDMI_RSET
    1 E7 B6 Z
    VDDIO_SDMMC4 SDMMC4_DAT0 EMMC_DA0 <11>
    1

    G9 Z
    R26 SDMMC4_DAT1 Z EMMC_DA1 <11>
    (1.2/1.8V) SDMMC4_DAT2
    C5
    EMMC_DA2 <11>
    T30S-R-A3-1.4G_FCCSP681 1K_0201_1% B4 Z

    0.1U_0201_10V6K
    SDMMC4_DAT3 Z EMMC_DA3 <11>
    10/03 Co-lay SOT-23 and SC-70 1 2 SDMMC4_DAT4
    A5
    D6 Z EMMC_DA4 <11>
    2

    C5 C6 SDMMC4_DAT5 Z EMMC_DA5 <11>


    C7
    U1J SDMMC4_DAT6 Z EMMC_DA6 <11>
    SB93413000000 and SB000009O00 4.7U_0402_6.3V6M
    2 1 SDMMC4_DAT7
    D8
    EMMC_DA7 <11>

    Q6
    9/21 VDAC F8 PU
    SDMMC4_CLK EMMC_CLK <11>
    AO3413_SOT23-3 (2.8V) H10 PU
    SDMMC4_CMD EMMC_CMD <11>
    AD2 AH14
    AVDD_VDAC VDAC_R
    1 3 AJ13
    D

    VDAC_G Z
    AH12 B8
    VDAC_B SDMMC4_RST* EMMC_RST# <11>
    G
    2

    +3VS Q2 +AVDD_3V3_HDMI_S
    @
    NTS4101PT1G_SC70-3
    D

    A 1 3 AN11 A
    10MIL VDAC_VREF
    1

    0.1A 3.3V
    R27 AM12
    G
    2

    1M_0201_1% VDAC_RSET
    2

    EN_HDMI_3V3# T30S-R-A3-1.4G_FCCSP681
    T30S-R-A3-1.4G_FCCSP681
    VDD_1V8_GEN
    Security Classification Compal Secret Data Compal Electronics, Inc.
    1

    D
    2 Q3 2011/06/20 2012/06/20 Title
    Issued Date Deciphered Date
    G BSS138W-7-F_SOT323-3
    S T30S(1/5)LCD/CRT/HDMI/NAND
    3

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 4 of 38
    5 4 3 2 1
    5 4 3 2 1

    Acer request

    VDD_1V2_MEM

    U1D

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    VDD_1V2_MEM
    1 1 1 1
    3/21 DDR MEMORY
    D D

    C10

    C11

    C12

    C13
    (1.2/1.25/1.35/1.5V)
    M14 E29
    2 2 2 2 VDDIO_DDR_01 DDR_DQ00 DDR_A_D0 <9>
    M16 F28
    VDDIO_DDR_02 DDR_DQ01 DDR_A_D1 <9>
    M18 B30
    VDDIO_DDR_03 DDR_DQ02 DDR_A_D2 <9>
    SDMMC1 : SD card M20
    M22
    VDDIO_DDR_04
    VDDIO_DDR_05
    DDR_DQ03
    DDR_DQ04
    E25
    A29
    DDR_A_D3
    DDR_A_D4
    <9>
    <9>
    M24 C25
    U1P VDDIO_DDR_06 DDR_DQ05 DDR_A_D5 <9>
    N15 D24
    +VDD_3V3_SDMMC1_TEGRA VDDIO_DDR_07 DDR_DQ06 DDR_A_D6 <9>
    N17 F24
    VDDIO_DDR_08 DDR_DQ07 DDR_A_D7 <9>
    17/21 SDMMC1 N19 F14
    VDDIO_DDR_09 DDR_DQ08 DDR_A_D8 <9>
    (1.8/2.8~3.3V) N21 C15
    PU VDDIO_DDR_10 DDR_DQ09 DDR_A_D9 <9>
    R1 U7 N23 D14

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    VDDIO_SDMMC1 SDMMC1_DAT0 PU SDMMC_DAT0 <20> VDDIO_DDR_11 DDR_DQ10 DDR_A_D10 <9>
    W11 1 1 1 1 P26 H14
    SDMMC1_DAT1 PU SDMMC_DAT1 <20> VDDIO_DDR_12 DDR_DQ11 DDR_A_D11 <9>

    C14

    C22

    C15

    C16
    C17 1 U1 R25 C13
    SDMMC1_DAT2 PU SDMMC_DAT2 <20> VDDIO_DDR_13 DDR_DQ12 DDR_A_D12 <9>
    Y10 T26 C11
    4.7U_0402_6.3V6M

    SDMMC1_DAT3 SDMMC_DAT3 <20> VDDIO_DDR_14 DDR_DQ13 DDR_A_D13 <9>


    D12
    PU 2 2 2 2 DDR_DQ14 DDR_A_D14 <9>
    T6 SDMMC_CLK <20> A9
    2 SDMMC1_CLK PU DDR_DQ15 DDR_A_D15 <9>
    T8 D30
    SDMMC1_CMD SDMMC_CMD <20> DDR_DQ16 DDR_A_D16 <9>
    K24
    DDR_DQ17 DDR_A_D17 <9>
    G27
    DDR_DQ18 DDR_A_D18 <9>
    H24
    DDR_DQ19 DDR_A_D19 <9>
    E27
    DDR_DQ20 DDR_A_D20 <9>
    +VDD_3V3_SDMMC1_TEGRA G29
    +VDD_3V3_DDR_RX_TEGRA DDR_DQ21 DDR_A_D21 <9>
    H28
    DDR_DQ22 DDR_A_D22 <9>
    (2.8/3.3V) J25

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    SDMMC1_COMP_PU R29 DDR_DQ23 DDR_A_D23 <9>
    AF10 1 2 33.2_0402_1% 1 1 1 1 A15 K14
    SDMMC1_COMP_PU VDD_DDR_RX DDR_DQ24 DDR_A_D24 <9>

    C18

    C19

    C20

    C21
    F10
    SDMMC1_COMP_PD R30 DDR_DQ25 DDR_A_D25 <9>
    U9 1 2 33.2_0402_1% L15

    4.7U_0402_6.3V6M
    SDMMC1_COMP_PD DDR_DQ26 DDR_A_D26 <9>
    1 J15
    2 2 2 2 DDR_DQ27 DDR_A_D27 <9>
    H12
    DDR_DQ28 DDR_A_D28 <9>

    C23
    G11
    DDR_DQ29 DDR_A_D29 <9>
    C9
    2 DDR_DQ30 DDR_A_D30 <9>
    Y6 Z E9
    GPIO_PV2 DDR_DQ31 DDR_A_D31 <9>
    W9 Z
    GPIO_PV3
    U3 PD F26
    CLK2_OUT Z CP_GPIO <27> DDR_DM0 DDR_A_DM0 <9>
    U5 E13 DDR_A_DM1 <9>
    CLK2_REQ DDR_DM1
    C C29 C

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    DDR_DM2 DDR_A_DM2 <9>
    1 1 1 1 (1.05V) J13 DDR_A_DM3 <9>
    DDR_DM3

    C30

    C108

    C109

    C110
    +VDD_1V0_DDR_HS_TEGRA K12
    T30S-R-A3-1.4G_FCCSP681 VDD_DDR_HS_1
    L23
    VDD_DDR_HS_2
    9/22 2 2 2 2 DDR_DQS0N
    B26
    DDR_A_DQS#0 <9>
    Add U1.U3 GPIO to control Power CP function. DDR_DQS0P
    A27
    DDR_A_DQS0 <9>

    4.7U_0402_6.3V6M
    1 A11
    DDR_DQS1N DDR_A_DQS#1 <9>
    B12
    DDR_DQS1P DDR_A_DQS1 <9>

    C24
    K26
    2 DDR_DQS2N DDR_A_DQS#2 <9>
    H26
    DDR_DQS2P DDR_A_DQS2 <9>

    SDMMC3 : WIFI 2 2
    DDR_DQS3N
    DDR_DQS3P
    E11
    F12
    DDR_A_DQS#3 <9>
    DDR_A_DQS3 <9>

    33P 50V J NPO 0201

    33P 50V J NPO 0201


    C205

    C215
    U1O J23
    +VDD_1V8_SDMMC3_TEGRA DDR_A00 DDR_A_MA0 <9>
    C23 DDR_A_MA1 <9>
    1 1 DDR_A01
    E21 DDR_A_MA2 <9>
    6/21 SDMMC3 DDR_A02
    A23 DDR_A_MA3 <9>
    DDR_A03
    E23 DDR_A_MA4 <9>
    PU DDR_A04
    M36 N33 B18 DDR_A_MA5 <9>
    VDDIO_SDMMC3 SDMMC3_DAT0 PU WFMMC_DAT0 <22> DDR_A05
    L37 A17 DDR_A_MA6 <9>
    (1.8/2.8~3.3V) SDMMC3_DAT1
    M34 PU WFMMC_DAT1 <22> DDR_A06
    F18
    0.1U_0201_10V6K

    SDMMC3_DAT2 PU WFMMC_DAT2 <22> DDR_A07 DDR_A_MA7 <9>


    1 C26 1 P34 B14
    SDMMC3_DAT3 PU WFMMC_DAT3 <22> DDR_A08 DDR_A_MA8 <9>
    C25

    J37 C17
    4.7U_0402_6.3V6M

    SDMMC3_DAT4 PU @ PAD T17 DDR_A09 DDR_A_MA9 <9>


    N29 F16
    SDMMC3_DAT5 PU DDR_A10
    M32 G17
    2 2 SDMMC3_DAT6 PU DDR_A11
    SDMMC3_DAT7
    M28 9/26 Modify BOARD_ID3 from U1.J37 to U1.R37 DDR_A12
    J17
    H18
    DDR_A13
    J19
    DDR_A14
    J35 PU WFMMC_CLK <22>
    SDMMC3_CLK
    M30 PU J21
    SDMMC3_CMD WFMMC_CMD <22> DDR_RAS*
    +VDD_1V8_SDMMC3_TEGRA H20
    <BOM Structure> DDR_CAS*
    <BOM Structure> L35 SDMMC3_COMP_PU R31 1 2 33.2_0402_1% H22
    SDMMC3_COMP_PU DDR_WE*
    N35 SDMMC3_COMP_PD R32 1 2 33.2_0402_1%
    B SDMMC3_COMP_PD B
    F20
    DDR_BA0
    G21
    DDR_BA1
    F22
    T30S-R-A3-1.4G_FCCSP681 DDR_BA2
    C21 M_CS#0 <9>
    DDR_CS0*
    D20 M_CS#1 <9>
    DDR_CS1*
    <BOM Structure>
    G23
    DDR_ODT0
    L19
    DDR_ODT1
    B20 M_CKE0 <9>
    U1M DDR_CKE0
    E19 M_CKE1 <9>
    DDR_CKE1
    15/21 HSIC D18 M_CLK_DDR#0 <9>
    DDR_CLK*
    C19 M_CLK_DDR0 <9>
    Y2
    (1.2V) AC5
    DDR_CLK
    VDDIO_HSIC HSIC_DATA
    AD6
    HSIC_STROBE DDR_RESET
    K20 @ PAD T3
    DDR_RESET
    AD10 C27 QUSE0 R33 1 2 0_0201_5%
    HSIC_REXT DDR_QUSE0 QUSE1
    D26
    DDR_QUSE1 QUSE2 R34
    G15 1 2 0_0201_5%
    DDR_QUSE2 QUSE3
    H16
    T30S-R-A3-1.4G_FCCSP681 DDR_QUSE3
    VDD_1V2_MEM

    E17 DDR_COMP_PU R35 1 2 49.9_0402_1%


    DDR_COMP_PU
    U1N E15 DDR_COMP_PD R36 1 2 49.9_0402_1%
    DDR_COMP_PD
    16/21 IC_USB
    AB8 AD4
    AVDD_IC_USB IC_USB_DN T30S-R-A3-1.4G_FCCSP681
    (1.8/3.0V) AE3
    IC_USB_DP

    A A

    AD8
    IC_USB_REXT

    T30S-R-A3-1.4G_FCCSP681

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    T30S(2/5)OSC/PLL/SYS/DDR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 5 of 38
    5 4 3 2 1
    A B C D E

    U1L

    11/21 USB
    U1Q is not place on grid , need check connection +AVDD_3V3_USB_TEGRA
    AF8 +T30S_USB1
    USB1_VBUS
    (3.3V)
    AB6
    AVDD_USB
    AL5
    USB1_DN USB1_DN <20>
    AM4
    USB1_DP USB1_DP <20>
    1 1 1

    4.7U_0402_6.3V6M
    C27
    +VDD_1V8_AUDIO_TEGRA AU5 USB1_ID <20>
    USB1_ID
    U1Q 2
    RF note
    13/21 AUDIO
    (1.8/3.3V)
    G33 E35 AUDIO_CLK R37 1 2 0_0201_5%
    VDDIO_AUDIO CLK1_OUT AUDIO_CLK_R <15>
    0.1U_0201_10V6K

    1
    L29 PD
    C28

    DAP1_SCLK AUDIO_SEL <14>


    B34 PD AUDIO_RST# <14>
    DAP1_FS +AVDD_1V8_USB_PLL_TEGRA
    D32 PD ES305_INT_R <14>
    2 DAP1_DOUT
    A33 PD ENABLE_USB_HOST <20,27>
    DAP1_DIN
    (1.8V)
    8/24 Modify Off-Page type. V2
    AVDD_USB_PLL
    H34 PD

    0.1U_0201_10V6K
    DAP2_SCLK PD AUDIO_SCLK2 <14>
    K30 1
    DAP2_FS PD AUDIO_FS2 <14>

    C29
    F34 AH6
    DAP2_DOUT PD AUDIO_DOUT2 <14> USB2_VBUS
    C33 AUDIO_DIN2 <14>
    DAP2_DIN
    2 AG3
    USB2_DN 3G_USB_DN <18>
    AG1
    USB2_DP 3G_USB_DP <18>
    L31 PU
    SPDIF_IN
    SPDIF_OUT
    J31 PU 10/24 Add BATT_LEARN GPIO to Power request.
    AJ7
    USB2_ID
    10/03 Add D18 on +T30S_USB1 to protect CPU.
    SPI1_SCK
    G35 PU 10/19 Modify D18 from +T30S_USB1 to VBUS_USB
    H36 PU
    SPI1_CS0*
    SPI1_MOSI
    L33 PU BATT_LEARN <27> 12/2 Modify D18 from moun to @,Add Zener on samll board.
    F36 PD
    SPI1_MISO COMPASS_DRDY <20>

    SC400003Z00
    2 2
    VBUS_USB
    PU +T30S_USB1 Q18
    K32
    SPI2_SCK PU AO3413_SOT23-3
    J33 LIGHT_INT <20>
    SPI2_CS0* PU
    B32 HP_DET# <20>
    SPI2_CS1* PU

    S
    F30 CDC_IRQ# <15> 1 3
    SPI2_CS2* PD 10MIL
    D36

    1
    SPI2_MOSI EN_ES305_OSC <14>

    1
    E37 PD 0.1A 3.3V
    SPI2_MISO GYRO_INT_R <16> D18 @ AR5

    G
    +T30S_USB1

    2
    R42 USB3_VBUS
    1M_0201_1% BZT52-B5V6S_SOD323-2
    AF4

    2
    2
    USB3_DN USB_HOST_DN <20>
    EN_T30S_USB1 AE5
    USB3_DP USB_HOST_DP <20>
    T30S-R-A3-1.4G_FCCSP681 +AVDD_3V3_USB_TEGRA
    AK12
    USB3_ID

    1
    D
    2 Q5
    G BSS138W-7-F_SOT323-3
    R39
    S

    3
    AE9 USB_REXT 2 1
    USB_REXT

    1K_0201_1%
    T30S-R-A3-1.4G_FCCSP681

    +AVDD_1V2_DSI_CSI_TEGRA U1H
    USB VBUS overvoltage protection
    7/21 DSI/CSI

    (1.2V)
    AF2 AP2 5M_CAM_CLK#_R <17>
    AVDD_DSI_CSI CSI_CLKAN +VDD_1V8_CAM_TEGRA
    AN3 5M_CAM_CLK_R <17>
    CSI_CLKAP CAM_I2C_SCL CAM_I2C_SDA
    AJ5
    0.1U_0201_10V6K

    CSI_D1AN 5M_CAM_DA1#_R <17>


    1 1 AJ3 1 1
    CSI_D1AP 5M_CAM_DA1_R <17>
    C32

    C186 C187
    4.7U_0402_6.3V6M
    C31

    AL9
    CSI_D2AN 5M_CAM_DA2#_R <17>

    1
    3 3
    AK10

    39P_0201_50V8J

    39P_0201_50V8J
    2 2 CSI_D2AP 5M_CAM_DA2_R <17> R40 R41 2 2
    U1G 2.2K_0201_1% 2.2K_0201_1%
    +VDD_1V8_CAM_TEGRA
    18/21 CAM

    2
    (1.8/2.8 ~ 3.3V) Z
    AL11
    VDDIO_CAM CAM_I2C_SCL
    AK14
    AN15 Z CAM_I2C_SCL <17,26,35> RF note
    CAM_I2C_SDA CAM_I2C_SDA <17,26,35>
    AR7 AG15 Z R72 1 2 0_0201_5%

    0.1U_0201_10V6K
    CSI_CLKBN 2M_CAM_CLK#_R <17> CAM_MCLK CAM_MCLK <17>
    AN7 2M_CAM_CLK_R <17> 1 1 1
    CSI_CLKBP
    C35
    C372
    4.7U_0402_6.3V6M

    Z
    C34

    AK4 AM10 2M_CAM_RST# <17>


    CSI_D1BN 2M_CAM_DA1#_R <17> GPIO_PBB0 Z
    AL3 AM14

    10P_0201_50V8J
    CSI_D1BP 2M_CAM_DA1_R <17> 2 2 GPIO_PBB3 Z 5M_CAM_PWDN <17> 2
    AL15 5M_CAM_RST# <17>
    GPIO_PBB4 Z
    AT6 AJ15 2M_CAM_PWDN <17>
    CSI_D2BN 2M_CAM_DA2#_R <17> GPIO_PBB5 Z
    AP6 AM16 DOCK_DET# <20>
    CSI_D2BP 2M_CAM_DA2_R <17> GPIO_PBB6 Z
    AT14
    GPIO_PBB7

    AU15 PU
    GPIO_PCC1 PU
    GPIO_PCC2
    AR15 9/26 Swap U1.AM16 to U1.AM10 for WAKE UP issue

    T30S-R-A3-1.4G_FCCSP681
    AJ1
    DSI_CLKAN
    AK2
    DSI_CLKAP +AVDD_1V2_DSI_CSI_TEGRA
    AN1
    DSI_D1AN
    AM2
    DSI_D1AP
    1

    AH8
    DSI_D2AN R44
    AG9
    DSI_D2AP 453_0402_1%

    4 4
    2

    AG7 DSI_CSI_RUP
    DSI_CSI_RUP
    AT4 DSI_CSI_RDN
    DSI_CSI_RDN
    1

    T30S-R-A3-1.4G_FCCSP681 R45
    49.9_0402_1%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2

    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    T30S(3/5)USB/SDIO/UART/AUDIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 6 of 38
    A B C D E
    A B C D E

    8/25 Modify C36&C37 from 12P to 8P.


    +VDD_1V8_SENSOR BT_RST# GPS_RESET# 10/11 Modify C36&C37 from 8P to 10P.
    +VDD_1V8_SYS_TEGRA C36
    Y1

    1
    1 2 T30S_XTAL_IN 1 2
    <32> PMU_OSC32KIN PMU_OSC32KOUT <32>
    R56 R75

    1
    +VDD_1V8_UART_TEGRA 10P_0201_50V8J
    R46 R47 100K_0201_5% 100K_0201_5% 32.768KHZ_12.5P_1TJF125DP1A000D

    2
    U1R

    1
    屬屬HW料.
    2.2K_0201_1% 2.2K_0201_1% R50 Y10

    G
    Open Drain R48 R49 26MHZ_10PF_7M26000039

    4 G
    2

    2
    14/21 UART
    For PMU RTCCLK , Load BOM 10K_0201_5% 100K_0201_5% 2M_0201_5%

    3
    (1.8/3.3V)

    2
    AC37 AH30 Z
    GEN1_I2C_SCL <16,20> C37

    2
    VDDIO_UART GEN1_I2C_SCL Z CORE_PWR_REQ
    AE29
    GEN1_I2C_SDA GEN1_I2C_SDA <16,20> T30S_XTAL_OUT 1 2
    0.1U_0201_10V6K

    1 1
    1 AN35 PU CPU_PWR_REQ
    UART2_TXD PU GPS_UART_TXD <21>
    C38

    AG29 GPS_UART_RXD <21>


    UART2_RXD 10P_0201_50V8J
    UART2_RTS*
    AG31 PU
    PU GPS_UART_RTS# <21> 12/29 Modify R48 from 100K to 10K to meet Voltage level.
    AJ31
    2 UART2_CTS* GPS_UART_CTS# <21> 9/22
    PU U1C
    UART3_TXD
    AE33
    AJ35 PU BT_UART_TXD <22> Change EN_3V3_MODEM from AE35 to AF36.
    UART3_RXD PU BT_UART_RXD <22> VDD_1V8_GEN
    UART3_RTS*
    AK36
    AJ37 PU BT_UART_RTS# <22> 9/26 2/21 OSC, PLL & SYS
    UART3_CTS* BT_UART_CTS# <22> L3
    Change BT_PD# from Y36 to AJ33 09/15 Add for Acer request.
    AK34 Z 1 2 AVDD_OSC P36 R33 T30S_XTAL_IN
    GPIO_PU0 Z BT_RST# <22> AVDD_OSC XTAL_IN
    AF36 MPZ1005S300CT_2P
    GPIO_PU1 Z EN_3V3_MODEM <18,30> +VDD_1V8_SYS_TEGRA
    GPIO_PU2
    AN37 GPS_PWRON <21> (1.8V)
    AG33 Z 1
    GPIO_PU3 Z GPS_RESET# <18,21>
    AM36 U1T

    4.7U_0402_6.3V6M
    GPIO_PU4 Z DEBUG_UART1_RX_R

    C39
    AG37 1 R149 2 DEBUG_UART1_RX <20> Deep Sleep : OFF
    GPIO_PU5 Z 0_0201_5% 19/21 PEX
    T30S_XTAL_OUT
    AJ33 BT_PD# <22> R35
    GPIO_PU6 XTAL_OUT

    1
    2
    R91
    AF34 PD (1.05V)
    DAP4_DIN PD BT_PCM_IN <22>
    AG35 AN29 AT30 100K_0201_5%
    DAP4_DOUT PD BT_PCM_OUT <22> AVDD_PEXB PEX_L5_TXN
    AF28 BT_PCM_SYNC <22> AU29

    2
    DAP4_FS PD PEX_L5_TXP
    AL35 BT_PCM_CLK <22>
    DAP4_SCLK +AVDD_1V1_PLL_TEGRA LINE_OUT_DET#
    (1.05V)
    AM30
    VDD_PEXB
    0 PLL_S_PLL_LF
    AVDD_PLLA_P_C_S (1.1V)
    AH32 CLK_12M_ES305 <14> B24 R27
    CLK3_OUT Z PLL_S_PLL_LF
    CLK3_REQ
    AF32 (1.05V)
    AN31 AP30

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    AVDD_PEX_PLL PEX_L5_RXN
    PEX_L5_RXP
    AR29 1 1 K18
    AVDD_PLLX
    (1.1V) 1

    C41

    C42

    C40
    A21
    AVDD_PLLM
    (1.1V)
    T30S-R-A3-1.4G_FCCSP681 +VDD_1V8_BB_TEGRA 2 2 @ 2
    10/19 Modify R51 and R52 to 1K ohm
    AG5 (1.1V) +VDD_1V8_SYS_TEGRA
    AVDD_PLLU_D

    1
    2 2
    R77

    1
    100K_0201_5% AF30 (1.05V)
    AVDD_PLLE
    AT34

    2
    PEX_CLK3N

    2
    AR33 R51 R52
    PEX_CLK3P R53 1K_0201_1% 1K_0201_1%
    +VDD_1V8_BB_TEGRA
    EN_SENSOR_1V8#

    2
    0_0201_5%
    U1S V36 Z

    1
    PWR_I2C_SCL PWR_I2C_SCL <10,14,15,26,32,34>
    (3.3V) V30 Z
    PWR_I2C_SDA PWR_I2C_SDA <10,14,15,26,32,34>
    12/21 BB AL29
    HVDD_PEX Z
    AR31 U31 PMU_RESET_OUT_1V8# <32>
    PEX_L2_CLKREQ* SYS_RESET*
    V6 AA7 PU DEBUG_UART1_TX <20> AT32 Z
    VDDIO_BB ULPI_DATA0 PEX_L2_PRSNT* +VDD_1V8_SYS_TEGRA
    (1.8/3.3V) AC7 PU DEBUG_UART1_RX <20> AU33 Z
    ULPI_DATA1 PEX_L2_RST*
    V8 PU
    0.1U_0201_10V6K

    ULPI_DATA2
    1 AC3 PU WAKE_UP_ACIN <27> (1.8V) P28 PMU_INT# <32>
    ULPI_DATA3 PWR_INT*
    V4 PU Z
    C43

    SIM_DET <18> AP32 Y32


    ULPI_DATA4 PEX_WAKE* VDDIO_SYS
    AC11 PU T32 CORE_PWR_REQ <27,32>
    ULPI_DATA5 CORE_PWR_REQ
    AF6 PU Y34 CPU_PWR_REQ <32>
    2 ULPI_DATA6 CPU_PWR_REQ
    AA9 PU

    0.1U_0201_10V6K
    ULPI_DATA7 SYS_CLK_REQ
    (3.3V) 1 Deep Sleep : ON W27 Z @ PAD T2
    SYS_CLK_REQ

    C44
    AC1 AUDIO_UART4_TX <14> AK28
    ULPI_CLK VDDIO_PEX_CTL
    W3 Z AUDIO_UART4_RX <14> T30 PMU_CLK_32K <32>
    ULPI_DIR CLK_32K_IN
    AC9 Z EN_VDD_GPS <21> AP36 AB32 0 CLK_32K_OUT <22>
    ULPI_NXT PEX_TERMP 2 CLK_32K_OUT
    V10 Z EN_SENSOR_1V8# <23>
    ULPI_STP
    U37 PU SC_LOCK# <20>
    KB_COL00
    U29 PU VOL_UP# <4,20>
    KB_COL01
    AD32 PU VOL_DOWN# <4,20>
    PD KB_COL02 +VDD_1V8_SYS_TEGRA
    AA1 CAM_LED_EN_NV <35> AD36 PU EN_CAM_2V8 <17>
    DAP3_DIN PD KB_COL03
    W5 WF_RST# <22>
    U1U T30S-R-A3-1.4G_FCCSP681 AC31 PU BOARD_ID_WP <10>
    DAP3_DOUT KB_COL04

    2
    10K_0201_5%
    Y4 PD Y30 PU
    DAP3_FS BT_WAKEUP <22> KB_COL05

    PICASSO_M@
    AA3 PD 20/21 SPARE AD30 PU
    DAP3_SCLK EN_SENSOR_3V3_2 <23> KB_COL06

    R195
    W35 PU 9/22 Swap AD36 & W29 GPIO function.
    KB_COL07
    9/27 SPARE_1
    AC27 Default pull up& pull down swap
    AD28

    1
    SPARE_2
    Y8 Z ON_KEY# ADD EN_SENSOR_3V3_2 to U1.AA3 AG19 AC33 PD WAKEUP_LED <27>
    3 GPIO_PV0 SPARE_3 KB_ROW00 PCB_ID3 3
    AA5 Z WAKE_UP_VBUS <27> AL33 R37 PD
    GPIO_PV1 SPARE_4 KB_ROW01
    AM34 W29 PD EN_CAM_1V8# <23>
    SPARE_5 KB_ROW02 PD
    R31
    KB_ROW03

    2
    10K_0201_5%
    U35 we not
    PD use Audio LDO
    KB_ROW04

    PICASSO_2@
    V34 PD
    KB_ROW05 UART_SW <20>

    R163
    U33 PD 9/22 Change EN_3V3_MODEM to AF36
    +VDD_1V8_BB_TEGRA KB_ROW06
    AE35 PD @ PAD T10
    KB_ROW07
    AA35 PD SHORT_DET <15>

    1
    +VDD_1V8_SYS_TEGRA KB_ROW08 PD
    KB_ROW09
    AA37 08/12 Delete EN_ACER_USB_CHARGE
    AA29 PD WF_WAKE# <22>
    KB_ROW10
    1

    PD
    @ PAD T14 9/26 Change BT_PD# to AJ33
    T30S-R-A3-1.4G_FCCSP681 JDBUG1 Y36
    R164 KB_ROW11 PD
    1 P30 SD_DET# <20>
    1 KB_ROW12
    100K_0201_5% JTAG_TRST# 2 AC29 PD G_ACC_INT <16>
    JTAG_TDI 2 KB_ROW13 PD
    3 P32 LINE_OUT_DET# <20>
    3 KB_ROW14
    JTAG_TMS 4 AB30 PD BT_IRQ# <22>
    2

    D20 JTAG_TCK 4 KB_ROW15


    5
    RB751V-40_SOD323-2 JTAG_RTCK 5
    6
    ON_KEY# T30S-R-A3-1.4G_FCCSP681 JTAG_TDO 6
    2 1 ONKEY# <20> 7
    7 JTAG_TCK
    <20> HOT_RST# 8 AA31 @ PAD T4
    ONKEY# 8 JTAG_TCK JTAG_TDI
    9 AC35 @ PAD T5
    9 JTAG_TDI JTAG_TDO
    10 Y28 @ PAD T6
    10 JTAG_TDO JTAG_TMS
    11 AA33 @ PAD T7
    GND JTAG_TMS JTAG_TRST#
    12 W33 @ PAD T8
    GND JTAG_TRST* JTAG_RTCK
    AD34 @ PAD T9
    ACES_87036-1001-CP JTAG_RTCK
    R57 CONN@
    +3VS 1 2 +3VS_TH E31 NV_THERM_DN
    0.1U_0201_10V6K

    THERM_DN NV_THERM_DP
    1 C31
    VDD_1V8_PMU_VRTC THERM_DP
    C45

    49.9_0402_1%
    +VDD_1V8_SYS_TEGRA R29
    OWR
    max current is 350uA 2 V32 Z
    +3VS JTAG_TDI R155 HDMI_CEC HDMI_CEC <19>
    VR1 =17mV 1 2
    10K_0201_5% V28 TEST_MODE_EN
    JTAG_TMS R159 TEST_MODE_EN
    1 2
    1

    10K_0201_5% 9/26 Change from J37 to R37.


    1

    2
    0_0201_5%
    R59 100_0201_1% R58 JTAG_RTCK R160 1 2

    R62
    4 NV_THERM_DP 2 1 THERMD_F_P R60 10K_0201_5% 4
    U4 100K_0201_5% JTAG_TCK R161 2 1 100K_0201_5% PICASSO_M PICASSO_2
    1

    C46 2 1 100K_0201_5% T30S-R-A3-1.4G_FCCSP681


    2

    1000P_0201_16V7K D+ VDD JTAG_TRST# R162 2 @


    3 1 100K_0201_5%
    2

    1
    R61 100_0201_1% D-
    4 AP_OVERHEAT# <32> PCB_ID3 H L
    2

    NV_THERM_DN THERMD_F_N THERM#


    2 1 6 TEMP_ALERT# <4>
    PWR_I2C_SCL ALERT#
    8
    <10,14,15,26,32,34> PWR_I2C_SCL PWR_I2C_SDA SCL
    7 5
    <10,14,15,26,32,34> PWR_I2C_SDA SDA GND
    9/28 Change Net name from Board_ID3 to PCB_ID3
    NCT1008CMT3R2G_WDFN8_2X2
    Compal Electronics, Inc.
    Thermal Security Classification
    Issued Date 2011/06/20
    Compal Secret Data
    Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    T30S(4/5) UART/OSC/PLL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 7 of 38
    A B C D E
    5 4 3 2 1

    U1B
    U1A +VDD_1V2_RTC_TEGRA 21/21 GND

    1/21 CORE POWER


    (1.0 ~ 1.2V) AU7
    GND_100 GND_1
    A13
    AH26 B10 A19
    VDD_RTC_1 GND_101 GND_2
    AJ25 B16 A25
    VDD_RTC_2 GND_102 GND_3
    B2 A3

    0.1U_0201_10V6K
    GND_103 GND_4
    1 B22 A31
    GND_104 GND_5

    C47
    B28 A35
    GND_105 GND_6
    B36 A7
    GND_106 GND_7
    C1 AA11
    2 GND_107 GND_8
    C3 AA13
    D VDD_1V0_GEN GND_108 GND_9 D
    C35 AA15
    GND_109 GND_10
    Acer request 07/04 C37
    GND_110 GND_11
    AA17
    D10 AA19
    GND_111 GND_12
    D16 AA21
    GND_112 GND_13
    D22 AA23
    GND_113 GND_14
    D28 AA25
    GND_114 GND_15
    (0.9 ~ 1.0V) D34 AA27
    GND_115 GND_16
    AB12 D4 AB10
    VDD_CPU_01 GND_116 GND_17
    AB14 E33 AB2

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    VDD_CPU_02 GND_117 GND_18
    AB16 1 1 1 1 1 1 1 1 1 E5 AB28
    VDD_CPU_03 GND_118 GND_19

    C88

    C101

    C102

    C103
    AB18 F32 AB34

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    VDD_CPU_04 GND_119 GND_20

    C49

    C50

    C51

    C52

    C48
    AB20 F6 AB36
    VDD_CPU_05 GND_120 GND_21
    AD12 G1 AB4
    VDD_CPU_06 2 2 2 2 2 2 2 2 2 GND_121 GND_22
    AD14 G13 AC13
    VDD_CPU_07 GND_122 GND_23
    AD16 G19 AC15
    VDD_CPU_08 GND_123 GND_24
    AD18 G25 AC17
    VDD_CPU_09 GND_124 GND_25
    AF14 G31 AC19
    VDD_CPU_10 GND_125 GND_26
    AF16 G37 AC21
    VDD_CPU_11 GND_126 GND_27
    T20 G7 AC23
    VDD_CPU_12 GND_127 GND_28
    V18 H30 AC25
    VDD_CPU_13 GND_128 GND_29
    V20 H32 AE1
    VDD_CPU_14 GND_129 GND_30
    Y18 H6 AE11

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    VDD_CPU_15 GND_130 GND_31
    Y20 1 1 1 1 1 1 H8 AE13
    VDD_CPU_16 GND_131 GND_32

    C53

    C54
    J11 AE15

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    GND_132 GND_33

    C55

    C56

    C57

    C58
    J27 AE17
    GND_133 GND_34
    (1.0 ~ 1.2V) 2 2 2 2 2 2
    J29
    GND_134 GND_35
    AE19
    AB22 J9 AE21
    VDD_CORE_01 GND_135 GND_36
    AB24 K10 AE23
    VDD_CORE_02 GND_136 GND_37
    AB26 K16 AE25
    VDD_CORE_03 GND_137 GND_38
    AD20 K2 AE27
    VDD_CORE_04 GND_138 GND_39
    AD22 K22 AE31
    VDD_CORE_05 GND_139 GND_40
    AD24 K28 AE37
    VDD_CORE_06 GND_140 GND_41
    VDD_CORE_07
    AD26
    VDD_1V2_SOC
    Acer request 07/04 K34
    GND_141 GND_42
    AE7
    AF18 K36 AF12
    VDD_CORE_08 GND_142 GND_43
    AF20 K4 AF26
    VDD_CORE_09 GND_143 GND_44
    AF22 L11 AG11
    VDD_CORE_10 GND_144 GND_45
    AF24 L13 AG13
    VDD_CORE_11 GND_145 GND_46
    C P14 L17 AG17 C
    VDD_CORE_12 GND_146 GND_47
    P16 L21 AG21

    0.1U_0201_10V6K
    VDD_CORE_13 GND_147 GND_48
    P18 1 1 1 1 1 1 L25 AG25

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    VDD_CORE_14 GND_148 GND_49

    C64
    P20 1 1 1 1 L27 AG27

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    VDD_CORE_15 GND_149 GND_50

    C59

    C60

    C61

    C62

    C63

    C104

    C105

    C106

    C107
    P22 M12 AH10
    VDD_CORE_16 GND_150 GND_51
    T14 M26 AH16
    VDD_CORE_17 2 2 2 2 2 2 GND_151 GND_52
    T16 N1 AH2
    VDD_CORE_18 2 2 2 2 GND_152 GND_53
    T18 N11 AH22
    VDD_CORE_19 GND_153 GND_54
    T22 N13 AH28
    VDD_CORE_20 GND_154 GND_55
    T24 N25 AH34
    VDD_CORE_21 GND_155 GND_56
    V12 N27 AH36
    VDD_CORE_22 GND_156 GND_57
    V14 N31 AH4
    VDD_CORE_23 GND_157 GND_58
    V16 N37 AJ11
    VDD_CORE_24 GND_158 GND_59
    V22 N7 AJ27
    VDD_CORE_25 GND_159 GND_60
    V24 P24 AJ29
    VDD_CORE_26 GND_160 GND_61
    V26 R13 AJ9
    VDD_CORE_27 GND_161 GND_62
    W25 R15 AK30
    VDD_CORE_28 GND_162 GND_63
    Y12 R17 AK32
    VDD_CORE_29 GND_163 GND_64
    Y14 R19 AK6
    VDD_CORE_30 GND_164 GND_65
    Y16 R21 AK8
    VDD_CORE_31 GND_165 GND_66
    Y22 R23 AL1
    VDD_CORE_32 GND_166 GND_67
    Y24 T10 AL13
    VDD_CORE_33 GND_167 GND_68
    Y26 T2 AL19
    VDD_CORE_34 GND_168 GND_69
    T28 AL25
    GND_169 GND_70
    T34 AL31
    GND_170 GND_71
    T36 AL37
    GND_171 GND_72
    T4 AL7
    +VDD_3V3_FUSE_TEGRA GND_172 GND_73
    U11 AM32
    GND_173 GND_74
    U13 AM6
    GND_174 GND_75
    U15 AN33
    GND_175 GND_76
    U17 AN5
    GND_176 GND_77
    (3.3V) VPP_FUSE
    AU17 U19
    GND_177 GND_78
    AP10
    AU9 VPP_KFUSE U21 AP16
    (3.3V) VPP_KFUSE GND_178 GND_79
    U23 AP22
    GND_179 GND_80
    U25 AP28
    0.1U_0201_10V6K

    GND_180 GND_81
    1
    2

    1 U27 AP34
    GND_181 GND_82
    C65

    R64 R65 W1 AP4


    10K_0201_5% GND_182 GND_83
    W13 AR1
    B GND_183 GND_84 B
    10K_0201_5% W15 AR3
    2 GND_184 GND_85
    T30S-R-A3-1.4G_FCCSP681 12/12 Modify R65 from @ to mount. W17 AR35
    2

    GND_185 GND_86
    1

    W19 AR37
    GND_186 GND_87
    W21 AT10
    GND_187 GND_88
    W23 AT16
    GND_188 GND_89
    W31 AT2
    GND_189 GND_90
    W37 AT22
    GND_190 GND_91
    W7 AT28
    GND_191 GND_92
    AT36
    GND_93
    AU13
    GND_94
    AU19
    GND_95
    AU25
    GND_96
    AU3
    GND_97
    AU31
    GND_98
    AU35
    GND_99

    T30S-R-A3-1.4G_FCCSP681

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    T30S(5/5)PWR_GND_NC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 8 of 38
    5 4 3 2 1
    5 4 3 2 1

    Follow NV design +VDD_1V2_DDR_MEM


    NET NAME BALL NAME +VDD_1V8_DDR_MEM +VDD_1V8_DDR_MEM
    A0 P3

    1
    A1 N3 R66
    A2 M3 +VDD_1V2_DDR_MEM +VDD_1V2_DDR_MEM 100K_0201_5%
    A3 M2 +VRAM_VREDQ
    U7
    A4 M1

    2
    A1 J8
    A5 G2 NU VSS
    A2 J9
    NU VREFDQ
    A6 F2 A9 K1

    0.1U_0201_10V6K
    NU CKE0 M_CKE0 <5>

    1
    A10 K2 1
    D A7 F3 NU CKE1 M_CKE1 <5> D

    C66
    B1 K3 R67
    NU NC
    A8 E3 B2
    NC DM0
    K5 DDR_A_DM0 <5> 100K_0201_5%
    A9 E2 B3
    NC VDDQ
    K6
    2
    F1,H1,N2 are the NC pins which assembled/embedded
    B5 L1 M_CS#0 <5> the interconnection into ELP Vdd sources already.

    2
    CKE0 K1 VDD2 /CS0
    B6 L2 M_CS#1 <5>
    VDD1 /CS1 due to co-layout the LPDDR2,
    CKE1 K2 <5> DDR_A_D29 B7
    DQ31 NC
    L3
    B8 L5 it is need to apply 1.2 volt on F1, H1 and N2 pins.
    CLK J3 <5> DDR_A_D25
    B9
    DQ29 /DQS0
    L6
    DDR_A_DQS#0 <5>
    <5> DDR_A_D31 DQ26 DQS0 DDR_A_DQS0 <5>
    CLK# H3 B10
    NU DQ5
    L7 DDR_A_D5 <5>
    CS0 L1 C1 L8 DDR_A_D6 <5>
    VDD1 DQ6
    C2 L9 DDR_A_D4 <5>
    CS1 L2 1 R70 2 C3
    VSS DQ7
    L10
    ZQ1 VSS
    DM0 K5 240_0402_1% C5
    Vss CA4
    M1
    DDR_A_MA4 <5>
    DM1 H5 C6 M2
    VSS CA3 DDR_A_MA3 <5>
    C7 M3
    DQ0 M9 VDDQ CA2 DDR_A_MA2 <5>
    <5> DDR_A_D30 C8 M5
    DQ25 VSS
    DQ1 N8 C9 M6 DDR_A_D7 <5>
    VSS DQ4
    C10 M7 DDR_A_D3 <5>
    DQ10 F7 D1
    VDDQ DQ2
    VSS
    DQ11 F9 D2
    VDD2
    DQ12 F6 1 R71 2 D3
    240_0402_1% ZQ0
    D5 M8 DDR_A_D2 <5>
    DQ13 G9 VDDQ DQ1
    <5> DDR_A_D24 D6 M9 DDR_A_D0 <5>
    DQ30 DQ3
    DQ14 F8 <5> DDR_A_D28 D7
    DQ27 VDDQ
    M10
    D8 N1
    DQ15 E8 <5> DDR_A_DQS3
    D9
    DQS3 VSS
    N2
    <5> DDR_A_DQS#3 /DQS3 NC
    DQ2 M8 D10
    VSS CA1
    N3
    DDR_A_MA1 <5>
    DQ3 M7 N5 DDR_A_D19 <5>
    DQ19
    N6 DDR_A_D17 <5>
    DQ4 L9 DQ23
    DQ5 L7 E1
    VSS
    E2
    DQ6 L8 <5> DDR_A_MA9
    E3
    CA9
    DQ7 M6 <5> DDR_A_MA8 CA8
    N7 DDR_A_DM2 <5>
    DM2
    DQ8 G7 N8 DDR_A_D1 <5>
    DQ0
    <5> DDR_A_D26 E5 N9
    DQ9 G8 E6
    DQ28 VDDQ
    N10
    <5> DDR_A_D27 DQ24 VSS
    C DQS0 L6 <5> DDR_A_DM3 E7
    DM3 VSS
    P1 C

    DQS0# L5 <5> DDR_A_D15 E8 P2


    DQ15 VDD2
    E9 P3
    DQS1 G6 VDDQ CA0 DDR_A_MA0 <5>
    E10 P5
    VSS VDDQ
    DQS1# G5 F1
    NC DQ17
    P6 DDR_A_D23 <5> Acer request
    F2 P7 DDR_A_D18 <5>
    <5> DDR_A_MA6 CA6 DQ20
    F3 P8
    <5> DDR_A_MA7 CA7 DQS2 DDR_A_DQS2 <5>
    Layer 2 F5
    VSS /DQS2
    P9
    DDR_A_DQS#2 <5>
    F6 P10 +VDD_1V2_DDR_MEM
    <5> DDR_A_D12 DQ11 VSS
    <5> DDR_A_D10 F7 R1
    DM2 N7 DQ13 VDD1
    R2
    VSS +VDD_1V8_DDR_MEM
    DM3 E7 NC
    R3
    R5
    DQ16 T8 VSS
    R6 0.1U_0201_10V6K

    0.01U_0201_16V7

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    VSS
    DQ17 N6 <5> DDR_A_D14 F8
    DQ14 VDDQ
    R7 C69 1 1 1 1 1 1 1 1
    +VDD_1V2_DDR_MEM R8
    DQ18 P7 DQ22 DDR_A_D22 <5>

    C73

    C74

    C75

    C76
    F9 C70 C71 C72
    DQ19 N5 <5> DDR_A_D11 DQ12
    R9 0.1U_0201_10V6K
    VSS
    1

    2 2 2 2 2 2 2 2
    DQ20 T7 F10
    VDDQ VDDQ
    R10
    R68 T1 1U_0402_6.3V4Z
    DQ21 T9 100K_0201_5% G1
    NU
    T2
    DQ22 R8 +VRAM_VREFA VDD2 NC
    T3
    NC
    DQ23 P6 G2 T5
    2

    <5> DDR_A_MA5 CA5 VDD2


    T6
    DQ24 D6 G3
    VDD1
    T7
    VREFCA DQ16 DDR_A_D20 <5>
    DQ25 B8 <5> DDR_A_DQS#1
    G5
    /DQS1
    1

    DQ26 E5 1
    R69

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    DQ27 E6 100K_0201_5% C68 T8 DDR_A_D16 <5> 1 1 1 1
    DQ18 +VDD_1V8_DDR_MEM

    C81

    C82

    C83

    C84
    DQ28 D7 0.1U_0201_10V6K T9
    2 DQ21 DDR_A_D21 <5>
    G6
    2

    DQ29 B7 <5> DDR_A_DQS1


    G7
    DQS1 0.1U_0201_10V6K

    0.01U_0201_16V7
    <5> DDR_A_D8 DQ10 2 2 2 2
    DQ30 C8 <5> DDR_A_D9 G8
    DQ9
    C77 1 1 1 1
    DQ31 B9 <5> DDR_A_D13 G9
    DQ8 C78 C79 C80
    T10
    DQS2 P8 NU 0.1U_0201_10V6K
    G10 U1
    VSS NU 2 2 2 2
    DQS2# P9 H1
    NC
    H2 1U_0402_6.3V4Z
    B DQS3 D8 H3
    VSS B
    <5> M_CLK_DDR#0 /CK
    DQS3# D9
    U2

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    NU
    <5> DDR_A_DM1 H5 U9 1 1 1 1
    DM1 NU

    C89

    C90

    C91
    C178
    H6
    VDDQ
    J1
    VSS
    J2
    NC 2 2 2 2
    U10
    NU

    <5> M_CLK_DDR0 J3
    CK +VDD_1V8_DDR_MEM
    J5
    VSS 0.1U_0201_10V6K

    0.01U_0201_16V7
    C85 1 1 1 1
    J6
    VDDQ C86 C92 C87

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    0.1U_0201_10V6K 1 1 1 1
    2 2 2 2

    C97

    C98

    C99

    C100
    J7
    VDD2 1U_0402_6.3V4Z
    2 2 2 2
    EDB8132B2MA-6D-F_FBGA134
    X76_ELP_512M@

    U7
    X76_SAM_1GB@ +VDD_1V8_DDR_MEM
    ( 1GB Samsung )
    SA00004YY20 0.1U_0201_10V6K 2 2

    0.01U_0201_16V7

    33P 50V J NPO 0201

    33P 50V J NPO 0201


    C93 1

    C260

    C252
    1 1 1
    C94 C95 C96
    U7 0.1U_0201_10V6K 1 1
    2 2 2 2
    X76_ELP_1GB@
    1U_0402_6.3V4Z
    ( 1GB Elpida )
    A
    SA000050Z10 A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LPDDRII-DEVICE DOWN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 9 of 38
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    Remove EC
    +VDD_1V8_SYS_TEGRA

    PN:SA00004KS00

    0.1U_0201_10V6K
    2
    2k bit C115
    U54
    1
    need check with WC of GPIO
    1 8
    A0 VCC
    2 7 BOARD_ID_WP <7>
    A1 WP
    3 6
    B A2 SCL PWR_I2C_SCL <7,14,15,26,32,34> B
    4 5
    GND SDA PWR_I2C_SDA <7,14,15,26,32,34>

    AT24C02C-XHM-T_TSSOP8
    need check with SW Roger
    08/04 Change U54 and C115 to @
    08/12 Change U54 to SA000056G00
    08/12 Change U54 footprint to AT24C64A-10TQ-2P7_TSSOP8
    08/12 Change U54 footprint to AT24C64A-10TQ-2P7_TSSOP9
    08/20 Change U54 to SA00004KS00
    11/30 Change U54 to SA00005GV00
    12/16 Change U54 to SA00004KS00(2K).

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC(Reserved)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 10 of 38
    5 4 3 2 1
    5 4 3 2 1

    +VDDIO_1V8_EMMC
    +VDD_2V85_EMMC
    EMMC_CLK_R

    @ C148 C149 @ C150 C117 C118


    1
    C122
    C119

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    22U_0603_6.3V6M
    1 1 1 2 2 1 1

    10U_0402_6.3V6M

    0.1U_0201_10V6K
    1
    12P_0201_50V8J
    2
    2.2U_0402_6.3VM

    2
    D 2 2 2 1 1 2 2 D

    C120 C121
    +VDDIO_1V8_EMMC 0.1U_0201_10V6K 0.1U_0201_10V6K
    close U13 +VDD_2V85_EMMC

    11/23 Reserver C148,C149 and C150 for Acer HW request.


    11/23 Modify C117 from 2.2U 0402 to 10U 0402.
    12/7 Modify C148,C149,C150 from @ to mount
    12/16 Modify C148 and c150 from mount to @ for LDO solution.

    AA3
    AA5
    T10

    W4
    M6
    N5

    U9

    K6

    Y4
    U13
    A4

    VCC
    VCC
    VCC
    VCC

    VCCQ
    VCCQ
    VCCQ
    VCCQ
    VCCQ
    NC +VDDIO_1V8_EMMC
    A6
    NC
    A9
    NC EMMC_CMD_R
    A11 W5 1 2
    NC CMD R102 33_0201_1% EMMC_CMD <4>
    B2
    NC
    B13
    NC
    D1
    NC
    D14
    NC

    2
    H1
    NC R113 R114
    H2
    NC

    4.7K_0201_5%

    4.7K_0201_5%
    H6 W6 EMMC_CLK_R R103 1 2 0_0201_5%
    NC CLK EMMC_CLK <4>
    H7
    NC
    H8

    1
    NC
    H9
    NC
    H10
    NC
    H11
    NC EMMC_DAT0_R R104 33_0201_1%
    H12 H3 1 2
    NC DAT0 EMMC_DAT1_R R105 33_0201_1% EMMC_DA0 <4> EMMC_CMD_R
    H13 H4 1 2
    NC DAT1 EMMC_DAT2_R R106 33_0201_1% EMMC_DA1 <4>
    H14 H5 1 2
    NC DAT2 EMMC_DAT3_R R107 33_0201_1% EMMC_DA2 <4> MMC_RST#
    J1 J2 1 2
    NC DAT3 EMMC_DAT4_R R108 33_0201_1% EMMC_DA3 <4>
    J7 J3 1 2
    NC DAT4 EMMC_DAT5_R R109 33_0201_1% EMMC_DA4 <4>
    C J8 J4 1 2 C
    NC DAT5 EMMC_DAT6_R R110 33_0201_1% EMMC_DA5 <4>
    J9 J5 1 2
    NC DAT6 EMMC_DAT7_R R111 33_0201_1% EMMC_DA6 <4>
    J10 J6 1 2
    NC DAT7 EMMC_DA7 <4>
    J11
    NC
    J12
    NC C123 1 U13
    J13 K2 2
    NC VDDi
    J14
    NC 0.1U_0201_10V6K
    KING16GB@
    K1 U1
    NC NC
    K3 U2
    K5
    NC
    NC
    NC
    NC
    U3 R112 0_0201_5% SA00004O610
    K7 U5 MMC_RST# 1 @ 2
    NC RSTN EMMC_RST# <4>
    K8 U6
    NC NC U13
    K9 U7
    NC NC
    K10
    NC NC
    U10 02/17 Change to 0201 shortpad SAND16GB@
    K11 U12
    NC NC
    K12
    K13
    NC NC
    U13
    U14 SA00004XA00
    NC NC
    K14 V1
    NC NC
    L1 V2
    NC NC U13
    L2 V3
    NC NC
    L3
    NC NC
    V12 SAM16GB@
    L4 V13
    NC NC
    L12
    L13
    NC NC
    V14
    W1 SA00004FN20
    NC NC
    L14 W2
    NC NC
    M1 W3
    NC NC
    M2 W7
    NC NC
    M3 W8
    NC NC
    M5 W9
    NC NC
    M8 W10
    NC NC
    M9 W11
    NC NC
    M10 W12
    NC NC
    M12 W13
    NC NC
    M13 W14
    NC NC
    M14 Y1
    NC NC U13
    N1 Y3
    NC NC
    N2
    NC NC
    Y6 KING32GB@
    N3 Y7
    B NC NC B
    N10 Y8
    N12
    NC
    NC
    NC
    NC
    Y9 SA00004TD00
    N13 Y10
    NC NC
    N14 Y11
    NC NC U13
    P1 Y12
    NC NC
    P2
    NC NC
    Y13 SAM32GB@
    P3 Y14
    NC NC
    P10
    P12
    NC NC
    AA1
    AA2 SA00004FO40
    NC NC
    P13 AA7
    NC NC
    P14 AA8
    NC NC U13
    R1 AA9
    NC NC
    R2
    NC NC
    AA10 SAND32GB@
    R3 AA11
    NC NC
    R5
    R12
    NC NC
    AA12
    AA13 SA000052910
    NC NC
    R13 AA14
    NC NC
    R14 AE1
    NC NC
    T1 AE14
    NC NC
    T2 AG2
    NC NC U13
    T3 AG13
    NC NC
    T5
    NC NC
    AH4 SAND432GB@
    T12 AH6
    NC NC
    T13 AH9
    T14
    NC NC
    AH11 SA000042X20
    NC NC
    U13
    13
    NC SAND64GB@
    14 1
    NC NC
    15
    16
    NC NC
    2
    3 SA00004XQ10
    NC NC
    17 4
    NC NC
    18 5
    NC NC
    19 6
    NC NC
    20 7
    NC NC
    21 8
    22
    NC
    NC
    NC
    NC
    9 8/26 ADD for SKU control.
    A 23 10 A
    NC NC
    24 11
    NC NC
    12
    NC
    VSSQ
    VSSQ
    VSSQ
    VSSQ
    VSSQ

    VSS
    VSS
    VSS
    VSS
    AA6
    AA4
    Y5
    Y2
    K4

    U8
    R10
    P5
    M7

    SAND64GB@
    SDIN5F1-64G_TFBGA169
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    eMMC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 11 of 38
    5 4 3 2 1
    5 4 3 2 1

    10/03 Modify C125,C126,C128,C129,C132,C139,C140,C141 and C142 from +VDD_LVDS to LB_VCC power domain.
    08/09 Add C139-C140 for +VDD_LVDS

    LB_VCC C131 C134 C124 C125 C126 C128 C129 C132 C139 C140 C141 C142 C127 C130 C133
    PLLVCC

    33P_0201_50V8J

    33P_0201_50V8J

    33P_0201_50V8J

    33P_0201_50V8J
    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    0.01U_0201_16V7

    0.01U_0201_16V7

    0.01U_0201_16V7

    0.01U_0201_16V7
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K
    1 2 1 1 1 1 1 2 1 1 2

    1
    2

    2
    2 1 2 2 2 2 2 1 2 2 1

    D D

    +VDD_LVDS
    10/19 Modify U20 PN from SA000050500 to SA000059A00 U20
    A2 LB_VCC 1 R192 2 R122 2 1 0_0402_5% +LCDVDD
    VCC_1
    B36
    TA10 VCC_2
    A7 0_0402_5% 09/26
    A43
    TA11 VCC_3
    B39 Change R122 & R156 package from 0201 to 0402
    R0 B37 B44 R156 2 @ 1 0_0402_5%
    <4> LCD_D22 TA12 VCC_4 +3VS
    R1 A44 B49
    <4> LCD_D23 R2 TA13 VCC_5
    <4> LCD_D12 B38 A63
    R3 TA14 VCC_6
    <4> LCD_D13 A45 B59
    R4 TA15 VCC_7
    <4> LCD_D14 B40 A76
    R5 TA16 (3.3V) VCC_8
    <4> LCD_D15 A47
    R6 TA17
    <4> LCD_D16 A48 A24
    R7 TA18 LVCC_1
    <4> LCD_D17 B41 B23
    TA19 LVCC_2
    A49 B26
    TB10 LVCC_3
    B42
    TB11 LVCC_4
    B29 09/21 Isolated LB_VCC and PLLVCC.
    G0 A50 A37
    <4> LCD_D20 G1 TB12 LVCC_5
    <4> LCD_D21 B43
    G2 TB13 CH 1 Input PLLVCC
    <4> LCD_D06 A51 A19 1 R189 2
    G3 TB14 PVCC_1 0_0402_5%
    <4> LCD_D07 B45 B35
    G4 TB15 PVCC_2
    <4> LCD_D08 A53
    G5 TB16 LVDS_ACLK2 R125 1
    <4> LCD_D09 B46 2 0_0201_5% LVDS_ACLK2_R <13> LVDS_ACLK1 R126 1 2 0_0201_5% LVDS_ACLK1_R <13>
    G6 TB17 @ @
    <4> LCD_D10 A54
    G7 TB18 L5 L6
    <4> LCD_D11 A55
    TB19 LVDS_A0
    B47 B33 4 3 4 3
    TC10 TXA1+ LVDS_A0# 4 3 4 3
    A56 A39
    B0 TC11 TXA1-
    <4> LCD_D18 B48
    TC12 SM070002I00 SM070002I00
    B1 A57 B32 LVDS_A1 1 2 1 2
    <4> LCD_D19 B2 TC13 TXB1+ 1 2 1 2
    B50 A38 LVDS_A1#
    <4> LCD_D00 B3 TC14 TXB1-
    A59 S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
    <4> LCD_D01 TC15
    B4 B51 B30 LVDS_A2 LVDS_ACLK2# R123 1 2 0_0201_5% LVDS_ACLK2#_R <13> LVDS_ACLK1# R124 1 2 0_0201_5% LVDS_ACLK1#_R <13>
    <4> LCD_D02 B5 TC16 LVDS CH1 TXC1+
    B52 A36 LVDS_A2# @ @
    <4> LCD_D03 B6 TC17 TXC1-
    <4> LCD_D04 A62
    B7 TC18 LVDS_A3 LVDS_A4 R127 1
    <4> LCD_D05 B53 A32 2 0_0201_5% LVDS_A4_R <13> LVDS_A0 R128 1 2 0_0201_5% LVDS_A0_R <13>
    TC19 TXD1+ LVDS_A3# @ @
    B8 B28
    RES11 TXD1- L8 L7
    A10
    RES12
    C A31 2 1 4 3 4 3 C
    TXE1+ R73 100_0201_1% 4 3 4 3
    A64 B27
    TA20 TXE1-
    09/21 swap LCD_D00~LCD_D23 for colay. B55
    TA21 SM070002I00 SM070002I00
    A65 1 2 1 2
    TA22 LVDS_A4 1 2 1 2
    B56 A29
    TA23 TXA2+ LVDS_A4# S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
    A66 B25
    TA24 TXA2- LVDS_A4# R129 1 LVDS_A0#
    A67 2 0_0201_5% LVDS_A4#_R <13> R130 1 2 0_0201_5% LVDS_A0#_R <13>
    TA25 LVDS_A5 @ @
    B57 A28
    TA26 TXB2+ LVDS_A5#
    A68 B24
    TA27 TXB2-
    B58
    TA28 LVDS_A6 LVDS_A5 R131 1
    A69 B22 2 0_0201_5% LVDS_A5_R <13> LVDS_A1 R132 1 2 0_0201_5% LVDS_A1_R <13>
    TA29 LVDS CH2 TXC2+ LVDS_A6# @ @
    B60 A26
    +VDD_LVDS TB20 TXC2- L10 L9
    A71
    TB21 LVDS_A7
    B61 B19 4 3 4 3
    TB22 TXD2+ LVDS_A7# 4 3 4 3
    A72 A23
    TB23 CH 2 Input TXD2-
    B62
    TB24 SM070002I00 SM070002I00
    2

    A73 B18 2 1 1 2 1 2
    R139 TB25 TXE2+ R74 100_0201_1% 1 2 1 2
    B63 A22
    TB26 TXE2- S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
    10K_0201_5% A74
    TB27 LVDS_A5# R133 1 LVDS_A1#
    A75 2 0_0201_5% LVDS_A5#_R <13> R134 1 2 0_0201_5% LVDS_A1#_R <13>
    PICASSO_M@ TB28 LVDS_ACLK1 @ @
    B64 A34
    1

    LVDS_MAP TB29 TCLK1+ LVDS_ACLK1#


    A77 A35
    TC20 TCLK1- LVDS_A6 R135 1
    B66 2 0_0201_5% LVDS_A6_R <13> LVDS_A2 R136 1 2 0_0201_5% LVDS_A2_R <13>
    TC21
    2

    A78 B21 LVDS_ACLK2 @ @


    R193 TC22 TCLK2+ LVDS_ACLK2# L11 L12
    B67 A25
    TC23 TCLK2-
    10K_0201_5% A79 4 3 4 3
    TC24 4 3 4 3
    B68 1 1 1 1
    TC25

    10P_0201_50V8J

    C328
    10P_0201_50V8J

    C338
    10P_0201_50V8J

    C360
    10P_0201_50V8J

    C364
    PICASSO_2@ A1 SM070002I00 SM070002I00
    1

    TC26
    B1 A17 1 2 1 2
    TC27 TEST 1 2 1 2
    A3
    TC28 2 2 2 2
    09/21 Add R165 select pin for Picasso M. B3
    TC29
    S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
    B9 LVDS_A6# R137 1 2 0_0201_5% LVDS_A6#_R <13> LVDS_A2# R138 1 2 0_0201_5% LVDS_A2#_R <13>
    RES21 @ @
    A11 B5
    RES22 NC_1
    A6
    NC_2
    LVDS_MAP configuration: <4> LCD_VSYNC B4
    VSYNC NC_3
    B6
    A4 A9 LVDS_A7 R249 1 2 0_0201_5% LVDS_A7_R <13> LVDS_A3 R247 1 2 0_0201_5% LVDS_A3_R <13>
    High: Picasso M <4> LCD_HSYNC HSYNC Input control NC_4
    A5 B11 @ @
    <4> LCD_DE DE NC_5
    Low: Picasso 2 B13 L45 L46
    B NC_6 B
    <4> LCD_PCLK B7 A16 4 3 4 3
    CLKIN NC_7 4 3 4 3
    NC_8
    B15 SM070002I00 SM070002I00
    LVDS_MAP A13 A18
    LVDS_CTRL0 MAP NC_9
    A14 A60 1 2 1 2
    LVDS_CTRL1 CTRL0 NC_10 1 2 1 2
    B12 A61
    LVDS_CTRL2 CTRL1 NC_11 S COM FI_ ICT ICMF112P900MFR S COM FI_ ICT ICMF112P900MFR
    A15 A80
    CTRL2 NC_12 LVDS_A7# R252 1 LVDS_A3#
    2 0_0201_5% LVDS_A7#_R <13> R250 1 2 0_0201_5% LVDS_A3#_R <13>
    LVDS_RF B10 @ @
    R/F
    GND_PAD
    PGND_1
    PGND_2
    PGND_3
    PGND_4
    PGND_5

    LGND_1
    LGND_2
    LGND_3
    LGND_4
    LGND_5
    LGND_6
    LGND_7
    LGND_8

    LVDS_RS A12 11/11 Add C328,C338,C360 and C364 for Acer RF request.
    GND_1
    GND_2
    GND_3
    GND_4
    GND_5
    GND_6
    GND_7
    GND_8

    RS

    <4> LVDS_SHTDN# B14


    PD# 1RLP105ANQG8_QFN148_11X11 08/05 Change L5-L12,L45,L46 to mount
    B2
    A8
    A46
    A52
    A58
    B54
    A70
    B65

    A42
    A41
    A20
    B17
    B16

    A21
    B20
    A27
    A30
    A33
    B31
    B34
    A40

    Z1
    2

    need check for single in single out 08/12 Change L5-L12,L45,L46 to SM070002N00
    R148
    10K_0201_5% @ 10/17 Chanfe Bead P/N from SM070002N00 to SM070002I00
    +VDD_LVDS +VDD_LVDS +VDD_LVDS

    Close LVDS Transmitter (U20)


    1
    2

    R144 @ R140 R147 PICASSO_M@


    10K_0201_5% 10K_0201_5% 10K_0201_5% 08/12 Add R148 PD LVDS_SHTDN# to GND
    1

    LVDS_CTRL2 LVDS_CTRL1 LVDS_CTRL0


    2

    +VDD_LVDS LVDS
    R143 R141 PICASSO_2@ +VDD_LVDS RS Input Voltage Output Swing CMOS/TTL Input Configuration ( Input Voltage Swing
    10K_0201_5% 10K_0201_5%
    1

    VCC 350 mV Standard Input and Output Configuration


    1

    R146
    R188 200K _0201_1%
    10K_0201_5% 0.6 ~ 1.4 V 350 mV Small Input Swing, Standard Output Swing Configuration
    2

    A A
    1

    CTRL[2:0] = LHL Single-In, Dual-Out (DDR Off) LVDS_RF C135 LVDS_RS GND 200 mV Standard Input Swing, Reduced Output Swing Configuration
    2

    0.1U_0201_10V6K

    R145 @ 1
    CTRL[2:0] = HHL Single-In, Dual-Out (DDR On) 0_0201_5% R142 @
    100K_0201_5% 10/14 Modify LVDS_RS from pull up to pull down to reduce power consumption.
    1

    2
    11/1 Modify LVDS_RS from pull down to pull up to meet SPEC
    2

    CTRL[2:0] = LHH Single-In, Single-Out (Distribution Off) Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    CTRL[2:0] = HHH Single-In, Single-Out (Distribution On) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LVDS Transmitter
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 12 of 38
    5 4 3 2 1
    5 4 3 2 1

    08/01 Change L13 to SM010031680


    08/01 Change L13 footprint to +LCDVDD
    KC_FBMA-L11-160808-121LMT_2P
    U21 L13
    1 +LCDVDD_L 1 2
    VOUT FBMA-L11-160808-301LMA20T_0603~D
    +3VS 5
    VIN C188
    2 1 1 1 1
    R279 0_0201_5% GND C180 C181 C182
    1 @ 2 4

    39P_0201_50V8J

    3300P_0201_16V6K
    0.1U_0201_10V6K

    4.7U_0402_6.3V6M
    <4> EN_VDDLCD_T30S EN
    3
    OCB 2 2 2 2
    D D
    +LCDVDD
    02/17 Change to 0201 shortpad
    APL3511CBI-TRG_SOT23-5

    1
    R150

    100K_0201_5%
    1 1
    C179 C185

    2
    0.1U_0201_10V6K 1U_0402_6.3V4Z
    2 2 11/06 Add for COMPAL EMI request.

    LCD POWER CIRCUIT

    JLVDS1
    1
    1
    2 +LCDVDD
    2
    3
    3
    Panel SPEC 4
    4
    5
    5
    6
    2 VDD Power Supply +3.3V 6
    7
    7 Remove LVDS I2C 10/19 Add for Discharge +5VS
    3 VDD Power Supply +3.3V 8
    8
    9 LVDS_A0#_R <12>
    4 VDDEDID EDID +3.3V 9
    10
    10 LVDS_A0_R <12> B+ +5VS
    11
    11
    12 LVDS_A1#_R <12>
    12
    C 13 LVDS_A1_R <12>
    C
    13
    14
    14

    1
    38 DCR_EN (CABC_EN) Dynamic backlight control 15
    15 LVDS_A2#_R <12>
    16 R95 R96
    39 PWM_IN System PWM signal input for dimming 16
    17
    LVDS_A2_R <12>
    100K_0201_5% 1K_0201_1%
    40 PWM_OUT Panel PWM signal output to system 17
    18 LVDS_ACLK1#_R <12>
    18
    19 LVDS_ACLK1_R <12>

    2
    19 Q48
    20
    43 LED_CA5 LED Cathode 5 20
    21 5 4
    21 LVDS_A3#_R <12> G1 S1
    44 LED_CA4 LED Cathode 4 22
    22 LVDS_A3_R <12> D1
    3
    45 LED_CA3 LED Cathode 3 23 6
    23 D2
    24 LVDS_A4#_R <12> <28,32> EN_5V0_BUCKBOOST 2 1
    46 LED_CA2 LED Cathode 2 24 G2 S2
    25 LVDS_A4_R <12>
    25 DMN2004DWK-7_SOT363-6
    47 LED_CA1 LED Cathode 1 26
    26 02/22 Change to 0201 shortpad
    27 LVDS_A5#_R <12>
    27
    28
    28 LVDS_A5_R <12> 8/25 Acer request
    49 VLED Output LED Backlight power 29
    29
    50 VLED Output LED Backlight power 30
    30 LVDS_A6#_R <12> Add R86,R83&R82 to panel back light.
    31 LVDS_A6_R <12>
    31
    32
    32
    33 LVDS_ACLK2#_R <12>
    33 R86 0_0201_5%
    34 LVDS_ACLK2_R <12>
    34 LCD_PWM_OUT INVTPWM
    35 2 1
    35
    36 LVDS_A7#_R <12>
    36
    37 LVDS_A7_R <12>
    37
    38
    38
    39 LCD_DCR <4>
    39
    40
    40 R83 2 @ 1 0_0201_5% LCD_PWM_OUT <4> 40 . to LED power IC
    41
    41 R82 2 @ 1 0_0201_5% INVTPWM <31> 41 . For Picasso 1 Pannel backlight
    42 DISPOFF# <4,31>
    42
    43 FB5 <31>
    43
    44 FB4 <31>
    44
    45 FB3 <31>
    45 +5VS
    51 46 FB2 <31>
    GND 46
    52 47 FB1 <31>
    GND 47
    53 48
    GND 48 L14
    54 49 +VDD_LED_BL
    GND 49
    50 1 2
    B 50 MPZ1005S300CT_2P
    B

    STARC_300E50-0010RA-G3
    CONN@ 1 1 1 1
    C169 C184 C168 C183
    Remove C188 , due to PC57,PC55 is close to pin 48 2 2 2 2
    0.1U_0201_10V6K

    LTCX003KB00
    07/28 Change JLVDS1 footprint 4.7U_0402_6.3V6M 0.1U_0201_10V6K 4.7U_0402_6.3V6M

    JTP1
    1
    1
    <4> GEN2_I2C_SCL 2
    2
    3
    <4> GEN2_I2C_SDA 3
    <4> TS_INT# 4
    4
    5
    5
    <4> TS_RST# 6
    6
    7
    7
    <4> TS_PWR_EN 8
    8
    T15 PAD @ 9
    9
    T16 PAD @ 10
    10
    10/02 Modify R166 BOM Structure from Mount to Unmount
    11
    GND1
    12
    +3VS TS_INT# GEN2_I2C_SCL GND2
    TS_RST# GEN2_I2C_SDA ACES_50506-01041-001
    CONN@
    1 R166

    2
    LTCX003HG00
    100K_0201_5% D12 @ D13 @
    @ TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
    2

    A TS_RST# SCA00001W00 SCA00001W00 A

    1
    Touch Panel

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LCD Panel/Touch Panel
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 13 of 38
    5 4 3 2 1
    5 4 3 2 1

    +VDD_1V8_AUDIO

    R168
    1 2 VDD_IO_305
    0_0201_5% 1 1
    C193 C194

    1U_0402_6.3V4Z 0.1U_0201_10V6K
    2 2

    D D

    VDD_DAL_305 +VDD_1V8_AUDIO
    1 1
    C196 C197

    1
    1U_0402_6.3V4Z 0.1U_0201_10V6K
    2 2 R167 @
    02/17 Change to 0201 shortpad
    10K_0201_5%

    2
    R169 0_0201_5% U23 +VDD_1V8_AUDIO
    1 @ 2 AUDIO_SEL_R 1 10 CODEC_IN
    <6> AUDIO_SEL IN1 COM1
    AUDIO_DOUT2 2 9
    VDD_P_305 NO1 NC1
    3 8
    AUDIO_DIN2 GND V+
    1 1 4 7 1
    NO2 NC2

    2
    C198 C199 5 6 CODEC_OUT C195
    R170 IN2 COM2
    1U_0402_6.3V4Z 0.1U_0201_10V6K 470K_0402_5% TS5A23157RSER_QFN10_2X1P5 0.1U_0201_10V6K
    2 2 2
    +VDD_1V8_AUDIO SA000039100

    1
    1
    R180 @ R177
    10K_0201_5% AUDIO_DOUT2_R 1 2
    AUDIO_DOUT2 <6>
    0_0201_5%

    2
    UART_SOUT R178 0_0201_5% 02/17 Change to 0201 shortpad
    AUDIO_DIN2_R 1 @ 2
    +VDD_1V8_AUDIO AUDIO_DIN2 <6>
    Support for input clock frequencies of 24 MHz and 26 MHz
    requires a 10kΩ pull-up resistor on the UART_SOUT pin. R171
    <15> AUDIO_SCLK2_VOICE 1 2
    AUDIO_SCLK2 <6>
    0_0201_5%
    1 ES305_INT
    C380 R174
    C 0.01U_0201_16V7 1 2 C
    <15> AUDIO_FS2_VOICE AUDIO_FS2 <6>
    1

    2
    0_0201_5%
    R187 2 R205
    @ R184 0_0201_5% 470K_0402_5%
    10K_0201_5%
    20110823 Modify for Acer request
    2

    1
    02/17 Change to 0201 shortpad
    AUDIO_FS2_VOICE connect to portA and CODEC,
    R182 0_0201_5% X5
    1 @ 2 1 4 AUDIO_FS2 connect to portB, portC and CPU.
    <6> EN_ES305_OSC OE VDD
    2 3 ES305_CLK_12M AUDIO_SCLK2_VOICE connect to portA and CODEC
    GND OUTPUT
    2

    R183 12MHZ_15PF_FK1200007 AUDIO_SCLK2 connect to portB, portC and CPU.


    470K_0402_5%
    Vcount Output
    SJ000004400
    1

    H OSC out 07/27 Change X5 footprint


    OPEN OSC out
    L High Z Active --> 17 mA
    Sleep --> 35 uA 20110823 Modify for Acer request
    U24
    VDD_IO_305 D6 A2
    VDD_IO PORTA_DI CODEC_OUT <15>
    VDD_DAL_305 C6 B2 CODEC_IN <15>
    VDD_DAL PORTA_DO
    B6 A1 AUDIO_SCLK2_VOICE
    VDD_DPD PORTA_CLK
    VDD_P_305 A6 B1 AUDIO_FS2_VOICE
    VDD_P PORTA_FS
    R185 1 @ 2 0_0201_5%
    <7> CLK_12M_ES305

    SW ES305_CLK_12M R186 1

    R172 1
    2 0_0201_5% ES305_CLK_IN

    UART_SIN
    A4
    CLK_IN 12M ~ 16M PORTB_DI
    F3 AUDIO_DOUT2_R

    <7> AUDIO_UART4_TX 2 0_0201_5% A3 F4 R173 2 1 100K_0201_5%


    UART_SIN PORTB_DO
    B B
    R175 1 2 0_0201_5% UART_SOUT B4 E4 AUDIO_SCLK2
    <7> AUDIO_UART4_RX UART_SOUT PORTB_CLK
    R176 1 2 0_0201_5% ES305_INT B3 E3 AUDIO_FS2
    <6> ES305_INT_R GPIO_A PORTB_FS
    02/22 Change to 0201 shortpad ES305_I2C_SDA B5
    I2C_DATA
    ES305_I2C_SCL C5 F2 AUDIO_DOUT2_R
    R179 0_0201_5% I2C_CLK PORTC_DI
    AUDIO_DIN2 CODEC_OUT @ AUDIO_RST#_R AUDIO_DIN2_R
    DAP2_DIN C_DO A_DI ADC <6> AUDIO_RST# 1 2 D5
    RESET_ low active PORTC_DO
    E2

    02/17 Change to 0201 shortpad F5 E1 AUDIO_SCLK2


    TEST PORTC_CLK
    AUDIO_DOUT2 CODEC_IN AUDIO_FS2
    DAP2_DOUT C_DI A_DO DAC PORTC_FS
    F1

    AUDIO_SCLK2 AUDIO_SCLK2_VOICE
    DAP2_SCLK C_CLK A_CLK CLK A5
    GND_P PORTD_DI
    D1

    E5 C1
    GND PORTD_DO

    DAP2_FS C_FS A_FS LRC E6


    GND PORTD_CLK
    C2

    2
    AUDIO_FS2 AUDIO_FS2_VOICE F6
    GND PORTD_FS
    D2

    T30S ES305 WM8903 ES305_BGA32 R181


    100K_0201_5%
    B_DO D_DO

    1
    10/11 Change P/N from SA00004Y400 to SA00004Y410

    B_DI D_DI

    R226 1 2 0_0201_5% ES305_I2C_SDA


    B_CLK D_CLK <7,10,15,26,32,34> PWR_I2C_SDA
    R246 1 2 0_0201_5% ES305_I2C_SCL
    <7,10,15,26,32,34> PWR_I2C_SCL
    A A
    B_FS D_FS

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Audio Block Diagram Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ES305
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 14 of 38
    5 4 3 2 1
    5 4 3 2 1

    AUDIO_CLK_R AUDIO_SCLK2_VOICE

    +VDD_1V8_AUDIO +VDD_1V8_AUDIO +CPVDD +AVDD_CDC

    1
    R190 @ R191 @
    0_0201_5% 0_0201_5% 1 1 1 1
    C213 C214 C212 C216
    1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

    2
    C217 R194
    2 2 2 2 1 2 2 1
    2 2

    1
    C236 C218 C219 0.1U_0201_10V6K 20_0402_5%
    33P_0201_50V8J 68P_0201_25V8 68P_0201_25V8 Close U113.40 Close U113.39 Close U113.10 Close U113.24

    2
    1 1
    @ @
    C220 R196
    1 2 2 1
    D D
    08/09 Add C236 for AUDIO_CLK_R +VDD_1V8_AUDIO
    0.1U_0201_10V6K 20_0402_5%

    <7,10,14,26,32,34> PWR_I2C_SDA
    R256 1 2 0_0201_5% CODEC_I2C_SDA +VDD_1V8_AUDIO
    U25
    Audio Codec
    R322 1 2 0_0201_5% CODEC_I2C_SCL 39 16 CDC_HP_R
    9/19 Modify Value from 1u to 0.1u Acer Request.
    <7,10,14,26,32,34> PWR_I2C_SCL DCVDD HPOUTR
    L41 40 18 CDC_HP_L R199
    L17 +CPVDD DBVDD HPOUTL R443 10_0201_5% 2 @ C221 1
    1 2 10 17 2 0.1U_0402_10V7K 1 2
    FBMA-10-100505-121T_0402 +AVDD_CDC CPVDD HPGND
    1 2 24
    FBMA-10-100505-121T_0402 AVDD R446 10_0201_5% 2 20_0402_5%
    HPGND <20>
    CODEC_I2C_SCL 37 19 L43 2 1
    SCLK LINEOUTR LINE_DOCK_R <20>
    CODEC_I2C_SDA 36 21 L42 2 1
    SDIN LINEOUTL LINE_DOCK_L <20>
    EN_SPEK 5 20 R447 10_0201_5% 2 @ S SUPPRE_ KC FBMA-11-100505-601T 0402
    <6> CDC_IRQ# INTERRUPT LINEGND S SUPPRE_ KC FBMA-11-100505-601T 0402
    2 R452 10_0201_5% 2
    <6> AUDIO_CLK_R MCLK LINEGND <20>
    1

    6 22 CDC_LEFT_P C222 1 2 0.1U_0402_10V7K 1 2


    R457 <14> AUDIO_SCLK2_VOICE BCLK LOP CDC_LEFT_N
    300K_0201_1%
    8/24 Modify Net Name for Acer request. <14> AUDIO_FS2_VOICE
    8
    LRC LON
    23
    28 CDC_RIGHT_P 20_0402_5%
    ROP CDC_RIGHT_N R204
    <14> CODEC_IN 7 27
    DACDAT RON
    <14> CODEC_OUT 9
    2

    ADCDAT CFB1 C223 1


    02/17 Change to 0201 shortpad 11 2 2.2U_0402_6.3VM
    R430 0_0201_5% EN_SPEK CFB1 CFB2 +MIC_BIAS +VMID_CDC +VPOS_CDC +VNEG_CDC
    38 13
    @ SHORT_DETECT GPIO3/ADDR CFB2
    <7> SHORT_DET 1 2 3
    DMIC_DAT/GPIO2
    4 29 +MIC_BIAS
    DMIC_LR/GPIO1 MICBIAS C226 C227
    10/13 Modify R392 from 0 ohm to 1K for noise issue. CDC_COM_MIC C230 1 2 1U_0402_10V6K 32 25
    1 1
    C228
    1
    C229
    1
    +VMID_CDC

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M
    C231 1 IN1R VMID
    2 1U_0402_10V6K 35 14 +VPOS_CDC
    R392 1 CDC_COM_MIC IN1L VPOS
    2 1K_0402_5% 15 +VNEG_CDC

    2.2U_0402_6.3VM

    2.2U_0402_6.3VM
    <20> COM_MIC VNEG 2 2 2 2
    AMIC_RIGHT+ C224 1 2 1U_0402_10V6K 31
    AMIC_LEFT+ C225 1 IN2R
    2 2 1U_0402_10V6K 34 12
    C209 IN2L CPGND
    26
    AMIC_RIGHT- C269 1 AGND
    2 1U_0402_10V6K 30 41
    100P_0201_25V8J AMIC_LEFT- C258 1 IN3R GNDPAD
    2 1U_0402_10V6K 33 1
    1 IN3L DGND
    WM8903LGEFK-RV_QFN40_5X5

    CDC_HP_R 1 R409 2 HP_R


    HP_R <20> 8/25 Modify Value for Acer request. SA00003MP00
    68NH_5% LQG15HS68NJ02D
    C
    CDC_HP_L 1 R423 2 HP_L
    HP_L <20>
    10/2 Modify C398&C399 from 1u to 2.2u for Acer AUDIO C

    68NH_5% LQG15HS68NJ02D
    +VDD_1V8_AUDIO 10/2 Modify C257&C270 from 1u to 10u for Acer AUDIO
    9/22 Add R151&R165 for MIC noise issue
    2

    C210 C211
    33P_0201_50V8J 33P_0201_50V8J
    R151 1 2 0_0402_5% +VDD_1V8_MIC S SUPPRE_ KC FBMA-11-100505-601T 0402
    1

    NONLDO@ S SUPPRE_ KC FBMA-11-100505-601T 0402


    +VDD_1V8_AUDIO_LDO
    R165 1 2 0_0402_5%
    LDO@ Main MIC Second MIC AMIC_RIGHT+ L18 2 1 AMIC_R+ <20>

    2
    AMIC_RIGHT- L19 2 1 AMIC_R- <20>
    R243 R212
    11/17 Modify C210&C211 form 100P to 33P for Acer AUDIO request. 620_0402_5% 620_0402_5%
    C234 2 C235 from Docking/B
    12/2 Modify R409 and R423 from 0ohm to 68nH for Acer AUDIO request. C232 2 2 C233
    2

    100P_0201_25V8J

    100P_0201_25V8J
    1

    1
    C270 1 2 C257 1 2

    100P_0201_25V8J

    100P_0201_25V8J
    R265 C399 2.2U_0402_6.3VM R213 C398 2.2U_0402_6.3VM
    MIC_GND 2 1 1 2 MIC_GND 2 1 1 2 1 1
    1 1
    620_0402_5% 620_0402_5%
    MIC_GND 10U_0402_6.3V6M 10U_0402_6.3V6M
    1

    D
    4.7U_0402_6.3V6M

    2
    +MIC_BIAS 2 Q23
    G BSS138W-7-F_SOT323-3 NONLDO@ 1 C237 R260 R221 R209 R206
    S NONLDO@ LDO@ 620_0402_5% 620_0402_5% 620_0402_5% 620_0402_5% S SUPPRE_ KC FBMA-11-100505-680T 0402
    3

    S SUPPRE_ KC FBMA-11-100505-680T 0402


    C237

    Vth (Max) = 1.5 SD028000080


    1

    1
    2 AMIC_LEFT+ AMIC_RIGHT+ AMIC_LEFT+ L50 2 1 AMIC_L+
    AMIC_LEFT- L51 2 1 AMIC_L-
    0_0402_5% AMIC_LEFT- AMIC_RIGHT-

    47P 25V J NPO 0201

    47P 25V J NPO 0201


    2 2

    47P 25V J NPO 0201

    47P 25V J NPO 0201


    10/04 Add R269,C206 and C207 for Main Mic issue. referece to Acer
    2 2
    C2551 C2561
    B
    Int. Speaker Conn. JSPK1 R269 620_0402_5% JMIC1
    C2531
    1 1
    C2541 1 1
    B
    SPKR_LEFT# L20 2 1 FBMA-101_0402 SPK_L# 1 AMIC_L+ 2 1 AMIC_L+_R 1
    SPKR_LEFT L21 FBMA-101_0402 SPK_L 1 AMIC_L- 1
    2 1 2 2
    SPKR_RIGHT# L22 FBMA-101_0402 SPK_R# 2 2
    2 1 3 5
    SPKR_RIGHT L23 FBMA-101_0402 SPK_R 3 G1 C206
    2 1 4 6
    4 G2
    2 2 1

    3
    C240 C241 C242 C243 ACES_50281-0040N-001 3
    08/01 Change L20-L23 to SM01000DI00 2 2 2 2 CONN@ C207
    33P 50V J NPO 0201
    33P 50V J NPO 0201 4
    GND1
    GND2 10/7 Change L51 and L50 from 60ohm to 68 ohm.
    10/7 Change C2531,C2541,C2551 and C2561 from 100P to 47P
    100P_0201_25V8J

    100P_0201_25V8J

    100P_0201_25V8J

    100P_0201_25V8J

    1 ACES_50281-0020N-001
    SP02000SC00 TVNST52302AB0_SOT523-3
    SPK_R# SPK_L# 1 1 1 1 D8 CONN@
    9/22 Add for MIC noise issue

    1
    SPK_R SPK_L
    SCA00001W00 SP02000S000
    2

    D6
    TVNST52302AB0_SOT523-3
    D7
    TVNST52302AB0_SOT523-3 B+ +AMP_VDD +MIC_BIAS
    Must change to correct symbol&footprint
    R445 1 2 0_0402_5% +3VS
    SCA00001W00 SCA00001W00
    1

    +VDD_1V8_AUDIO_LDO
    +AMP_VDD

    2
    1 U8
    R197 C202 +MIC_BIAS
    +AMP_VDD

    1 5
    0_0201_5% VIN VOUT
    3
    EN
    2 1 4 1 2 2
    C238 10U_0402_6.3V6M 2 BP GND LDO@ LDO@

    1
    1 2 C143 C116
    2 1 1 2 4.7U_0402_6.3V6M LDO@ LDO@ LDO@ 1U_0402_6.3V4Z 0.1U_0201_10V6K
    C261 10U_0402_6.3V6M C239 1U_0402_6.3V4Z C145 C144 RP114Q182D-TR-FE SC-88A 5P 2 1

    1
    1U_0402_6.3V4Z 0.1U_0201_10V6K
    R198 2 1
    2.2K_0201_1%
    B1
    B2

    B1
    B2

    1U_0402_6.3V4Z U2 U5
    SA000059P00
    2
    C250 150K_0201_5% C248 1U_0402_6.3V4Z 150K_0201_5%
    VDD
    PVDD

    VDD
    PVDD

    CDC_LEFT_P 1 2 1 2 A1 CDC_RIGHT_P 1 2 1 2 A1 COM_MIC


    CDC_LEFT_N 1 IN+ IN+
    A 2 1 R259 2 C1 CDC_RIGHT_N 1 2 1 R267 2 C1 A
    C251 R263 IN- C249 1U_0402_6.3V4Z R268 IN-
    1U_0402_6.3V4Z 150K_0201_5% C3 SPKR_LEFT 150K_0201_5% C3 SPKR_RIGHT
    VO+ SPKR_LEFT# VO+ SPKR_RIGHT#
    A3 A3 2 1
    VO- VO- R200 0_0201_5% EAR_JACK_GND <20>
    EN_SPEK C2 EN_SPEK C2
    SHUTDOWN# SHUTDOWN#
    resistor is for gain setting resistor is for gain setting close to 8903 for psudo differential
    GND
    GND

    GND
    GND

    Security Classification Compal Secret Data Compal Electronics, Inc.


    A2
    B3

    A2
    B3

    APA2010HAI-TRG WLCSP 9P CLASS D AMP APA2010HAI-TRG WLCSP 9P CLASS D AMP


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Audio Codec / AMP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 15 of 38
    5 4 3 2 1
    5 4 3 2 1

    GYRO_CLKIN GYRO_FSYNC
    V_logic must be <= VDD at all time

    1
    R253 @ R255 @
    10K_0201_5% 10K_0201_5%

    2
    D +VDD_3V3_SENSOR D

    GYRO
    U29

    GYRO_CLKIN 1 13 C253 1 2 0.1U_0201_10V6K


    IME_DA CLKIN VDD
    6
    IME_CL IME_DA C254
    7 10 1 2 0.1U_0201_10V6K
    IME_CL REGOUT GYRO_FSYNC R220
    +VDD_1V8_SENSOR 8 11
    AD0 VLOGIC FSYNC GYRO_INT
    9 12 1 2 GYRO_INT_R <6>
    AD0 INT 0_0201_5%
    20 1 2
    CPOUT C255 2200P_0201_50V7K
    1 22
    CLKOUT
    07/28 Change C255 to SE00000TE00
    C256 2
    NC
    0.1U_0201_10V6K 3 23 GEN1_I2C_SCL <7,20>
    2 NC SCL
    4 24 GEN1_I2C_SDA <7,20>
    NC SDA
    5
    NC
    14 18
    NC GND
    15
    NC
    16 19
    NC RESV
    17 21
    NC RESV

    MPU-3050_QFN24_4X4

    AD0

    G Sensor
    1

    R224
    10K_0201_5%
    U31
    2

    +VDD_1V8_SENSOR 1 10 IME_DA
    IO VDD SDA IME_CL
    1 2 9
    DNC SCL
    C 3 8 C
    C259 DNC DNC G_INT
    4 7 1 2 G_ACC_INT <7>
    GND INT R231 0_0201_5%
    0.1U_0201_10V6K 5 6
    2 VDD DNC
    07/28 Change R224 to 10K
    KXTF9-4100_LGA10_3X3

    P Sensor 08/09 Change PAD2 to CLIP_1P8X3P2


    08/12 Change PAD2 footprint to EMIST_SQ-21G_1P
    B B
    +VDD_3V3_SENSOR TP
    2
    PAD2
    C111 @ CONN@
    2

    2P_0402_50V8C
    R14 @ 1

    1
    4.7K_0402_5%
    R16 @ +VDD_3V3_SENSOR
    U6 @ 470_0402_5%
    1

    2 1 POUTL_R 1 6 2 1 CAP3
    <4> POUT_WIFI OUT CX
    2 5
    R15 @ CTRL VSS VDDHI CAP_VREG
    3 4
    0_0402_5% CTRL VREG
    2

    IQS12800100TSR_TSOT23-6 3 @
    2

    D11
    R13
    1 2 1 SCA00001W00
    10K_0402_5% @ C114 C112 @ C113 @ TVNST52302AB0_SOT523-3
    @ 1U_0402_6.3V4Z 100P_0402_50V8J 1U_0402_6.3V4Z
    2 1 2
    close to PAD2
    1

    9/15 Add D11 to Compal ESD request.

    10/13 Modify R14,U6,C111,R16,D11,C113,C112 and C114 from WIFI @ to @ .

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    GYRO/P-Sen/G-Sen
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 16 of 38
    5 4 3 2 1
    5 4 3 2 1

    U39
    1 +VDD_VCM_3V3 +VDD_CAM_2V8_R +VDD_CAM_1V8_R
    +3VS VIN
    1 5 +VDD_CAM_2V8
    VOUT
    2 1 1 1
    C276 GND
    1 1 1

    1
    2.2U_0402_6.3VM 4 C281 C282 C283
    2 NC 0.1U_0201_10V6K C277 C278 C279 C280 0.1U_0201_10V6K 2.2U_0402_6.3VM
    <7> EN_CAM_2V8 3
    EN 2 0.1U_0201_10V6K 2.2U_0402_6.3VM 0.1U_0201_10V6K 47U_0805_4V6 2 2

    2
    1
    2 2 2

    @ R257 APL5603-28BI-TRG_SOT23-5
    D D
    100K_0201_5% SA00004BW00
    Vth=1.6V

    2
    10/17 Change L24-L28,L34 to 0 ohm 11/3 Modify R257 to unmount for panel garbage issue.
    08/05 Change L24-L28,L34 to mount
    08/05 Change L24-L28,L34 to SM070002N00

    R258
    1 2 5M_CAM_CLK#
    <6> 5M_CAM_CLK#_R
    0_0201_5%

    L24 @
    4 3
    4 3
    SM070002N00
    1 2
    1 2
    OCF1210900YZF_4P JCAM1
    2M_CAM_DA2 1 2
    R261 2M_CAM_DA2# 1 2
    3 4
    5M_CAM_CLK 3 4
    1 2 5 6
    <6> 5M_CAM_CLK_R 2M_CAM_CLK 5 6
    7 8 2M_CAM_PWDN <6>
    0_0201_5% 2M_CAM_CLK# 7 8 +VDD_CAM_2V8_R +VDD_CAM_2V8
    9 10
    9 10
    11 12
    2M_CAM_DA1# 11 12
    13 14 1 2
    R262 2M_CAM_DA1 13 14 R274 0_0402_5%
    15 16
    5M_CAM_DA1# 15 16
    1 2 17 18 2M_CAM_RST# <6>
    <6> 5M_CAM_DA1#_R 17 18
    08/09 Add C373,C374,R271 for CAM_MCLK 19
    19 20
    20 CAM_I2C_SCL <6,26,35>
    0_0201_5% 21 22
    R271 21 22 CAM_I2C_SDA <6,26,35>+VDD_CAM_1V8_R +VDD_CAM_1V8
    23 24
    L25 @ CAM_MCLK_R 23 24
    <6> CAM_MCLK 1 2 25 26
    25 26
    4 3 27 28 1 2
    4 3 0_0201_5% 5M_CAM_DA2 27 28 R275 0_0402_5%
    SM070002N00 1 29
    29 30
    30

    1
    5M_CAM_DA2# 31 32 5M_CAM_RST# <6>
    C373 C374 31 32
    C 1 2 33 34 CAM_LED_EN <35>
    C
    1 2 22P_0201_25V8 33P_0201_50V8J 5M_CAM_CLK 33 34
    35 36 5M_CAM_PWDN <6>

    2
    OCF1210900YZF_4P 2 5M_CAM_CLK# 35 36
    37 38
    37 38
    39 40
    R264 5M_CAM_DA1 39 40
    41 42
    5M_CAM_DA1 5M_CAM_DA1# 41 42
    1 2 43 44 +VDD_VCM_3V3
    <6> 5M_CAM_DA1_R 43 44
    45 46
    0_0201_5% GND GND
    47 48
    GND GND
    PANAS_AXK8L44124BG
    R266 CONN@
    1 2 5M_CAM_DA2#
    <6> 5M_CAM_DA2#_R
    0_0201_5%
    LTCX003I300
    L26 @
    4 3

    1
    4

    1
    3

    2
    2
    SM070002N00
    Camera Board reference Acer schematic

    CAM_LED_EN
    OCF1210900YZF_4P 5M_CAM_RST#
    CAM_I2C_SCL
    R270 CAM_I2C_SDA
    1 2 5M_CAM_DA2 5M_CAM_PWDN
    <6> 5M_CAM_DA2_R
    0_0201_5% 1 1 1 1 1
    C321 C327 C334 C361 C362
    10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J
    2 2 2 2 2

    R277
    1 2 2M_CAM_CLK#
    <6> 2M_CAM_CLK#_R
    0_0201_5%
    B B
    L27 @
    4 3
    4 3
    SM070002N00
    1 2
    1 2
    OCF1210900YZF_4P reference Acer schematic
    R280
    1 2 2M_CAM_CLK
    <6> 2M_CAM_CLK_R 2M_CAM_RST#
    0_0201_5% 2M_CAM_PWDN

    R281
    1 2 2M_CAM_DA1# 1 1
    <6> 2M_CAM_DA1#_R C363 C366
    0_0201_5% 10P_0201_50V8J 10P_0201_50V8J

    L28 @ 2 2
    4 3
    4 3
    SM070002N00
    1 2
    1 2
    OCF1210900YZF_4P

    R283
    1 2 2M_CAM_DA1
    <6> 2M_CAM_DA1_R
    0_0201_5%

    R425
    1 2 2M_CAM_DA2#
    <6> 2M_CAM_DA2#_R
    0_0201_5%
    A A
    L34 @
    4 3
    4 3
    SM070002N00
    1 2
    1 2
    OCF1210900YZF_4P

    R386
    2M_CAM_DA2
    <6> 2M_CAM_DA2_R
    1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
    0_0201_5% 2011/06/20 2012/06/20 Title
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    5M Camera/ 2M Camera
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 17 of 38
    5 4 3 2 1
    5 4 3 2 1

    12/16 Modify R454 from 3G@ to LTE@ to meet SPEC.


    8/23 Modify for Leakage issue.
    +VDD_1V8_BB_TEGRA +UIM_PWR

    UIM_DATA
    UIM_RST

    UIM_CLK
    SIM_DET
    2

    2
    R285 R454

    2
    100K_0201_5% 15K_0201_5%
    D D
    D14 @ D15 @
    1 3G@ LTE@ TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 Q15

    1
    AO3413_SOT23-3

    D
    +UIM_PWR_R 3 1 +UIM_PWR
    3G@

    1
    SIM_DET UIM_DATA
    SCA00001W00 SCA00001W00

    G
    2
    T30 internal PU , reserve V_MINCARD_3V3

    2
    R287
    JSIM1 100K_0201_5%
    4 1 +UIM_PWR 3G@
    GND VCC UIM_RST
    5 2

    1
    UIM_DATA VPP RST UIM_CLK
    6 3
    I/O CLK R286 3G@
    <7> SIM_DET 7
    DET
    1 2
    8 47K_0201_1%
    D+
    1 1 9 1 1 1 1 1
    3G@ C285 3G@ C297 D- 3G@ C287 3G@ C286
    10
    10P_0201_50V8J 10P_0201_50V8J GND 39P_0201_50V8J 10P_0201_50V8J @ C288 C289 3G@ C290 3G@
    11
    GND 1U_0402_6.3V4Z 0.1U_0201_10V6K 0.047U_0201_10V6K

    1
    2 2 2 2 2 2 R76 3G@ D 2
    SIM_DET 1 2 2 Q21
    G BSS138W-7-F_SOT323-3
    1 S 3G@

    3
    TAITW_PMPAT7-08GLBS1N14H0 10K_0201_5%
    CONN@ C301 3G@
    1U_0402_6.3V4Z
    SP07000NX00 2

    Detect pin
    Normal : short GND
    C Insert Card : Open SIM CARD C

    SGA00006500
    V_MINCARD_3V3 V_MINCARD_3V3 V_MINCARD_3V3 V_MINCARD_3V3

    V_MINCARD_3V3
    1 1 1 1
    + C296 3G@ + C305 3G@ + C307 3G@ + C306 3G@
    0.1U_0201_10V6K 2200P_0201_16V7K 100U_A_6.3VM_R70M 100U_A_6.3VM_R70M 100U_A_6.3VM_R70M 100U_A_6.3VM_R70M
    2 1 1 2
    1

    2 2 2 2
    C293 C292 C295 C291 C294 10/04 Modify R55 from 2.2K to 1K.
    3G@ 3G@ 3G@ @ 3G@
    2

    1 2 2 1
    10U_0402_6.3V6M 0.01U_0201_16V7 22P_0201_25V8 8/23 Add for Discharge V_MINCARD_3V3
    8/25 Modify part form SB00000EO10 to SB00000IV00
    change Cap value to 100U +3VS V_MINCARD_3V3

    1
    R80 R55
    100K_0201_5% 1K_0201_1%
    3G@ 3G@

    2
    Q45 3G@
    B V_MINCARD_3V3 B
    5 4
    V_MINCARD_3V3 G1 S1
    3
    D1
    6
    V_MINCARD_3V3 D2
    <7,30> EN_3V3_MODEM 2 1
    G2 S2
    1

    DMN2004DWK-7_SOT363-6

    1
    R288 @
    100K_0201_5% R291 R81
    100K_0201_5% 1M_0201_1%
    2

    T30 internal PU , reserve C298 3G@ @ 3G@


    22P_0201_25V8

    2
    JMIN1
    1 2 2 1 3G_DISABLE#
    <4> 3G_WAKE# 1 2
    3 4
    3 4
    5
    5 6
    6 need check module internal PU or not , All vender.
    7 8 +UIM_PWR_R
    7 8 UIM_DATA
    9 10
    9 10 UIM_CLK
    11 12
    11 12 UIM_RST
    13 14
    13 14
    15 16
    15 16
    17 18
    17 18
    19 20 3G_DISABLE# <4>
    19 20 @
    21 22
    21 22 R292
    23 24
    23 24 USB2_N2_COMM
    25 26 1 2
    25 26 0_0402_5% 3G_USB_DN <6>
    27 28
    27 28
    29 30
    29 30 WCM-2012-900T_4P
    31 32
    31 32
    33 34 2 1
    33 34 2 1
    35 36
    35 36 3G@
    37 38
    37 38
    V_MINCARD_3V3 39 40 3 4
    39 40 3 4
    41 42
    41 42 L29
    43 44
    43 44
    45 46
    45 46 USB2_P2_COMM
    47 48 1 2
    47 48 0_0402_5% 3G_USB_DP <6>
    49 50
    LTE_GPS_RESET 49 50
    A 51 52 A
    51 52 R295
    53 54
    GND GND @
    ACES_50709-0524W-001
    CONN@ 08/05 Change L29 to mount
    1

    R92 LTE@ D LTE@


    <7,21> GPS_RESET#
    2 1 2
    G Q49 LTCX003HC00
    0_0201_5% S S TR DMN3150LW-7 1N SOT-323-3
    WWAN Card
    3

    Vth=1.4V
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    Add R92 and Q49 to GPS_RESET of LTE module . THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    3G card
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 18 of 38
    5 4 3 2 1
    5 4 3 2 1

    8/25 Modify R451&R455 from 47K 1% to 4.7K 5%


    +VDD_3V3_LCD_TEGRA +VDD_3V3_LCD_TEGRA +VDDIO_HDMI

    C299 2 1

    0.1U_0201_10V6K

    2
    C300 2 1
    R449 R450
    D
    R451 R455 4.7K_0201_5% 4.7K_0201_5% Reserved U40 0.1U_0201_10V6K
    D

    4.7K_0402_5% 4.7K_0402_5% +5VS 6 1 +VDDIO_HDMI


    IN OUT
    02/17 Change to 0201 shortpad

    2
    2

    1
    G
    5 2
    IN GND
    R420 0_0402_5% 4 3 1 R323 2
    <4> EN_HDMI_5V0 EN DIS
    1 6 DDC_SCL 1 @ 2 HDMI_DDC_SCL 0_0201_5%
    <4> DDC_SCL_R 3.3V Vth=2.0

    D
    S
    7

    5
    TMLPAD

    G
    G5287RR1U_TDFN6_1P6X1P6
    Q43A R426 0_0402_5%
    4 3 2N7002KDWH 2N SOT363-6 DDC_SDA 1 @ 2 HDMI_DDC_SDA
    <4> DDC_SDA_R

    D
    S
    1 1
    Q43B 08/04 Change U40 to SA000055200 (TDFN6)
    C400 C401
    2N7002KDWH 2N SOT363-6 4.7P_0402_50V8C 4.7P_0402_50V8C
    2 2

    07/28 Change C400,C401 to SE07147AC80

    JHDMI1
    +3VS +VDD_3V3_LCD_TEGRA
    HDMI_DET 1
    HP_DET
    2
    HDMI_TXD2P_R Utility
    12/2 Modify Q1 from SB503010010 to SB503010020 for HF request. 3
    4
    D2+
    D2_Shield
    HDMI_TXD2N_R 5
    HDMI_TXD1P_R D2-
    6
    D1+

    1
    7
    R24 R436 HDMI_TXD1N_R D1_Shield
    8 20
    32.4K_0402_1% 1M_0201_1% HDMI_TXD0P_R D1- GND0
    9 21
    D0+ GND1
    1

    C 10 22 C
    D0_Shield GND2
    2

    2
    G

    Q1 HDMI_TXD0N_R

    G
    11 23

    2
    R25 FDV301N_G 1N SOT23-3 HDMI_TXCP_R D0- GND3
    12
    162K_0402_1% HDMI_DET CK+
    3 1 1 3 HDMI_DET_T30S <4> 13
    2 HDMI_TXCN_R CK_Shield
    S

    SC100000S00 14

    S
    2

    D1 HDMI_CEC_CON CK-
    15
    CEC
    RB751S40T1_SOD523-2~D 16
    Q39 DDC/CEC_GND

    1
    HDMI_DDC_SCL 17
    SCL

    1
    D2 @ C67 R448 SSM3K7002FU_SC70-3 HDMI_DDC_SDA 18
    1

    HDMI_CEC_CON 1000P_0201_16V7K 100K_0201_5% SDA


    2 1 +VDDIO_HDMI 19
    <7> HDMI_CEC +5V

    2
    RB751S40T1_SOD523-2~D BELLW_80082-5021

    2
    CONN@
    SC100000S00
    DC232001M10
    HDMI Type D Connector

    08/05 Change L30-L33 to SM070002N00

    1 R310 2 HDMI_TXD0P_R 1 R311 2 HDMI_TXD1P_R


    <4> HDMI_TXD0P <4> HDMI_TXD1P
    @ 0_0201_5% @ 0_0201_5%

    L30 L31
    4 3 4 3
    4 3 4 3
    SM070002N00 SM070002N00
    1 2 1 2
    1 2 1 2
    OCF1210900YZF_4P OCF1210900YZF_4P
    B B

    1 R312 2 HDMI_TXD0N_R 1 R313 2 HDMI_TXD1N_R


    <4> HDMI_TXD0N <4> HDMI_TXD1N
    @ 0_0201_5% @ 0_0201_5%

    <4> HDMI_TXCP 1 R314 2 HDMI_TXCP_R


    <4> HDMI_TXD2P 1 R315 2 HDMI_TXD2P_R
    @ @ 0_0201_5%
    0_0201_5%
    L32 L33
    4 3 4 3
    4 3 4 3
    SM070002N00 SM070002N00
    1 2 1 2
    1 2 1 2
    OCF1210900YZF_4P OCF1210900YZF_4P

    1 R317 2 HDMI_TXCN_R 1 R318 2 HDMI_TXD2N_R


    <4> HDMI_TXCN <4> HDMI_TXD2N
    @ 0_0201_5% @ 0_0201_5%

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDMI
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 19 of 38

    5 4 3 2 1
    5 4 3 2 1

    08/09 Add C381,C382 for VBUS_USB +3VS


    33P_0201_50V8J 2 1 C383 C382 1 2 33P_0201_50V8J

    0.1U_0201_10V6K 2 1 C377 C381 1 2 0.1U_0201_10V6K VDD_1V8_PMU_VRTC VDD_1V8_PMU_VRTC

    1
    JDOCK1
    1A (Max) 1 2 1A (Max) R316
    +5VS 1 2 VBUS_USB
    08/09 Add C377,C383 for +5VS 3
    3 4
    4 0_0201_5%

    1
    5 6
    5 6

    1
    7 8 08/09 Add C385,C386 for DC_IN R433

    2
    7 8 1.5 A
    <6> USB1_ID 9
    9 10
    10 DC_IN 08/12 Delete C385 R432 56K_0201_1%
    <6,27> ENABLE_USB_HOST 11 12 100K_0201_5% +3VS_VB
    11 12 C386
    13 14 1 2 33P_0201_50V8J

    2
    13 14
    15 16 HDRST <32>

    2
    <6> USB_HOST_DN 15 16
    17 18 2
    <6> USB_HOST_DP 17 18

    1
    D
    19 20
    19 20 Q4 C303
    21 22 LINE_OUT_DET# <7> <7> HOT_RST# 2
    <6> USB1_DN 21 22 DEBUG_UART1_RX G BSS138W-7-F_SOT323-3
    23 24 DEBUG_UART1_RX <7> 0.1U_0201_10V6K
    <6> USB1_DP 23 24 1
    25 26 S

    3
    D 25 26 D
    <6> COMPASS_DRDY 27
    27 28
    28 for IR function
    <7,16> GEN1_I2C_SCL GEN1_I2C_SCL 29 30
    GEN1_I2C_SDA 29 30
    31 32
    <7,16> GEN1_I2C_SDA 31 32 VDD_1V8_PMU_VRTC +VDD_1V8_CAM_TEGRA
    +VDD_1V8_SENSOR 33 34 LINE_DOCK_L <15>
    HOT_RST# 33 34
    35 36 LINEGND <15>
    35 36 VB_N
    <27> DOCK_DET_R# 37 38 LINE_DOCK_R <15>
    37 38
    +VDD_3V3_SENSOR 39 40
    39 40

    1
    <4> POUT_3G_1 41
    41 42
    42 AMIC_R+ <15> 02/17 Change to 0201 shortpad
    43 44 AMIC_R- <15> R429 R431
    43 44
    45 46 100K_0201_5% 100K_0201_5%
    GND GND

    1
    D
    47
    GND GND
    48 02/22 Change to 0201 shortpad R320 0_0201_5%
    Q20 2 2 1 VIB_EN_T30S <4>

    2
    PANAS_AXK8L44124BG BSS138W-7-F_SOT323-3 G
    D21
    CONN@ R324 0_0201_5% S @
    Docking / Board

    1
    LTCX003I300 DOCK_DET_R# 1 2 1 2 DOCK_DET# <6>
    R321
    2 RB751V-40_SOD323-2 100K_0201_5%
    27P_0201_25V8 2 1 C376 08/09 Add C375,C376 for B+
    08/13 Add EN_P_SENSOR for P-sensor PWR Switch C146
    VIBRATOR

    2
    0.1U_0201_10V6K 2 1 C375 4.7U_0402_6.3V6M
    JFUN1 +VDD_1V8_AUDIO 1
    1
    B+ <27> O_LED_CTL 2
    1
    2

    1
    <27> W_LED_CTL 3
    3 SP01000QQ00 10/19 Add R324 and C146 to Dock_DET# for debouncing.
    4 R9 10/19 Change power domain from +VDD_1V8_CAM_TEGRA to VDD_1V8_PMU_VRTC
    +3VS_VB VB_N 5
    4
    100K_0201_5% 10/31 Modify C146 from 0.1U to 4.7U for Acer HW request. 0208 Add R327 and R328 to HP RIGHT& LEFT to reduce cost.
    EN_P_SENSOR 5
    <4> EN_P_SENSOR 6
    6 11/7 Add D21 R431 to DOCK_DET_R# leakage issue. 0208 Unmont U3 for cost down.
    7 R28 0316 mont U3; unmount R327 and R328 for PVT debug.

    2
    7 HP_IN
    remove POUT_WIFI net on JFUN1 T19
    @ PAD
    T20@ PAD 8
    8
    1 2 HP_DET# <6> 0325 Unmont U3; mount R327 and R328 for cost down.
    <4,7> VOL_UP# 9 1K_0201_1% 2
    9
    <4,7> VOL_DOWN# 10
    10 C9
    +VDD_3V3_SENSOR 11
    11 0.1U_0201_10V6K
    <4> POUT_3G 12
    12 1 +VDD_3V3_GMI_TEGRA
    13
    13 +VDD_1V8_BB_TEGRA HP_R HP_RIGHT
    <7> ONKEY# 14 1 2
    14 R327 0_0201_5%
    15
    15
    <7> SC_LOCK# 16
    16 HP_L HP_LEFT
    C +VDD_1V8_SENSOR 17 1 2 C
    17 R328 0_0201_5%
    18
    <6> LIGHT_INT
    19
    18 Flash LED / Board 1
    19

    1
    GEN1_I2C_SDA 20 JLED1 C397
    GEN1_I2C_SCL 20 R234 0.1U_0201_10V6K
    21 <35> LED+ 1
    21 1 2
    22
    22 <35> LED- 2
    2 100K_0201_5% For debug port leakage
    HP_IN 23
    23
    24

    2
    HP_LEFT 24 D19 U3 @
    25
    25 RB751V-40_SOD323-2
    26 3 A2 A1 DEBUG_UART1_TX <7>
    26 GND1 V+ NO2

    3
    HP_RIGHT 27 4 DEBUG_UART1_RX 2 1 A3 B1 HP_RIGHT
    27 GND2 <7> DEBUG_UART1_RX NO1 COM2
    28 D16 HP_LEFT B3 C1
    <15> COM_MIC 28 COM1 NC2 HP_R <15>
    29 ACES_50281-0020N-001 C3 D1
    29 <15> HP_L NC1 IN2
    30 CONN@ D3 D2
    <15> EAR_JACK_GND 30 <7> UART_SW IN1 GND
    31
    G1 close to JLED1 SP02000S000
    32 TS5A22362YZPR_DSBGA10

    1
    G2 TVNST52302AB0_SOT523-3
    ACES_88196-3041
    SCA00001W00
    1

    CONN@
    SA00005AE00
    HPGND <15>

    1
    R347
    9/15 Add D16 to Compal ESD request. 9/29 Modify U3 from TS5A22364 to TS5A22362.
    1

    0_0201_5% R210
    @
    Function / Board 100K_0201_5% SA00004ON00------>SA00005AE00
    2

    R345 @
    0_0201_5%
    HP Switch

    2
    2

    10/13 Modify R345 from mount to @ for Acer AUDIO request.


    02/02 Add AND gate/RC delay schematics for ONKEY# function.
    Micro SD +VDD_3V_SD
    +VDD_3V_SD
    02/17 Add C402 to B+.

    B
    reference NV schematic 02/21 Change U57 from AND gate to Rest IC. B
    03/26 Change C392 from 0.022uF to 0.018uF for Acer request.
    @
    1

    47K_0402_1%

    2
    C311
    R337

    Remove R332 0.01U_0201_16V7 C312


    B+ B+
    1U_0402_6.3V4Z

    1
    2
    2

    2
    reference PBJ20
    R273
    reserve for 33 0hm 100K_0201_5%

    JMSD1 U57

    1
    R343 2 1 0_0201_5% SDMMC_DAT2_R 1 1 6 R403 0_0201_5%
    <5> SDMMC_DAT2 R342 2 DAT2 MRDLY VCC
    1 0_0201_5% SDMMC_DAT3_R 2 2 5 1 2 A_ONKEY# <32>
    <5> SDMMC_DAT3 R341 2 SDMMC_CMD_R DAT3 GND RESET ONKEY#
    1 0_0201_5% 3 3 4
    <5> SDMMC_CMD CMD CD MR
    Detect pin 4 11

    0.018U_0402_16V7K
    R368 2 SDMMC_CLK_R VDD G1
    Normal : Open <5> SDMMC_CLK 1 0_0201_5% 5 12 1 1 G677L308A31U_ADFN6_1P5x1P5
    CLK G2
    6 13 1 1 R400 2
    Insert Card : Short GND R340 2 Vss G3
    1 0_0201_5% SDMMC_DAT0_R 7 14 @ 0_0201_5%
    <5> SDMMC_DAT0 R339 2 SDMMC_DAT1_R DAT0 G4
    1 0_0201_5% 8 15 C392 C404 C402 @
    <5> SDMMC_DAT1 DAT1 G5 2 2 0.1U_0201_10V6K 0.1U_0201_10V6K
    <7> SD_DET# 9
    DETECT1 2
    2 1 10
    R344 DETECT2
    1 0_0201_5% PROCO_879S-R010-00A0
    C325 CONN@
    10P_0201_50V8J
    reference Acer schematic 2
    11/28 Change JMSD1 form SP07000GQ00 to SP07000TV00
    SDMMC_CLK_R
    SDMMC_DAT0_R
    SDMMC_DAT1_R
    SDMMC_DAT2_R
    A SDMMC_DAT3_R A
    SDMMC_CMD_R

    1 1 1 1 1 1
    C367 C368 C369 C370 C371 C310
    10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J 10P_0201_50V8J
    2 2 2 2 2 2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    S/B conn / Vibrator / Micro SD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Wednesday, March 28, 2012 Sheet 20 of 38
    5 4 3 2 1
    5 4 3 2 1

    +2V8_GPS

    9/02 Modify C315 from GPS@ to @ for RF team request.


    C313
    GPS@
    1
    9/10 Modify C315 from 1.8P to 2.2P for RF team request. L35 1 2 BLM15AG601SN1D_2P 1 2

    1
    C322 L39 9/14 Modify L38 from 6.2NH to 7.5P for RF team request.
    GPS@ GPS@ 2.2U_0402_6.3V6M
    0.1U_0201_10V6K 2 47NH_LQG15HN47NJ02D_5% 12/7 Modify L38 from 7.5P to 0 ohm for RF team request. GPS@
    Antenna 12/7 Modify C315 from 2.2P to 5.1nH for RF team request. U47

    H10
    J10
    L37 GPS@

    K7

    K6
    2
    GPSANT SAFFB1G58KA0F0AR14_5P
    2 C314 GPS@ L38 GPS@

    GPS_VDDPL
    Ground

    GPS_VDDIF

    VDD1P2_GRF
    GPS_VDDLNA
    3 1 GPS_ANT1 1 2 GPS_ANT2 1 4 GPS_ANT3 1 2 GPS_ANT4 K9
    Input Output GPS_RFIP
    4
    22P_0402_50V8J 1 0_0201_5%
    D D
    I-PEX_20429-001E 2 2

    GND
    GND
    GND
    CONN@ C315
    D9 @ 5.1NH_0.3NH_LQG15HN5N1S02D D17 @
    SP060004L00 1P_0402_50V NPO 2 GPS@ 1P_0402_50V NPO J8
    RF

    2
    3
    5
    1 1 GPS_VSSIF
    07/27 Change GPSANT from J9
    GPS_VSSPLL GPS_AUXOP
    J7
    LTCX003HH00 to SP060004L00 K8
    GPS_VSSLNA
    K10 H8
    GPS_VSSLNA GPS_AUXON
    close to GPSANT E10
    GND_IFP

    9/15 Add D17 to Compal ESD request.


    9/15 Add D9 to Compal ESD request.
    +GPS_AUX_OUT +1V8_GPS

    A4
    GPS_CAL CLK IF
    GPS_CLK_26M_R G10
    TCXO
    1 B7
    CAL_REQ
    1 C316 remove reserve 32K from T30S GPS_CLK_32K_R K2
    LPO_IN
    0.01U_0201_16V7 H9
    C379 GPS@ NC
    F10 F9
    0.1U_0201_10V6K 2 NC NC
    GPS@ 2 F8
    GPS@ NC
    6

    4
    X2 X3 G9
    GPS_CLK_26M 1 NC
    4 2 GPS_CLK_26M_R GPS@
    VCC

    VDD
    OUTPUT R352 GPS@ 0_0402_5%
    1
    OE Clock Output
    3 GPS_CLK_32K R351 1 GPS@ 2 0_0402_5% GPS_CLK_32K_R
    SYS IF AUX_HI
    K4
    GPS@
    2 H6 +GPS_AUX_OUT C318 2 1 0.22U_0201_6.3V6M
    ENABLE/DISABLE 26MHZ_10PF_TX5651 VDD_AUX_O
    5 H7 +3V3_GPS
    NC VDD_AUX_IN
    1
    GND

    GND
    NC
    A6
    HOST_REQ
    A8
    GPS_SYNC/PPS_OUT
    02/17 Change to 0201 shortpad B6
    3

    2
    32.768KHZ_15PF_KK3270032 LNA_EN
    A7
    IFVALID
    C C
    R383 1 @ 2 0_0201_5% GPS_RESET#_R A5 A3
    <7,18> GPS_RESET# RST_N C_GPIO_6
    B5
    R416 1 @ GPS_PWRON_R C_GPIO_7
    <7> GPS_PWRON 2 0_0201_5% J4
    REGPU
    A2
    D_GPIO_5
    H2 H1 C317
    TM1 D_GPIO_6
    K1
    GPS_PWRON_R TM2 GPS_REF_CAP
    B3 J6 1 2
    TM3 REF_CAP

    UART/I2C IF 0.01U_0201_16V7

    1
    R348 GPS@ D2 GPS@
    C_GPIO_2
    100K_0201_5% C1
    C_GPIO_3 R417 0_0201_5%
    E1 1 2 GPS_UART_RXD <7>
    SCL2/UART_TX R421 0_0201_5%
    SB00000SM00 D1 1 2 GPS_UART_TXD <7>

    2
    +1V8_GPS SDA2/UART_RX R434 0_0201_5%
    B2 1 2 GPS_UART_CTS# <7>
    VDD_1V8_GEN UART_nRTS
    Q28 Acer request UART_nCTS
    A1 R435 1 2 0_0201_5%
    GPS_UART_RTS# <7>

    4 3
    MEMORY
    2 F2 E5
    NC NC
    1

    5 1 2 1 F7 B1
    NC NC
    1

    C323 H3 E6
    GPS@ R303 C332 C326 C353 C324 NC NC
    6 H4 D4
    2

    1U_0402_6.3V4Z 1M_0402_1% 0.1U_0201_10V6K 4.7U_0402_6.3V6M NC NC


    1 1U_0402_6.3V4Z 68P_0201_25V8 J2 C4
    2

    GPS@ GPS@ 2 GPS@ 1 2 GPS@ NC NC


    GPS@ G8 E3
    NC NC
    FDG6331L_SC70-6 G7 F6 9/25 Modify R346 from @ to mount for leakage issue.
    2

    NC NC
    GPS@ J1 E7
    NC NC
    G6 C2
    NC NC +1V8_GPS
    G4 D10
    <7> EN_VDD_GPS Vth = 1.5 NC NC
    G1 B4
    NC NC
    1

    F1 A9
    1.8V NC NC
    G5 A10
    NC NC

    1
    R304 C10 B9
    1M_0402_5% NC NC R346
    C8 C9
    NC NC
    D5 B10
    2

    B NC NC 100K_0201_5%
    B

    10/06 Modify R304 from @ to mount. D8 F5

    2
    NC NC
    D6 E4
    NC NC GPS_UART_RXD
    D9 E2
    NC NC

    +3V3_GPS J5
    VDD_BAT
    R428 1 GPS@ 2 VDD_PRE H5 E8
    0_0402_5% VDD_PRE NC
    GPS_VDDC E9
    VDDIFP
    PWR AVSS
    J3
    G2 K3
    VDDC AVSS
    C7
    VDDC
    C3
    VDDC
    K5 G3
    VDD1P2_CORE VSSC
    F4
    VSSC
    +1V8_GPS C6 B8
    VDDIO VSSC
    SB00000SM00 +3V3_GPS
    D7
    VDDIO VSSC
    C5
    F3 D3
    +3VS Q29 VDDIO VSSC

    4 3 BCM47511IFBG_FBGA100

    GPS@
    5
    2
    SA00004YJ00
    1

    +3V3_GPS
    1 2
    1

    C330 R305 6 U50


    1U_0402_6.3V4Z 1M_0402_1% 1 C331 C333 C347
    2

    GPS@ GPS@ 1U_0402_6.3V4Z 2.2U_0402_6.3V6M 68P_0201_25V8 1


    2

    FDG6331L_SC70-6 GPS@ 2 GPS@ 1 VIN


    GPS@
    2

    GPS@ 1 5 +2V8_GPS
    C329 VOUT
    2
    VDD_PRE GPS_VDDC GND C335
    1
    EN_VDD_GPS 1U_0402_6.3V4Z 4 GPS@
    GPS@ 2 GPS_PWRON_R NC
    1 1 3
    1.8V Vth = 1.5 EN 2.2U_0402_6.3V6M
    A A
    C319 C320 Vth=1.6V 2
    2.2U_0402_6.3V6M 2.2U_0402_6.3V6M APL5603-28BI-TRG_SOT23-5
    2 2 GPS@
    @ GPS@
    SA00004BW00
    For Antenna circuit

    Security Classification Compal Secret Data Compal Electronics, Inc.


    2011/06/20 2012/06/20 Title
    GPS POWER SOURCE Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    GPS BCM47511
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 21 of 38
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    SB00000SM00 +3VS_WIFI
    Q31

    4 3
    dual-Band wifi RF matching , Reserve " 2 Pi " filter
    2
    9/10 Modify C136 from 100P to 1P for RF request.

    1
    5 1 1 2 WIFANT

    1
    C337 C342
    2

    Ground
    1U_0402_6.3V4Z R308 6 C339 C341 C340
    2.4RF_IN_L R375 1 WIFI@ 2 0_0402_5% 2.4RF_IN_R R387 1 WIFI@ 2 0_0402_5% 2.4RF_IN

    2
    WIFI@ 1M_0402_1% 4.7U_0402_6.3V6M 0.1U_0201_10V6K 1 3
    1 1U_0402_6.3V4Z 68P_0201_25V8

    2
    WIFI@ WIFI@ 2 WIFI@ 2 WIFI@ 1 4
    WIFI@ 2 2 2
    FDG6331L_SC70-6
    I-PEX_20429-001E

    2
    WIFI@ C136 @ C137 @ C138 @ CONN@
    1P_0402_50V NPO 100P_0402_50V8J 100P_0402_50V8J
    D
    1 1 1 SP060004L00 D
    <4> EN_WIFI_VDD Vth = 1.5 07/27 Change WIFANT from

    1
    LTCX003HH00 to SP060004L00
    R307
    1M_0402_5%
    @

    2
    SB00000SM00 AH662 use 1U, AH663 use 0.1U
    VDD_1V8_GEN +1.8VS_WIFI
    Q32 8/23 Add for AH663.
    +SR_PA_OUT +VDD_WL_PA 9/21 Add D10 to Compal ESD request.
    4 3 2.4RF_IN
    C356

    2
    2 AH663@
    1

    5 C356 C359
    2
    1

    C348 1U_0402_6.3V4Z 1U_0402_6.3V4Z


    SE070104Z80

    1
    1 1 2

    1
    1U_0402_6.3V4Z R319 6 NH660@ WIFI@ D10 @
    2

    WIFI@ 1M_0402_1% 1 C349 C354 C352 C351 1P_0402_50V NPO


    WIFI@ 0.1U_0201_10V6K 4.7U_0402_6.3V6M 0.1U 16V V4Z 1
    1U_0402_6.3V4Z 68P_0201_25V8

    2
    FDG6331L_SC70-6 WIFI@ 2 WIFI@ 2 WIFI@ 1
    WIFI@
    2

    WIFI@ close to H2 close to G9 close to WIFANT

    EN_WIFI_VDD

    Vth = 1.5 +SR_PA_OUT +VDD_LN

    +3VS +3VS_WIFI +3VS_WIFI +VDD_WL_PA


    10/19 Add for Discharge +3VS_WIFI reserve

    1
    C R361 1 @ C
    2 0_0402_5%
    R93 R94
    100K_0201_5% 1K_0201_1% +VDD_CORE
    2 B+

    2
    Q47 +VDD1P4_WIFI
    Q37
    5 4 1
    G1 S1 VDD
    3 5
    D1 VOUT
    6 2
    EN_WIFI_VDD D2 1 1 GND
    2 1 4
    G2 S2 +1.8VS_WIFI VFB

    2
    C343 C350 3 1 1
    DMN2004DWK-7_SOT363-6 4.7U_0402_6.3V6M 0.1U_0201_10V6K CE R356
    WIFI@ 2 WIFI@ 2 RP111N331D-TR-FE_SOT23-5 C378 C346
    0_0201_5%
    WIFI@ WIFI@
    WIFI@ 2 2 WIFI@

    1
    0.1U_0201_10V6K
    +3VS_WIFI 4.7U_0402_6.3V6M

    +CBUCK_OUT
    +VDD_WL_PA

    +VDD_WL_PA

    +VDD_LN

    1
    FM power <4> EN_WIFI_VDD R456 @

    1
    15K_0402_5%
    R389

    G9

    2
    H9
    H2

    C1

    C2
    D1

    H1
    A2

    A3

    B9

    B1

    B4
    B3

    E2
    J3
    U53 1M_0201_1%
    +1.8VS_WIFI WIFI@

    VBAT_IN

    VOUT_2P5_IN

    VDD_LN_IN
    SR_PA_OUT

    VDDIO_RF

    CBUCK_OUT

    VOUT_2P5_OUT

    VIN_LDO

    VDD_LN_OUT
    VDD1P2_CLDO_OUT

    VDDIO
    VDD_WL_PA_A_MODE

    VDD_BT_PA
    VDD_WL_PA

    VDD_CORE

    2
    A8
    WFMMC_CMD_R R367 @ FM_AUDIO_L
    1 2 100K_0201_5% A7
    FM_AUDIO_R
    F1,F2,F3,G2,G3 internal weak pull up resister to VDDIO
    R272 A6
    WFMMC_CLK_R ANT_FM_TX
    <5> WFMMC_CLK 1 2 G1 A5
    R373 WIFI@ 0_0201_5% WFMMC_CMD_R SDIO_CLK_SPI_CLK ANT_FM_RX
    <5> WFMMC_CMD 1 2 G3
    B
    0_0201_5% R374 WIFI@ 0_0201_5% WFMMC_DAT0_R SDIO_CMD_SPI_DI 2.4RF_IN_L B
    1 <5> WFMMC_DAT0 1 2 F2 J7
    SDIO_DATA0_SPI_DO ANT_2G4_5G
    1

    R376 1 WIFI@ 2 0_0201_5% WFMMC_DAT1_R F1


    <5> WFMMC_DAT1 SDIO_DATA1_SPI_IRQ
    @ C387 @ C388 R377 1 WIFI@ 2 0_0201_5% WFMMC_DAT2_R G2 H4 +1.8VS_WIFI
    <5> WFMMC_DAT2 SDIO_DATA2_SPI_NC ANT_MAIN_EN
    22P_0201_25V8 33P_0201_50V8J R378 1 WIFI@ 2 0_0201_5% WFMMC_DAT3_R F3 H6
    <5> WFMMC_DAT3
    2

    2 SDIO_DATA3_SPI_CS ANT_AUX_EN

    D7
    BT_I2S_DI

    1
    D5
    BT_I2S_DO
    08/09 Add C387,C388,R272 for WFMMC_CLK E6
    WL_GPIO_1 BT_I2S_WS
    C7 R366
    08/25 Modify C387&C388 from mount to unmount E4
    WL_GPIO_2 BT_I2S_CLK
    B6 100K_0201_5%
    02/17 Change to 0201 shortpad
    D6

    2
    WL_GPIO_5
    C6 G4 BT_PCM_SYNC <7>
    R382 0_0201_5% WL_GPIO_6 BT_PCM_SYNC BT_UART_RXD
    F5 BT_PCM_CLK <7>
    @ WF_RST#_R BT_PCM_CLK
    <7> WF_RST# 1 2 D2 F4 BT_PCM_OUT <7>
    TP36 WL_SHUTDOWN#_RST# BT_PCM_IN
    <7> WF_WAKE# F6 G5 BT_PCM_IN <7>
    WL_HOST_WAKE BT_PCM_OUT
    TP34 E3 02/17 Change to 0201 shortpad
    TP35 WL_UART_TX
    G7 C8 @ PAD T11 BT_WAKEUP <7>
    WL_UART_RX BT_DEVICE_WAKE
    C345 WIFI@ 0.01U_0201_16V7 B7 @ PAD T12 BT_IRQ# <7>
    BT_HOST_WAKE R381 0_0201_5%
    1 2 C3 @ PAD T13 BT_PD# <7>
    +SR_PA_OUT BT_SHUTDOWN# @
    H3 C4 1 2 BT_RST# <7>
    HSIC_DATA BT_RST#
    C344 WIFI@ 4.7U_0402_6.3V6M J2
    HSIC_STROBE
    1 2
    E7 R365 1 WIFI@ 2 0_0201_5%
    BT_UART_RTS# BT_UART_CTS# <7>
    F7 R370 1 WIFI@ 2 0_0201_5%
    BT_UART_CTS# BT_UART_RTS# <7>
    R384 1 WIFI@ 2 0_0402_5% RTC_32K_WIFI D3
    <7> CLK_32K_OUT RTC_CLK
    F8 R371 1 WIFI@ 2 0_0201_5%
    BT_UART_TXD BT_UART_RXD <7>
    E8 R369 1 WIFI@ 2 0_0201_5%
    BT_UART_RXD BT_UART_TXD <7>
    H8
    NC
    8/22 Change BOM structure
    C355 WIFI@ D9
    NC
    +VDD_LN 1 2
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND

    U53
    4.7U_0402_6.3V6M
    8/22 Change BOM structure NH660@
    A1
    A4
    A9
    B2
    B5
    B8
    C5
    C9
    D4
    D8
    E1
    E5
    E9
    F9
    G6
    G8
    H5
    H7
    J1
    J4
    J5
    J6
    J8
    J9
    A10
    C10
    E10
    G10
    J10

    A C358 WIFI@ 0.01U_0201_16V7


    AH663@ AW-AH663_86P PK29S003400 A

    +VDD_CORE 1 2
    L40 WIFI@
    PK29S003200
    +VDD1P4_WIFI 1 2 +CBUCK_OUT Footprint use AH662 co-lay
    C357 WIFI@ 4.7U_0402_6.3V6M
    1 2 C336 WIFI@ 2.2UH_VLS252012T-2R2M1R3_1.8A_20%
    2 1

    10U_0402_6.3V6M

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    WIFI/BT AH662
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 22 of 38
    5 4 3 2 1
    5 4 3 2 1

    R395 1 2 0_0201_5% 10mA R391 1 2 0_0201_5% 110mA


    From PMU VDD_1V8_GEN +VDD_1V8_SDMMC3_TEGRA +3VS +VDD_3V3_GMI_TEGRA
    From PMU VDD_PMU_LDO3 R442 1 2 0_0402_5% +VDD_3V3_SDMMC1_TEGRA
    10mA
    R397 1 2 0_0201_5% 10mA R396 1 2 0_0201_5% 130mA
    +VDD_1V8_AUDIO_TEGRA +AVDD_3V3_USB_TEGRA
    R412 1 2 0_0402_5% 30mA
    VDD_PMU_LDO8 +VDD_1V0_DDR_HS_TEGRA
    R399 1 2 0_0201_5% 10mA R419 1 2 0_0201_5% 50mA
    +AVDD_1V8_USB_PLL_TEGRA +VDD_3V3_DDR_RX_TEGRA
    VDD_PMU_LDO6 R410 1 2 0_0402_5% 56mA
    +AVDD_1V2_DSI_CSI_TEGRA
    R401 1 2 0_0201_5% 10mA R418 1 2 0_0201_5% +VDD_3V3_LCD_TEGRA 10mA
    +VDD_1V8_CAM_TEGRA
    VDD_PMU_LDO7 R411 1 2 0_0402_5% 54mA
    +AVDD_1V1_PLL_TEGRA
    R404 1 2 0_0201_5% 10mA
    +VDD_1V8_BB_TEGRA
    R407 1 2 0_0402_5% 20mA
    VDD_PMU_LDO4 +VDD_1V2_RTC_TEGRA
    R406 1 2 0_0201_5% 10mA
    +VDD_1V8_SYS_TEGRA
    R422 1 @ 2 0_0402_5% 200mA
    VDD_PMU_LDO1 +VDD_2V85_EMMC
    R398 1 2 0_0402_5% 20mA
    +VDD_1V8_DDR_MEM
    VDD_PMU_LDO5 R408 1 2 0_0402_5% 135mA
    +VDD_VCM_3V3
    R101 1 2 0_0402_5% 200mA
    +VDDIO_1V8_EMMC
    R441 1 2 0_0402_5% 45mA
    D VDD_PMU_LDO2 +VDD_3V_SD D
    R157 1 2 0_0402_5% 33mA
    +VDD_1V8_AUDIO
    VDD_1V2_MEM R444 1 2 0_0402_5% 475mA
    +VDD_1V2_DDR_MEM
    R390 1 2 0_0201_5% 10mA
    +VDD_1V8_SDMMC4_TEGRA
    R402 1 2 0_0201_5% 10mA
    +VDD_1V8_UART_TEGRA 12/08 Add U51, C365 , C385 and R437 for EMMC drop issue.
    12/16 Modify U51, C365 , C385 and R437 from @ to mount.
    Must change to correct symbol&footprint

    +3VS
    +VDD_2V85_EMMC
    U51
    1
    VIN R437
    1 5 1 2
    C385 VOUT
    2
    2.2U_0402_6.3V6M GND 0_0402_5%
    2
    4
    2 VDD_PMU_LDO1 NC C365
    3
    EN
    1U_0402_6.3V4Z
    1
    G9001-300TO1U TSOT-23 5P LDO H1 H2 H5 H6
    H_2P3 H_2P3 H_2P3 H_2P3
    SA00005II00
    H_2P3 *6

    1
    @ @ @ @
    Q26 close to Camera Conn.

    H8
    VDD_1V8_GEN
    Q26
    ME2301A-G_SOT23-3
    +VDD_CAM_1V8
    H_2P0N *1 H_2P0N

    C
    10/04 Add R19 and Q46 to Discharge +VDD_CAM_1V8. @
    C

    1
    S

    3 1
    Q33 close to T30S
    FD1 FD2 FD3 FD4
    FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
    G

    1
    2

    1
    SB00000JL00 C33 +3VS +VDD_3V3_FUSE_TEGRA
    1U_0402_6.3V4Z Q33
    ME2301A-G_SOT23-3 @ @ @ @

    1
    2 R19
    2.2K_0201_1%

    D
    3 1
    2
    1

    G
    1
    9/2 Add CLP22~CLP27

    2
    2
    Q46 B+ SB00000JL00 C159
    G 1U_0402_6.3V4Z
    S
    S TR DMN3150LW-7 1N SOT-323-3 9/2 Add CLP28,CLP29
    3

    2
    11/8 Del CLP22~CLP27 for ME request

    1
    R300
    2 1 R326
    <7> EN_CAM_1V8#
    100K_0201_5% 1
    200K _0201_1%
    TOP Clip type conn BOTTOM
    R325

    2
    C384 2 1
    0.1U_0201_10V6K CLP1 CLP7 CLP11 CLP17
    2 100K_0201_5% 1

    3
    C389
    Q25B 0.1U_0201_10V6K
    5 DMN2004DWK-7_SOT363-6 2
    <4> EN_T30S_FUSE_3V3
    EC0M5000700 EC0M5000700 EC0M5000700 EC0M5000700
    3.3V EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
    4
    SB00000IV00 CLP2 CLP8
    CLP12 CLP18

    9/29 Modify Q25 from 2N7002KDWH to DMN2004DWK-7


    B B
    VDD_1V8_GEN +VDD_1V8_SENSOR EC0M5000700 EC0M5000700
    Q35 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EC0M5000700 EC0M5000700
    ME2301A-G_SOT23-3 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
    S

    CLP3 CLP9 CLP13


    D

    3 1
    CLP19
    G

    1
    2

    SB00000JL00 C160
    1U_0402_6.3V4Z
    EC0M5000700 EC0M5000700 EC0M5000700
    9/2 Modify R330 to meet SPEC sequence 2 +3VS +VDD_3V3_SENSOR EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EC0M5000700
    Q38 EMIST_SUL-12A2M_1P
    ME2301A-G_SOT23-3
    CLP4 CLP10 CLP14
    S

    3 1 CLP20
    D

    R330

    <7> EN_SENSOR_1V8# 2 1
    G

    1
    2

    1
    B+ SB00000JL00 C163
    47K_0201_1% C390 @ 1U_0402_6.3V4Z EC0M5000700 EC0M5000700 EC0M5000700
    EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EC0M5000700
    0.1U_0201_10V6K 2 EMIST_SUL-12A2M_1P
    1

    2
    R414 CLP5 CLP28 CLP15 CLP21
    10/07 Modify C390 from mount to @. 200K _0201_1%

    R415
    2

    2 1

    100K_0201_5% 1 EC0M5000700 EC0M5000700 EC0M5000700 EC0M5000700


    6

    EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P


    C391
    Q25A 0.1U_0201_10V6K CLP6 CLP16
    R427 1 @ 2 0_0201_5% 2 DMN2004DWK-7_SOT363-6 2 CLP29
    9/27 Add EN_SENSOR_3V3_2 from U1.AA3 <4> EN_SENSOR_3V3
    3.3V
    A
    9/29 Modify R424 from unmout to mount A
    1

    R424 0_0201_5%
    @
    9/29 Modify R427 from mout to unmount <7> EN_SENSOR_3V3_2 1 2
    EC0M5000700 EC0M5000700
    1.8V EMIST_SUL-12A2M_1P EC0M5000700 EMIST_SUL-12A2M_1P
    EMIST_SUL-12A2M_1P
    02/17 Change to 0201 shortpad

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC interface/Power Button
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 23 of 38
    5 4 3 2 1
    5 4 3 2 1

    AC Mode
    PU7 T30S-R-A1-1.4G
    PTPS659110A2ZRCR Core Power
    PU1 T30 PWR RAIL VDD_PMU_LDO4 20mA R407_0_0402 +VDD_1V2_RTC_TEGRA
    1.0V~1.2V VDD_RTC
    VIN Charger IC PMU IC VDD_1V0_GEN 6100mA
    DC_IN VDD_1V8_GEN 0.9V~1.0V VDD_CPU
    BQ24171 VDD_1V2_SOC 2500mA
    D 1.0V~1.2V VDD_CORE D

    +3VS 40mA +VDD_3V3_FUSE_TEGRA


    PU2 Q33 3.3V VPP_FUSE

    TPS63020DSJR DDR
    GPS
    VDD_1V2_MEM 475mA
    PL3 SYSTEM +3VS 1.2V VDDIO_DDR
    Boost-Buck IC 0.37mA +1V8_GPS
    Batt. Mode Q28 1.8V VDD_PMU_LDO8 30mA R412_0_0402 +VDD_1V0_DDR_HS_TEGRA
    1.05V VDD_DDR_HS
    +2V8_GPS
    U50 2.8V +3VS 50mA R419_0_0201 +VDD_3V3_DDR_RX_TEGRA
    3.3V VDD_DDR_RX

    Battery
    BATT+ B+ Q29
    250mA +3V3_GPS
    3.3V
    LCD
    PR19 +3VS 10mA R418_0_0201 +VDD_3V3_LCD_TEGRA
    1S2P PU4 3.3V VDDIO_LCD
    WIFI/BT
    Charge G5910-50RBU_TDFN6 HDMI
    800mA +1.8VS_WIFI +3VS 15mA Q2 +AVDD_3V3_HDMI_S
    Charge PUMP VDD_5V0_SBY Q32 1.8V 3.3V AVDD_HDMI
    Boost IC 80mA L2 AVDD_HDMI_PLL
    20mA +3VS_WIFI 3.3V 1.8V AVDD_HDMI_PLL
    Q31
    SD Card
    VDD_PMU_LDO3 10mA R442_0_0402 +VDD_3V3_SDMMC1_TEGRA
    3.3V VDDIO_SDMMC1
    PU3 WiFi
    Touch Panel
    TPS61030RSAR 10mA R395_0_0201 +VDD_1V8_SDMMC3_TEGRA
    C
    1.8V VDDIO_SDMMC3 C

    SYSTEM +5VS L14 5V


    Buck IC Audio
    10mA R397_0_0201 +VDD_1V8_AUDIO_TEGRA
    1.8V VDDIO_AUDIO

    Camera
    VDD_PMU_LDO6 56mA R410_0_0402 +AVDD_1V2_DSI_CSI_TEGRA
    PU2 1.2V AVDD_DSI_CSI
    3G CARD 10mA R401_0_0201 +VDD_1V8_CAM_TEGRA
    TPS63020DSJR 1.8V VDDIO_CAM
    BATT+ 2750mA
    3G V_MINCARD_3V3 3.3V
    USB
    Boost-Buck IC +3VS 130mA R396_0_0201 +AVDD_3V3_USB_TEGRA
    3.3V AVDD_USB
    +3VS 10mA R399_0_0201 +AVDD_1V8_USB_PLL_TEGRA
    1.8V AVDD_USB_PLL
    PU6
    OSC
    OZ9979LN-A3-0-TR LVDS Panel L3
    10mA AVDD_OSC
    20mA 1.8V AVDD_OSC
    BACK LIGHT +VDD_LED_BL 12V
    Boost IC eMMC
    10mA R390_0_0201 +VDD_1V8_SDMMC4_TEGRA
    1.8V VDDIO_SDMMC4
    PU9 SYSTEM
    AMP
    TPS61050YZGR LED Board 10mA R406_0_0201 +VDD_1V8_SYS_TEGRA
    1.8V VDDIO_SYS
    R445_0_0402 LED+ 1500mA
    B 5V LED flash B

    LED- 3V VDD_PMU_LDO7 54mA R411_0_0402 +AVDD_1V1_PLL_TEGRA


    Boost IC 1.1V AVDD_PLL
    +AMP_VDD 400mA
    10mA R404_0_0201 +VDD_1V8_BB_TEGRA
    Camera 1.8V VDDIO_BB
    G Sensor Light Sensor 180mA
    R275_0_0402 +VDD_CAM_1V8 10mA R402_0_0201 +VDD_1V8_UART_TEGRA
    NCT1008CMT3R2G 1.8V Q26 1.8V VDDIO_UART
    1.8V 1.8V
    +VDD_CAM_1V8_R 110mA R391_0_0201 +VDD_3V3_GMI_TEGRA
    THERMAL 2.8V 1.8V VDDIO_GMI
    0.10mA 0.4mA
    Gyro Sensor
    +3VS_TH
    3.3V VDD 0.67mA 180mA
    1.8V +VDD_CAM_2V8_R MT46H64M32L2JG
    3.3V R274_0_0402
    DDR
    6.5mA
    20mA R398_0_0402 +VDD_1V8_DDR_MEM
    1.8V VDD1
    +VDD_CAM_2V8
    P Sensor VDD_1V2_MEM 180mA R444_0_0402 +VDD_1V2_DDR_MEM
    +VDD_3V3_SENSOR 1.2V VDD2
    U39
    3.3V
    Q38
    +VDD_1V8_SENSOR
    0.07mA Q35 eMMC
    R57_49.9_0201
    VDD_PMU_LDO1 200mA R422_0_0402 +VDD_2V85_EMMC
    0.35mA 2.85V VCC
    R157_0_0402
    +3VS
    200mA R101_0_0402 +VDDIO_1V8_EMMC
    +VDD_1V8_AUDIO 44mA 1.8V VCCQ
    U21 LCD Panel
    A
    300+171mA A

    ES305 Codec
    3.3V VDD_PMU_LDO2 45mA R441_0_0402 +VDD_3V_SD Micro SD
    DS90C387AVJD 1.8V 1.8V
    3.3V
    LVDS Transmitter
    300mA 171mA
    +LCDVDD R122_0_0201 +VDD_LVDS
    3.3V LVDSVCC

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/05/20 Deciphered Date 2012/05/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power Tree
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 24 of 38
    5 4 3 2 1
    5 4 3 2 1

    TPS61030
    Charger IC SYSTEM +5VS
    VIN BQ24171
    AC=12V Boost-Buck IC

    D D
    SWITCH B+

    +VIN_USB TPS63020
    USB=5V Battery SYSTEM +3VS
    1S2P Boost-Buck IC

    G5910
    Charge PUMP +VDD_5V0_SBY
    Boost IC

    TPS63020
    3G +V_MINICARD_3V3
    C C
    Boost-Buck IC

    Oz9979
    BACK LIGHT +VDD_LED_BL
    Boost IC

    TPS61050
    LED flash LED+
    Boost IC

    B B

    PTPS6591102AA2ZRC T30
    T30 PWR RAIL CHIP
    PMU IC

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 25 of 38
    5 4 3 2 1
    5 4 3 2 1

    SP02000V310
    ACES_88231-09001
    11
    GND BATT+
    10
    D GND D
    9
    9
    8
    8
    7
    7
    6 BATT_TEMP <27>
    6
    5
    5
    4

    33P_0402_50V8J

    1000P_0402_50V7K
    4
    3

    2200P_0402_50V7K

    0.033U_0402_16V7K
    0.01UF_0402_25V7K
    3

    1
    2 PR1 100_0402_1%
    2

    1
    PC8

    PC9

    PC11
    1 1 2 PWR_I2C_SCL <7,10,14,15,32,34>
    1

    PC1

    PC2
    2

    2
    @ PJP1 @ PR2 0_0402_5%

    2
    1 2 CAM_I2C_SCL <6,17,35>
    PR3 100_0402_1%
    2 1 PWR_I2C_SDA <7,10,14,15,32,34>
    @ PR12 0_0402_5%
    1 2 CAM_I2C_SDA <6,17,35>

    Battery I2C reserve CAM_I2C-10/31

    VIN

    C PL1 C
    DC_IN FBMA-L11-160808-301LMA20T
    1 2

    1000P_0402_50V7K

    1000P_0402_50V7K

    0.22U_0402_16V7K

    0.22U_0402_16V7K
    0.01UF_0402_25V7K
    1

    1
    PC6
    PC4

    PC5

    PC7
    PC120

    2
    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC IN/BATT IN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 26 of 38
    5 4 3 2 1
    5 4 3 2 1

    OVP UVP Range setting:


    ##OVPSET voltage is between 0.497~1.6V ## CHARGER BQ24171 AC Insert or remove --> Wake up T30S
    USB Insert or remove --> Wake up T30S
    VDD_1V8_GEN VDD_1V8_GEN

    1
    SW to check if Acer USB --> Change charge current to 1A
    1.6V*(768+100)/100=13.888V
    100K_0402_5% 100K_0402_5%
    PD1 IF=3A VF=0.5V VR=40V 0.497V*(768+100)/100=4.314V PD2 PR5 PR6
    PD3
    PR136 RB751V-40_SOD323-2
    VIN 2 1
    Setting "OVP 13.888V" & "UVP 4.314V" VIN VBUS_USB

    2
    2 1 1 2 WAKE_UP_ACIN <7> 1 2 WAKE_UP_VBUS <7>
    SBR3U40P1-7_POWERDI123-2
    Max Rds(on) 16.5mohm 4.02K_0402_1% RB751V-40_SOD323-2

    2
    Max Rds(on) 36mohm PR8

    1K_0402_1%

    0.01UF_0402_25V7K
    1

    1
    PQ17 P3 PQ3
    PQ1 PQ2 SI7716ADN-T1-GE3_POWERPAK8-5 SI7716ADN-T1-GE3_POWERPAK8-5 PC12 10K_0402_1% PC13

    PR131

    PC125
    AON7403L_DFN8-5 AON7403L_DFN8-5 P2 1 1 0.01UF_0402_25V7K 0.01UF_0402_25V7K
    PR9

    2
    1 1 2 2

    1
    VBUS_USB 5 2 2 5 5 3 3 5 1 4 Charge_in @
    3 3

    100K_0402_1%
    2.2U_0402_6.3V6M
    D D

    2
    2 3

    4
    1
    PC89

    1 PR16
    PR10 BATT+ BATT+
    4

    4
    100K_0402_1% 0.05_1206_1%
    PD4
    2 @ 3.3_1206_5% @
    PC14

    1
    PR11 1 2 CHARGER_LED#

    38.3K_0402_1%
    2

    2
    1 2 Battery OVP protect

    2
    806K_0402_1%

    PR67
    RB751V-40_SOD323-2
    2

    Change 0.22U*2 for VBUS_USB issue 10/19 SB000005N00 PR62


    10K_0402_5%
    1U_0603_25V6K
    2

    1
    PC15 0.1U_0402_25V6 PU17
    PC121

    1
    PR13

    0.01U_0603_50V7K PC16
    PC101

    1
    1
    PC17 D
    0.1U_0402_25V6 1 2 1
    1

    2
    VBUS_USB BTB_OFF VDD
    0.1U_0402_25V6 2 2

    SSM3K7002FU_SC70-3
    1

    VDD_3V3_BQ24171_VREF

    2
    6

    2
    @ PQ23A D G RESET/RESET
    3

    200K_0402_1%
    0.1U_0402_16V4Z
    2
    BTB_OFF 2.2U_0603_16V6K GND

    PR68
    1@ PR14

    BQ24171_ACN
    2 2 S

    3
    2
    806K_0402_1%

    PQ27
    G 499K_0402_1%
    2

    1
    PR114

    PC118
    S SI1034CX-T1-GE3_SC89-6 PR127

    10U_0805_25V6K

    0.01UF_0402_25V7K
    1
    2 PR40 1DOCK_CP 1M_0201_1% RT9818A-36PV_SOT23-3

    1
    1

    1
    PR15 PU1

    2
    PC19

    PC20
    100K_0402_1% 100K_0402_1% PC18

    1
    3
    SI1034CX-T1-GE3_SC89-6 PQ26B D
    1 2 5 2
    SI1034CX-T1-GE3_SC89-6
    1

    2
    3

    PQ4B D ACN PVCC


    5
    6

    D
    5 <20> DOCK_DET_R# G 0.047U_0402_25V7K 3
    PVCC
    G 2 S SI1034CX-T1-GE3_SC89-6 B+

    4
    6

    PQ4A D G
    S
    Batt OVP :
    4

    1 BQ24171_ACP

    1M_0201_1%
    2 S 6
    1

    ACP
    PQ26A

    PR124

    G
    ENABLE_USB_HOST S SI1034CX-T1-GE3_SC89-6 19 BATDRV# Batt+ over 4.4V
    1

    BATDRV#

    22U_0603_6.3V6M
    Back to back will turn off

    0.01UF_0402_25V7K
    PR17 4.02K_0402_1% PD5
    2

    2
    1 2 7 2 1
    CMSRC

    PC25

    PC24
    VBUS_USB PR18 4.02K_0402_1% SBR3U40P1-7_POWERDI123-2
    VDD_3V3_BQ24171_VREF

    1
    PR20 2

    SH00000OD00 BATT+
    21K_0402_1%

    1 2
    PJ7
    8 1 PL3 PR19 @
    100K_0402_1%
    2

    ACDRV SW BQ24171_SW charger_out


    1 2 1 4 1 2
    2.2UH_PCME051E-2R2MS_3.3A_20% 1 2
    24
    1

    SW
    PR23

    BQ24171 internal regulator 2 3

    22U_0603_6.3V6M
    1

    JUMP_43X118

    267K_0402_1%
    3

    1
    DMN66D0LDW-7_SOT363-6

    D BQ24171_BTST
    C 2.5V 1 2 12 21 PR98 PC22 C
    1

    1
    VREF BTST 0.01_1206_1%

    PR22
    USB500MA 5 PR21 1 2 1 2
    G PR123 PC21 2.2_0603_5%
    PC26
    2

    BQ24171_SRP

    PC23
    57.6K_0402_1% 1U_0402_6.3V6K 16 0.047U_0402_25V7K
    100K_0402_1%
    0.1U_0402_25V6

    2
    2

    100K_0402_1% SRP
    S 1 2
    4

    2
    PQ6B

    BQ24171_ISET
    PC29

    1 PR24

    13
    ISET BQ24171_SRN
    15
    1

    BQ24171_ACSET SRN 0.1U_0402_16V4Z


    17
    VDD_3V3_BQ24171_VREF

    1
    PC30 ACSET
    1U_0603_25V6K PC27 PC28
    73.2K_0402_1%
    PR48 1

    2 PR28 1 2 PC31 0.1U_0402_16V4Z 0.1U_0402_16V4Z


    BATT+

    2
    1

    1
    DMN66D0LDW-7_SOT363-6

    11K_0402_1%

    10_0805_1% 20 BQ24171_REGN 1 2 PR29


    REGN
    6

    D
    PR26

    1 1 2 2.43K_0402_1% @PR27
    @ PR27 PR35
    ACIN_12V_OFF 2 @ PR25 P2 1U_0402_16V6K 82K_0402_0.1% 82K_0402_0.1%
    G 73.2K_0402_1% 3 PD6 BQ24171_AVCC 4 PR30
    2

    BAT54CW_SOT323-3 AVCC 7.68K_0402_1%


    2

    2
    PQ6A

    S 10 BQ24171_TS 1 2
    1

    TS
    1
    SI1034CX-T1-GE3_SC89-6 SI1034CX-T1-GE3_SC89-6

    PR31 PR32
    0_0402_5%
    PR135 49.9K_0402_1%
    2

    0_0402_5%
    PR1009

    768K_0402_1%
    6

    D BQ24171_FB
    14 1 2
    4.99K_0402_1%

    BATT_TEMP <26>
    1

    BQ24171_OVPSET FB
    2 18
    2

    OVPSET
    Charging 0-58C
    PR1010

    G
    2

    <7,32> CORE_PWR_REQ
    PQ24A

    S 22
    Charge Current setting: VDD_3V3_BQ24171_VREF LNJT103F011-20
    1

    VIN BQ24171_TTC PGND


    11
    TTC
    3

    PQ23B D
    23
    ICHG=VISET/(20*PR352)
    2

    @ PR33 PGND
    5
    470K_0201_1%
    1

    D G @ PR34
    <<AC adaptor charge>> 100K_0402_1%
    CHARGER_LED#
    PR105

    5 S SI1034CX-T1-GE3_SC89-6 10K_0201_1% 9 25
    4

    STAT THERMALPAD
    VISET=VREF*[PR26/(PR26+(PR22//PR46))] G Vbat=2.1*(1+R27/R37)
    2

    1
    S
    LED status: (AC/Dock station)
    4

    1
    PQ24B

    @ PR37
    =3.3*[11/(11+267//47.5)]= 0.707V BQ24171RGYR_VQFN24_3P5X5P5
    2

    2.39V @ PR36 82.5K_0402_0.1%


    ICHG=0.707/(20*0.01)=3.536A 1 2 VDD_3V3_BQ24171_VREF
    No charge : LED off
    @ 2 1 10K_0402_5%
    Fully charged : Static White LED

    2
    1

    BATT_LEARN <6>
    <<USB charge>>
    0_0201_5%
    100K_0201_1%
    PR129

    0_0201_5% PR1012
    Charging : Static Orange LED
    PR1331

    PR93

    PC32
    VISET=VREF*[PR26/(PR26+PR22)]
    0_0201_5%

    SSM3K7002FU_SC70-3

    0.1U_0402_25V6 1 2 W_LED_CTL <20>


    BATDRV# Charging error : Blink
    1

    D
    =3.3*[11/(11 +267)]= 0.131V @ @ PR1013
    2

    +3VS
    1
    PQ28

    @ TTC_PRECH 2 51K_0402_1%
    B
    ICHG=VISET/(20*0.01)=0.653A G 2 PR38 1
    VDD_3V3_BQ24171_VREF White LED B
    2

    S @
    LED status: (USB)
    3

    100K_0402_1%
    O_LED_CTL <20>
    ## VISET voltage is between 0.12~0.8V ## @ PR130
    <4> CHARGER_STAT
    All LED off TTC setting:

    6
    0_0201_5% D
    2 1
    2 1 DOCK_CP PR119 Orange LED 2
    100K_0201_1% G High:Disable charge timer,allow termination.
    Boot : Static White LED 5sec
    3

    PR132 D PQ21B PQ21A D SI1034CX-T1-GE3_SC89-6


    S
    Low:Disable charge termination & timer.

    1
    3

    3
    D 0_0201_5% D
    5 2 PQ7A
    5 2 1 G G 5 Wake up : Static White LED 5sec Connect capacitor:Set fast charge timer.
    PQ22B G DMN66D0LDW-7_SOT363-6 G PQ7B
    S <5> CP_GPIO S SDMN66D0LDW-7_SOT363-6 S SI1034CX-T1-GE3_SC89-6
    4

    4
    SI1034CX-T1-GE3_SC89-6
    Pre-Charge reserved circuit
    PD9
    2
    VDD_3V3_BQ24171_VREF
    1

    1
    26.1K_0402_1%

    1
    0.022U_0402_25V7K

    BATT+
    PR126

    PC124

    1
    DMN66D0LDW-7_SOT363-6

    51K_0402_5%
    3
    6

    DMN66D0LDW-7_SOT363-6
    D D D

    PR45

    3
    2 WAKEUP_LED 2 USB500MA 2 USB500MA 5 <7> WAKEUP_LED @
    2.2U_0402_6.3V6M

    4.7U_0402_6.3V6M
    2

    G G G BAT54CW_SOT323-3 @ PR75@ PQ5


    2 1 2

    2
    PC126

    PC127

    SI1034CX-T1-GE3_SC89-6 100K_0402_5% @ PR86 2SA1037AK_SC59-3~D

    0_0402_5%

    0_0402_5%
    S
    1

    2
    PQ29A

    PR92
    PQ22A

    PR125
    S S
    2

    1
    300_0402_1%
    PQ29B

    @ PQ9

    2
    AON7403L_DFN8-5
    @ @ 1 BATT+

    1
    charger_out 2 5

    1
    3
    VDD_3V3_BQ24171_VREF @ PR61
    VDD_3V3_BQ24171_VREF

    1
    L: charge in progress 100K_0402_5%
    PU18 @ @
    H : charge is complete or in sleep mode

    4
    100K_0402_5%
    1

    2
    IN+
    2

    Blink (0.5Hz): fault occur (charge suspend, input over-voltage, timer fault and battery absent) 5 PR7
    2

    VCC+
    SB00000SP00 use BSS8402DW footprint PR44 2 @ PR41

    2
    PR47 10K_0201_1% GND 0_0201_5%
    4
    10K_0201_1% CP setting: 3
    OUT
    2 1 TTC_PRECH
    1

    VIN IN-
    1M_0402_1%

    Idpm=Vacset/(20*PR9)
    4 1

    A A
    PR39

    LMV331IDCKRG4_SC70-5
    1
    4

    PQ18 PQ19
    402K_0402_1%

    <<AC adaptor>> BATT+ under 3.3V,


    1

    1
    5 5
    PR42

    PR79@
    Vacset=3.3*PR25/(PR21+PR25)=1.395V Pre-charge will start
    2

    3 3 BQ24171_TTC 100K_0402_5%
    @ PR82
    1 1
    Iin=Vacset/(20*PR9)=1.395A 100K_0402_5%
    2

    2
    BATT+
    2.39V ACIN_12V_OFF 2 6 USB500MA 2 6
    <<USB>> 1 2

    Vacset=3.3*(PR25//PR20)/(PR21+PR25//PR20)=0.463V
    0.1U_0402_16V4Z
    1

    BSS8402DW_SOT363-6 BSS8402DW_SOT363-6
    100K_0402_5%
    PR43

    Iin=Vacset/(20*PR9)=0.463A Security Classification Compal Secret Data Compal Electronics, Inc.


    1

    PC33

    <<Dock-in>> Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title


    PR46 Charger
    2

    BQ24171_ISET 1 2
    Vacset=3.3*(PR25//PR23)/(PR21+PR25//PR123)=0.804V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    47.5K_0402_1%
    Iin=Vacset/(20*PR9)=0.804A DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    2005/4/21
    A2
    Picasso II/M 2.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, March 26, 2012 Sheet 27 of 38
    5 4 3 2 1
    5 4 3 2 1

    @ PR113 63020_B+
    1 2 <32> EN_3V3_SYS
    10K_0402_1%

    0_0201_5%
    PR50

    1
    PR49

    0.1U_0402_25V6
    0_0402_5%

    PR51
    1 2

    PC34
    2 1
    100K_0402_1% PU2
    PR52

    2
    1 14 0_0201_5% @
    @ PD11 VINA PG PR53 1M_0201_1%
    2 13 1 2
    +3VS_FB GND PS/SYNC PL4
    2 1 3 12 1 2
    FB EN 63020_B+
    D Vfb = 0.5V 4
    VOUT VIN
    11 1 2
    B+ D
    1SS355_UMD2-2 5 10
    PR54 VOUT VIN
    6 9 HCB2012KF-121T50_0805
    L2 L1

    PGND
    1 2 7 8 PC35 PC36
    L2 L1

    1
    560K_0402_1%

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    PC56 2 1 TPS63020DSJR_QFN14_4X3

    15
    @ 0.1U_0402_25V6

    2
    PC113
    +3VS 33P_0402_50V8K

    PL5
    1 2

    1.5UH_TMPC0412HP-1R5M-Z02_3A_20%
    PC37 PC38
    Imax=1A

    1
    22U_0603_6.3V6M

    22U_0603_6.3V6M
    <Vo=3.3 VS> VFB=0.5V

    2
    Vo=VFB(1+R12/R14)
    3.3=0.5(1+560/100)

    C C

    1
    PR55
    2.05K_0402_1%

    2
    Vout = 0.5* (1+PR56/PR55) = 5.158V
    +5VS_FB FB: 0.5V

    1
    PR56
    19.1K_0402_1% PC1007
    1000P_0402_25V8J
    5.045V

    2
    H/W maxloading:2A
    13

    14

    15

    16

    17

    2
    PU3
    GND

    PADGND
    VOUT

    VOUT
    FB

    spec: Ven >0.8*VBAT


    12 1
    LBO VOUT +5VS
    VBAT=5V-->Ven>4V
    <13,32> EN_5V0_BUCKBOOST 11 2

    100U_B3_6.3VM_R45M
    EN NC
    1

    22U_0603_6.3V6M
    1
    B B

    PC40
    +

    PC39
    1

    10 3

    2
    SYNC SW
    1

    PR57
    PC41
    0.1U_0402_25V6

    1M_0402_1% 2
    2

    @ 9 4
    2

    LBI SW
    2

    PGND

    PGND

    PGND
    VBAT
    0_0402_5%

    0_0402_5%

    Change C_B3 footprint


    PR96

    PR58

    @
    1

    PL6
    2.2UH_PCMB041B-2R2MS_2.75A_20%
    SYNC High : disable power saving TPS61030RSAR_QFN16_4X4
    SYNC low : enable power saving
    2

    PL7
    1 2
    B+
    HCB2012KF-121T50_0805 PC42
    1
    10U_0603_6.3V6M

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +3.3VALWP/+5VALWP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 28 of 38
    5 4 3 2 1
    5 4 3 2 1

    B+ VDD_5V0_SBY
    D D

    PU4
    PL8 G5910_CP 4
    C+
    3
    HCB1608KF-121T30_0603 VOUT
    5
    PC43 VIN
    1 2 2
    GND

    1
    G5910_CP 1 2 G5910_CN 6
    C- PC44
    7 1
    1U_0603_25V6K TP SHDN 10U_0603_6.3V6M
    Imax=110mA

    2
    1
    G5910-50RBU_TDFN6_2X2
    PC45
    10U_0603_6.3V6M
    Iocp(min)=250mA

    2
    PR59
    <32,34> EN_5V_CHARGEPUMP 2 1

    0_0201_5%

    1
    @
    @ PR60 PC46
    100K_0201_1% 0.1U_0201_6.3V6K

    2
    2
    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +5V_charge_pump
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 29 of 38
    5 4 3 2 1
    5 4 3 2 1

    D D

    BATT+
    @ PR89
    1 2
    EN_3V3_MODEM <7,18>
    10K_0201_1% 3G@ PR85
    3G@ PR63

    2
    1 2 0_0402_5%

    0.1U_0402_25V6
    PR65 3G@

    3G@ PC47
    2 1

    1
    100K_0201_1% PU5 3G@ 100K_0402_5%
    @ PR64
    1 14 0_0201_5% 1U_0402_6.3V6K 3G@ PL16
    PC1006

    1
    @ PD10 VINA PG 3G@
    2 13 1 2
    3G_FB GND PS/SYNC HCB1608KF-121T30_0603
    2 1 3 12 1 2
    FB EN
    4 11 1 2
    1SS355_UMD2-2 5
    VOUT VIN
    10
    BATT+
    PR66 VOUT VIN
    3G@ 6 9
    L2 L1

    PGND
    1 2 7 8
    560K_0402_1% L2 L1

    10U_0603_6.3V6M

    47U_0805_6.3V6M
    2

    PC119
    10U_0603_6.3V6M
    1

    1
    PC49 3G@

    PC50 3G@
    PC48 TPS63020DSJR_QFN14_4X3

    15
    @ 0.1U_0201_10V6K 2 1

    1
    PJ8 @

    2
    @ JUMP_43X79 PC114 3G@
    33P_0402_50V8K
    2 1
    V_MINCARD_3V3 2 1 PL9
    3G@
    C 1 2 C

    1.5UH_TMPC0412HP-1R5M-Z02_3A_20%
    Imax=1A PC51 PC52

    1
    <Vo=3.3 VS> VFB=0.5V

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    Vo=VFB(1+R12/R14)

    2
    3.3=0.5(1+560/100)

    3G@ 3G@

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    3G PA(SY8033B/APL5916)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 30 of 38
    5 4 3 2 1
    5 4 3 2 1

    D D

    VISHAY use DII footprint


    Use other footprint
    PL10 PD8
    1 2 SW 2 1
    B+ 4.7UH_PCME051E-4R7MS_3A_20% +VDD_LED_BL

    33P_0402_50V8J
    0.1U_0603_25V7K

    4.7U_0805_50V6K

    4.7U_0805_50V6K
    4.7U_0603_6.3V6M
    SBR3U40P1-7_POWERDI123-2

    1
    1

    1
    PC53

    PC117

    PC57

    PC55
    PC54

    1
    2

    PR107
    PC61 1M_0201_1%
    0.01UF_0402_25V7K
    2 1

    2
    9979_OVP
    2 1 2 1

    1
    PR100 100_0402_1% PC110 0.47U_0402_10V4Z

    2
    P2@PR112
    P2@ PR112 PM@ PR112

    1
    PR94 9979_OVP 93.1K_0201_1% 76.8K_0201_1%
    C PR69 C
    0_0201_5% PC1005
    1 2 100P_0201_25V8J
    +5VS

    2
    FB1 <13>

    1
    0.1U_0402_25V6

    10_0402_1%
    1

    SA000051D00
    PC58

    21

    20

    19

    18

    17

    16
    PU6
    2

    PAD

    SYNC

    SSTCMP

    OVP

    ISEN1
    SW
    Picasso M: PR112 76.8K OVP :35.05V

    2
    @PR97
    @ PR97 1 15
    Picasso II : PR112 93.1K OVP :29.35V
    0_0201_5% VIN ISEN2 FB2 <13>

    DCTRL 2 14

    1
    0_0201_5% PC1004 PWM ISEN3 FB3 <13>
    PR70 1U_0402_6.3V6K OZ9979LN-A3-0-TR_QFN20_4X4
    1 2 9979_EN 1 2 9979_VREF 3 13
    <4,13> DISPOFF# PR1007 VREF GNDA
    0_0201_5%
    1000P_0201_50V7K
    100K_0201_1%

    1 2 4 ADIM ISEN4 12
    2

    PR1008 FB4 <13>


    1
    PR103

    PC59

    100K_0201_1%
    1 2 5 RT ISEN5 11
    B
    FB5 <13> B
    2

    ISEN6
    ISET

    ENA
    1

    LRT

    LPF
    6

    10
    PWM dimming frequency: 6K(TYP)
    TP2

    9979_EN
    1K_0201_1%
    24K_0402_1%

    56K_0201_1%
    PR71
    2 PAD

    1U_0402_6.3V6K
    1 2 DCTRL

    2
    <13> INVTPWM
    PR72

    PR99

    PC60
    1000P_0201_50V7K
    100K_0201_1%

    1
    2
    PR73

    1
    1

    @PC62
    2
    1

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LED driver
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    B 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 31 of 38
    5 4 3 2 1
    5 4 3 2 1

    a. GP0: EN_5V_CP Follow ACER circuit 6/22

    PMU-TPS65911 1/3 b.
    c.
    d.
    e.
    GP2:
    GP6:
    GP7:
    GP8:
    EN_SOC
    EN_3V3_SYS
    EN_DDR (Optional on Cardhu S since we are using VDD2 for memory)
    EN_5V0

    VDD_5V0_SBY
    PU7A VDD_1V8_PMU_VRTC
    PMU_OSC32KOUT

    F7 PMU_OSC32KIN <7>PMU_OSC32KOUT <7>


    OSC32KOUT

    1
    PR74 1 2 0_0201_5% M4 PR78 PR80

    22P_0402_50V8J

    22P_0402_50V8J
    <7,10,14,15,26,34> PWR_I2C_SCL SCL PMU_OSC32KIN

    PC63

    PC64
    F8
    OSC32KIN

    100K_0201_1%

    100K_0201_1%
    PR76 1 2 0_0201_5% M5

    100K_0201_1%
    2

    2
    <7,10,14,15,26,34> PWR_I2C_SDA SDA

    1
    D D

    PR77
    @
    PR81 1 2 0_0201_5% M7
    <7> CPU_PWR_REQ

    2
    TP1 EN1
    PAD M6 L5
    EN2 GPIO0 EN_5V_CHARGEPUMP <29,34>
    VDD_1V8_GEN L4
    GPIO7
    K5 TP_PMU_GPIO8
    GPIO8 EN_5V0_BUCKBOOST <13,28>

    1
    PR83
    10K_0402_5% PR84 1 2 0_0201_5% F1
    <7,27> CORE_PWR_REQ SLEEP
    L2 EN_VDD_SOC <34>
    GPIO2
    G3 EN_3V3_SYS <28>

    2
    GPIO6

    <7> PMU_INT# L3
    INT1

    F6
    GPIO1
    TP4 B7
    PAD POWERHOLD GPIO3 TP5
    N1
    PWRHOLD PAD

    PR88 0_0201_5% F4 1 2
    CLK32KOUT PMU_CLK_32K <7>
    <7> AP_OVERHEAT# 1 2 N2
    PWRDN PR87 33_0402_1% TP7
    PAD

    HDRST L6 PR91 0_0201_5%


    <20> HDRST HDRST
    H4 1 2 PMU_RESET_OUT_1V8# <7>
    NRESPWRON
    C7
    NRESPWRON2 TP6 PAD 1@ PR134 2 VDD_1V8_GEN
    C C
    100K_0402_5%

    D7 PMU_VBACKUP
    VBACKUP

    1
    PC65
    1U_0402_6.3V6K
    VDD_1V8_GEN

    2
    TP12
    PAD H7
    GPIO4
    TP11
    PAD G6 N7
    GPIO5 VDDIO

    B+

    1
    PC66 B+
    4.7U_0402_6.3V6M

    2
    B6
    VCC7

    1
    PR95 1 2 0_0201_5% PMU_ONKEY# PC67 VDD_1V8_PMU_VRTC
    <20> A_ONKEY# E4
    PWRON 4.7U_0402_6.3V6M
    Always on

    2
    2 PR4 1 1.8V
    0_0402_5%
    0.05A
    1

    10MIL
    PC181 B5
    1U_0402_6.3V6K VDD_1V8_PMU_VRTC VRTC
    2

    1
    PMU_VCCS E8
    VCCS PC68 VDD_0V85_PMU_VREF
    4.7U_0402_6.3V6M

    2
    2

    0 = Hardcode 0.85V
    PR90
    B B
    0_0201_5% 1 = EEPROM 10MIL 0.05A
    G8
    VREF
    1

    PMU_BOOT1 J5
    BOOT1

    1
    PC69
    0.1U_0402_25V6

    2
    G7
    REFGND

    B8
    TESTV

    D6
    AGND1
    E6
    AGND2
    E5
    AGND3
    F5
    AGND4
    G4
    AGND5
    H6
    AGND6
    J3
    AGND7
    J4
    AGND8
    J6
    AGND9
    K3
    AGND10
    H5
    AGND11
    M8
    AGND21
    N8
    AGND22
    A1
    DGND1
    B1
    DGND2
    B2
    DGND3

    PTPS659110A2ZRCR_BGA98

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PMU part1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 32 of 38
    5 4 3 2 1
    5 4 3 2 1

    PMU-TPS65911 2/3

    D D

    PU7B Note: LDO1 & LDO2 need 4.7uF cap according to TI on July 6th

    VDD_PMU_LDO1 2.85V
    N5 N6
    +3VS VCC6 LDO1 VDD_PMU_LDO1
    0.5A
    30MIL

    1
    N4 VDD_PMU_LDO2
    LDO2 VDD_PMU_LDO2

    1
    PC70

    1
    4.7U_0402_6.3V6M 3V

    1
    PC72 PC122
    PC71 0.2A 1U_0402_6.3V6K 1M_0402_5%

    2
    4.7U_0402_6.3V6M

    2
    30MIL
    D8 E7 VDD_PMU_LDO3 3V
    B+ VCC5 LDO3 VDD_PMU_LDO3
    20MIL 0.2A

    1
    C8 VDD_PMU_LDO4
    LDO4 VDD_PMU_LDO4

    1
    PC73

    1
    4.7U_0402_6.3V6M 1.2V PC75

    2
    PC74

    2
    0.1A 2.2U_0402_6.3V6M

    2
    2.2U_0402_6.3V6M

    C C

    30MIL
    PR110
    B+ L1
    VCC4 20MIL
    LDO5
    K1 1 2
    VDD_PMU_LDO5 2.8V
    5V 0_0402_5% 0.2A
    1 PC76
    0.2A

    1
    4.7U_0402_6.3V6M
    2

    PC77

    2
    2.2U_0402_6.3V6M

    10MIL
    N3 M2 VDD_PMU_LDO6
    B VDD_1V8_GEN VCC3 LDO6 VDD_PMU_LDO6 B

    10MIL 1.2V
    1

    M3 VDD_PMU_LDO7
    PC78 LDO7 VDD_PMU_LDO7
    4.7U_0402_6.3V6M
    0.1A
    1.2V
    2

    M1 VDD_PMU_LDO8
    LDO8 VDD_PMU_LDO8
    0.05A
    1.0V
    0.02A

    1
    PC79 PC80 PC81

    2
    2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M

    PTPS659110A2ZRCR_BGA98

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PMU part2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 33 of 38
    5 4 3 2 1
    5 4 3 2 1

    B+
    FOR VDD_1V2_CORE_TEGRA

    PMU-TPS65911 3/3 PC82


    10U_0603_6.3V6M 1

    1
    <29,32> EN_5V_CHARGEPUMP
    PC83
    0.1U_0402_25V6 VDD_1V2_SOC

    2
    2
    2 PU8
    PL11
    PR101

    2
    PR102 100K_0201_5% A4 B3 TPS62361_SW1 2
    VIN SW 2.2UH_PCMB041B-2R2MS_2.75A_20%
    A1 B4

    0.1U_0402_25V6
    AVIN SW

    100K_0201_5%
    1

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    1
    <32> EN_VDD_SOC B2
    EN

    PC84

    PC85

    PC100

    PC112
    1
    PU7C VDD_1V2_SOC

    PC111
    D1 B1

    2
    D
    PC88 PR104 0_0201_5% VDD SENSE+ 2 D
    20MIL VDD_1V8_GEN PWR_I2C_SDA <7,10,14,15,26,32>

    1
    E1 D2 1 2 D2 C1
    B+ VCCA1 SWA1 SDA SENSE -

    0.1U_0402_25V6
    D1 1 2 D3
    SWA2 SCL
    F2 E2

    0.1U_0402_25V6
    PWR_I2C_SCL <7,10,14,15,26,32>

    2
    VCCA2 SWA3 PR106 0_0201_5% C2 Close to CPU
    10U_0603_6.3V6M
    VSEL0
    1

    1
    F3 A3 D4
    VCCA3 VSEL1 PGND
    PC86

    PC108
    C3
    PGND
    A2 C4
    2

    2 AGND PGND
    C2
    Ipeak =2.5A( 6us)
    GNDSWA1 TPS62361YZHR_XBGA16
    GNDSWA2
    C1 Imax = 1.8A(60us) sustained
    D3
    GNDSWA3

    D4
    VFB1
    TPS62361B
    TPS62361YZHR_XBGA16
    B+
    2.2UH_VLS252012T-2R2M1R3_1.8A_20%
    50MIL PL13 50MIL
    30MIL G2 H2 1 2
    VCCBB1 SWB1 VDD_1V2_MEM
    1.2V 2A
    G1 H1 1.2V
    0.1U_0402_25V6
    10U_0603_6.3V6M

    VCCB2 SWB2
    1

    2A
    PC90

    PC87

    0.1U_0402_25V6
    10U_0603_6.3V6M
    2

    1
    1
    2

    1
    PR108

    PC91

    PC102
    0_0402_5%
    J2

    2
    GNDSWB1 2

    2
    J1 50OHM_NETCLASS1
    GNDSWB2

    C K2 PMU_VFB2 C
    VFB2

    VDD_5V0_SBY
    PC92
    A5 B+
    V5IN PMU_VBST
    A2 1 2
    VBST
    0.1U_0402_25V6

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1 4.5 ~ 6.5V
    1U_0402_16V6K

    0.1U_0402_25V6
    0.1U_0402_25V6
    1

    1
    PC94

    PC95
    PC107

    1
    PC93

    PC103
    PR109
    2

    2
    2
    A3 PMU_DRVH 1 2 PMU_DRVH_R 2
    DRVH PMU_DRVH_R
    0_0402_5% Tj<90 degree ==>6.1A

    1
    Tj<70 degree ==>5.1A

    D1

    D1

    D1

    G1
    PL14
    2.2UH_MMD-06AE-2R2M-M1L_6A_20% 200MIL
    A4 PMU_SW 10 9 PMU_SW 1 2
    SW D1 D2/S1 VDD_1V0_GEN
    1V Change C_B3 footprint

    G2
    S2

    S2

    S2
    8A

    220U_A_2.5VM_R35M

    220U_A_2.5VM_R35M

    150U_B_6.3VM_R35M
    FDMC7200_POWER33-8-10 1 1 1

    0.1U_0402_25V6
    5

    8
    PQ16 1
    + + +

    PC96
    PC104

    PC109

    PC123
    A6 PMU_DRVL
    DRVL

    1
    PMU_DRVL
    PR121 2 2 @ 2 @ 2 @ ZZZ
    0_0402_5% X76376BOL11

    2
    B B

    B4 PMU_VOUT
    VOUT
    X76 control
    PC97 X76376BOL11: NEC 220U_R35*2
    C5 1 2 X76376BOL12: NEC 220U_R70*2+Sanyo 100U_R45*1
    VFB

    330P_0402_50V7K 50OHM_NETCLASS1
    C4 PMU_PGOOD PAD TP8
    PGOOD
    A8 D5
    GNDC1 EN
    A7 C6
    GNDC2 TRAN
    B3 PMU_TRIP 1 2
    TRIP PR111
    90.9K_0402_1%

    B+

    2.2UH_VLS252012T-2R2M1R3_1.8A_20%
    L8 PL15 50MIL
    VCCIO1 PMU_SWIO
    K8 1 2 VDD_1V8_GEN
    10U_0603_6.3V6M

    0.1U_0402_25V6

    SWIO1
    1 L7
    VCCIO2
    1
    PC98

    1.8V
    PC106

    K7
    SWIO2
    2A
    0.1U_0402_25V6
    10U_0603_6.3V6M
    2

    2
    1
    1

    PR122
    PC99

    PC105

    A J7 0_0402_5% A
    GNDIO1
    2

    J8 2
    2

    GNDIO2

    50OHM_NETCLASS1
    H8
    VFBIO

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    PTPS659110A2ZRCR_BGA98
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PMU part3
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 34 of 38
    5 4 3 2 1
    5 4 3 2 1

    D D

    0_0402_5%
    P2@ PR118
    <7> CAM_LED_EN_NV 1 2

    2
    <17> CAM_LED_EN 1 2 @ PR120 +3VS
    @ PR117 1M_0402_1%
    0_0201_5%
    PC115 PU9

    2
    P2@ 10U_0805_25V6K

    PR115
    100K_0402_1%
    1 2 A1 FLASH_SYNC PGND C1

    <20> LED+ A2 C2 @
    C PR116 P2@ VOUT PGND C
    indicator for TPS61050

    1
    <6,17,26> CAM_I2C_SDA 1 2 A3 SDA ENVM C3
    0_0201_5%
    B+ 2 1 B1 SW AGND D1
    P2@PL17
    P2@ PL17
    2.2UH_VLS252012T-2R2M1R3_1.8A_20% B2 D2
    SW LED LED- <20>
    <6,17,26> CAM_I2C_SCL 1 2 B3 SCL AVIN D3 B+
    P2@PR128
    P2@ PR128
    0_0201_5%

    1
    TPS61050YZGR_DSBGA12

    10U_0603_6.3V6M
    P2@
    PC116

    2
    P2@

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LED FLASH
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    A3 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Monday, March 26, 2012 Sheet 35 of 38

    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List)

    Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

    01 28 change PL5, PL9 from PCMB041B-2R2MS 2.75A to EVT


    1 Ripple un-stable Loop stable for TPS63020 PCMB041B-1R5MS 3A,
    20110806 (QAJ70)
    D 30 D

    change PR9 form 0.01_1206_1% to 0.05_1206_1%

    2 charger CP setting for adaptor protect 02 26


    change
    change
    PR25 form 10K to 73.2K
    PR20 form 3.83K to 21K 20110809 DVT
    Remove ACER USB setting circuit (QAJ50)

    3 Net name error 02 35 change net name from VDD_1V8_SYS to VDD_1V8_GEN 20110809 DVT
    (QAJ50)

    4 Material version change 02 35 change PQ16 from FDMC7200 2N POWER33-8 to FDMC7200S 2N POWER33-8 20110809 DVT
    (QAJ50)

    5 GPIO only support 1.8V Use low Vth dual N TR 02 26 change PQ4,PQ6,PQ7,PQ21,PQ21 from DMN66D0LDW-7_SOT363 to SI1034CX 20110809 DVT
    (QAJ50)

    6 material change for common use 02 26 change PQ18 from BSS8402DW 1P/1N SOT363-6 to SI1553CDL-T1-GE3
    1P/1N SC70-6 20110809 DVT
    C
    (QAJ50) C

    7
    No support Acer USB, delete related 02 26 Delete PQ19, PR40, PR44, PR47, PR41.
    20110809 DVT
    control circuit (QAJ50)

    8 Back-to-back MOS can't The BATDRV# pull low 1K will cause ACDRV 02 26 Change PR16, PR12, PD4 to reserve
    20110809 DVT
    fully turn on abnormal (QAJ50)
    Charger will terminate The TTC pull high 100K will cause wrong 02 26 Change PR34 from 100K to 10K
    DVT
    9 voltage level 20110809 (QAJ50)

    10 02 26 Change PR36 from 100K to 10Kohm


    DVT
    Orange LED can't turn off STAT pull high 100K can't drive TR 20110809 (QAJ50)

    11 Modify Battery OVP circuit to avoid AC


    02 26 Add PC118, PR144,PQ23. Delete PD7 20110809 DVT
    turn off when Battery over discharge (QAJ50)
    B B

    12 Pre-charge circuit can't Change PR86,PR92,PR93 to PNP 2SA1037K


    DVT
    work normally Modify Pre-charge circuit 02 26 20110816 (QAJ50)

    13 Sub/B +5VS will drop to Modify +5VS voltage setting to 5.15V 02 28 Change PU3 to TPS61030, PR56 to 19.1K, PR55 to 2.05K 20110824 DVT
    under 4.75V (QAJ50)
    14 TPS63020 add 33P on feedback resistor 02 28 Add PC113, PC114 33P 20110824 DVT
    for loop stable
    30 (QAJ50)

    15 V_MINCARD_3V3 sequence 02 30
    Change PR65 from 1M_0402_1% to 100K_0402_1%
    Add PC1006 1U_0402_6.3V6K 20110824 DVT
    (QAJ70)

    16 modify crystal cap 02 32 Change PC63, PC64 from 12P_0402_50V8J to 22P_0402_50V8J 20110825 DVT
    (QAJ70)
    A
    Add LED control circuit for wake up/boot 02 26 Add PQ22 to turn off O_LED
    DVT A

    17 define 20110825 (QAJ70)


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 36 of 38
    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List)

    Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

    Add for pre-charge and fast charge timeout 02 27 Add PQ19 ,PR44,PR47
    DVT
    D
    1 20110826 (QAJ70) D

    Modify PD1, PD5, PD8 from SS3P4-M3-84A_SMP2 DVT


    2 BOM control 02 27,31 to SBR3U40P1 20110826 (QAJ70)
    Modify PL13, PL15, PL17 footprint to DVT
    3 footprint control 02 34,35 TOKO_1239AS-H-2R2N-P2_2P 20110826 (QAJ70)

    4 Change CP setting for adaptor protect 02 27 Add PQ23 DVT


    20110826 (QAJ70)
    Add VDD_1V0_GEN and VDD_1V8_GEN DVT
    5 Fb resistor for test request 02 34 Add PR121, PR122
    20110826 (QAJ70)
    03 27 Change PL1 to 300ohm bead, add PC120, PR11, PC15, DVT2
    6 EMI request PC20, PR98, PC1,PC2 for EMI request 20110920 (QAJ50)
    C C

    7 Cancel the function 03 27 Delete PR12, PR16, PD4 20110920 DVT2


    (QAJ50)

    8 Reserve the CP control for thermal improve 03 27 Add PR48, PQ24 for reserve 20110920 DVT2
    (QAJ50)
    DVT2
    9 Dock in CP setting 03 27 Add PQ26 PR93 PR96 PR124 PR123 PR40 20110920 (QAJ50)

    10 Solve White LED flash issue when AC


    03 27 Add PD4,PC121,PR126,PR127,PQ27 20110920 DVT2
    plug in (QAJ50)
    11 Battery OTP change to 55C 03 27 Change PR29 to 2.74K, PR30 to 8.87K 20110920 DVT2
    (QAJ50)
    B B

    12 remove pre-charge function 03 20111006 DVT2


    Reserved PU18, PQ9, PR7, PR61, PR79, PR86, PR41
    (QAJ50)
    13 solve leakage current 03 27,31 Change PD1,PD5,PD8 from SBR3U40 to SS3P4; 20111006 DVT2
    PR62, PR114 to 806K (QAJ50)
    14 04 28 Change PC39 to 100U_B3_6.3VM_R45 20111027 DVT2
    Thermal over temperature
    (QAJ70)
    04 Change PC6, PC7 to 0.22U. Add PC89 2.2U 20111027 PVT
    15 VBUS leakage PQ1 will turn on when AC plug out 26,27 (QAJ50)
    20111027 PVT
    16 OTP change to 58C 04 27 Change PR29 to 2.43K, PR30 to 7.68K
    (QAJ50)
    A
    PVT A

    17 Modify battery OVP to 4.4V 04 27 Change PR67 to 38.3K 20111105 (QAJ50)


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 2.0
    27
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date:
    Picasso II/M
    Thursday, March 22, 2012 Sheet 37 of 38
    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List)

    Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
    PVT
    1 Turn off charge LED when USB in 04 27 Add PQ29, PC126, PC127 20111210 (QAJ50)
    D D

    2
    White LED can't light
    Don't need the component 04 27 Change PR45 to reserve 20111210 PVT
    when power on (QAJ50)
    Adjust CP setting when power on for PVT
    3 thermal issue 04 27 Add PQ22, PR132, PR135 20111210 (QAJ50)

    4
    Battery can't be charged Modify the battery capacity control for 04 27 Add PR1012, change P135 to 4.99K 20111210 PVT
    when dock in EN_USB_HOST to BATT_LEARN (QAJ50)

    5
    T30S WAKE_UP_ACIN damage Avoid WAKE_UP_ACIN in-rush voltage 04 27 Add PR136, PR131 20111210 PVT
    (QAJ50)

    6
    Modify charge output voltage to improve 04 27 Change PR35 to 82K and PR31 to 82.5K 20111210 PVT
    C
    battery capacity (QAJ50) C

    7
    Avoid white LED will flash 1s when AC/USB 04 27 Change PD4 to reserve, Add PR1013, PR126, PC124 20111210 PVT
    plug in/out (QAJ50)

    8
    Modify crystal cap value 04 32 Change PC63, PC64 to 22P 20111210 PVT
    (QAJ50)

    9 EMMC voltage drop PMIC LDO1 compensation 04 33 Change PC72 to 1U 20111210 PVT
    (QAJ50)
    10
    PVT
    Avoid EMMC external LDO floating 04 33 Add PC122 1M 20111219 (QAJ50)

    11
    B B

    12

    13

    14

    15

    16
    A A

    17

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/20 Deciphered Date 2012/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 2.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Picasso II/M
    Date: Thursday, March 22, 2012 Sheet 38 of 38
    5 4 3 2 1
    www.s-manuals.com

    You might also like