A B C D E

ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4

PCB PCB PCB PCB PCB

DAZ@ DAZ@ DAZ@ DAZ@

1 1

Compal Confidential
2 2

Everest Schematics Document

Intel Merom Processor with Calistoga + DDRII + ICH7M

3
2007-05-15 3

REV: 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3781P
Date: Friday, May 18, 2007 Sheet 1 of 46
A B C D E
 A B C D E

Compal Confidential
Model Name : Everest Intel Merom Processor
File Name : LA-3781P uPGA-478 Package
1
page 4,5,6 1

FSB
H_A#(3..35) 667/800MHz H_D#(0..63)

CRT CRT CRT

NB8M page 19
128M Intel Calistoga GMCH Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
VGA/B LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15
LCD Conn. LVDS
page 18 1.8V DDRII 533/667
PCBGA 1466
PCI-Express
page 7,8,9,10,11,12,13

DMI USB conn x2 USB conn x2 3 in 1

Bluetooth Card Reader socket
X4 mode TO M/B TO I/O/B RTS 5158
page 33 page 37
Conn page 33 page 28
page 29

2 2
PCI-Express USB
Intel ICH7-M 3.3V 48MHz

3.3V 24.576MHz/48Mhz HD Audio

3.3V ATA-100 IDE
mBGA-652
S-ATA port 0
page 20,21,22,23
New Card MINI Card LAN(10/100M) MDC 1.5 HDA Codec
Socket WLAN,
BCM5906 Conn
page 42
ALC861VD
page 38
page 33 3G/TV-Tuner
Robson page 32 page 30
S-ATA HDD CDROM
LPC BUS Conn.page 24 Conn.
page 24
Audio AMP
RJ45 page 39
3
page 31 3

ENE KB926 SPI ROM BIOS Int SPK Mic/Int

page 34 page 36

USB BD Audio BD

Fan Control Touch Pad Int.KBD

page 4 K_SW page 36 Line-out Mic/Ext
page 35

Clock Generator Sub BD

SLG8LP465VTR
page 16 USBx2

Thermal Sensor
4
G781F 4
page 4
SW Board
HDD/ODD NUM CAP Scroll NOVO Mute User Power
Power circuit
page X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Power Battery W/L
MB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3781P
Date: Friday, May 18, 2007 Sheet 2 of 46
A B C D E
 A B C D E

1 1

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2 2
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
EC SM Bus1 address EC SM Bus2 address
+RTCVCC RTC power ON ON ON
Device Address Device Address
Smart Battery 0001 011X b GMT-781 1001 100X b
EEPROM(24C16/02) 1010 000X b NVIDIA NB8X
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

3 ICH7M SM Bus address 3

Device Address
BOARD ID Table
Clock Generator 1101 001Xb
ID BRD ID R54/42(Rb) Vab (SLG8LP465VTR)

I I 0 R01 (EVT) 0 0V DDR DIMM0 1010 000Xb

H H
L L 1 R02 (DVT) 8.2K 0.25V DDR DIMM1 1010 010Xb
0 V
0 2 2 R03 (PVT) 18K 0.50V
/ Wireless
3 3 R10A (MP) 33K 0.82V NewCard
I 4 R01 (EVT) 56K 1.19V
G LAN
T 5 R02 (DVT) 100K 1.65V
3
0 6 R03 (PVT) 200K 2.20V
7 R10A (MP) NC 3.30V

PANEL ID Table
ID UMA_DES Vab
4
0 IHL00/IGT30 UMA 3.30V 4

1 IHLV3 UMA 2.20V

2
3
4 Security Classification Compal Secret Data Compal Electronics, Inc.
5 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

6 IHLV2 VGA 0.25V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
7 IHL00/IGT30 VGA 0V B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3781P
Date: Friday, May 18, 2007 Sheet 3 of 46
A B C D E
 5 4 3 2 1

+VCCP
<7> H_A#[3..31] H_D#[0..63] <7>
JP15A This shall place near CPU
ITP_TDI R509 1 2 56_0402_5%
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
ITP_TMS R510 1 2 56_0402_1%
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 ITP_TDO R512 1 2 56_0402_5%
H_A#7 A6# D3# H_D#4
M1 A7# D4# F23
H_A#8 N2 G25 H_D#5 R515 1 2 56_0402_5%
H_A#9 A8# D5# H_D#6 @
J1 A9# D6# E25
H_A#10 N3 E23 H_D#7 ITP_TRST# R513 1 2 56_0402_5%
H_A#11 A10# D7# H_D#8
P5 A11# D8# K24
H_A#12 P2 G24 H_D#9 ITP_TCK R514 1 2 56_0402_5%
D H_A#13 A12# D9# H_D#10 D
L1 A13# D10# J24
H_A#14 P4 J23 H_D#11
H_A#15 A14# D11# H_D#12
P1 A15# D12# H26
H_A#16 R1 F26 H_D#13
H_A#17 A16# D13# H_D#14
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15 ITP_DBRESET# R511 1 2 @ 200_0402_5% PAD T35
H_A#19 A18# D15# H_D#16
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17
H_A#21 A20# D17# H_D#18
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28 +3VS
<7> H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29
D29# C327
H_REQ#0 K3 T25 H_D#30
H_REQ#1 REQ0# D30# H_D#31
H2 REQ1# D31# N24 1 2

2
H_REQ#2 K2 AA23 H_D#32
H_REQ#3 REQ2# D32# H_D#33 0.1U_0402_16V4Z @ R268
J3 REQ3# D33# AB24
H_REQ#4 L5 V24 H_D#34 U19 10K_0402_5%
REQ4# D34# H_D#35 H_THERMDA
D35# V26 2 D+ VDD1 1
H_ADSTB#0 L2 W25 H_D#36 C328
<7> H_ADSTB#0

1
H_ADSTB#1 ADSTB0# D36# H_D#37 H_THERMDC THERM_SCI#
<7> H_ADSTB#1 V4 ADSTB1# D37# U23 1 2 3 D- ALERT# 6 2 1 EC_THERM# <21,31>
U25 H_D#38 2200P_0402_50V7K R267 @ 0_0402_5%
D38# H_D#39 EC_SMB_CK2 THERM#
D39# U22 <31> EC_SMB_CK2 8 SCLK THERM# 4 2 1 +3VS
AB25 H_D#40 10K_0402_5% @R269 Check : to sb
D40# H_D#41 EC_SMB_DA2
D41# W22 <31> EC_SMB_DA2 7 SDATA GND 5
C H_D#42 C
D42# Y23
CLK_CPU_BCLK A22 AA26 H_D#43
<15> CLK_CPU_BCLK BCLK0 D43# G781F_SOP8
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y22 Address:100_1100
AC26 H_D#46
D46# H_D#47
D47# AA24
H_ADS# H1 AC22 H_D#48
<7> H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53
R73
56_0402_5%
<7>
<7>
H_DRDY#
H_HIT#
H_HIT#
H_HITM#
G6
DRDY#
HIT#
D53#
D54# AD20 H_D#54
H_D#55
FAN1 Conn
<7> H_HITM# E4 HITM# CONTROL D55# AE22
1 2 H_IERR# D20 AF23 H_D#56
+VCCP H_LOCK# IERR# D56# H_D#57
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
<7> H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60
<7> H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62 +5VS
F4 RS1# D62# AF22
H_RS#2 H_D#63 C100 2.2U_0603_16V6K +5VS
H_TRDY#
G3
G2
RS2# D63# AF26
1 2
DIODE
<7> H_TRDY# TRDY#
Closed to

1
J26 H_DINV#0
DINV0# H_DINV#0 <7> Connector
M26 H_DINV#1 U6 D8
DINV1# H_DINV#1 <7>
AD4 V23 H_DINV#2 1 8
BPM0# DINV2# H_DINV#2 <7> VEN GND
AD3 AC20 H_DINV#3 2 7 1SS355_SOD323
BPM1# DINV3# H_DINV#3 <7> VIN GND
AD1 +VCC_FAN1 3 6 @ D7

2
BPM2# EN_FAN1 VO GND @ 1N4148_SOT23
AC4 BPM3# H_DSTBN#[0..3] <7> <31> EN_FAN1 4 VSET GND 5
H23 H_DSTBN#0 1 2
ITP_DBRESET# C20 DSTBN0# H_DSTBN#1 G993P1UF_SOP8
<21> ITP_DBRESET# DBR# DSTBN1# M24
B H_DBSY# H_DSTBN#2 B
<7> H_DBSY# E1 DBSY# DSTBN2# W24
H_DPSLP# B5 AD23 H_DSTBN#3 C94
<20> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0 2.2U_0603_16V6K
<20,44> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1 1 2
<7> H_DPWR# DPWR# DSTBP1#
AC2 MISC Y25 H_DSTBP#2
<44> H_PROCHOT# T48 PRDY# DSTBP2# H_DSTBP#3 +3VS C358
AC1 PREQ# DSTBP3# AE24
1 R70 2 PAD H_PROCHOT# D21 1000P_0402_50V7K
+VCCP 68_0402_5% PROCHOT#
1 2

1
H_PW RGOOD D6
<20> H_PWRGOOD H_CPUSLP# PWRGOOD R276
<7,20> H_CPUSLP# D7 SLP#
ITP_TCK AC5 1K_0402_5%
ITP_TDI TCK H_A20M#
ITP_TDO
AA6 TDI A20M# A6
H_FERR#
H_A20M# <20> 40mil JP17
AB3 A5 H_FERR# <20>

2
R499 1 TEST1 TDO FERR# H_IGNNE# +VCC_FAN1
2 @ 1K_0402_5% C26 TEST1 IGNNE# C4 H_IGNNE# <20> 1 1
R307 1 2 51_0402_5% TEST2 D25 B3 H_INIT# 2
TEST2 INIT# H_INIT# <20> <31> FAN_SPEED1 2
ITP_TMS AB5 C6 H_INTR 3
TMS LINT0 H_INTR <20> 3
ITP_TRST# AB6 B4 H_NMI 1
TRST# LINT1 H_NMI <20>
LEGACY CPU 4 GND
THERMAL C341 5
H_THERMDA H_STPCLK# GND
A24 THERMDA DIODE STPCLK# D5 H_STPCLK# <20> 100P_0402_50V8J
H_THERMDC H_SMI# 2
A25 THERMDC SMI# A3 H_SMI# <20>
H_THERMTRIP# C7 ACES_85205-03001
<7,20> H_THERMTRIP# THERMTRIP# ME@
H_THERMDA, H_THERMDC routing together.
TYCO_1-1674770-2_Yonah~D
Trace width / Spacing = 10 / 10 mil ME@

+VCCP

A A
1

+VCCP
R68
R487
@ 56_0402_5% H_DPSLP# 1 2
2 2

@ 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
B

R486
H_DPRSTP# 1 2 2006/08/18 2007/8/18 Title
Issued Date Deciphered Date
E

H_PROCHOT# 1 OCP#
3 OCP# <21> Merom (1/3)
C

@ Q4 @ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MMBT3904_SOT23 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3781P
Date: Friday, May 18, 2007 Sheet 4 of 46
5 4 3 2 1
 5 4 3 2 1

D D

+VCCP +CPU_CORE
Length match within 25 mils JP15B JP15C
The trace width 18 mils space
1

<44> VCCSENSE VCCSENSE AF7 AB26 AE18 K1

VCCSENSE VSS VCC VSS
+CPU_CORE 7 mils <44> VSSSENSE VSSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R263 R266 AD25 AB15 M2
+CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2

+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
R516 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C283

C284
N6 AD22 AA13 D26
R67
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21
T21
VCCP VSS AC19
AF19
AA12
AD12
VCC YONAH VSS E24
B21
Close to CPU pin AD26 VCCP VSS VCC VSS
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22
W21 AA16 AE12 E21

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
<44> H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
C CPU_VID0 C
<44> CPU_VID0 AD6 VID0 VSS AD13 AC10 VCC VSS B16
CPU_VID1 AF5 AC14 AC9 A16
<44> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<44> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<44> CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
<44> CPU_VID4 VID4 VSS VCC VSS
CPU_VID5 AF2 AA11 AE9 E16
<44> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<44> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
+CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 1 CPU_BSEL1 B23 AD8 F20 B11
<15> CPU_BSEL1 BSEL1 VSS VCC VSS
CPU_BSEL2 C21 AC8 E20 A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+CPU_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R76
R261

R264

R517

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

B VCC VSS VCC VSS B

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

TYCO_1-1674770-2_Yonah~D TYCO_1-1674770-2_Yonah~D
ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (2/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3781P
Date: Friday, May 18, 2007 Sheet 5 of 46
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
3 x 330uF(9mOhm/2) 3 x 330uF(9mOhm/2)
1 1 1 1
+ C298 + C297 + C332 + C331

330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
2 330U_D2E_2.5VM_R9
2 2 330U_D2E_2.5VM_R9
2

D D
South Side Secondary North Side Secondary

+CPU_CORE

1 1 1 1 1 1 1 1
C26 C27 C28 C29 C30 C31 @ C32 C33

@ 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

2 2 2 2 2 2 2 2
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

(Place these capacitors on South side,Secondary Layer)

+CPU_CORE

1 1 1 1 1 1 1 1
C56 C55 C54 C53 C52 C51 C50 C49

10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

9/25 10U checked. OK for use!
2 2 2 2 2 2 2 2
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

C (Place these capacitors on North side,Secondary Layer) C

+CPU_CORE

1 1 1 1 1 1 1 1
C315 C316 C305 C306 C307 C308 C309 C310

@ 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

2 2 2 2 2 2 2 2
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

(Place these capacitors on South side,Primary Layer)

+CPU_CORE

1 1 1 1 1 1 1 1
C313 C314 C323 C322 C321 C320 C319 C318
@
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

B
(Place these capacitors on North side,Primary Layer) B

+CPU-CORE C,uF ESR, mohm ESL,nH

Decoupling
SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6
32X22uF 3m ohm/32 0.6nH/32
MLCC 0805 X5R
32X10uF 3m ohm/32 0.6nH/32

+VCCP

1
1 1 1 1 1 1
C324 + C38 C43 C58 C24 C39 C45
220U_B2_2.5VM_R35
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (3/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 6 of 46
5 4 3 2 1
 5 4 3 2 1

<4> H_D#[0..63] H_A#[3..31] <4> Description at page15.

U20A U20B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <21> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <21> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <21> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T9
HD4# HA7# <21> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T3
U20 H_D#6 HD5# HA8# H_A#9 CFG4 CFG5
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T10
D HD7# HA10# <21> DMI_TXP0 DMIRXP0 CFG6 D
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <21> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T7
HD9# HA12# <21> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <21> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T5
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
965GM H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
PM@ H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <21> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <21> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T2
HD15# HA18# <21> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T8
HD16# HA19# <21> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T1
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <21> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <21> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <21> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <21> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> DDRA_CLK0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 AR1
HD26# HA29# <13> DDRA_CLK1 SM_CK1
H_D#27 W7 C14 H_A#30 AW7 A27 CLK_MCH_DREFCLK#

CLK
HD27# HA30# <14> DDRB_CLK0 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# <15>
H_D#28 U5 D14 H_A#31 AW40 A26 CLK_MCH_DREFCLK
HD28# HA31# <14> DDRB_CLK1 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK <15>
H_D#29 T9
H_D#30 HD29#
W6 HD30# <13> DDRA_CLK0# AW35 SM_CK0# D_REF_SSCLKN C40 CLK_MCH_SSCDREFCLK# CLK_MCH_SSCDREFCLK# <15>
H_D#31 T5 AT1 D41 CLK_MCH_SSCDREFCLK
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
DDRA_CLK1#
DDRB_CLK0# AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP CLK_MCH_SSCDREFCLK <15>
H_D#33 AA9 G8 H_REQ#1 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 <14> DDRB_CLK1# SM_CK3# CLK_REQ# MCH_CLKREQ# <15>
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3
W3 HD35# HREQ#3 F8 <13> DDRA_CKE0 AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 AT20
HD36# HREQ#4 <13> DDRA_CKE1 SM_CKE1
H_D#37 Y7 BA29 A3
HD37# <14> DDRB_CKE0 SM_CKE2 NC0
H_D#38 W5 AY29 A39
HD38# <14> DDRB_CKE1 SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
C HD39# HADSTB#0 H_ADSTB#0 <4> NC2 C
H_D#40 AB8 C13 H_ADSTB#1 AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDRA_SCS0# SM_CS0# NC3
H_D#41 W2 AW12 AW1
HD41# <13> DDRA_SCS1# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDRB_SCS0# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDRB_SCS1# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] <4> <13> DDRA_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V
AB4 HD49# HDSTBP#0 K3 <13> DDRA_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#50 AC9 T6 H_DSTBP#1 AY20 C1
HD50# HDSTBP#1 <14> DDRB_ODT0 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 AU21 AY41
HD51# HDSTBP#2 <14> DDRB_ODT1 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R33 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R518 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 +DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 T32

HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32

HD59# RESERVED2
R35

R283

H_D#60 AB5 <21> PM_BMBUSY# PM_BMBUSY# G28 PM_BMBUSY# F3

H_D#61 HD60# H_RESET# R164 <13,14> PM_EXTTS#0 PM_EXTTS#0 RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# <4> F25 PM_EXTTS0# RESERVED4 F7

RESERVED
PM
H_D#62 AD4 E8 H_ADS# <21,44> PM_DPRSLPVR 2 1 PM_EXTTS#1 H26 PM_EXTTS1# AG11
HD62# HADS# H_ADS# <4> RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,20> H_THERMTRIP# H_THERMTRIP# G6 PM_THERMTRIP# AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# 0_0402_5% ICH_POK RESERVED6

HDPWR# J9 H_DPWR# <4> <21,31> ICH_POK AH33 PWROK RESERVED7 H7
H8 H_DRD Y# 2 1 PLTRST_R# AH34 RSTIN# J19
HDRDY# H_DRDY#
<16,19,21,23,24,27,29>
<4> PLT_RST_BUF# RESERVED8
J13 C3 H_DEFER# R117 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
+H_VREF K13 D4 H_HITM# <19> MCH_ICH_SYNC# K28 ICH_SYNC# A34
HVREF1 HHITM# H_HITM# <4> RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
HXSCOMP HLOCK# H_LOCK# <4> RESERVED12
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR#
B HYSCOMP HBNR# H_BNR# <4> B
+H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4>
+H_SWNG1 W1 A7 H_DBSY# GM@
HYSWING HDBSY# H_DBSY# <4>
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# <4,20>
24.9_0402_1%

24.9_0402_1%

+DDR_MCH_REF
1

trace width and

R39

R24

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 spacing is 20/20.
D6 H_RS#2 +3VS
HRS2#
H_RS#[0..2] <4>
2

CALISTOGA_FCBGA1466~D +1.8V
GM@
R519

1
10K_0402_5%
R282 PM_EXTTS#0 2 1

Layout Note: 100_0402_1% R279

@ 10K_0402_5%

2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / +DDR_MCH_REF PM_EXTTS#1 2 1
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 10/20.

1 1 R27
+VCCP +VCCP R112
C287

100_0402_1% @ 40.2_0402_1%
+VCCP M_OCDOCMP0 2 1
2

2
221_0603_1%

221_0603_1%
1

1
100_0402_1%

R32
1

R520

R521

@ 40.2_0402_1%
R31

M_OCDOCMP1 2 1
2

+H_SWNG0 +H_SWNG1
2

A +H_VREF A
0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1
1

200_0402_1%

R28
R168

1
R37

C91

C303

C286

2 2
2

2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (1/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 7 of 46
5 4 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
<13> DDRA_SDQ[0..63] <14> DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
<13> DDRA_SDM[0..7] <14> DDRB_SDM[0..7]
DDRA_SMA[0..13] DDRB_SMA[0..13]
<13> DDRA_SMA[0..13] <14> DDRB_SMA[0..13]

D D

U20D U20E

AU12 AJ35 DDRA_SDQ0 AT24 AK39 DDRB_SDQ0

<13> DDRA_SBS0 SA_BS0 SA_DQ0 <14> DDRB_SBS0 SB_BS0 SB_DQ0
AV14 AJ34 DDRA_SDQ1 AV23 AJ37 DDRB_SDQ1
<13> DDRA_SBS1 SA_BS1 SA_DQ1 <14> DDRB_SBS1 SB_BS1 SB_DQ1
BA20 AM31 DDRA_SDQ2 AY28 AP39 DDRB_SDQ2
<13> DDRA_SBS2 SA_BS2 SA_DQ2 <14> DDRB_SBS2 SB_BS2 SB_DQ2
AM33 DDRA_SDQ3 AR41 DDRB_SDQ3
SA_DQ3 DDRA_SDQ4 SB_DQ3 DDRB_SDQ4
SA_DQ4 AJ36 SB_DQ4 AJ38
AK35 DDRA_SDQ5 AK38 DDRB_SDQ5
DDRA_SDM0 SA_DQ5 DDRA_SDQ6 DDRB_SDM0 SB_DQ5 DDRB_SDQ6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDRA_SDM1 AM35 AH31 DDRA_SDQ7 DDRB_SDM1 AR38 AP41 DDRB_SDQ7
DDRA_SDM2 SA_DM1 SA_DQ7 DDRA_SDQ8 DDRB_SDM2 SB_DM1 SB_DQ7 DDRB_SDQ8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDRA_SDM3 AN22 AP33 DDRA_SDQ9 DDRB_SDM3 BA31 AV41 DDRB_SDQ9
DDRA_SDM4 SA_DM3 SA_DQ9 DDRA_SDQ10 DDRB_SDM4 SB_DM3 SB_DQ9 DDRB_SDQ10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDRA_SDM5 AL9 AP31 DDRA_SDQ11 DDRB_SDM5 AH8 AV38 DDRB_SDQ11
DDRA_SDM6 SA_DM5 SA_DQ11 DDRA_SDQ12 DDRB_SDM6 SB_DM5 SB_DQ11 DDRB_SDQ12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDRA_SDM7 AH4 AM36 DDRA_SDQ13 DDRB_SDM7 AN4 AR40 DDRB_SDQ13
SA_DM7 SA_DQ13 DDRA_SDQ14 SB_DM7 SB_DQ13 DDRB_SDQ14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDRA_SDQ15 AY38 DDRB_SDQ15
SA_DQ15 DDRA_SDQ16 SB_DQ15 DDRB_SDQ16
SA_DQ16 AK26 SB_DQ16 BA38
AL27 DDRA_SDQ17 AV36 DDRB_SDQ17
DDRA_SDQS0 SA_DQ17 DDRA_SDQ18 DDRB_SDQS0 SB_DQ17 DDRB_SDQ18
<13> DDRA_SDQS0 AK33 SA_DQS0 SA_DQ18 AM26 <14> DDRB_SDQS0 AM39 SB_DQS0 SB_DQ18 AR36
DDRA_SDQS1 AT33 AN24 DDRA_SDQ19 DDRB_SDQS1 AT39 AP36 DDRB_SDQ19
<13> DDRA_SDQS1 SA_DQS1 SA_DQ19 <14> DDRB_SDQS1 SB_DQS1 SB_DQ19
DDRA_SDQS2 AN28 AK28 DDRA_SDQ20 DDRB_SDQS2 AU35 BA36 DDRB_SDQ20

DDR SYS MEMORY A

DDR SYS MEMORY B

<13> DDRA_SDQS2 SA_DQS2 SA_DQ20 <14> DDRB_SDQS2 SB_DQS2 SB_DQ20
DDRA_SDQS3 AM22 AL28 DDRA_SDQ21 DDRB_SDQS3 AR29 AU36 DDRB_SDQ21
<13> DDRA_SDQS3 SA_DQS3 SA_DQ21 <14> DDRB_SDQS3 SB_DQS3 SB_DQ21
DDRA_SDQS4 AN12 AM24 DDRA_SDQ22 DDRB_SDQS4 AR16 AP35 DDRB_SDQ22
<13> DDRA_SDQS4 SA_DQS4 SA_DQ22 <14> DDRB_SDQS4 SB_DQS4 SB_DQ22
DDRA_SDQS5 AN8 AP26 DDRA_SDQ23 DDRB_SDQS5 AR10 AP34 DDRB_SDQ23
<13> DDRA_SDQS5 SA_DQS5 SA_DQ23 <14> DDRB_SDQS5 SB_DQS5 SB_DQ23
DDRA_SDQS6 AP3 AP23 DDRA_SDQ24 DDRB_SDQS6 AR7 AY33 DDRB_SDQ24
<13> DDRA_SDQS6 SA_DQS6 SA_DQ24 <14> DDRB_SDQS6 SB_DQS6 SB_DQ24
DDRA_SDQS7 AG5 AL22 DDRA_SDQ25 DDRB_SDQS7 AN5 BA33 DDRB_SDQ25
<13> DDRA_SDQS7 SA_DQS7 SA_DQ25 <14> DDRB_SDQS7 SB_DQS7 SB_DQ25
C AP21 DDRA_SDQ26 AT31 DDRB_SDQ26 C
SA_DQ26 DDRA_SDQ27 SB_DQ26 DDRB_SDQ27
SA_DQ27 AN20 SB_DQ27 AU29
DDRA_SDQS0# AK32 AL23 DDRA_SDQ28 DDRB_SDQS0# AM40 AU31 DDRB_SDQ28
<13> DDRA_SDQS0# SA_DQS0# SA_DQ28 <14> DDRB_SDQS0# SB_DQS0# SB_DQ28
DDRA_SDQS1# AU33 AP24 DDRA_SDQ29 DDRB_SDQS1# AU39 AW31 DDRB_SDQ29
<13> DDRA_SDQS1# SA_DQS1# SA_DQ29 <14> DDRB_SDQS1# SB_DQS1# SB_DQ29
DDRA_SDQS2# AN27 AP20 DDRA_SDQ30 DDRB_SDQS2# AT35 AV29 DDRB_SDQ30
<13> DDRA_SDQS2# SA_DQS2# SA_DQ30 <14> DDRB_SDQS2# SB_DQS2# SB_DQ30
DDRA_SDQS3# AM21 AT21 DDRA_SDQ31 DDRB_SDQS3# AP29 AW29 DDRB_SDQ31
<13> DDRA_SDQS3# SA_DQS3# SA_DQ31 <14> DDRB_SDQS3# SB_DQS3# SB_DQ31
DDRA_SDQS4# AM12 AR12 DDRA_SDQ32 DDRB_SDQS4# AP16 AM19 DDRB_SDQ32
<13> DDRA_SDQS4# SA_DQS4# SA_DQ32 <14> DDRB_SDQS4# SB_DQS4# SB_DQ32
DDRA_SDQS5# AL8 AR14 DDRA_SDQ33 DDRB_SDQS5# AT10 AL19 DDRB_SDQ33
<13> DDRA_SDQS5# SA_DQS5# SA_DQ33 <14> DDRB_SDQS5# SB_DQS5# SB_DQ33
DDRA_SDQS6# AN3 AP13 DDRA_SDQ34 DDRB_SDQS6# AT7 AP14 DDRB_SDQ34
<13> DDRA_SDQS6# SA_DQS6# SA_DQ34 <14> DDRB_SDQS6# SB_DQS6# SB_DQ34
DDRA_SDQS7# AH5 AP12 DDRA_SDQ35 DDRB_SDQS7# AP5 AN14 DDRB_SDQ35
<13> DDRA_SDQS7# SA_DQS7# SA_DQ35 <14> DDRB_SDQS7# SB_DQS7# SB_DQ35
AT13 DDRA_SDQ36 AN17 DDRB_SDQ36
SA_DQ36 DDRA_SDQ37 SB_DQ36 DDRB_SDQ37
SA_DQ37 AT12 SB_DQ37 AM16
AL14 DDRA_SDQ38 AP15 DDRB_SDQ38
DDRA_SMA0 SA_DQ38 DDRA_SDQ39 DDRB_SMA0 SB_DQ38 DDRB_SDQ39
AY16 SA_MA0 SA_DQ39 AL12 AY23 SB_MA0 SB_DQ39 AL15
DDRA_SMA1 AU14 AK9 DDRA_SDQ40 DDRB_SMA1 AW24 AJ11 DDRB_SDQ40
DDRA_SMA2 SA_MA1 SA_DQ40 DDRA_SDQ41 DDRB_SMA2 SB_MA1 SB_DQ40 DDRB_SDQ41
AW16 SA_MA2 SA_DQ41 AN7 AY24 SB_MA2 SB_DQ41 AH10
DDRA_SMA3 BA16 AK8 DDRA_SDQ42 DDRB_SMA3 AR28 AJ9 DDRB_SDQ42
DDRA_SMA4 SA_MA3 SA_DQ42 DDRA_SDQ43 DDRB_SMA4 SB_MA3 SB_DQ42 DDRB_SDQ43
BA17 SA_MA4 SA_DQ43 AK7 AT27 SB_MA4 SB_DQ43 AN10
DDRA_SMA5 AU16 AP9 DDRA_SDQ44 DDRB_SMA5 AT28 AK13 DDRB_SDQ44
DDRA_SMA6 SA_MA5 SA_DQ44 DDRA_SDQ45 DDRB_SMA6 SB_MA5 SB_DQ44 DDRB_SDQ45
AV17 SA_MA6 SA_DQ45 AN9 AU27 SB_MA6 SB_DQ45 AH11
DDRA_SMA7 AU17 AT5 DDRA_SDQ46 DDRB_SMA7 AV28 AK10 DDRB_SDQ46
DDRA_SMA8 SA_MA7 SA_DQ46 DDRA_SDQ47 DDRB_SMA8 SB_MA7 SB_DQ46 DDRB_SDQ47
AW17 SA_MA8 SA_DQ47 AL5 AV27 SB_MA8 SB_DQ47 AJ8
DDRA_SMA9 AT16 AY2 DDRA_SDQ48 DDRB_SMA9 AW27 BA10 DDRB_SDQ48
DDRA_SMA10 SA_MA9 SA_DQ48 DDRA_SDQ49 DDRB_SMA10 SB_MA9 SB_DQ48 DDRB_SDQ49
AU13 SA_MA10 SA_DQ49 AW2 AV24 SB_MA10 SB_DQ49 AW10
DDRA_SMA11 AT17 AP1 DDRA_SDQ50 DDRB_SMA11 BA27 BA4 DDRB_SDQ50
DDRA_SMA12 SA_MA11 SA_DQ50 DDRA_SDQ51 DDRB_SMA12 SB_MA11 SB_DQ50 DDRB_SDQ51
AV20 SA_MA12 SA_DQ51 AN2 AY27 SB_MA12 SB_DQ51 AW4
DDRA_SMA13 AV12 AV2 DDRA_SDQ52 DDRB_SMA13 AR23 AY10 DDRB_SDQ52
SA_MA13 SA_DQ52 DDRA_SDQ53 SB_MA13 SB_DQ52 DDRB_SDQ53
SA_DQ53 AT3 SB_DQ53 AY9
AN1 DDRA_SDQ54 AW5 DDRB_SDQ54
SA_DQ54 DDRA_SDQ55 SB_DQ54 DDRB_SDQ55
SA_DQ55 AL2 SB_DQ55 AY5
AY13 AG7 DDRA_SDQ56 AR24 AV4 DDRB_SDQ56
B <13> DDRA_SCAS# SA_CAS# SA_DQ56 <14> DDRB_SCAS# SB_CAS# SB_DQ56 B
AW14 AF9 DDRA_SDQ57 AU23 AR5 DDRB_SDQ57
<13> DDRA_SRAS# SA_RAS# SA_DQ57 <14> DDRB_SRAS# SB_RAS# SB_DQ57
AY14 AG4 DDRA_SDQ58 AR27 AK4 DDRB_SDQ58
<13> DDRA_SWE# SA_WE# SA_DQ58 <14> DDRB_SWE# SB_WE# SB_DQ58
T6 PAD SA_RCVENIN# AK23 AF6 DDRA_SDQ59 T4 PAD SB_RCVENIN# AK16 AK3 DDRB_SDQ59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDRA_SDQ60 SB_RCVENOUT# AK18 SB_RCVENIN# SB_DQ59 DDRB_SDQ60
T12 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T11 PAD SB_RCVENOUT# SB_DQ60 AT4
AH6 DDRA_SDQ61 AK5 DDRB_SDQ61
SA_DQ61 DDRA_SDQ62 SB_DQ61 DDRB_SDQ62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDRA_SDQ63 AJ3 DDRB_SDQ63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
GM@ GM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (2/7)-DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 8 of 46
5 4 3 2 1
 5 4 3 2 1

R113 +1.5VS_PCIE
U20C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38

F34 PCIE_GTX_C_MRX_N0
LVDS_A0 EXP_RXN0 PCIE_GTX_C_MRX_N1
<17> LVDS_A0 B37 LA_DATA0 EXP_RXN1 G38
<17> LVDS_A1 LVDS_A1 B34 H34 PCIE_GTX_C_MRX_N2
LVDS_A2 LA_DATA1 EXP_RXN2 PCIE_GTX_C_MRX_N3
<17> LVDS_A2 A36 LA_DATA2 EXP_RXN3 J38
L34 PCIE_GTX_C_MRX_N4
LVDS_A0# EXP_RXN4 PCIE_GTX_C_MRX_N5
D <17> LVDS_A0# C37 LA_DATA#0 EXP_RXN5 M38 D
<17> LVDS_A1# LVDS_A1# B35 N34 PCIE_GTX_C_MRX_N6
LVDS_A2# LA_DATA#1 EXP_RXN6 PCIE_GTX_C_MRX_N7
<17> LVDS_A2# A37 LA_DATA#2 EXP_RXN7 P38
R34 PCIE_GTX_C_MRX_N8
LVDS_B0 EXP_RXN8 PCIE_GTX_C_MRX_N9
<17> LVDS_B0 F30 LB_DATA0 EXP_RXN9 T38
LVDS_B1 PCIE_GTX_C_MRX_N10 PCIE_MTX_C_GRX_N[0..15]

LVDS
<17> LVDS_B1 D29 LB_DATA1 EXP_RXN10 V34 PCIE_MTX_C_GRX_N[0..15] <16>
<17> LVDS_B2 LVDS_B2 F28 W38 PCIE_GTX_C_MRX_N11
LB_DATA2 EXP_RXN11 PCIE_GTX_C_MRX_N12 PCIE_MTX_C_GRX_P[0..15]
EXP_RXN12 Y34 PCIE_MTX_C_GRX_P[0..15] <16>
<17> LVDS_B0# LVDS_B0# G30 AA38 PCIE_GTX_C_MRX_N13
LVDS_B1# LB_DATA#0 EXP_RXN13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N[0..15]
<17> LVDS_B1# D30 LB_DATA#1 EXP_RXN14 AB34 PCIE_GTX_C_MRX_N[0..15] <16>
<17> LVDS_B2# LVDS_B2# F29 AC38 PCIE_GTX_C_MRX_N15
LB_DATA#2 EXP_RXN15 PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_P[0..15] <16>
LVDS_ACLK A32 D34 PCIE_GTX_C_MRX_P0
<17> LVDS_ACLK LA_CLK EXP_RXP0
LVDS_ACLK# A33 F38 PCIE_GTX_C_MRX_P1
<17> LVDS_ACLK# LA_CLK# EXP_RXP1
LVDS_BCLK E26 G34 PCIE_GTX_C_MRX_P2
<17> LVDS_BCLK LB_CLK EXP_RXP2
LVDS_BCLK# E27 H38 PCIE_GTX_C_MRX_P3
<17> LVDS_BCLK# LB_CLK# EXP_RXP3
J34 PCIE_GTX_C_MRX_P4

PCI-EXPRESS GRAPHICS
EXP_RXP4 PCIE_GTX_C_MRX_P5
D32 LBKLT_CTL EXP_RXP5 L38
<17> GMCH_ENBKL GMCH_ENBKL J30 M34 PCIE_GTX_C_MRX_P6
LBKLT_EN EXP_RXP6 PCIE_GTX_C_MRX_P7
H30 LCTLA_CLK EXP_RXP7 N38
H29 P34 PCIE_GTX_C_MRX_P8
LCTLB_DATA EXP_RXP8 PCIE_GTX_C_MRX_P9
<17> LVDS_SCL G26 LDDC_CLK EXP_RXP9 R38
<17> LVDS_SDA G25 T34 PCIE_GTX_C_MRX_P10
LDDC_DATA EXP_RXP10 PCIE_GTX_C_MRX_P11
<17> GMCH_ENVDD F32 LVDD_EN EXP_RXP11 V38
2 1 B38 W34 PCIE_GTX_C_MRX_P12
R104 1.5K_0402_1% LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15
C32 LVREFL EXP_RXP15 AB38
C F36 PCIE_MTX_GRX_N0 C175 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0 C
EXP_TXN0 PCIE_MTX_GRX_N1 C404 1
A16 TVDAC_A EXP_TXN1 G40 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N1
C18 H36 PCIE_MTX_GRX_N2 C144 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
TVDAC_B EXP_TXN2 PCIE_MTX_GRX_N3 C408 1
A19 TVDAC_C EXP_TXN3 J40 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N3

TV
L36 PCIE_MTX_GRX_N4 C142 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
EXP_TXN4
2 R114 1 J20 TV_IREF EXP_TXN5 M40 PCIE_MTX_GRX_N5 C411 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N5
4.99K_0402_1% N36 PCIE_MTX_GRX_N6 C149 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6
EXP_TXN6 PCIE_MTX_GRX_N7 C423 1
B16 TV_IRTNA EXP_TXN7 P40 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N7
B18 R36 PCIE_MTX_GRX_N8 C172 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8
TV_IRTNB EXP_TXN8 PCIE_MTX_GRX_N9 C465 1 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N9
B19 TV_IRTNC EXP_TXN9 T40 2
V36 PCIE_MTX_GRX_N10 C162 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10
EXP_TXN10 PCIE_MTX_GRX_N11 C441 1
J29 TV_DCONSEL1 EXP_TXN11 W40 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N11
K30 Y36 PCIE_MTX_GRX_N12 C166 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12
TV_DCONSEL0 EXP_TXN12 PCIE_MTX_GRX_N13 C440 1 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N13
EXP_TXN13 AA40 2
AB36 PCIE_MTX_GRX_N14 C177 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14
EXP_TXN14 PCIE_MTX_GRX_N15 C448 1
EXP_TXN15 AC40 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N15
<18> GMCH_CRT_CLK C26 DDCCLK

CRT
<18> GMCH_CRT_DATA C25 D36 PCIE_MTX_GRX_P0 C133 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
DDCDATA EXP_TXP0 PCIE_MTX_GRX_P1 C407 1
EXP_TXP1 F40 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
H23 G36 PCIE_MTX_GRX_P2 C129 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
<18> GMCH_CRT_VSYNC VSYNC EXP_TXP2
G23 H40 PCIE_MTX_GRX_P3 C406 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
<18> GMCH_CRT_HSYNC HSYNC EXP_TXP3
E23 J36 PCIE_MTX_GRX_P4 C178 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
<18> GMCH_CRT_B BLUE EXP_TXP4
2 1 GMCH_CRT_R D23 L40 PCIE_MTX_GRX_P5 C405 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
R397 GM@ 150_0402_1% BLUE# EXP_TXP5 PCIE_MTX_GRX_P6 C167
<18> GMCH_CRT_G C22 GREEN EXP_TXP6 M36 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
2 1 GMCH_CRT_G B22 N40 PCIE_MTX_GRX_P7 C419 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
R526 GM@ 150_0402_1% GREEN# EXP_TXP7 PCIE_MTX_GRX_P8 C161 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
<18> GMCH_CRT_R A21 RED EXP_TXP8 P36 1 2
2 1 GMCH_CRT_B B21 R40 PCIE_MTX_GRX_P9 C426 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
R524 GM@ 150_0402_1% RED# EXP_TXP9 PCIE_MTX_GRX_P10 C155
EXP_TXP10 T36 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10
V40 PCIE_MTX_GRX_P11 C429 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
B EXP_TXP11 B
2 R122 1 J22 CRT_IREF EXP_TXP12 W36 PCIE_MTX_GRX_P12 C173 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12
255_0402_1% Y40 PCIE_MTX_GRX_P13 C437 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
EXP_TXP13 PCIE_MTX_GRX_P14 C170
EXP_TXP14 AA36 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
AB40 PCIE_MTX_GRX_P15 C464 1 2 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
EXP_TXP15

CALISTOGA_FCBGA1466~D
GM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (3/7)-DDRII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 9 of 46
5 4 3 2 1
 5 4 3 2 1

+VCCP

2
D21 @

+2.5VS
RB751V-40TE17_SOD323-2
1 1 U20H
+VCCP H22 1 2
VCC_SYNC C396
R531 +2.5VS AC14 0.1U_0402_16V4Z
VTT0
AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS
@ 10_0402_5% W14 C30
VTT2 VCCTX_LVDS1 +1.5VS_PCIE R86
V14 A30
2

D VTT3 VCCTX_LVDS2 0_0805_5% D

T14 VTT4 W=40 mils

220U_B2_2.5VM_R35
R14 VTT5 VCC3G0 AB41 2 1 +1.5VS

10U_1206_6.3V6M

10U_1206_6.3V6M
P14 VTT6 VCC3G1 AJ41
+1.5VS N14 L41
VTT7 VCC3G2 1
M14 VTT8 VCC3G3 N41 1 1
L14 R41 C438 +
VTT9 VCC3G4
2

+2.5VS

C134

C605

0.1U_0402_16V4Z
D19 @ AD13 V41
VTT10 VCC3G5
220U_B2_2.5VM_R35
AC13 VTT11 VCC3G6 Y41
2 2 2
AB13 VTT12 1
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL

C430
RB751V-40TE17_SOD323-2 Y13 G41 +2.5VS
1 1

VTT14 VCCA_3GBG
C604

+ W13 H41
VTT15 VSSA_3GBG 2 +1.5VS_DPLLA +1.5VS_DPLLB
V13 VTT16
R530 +3VS U13 R878 L42 L43
2 VTT17 +2.5VS_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 2 1 +2.5VS 1 2 +1.5VS 1 2 +1.5VS

10U_0805_6.3V6M
@ 10_0402_5% R13 F21 10_0603_5% FBM-L10-160808-301-T_0603 FBM-L10-160808-301-T_0603
VTT19 VCCA_CRTDAC1

0.022U_0402_16V7K

0.1U_0402_16V4Z

330U_D2E_2.5VM

GM@ C417

0.1U_0402_16V4Z

330U_D2E_2.5VM

GM@ C145
0.1U_0402_16V4Z
N13 G21 close pin G41
2

VTT20 VSSA_CRTDAC2
M13 VTT21 1 1 1 1 1
L13 VTT22 1 1

C124

C431
C432
+ +
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA CRTDAC: Route caps within

C442
AA12 VTT24 VCCA_DPLLB C39 +1.5VS_DPLLB
Y12 AF1 +1.5VS_HPLL
2 2 2 250mil of Alviso. Route FB
VTT25 VCCA_HPLL 2 2 2 2

C619
W12 VTT26 within 3" of Calistoga
V12 VTT27
U12 VTT28 VCCA_LVDS A38 +2.5VS
T12 VTT29 VSSA_LVDS B39
R12 VTT30
P12 +2.5VS
VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
+3VS_TVDACA +3VS_TVDACA +3VS_TVDACA +3VS

0.01U_0402_16V7K
4.7U_0805_10V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z
L12 VTT34 VCCA_TVBG H20 +3VS_TVBG
R11 G20 R528
C VTT35 VSSA_TVBG C
1 1 P11 VTT36 2 1
C168

C121

N11 1 1 0_0603_5%
VTT37

0.022U_0402_16V7K

0.022U_0402_16V7K
C397

C126

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19 1 1 1 1 1
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACA 2 2

C425

C153

C140
N10 VTT41 VCCA_TVDACB1 D20

C400

C606
M10 VTT42 VCCA_TVDACC0 E20 +3VS_TVDACA 2 2 2 2 2
P9 VTT43 VCCA_TVDACC1 F20
N9 VTT44
M9 VTT45 close pin A38
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48
M8 +3VS_TVBG +3VS
VTT49 R529
P7 VTT50 VCCD_LVDS0 A28
N7 VTT51 VCCD_LVDS1 B28 2 1
M7 C28 10_0805_1%
VTT52 VCCD_LVDS2

0.022U_0402_16V7K
0.1U_0402_16V4Z
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS_TVDAC 1 1
M6 VTT55 VCCDQ_TVDAC H19

C608
MCH_A6 A6 VTT56
0.47U_0603_10V7K

C607
R5 VTT57 VCCHV0 A23 +3VS 2 2
P5 VTT58 VCCHV1 B23
0.1U_0402_16V4Z

10U_1206_6.3V6M
1 N5 VTT59 VCCHV2 B25
C602

M5 VTT60 1 1
P4 VTT61 VCCAUX0 AK31
N4 VTT62 VCCAUX1 AF31
2
C394

C424
M4 VTT63 VCCAUX2 AE31
2 2
R3 VTT64 VCCAUX3 AC31
P3 AL30
N3
VTT65
VTT66
VCCAUX4
VCCAUX5 AK30 PCI-E/MEM/PSB PLL decoupling
0.22U_0603_10V7K

M3 VTT67 VCCAUX6 AJ30

B
R2 AH30 +1.5VS B
VTT68 VCCAUX7
P2 VTT69 VCCAUX8 AG30
+1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.1U_0402_16V4Z

1 M2 AF30 R87 R527

VTT70 VCCAUX9
C165

MCH_D2 D2 AE30 0_0603_5% 0_0603_5%

VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1 2 1 2 1
0.22U_0603_10V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_1206_6.3V6M
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12

0.022U_0402_16V7K
C422

1 P1 VTT74 VCCAUX13 AG29

C163

N1 VTT75 VCCAUX14 AF29 1 1 1 1 1 1

2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

C130

C603

C410

C143

C402
VCCAUX16 AD29
2

C148
1 VCCAUX17 AC29
2 2 2 2 2 2
C600

VCCAUX18 AG28
VCCAUX19 AF28
AE28 @ @
2 VCCAUX20
VCCAUX21 AH22
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
+1.5VS_MPLL R85 +1.5VS_HPLL R17
AF13 VCCAUX36 VCCAUX27 P19
AE13 P16 0_0603_5% 0_0603_5%
+1.5VS VCCAUX37 VCCAUX28
AF12 VCCAUX38 VCCAUX29 AH15 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
AE12 VCCAUX39 VCCAUX30 P15

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_1206_6.3V6M

10U_1206_6.3V6M
AD12 VCCAUX40 VCCAUX31 AH14

1 1 1 1
CALISTOGA_FCBGA1466~D

C154

C157

C601

C427
GM@
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (4/7)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 10 of 46
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U20F CFG[19:18] have internal pull down

+VCCP +1.5VS +VCCP U20G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_10V7K

0.47U_0603_10V7K
D D
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C139
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C158
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30
C159

C115

C127

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG6 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 10 = 1.05V*(Default)
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG10 CFG18 01 = 1.5V
1U_0603_10V4Z
10U_1206_6.3V6M

10U_1206_6.3V6M

T25 W17 T30 AJ27

P O W E R

VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1

R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C118

C138

C112

C146
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C136

C114

C119

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
C
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present C
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
220U_B2_2.5VM_R35

V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22

1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
C150

C141
+ R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22
2 R124
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 <7> CFG5 1 2 @ 2.2K_0402_5%
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R88 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 <7> CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R110 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 <7> CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R123 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 <7> CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19

10U_1206_6.3V6M

10U_1206_6.3V6M
R20 N26 AW19 R125 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 <7> CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19
V19 AE26 N25 AU19 1 1 R109 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 <7> CFG13
U19 VCC_NCTF62 VSS_NCTF2 AE25 M25 VCC62 VCC_SM62 AT19

C137

C122
T19 AE24 L25 AR19 R108 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 <7> CFG16
AD18 VCC_NCTF64 VSS_NCTF4 AE23 P24 VCC64 VCC_SM64 AP19
2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
AB18 VCC_NCTF66 VSS_NCTF6 AE21 M24 VCC66 VCC_SM66 AJ19
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
B B
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
U18 Y17 N23 AH16 +3VS
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_10V7K
AC22 AW15 R131 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R130 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R126 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C128
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C147

C164

GM@ AB20 VCC89 VCC_SM89 AY8

Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6
A A

CALISTOGA_FCBGA1466~D
GM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (5/7)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 11 of 46
5 4 3 2 1
 5 4 3 2 1

U20I U20J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
D AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9 D
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
C F39 N29 AM15 B6 C
VSS39 VSS139 VSS239 VSS319
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
B B
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23 GM@
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
A AN34 VSS96 VSS196 A22 A
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21
CALISTOGA_FCBGA1466~D
GM@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline (6/7)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 12 of 46
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JP25
9/25 Change DIMM0 to SP070004Z00 (HBL50) +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5
DDRA_SDQ1 DQ0 DQ5 R195
7 DQ1 VSS 8
9 10 DDRA_SDM0 +DIMM_VREF
DDRA_SDQS0# VSS DM0 1K_0402_1%
<8> DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ6
20mils
13 14

2
<8> DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18 1 1
DQ2 VSS

1
DDRA_SDQ3 19 20 DDRA_SDQ12 C224 C225 1
D DQ3 DQ12 DDRA_SDQ13 R198 C221 D
21 VSS DQ13 22
DDRA_SDQ9 23 24 0.1U_0402_16V4Z 2.2U_0805_10V6K
DDRA_SDQ8 DQ8 VSS DDRA_SDM1 2 2 1K_0402_1% 220P_0402_50V7K
25 DQ9 DM1 26
2 @
27 28

2
DDRA_SDQS1# VSS VSS
<8> DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 <7>
DDRA_SDQS1 31 32
<8> DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# <7>
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
45 DQ17 DQ21 46
47 VSS VSS 48
DDRA_SDQS2# 49 50 R207 1 2 0_0402_5%
<8> DDRA_SDQS2# DQS2# NC PM_EXTTS#0 <7,14> DDRA_SMA[0..13]
DDRA_SDQS2 51 52 DDRA_SDM2 <8> DDRA_SMA[0..13] Layout Note:
<8> DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ22 DDRA_SDQ[0..63] Place near JP35
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23 <8> DDRA_SDQ[0..63]
57 DQ19 DQ23 58
59 60 DDRA_SDM[0..7] +1.8V
VSS VSS <8> DDRA_SDM[0..7]
DDRA_SDQ24 61 62 DDRA_SDQ28
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29
63 DQ25 DQ29 64
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3# 1 1 1 1 1
EC_TX_P80_DATA 69 DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# <8> C232 C245 C233 C242 C246
<14,31,33> EC_TX_P80_DATA NC DQS3 70 DDRA_SDQS3 <8>
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 2 2 2 2 2
75 DQ27 DQ31 76
77 78 +0.9VS
DDRA_CKE0 VSS VSS DDRA_CKE1
<7> DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 <7>
C DDRA_CKE0 C
81 VDD VDD 82 1 4
EC_RX_P80_CLK 83 84 DDRA_SBS2 2 3
<14,31,33> EC_RX_P80_CLK NC NC/A15
DDRA_SBS2 85 86 RP14 56_0404_4P2R_5%
<8> DDRA_SBS2 BA2 NC/A14 +1.8V
87 VDD VDD 88
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SMA12 1 4
A12 A11

220U_B2_2.5VM_R35
DDRA_SMA9 91 92 DDRA_SMA7 DDRA_SMA9 2 3
DDRA_SMA8 A9 A7 DDRA_SMA6 RP15 56_0404_4P2R_5%
93 A8 A6 94
95 VDD VDD 96 1 1 1 1 1
DDRA_SMA5 97 98 DDRA_SMA4 DDRA_SMA8 1 4 C243 C244 C230 C231
A5 A4

C614
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_SMA5 2 3 +
DDRA_SMA1 A3 A2 DDRA_SMA0 RP16 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
101 A1 A0 102
2 2 2 2 @
103 VDD VDD 104
DDRA_SMA10 DDRA_SBS1 DDRA_SMA3 2
105 A10/AP BA1 106 DDRA_SBS1 <8> 1 4
DDRA_SBS0 107 108 DDRA_SRAS# DDRA_SMA1 2 3
<8> DDRA_SBS0 BA0 RAS# DDRA_SRAS# <8>
DDRA_SWE# 109 110 DDRA_SCS0# RP17 56_0404_4P2R_5%
<8> DDRA_SWE# WE# S0# DDRA_SCS0# <7>
111 VDD VDD 112
DDRA_SCAS# 113 114 DDRA_ODT0 DDRA_SMA10 1 4
<8> DDRA_SCAS# CAS# ODT0 DDRA_ODT0 <7>
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SBS0 2 3
<7> DDRA_SCS1# NC/S1# NC/A13
117 118 RP18 56_0404_4P2R_5%
DDRA_ODT1 VDD VDD +0.9VS
<7> DDRA_ODT1 119 NC/ODT1 NC 120
121 122 DDRA_SWE# 1 4
DDRA_SDQ32 VSS VSS DDRA_SDQ36 DDRA_SCAS#
123 DQ32 DQ36 124 2 3
DDRA_SDQ33 125 126 DDRA_SDQ37 RP19 56_0404_4P2R_5%
DQ33 DQ37
127 VSS VSS 128 1 1 1 1 1
DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_SCS1# 1 4 C235 C236 C237 C238 C239
<8> DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 DDRA_ODT1
<8> DDRA_SDQS4 131 DQS4 VSS 132 2 3
133 134 DDRA_SDQ38 RP20 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39 2 2 2 2 2
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45 DDRA_SMA11 1 4
DDRA_SDQ41 DQ40 DQ45 DDRA_CKE1
143 DQ41 VSS 144 2 3
B
145 146 DDRA_SDQS5# RP21 56_0404_4P2R_5% +0.9VS B
DDRA_SDM5 VSS DQS5# DDRA_SDQS5 DDRA_SDQS5# <8>
147 DM5 DQS5 148 DDRA_SDQS5 <8>
149 150 DDRA_SMA6 1 4
DDRA_SDQ42 VSS VSS DDRA_SDQ46 DDRA_SMA7
151 DQ42 DQ46 152 2 3
DDRA_SDQ43 153 154 DDRA_SDQ47 RP22 56_0404_4P2R_5% 1 1 1 1 1
DQ43 DQ47 C240 C241 C250 C251 C252
155 VSS VSS 156
DDRA_SDQ48 157 158 DDRA_SDQ52 DDRA_SMA2 1 4
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
159 DQ49 DQ53 160 2 3
EC_RX_P80_CLK R201 1 0_0402_5% RP23 56_0404_4P2R_5% 2 2 2 2 2
2 161 VSS VSS 162
EC_RX_P80_CLK_R 163 164
<14> EC_RX_P80_CLK_R NC,TEST CK1 DDRA_CLK1 <7>
165 166 DDRA_SBS1 1 4
VSS CK1# DDRA_CLK1# <7>
DDRA_SDQS6# 167 168 DDRA_SMA0 2 3
<8> DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6 RP24 56_0404_4P2R_5%
<8> DDRA_SDQS6 169 DQS6 DM6 170
171 172 +0.9VS
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SCS0#
173 DQ50 DQ54 174 1 4
DDRA_SDQ51 175 176 DDRA_SDQ55 DDRA_SRAS# 2 3
DQ51 DQ55 RP25 56_0404_4P2R_5%
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60 1 1 1
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_SMA13 C253 C254 C255
181 DQ57 DQ61 182 1 4
183 184 DDRA_ODT0 2 3
DDRA_SDM7 VSS VSS DDRA_SDQS7# RP26 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
185 DM7 DQS7# 186 DDRA_SDQS7# <8>
DDRA_SDQS7 2 2 2
187 VSS DQS7 188 DDRA_SDQS7 <8>
DDRA_SDQ58 189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
D_CK_SDATA VSS DQ63
<14,15,23> D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 R204 1 2 10K_0402_5%
<14,15,23> D_CK_SCLK SCL SA0
+3VS 199 200 R205 1 2 10K_0402_5%
VDDSPD SA1
Layout Note:
TYCO_292526-4 Layout Note: Place one cap close to every 2 pullup
A +3VS
ME@ Pla ce these resistor resistors terminated to +0.9VS A
Change PCB Footprint closely JP35,all
trace length Max=1.5"
1 1
DIMM0 STD H:5.2mm (BOT)
@ C234 C228

0.1U_0402_16V4Z
2
2.2U_0805_10V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 13 of 46
5 4 3 2 1
 A B C D E

9/25 Change DIMM1 to SP070006F00

+1.8V +1.8V
+DIMM_VREF
JP23
+DIMM_VREF 1 VREF VSS 2
3 4 DDRB_SDQ1
DDRB_SDQ5 VSS DQ4 DDRB_SDQ0 DDRB_SMA[0..13]
5 DQ0 DQ5 6 <8> DDRB_SMA[0..13] 1 1
DDRB_SDQ4 7 8 C199 C200
DQ1 VSS DDRB_SDM0 DDRB_SDQ[0..63]
9 VSS DM0 10 <8> DDRB_SDQ[0..63]
DDRB_SDQS0# 11 12 2.2U_0805_10V6K
1 <8> DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6 DDRB_SDM[0..7] 2 2
0.1U_0402_16V4Z 1
<8> DDRB_SDQS0 13 DQS0 DQ6 14 <8> DDRB_SDM[0..7]
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
<8> DDRB_SDQS1# DQS1# CK0 DDRB_CLK1 <7>
DDRB_SDQS1 31 32
<8> DDRB_SDQS1 DQS1 CK0# DDRB_CLK1# <7>
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
0_0402_5%
Layout Note:
47 VSS VSS 48
DDRB_SDQS2# 49 50 R199 1 2 PM_EXTTS#0 <7,13>
Place near JP34
<8> DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2
<8> DDRB_SDQS2 51 DQS2 DM2 52
53 VSS VSS 54
DDRB_SDQ19 55 56 DDRB_SDQ18
DDRB_SDQ22 DQ18 DQ22 DDRB_SDQ23 +1.8V
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29
63 DQ25 DQ29 64
65 VSS VSS 66 1 1 1 1 1
DDRB_SDM3 67 68 DDRB_SDQS3# C483 C487 C219 C220 C216
EC_TX_P80_DATA DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# <8>
<13,31,33> EC_TX_P80_DATA 69 NC DQS3 70 DDRB_SDQS3 <8>
71 72 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
2 DDRB_SDQ26 VSS VSS DDRB_SDQ30 +0.9VS 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31
DQ27 DQ31
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1 DDRB_CKE0 1 4
<7> DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 <7>
81 82 DDRB_SBS2 2 3
EC_RX_P80_CLK VDD VDD RP1 56_0404_4P2R_5% +1.8V
<13,31,33> EC_RX_P80_CLK 83 NC NC/A15 84
DDRB_SBS2 85 86
<8> DDRB_SBS2 BA2 NC/A14
87 88 DDRB_SMA12 1 4
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_SMA9
89 A12 A11 90 2 3
DDRB_SMA9 91 92 DDRB_SMA7 RP2 56_0404_4P2R_5% 1 1 1 1
DDRB_SMA8 A9 A7 DDRB_SMA6 C218 C217 C482 C479
93 A8 A6 94
95 96 DDRB_SMA8 1 4
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA5 0.1U_0402_16V4Z 0.1U_0402_16V4Z
97 A5 A4 98 2 3
DDRB_SMA3 DDRB_SMA2 RP3 56_0404_4P2R_5% 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
99 A3 A2 100
DDRB_SMA1 101 102 DDRB_SMA0
A1 A0 DDRB_SMA3
103 VDD VDD 104 1 4
DDRB_SMA10 105 106 DDRB_SBS1 DDRB_SMA1 2 3
A10/AP BA1 DDRB_SBS1 <8>
DDRB_SBS0 107 108 DDRB_SRAS# RP4 56_0404_4P2R_5%
<8> DDRB_SBS0 BA0 RAS# DDRB_SRAS# <8>
DDRB_SWE# 109 110 DDRB_SCS0#
<8> DDRB_SWE# WE# S0# DDRB_SCS0# <7>
111 112 DDRB_SMA10 1 4
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SBS0
<8> DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 <7> 2 3
DDRB_SCS1# 115 116 DDRB_SMA13 RP5 56_0404_4P2R_5% +0.9VS
<7> DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 DDRB_SWE# 1 4
<7> DDRB_ODT1 NC/ODT1 NC
121 122 DDRB_SCAS# 2 3
DDRB_SDQ32 VSS VSS DDRB_SDQ36 RP6 56_0404_4P2R_5%
123 DQ32 DQ36 124 1 1 1 1 1
DDRB_SDQ33 125 126 DDRB_SDQ37 C192 C193 C194 C195 C196
DQ33 DQ37 DDRB_SCS1#
127 VSS VSS 128 1 4
DDRB_SDQS4# 129 130 DDRB_SDM4 DDRB_ODT1 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<8> DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4 RP7 56_0404_4P2R_5% 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
<8> DDRB_SDQS4 131 DQS4 VSS 132
133 134 DDRB_SDQ38
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39
135 DQ34 DQ39 136
3 DDRB_SDQ35 DDRB_SMA11 3
137 DQ35 VSS 138 1 4
139 140 DDRB_SDQ44 DDRB_CKE1 2 3
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 RP8 56_0404_4P2R_5% +0.9VS
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
DQ41 VSS DDRB_SDQS5# DDRB_SMA6
145 VSS DQS5# 146 DDRB_SDQS5# <8> 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_SMA7 2 3
DM5 DQS5 DDRB_SDQS5 <8> RP9 56_0404_4P2R_5%
149 VSS VSS 150 1 1 1 1 1
DDRB_SDQ42 151 152 DDRB_SDQ46 C197 C198 C203 C204 C205
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA2
153 DQ43 DQ47 154 1 4
155 156 DDRB_SMA4 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ48 VSS VSS DDRB_SDQ52 RP10 56_0404_4P2R_5% 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
157 DQ48 DQ52 158
DDRB_SDQ49 159 160 DDRB_SDQ53
DQ49 DQ53 DDRB_SBS1
161 VSS VSS 162 1 4
EC_RX_P80_CLK_R 163 164 DDRB_SMA0 2 3
<13> EC_RX_P80_CLK_R NC,TEST CK1 DDRB_CLK0 <7> +0.9VS
165 166 RP11 56_0404_4P2R_5%
VSS CK1# DDRB_CLK0# <7>
DDRB_SDQS6# 167 168
<8> DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SCS0#
<8> DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SRAS# 2 3
DDRB_SDQ50 VSS VSS DDRB_SDQ55 RP12 56_0404_4P2R_5%
173 DQ50 DQ54 174 1 1 1
DDRB_SDQ54 175 176 DDRB_SDQ51 C206 C207 C208
DQ51 DQ55 DDRB_SMA13
177 VSS VSS 178 1 4
DDRB_SDQ56 179 180 DDRB_SDQ60 DDRB_ODT0 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61 RP13 56_0404_4P2R_5% 2 2
0.1U_0402_16V4Z 2
181 DQ57 DQ61 182
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7#
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# <8>
187 VSS DQS7 188 DDRB_SDQS7 <8>
DDRB_SDQ58 189 190
DDRB_SDQ59 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
<13,15,23> D_CK_SDATA 195 SDA VSS 196 Layout Note: Layout Note:
D_CK_SCLK 197 198 R196 1 2 10K_0402_5%
<13,15,23> D_CK_SCLK SCL SAO R197
Pla ce these resistor Place one cap close to every 2 pullup
+3VS 199 VDDSPD SA1 200 1 2 10K_0402_5% +3VS
4 closely JP35,all 4
resistors terminated to +0.9VS
trace length Max=1.5"
TYCO_292530-4
ME@

DIMM1 STD H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 14 of 46
A B C D E
 5 4 3 2 1

FSLC FSLB FSLA CPU SRC PCI +3VS +CK_VDD_MAIN1

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
+3VS 1 2
R552 R434 R430 0_0805_5% 1 1 1 1 1 1 1
0 0 1 133 100 33.3 C343 C338 C336 C434 C335 C337 C472
2.2K_0402_5% 2.2K_0402_5%
Q34 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2N7002_SOT23 2 2 2 2 2 2 2
0 1 1 166 100 33.3
D_CK_SDATA

S
<21,24,29> ICH_SMBDATA 1 3
Table : ICS954306 +CK_VDD_MAIN2

G
2
D C480 2 D
FSB Frequency Selet: +3VS 1 2 1 27P_0402_50V8J
+3VS R400 0_0805_5% 1 1 1

1
C418 @ C463 @ C474
Stuff CLK_Ra CLK_Rb CLK_Rc Y3

2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CLK_XTAL_IN 14.31818MHZ_20P_6X1430004201

G
CPU Driven 2 2 2

2
D_CK_SCLK CLK_XTAL_OUT
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf
<21,24,29> ICH_SMBCLK 1 3
C471
2 1
27P_0402_50V8J

S
Stuff CLK_Rd CLK_Re CLK_Rf 2N7002_SOT23 L19
533MHz Q32 U23 1 2 +3VS
+CK_VDD_MAIN1
1 1 FBM-L10-160808-301-T_0603
No Stuff CLK_Ra CLK_Rb CLK_Rc C466 C485 Place crystal within
1 VDDSRC VDDA 7 500 mils of CK410
49 0.1U_0402_16V4Z 10U_0805_10V4Z
VDDSRC 2 2
Stuff CLK_Rd CLK_Rf 54 8 1 2
65
VDDSRC
VDDSRC
GNDA R865 0_0402_5% Place near U4
667MHz
No Stuff CLK_Ra CLK_Rb CLK_Rc 25 H_STP_PCI#
PCI_SRC_STOP# H_STP_PCI# <21>
30 VDDPCI
CLK_Re 36 24 H_STP_CPU#
VGATE <21,44> VDDPCI CPU_STOP# H_STP_CPU# <21>
12 VDDCPU
+VCCP 11 CLK_MCH_BCLK
CPUCLKT1LP CLK_MCH_BCLK <7>

2
+CK_VDD_MAIN2

G
1 2 18 VDDREF
C477 0.1U_0402_16V4Z 10 CLK_MCH_BCLK#
CPUCLKC1LP CLK_MCH_BCLK# <7>
2

CLK_ENABLE# 1 3 1 2 +CK_VDD_MAIN2
40
@ R456 C433 0.1U_0402_16V4Z VDD48

S
56_0402_5% 14 CLK_CPU_BCLK
CPUCLKT0LP CLK_CPU_BCLK <4>
R396 CLK_Rd 2N7002_SOT23 CLK_XTAL_IN 20
8.2K_0402_5% X1 CLK_CPU_BCLK#
Q40 13 CLK_CPU_BCLK# <4>
1

FSA 2 CPUCLKC0LP
1 1 2 MCH_CLKSEL0 <7>
C CLK_XTAL_OUT C
19 X2
1 2 R327 6
<5> CPU_BSEL0 CPUCLKT2_ITP/SRCCLKT10LP
R451 1K_0402_5% R408
0_0402_5% <21> CLK_ICH_48M CLK_ICH_48M 2 1 FSA 41 5
USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1

CLK_Ra 33_0402_5%
R553 FSB 45 FSLB/TEST_MODE/24Mhz
SRCCLKT9LP 3
@ 1K_0402_5% <21> CLK_ICH_14M CLK_ICH_14M 2 1 CLKREF1 23
R418 33_0402_5% REF0/FSLC/TEST_SEL
2
2

SRCCLKC9LP
PCI_MINI 34 72
PCICLK4/FCTSEL1 CLKREQ9#
+VCCP 33_0402_5% 2 1 R545 PCI_EC 33 70
<31> CLK_PCI_LPC SEL_48M/PCICLK3 SRCCLKT8LP
32 SEL_24M/PCICLK2 SRCCLKC8LP 69
2

R129 PCI6 27 71
SEL_PCI6/PCICLK1 CLKREQ8#
@ 1K_0402_5% 66 CLK_PCIE_SATA
SRCCLKT7LP CLK_PCIE_SATA <20>
PCI5 22
1

FSB SEL_PCI5/REF1 CLK_PCIE_SATA#

1 2 <16> CLK_27M_VGA
MCH_CLKSEL1 <7> 1 2 SRCCLKC7LP 67 CLK_PCIE_SATA# <20>
R450 @ 0_0402_5%
1 2 R127 <7> CLK_MCH_DREFCLK CLK_MCH_DREFCLK1 2 MCH_DREFCLK 43 38 SATA_CLKREQ#
<5> CPU_BSEL1 DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 SATA_CLKREQ# <21>
R132 1K_0402_5% R440 GM@ 0_0402_5%
0_0402_5% <7> CLK_MCH_DREFCLK# CLK_MCH_DREFCLK#
1 2 MCH_DREFCLK# 44 63 CLK_PCIE_EXP
DOTC_96MHz/27MHz_spread SRCCLKT6LP CLK_PCIE_EXP <24>
1

CLK_Rb <16> CLK_27M_VGA# R5401 GM@ 20_0402_5%

@ R120 R534 @ 0_0402_5% 64 CLK_PCIE_EXP#
SRCCLKC6LP CLK_PCIE_EXP# <24>
CLK_PCI_ICH 2 R392 1 PCI_ICH 37
<19> CLK_PCI_ICH ITP_EN/PCICLK_F0
0_0402_5% 33_0402_5% 62 EXP_CLKREQ#
CLKREQ6# EXP_CLKREQ# <24>
CLK_Re
2

CLK_ENABLE# 39 60 CLK_MCH_3GPLL
<44> CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_MCH_3GPLL <7>
B CLK_MCH_3GPLL# B
SRCCLKC5LP 61 CLK_MCH_3GPLL# <7>
+VCCP
<13,14,23> D_CK_SCLK D_CK_SCLK 16 29 MCH_CLKREQ#
SMBCLK CLKREQ5#/PCICLK6 MCH_CLKREQ# <7>
2

58 CLK_PCIE_ICH
SRCCLKT4LP CLK_PCIE_ICH <21>
R542
D_CK_SDATA 17 59 CLK_PCIE_ICH#
<13,14,23> D_CK_SDATA SMBDAT SRCCLKC4LP CLK_PCIE_ICH# <21>
R547 @ 1K_0402_5%
8.2K_0402_5% 57
1

CLKREF1 2 CLKREQ4#
1 1 2 MCH_CLKSEL2 <7>
CLKIREF 9 55 CLK_PCIE_LAN
GND SRCCLKT3LP CLK_PCIE_LAN <29>
1 2 R551
<5> CPU_BSEL2
R399 1K_0402_5% 4 56 CLK_PCIE_LAN#
GNDSRC SRCCLKC3LP CLK_PCIE_LAN# <29>
0_0402_5%
1

CLK_Rc 15 28 CLKREQ_LAN#
+3VS +3VS +3VS +3VS GNDCPU CLKREQ3#/PCICLK5 CLKREQ_LAN# <29>
@ R390
ITP PCI6 PCI5 21 52 CLK_PCIE_WLAN
GNDREF SRCCLKT2LP CLK_PCIE_WLAN <23>
0_0402_5%
1

CLK_Rf 31 53 CLK_PCIE_WLAN#
CLK_PCIE_WLAN# <23>
2

R448 R444 R557 R555 GNDPCI SRCCLKC2LP

35 26 W LAN_CLKREQ#
GNDPCI CLKREQ2# WLAN_CLKREQ# <23>
10K_0402_5% 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5%
42 50 CLK_PCIE_VGA
CLK_PCIE_VGA <16>
2

CLK_ENABLE# PCI_ICH PCI6 PCI5 GND48 SRCCLKT1LP

68 51 CLK_PCIE_VGA#
GNDSRC SRCCLKC1LP CLK_PCIE_VGA# <16>
1

R532 R537 R549 @ R415 46

CLKREQ1# SATA_CLKREQ# 2 1 +3VS
@ 10K_0402_5% @ 10K_0402_5% 10K_0402_5% 10K_0402_5% 47 CLK_MCH_SSCDREFCLK R407 10K_0402_5%
LCD100/96/SRC0_TLP CLK_MCH_SSCDREFCLK <7>
CLKREQ_LAN# 2 1
2

+3VS 48 CLK_MCH_SSCDREFCLK# @ R141 10K_0402_5%

LCD100/96/SRC0_CLP CLK_MCH_SSCDREFCLK# <7>
W LAN_CLKREQ# 2 1
A R140 WLAN@ 10K_0402_5% A
73 GND
1

PCI_MINI = FCTSEL1 EXP_CLKREQ# 2 1

R445 PCI_PME=SEL_PCI6 SLG8LP465VTR_QFN72 R142 10K_0402_5%
FCTSEL1 MCH_CLKREQ# 1 2
@ 10K_0402_5% PIN43 PIN44 PIN47 PIN48 R870 10K_0402_5%
(PIN34) PCI6 PIN27
2

PCI_MINI
0 CLKREQ5 Security Classification Compal Secret Data Compal Electronics, Inc.
1

0 DOT96T DOT96C 96/100M_T 96/100M_C

R401 1 PCICLK6 2006/08/04 2006/10/06 Title
Issued Date Deciphered Date
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
1 27Mout 27MSSout SRCT0 SRCC0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 15 of 46
5 4 3 2 1
 5 4 3 2 1

D D
MAX. 4.06A @ 1.8V

<9> PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15] MAX. 130mA @ 2.5V
PCIE_MTX_C_GRX_P[0..15]
<9> PCIE_MTX_C_GRX_P[0..15] MAX. 655mA @ 3.3V
PCIE_GTX_C_MRX_N[0..15]
<9> PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
<9> PCIE_GTX_C_MRX_P[0..15]

JP19 JP20
1 1 41 41 1 1 41 41
PCIE_MTX_C_GRX_P1 2 42 PCIE_GTX_C_MRX_P1 PCIE_MTX_C_GRX_P0 2 42 PCIE_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N1 2 42 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_N0 2 42 PCIE_GTX_C_MRX_N0
3 3 43 43 3 3 43 43
4 4 44 44 4 4 44 44
PCIE_MTX_C_GRX_P3 5 45 PCIE_GTX_C_MRX_P3 PCIE_MTX_C_GRX_P2 5 45 PCIE_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N3 5 45 PCIE_GTX_C_MRX_N3 PCIE_MTX_C_GRX_N2 5 45 PCIE_GTX_C_MRX_N2
6 6 46 46 6 6 46 46
7 7 47 47 7 7 47 47
PCIE_MTX_C_GRX_P5 8 48 PCIE_GTX_C_MRX_P5 PCIE_MTX_C_GRX_P4 8 48 PCIE_GTX_C_MRX_P4
PCIE_MTX_C_GRX_N5 8 48 PCIE_GTX_C_MRX_N5 PCIE_MTX_C_GRX_N4 8 48 PCIE_GTX_C_MRX_N4
9 9 49 49 9 9 49 49
10 10 50 50 10 10 50 50
PCIE_MTX_C_GRX_P7 11 51 PCIE_GTX_C_MRX_P7 PCIE_MTX_C_GRX_P6 11 51 PCIE_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N7 11 51 PCIE_GTX_C_MRX_N7 PCIE_MTX_C_GRX_N6 11 51 PCIE_GTX_C_MRX_N6
12 12 52 52 12 12 52 52
13 13 53 53 13 13 53 53
C PCIE_MTX_C_GRX_P9 PCIE_GTX_C_MRX_P9 PCIE_MTX_C_GRX_P8 PCIE_GTX_C_MRX_P8 C
14 14 54 54 14 14 54 54
PCIE_MTX_C_GRX_N9 15 55 PCIE_GTX_C_MRX_N9 PCIE_MTX_C_GRX_N8 15 55 PCIE_GTX_C_MRX_N8
15 55 15 55
16 16 56 56 16 16 56 56
PCIE_MTX_C_GRX_P11 17 57 PCIE_GTX_C_MRX_P11 PCIE_MTX_C_GRX_P10 17 57 PCIE_GTX_C_MRX_P10 +5VS +2.5VS
PCIE_MTX_C_GRX_N11 17 57 PCIE_GTX_C_MRX_N11 PCIE_MTX_C_GRX_N10 17 57 PCIE_GTX_C_MRX_N10
18 18 58 58 18 18 58 58
19 19 59 59 19 19 59 59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PCIE_MTX_C_GRX_P13 20 60 PCIE_GTX_C_MRX_P13 PCIE_MTX_C_GRX_P12 20 60 PCIE_GTX_C_MRX_P12
PCIE_MTX_C_GRX_N13 20 60 PCIE_GTX_C_MRX_N13 PCIE_MTX_C_GRX_N12 20 60 PCIE_GTX_C_MRX_N12
21 21 61 61 21 21 61 61
22 22 62 62 22 22 62 62 2 2 2 2

C174

C176

C454

C458
PCIE_MTX_C_GRX_P15 23 63 PCIE_GTX_C_MRX_P15 PCIE_MTX_C_GRX_P14 23 63 PCIE_GTX_C_MRX_P14
PCIE_MTX_C_GRX_N15 23 63 PCIE_GTX_C_MRX_N15 PCIE_MTX_C_GRX_N14 23 63 PCIE_GTX_C_MRX_N14
24 24 64 64 24 24 64 64
25 25 65 65 25 25 65 65
+1.8VS SUSP# 1 1 1 1
+3VS 26 26 66 66 +5VS <15> CLK_PCIE_VGA 26 26 66 66 SUSP# <24,31,36,40,42,43>
+1.5VS 27 67 27 67 VGA_THER_ALERT#
27 67 <15> CLK_PCIE_VGA# 27 67 VGA_THER_ALERT# <21>
28 68 28 68 PM@ PM@ @ @
28 68 28 68
29 29 69 69 <18> VGA_DDCCLK 29 29 69 69
+2.5VS 30 70 30 70
30 70 <18> VGA_DDCDATA 30 70 VGA_ENBKL <17>
31 31 71 71 31 31 71 71 PLT_RST_BUF# <7,19,21,23,24,27,29>
32 32 72 72 <18> VGA_VSYNC 32 32 72 72 CLK_27M_VGA <15>
33 73 B+ 33 73
33 73 33 73 CLK_27M_VGA# <15>
34 34 74 74 <18> VGA_HSYNC 34 34 74 74
35 35 75 75 35 35 75 75
36 76 36 76 +3VS
36 76 <18> VGA_CRT_R 36 76
37 37 77 77 37 37 77 77
38 38 78 78 <18> VGA_CRT_G 38 38 78 78

0.047U_0402_16V4Z

0.047U_0402_16V4Z
39 39 79 79 39 39 79 79
40 40 80 80 <18> VGA_CRT_B 40 40 80 80

HRS_FX8-80P-SV1(92) HRS_FX8-80P-SV1(92) 1 1

C444

C445
ME@ ME@

B 2 2 B

PM@ PM@

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number
VGA/B connector Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.2
Custom IEL10 LA-3451P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, May 18, 2007 Sheet 16 of 46
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT INVERTER Conn.

+3VALW +3VS
+LCDVDD
W=60mils

1
1 JP3

1
R90 C329
470_0603_5% R271 1
4.7U_0805_10V4Z 2
GM@ 100K_0402_5%
2 GM@ B+ <31> INVT_PWM
BKOFF# 3
GM@

1 2
4
<31> DAC_BRIG

2
5

3
D S
G 2 1+INVPWR_B+ 6
D GM@ Q6 Q29 L1 D
2 2 1 2 7
2N7002_SOT23 G R270 GM@ 1K_0402_5% SI2301BDS_SOT23 FBMA-L11-201209-221LMA30T_0805
S GM@ MOLEX_53780-0790

3
2 D C14 ME@
C330

1
1
+LCDVDD 0.1U_0603_50V4Z
Q39 0.047U_0402_16V7K W=60mils
1 GM@
DTC124EK_SC59
GM@
<9> GMCH_ENVDD 2 1 1
C334 C333

4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 GM@ 2 GM@

3
<9> GMCH_ENBKL 2 1 ENBKL
ENBKL <31>
R69 GM@ 0_0402_5%

2
<16> VGA_ENBKL 2 1
R72 PM@ 0_0402_5% R66

100K_0402_5%

1
LCD/PANEL BD. Conn.
ME@
ACES_87216-3006
31 GNDGND 32

<9> LVDS_A0# LVDS_A0# 15 30 LVDS_B0# LVDS_B0# <9>

LVDS_A0 15 30 LVDS_B0
<9> LVDS_A0 14 14 29 29 LVDS_B0 <9>
C C
13 13 28 28
<9> LVDS_A1# LVDS_A1# 12 27 LVDS_B1# LVDS_B1# <9>
LVDS_A1 12 27 LVDS_B1
<9> LVDS_A1 11 11 26 26 LVDS_B1 <9>
10 25 BKOFF#
10 25 <31> BKOFF#
<9> LVDS_A2# LVDS_A2# 9 24 LVDS_B2# LVDS_B2# <9>
LVDS_A2 9 24 LVDS_B2
<9> LVDS_A2 8 8 23 23 LVDS_B2 <9>

1
7 7 22 22
LVDS_ACLK# 6 21 LVDS_BCLK# R6
<9> LVDS_ACLK# 6 21 LVDS_BCLK# <9>
LVDS_ACLK 5 20 LVDS_BCLK
<9> LVDS_ACLK 5 20 LVDS_BCLK <9>
4 19 100K_0402_5%
+LCDVDD_L 4 19 LVDS_SDA
+LCDVDD 2 1 3 18

2
3 18 LVDS_SCL
(60 MIL) 2 2 17 17
GM@ 1 16 +3VS
1 16
L18 JP16
FBMA-L11-201209-221LMA30T_0805

Follow HEL80's pin definition

Except pin 29

+3VS
2.2K_0402_5%

2.2K_0402_5%

B B
1

1
R220

R285
GM@

GM@
2

<9> LVDS_SCL LVDS_SCL

<9> LVDS_SDA LVDS_SDA

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 17 of 46
5 4 3 2 1
 A B C D E

CRT Connector

1 1

Place closed to chipset L2

BK1608LL121-T 0603
1 2 CRT_R_1 1 2 RED
<16> VGA_CRT_R
R78 1 2 PM@ 0_0402_5% L3
<9> GMCH_CRT_R
R91 GM@ 0_0402_5% BK1608LL121-T 0603
1 2 CRT_G_1 1 2 GREEN
<16> VGA_CRT_G
R80 1 2 PM@ 0_0402_5% L4
<9> GMCH_CRT_G
R93 GM@ 0_0402_5% BK1608LL121-T 0603
1 2 CRT_B_1 1 2 BLUE
<16> VGA_CRT_B
R79 1 2 PM@ 0_0402_5%
<9> GMCH_CRT_B

1
R92 GM@ 0_0402_5%

1
R8 R9 1 1 1
R12 C15 C16 C17 +5VS +CRT_VCC
1 1 1
150_0402_1% C6 C13 C12 D1 W=40mils

2
2 @ 2 @ 2 @ 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 2 1

2
150_0402_1% 22P_0402_50V8J @ 2 @ 2 2 @
150_0402_1% 22P_0402_50V8J 22P_0402_50V8J RB411DT146_SOT23-3
1
+CRT_VCC JVGA_HS C5
1 2
L5 FCM1608C-121T_0603 0.1U_0402_16V4Z
2
1 2 2 1
C34 0.1U_0402_16V4Z R30 1K_0402_5% 1 2 JVGA_VS
L6 FCM1608C-121T_0603

1
U2
1 1

OE#
1 2 2 4 CRT_HSYNC_1 C11
<16> VGA_HSYNC A Y
R82 PM@ 0_0402_5% C10

G
1 2 10P_0402_50V8J 10P_0402_50V8J
2 <9> GMCH_CRT_HSYNC 2 2 2
R81 GM@ 39_0402_5% SN74AHCT1G125DCKR_SC70-5

3
+CRT_VCC
+CRT_VCC @ @
Place closed to chipset
1 2
C42 0.1U_0402_16V4Z JP1

1
U3 1
RED 1
2

OE#
CRT_VSYNC_1 2
<16> VGA_VSYNC 1 2 2 A Y 4 3 3
R83 PM@ 0_0402_5% GREEN 4
PIN ASSIGMENT 4

G
<9> GMCH_CRT_VSYNC 1 2 5 5
R84 GM@ 39_0402_5% SN74AHCT1G125DCKR_SC70-5 BLUE 6

3
6
7
PIN D-SUB FUNCTION JVGA_VS
JVGA_HS
8
9
7
8
VGA_DDC_DAT 9
Update Footprint 10
1 9 +CRT_VCC VGA_DDC_CLK
PIN4
11
12
10
11
12
2 1 RED 1 13
C7 GND1
14
3 6 GND @
GND2
ACES_87213-1200G
2 0.1U_0402_16V4Z ME@

+3VS
4 2 GREEN
+CRT_VCC
5 7 GND
2.2K 2.2K
6 3 BLUE
1

3 R53 2.2K_0402_5% 3

2.2K_0402_5% R60 +3VS 7 8 GND

1

1
2

R62 R56

2 1 2.2K_0402_5% 2.2K_0402_5%
8 14 VSYNC
<16> VGA_DDCDATA 0_0402_5% PM@ R58
10 GND
2

2
2
G

1 2 3 1 VGA_DDC_DAT
<9> GMCH_CRT_DATA 0_0402_5% GM@ R55 9 13 HSYNC
S

Q2
2
G

2N7002_SOT23

1 2 3 1 VGA_DDC_CLK
11 SENSE
<9> GMCH_CRT_CLK 0_0402_5% GM@ R61
S

Q3
2N7002_SOT23
10 12 SM_DAT
2 1
<16> VGA_DDCCLK 0_0402_5% PM@ R64
@ C9
1 1 11 15 SM_CLK
2 @ C8 2
12
100P_0402_50V8J 68P_0402_50V8K
5 GND
4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 18 of 46
A B C D E
 5 4 3 2 1

U29B
E18 D7 PCI_REQ#0
AD0 REQ0#
C18 AD1 GNT0# E7
PCI_REQ#1
+3VS
A16
F18
AD2 PCI REQ1# C16
D16
AD3 GNT1# PCI_REQ#2
E16 AD4 REQ2# C17
A18 AD5 GNT2# D17
E17 E13 PCI_REQ#3
R97 AD6 REQ3#
1 2 8.2K_0402_5% PCI_DEVSEL# A17 AD7 GNT3# F13
A15 A13 PCI_REQ#4
R96 AD8 REQ4# / GPIO22
D 1 2 8.2K_0402_5% PCI_STOP# C14 AD9 GNT4# / GPIO48 A14 D
E14 C8 PCI_REQ#5
R281 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_TRDY# D14 AD11 GPIO17 / GNT5# D8
B12 AD12
R101 1 2 8.2K_0402_5% PCI_FRAME# C13 B15
AD13 C/BE0#
G15 AD14 C/BE1# C12
R111 1 2 8.2K_0402_5% PCI_PLOCK# G13 D12
AD15 C/BE2#
E12 AD16 C/BE3# C15
R278 1 2 8.2K_0402_5% P CI_IRDY# C11 AD17 P CI_IRDY#
D11 AD18 IRDY# A7
R297 1 2 8.2K_0402_5% PCI_SERR# A11 E10
AD19 PAR PCI_RST#
A10 AD20 PCIRST# B18 PCI_RST# <31>
R107 1 2 8.2K_0402_5% PCI_PERR# F11 A12 PCI_DEVSEL#
AD21 DEVSEL# PCI_PERR#
F10 AD22 PERR# C9
E9 E11 PCI_PLOCK#
AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10
+3VS B9 F15 PCI_STOP#
AD25 STOP# PCI_TRDY#
A8 AD26 TRDY# F14
A6 F16 PCI_FRAME#
R301 1 AD27 FRAME#
2 8.2K_0402_5% PCI_PIRQA# C7 AD28
B6 C26 PCI_PLTRST#
R128 1 AD29 PLTRST#
2 8.2K_0402_5% PCI_PIRQB# E6 AD30 PCICLK A9 CLK_PCI_ICH
CLK_PCI_ICH <15> Place closely pin A9
D6 B19 PCI_PME#
AD31 PME# PCI_PME# <31>
R139 1 2 8.2K_0402_5% PCI_PIRQC#
CLK_PCI_ICH
R99 2 8.2K_0402_5% PCI_PIRQD#
1 Interrupt I/F

2
PCI_PIRQA# A3 G8 PCI_PIRQE#
R298 1 PIRQA# GPIO2 / PIRQE#
2 8.2K_0402_5% PCI_PIRQE# PCI_PIRQB# B4 PIRQB# GPIO3 / PIRQF# F7 PCI_PIRQF# R302
PCI_PIRQC# C5 F8 PCI_PIRQG#
R300 1 PIRQC# GPIO4 / PIRQG#
C 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQD# B5 PIRQD# GPIO5 / PIRQH# G7 PCI_PIRQH# @ 10_0402_5% C

1
R296 1 2 8.2K_0402_5% PCI_PIRQG#
AE5
MISC AE9
RSVD[1] RSVD[6] 1
R121 1 2 8.2K_0402_5% PCI_PIRQH# AD5 AG8 C371
RSVD[2] RSVD[7]
AG4 RSVD[3] RSVD[8] AH8
R116 1 2 8.2K_0402_5% PCI_REQ#0 AH4 F21 @ 8.2P_0402_50V
RSVD[4] RSVD[9] 2
AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# <7>
R102 1 2 8.2K_0402_5% PCI_REQ#1

R103 1 2 8.2K_0402_5% PCI_REQ#2 ICH7_BGA652~D

R100 1 2 8.2K_0402_5% PCI_REQ#3

R119 1 2 8.2K_0402_5% PCI_REQ#4

R133 1 2 8.2K_0402_5% PCI_REQ#5

+3VS

C611
1 2

0.1U_0402_16V4Z

U21

5
NC7SZ08P5X_NL_SC70-5
PCI_PLTRST# 2

P
B B B
Y 4 PLT_RST_BUF# <7,16,21,23,24,27,29>
1 A

1
3
R370

100K_0402_5%
1 2

2
@ R340 0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8M(1/4)-PCI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 19 of 46
5 4 3 2 1
 5 4 3 2 1

+RTCVCC
C344
15P_0402_50V8J
2 1 ICH_RTCX1

10M_0402_5%
R291
Y4

1
32.768K_1TJS125BJ4A421P

R115
1M_0402_5% 2 1
NC IN

2
SM_INTRUDER# 3 4
NC OUT U29A
LPC_AD[0..3] <31>

2
C346

RTC
15P_0402_50V8J AB1 AA6 LPC_AD0
+RTCVCC ICH_RTCX2 RTXC1 LAD0 LPC_AD1
2 1 AB2 RTCX2 LAD1 AB5
AC4 LPC_AD2
D R308 1 ICH_RTCRST# LAD2 LPC_AD3 D
+RTCVCC 2 AA3 RTCRST# LAD3 Y6

LPC
20K_0402_5%
1

ICH_INTVRMEN W4 AC3
R304 @ J2 SM_INTRUDER# INTVRMEN LDRQ0#
Y5 INTRUDER# LDRQ1# / GPIO23 AA5
1 2
332K_0402_1% 3MM AB3 LPC_FRAME#
LFRAME# LPC_FRAME# <31>
W1
2

EE_CS
Y1 EE_SHCLK 2 1 R274 10K_0402_5% +3VS
ICH_INTVRMEN C392 Y2 AE22 GATEA20
EE_DOUT A20GATE GATEA20 <31>

LAN
1U_0603_10V4Z W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# <4>

CPU
1 2
V3 AG27 H_CPUSLP_R# 2 @ 1 R361 0_0402_5%
LAN_CLK CPUSLP# H_CPUSLP# <4,7>
U3 AF24 DPRSLP# 2 1 R292 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# <4,44>
AH25 H_DPSLP#
TP2 / DPSLP# H_DPSLP# <4>
U5 2 1 56_0402_5% +VCCP
HD A_SYNC_ICH LAN_RXD0 H_FERR# R356
<25> HDA_SYNC_AUDIO 1 2 V4 LAN_RXD1 FERR# AG26 H_FERR# <4>
R363 33_0402_5% T5 LAN_RXD2 H_PW RGOOD
<24> HDA_SYNC_MDC 1 2 GPIO49 / CPUPWRGD AG24 H_PWRGOOD <4>
R368 33_0402_5% MDC@ U7 LAN_TXD0 H_IGNNE#
V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# <4>
<25> HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_ICH V7 AG21
R348 33_0402_5% LAN_TXD2 INIT3_3V# H_INIT#
INIT# AF22 H_INIT# <4>
<24> HDA_BITCLK_MDC 1 2 AF25 H_INTR
INTR H_INTR <4>
R349 33_0402_5% MDC@
+VCCP

AC-97/AZALIA
HDA_BITCLK_ICH U1
HDA_RST_ICH# HD A_SYNC_ICH ACZ_BCLK KB_RST#
<25> HDA_RST_AUDIO# 1 2 R6 ACZ_SYNC RCIN# AG23 KB_RST# <31>
R365 33_0402_5%

1
<24> HDA_RST_MDC# 1 2 HDA_RST_ICH# R5 AF23 H_SMI#
ACZ_RST# SMI# H_SMI# <4>
R364 33_0402_5% MDC@ AH24 H_NMI R293
NMI H_NMI <4>
<25> HDA_SDIN0 T2 ACZ_SDIN0
<25> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH <24> HDA_SDIN1 T3 AH22 H_STPCLK# 56_0402_5%
C ACZ_SDIN1 STPCLK# H_STPCLK# <4> C
R367 33_0402_5% T1

2
ACZ_SDIN2 THRMTRIP_ICH#
<24> HDA_SDOUT_MDC 1 2 THERMTRIP# AF26 1 R362 2 H_THERMTRIP# <4,7>
R366 33_0402_5% MDC@ HDA_SDOUT_ICH T4 24.9_0402_1%
ACZ_SDOUT
IDE_DA[0..2] <27>
AH17 IDE_DA0
SATA_LED# DA0 IDE_DA1
close ICH7 <27> SATA_LED# AF18 SATALED# DA1 AE17
IDE_DA2
DA2 AF17

<27> SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 2 1 SATA_ITX_DRX_P0 <27> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AF3 AE16 IDE_DCS1# IDE_DCS1# <27>
SATA_DTX_C_IRX_P0 SATA0RXN DCS1# IDE_DCS3#
<27> SATA_DTX_C_IRX_P0 AE3 SATA0RXP DCS3# AD16 IDE_DCS3# <27>
C436 1000P_0402_50V7K SATA_ITX_DRX_N0 AG2 SATA0TXN

SATA
SATA_ITX_C_DRX_N0 2 1 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 AH2 IDE_DD[0..15] <27>
<27> SATA_ITX_C_DRX_N0 SATA0TXP IDE_DD0
DD0 AB15
C435 1000P_0402_50V7K R702 1 2 1K_0402_5% AF7 AE14 IDE_DD1
R703 1K_0402_5% SATA2RXN DD1 IDE_DD2
1 2 AE7 SATA2RXP DD2 AG13
SATA RX n/p need tie to GND when no used AG6 AF13 IDE_DD3
SATA2TXN DD3 IDE_DD4
AH6 SATA2TXP DD4 AD14
AC13 IDE_DD5
CLK_PCIE_SATA# DD5 IDE_DD6
<15> CLK_PCIE_SATA# AF1 SATA_CLKN DD6 AD12
CLK_PCIE_SATA AE1 AC12 IDE_DD7
<15> CLK_PCIE_SATA SATA_CLKP DD7
AE12 IDE_DD8
R280 DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12
1 2 AG10 AB13 IDE_DD10
+3VS SATARBIASP DD10 IDE_DD11
DD11 AC14
24.9_0402_1% AF14 IDE_DD12
DD12 IDE_DD13
DD13 AH13
IDE_DD14
4.7K_0402_5% 2 1 R347 IDE_ DIORDY IDE_ DIORDY AG16
IDE DD14 AH14
AC15 IDE_DD15
<27> IDE_DIORDY IORDY DD15
8.2K_0402_5% 2 1 R346 IDE_IRQ IDE_IRQ AH16
<27> IDE_IRQ IDEIRQ
10K_0402_5% 2 1 R339 SATA_LED# IDE_DDACK# AF16
<27> IDE_DDACK# DDACK#
IDE_DIOW# AH15 AE15 IDE_DDREQ
<27> IDE_DIOW# DIOW# DDREQ IDE_DDREQ <27>
IDE_DIOR# AF15
B <27> IDE_DIOR# DIOR# B

ICH7_BGA652~D

BATT1.1

+RTCVCC

R118
+ BATT1
-
1 2 1 2
W=20mils
2 100_0603_1%
C345
1 2 +CHGRTC ML1220T13RE
0.1U_0402_16V4Z 45@
1
D9
RB751V-40TE17_SOD323-2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8M(2/4)-LAN,IDELPC,RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 20 of 46
5 4 3 2 1
 5 4 3 2 1

+3VS Place closely pin B2 Place closely pin AC1

CLK_ICH_48M CLK_ICH_14M
+3V_STB +3V_STB

1
10K_0402_5%
R311 1 2 SERIRQ R313 R334

1
2

2
8.2K_0402_5% R333 R330 @ 10_0402_5% @ 10_0402_5%
R329 1 2 PM_CLKRUN# R325 R310

2
2.2K_0402_5% 2.2K_0402_5% U29C
D 10K_0402_5% 10K_0402_5% 10K_0402_5% D
1 1

2
R328 1 2VGA_THER_ALERT# <15,24,29> ICH_SMBCLK ICH_SMBCLK C22 AF19 C385 C395

1
GM@ ICH_SMBDATA SMBCLK GPIO21 / SATA0GP
<15,24,29> ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18

SMB
SATA
GPIO
LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R289 2
ICH_SMLINK1 A25 100_0402_5%
SMLINK1
+3V_STB +3V_STB
R312 AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M <15>

Clocks
10K_0402_5% 1 2 I CH_RI# A28 B2 CLK_ICH_48M
RI# CLK48 CLK_ICH_48M <15>
R326 1 2 LINKALERT# 8.2K_0402_5%
SB_SPKR A19
<25> SB_SPKR SPKR
10K_0402_5% PAD T41 SUS_STAT# A27 C20 ICH_SUSCLK T44 PAD
R317 1 SUS_STAT# SUSCLK
2 ITP_DBRESET# <4> ITP_DBRESET#
ITP_DBRESET# A22 SYS_RST#

SYS
B24 PM_SLP_S3#
SLP_S3# PM_SLP_S3# <31>
10K_0402_5% PM_BMBUSY# AB18 D23 PM_SLP_S4# PM_SLP_S4# <31>
R275 1 <7> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4#
2 OCP# SLP_S5# F22 PM_SLP_S5# PM_SLP_S5# <31>
OCP# B23
<4> OCP# GPIO11 / SMBALERT#
10K_0402_5% AA4 ICH_POK @ R319
PWROK ICH_POK <7,31>

POWER MGT
R320 1 2 SPI_MISO H_STP_PCI# AC20 1 2 10K_0402_5%
<15> H_STP_PCI# GPIO18 / STPPCI#

GPIO
H_STP_CPU# AF21 AC22 1 2 PM_DPRSLPVR
<15> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR <7,44>
10K_0402_5% R105 100_0402_5%
R321 1 2 SB_SPI_CS# <27> IDERST_CD#
IDERST_CD# A21 GPIO26 TP0 / BATLOW# C21 ICH_LOW_BAT#

B21 C23 PBTN_OUT#

GPIO27 PWRBTN# PBTN_OUT# <31>
E23 GPIO28
C19 PLT_RST_BUF#
LAN_RST# PLT_RST_BUF# <7,16,19,23,24,27,29>
1K_0402_5% PM_CLKRUN# AG18
R290 1 GPIO32 / CLKRUN# EC_RSMRST#
2 ICH_PCIE_WAKE# RSMRST# Y4 EC_RSMRST# <31>
AC19 R318 10K_0402_5%
8.2K_0402_5% GPIO33 / AZ_DOCK_EN#
U2 GPIO34 / AZ_DOCK_RST# 1 2
R272 2 1 ICH_LOW_BAT#
C 10K_0402_5% ICH_PCIE_WAKE# F20 EC_SCI# C
<23,24,29> ICH_PCIE_WAKE# WAKE# GPIO9 E20 EC_SCI# <31>
@ R309 1 2 WL_ON SERIRQ AH21 A20
<31> SERIRQ SERIRQ GPIO10 ACIN <31,38>
EC_THERM# AF20 F19 PM_DPRSLPVR 2 1
<4,31> EC_THERM# THRM# GPIO12
10K_0402_5% E19 EC_LID_OUT# @ R106
GPIO13 EC_LID_OUT# <31>
R294 1 2 SPI_MOSI VGATE AD22 R4 100K_0402_5%
<15,44> VGATE VRMPWRGD GPIO14
E22 CPUSB# CPUSB# <24>
GPIO15 WL_ON
GPIO24 R3

VGA_THER_ALERT#
AC21
AC18
GPIO6 GPIO GPIO25 D20
AD21 SATA_CLKREQ#
<16> VGA_THER_ALERT# GPIO7 GPIO35 / SATAREQ# SATA_CLKREQ# <15>
EC_SMI# E21 AD20
<31> EC_SMI# GPIO8 GPIO38
GPIO39 AE20

ICH7_BGA652~D Need update symbol

U29D
PCIE_PTX_C_IRX_N1 F26 V26 DMI_RXN0
<24> PCIE_PTX_C_IRX_N1 PERn1 DMI0RXN DMI_RXN0 <7>
PCIE_PTX_C_IRX_P1 F25 V25 DMI_RXP0
<24> PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_RXP0 <7>

DIRECT MEDIA INTERFACE

NEW Card <24> PCIE_ITX_C_PRX_N1 C107 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N1 E28 U28 DMI_TXN0
PETn1 DMI0TXN DMI_TXN0 <7>
<24> PCIE_ITX_C_PRX_P1 C104 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P1 E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 <7>
PCIE_PTX_C_IRX_N2 H26 Y26 DMI_RXN1
<23> PCIE_PTX_C_IRX_N2 PERn2 DMI1RXN DMI_RXN1 <7>
WLAN WLAN@ PCIE_PTX_C_IRX_P2 H25 Y25 DMI_RXP1
<23> PCIE_PTX_C_IRX_P2 PERp2 DMI1RXP DMI_RXP1 <7>
<23> PCIE_ITX_C_PRX_N2 C101 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N2 G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 <7>
<23> PCIE_ITX_C_PRX_P2 C99 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P2 G27 W27 DMI_TXP1 USB_OC#3
PETp2 DMI1TXP DMI_TXP1 <7>
WLAN@ USB_OC#1 RP27

PCI-EXPRESS
PCIE_PTX_C_IRX_N3 K26 AB26 DMI_RXN2 USB_OC#5 4 5
<29> PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN DMI_RXN2 <7> +3V_STB
LAN PCIE_PTX_C_IRX_P3 K25 AB25 DMI_RXP2 USB_OC#7 USB_OC#2 3 6
<29> PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP DMI_RXP2 <7>
<29> PCIE_ITX_C_PRX_N3 C97 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_N3 J28 AA28 DMI_TXN2 USB_OC#4 2 7
PETn3 DMI2TXN DMI_TXN2 <7>
<29> PCIE_ITX_C_PRX_P3 C92 2 1 0.1U_0402_10V7K PCIE_ITX_PRX_P3 J27 AA27 DMI_TXP2 USB_OC#0 1 8
B PETp3 DMI2TXP DMI_TXP2 <7> B
USB_OC#6
M26 AD25 DMI_RXN3 10K_1206_8P4R_5%
PERn4 DMI3RXN DMI_RXN3 <7>
M25 AD24 DMI_RXP3
PERp4 DMI3RXP DMI_RXP3 <7>
L28 AC28 DMI_TXN3
PETn4 DMI3TXN DMI_TXN3 <7>
L27 AC27 DMI_TXP3
PETp4 DMI3TXP DMI_TXP3 <7>
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# <15>
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH <15>
N28 PETn5
N27 C25 R332 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 PERn6
T24 F1 USB20_N0
PERp6 USBP0N USB20_N0 <35>
R28 F2 USB20_P0
R27
PETn6 USBP0P
G4 USB20_N1
USB20_P0 <35> USB
PETp6 USBP1N USB20_N1 <23>
USB20_P1
R2
USBP1P G3
H1 USB20_N2
USB20_P1 <23> BT
SPI_CLK USBP2N USB20_N2 <24>
SB_SPI_CS# USB20_P2
P6 SPI_CS# USBP2P H2 USB20_P2 <24> New Card
SPI

P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 <23>
USB20_P3
SPI_MOSI P5
USBP3P J3
K1 USB20_N4
USB20_P3 <23> WLAN
SPI_MOSI USBP4N USB20_N4 <35>
SPI_MISO P2 K2 USB20_P4
SPI_MISO USBP4P
L4 USB20_N5
USB20_P4 <35> USB
USBP5N USB20_N5 <28>
L5 USB20_P5
USB_OC#0 D3
USBP5P
M1 USB20_N6
USB20_P5 <28> Card Reader
<35> USB_OC#0 OC0# USBP6N USB20_N6 <35>
USB_OC#1 USB20_P6
USB_OC#2
C4
D5
OC1# USB USBP6P M2
N4 USB20_N7
USB20_P6 <35> USB
<24> USB_OC#2 OC2# USBP7N USB20_N7 <35>
USB_OC#3 USB20_P7
USB_OC#4
D4
E5
OC3# USBP7P N3 USB20_P7 <35> USB
<35> USB_OC#4 OC4#
USB_OC#5 C3 R322 22_0402_1%
USB_OC#6 OC5# / GPIO29 USBRBIAS
<35> USB_OC#6 A2 OC6# / GPIO30 USBRBIAS# D2 1 2
USB_OC#7 B3 D1
A <35> USB_OC#7 OC7# / GPIO31 USBRBIAS A
Within 500 mils
ICH7_BGA652~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8M(3/4)-USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 21 of 46
5 4 3 2 1
 5 4 3 2 1

+VCCP
U29F U29E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C363 C357 + C351 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
0.1U_0402_16V4Z AA22 M11 220U_B2_2.5VM_R35 B20 R16
Vcc1_5_B[1] Vcc1_05[7] 2 2 2 VSS[7] VSS[105]
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS AB22 P11 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
C340 + C339 C379 C348 AB23 P18 C2 T6
D 220U_B2_2.5VM_R35 Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108] D
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

R295 D15 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% RB751V-40TE17_SOD323-2 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 V12 D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
ICH_V5REF_RUN Place closely pin D26 V16 E1 U12
Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
@C362 C361 D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C356 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3V_STB VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C355 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3V_STB H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

D16 @ K22 AB20 1 C353 G6 V28

R303 Vcc1_5_B[26] Vcc3_3[5] C401 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% RB751V-40TE17_SOD323-2 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C359 VSS[36] VSS[133]
M22 AG12 G21 W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C376 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C P23 B13 H4 AA1 C
0.1U_0402_16V4Z Vcc1_5_B[35] Vcc3_3[13] VSS[42] VSS[139]
R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H5 VSS[43] VSS[140] AA24
2
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C388

C350

C354
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C352 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3V_STB K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C384

C373
V23 A24 C386 C378 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3V_STB M4 VSS[62] VSS[159] AD4
R277 R299 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C391 C398 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C382

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C399

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C380 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z AF6 M7 M28 AE11 B
2 Vcc1_5_A[7] VccSus3_3[17] VSS[72] VSS[169]
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C375

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C381

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C377 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C349 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T46 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T15 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T43 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3V_STB Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C372 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C403 P15 AH3
0.1U_0402_16V4Z C374 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T47 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 IC H_Y7 0.1U_0402_16V4Z
T45 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
VccSus3_3/VccLAN3_3[3]
+3V_STB W7 VccSus3_3/VccLAN3_3[4]
A ICH7_BGA652~D A
1
C383

0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IFTXX M/B LA-3541P Schematic
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 22 of 46
5 4 3 2 1
 A B C D E

Mini-Express Card for 3G Or TV Tuner

Mini-Express Card for WLAN
+3VS_WLAN +1.5VS
+3V_WLAN

1 1 1 1 1
C365 C370 C364 C369 C368 1
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ C367
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_25V7K WLAN@
2 2 2 2 2 0.1U_0402_16V4Z
1 2 1

+3VS

JP18 WLAN@

3
<21,24,29> ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 2 +3VS_WLAN R871 1 2 0_0805_5% +3VS 47K
BT_ACTIVE @ R306 1 0_0402_5% 1 2
2 3 3 4 4
WLAN_ACTIVE @ R305 1 2 0_0402_5% 5 6 +1.5VS
W LAN_CLKREQ# 5 6 10K WLAN_LED#
<15> WLAN_CLKREQ# 7 7 8 8 2
9 9 10 10
<15> CLK_PCIE_WLAN# 11 11 12 12
13 14 DTA114YKAT146_SOT23-3
<15> CLK_PCIE_WLAN 13 14 Q41
15 15 16 16
17 18 WLAN@
WLAN_BLUE_LED# <34>

1
17 18 WL_OFF#
19 19 20 20 WL_OFF# <31>
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# <7,16,19,21,24,27,29>
<21> PCIE_PTX_C_IRX_N2 23 24 +3V_WLAN 1 2 +3VALW
23 24 @ R873 1
<21> PCIE_PTX_C_IRX_P2 25 25 26 26 2 0_0402_5% +3VS
27 28 R874 WLAN@ 0_0402_5%
27 28
29 29 30 30 D_CK_SCLK <13,14,15>
<21> PCIE_ITX_C_PRX_N2 31 31 32 32
33 34 D_CK_SDATA <13,14,15>
<21> PCIE_ITX_C_PRX_P2 33 34
35 35 36 36 USB20_N3 <21>
37 37 38 38 USB20_P3 <21>
39 39 40 40
2
41 42 @ R5001 2 0_0402_5% 2
41 42 (WWAN_LED#) WLAN_LED#
43 43 44 44
45 45 46 46

1
D
47 47 48 48
49 50 2 Q43
49 50 G
2005/09/27 modified. 51 51 52 52 2N7002KW_SOT323-3
WLAN@
S

3
Base on OPTION GTM351E Datasheet Rev0.1 53 54 @ R288
GND1 GND2
1 2 +5VS

1
Vcc 3.3V +/- 8% FOX_AS0B226-S56N-7F 100K_0402_5% R875
Peak Icc 2750mA ME@ 100K_0402_5%
with max supply droop 50mA WLAN@

2
Average Icc 1000mA

+5VS
1

R98
10K_0402_1%
BT@
1 2

3 Q9 3
DTC114EKA_SC59-3
BT@
<31> BT_OFF# 2 BT MODULE CONN
+3VS Q8 BT@ +3VS_BT
C60 BT@
3

3 1 2 1
AO3413_SOT23
0.1U_0402_16V4Z
G

<34> BT_LED#
2

JP6
1

1 1
2 2
<21> USB20_N1 USB20_N1 3
USB20_P1 3
<21> USB20_P1 4 4
Q7 2 BTON_LED 5
DTC124EK_SC59 BT_ACTIVE 5
6 6
BT@ WLAN_ACTIVE 7 7
1

8 8
9
3

R94 GND1
10 GND2
10K_0402_5%
BT@ MOLEX_53780-0870
2

ME@

4 4

Security Classification
2006/08/05
Compal Secret Data
2007/08/05 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/3G/FeliCa/FP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 23 of 46
A B C D E
 A B C D E

+1.5VS_CARD1
Imax = 0.75A
New Card Socket (Left/TOP)
1 1
C202 C201
Express Card Power Switch JP9
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
+1.5VS U11 1 GND
+1.5VS_CARD1 40mil <21> USB20_N2 2 USB_D-
2 1 12 1.5Vin 1.5Vout 11 <21> USB20_P2 3 USB_D+
1 C222 0.1U_0402_16V4Z CPUSB# 1
14 1.5Vin 1.5Vout 13 4 CPUSB#
+3VS 5 RSV
+3VS_CARD1 60mils +3VS_CARD1
6 RSV
2 1 2 3.3Vin 3.3Vout 3 <15,21,29> ICH_SMBCLK 7 SMB_CLK
C223 0.1U_0402_16V4Z 4 5 Imax = 1.35A 8
3.3Vin 3.3Vout <15,21,29> ICH_SMBDATA SMB_DATA
+3VALW +3VALW_CARD1 40mil +1.5VS_CARD1 9 +1.5V
2 1 17 AUX_IN AUX_OUT 15 10 +1.5V
C212 0.1U_0402_16V4Z 1 1 <21,23,29> ICH_PCIE_WAKE# 11
PLT_RST_BUF# 6 USB_OC#2 C213 C214 WAKE#
<7,16,19,21,23,27,29> PLT_RST_BUF# SYSRST# OC# 19 USB_OC#2 <21> +3VALW_CARD1 12 +3.3VAUX
PERST# 13
SYSON PERST# 10U_0805_10V4Z 0.1U_0402_16V4Z PERST#
<31,36,42> SYSON 20 SHDN# PERST# 8 +3VS_CARD1 14 +3.3V
2 2
15 +3.3V
SUSP# 1 16 16
<16,31,36,40,42,43> SUSP# STBY# NC <15> EXP_CLKREQ# CLKREQ#
CPUSB# 17 CPPE#
+3VALW 2 R200 1 100K_0402_5% 10 CPPE# GND 7 <15> CLK_PCIE_EXP# 18 REFCLK-
<15> CLK_PCIE_EXP 19 REFCLK+
CPUSB# 9 20
<21> CPUSB# CPUSB# GND
<21> PCIE_PTX_C_IRX_N1 21 PERn0
18 +3VALW_CARD1 22
RCLKEN <21> PCIE_PTX_C_IRX_P1 PERp0
Imax = 0.275A 23 GND
R5538_QFN20 <21> PCIE_ITX_C_PRX_N1 24 PETn0
<21> PCIE_ITX_C_PRX_P1 25 PETp0
1 1 26 GND
@ C210 C211
27 GND GND 29
10U_0805_10V4Z 0.1U_0402_16V4Z 28 30
2 2 GND GND
FOX_1CH4110C
ME@

(NEW)
2 2

3 3

MDC CONN. C559

MDC@
1 2
JP10
1U_0805_25V4Z
1 GND1 RES0 2
<20> HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
5 GND2 3.3V 6 +3V_STB
MDC@ HDA_SYNC_MDC 7 8
<20> HDA_SYNC_MDC IAC_SYNC GND3
<20> HDA_SDIN1 R474 1 2AZ_SDIN3 9 10
HDA_RST_MDC# 33_0402_5% IAC_SDATA_IN GND4
<20> HDA_RST_MDC# 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC <20>

1
GND
GND
GND
GND
GND
GND
R481
10_0402_5%
ACES_88018-124G @
13
14
15
16
17
18
R475 ME@

2
10K_0402_5%
Connector for MDC Rev1.5 1
MDC@
C560
22P_0402_50V8J
2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & USB Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 24 of 46
A B C D E
 A B C D E

+VDDA
AC97 Codec

1
28.7K for Module Design (VDDA = 4.702)
R242
10K_0402_1% +5VS +5VAMP
L17 U15
(output = 250 mA)
60mil 40mil

2
2 1C285 1 2 4 VIN VOUT 5 +VDDA
FBMA-L11-201209-221LMA30T_0805

2
1U_0603_10V4Z +VDDA
1 2 2 DELAY SENSE or ADJ 6 1 4.85V
C272 1 L16 @ 1
R245 1 2 470P_0402_50V7K C567 FBMA-L11-201209-221LMA30T_0805
C280 7 1 R493 C278
10K_0402_1% ERROR CNOISE 150K_0603_1% 10U_0805_10V4Z

1
C271 1U_0603_10V4Z 10U_0805_10V4Z 10U_1206_10V4Z 2
8 3 1

1
2 2 SD GND
1 2MONO_IN1 2 1 MONO_IN C578
1 R238 20K_0402_5% R229 SI9182DH-AD_MSOP8 1

1
1 2 10K_0402_1%
R239 20K_0402_5% 2

2
1
C279 R236 C C573 680P_0402_50V7K LINE_OUTL R492
<31> BEEP# 2 1 1 2 2 Q26 0.1U_0402_16V4Z 51K_0603_1%
1 B 2SC2411KT146_SOT23-3 C572 680P_0402_50V7K LINE_OUTR

2
1
C267 560_0402_5% E

3
1U_0603_10V4Z
@ 0.1U_0402_16V4Z R230
2 10K_0402_1%
C273

1
D
R227

2
<21> SB_SPKR 2 1 1 2 EAPD 2 @Q24
G BSS138LT1G_SOT23-3
1

1
560_0402_5% D11 S SUB WOOFER SUPPORT

3
1U_0603_10V4Z R231
@ 10K_0402_5% RB751V_SOD323
ALC262
2

+MIC2_VREFO +MIC1_VREFO_L +AUD_VREF

ALC861D
Window mode 10mil 10mil 1 10mil
Driver initial 1 1 @
DOS mode @ @ C264
C561 C263 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
ACPI 2 2

GNDA GNDA GNDA

RST
2 2

+VDDC
R218
CHB1608U301_0603
+AVDD_AC97
1 2 +3VS

1 1 1
L40 C257 C258 C259
CHB1608U301_0603
EC_MUTE 12sec +VDDA 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2
1 1 1
C260 0.1U_0402_16V4Z
C569
10U_0805_10V4Z C555 0.1U_0402_16V4Z

25

38

9
2 2 2 U13 1 2
0.1U_0402_16V4Z C262 @ 1000P_0402_50V7K

AVDD1

AVDD2

DVDD1

DVDD2
1 2
C261 @ 1000P_0402_50V7K
DOS mode DOS mode <26> HP_L
HP_L 1 2 14 LINE2_L FRONT_OUT_L 35 C_LINE_OUTL 1 2 LINE_OUTL
LINE_OUTL <26>
C549 4.7U_0603_6.3V6K C566 1U_0603_10V4Z
HP_R 1 2 15 36 C_LINE_OUTR 1 2 LINE_OUTR
<26> HP_R LINE2_R FRONT_OUT_R LINE_OUTR <26>
C552 4.7U_0603_6.3V6K C565 1U_0603_10V4Z
1 2 16 39 C_HP_OUTL 1 2 @ HP_L
C553 2.2U_0603_6.3V6K MIC2_L SURR_OUT_L C557 1U_0603_10V4Z
RST <26> INT_MIC
1 2 17 MIC2_R SURR_OUT_R 41 C_HP_OUTR 1 2 @ HP_R
C556 2.2U_0603_6.3V6K C551 1U_0603_10V4Z
23 LINE1_L SIDESURR_OUT_L 45

24 LINE1_R SIDESURR_OUT_R 46
3 3
18 CD_L CEN_OUT 43

20 44 R216 1 2 C256 1 2 22P_0402_50V8J

CD_R LFE_OUT @ 22_0402_5% @
19 CD_GND
6 HDA_BITCLK_AUDIO
BIT_CLK HDA_BITCLK_AUDIO <20>
EXT_MIC1 C_MIC
EC_MUTE 12sec
<26> EXT_MIC
C563
2
2.2U_0603_6.3V6K
21 MIC1_L
1 2 22 8 250_SDIN R215 1 2 HDA_SDIN0
MIC1_R SDATA_IN HDA_SDIN0 <20>
C564 2.2U_0603_6.3V6K 33_0402_5%
MONO_IN 12 37
PCBEEP NC
+3VS EAPD R213 1 2 0_0402_5% @ 29
R212 1 NC
<20> HDA_RST_AUDIO# 2 0_0402_5% 11 RESET#
LINE2_VREFO 31
<20> HDA_SYNC_AUDIO 10 SYNC 10mil
1

MIC1_VREFO_L 28 +MIC1_VREFO_L
R214
<20> HDA_SDOUT_AUDIO 5 SDATA_OUT
32
10mil
MIC1_VREFO_R +AUD_VREF
10K_0402_1% 2
@ GPIO GPIO0
3 30 +MIC2_VREFO
2

GPIO R467 GPIO1 MIC2_VREFO

<26> JACK_PLUG_MIC 1 2 20K_0402_1% 13 SENSE A 10mil
34 SENSE B VREF 27 2 1
1

C270 10U_0805_10V4Z
JACK_PLUG 1 2 R232 47 40 2 1
<26> JACK_PLUG EAPD JDREF
@ R217 39.2K_0402_1% R471 20K_0402_1%
1 2 10K_0402_1% 48 33 1 2 +VDDA
R463 0_0603_5% EAPD SPDIFO NC R228 @ 10K_0402_5%
<26,31> EAPD 1 2
2

L37 0_0603_5% 4 26
DVSS1 AVSS1
7 DVSS2 AVSS2 42
1 2
4 R466 0_0603_5% ALC861-VD-GR_LQFP48 4

1 2
R482 0_0603_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

GND GNDA Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ALC861 VD Codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IEL10 LA-3451P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 25 of 46
A B C D E
 A B C D E

+3VS
APA2056 SPK/HP Amplifier +5VAMP
L44 BLM15BB121SN1D_0402
1 2

W=40mil

0.1U_0402_16V4Z

10U_0805_10V4Z
1 1 2
C277 C275 C290

1U_0402_6.3V4Z
2 2 1

1 9/5 ANPEC Suggest 1

R240 @ 1.5K_0402_1%

11

19

20
10
Place 1U cap between pin 1 and 2

1
fo=1/(2*3.14*R*C)=106Hz 1 2 U16
R=1.5K / C= 1uF R253 @ 1.5K_0402_1%

CVDD

HVDD

PVDD
PVDD

VDD
1 2 ME@
1 R247 2 ACES_87213-0400G
<25> LINE_OUTR
0_0402_5% INR_A 3 22 SPKR+ SPKL+ R5 1 2 0_0402_5% SPK_L1+ 4 6
<25> LINE_OUTL 1 R243 2 INL_A 5
INR_A
INL_A
ROUT+
ROUT- 21 SPKR- Speaker SPKL- R4 1 2 0_0402_5% SPK_L1- 3
4 GND
3 GND 5
0_0402_5% SPKR+ R3 1 2 0_0402_5% SPK_R1+ 2
R254 1 AMP_EN#27 SPKL+ SPKR- SPK_R1- 2
2 100K_0402_5% 8 R2 1 2 0_0402_5% 1
/AMP EN LOUT+
LOUT- 9 SPKL- Speaker 1
JP2
R226 1 2 100K_0402_5% HP_EN 24 20mil
+5VAMP
HP_R INR _H
HP EN
HP_R 17 HP_ROUT
HP_LOUT Headphone Speaker Conn.
<25> HP_R 1 2 4 INR_H HP_L 18

@ C4

@ C3

@ C2

@ C1
R491 39K_0402_5% INL_H 6
HP_L INL_H
<25> HP_L 1 2 1 1 1 1
R488 39K_0402_5% 26 15 CVSS
VOL_AMP SET/SD CVSS
VSS 16

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
28 BEEP 2 2 2 2
GND 2
AMP_CP+ 12 23 1
AMP_CP- CP+ PGND C268
1 2 14 CP- PGND 7
C269 1U_0402_6.3V4Z 13
AMP_BIAS CGND 1U_0402_6.3V4Z
25 BIAS
C282 2.2U_0603_6.3V6K 2
GND 29
2 1

1
C288 0.1U_0402_16V4Z
APA2057RI-TRL_TSSOP28 R1
0_0402_5%
IN_A Gain = 10dB (Internal Speaker) @

2
2 2
IN_H Gain = 0dB (Headphone)

+5VAMP
EXT MIC
1

EAPD 2 1 R877
<25,31> EAPD +MIC1_VREFO_L
R234 @ 0_0402_5% 51K_0402_5%

Audio Jack
2

EC_MUTE# 2 1 VOL_AMP
<31> EC_MUTE#
2N7002_SOT23

R233 0_0402_5%
1

1
D
1

120K_0402_5%

EC_MUTE# 2
R505

0.1U_0402_16V4Z

G R465 JACK_PLUG_MIC
<25> JACK_PLUG_MIC
@ Q44 S 3K_0402_5%
3

+AUD_VREF
C612

2
EXT_MIC 1 2 EXT_MIC_L-2
<25> EXT_MIC
2

@ L36 FBM-11-160808-700T_0603

1
C542 JP27
47P_0402_50V8J 1 1 2
2 1 2 PL-OUT
3 3 4 4
C547 EXT_MIC_L-2 5 6 PR-OUT
GNDA 5 6
7 7 8 8
3 2 JACK_PLUG_MIC JACK_PLUG 3
9 9 10 10
GNDA 11 12
@ 11 12
13 G1 G2 14
10P_0402_50V8J 15 16
G3 G4
17 G5 G6 18

ACES_88028-1210M
ME@

JACK_PLUG
<25> JACK_PLUG
R476 47_0402_5% L38 FBM-11-160808-700T_0603
HP_ROUT 1 2 1 2 PR-OUT
R477 47_0402_5%
HP_LOUT 1 2 1 2 PL-OUT
L39 FBM-11-160808-700T_0603
1

R473 R480
+MIC2_VREFO 1K_0402_5% 1K_0402_5%
GNDA
INT MIC
2

GNDA

C546 1 1
1

End or Begain 10P_0402_50V8J C548

R490
3K_0402_5% @ 2 GNDA 2
2

4 MIC1 @ 4
1 INT_MIC 10P_0402_50V8J
INT_MIC <25>
2 GNDA

WM-64PCY_2P 1
45@
C574
47P_0402_50V8J
2 Security Classification Compal Secret Data Compal Electronics, Inc.
GNDA 2006/08/05 2007/08/05 Title
Issued Date Deciphered Date
AMP/VR/Audio Jack/MIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 21, 2007 Sheet 26 of 46
A B C D E
 A B C D E F G H

+5VS
+5VS Placea caps. near ODD CONN.
@ 0.1U_0402_16V4Z 10U_0805_10V4Z
0.1U_0402_16V4Z 10U_0805_10V4Z
1 1 1 1 1
1 1 1 1 1 IDE_DD[0..15] C296 C295 C299 C300 @C302
1 <20> IDE_DD[0..15] 1
C247 C540
IDE_DA[0..2]
<20> IDE_DA[0..2] 2 2 2 2 2
C248 C249 C541
2 2 2 2 2
1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z
1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z

SATA HDD Conn.

JP14
1 GND
<20> SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 2
JP28 SATA_ITX_C_DRX_N0 A+
<20> SATA_ITX_C_DRX_N0 3 A-
1 1 2 2 4 GND
3 4 SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0 5
R314 3 4 <20> SATA_DTX_C_IRX_N0 B-
<21> IDERST_CD# 1 2@ 0_0402_5% 5 5 6 6 IDE_DD8 C312 1000P_0402_50V7K 6 B+
R287 1 2 33_0402_5% IDE_DD7 7 8 IDE_DD9 SATA_DTX_C_IRX_P0 1 2 SATA_DTX_IRX_P0 7
19,21,23,24,29> PLT_RST_BUF# 7 8 <20> SATA_DTX_C_IRX_P0 GND
IDE_DD6 9 10 IDE_DD10 C311 1000P_0402_50V7K
IDE_DD5 9 10 IDE_DD11
11 11 12 12
IDE_DD4 13 14 IDE_DD12 8
13 14 +3VS V33
IDE_DD3 15 16 IDE_DD13 9
IDE_DD2 15 16 IDE_DD14 V33
17 17 18 18 10 V33
IDE_DD1 19 20 IDE_DD15 11
IDE_DD0 19 20 IDE_DDREQ GND
21 21 22 22 IDE_DDREQ <20> 12 GND
23 24 IDE_DIOR# 13
23 24 IDE_DIOR# <20> GND
IDE_DIOW# 25 26 14
<20> IDE_DIOW# 25 26 +5VS V5
IDE_ DIORDY 27 28 IDE_DDACK# 15
<20> IDE_DIORDY 27 28 IDE_DDACK# <20> V5
IDE_IRQ 29 30 16
<20> IDE_IRQ 29 30 V5
IDE_DA1 31 32 IDE_PDIAG# 1 2 R210 +5VS 17
2 IDE_DA0 31 32 IDE_DA2 100K_0402_5% GND 2
33 33 34 34 18 Reserved
<20> IDE_DCS1# IDE_DCS1# 35 36 IDE_DCS3# IDE_DCS3# <20> 19
IDE_LED# 35 36 GND
+5VS 2 1 37 37 38 38 20 V12
R209 100K_0402_5% +5VS 39 40 +5VS 21
39 40 V12
41 41 42 42 22 V12
43 43 44 44
45 45 46 46 SUYIN_127043FB022S338ZR_RV
1 2 IDE_CSEL 47 48
R206 470_0402_5% 47 48 ME@
49 49 50 50

OCTEK_CDR-50DY1G
ME@ (NEW)
(NEW) Change Library
IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or High for Slaver (Normal)

3 3

U12
IDE_LED# 2
1 DRIVE_LED#
SATA_LED# DRIVE_LED# <32>
<20> SATA_LED# 3
4 DAP202U_SOT323-3 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 27 of 46
A B C D E F G H
 5 4 3 2 1

1
1U_0603_16V4Z C526

CARD@
2

D 0_0402_5% R438 D
2 1
CARD@
C531 1 C580 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 2 CARD@
CARD@
2 U25 CARD@
Used 9701 by 10K
1 AV_PLL
R454 3
0_0402_5% A3V3
7 A3V3
SDPW R0_MSPWR 1 2 9 CARD_3V3 C523
CARD@ 11 D3V3
33 D3V3 VREG 10 1 2
CF_DMACK# 22
CARD@ 30
R495 1 CF_CS0# 1U_0603_16V4Z
2 0_0402_5% 8
+5VS
@ R496 1 2 0_0402_5% 1
RST#
MODE SEL
44
45
VBUS
RST#
CARD@ 3 in 1 Card Reader
+5VALW MODE_SEL
C532 XTLI 47 43
0.1U_0402_16V4Z XTLO XTLI XD_CLE/CF_SP19 JP26
48 XTLO XD_CE#/CF_D11_SP18 42
CARD@ 41 +VCC_3IN1 6
2 USB20_N5 XD_ALE/CF_D4_SP17 SD_DATA2 SD_MS_DATA0 VDD_SD
<21> USB20_N5 4 DM SD_DAT2/XD_RE#/CF_D12_SP16 40 9 DAT0_SD
USB20_P5 5 39 SD_DATA3 SD_MS_DATA1 10
<21> USB20_P5 DP SD_DAT3/XD_WE#/CF_D5_SP15 DAT1_SD
2

14 38 SD_DATA2 2
R437 GPIO0 XD_RDY/CF_D13_SP14 SD_DATA3 DAT2_SD
SD_DAT4/XD_WP#/CF_D6_SP13 37 3 CD/DAT3_SD
100K_0402_5% 35 CARD@ SD_MS_CLK R458 1 2 22_0402_5% SDCLK 7
CARD@ SD_DAT5/XD_D0/CF_D14_SP12 R446 1 CLK_SD
SD_CLK/XD_D1/MS_CLK/CF_D7_SP11 34 2 22_0402_5% SD_MS_CLK SDW P# CARD@ 11 WP_SD
31 MS_DATA3_SD_DATA6 SDCMD 4
1

RST# SD_DAT6/XD_D7/MS_D3/CF_D15_SP10 MSCD# S DCD# CMD_SD

MS_INS#/CF_IORD#_SP9 29 1 CD_SD
28 MS_DATA2_SD_DATA7 5
SD_DAT7/XD_D2/MS_D2/CF_IOWR#_SP8 SD_MS_DATA0 VSS_SD
1 SD_DAT0/XD_D6/MS_D0/CF_RST#_SP7 27 8 VSS_SD
C514 26 SD_MS_DATA1
CARD@ SD_DAT1/XD_D3/MS_D1/CF_IORDY_SP6 MSBS
C XD_D5/MS_BS/CF_A2_SP5 25 C
1U_0402_6.3V4Z 23 SD_MS_DATA1 19
2 CF_A1/XD_D4_SP4 S DCD# VCC_MS
CF_A0/SD_CD#_SP3 21 13 VCC_MS
20 SDW P# SD_MS_CLK MSCLK 14
CF_D0/SM_WPM#/XD_WP_SP2 MSCD# SCLK_MS
CF_D1/XD_CD#_SP1 19 16 INS_MS
18 SD_MS_DATA0 18
CF_D8/SM_CD#_SP0 MSBS SDIO_MS
20 BS_MS
2 13 MS_DATA3_SD_DATA6 15
RREF CF_CD# MS_DATA2_SD_DATA7 RESERVED_MS
CF_DMARQ 24 17 RESERVED_MS
12 DGND 21 VSS_MS
32 DGND CF_D10 15 12 VSS_MS
CF_D9 16 22 GND
6 AGND CF_D2 17 23 GND
46 36 SDCMD
AGND SD_CMD PROCO_MDR019-C0-1202
ME@

RTS5158-GR_LQFP48_7x7
2

R447 R433
6.19K_0402_1% 0_0402_5%
CARD@ CARD@
1

R497
1 2
CARD@

1
0_0402_5% R457 R459
40mil
+3VS @ U26 +VCC_3IN1 10_0402_5% 10_0402_5%
MODE SEL XTLI @ @

2
C511 18P_0402_50V8J 3 1
CARD@ SDPW R0_MSPWR VIN VOUT
4 VIN/CE VOUT 5

1U_0603_10V4Z

150K_0402_5%
@ @

1
0.1U_0402_16V4Z
B Y2 2 1 C536 C537 B
GND
1

CARD@ C538

R462
1 CARD@ 10P_0402_50V8J 10P_0402_50V8J
0.1U_0402_16V4Z C513 R436 1 RT9701CB_SOT25
1

@ 10K_0402_5% @
2

C535
CARD@ R501
2

2
2 12MHZ_16P_6X12000012 100K_0402_5%
2

CARD@ 2 @
2

XTLO
C515 18P_0402_50V8J reserved power circuit
CARD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1394+3 in 1 Card
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 28 of 46
5 4 3 2 1
 A B C D E

Layout Notice : 1.2V filter. Place as close

U30 C test change to 3413 chip as possible.
@ L15 Layout Notice : Place as close
Layout Notice : Filter place as close FBM-L11-321611-260-LMT_1206 +1.2V_LAN
chip as possible.
chip as possible. 1 2
+3VALW_VDDIO
U30

4.7U_0805_6.3V6K

0.01U_0402_25V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+2.5V_LAN 8 1
+3VALW D S
7 D S 2 2 2 2 2 2 2 2 2 2
2 1 +XTALVDD 6 D S 3

C456

C502

C503

C506

C481

C461

C460

C476

C457
4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
L35 FBM-L11-160808-601LMT_0603
2 5 4
D G
2 2 2 1 1 1 1 1 1 1 1 1
C488 AO4468_SO8
R174

C468

C505

C486

C507
4 0.1U_0402_16V4Z 4
1
+VSB 1 2
1 1 1

33K_0402_5%
2 1 +LAN_AVDD 1

1
L31 FBM-L11-160808-601LMT_0603 D C132
2 2
EN_WOL 2 0.1U_0603_25V7K
<31> EN_WOL
C450 C449 G
0.1U_0402_16V4Z 0.1U_0402_16V4Z Q11 S 2

3
1 1 2N7002_SOT23 U87

41 LAN_TX0-
close to each of the pins 38, 45, and 52 TRD0_N LAN_TX0- <30>
28 40 LAN_TX0+
<15> CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_TX0+ <30>
2 1 +LAN_BIASVDD 42 LAN_RX1-
TRD1_N LAN_RX1- <30>
L29 FBM-L11-160808-601LMT_0603
1 29 43 LAN_RX1+
<15> CLK_PCIE_LAN PCIE_REFCLK_P TRD1_P LAN_RX1+ <30>
C455 48 LAN_TX2-
TRD2_N LAN_TX2+
<15> CLKREQ_LAN# 11 CLKREQ TRD2_P 47
0.1U_0402_16V4Z (CLKREQ#) and (ENERGY_DET) are 49 LAN_TX3-
2 only supported in BCM5787M TRD3_N LAN_TX3+
1 2 TRD3_P 50
+1.2V_LAN R426 4.7K_0402_5%
3 LOW PWR
2 1 +3VALW_VDDIO Place closed to L14 & K14
+AVDDL
L28 FBM-L11-160808-601LMT_0603
2 2 +3VS 1 2 CBE#1 53 2 R425 1 2 0_0402_5% LINKLED# <30>
R371 1K_0402_5% VMAIN_PRSNT LINKLED
SPD100LED 1 R424 1 2 0_0402_5% C516 1 2 0.1U_0402_16V4Z
C439 C451 +3VALW_VDDIO 1 2 54 67 R420@1 2 0_0402_5%
4.7U_0805_6.3V6K 0.1U_0402_16V4Z R380 1K_0402_5% VAUX_PRSNT SPD1000LED C512 1
TRAFFICLED 66 ACTIVITY# <30> 2 4.7U_0603_6.3V6K
1 1

3
Q33
59 65 LAN_CLK
ENERGY_DET SCLK(EECLK) SI CTL12 MMJT9435T1G_SOT223
2 1 +GPHY_PLLVDD SI 63 1
L27 FBM-L11-160808-601LMT_0603
2 2 35 64 LAN_DATA
+GPHY_PLLVDD GPHY_PLLVDD SO(EEDATA) +1.2V_LAN
62 CS#
3 C443 C452 CS 3
<21> PCIE_ITX_C_PRX_N3 32

2
4
4.7U_0805_6.3V6K 0.1U_0402_16V4Z PCIE_RXD_N
1 1
<21> PCIE_ITX_C_PRX_P3 31 PCIE_RXD_P 1 1
14 CTL12 C510 C509
PCIE_MRX_C_LTX_N3 REGCTL12
<21> PCIE_PTX_C_IRX_N3 25 PCIE_TXD_N REGCTL25 18 CTL25
2 1 +PCIE_PLLVDD 0.1U_0402_10V7K C484 37 2 1 0.1U_0402_16V4Z 10U_0805_10V4Z
L33 FBM-L11-160808-601LMT_0603 PCIE_MRX_C_LTX_P3 RDAC R357 1K_0402_1% 2REG_GND 2
2 2 <21> PCIE_PTX_C_IRX_P3 26 PCIE_TXD_P
0.1U_0402_10V7K C478
C470
C459 0.1U_0402_16V4Z 23 +XTALVDD
4.7U_0805_6.3V6K 1 1 XTALVDD
<7,16,19,21,23,24,27> PLT_RST_BUF# 10 PERST VDDIO 6 +3VALW_VDDIO
15 +3VALW_VDDIO
VDDIO
<21,23,24> ICH_PCIE_WAKE# 1 2 12 WAKE VDDIO 19
2 1 +PCIE_VDD @ R427 0_0402_5% 56 1 2
L30 FBM-L11-160808-601LMT_0603 VDDIO C508
1 2 <31> LAN_WAKE# 1 2 VDDIO 61
R431 0_0402_5% 0.1U_0402_16V4Z
C453 C475 <15,21,24> ICH_SMBCLK 1 2 58 17
SMB_CLK VDDP +2.5V_LAN
4.7U_0805_6.3V6K 0.1U_0402_16V4Z @ R394 0_0402_5%
2 1
1 2 57
VDDP 68 4.7uF
<15,21,24> ICH_SMBDATA SMB_DATA
@ R383 0_0402_5% 5 +1.2V_LAN
VDDC

4
PCIE_GND SMBus to support ASF 13 Q31
VDDC MBT35200MT1G_TSOP6
VDDC 20
1 2 4 GPIO_0(SERIAL_DO) VDDC 34
@ R502 0_0402_5% 55 CTL25 3
LAN_WP VDDC
7 GPIO_1(SERIAL_DI) VDDC 60
No CIS Symbol
8 36 +LAN_BIASVDD

1
2
5
6
XTALO GPIO_2 BIASVDD
2 1 PCIE_PLLVDD 30 +PCIE_PLLVDD
R422 200_0603_1% 9 27 +PCIE_VDD
XTALI UART_MODE PCIE_VDD
Y1 PCIE_VDD 33
27P_0402_50V8J

27P_0402_50V8J

1 2 AVDD 38 +LAN_AVDD
2 XTALI 2
21 XTALI AVDD 45
2 2 AVDD 52
C495

C501

25MHZ_20P XTALO 22 XTALO

AVDDL 39 +AVDDL +2.5V_LAN
AVDDL 44
1 1 REG_GND
Pin16 conect to C1206 Pin1 16 REG_GND AVDDL 46
51 Notice : 4.7u 6.3V capactor Thickness 1.25mm

GND
PCIE_GND AVDDL
24 PCIE_GND
Layout Notice : Filter place as close

69
chip as possible.
Pin 24 conect to C1339 Pin1
Layout Notice : Place as close
chip as possible.
+3VALW_VDDIO
+2.5V_LAN
1 2
1

C116

2200P_0402_25V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
R165 R166 2 1 2 2

C504

C496
C498
4.7K_0402_5% 4.7K_0402_5%

C613
2

U7
1 2 1 1
8 VCC A0 1
LAN_WP 7 2
LAN_CLK WP A1
6 SCL NC 3
LAN_DATA 5 4
SDA GND
AT24C02_SO8
1 1

Close to U87
LAN_CLK 1 2
R419 4.7K_0402_5%
SI 2 1
@ R416 4.7K_0402_5%
CS# 1 2
@ R409 4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BCM5787M-GLAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IEL20 LA-3471P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 29 of 46
A B C D E
 5 4 3 2 1

+2.5V_LAN

1
D
R331
0_0402_5% T24
@ C615
68P_0402_50V8K
Lan Conn. D
2 1
LAN_RX1+ 1 16 MDO1+
<29> LAN_RX1+

2
LAN_RX1- RD+ RX+ MDO1- JP21
<29> LAN_RX1- 2 RD- RX- 15
C413 1 2 0.1U_0402_16V4Z TCT 3 14 MCT0 2 1 R175 ACTIVITY# 12
CT CT <29> ACTIVITY# Amber LED-
4 13 75_0402_5%
NC NC
5 NC NC 12 +3VALW_VDDIO 1 2 11 Amber LED+ SHLD4 16
C428 1 2 0.1U_0402_16V4Z TCT 6 11 MCT1 2 1 R178 @ R866 300_0402_5%
LAN_TX0+ CT CT MDO0+ 75_0402_5% MDO3-
<29> LAN_TX0+ 7 TD+ TX+ 10 10mil 8 PR4- SHLD3 15
LAN_TX0- 8 9 MDO0- 1 2
<29> LAN_TX0- TD- TX- +3VS R867 300_0402_5% MDO3+ 7 PR4+
350uH_NS0013LF MDO1- 6
@ C6161 PR2-
2 220P_0402_50V7K
Change T1 from SP050001210 to SP050001210 MDO2- 5 PR3-
MDO2+ 4 PR3+
MDO1+ 3
@ C617 PR2+
Change C468,C470,C473,C474,C475,C476 from 0.01uF to 0.1uF 68P_0402_50V8K MDO0- 2 PR1-
2 1 SHLD2 14
MDO0+ 1 PR1+
LINKLED# 10mil 10 13
<29> LINKLED# Green LED- SHLD1
LAN_RX1- 2 1 C446 1 2 9
R373 49.9_0402_1% +3VALW_VDDIO Green LED+
1 2 0.1U_0402_16V4Z @ R868 300_0402_5%
LAN_RX1+ 2 1 TYCO_2-1734819-5
R372 49.9_0402_1% 1 2 ME@
+3VS R170 300_0402_5%

C C
@ C6181 2 220P_0402_50V7K

LAN_TX0- 2 1 C447
R374 49.9_0402_1% 1 2 0.1U_0402_16V4Z
LAN_TX0+ 2 1
R375 49.9_0402_1%

C151
RJ45_PR 1 2 LANGND

near LAN controller 1000P_1206_2KV7K

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONTROLLER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3691P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 30 of 46
5 4 3 2 1
 +3VALW
+EC_AVCC
L8 1 1 1 1 1 1 +5VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
C23

C22

C21

C25

C40

C48
+3VALW 1 2 +EC_AVCC
FBM-11-160808-601-T_0603 2 +5VALW
1

1
C46 1 @ 2 USB_ON C59
C44 2 2 2 2 2 2
0.1U_0402_16V4Z R506 10K_0402_5% 1 2 0.1U_0402_16V4Z R65

111
125
1000P_0402_50V7K 100K_0402_1%

22
33
96

67
U1

9
1 ECAGND 2 +3VALW
1 2
L7 FBM-11-160808-601-T_0603 U4

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

2
8 VCC A0 1

2
7 WP A1 2
R872 1 2 10K_0402_5% R45 EC_SMB_CK1 6 3
+3VS SCL A2
1 21 INVT_PWM 100K_0402_1% EC_SMB_DA1 5 4
<20> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <17> SDA GND
2 23 BEEP#
<20> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <25>
3 26 AT24C16AN-10SU-2.7_SO8
<21> SERIRQ EN_WOL <29>

1
SERIRQ# FANPWM1/GPIO12 ACOFF
<20> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <38,40>
LPC_AD3 5 UMA_DES R42
<20> LPC_AD3 LAD3

1
LPC_AD2 7 PWM Output
<20> LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP R63
<20> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <39>

2
C35 LPC_AD0 BATT_OVP 100K_0402_1%
<20> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP <40>
R42
2 1 2 1 ADP_I/AD2/GPIO3A 65 ADP_I <40>

8.2K_0402_5%
PM@
R38 @ 10_0402_5% 12 AD Input 66 BRD_ID
<15> CLK_PCI_LPC

2
@ 22P_0402_50V8J PCICLK AD3/GPIO3B SKU_ID
<19> PCI_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 200K_0402_5%
1 2 EC_RST# 37 76 UMA_DES GM@
+3VALW

1
R59 47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43
<21> EC_SCI# 20 SCI#/GPIO0E
2 38 CLKRUN#/GPIO1D Analog Board ID definition,
C57 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG <17> Please see page 3.
70 EN_FAN1 +3VALW
EN_DFAN1/DA1/GPIO3D EN_FAN1 <4>
0.1U_0402_16V4Z DA Output 71 IR EF
1 IREF/DA2/GPIO3E IREF <40>
KSI0 55 72
KSI1 KSI0/GPIO30 DA3/GPIO3F EC_MUTE# +3VALW +3VALW
56 KSI1/GPIO31 1 2
KSI2 57 R40 @ 10K_0402_5%
KSI3 KSI2/GPIO32
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <26>

2
KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_ON <35>
KSI5 60 85 @ R50 R57
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C 100K_0402_1% 100K_0402_1%
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
KSO[0..15] KSI7 62 87 TP_CLK
<33> KSO[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <33>
KSO0 39 88 TP_DATA
TP_DATA <33>

1
KSI[0..7] KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F
<32,33> KSI[0..7]
40 KSO1/GPIO21 KB925 SPI STRAP PIN
KSO2 41 SKU_ID BRD_ID
KSO3 KSO2/GPIO22 R26
42 KSO3/GPIO23 SDICS#/GPXOA00 97 1 2 4.7K_0402_5%

2
KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 BT_OFF# <23>
KSO5 R51 R54
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99

56K_0402_5%

33K_0402_5%
KSO6 45 109 2 1
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 R23 10K_0402_5%
+3VALW
@
46 KSO7/GPIO27 SPI Device Interface
KSO8 47

1
KSO9 KSO8/GPIO28 FRD#SPI_SO
48 KSO9/GPIO29 SPIDI/RD# 119
KSO10 49 120 FWR#SPI_SI
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK
50 SPI Flash ROM SPICLK/GPIO58 126 UMA_DES Vab
KSO12 51
KSO11/GPIO2B
KSO12/GPIO2C SPICS# 128 FSEL#SPICS# ID
KSO13 52 0 IHL00/IGT30 UMA 3.30V
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73 2 1 1 IHLV3 UMA 2.20V
<32> KSO16
KSO16 81
KSO15/GPIO2F
KSO16/GPIO48
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41 74 R52 10K_0402_5%
+3VALW
ID BRD ID R54/42(Rb) Vab
+3VALW
<32> KSO17 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89
CHARGE_LED0#
FSTCHG <40> 2
BATT_CHGI_LED#/GPIO52 90 CHARGE_LED0# <34> I I 0 R01 (EVT) 0 0V
91 CAPS_LED# 3 H H
CAPS_LED#/GPIO53 CAPS_LED# <32>
EC_SMB_CK1 GPIO BATT_LOW_LED#/GPIO54 CHARGE_LED1# L L 1 R02 (DVT)
<39> EC_SMB_CK1
EC_SMB_DA1
77 SCL1/GPIO44 92 CHARGE_LED1# <34>
0 V
8.2K 0.25V
<39> EC_SMB_DA1
EC_SMB_CK2
78 SDA1/GPIO45 SUSP_LED#/GPIO55 93
SYSON
NOVO# <32> 4
<4> EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON <24,36,42> 0 2 2 R03 (PVT) 18K 0.50V
2

EC_SMB_DA2 80 121 5 /
<4> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <44>
R47 3 3 R10A (MP)
10K_0402_5% AC_IN/GPIO59 127 ACIN <21,38>
0.25V
33K 0.82V
6 IHLV2 VGA
I 4 R01 (EVT) 56K 1.19V
PM_SLP_S3# 6 100 7 IHL00/IGT30 VGA 0V G
<21> PM_SLP_S3# EC_RSMRST# <21>
1

PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT#

<21> PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# <21> T 5 R02 (DVT) 100K 1.65V
EC_SMI# 15 102 EC_ON 3
<29> LAN_WAKE# <21> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <32>
LID_SW# RB751V_SOD323 0 6 R03 (PVT)
<32> LID_SW#
SUSP#
16
17
LID_SW#/GPIO0A EC_SWI#/GPXO06 103
104 ICH_POK_EC 1 D5 2 ICH_POK
200K 2.20V
<16,24,36,40,42,43> SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_POK <7,21>
PBTN_OUT# GPO BKOFF# 7 R10A (MP)
1 2
<21> PBTN_OUT# 18
19
PBTN_OUT#/GPIO0C
GPIO
BKOFF#/GPXO08 105
106
BKOFF# <17>
1 2 1 2
NC 3.30V
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <23> +3VS
@ R507 0_0402_5% EC_THERM# R16 0_0402_5% R22 10K_0402_5%
<4,21> EC_THERM#
FAN_SPEED1
25
28
EC_THERM#/GPIO11 GPXO10 107
108 @
R57/45(Ra)=100K Ohm
<4> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 SCROLL_LED# <32>
S

<19> PCI_PME# 3 1 29 FANFB2/GPIO15

EC_TX_P80_DATA 30
<13,14,33> EC_TX_P80_DATA EC_TX/GPIO16
Q1 EC_RX_P80_CLK 31 110 PM_SLP_S4# <21>
<13,14,33> EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1
G

2N7002_SOT23 <32> ON/OFF# 32 112 ENBKL <17>

2

+3V_STB ON_OFF/GPIO18 ENBKL/GPXID2

@ <34> PWR_LED# 34 PWR_LED#/GPIO19 GPXID3 114 EAPD <25,26>
<32> NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 KILL_SW# <35>
GPXID5 116 2 1 +3VALW
117 R21 10K_0402_5%
GPXID6 STB <36>
GPXID7 118
XCLKI 122
XCLKO XCLK1 +3VALW
123 124
XCLK0 V18R
2 8M SPI ROM
AGND

@ C609 1 20mils
GND
GND
GND
GND
GND

1U_0402_6.3V4Z C293 U18

8 VCC VSS 4
KB926QFA1_LQFP128 1 0.1U_0402_16V4Z
11
24
35
94
113

69

2
3 W
ECAGND

7 HOLD
FSEL#SPICS# 2 1 SPI_CS# 1
R259 0_0402_5% S
+5VALW SPI_CLK 2 1 SPI_CLK_R 6
R19 15_0402_5% C
EC_SMB_CK1 C19 +5VS FWR#SPI_SI 2 SPI_SI SPI_SO 2
1 2 1 5 D Q 2 1 FRD#SPI_SO
R48 4.7K_0402_5% C20 R257 0_0402_5% R260 0_0402_5%
1

15P_0402_50V8J

1 2 EC_SMB_DA1 TP_CLK 1 2 SST25LF080A_SO8-200mil

15P_0402_50V8J

R44 4.7K_0402_5% X1 R36 4.7K_0402_5%

IN

OUT

TP_DATA 1 2
R34 4.7K_0402_5% JP11
SPI_CS# 1 2 +3VALW
SPI_SO 1 2
NC

NC

3 3 4 4
+3VALW 5 6 SPI_CLK_R
5 6 SPI_SI
7 8
2

32.768K_1TJS125BJ4A421P 7 8
E&T_2941-G08N-00E~D
ME@
C610
+3VS 2 1 2 1 SPI_CLK_R
R876 15_0402_5%
1 2 EC_SMB_CK2 @
R49 4.7K_0402_5% 10P_0402_25V8K
1 2 EC_SMB_DA2 @
R43 4.7K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 31 of 46
 JP4
SW1 ACES_88716-1601-01
@ ME@

GND
GND
1 3

10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
2 4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
+3VALW
SMT1-05_4P

6
5
+5VALW
ON/OFF switch TOP Side Switch Board Conn.

2
2 1
J1 @ JOPEN R255 +5VS
2 1 +5VALW 1 2
J3 @ JOPEN 100K_0402_5% R11 @ 0_0402_5%
Bottom Side +3VALW 1 2

1
D12 R10 @ 0_0402_5% DRIVE_LED#
<27> DRIVE_LED#
2 ON/OFF# CAPS_LED#
ON/OFF# <31> <31> CAPS_LED#
ON/OFFBTN# 1 NUM_LED#
<31> NUM_LED#
3 51_ON# SCROLL_LED#
51_ON# <38> <31> SCROLL_LED#
ON/OFFBTN#
DAN202U_SC70

1
Power Button C291
2
D13
KSI0 KSO16 KSI2 KSO17
<31> KSO16
<31,33> KSI0
1000P_0402_50V7K RLZ20A_LL34
1
<31> KSO17

3
D22 D23

PSOT24C_SOT23 PSOT24C_SOT23
<31,33> KSI2

1
D
EC_ON 2 Q27 NOVO_BTN#
<31> EC_ON

1
G
2

R258 3
S 2N7002_SOT23 MUTE# KSI 0 & KSO16
+3VALW
USER# KSI 2 & KSO17
10K_0402_5%
1

ON/OFFBTN#

2
NOVO_BTN#
R15

3
D24 100K_0402_5%

1
PSOT24C_SOT23 D4
NOVO# 2
<31> NOVO#
1 NOVO_BTN#

1
51_ON# 3
<38> 51_ON#
DAN202U_SC70

LID Switch

+3VALW
+3VALW 1 2
R241 0_0402_5%
2

1
2

R244 R221
47K_0402_5% 100K_0402_5%
VDD

1 3 D14 1 2
OUTPUT LID_SW# <31>
C289
10P_0402_50V8J

0.1U_0402_16V4Z 1 CH751H-40_SC76
GND

2 C276
U14
1

A3212ELHLT-T_SOT23W-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 32 of 46
 5 4 3 2 1

D
INT_KBD Conn. D
KSI[0..7]
KSI[0..7] <31,32>
KSO[0..15]
KSO[0..15] <31>

For IHL00 To TP/B Conn.

ME@
ACES_85202-24051
KSI0 C65 1 2 @ 100P_0402_50V8J KSO4 C66 1 2 @ 100P_0402_50V8J KSI1 1
KSI7 1
2 2
KSI1 C73 1 2 @ 100P_0402_50V8J KSO5 C64 1 2 @ 100P_0402_50V8J KSI6 3 JP8
KSO9 3
4 4 +5VS 1 1
KSI2 C63 1 2 @ 100P_0402_50V8J KSO6 C82 1 2 @ 100P_0402_50V8J KSI4 5 2
KSI5 5 TP_DATA 2
6 6 <31> TP_DATA 3 3
KSI3 C78 1 2 @ 100P_0402_50V8J KSO7 C81 1 2 @ 100P_0402_50V8J KSO0 7 TP_CLK 4
7 <31> TP_CLK 4
KSI2 8 5
KSI4 C76 8 5
1 2 @ 100P_0402_50V8J KSO8 C67 1 2 @ 100P_0402_50V8J KSI3 9 9 6 6
KSO5 10 7
KSI5 C62 10 7
1 2 @ 100P_0402_50V8J KSO9 C61 1 2 @ 100P_0402_50V8J KSO1 11 11 8 8
KSI0 12
KSI6 C75 12
1 2 @ 100P_0402_50V8J KSO10 C85 1 2 @ 100P_0402_50V8J KSO2 13 13
ACES_87151-0807G
KSO4 14 ME@
KSI7 C74 14
1 2 @ 100P_0402_50V8J KSO11 C70 1 2 @ 100P_0402_50V8J KSO7 15 15
TP_DATA
KSO8 16
KSO0 C77 16
1 2 @ 100P_0402_50V8J KSO12 C83 1 2 @ 100P_0402_50V8J KSO6 17 17
TP_CLK
KSO3 18 +5VS
18

3
C KSO1 C79 1 2 @ 100P_0402_50V8J KSO13 C69 1 2 @ 100P_0402_50V8J KSO12 19 C
KSO13 19
20 20
KSO2 C80 1 2 @ 100P_0402_50V8J KSO14 C84 1 2 @ 100P_0402_50V8J KSO14 21 C117 D10
KSO11 21 @
22 22
KSO3 C68 1 2 @ 100P_0402_50V8J KSO15 C86 1 2 @ 100P_0402_50V8J KSO10 23 0.1U_0402_16V4Z PSOT24C_SOT23
KSO15 23
24

1
24
25 G1
26 G2
JP7
Update Footprint

B B
EC DEBUG PORT
JP12
+3VALW 1 1
EC_TX_P80_DATA 2
<13,14,31> EC_TX_P80_DATA 2
EC_RX_P80_CLK 3
<13,14,31> EC_RX_P80_CLK 3
4 4
ACES_85205-0400
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB910L(Reserved)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 33 of 46
5 4 3 2 1
 LED
R249
300_0402_5%
+5VALW 1 2 2 1 PWR_LED# <31>
LED3
HT-191NB5-DT_BLUE_0603

R248 Amber
+3VALW 1 2 4 A 3 CHARGE_LED1# <31>
300_0402_5%
R250 Blue
+5VALW 1 2 2 B 1 CHARGE_LED0# <31>
300_0402_5%
LED1
HT-297UD/CB _BLUE/AMB_0603

Blue&Amber

LED@
R252 BT@ Amber
+3VS 1 2 4 A 3 BT_LED# <23>
300_0402_5%
R251 Blue
+5VS 1 2 2 B 1 WLAN_BLUE_LED# <23>
300_0402_5%
WLAN@
LED2
HT-297UD/CB _BLUE/AMB_0603

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/CIR & LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 34 of 46
 A B C D E

USB Conn.
W=80mils
+USB_VCCC
ME@
ACES_87213-1000G
Kill SWITCH GND2 12
GND1 11
1 +3VALW 1

10 10
9 USB20_P4
9 USB20_P4 <21>
8 USB20_N4
8 USB20_N4 <21>

2
@ D2 7
DAN217_SC59 +3VS 7 USB20_P7
6 6 USB20_P7 <21>
+USB_VCCC +USB_VCCC 5 USB20_N7
5 USB20_N7 <21>

2
4 4
+USB_VCCC R7 3 KILL_SW#
3
1 2

1
2
1 1+USB_VCCC 100K_0402_5%
1 1
+ C497 C499 C18

1
150U_Y_6.3VM @ @ KILL_SW# JP5
KILL_SW# <31>
470P_0402_50V7K 470P_0402_50V7K W=80mils
2 2 2

2 +5VALW
U17
+USB_VCCC
USB CONN. 1 2

1 GND OUT 8
2 IN OUT 7
3 6 +USB_VCCA
IN OUT @ D17
C301
1 4 EN# FLG 5 USB_OC#4 <21>
USB20_P0 USB20_N6 +USB_VCCA
W=80mils
6 CH3 CH2 3
G545C1P1U_SO8 1
4.7U_0805_10V4Z 1
2 USB_OC#7 <21> + C462 C473
1 +USB_VCCA 5 Vp Vn 2
C294 220U_V_6.3VM_R25 470P_0402_50V7K
2 2
<31> USB_ON
0.1U_0402_16V4Z JP22
2 @ USB20_P6 USB20_N0
4 CH4 CH1 1 1 VCC
USB20_N0 2
<21> USB20_N0 D-
USB20_P0 3
CM1293-04SO_SOT23-6 <21> USB20_P0 D+
4 GND
5 GND1
6 GND2
7 GND3
8 GND4
SUYIN_020173MR004G579ZR
ME@

3 3

+5VALW
USB CONN. 2
+USB_VCCA

+USB_VCCA
U24
W=80mils
1 GND OUT 8
C527 0.1U_0402_16V4Z 2 7 1
IN OUT C528
2 1 3 IN OUT 6
<31> USB_ON USB_ON 4 5
EN# FLG USB_OC#6 <21>
470P_0402_50V7K
G545C1P1U_SO8 2
USB_OC#0 <21>
JP24
1 1 VCC
C500 USB20_N6 2
<21> USB20_N6 D-
@ 1000P_0402_50V7K USB20_P6 3
<21> USB20_P6 D+
4 GND
2
5 GND1
6 GND2
7 GND3
8 GND4
SUYIN_020173MR004G579ZR
ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 35 of 46
A B C D E
 A B C D E

1 +5VALW TO +5VS 1
+3VALW TO +3VS +1.8V to +1.8VS
+5VALW +5VS
+3VALW +3VS +1.8V +1.8VS
U28
8 1 U10 U9
D S
7 D S 2 8 D S 1 8 D S 1

2
6 D S 3 1 1 7 D S 2 7 D S 2 1 1

2
1 1 5 4 C575 C579 R484 6 3 1 1 6 3 C184 C185
C577 C571 D G D S C229 C226 R203 D S R193
1 1 5 D G 4 1 1 5 D G 4
AO4468_SO8 10U_0805_10V4Z 470_0603_5% C227 C215 C190 C191 10U_0805_10V4Z PM@
10U_0805_10V4Z 2 2
1U_0603_10V4Z AO4468_SO8 10U_0805_10V4Z 470_0603_5% AO4468_SO8 PM@ 2 2
1U_0603_10V4Z 470_0603_5%

1
2 2
10U_0805_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z PM@ PM@

1 1

1
2 2
10U_0805_10V4Z PM@ 2 2
10U_0805_10V4Z

1
D D PM@

1
D
2 SUSP 2 SUSP
G G 2 SUSP
+VSB 1 2 5VS_GATE S Q38 S Q19 G

3
R483 2N7002_SOT23 +VSB 1 2 2N7002_SOT23 +VSB 1.8VS_GATE S Q17

3
20K_0402_5% 1 R202 R192 2N7002_SOT23
1

D C568 47K_0402_5% 180K_0402_5% PM@

1 1

1
SUSP D C209 PM@ C189
2

1
Q37G 0.1U_0603_25V7K SUSP D
2
2N7002_SOT23 2 Q18 G 0.1U_0603_25V7K SUSP 0.1U_0603_25V7K
S 2
3

2N7002_SOT23 S 2 G 2 PM@

3
Q15 S

3
2N7002_SOT23
PM@

+5VALW
2 2

2
+3VALW to +3V Transfer R225
100K_0402_5%
+3VALW +3V_STB
@ J4

1
PAD-OPEN 3x3m
1 2

SYSON#

@ U27
8 1 10U_0805_10V4Z
D S
1 7 D S 2 1 1

1
C539 6 3 C545 C543
D S @ Q23
5 D G 4
10U_0805_10V4Z 0.1U_0402_16V4Z
@ 2 AO4468_SO8 2 2 @
SYSON 2
<24,31,42> SYSON

1
Q35 DTC124EK_SC59
2N7002KW_SOT323-3 @ R224
D

1 3

3
+VSB 100K_0402_5%
G
2

2
1

R464 @
33K_0402_5%
@
2

3 RTCVREF 3
+5VALW
1
1

D C544

2
STB 2 Q36 0.1U_0603_25V7K
<31> STB
G BSS138LT1G_SOT23-3 @ R508 R223
S 2 10K_0402_5% 100K_0402_5%
@
3

1
SUSP
<43> SUSP

1
Q22

<16,24,31,40,42,43> SUSP# 2

1
+1.5VS +2.5VS +VCCP +0.9VS +1.8V DTC124EK_SC59
@ R222

3
100K_0402_5%
2

R235 R137 R262 R211 R191

2
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
1

1
1

D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G
4 S Q25 S Q10 S Q28 S Q20 S Q16 4
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 36 of 46
A B C D E
 FM1 FM3 FM2 FM4 FM6 FM5
H2 H3 H4 H10 H14 H25 H26 H27 H17
H H H H H H H H H

1
CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8
1

1
@ H5 @ @
H6 @ @
H12 @ @
H13 @ @
H H H H
1

1
@

H8 H9 @
H15 H18 @
H20 H23 @
H19 H21 H22
H H H H H H H H H
1

1
@
H28 @
H11 @ @
H16 @ @ @
H7 @ @
H24
H H H H H
1

1
@ @ @ @ @
H1
H H29
H
1

@
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-3691P
Date: Friday, May 18, 2007 Sheet 37 of 46
 A B C D

ACIN BATT ONLY

DC030005Q00 Precharge detector Precharge detector
PL11 VIN Min. typ. Max. Min. typ. Max.
PJP1 ADPIN FBMA-L11-322513-201LMA40T_1210
H-->L 14.589V 14.84V 15.243V H-->L 6.138V 6.214V 6.359V

10_1206_5%
1 1 1 2
L-->H 15.562V 15.97V 16.388V L-->H 7.196V 7.349V 7.505V

1
2 2

PR1
100P_0402_50V8J
1000P_0402_50V7K
3 3

100P_0402_50V8J

1000P_0402_50V7K
1

1
1 4 PR2 1

1 2
4

PC1

PC2

PC3

PC4
1K_1206_5%

RLZ24B_LL34
1 2

PD1
JST_B4B-EH-A(LF)(SN)
PR3
PD2 1K_1206_5% PQ1

2
VIN 2 1 1 2 3 TP0610K-T1-E3_SOT23-3
1

LL4148_LL34-2 PR5
PR4 PC5 1K_1206_5%
@10K_0402_1% @ 0.01U_0402_25V7K 1 2

100K_0402_5%

100K_0402_5%
1 2 1 2

1
VS PR7

PR8

PR9
PR6 1K_1206_5%

2
VIN 1M_0402_1% 1 2
1 2

10K_0402_1%

2
1
84.5K_0402_1%
1

VS

PR11
PR10

PR12
10K_0402_1%

100K_0402_5%
1 2

2
ACIN <21,31>

1
PR13
2

PR14
22K_0402_1%

1
1 2 3
P

+ PACIN PQ2
O 1 PACIN <40>
1000P_0402_50V7K

20K_0402_1%

2 DTC115EUA_SC70-3

1 2
-
1

G
0.1U_0402_16V7K

10K_0402_1%
PU1A
1

1
PR15

2 LM393DG_SO8 PD3 2 2
4

<31,40> ACOFF
PC6

PC7

PR16
PQ3
Vin Detector DTC115EUA_SC70-3
2

GLZ4.3B_LL34-2
B+
2

PR17 2

3
10K_0402_1%
2 1
High 18.764 17.901 17.063
RTCVREF
3.3V Low 17.745 16.9 16.03

3
VIN
PR18
VL 2.2M_0402_5%

2
2 1

PD4
LL4148_LL34-2

499K_0402_1%
1

1
PD5

PR19
2 1 VS
3.3V BATT+

1
68_1206_5%

68_1206_5%

100K_0402_1%
1
RTCVREF

PR20

PR21
RB751V-40_SOD323-2
VS

PR22
G920AT24U_SOT89-3

2
PR24 PU2 PR25 2

2
PR23 560_0603_5% 200_0805_5%

8
560_0603_5%
1 2 1 2 3 2 2 1 CHGRTCP 3 1 PD6
OUT IN
0.22U_1206_25V7K

<39,41> MAINPWON 2 5

P
3 3
+
1

PC9
4.7U_0805_6.3V6K

0.1U_0603_25V7K
1U_0805_25V4Z

+CHGRTC 1 7 O
1

GND
PC8

0.01U_0402_25V7K
100K_0402_5%

191K_0402_1%

499K_0402_1%
<40> ACON 3 - 6
1

1
PR26

PC10

PC11

0.1U_0603_25V7K
PU1B
2

1
1

PR27

PR28

PC14
1000P_0402_50V7K
BAS40CW_SOT323-3 LM393DG_SO8
2

4
1

1
PC12
2

PC13
PR29
2

2
22K_0402_1%

PRG++ 2

2
<32> 51_ON# 1 2

PQ4
TP0610K-T1-E3_SOT23-3
2N7002W-T/R7_SOT323-3
PR30 PR31

1
PJ2 34K_0402_1% PQ5 D 47K_0402_1%
PAD-OPEN 3x3m PJ3 PAD-OPEN 3x3m
2 1 2 2 1
+1.5VSP 1 2 +1.5VS 1 2 +1.8V
RTCVREF G PACIN <40>
+1.8VP

1
S

3
66.5K_0402_1%
PQ6

1
(7A,280mils ,Via NO.=14) (8A,320mils ,Via NO.= 16) DTC115EUA_SC70-3

PR32
PJ5 PJ6 2 +5VALWP
PAD-OPEN 3x3m PAD-OPEN 3x3m @
+5VALWP 1 2 +5VALW +0.9VSP 1 2 +0.9VS

3
(6A,240mils ,Via NO.= 12) (2A,80mils ,Via NO.= 4)
4 PJ7 4
PJ8
PAD-OPEN 3x3m
+3VALWP 1 2 +3VALW +2.5VSP 1 1 2 2 +2.5VS
JUMP_43X79
(6A,240mils ,Via NO.=12) (1A,40mils ,Via NO.= 2)
PJ4 PJ10 Security Classification Compal Secret Data Compal Electronics, Inc.
PAD-OPEN 3x3m PAD-OPEN 3x3m 2005/10/17 2006/10/17 Title
Issued Date Deciphered Date
1 2 1 2
+VCCPP +VCCP +VSBP +VSB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
(16A,800mils ,Via NO.= 24) (0.3A,40mils ,Via NO.= 2) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 38 of 46
A B C D
 A B C D

BATT++ PL12
DC040003600 HCB4532KF-800T90_1812
1 2 BATT+

PJP2
PH1 under CPU botten side :
BATT++
1 1
2
1 2 +3VALWP CPU thermal protection at 85 degree C
2

1000P_0603_50V7K

1000P_0603_50V7K
ID PR34 PR33
3 3 Recovery at 70 degree C

0.01U_0603_50V7K
4 B /I 1 2 100K_0402_5%
4 +3VALWP

1
5 SMC VS
5

1
PC15

PC16

PC17
6 SMD @ 100K_0402_5%
6 TS
7

2
7

2
VL

0.1U_0603_25V7K
1K_0402_5%
1 8 GND 1

2
8

2
VL

PR36
9 9

PC18
G1 10

150K_0402_1%
G2 11 PR35

2
10.5K_0402_1%
1K_0402_1%

2
1

PR38
SUYIN_200275MR009G180ZR

PR37
PR39
1 442K_0603_1%
2

1
ALI/MH# <40>

2
100_0402_1%
PR42

8
100_0402_1%
69.8K_0603_1%

PR40

PR41
1 2 3

P
+
O 1
TM_REF1 2 MAINPWON <38,41>
-

G
100K_0603_1%_TH11-4H104FT
PU3A
2

1
LM393DG_SO8

4
PH1
1000P_0402_50V7K
EC_SMB_CK1 <31>

1U_0603_6.3V6M
2
1

PC19
EC_SMB_DA1 <31>

PC20
PR43
2 150K_0402_1%
1 VL

2
1 2 +3VALWP

150K_0402_1%
PR44

1
1K_0402_1%

6.49K_0402_1% VS
1

PR46
2 2
PR45

8
2

BATT_TEMP <31> 5

P
+
O 7
6 -

G
PU3B
LM393DG_SO8

4
PJ20
1 1 2 2

JUMP_43X79
PQ7
TP0610K-T1-E3_SOT23-3
3 3

B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K
1

100K_0402_5%

1
PR47

PC21

PC22
2

PR48
2

22K_0402_1%
VL 1 2
100K_0402_5%
2
PR49

PR50
1

@ 0_0402_5% PQ8 D

<41> SPOK 1 2 2
G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC23
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IHL00 LA-3691P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 39 of 46
A B C D
 A B C D

65W, Iadapter=0~3.42A, Current sense=0.02ohm, PR69=39.2K, CP=3.079A ADP_I = 19.9*Iadapter*Rsense

90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR69=28.7K, CP=4.263A
B+

PQ9 P2 PQ10 P3 CHG_B+ PQ11

AO4407_SO8 AO4407_SO8 PJ12
AO4407_SO8
VIN 8 1 1 8 1 4 1 1 2 2 1 8
7 2 2 7 2 7

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M

0.1U_0603_25V7K
6 3 3 6 CSIP 2 3CS IN JUMP_43X118 3 6
5 5 5

1
PC24

PC25
1
PR51 1

PC26

PC27
0.02_2512_1%

4
PR54

2
47K_0402_1%
1

5600P_0402_25V7K
PQ42 1 2
TP0610K-T1-E3_SOT23-3 VIN

0.1U_0603_25V7K
PR52

2
47K_0402_1% PR53

PC28

PC29
200K_0402_1% VIN 3 1 6251DC_IN PQ43 PR55 PD7

1
DTC115EUA_SC70-3 10K_0402_1% 1 2
2

1
ACOFF <31,38>

1
100K_0402_1%
PC30

PR208
PD16 1SS355_SOD323-2

1
0.1U_0603_25V7K 2 FSTCHG

2
3

2 1
PQ12 3 200K_0402_1%

2
DTA144EUA_SC70-3 1 2 SUSP# <16,24,31,36,42,43> PR56

2
2 PR209 BAS40CW_SOT323-3 1 2 VIN
100K_0402_1%

1
0.1U_0603_25V7K
PU4 PQ14
1

PC32 DTC115EUA_SC70-3 PD9

1

6251VDD 1 24 6251DC_IN 2 1 2 1 2
VDD DCIN BATT+
2N7002W-T/R7_SOT323-3

1
1SS355_SOD323-2 PC31 1SS355_SOD323-2

1
PD8 2.2U_0603_6.3V6K D PQ15
2 2 ACSET ACPRN 23

1
0.1U_0603_25V7K
1 2 6251_EN PR219 2
<31> FSTCHG PACIN <38>

PC33
PQ13 20_0603_5% G

1
100K_0402_1%
DTC115EUA_SC70-3 2 1 3 22 1 2 CSON S

3
EN CSON
1

2
PQ16 D PR57 PC156 PC35
3

5
6
7
8
PR59
2 PR60 10K_0402_5% 0.1U_0402_16V7K 0.047U_0603_25V7M
G 2N7002W-T/R7_SOT323-3 150K_0402_1% CELLS 4 21 1 2 CSOP

D
D
D
D
2

1
@ 680P_0402_50V7K CELLS CSOP PR61 20_0603_5% PQ17
S
3

2
2
PC34 SI4800BDY-T1-E3_SO8 2
2

CSON1 2 5 20 2 1 CS IN
ICOMP CSIN

G
S
S
S
PC38 PR62 20_0603_5%
2

0.1U_0603_25V7K

4
3
2
1
PC36 6 19 1 2 CSIP <BOM Structure> PL1

1
6800P_0402_25V7K VCOMP CSIP PR220 10U_LF919AS-100M-P3_4.5A_20%
1

100P_0402_50V8J 100_0402_1% 2.2_0603_5%

2

2
PR66 PC39 1 PR64 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE BATT+
1

22K_0402_1% PQ18 D
PACIN 1 2 2 CSOP 2 3 CSON
<38> PACIN 1
G 2N7002W-T/R7_SOT323-3 6251VREF 8 17 DH_CHG
PR63 VREF UGATE PR65
S
3

2 1

5
6
7
8
10K_0402_1% PR68 0.02_2512_1%

10U_1206_25V6M

10U_1206_25V6M
9 16 BST_CHG 1 2 BST_CHGA 2 1

D
D
D
D
ACON PC37 CHLIM BOOT 2.2_0603_5%
<38> ACON

1
PC42

PC43
0.01U_0402_25V7K <31> ADP_I PC41 PQ19
1

10 15 6251VDDP PD10 0.1U_0603_25V7K

ACLIM VDDP
1

G
S
S
S
SI4800BDY-T1-E3_SO8

2
PC40 RB751V-40_SOD323-2

4
3
2
1
0.1U_0402_16V7K 11 14 DL_CHG
1

2
VADJ LGATE
1 26251VDD
2 PR67 4.7_0603_5%
<31,38> ACOFF 143K_0402_1% 12 13 PR71
GND PGND

2
PQ20 2 1
<31> IREF
39.2K_0402_1%
DTC115EUA_SC70-3 PR70 ISL6251AHAZ-T_QSOP24 PC45
3

1
0.01U_0402_25V7K

6251VREF 1 2 4.7U_0805_6.3V6K
1

1
PC44

PR69
100K_0402_1%
1

6251VREF
2

10K_0402_1% 6251VDD 1 2 CELLS

2

3 3

PR72 1

1
PR58
PR210 47K_0402_5% PQ45
2

100K_0402_1% DTC115EUA_SC70-3
6251_EN VS BATT+
<39> ALI/MH# 2
2

6251VREF 3 1 1 2
PR73
1

1
@ 274K_0402_1% C PQ44
1

2 PR75

3
0.01U_0402_25V7K

0.01U_0402_25V7K
PR74 B 340K_0402_1%
CP mode @ 100K_0402_1% PQ21 E 2SC2411KT146_SOT23-3
3

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) @

2
1

1
PC157

PC46
@ SI2301BDS-T1-E3_SOT23-3 PR211
2

where Vaclm=0.5535V, Iinput=3.079A 20K_0402_1%

1
2

2
where Vaclm=0.6667V, Iinput=4.263A PR76
499K_0402_1%
2

CSON
OVP voltage :

8
PR77 PU5A

2
CHGSEL 10K_0402_1% 3 LI-3S :13.50V--BATT-OVP=1.5V

P
+
1 2 1
CC=0.6~3.4A <31> BATT_OVP 0
0.01U_0402_25V7K

If this area float, Charge voltage is 4.2V/cell - 2 LI-4S :18V--BATT-OVP=2.0V

G
VCHLM=0.24V~1.36V

1
LM358ADR_SO8 BATT-OVP=0.111*BATT+

4
1

1
PC47

PR78 PC48
IREF=0.972*Icharge 105K_0402_1% 0.01U_0402_25V7K
@
IREF=0.5832V~3.3V
2

2
2
4 4

Charging Voltage
BATT Type ALI/MH# CV mode
(0x15)
4800mAH 3S pack 16800mV LOW 16.8V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title
2400mAH 4S pack 12600mV HIGH 12.60V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 40 of 46
A B C D
 A B C D

B+

2
PJ13
2

JUMP_43X118
1

PC49 PC50
1

0.1U_0402_16V7K 0.1U_0402_16V7K

2
1 2 BST5B PD11 BST3B 1 2

1 B+++ <BOM Structure> 1

B+++

SI4800BDY-T1-E3_SO8
VL

8
7
6
5

1
10U_1206_25V6M

D
D
D
D

0_0603_5%
PQ22
BAW56W_SOT323-3
1

B+++
PC51

PR79

SI4800BDY-T1-E3_SO8
2200P_0402_50V7K
2

0.1U_0402_16V7K
47_0402_5%
G

5
6
7
8
S
S
S

4.7_1206_5%

4.7_1206_5%

PR82

10U_1206_25V6M
2

1
PR80

PR81

PC52
PR83

D
D
D
D
1
2
3
4

1
PC53

PC54

PQ23
0_0603_5%

2
5HG 1 2 DH5

2
2

G
S
S
S
LX5

SI4810BDY-T1-E3_SO8
@

4
3
2
1
8
7
6
5

2
0.1U_0603_25V7K
PC55
1U_0805_25V4Z

0_0603_5%
PR84
VL 3HG

D
D
D
D
8734_VREF

PQ24
LX3

200K_0402_1%
2
4.7U_0805_6.3V6K
10UH_1164AY-100M=P3_4.7A_20%

1 PC58

PR85

200K_0402_1%

1
G

5
6
7
8
S
S
S

1U_0805_16V7K

PR86

SI4810BDY-T1-E3_SO8
1

PC57

D
D
D
D
1
2
3
4

1
BST3A

PC56

PQ25
2

0_0603_5%
DL5

G
S
S
S
PR87
2

10UH_1164AY-100M=P3_4.7A_20%
499K_0402_1%
18

20

13

17

4
3
2
1
PR88

499K_0402_1%
2
PL2

BST5A 14

V+
LD05

TON

VCC

1
BST5

PR89
2
<BOM Structure> ILIM3 5 2

16 DL3

1
DH5
+5VALWP
1

2
15

1
LX5
19 DL5 ILIM5 11

PL3
21 OUT5
9 PU7 28
FB5 BST3
10.5K_0402_1%

1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2

24

1
DL3
150U_D2_6.3VM

PR90

6 SHDN# LX3 27
VS 4 22
1 ON5 OUT3
1 2 3 ON3
PC59

+ PR91 7
1

0_0402_5% FB3
12 SKIP# PGOOD 2 +3VALWP
2 8734_VREF

PRO#
LDO3
PR93 8

GND
REF
2

2
6.81K_0402_1%

6.81K_0402_1%
PZD1 47K_0402_1%

2
PR92

1 2 1 2

330U_D3L_6.3VM_R25M
PR95
PR94

23

25

10
0.047U_0603_16V7K

0.22U_0603_16V7K
GLZ5.1B_LL34-2 0_0402_5% 1

4.7U_0805_6.3V6K
100K_0402_5%
1

1
2

PC61

PC62
+

1
PR96

PC60

0_0402_5%
<39> SPOK
2

2
2

PC63

PR97

10K_0402_1%
1

PR99
PR98
+5V Ipeak = 6.66A ~ 10A 47K_0402_1%

1
1 2
0.047U_0603_16V7K

3 3

1
1

PC64

VFB=2V
2

+3.3V Ipeak = 6.66A ~ 10A

MAINPWON <38,39>
1U_0603_6.3V6M
1

PC65
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 41 of 46
A B C D
 5 4 3 2 1

+5VALW

D D

1
1

1
PC83 PR101 BAW56W_SOT323-3
2.2U_0603_6.3V6K PR110 10_0603_5%

2
10_0603_5% PD12
VCCA_1.8V
B+

2
VCCA_1.05V

1 2

1U_0603_10V6K

1U_0603_10V6K
B+_1.8/1.05

3
1

1
PC90

PC91
PJ14
PR100
1 2 100K_0402_5%

2
1 2
4.7U_1206_25V6K

@
4.7U_1206_25V6K

2
JUMP_43X118 BST_1.8V-1 BST_1.05V-1
1

1
PC87

8
7
6
5
PC86

PU8
PQ28
D
D
D
D
2

SI4800BDY-T1-E3_SO8 1 PGND1 VSSA1 28

DL_1.8V 2 27 PGOOD1_1.8V
G DL1 PGD1
S
S
S
PR119 PC80
Maximum continuous current=>6A 0_0402_5% 1 2 +5VALW 3 26 FB_1.8V B+_1.8/1.05
1
2
3
4

VDDP1 FB1

4.7U_1206_25V6K
DH_1.8V-1
1 2 1U_0603_10V6K PC84

1
+1.8VP

4.7U_1206_25V6K
PL5 1 2 ILIM_1.8V
4 25 VCCA_1.8V 1000P_0402_50V7K
ILIM1 VCCA1

PC66

PC67
1.8UH_1164AY-1R8N=P3_9.5A_30% PR114 27.4K_0402_1% 1 2
Vout_1.8V 1 2 LX_1.8V 5 24 Vout_1.8V SI4800BDY-T1-E3_SO8

2
LX1 VOUT1

5
6
7
8
PR112
DH_1.8V 6 23 2 1 B+_1.8/1.05 PQ26

D
D
D
D
DH1 TON1
1

26.1K_0402_1%

C PC82 PR115 820K_0402_5% C

1

1 2 1 2 BST_1.8V 7 BST1 EN/PSV1 22

PR122

PC89 PR108 PC72

8
7
6
5

G
S
S
S
220U_D2_4VY_R15M

1 33P_0402_50V8K 0.1U_0603_25V7K 0_0402_5% 8 21 BST_1.05V

1 2 1 2 PR102
2

PQ29 EN/PSV2 BST2 0_0402_5% 0_0402_5% Maximum continuous current=>6A

D
D
D
D
2

4
3
2
1
PC85

+ FB_1.8V SI4810BDY-T1-E3_SO8 B+_1.8/1.05 2 1 9 20 DH_1.05V 0.1U_0603_25V7K 1 2 DH_1.05V-1 PL4

TON2 DH2
PR116 Vout_1.05V 10 19 LX_1.05V
1.8UH_1164AY-1R8N=P3_9.5A_30%
1 2 Vout_1.05V
+VCCPP
VOUT2 LX2
1

2
S
S
S

1M_0402_5% PR109

11K_0402_1%
PR121 VCCA_1.05V 11 18 ILIM_1.05V1 2
1
2
3
4

VCCA2 ILIM2

5
6
7
8

1
10K_0402_1% PC68 34K_0402_1% SI4810BDY-T1-E3_SO8

330U_D2_2V_Y

330U_D2_2V_Y
PR106
1000P_0402_50V7K FB_1.05V 12 17 +5VALW PQ27 PC74 1 1

D
D
D
D
2
FB2 VDDP2 33P_0402_50V8K
2

PC69

PC71
13 16 DL_1.05V + +
PGD2 DL2

2
G
S
S
S
14 15 FB_1.05V
VSSA2 PGND2

1
2 2

4
3
2
1

1
PR103 PC78
56K_0402_5% 1U_0603_10V6K PR107 @

2
Close to IC Side 1 2 SC413TSTRT_TSSOP28 10K_0402_1%
<16,24,31,36,40,43> SUSP#
Differential routing of feedback VFB=0.5V

2
1

PC70
to VSSA1 and VOUT1 PIN +5VALW 0.1U_0402_16V7K
2
1

PR113 PR124 Close to IC Side

B 100K_0402_5% 0_0402_5% B
@ 1 2 Differential routing of feedback to VSSA2 and VOUT2 PIN
<24,31,36> SYSON
2

1
@ PC168
PGOOD2_1.05V 0.1U_0402_16V7K

2
VFB=0.5V
VFB=0.5V Vo=VFB*(1+PR129/PR130)=1.5V
Vo=VFB*(1+PR122/PR127)=1.805V Ipeak=5.16A, Imax=3.612A
Ipeak=12.17A, Imax=8.519A Ton=(3.3E-12*(PR125+37K)*(Vout/VBat))+50ns
Ton=(3.3E-12*(PR121+37K)*(Vout/VBat))+50ns =0.3201us
=3.3*10e-12*(820K+37K)*(1.8/19)+50ns=0.3179us AO4916 Rds(on)=>Typ:21 mOhm
FDS6670AS:Rds(on)=>Typ:9 mOhm Max:27 mOhm
Max:11.5 mOhm Ivalleymin=9*10u*(29.4K/0.027*1.4)=7A
Iocp=Ivalley+  Iripple /2 Ivalleymax=11*E-6*(29.4K/0.021*1.1)=12.833A
Iripple=(vin-vout)*(Ton/L)=5.467A, 1/2 Iripple=2.734A. Iripple=(vin-vout)*(Ton/L)=2.546A, 1/2Iriiple=1.273A

A
Ivalleymin=10E-6*(PR120/Rds(ON)max*1.5) Iocp=Ivalley+  Iripple /2 A

=9*10e-6*(27.4K/0.0115*1.5)=14.295A>11.73*1.2=14.076A OCP==>8.273A~14.106A
Ivalleymax=10E-6*(PR120/Rds(ON)typ*1.2)
=11*10e-6*(27.4K/0.009*1.2)=27.907A. Security Classification Compal Secret Data Compal Electronics, Inc.
OCP==>17.029A~30.641A Issued Date 2007/01/16 Deciphered Date 2008/01/16 Title
+VCCPP/+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 42 of 46
5 4 3 2 1
 5 4 3 2 1

+5VALW

1
1
PR127
PR212 PC97 10_0603_5%
47K_0402_5% 2.2U_0603_6.3V6K

2
1 2 PD14

2
<16,24,31,36,40,42> SUSP# VCCA_1.5V

1U_0603_10V6K
D PR213 D
B+_1.5VSP

PC99
PC163 1M_0402_5% 1SS355_SOD323-2
PJ15
B+_1.5VSP
0.1U_0402_16V7K 2 1

1
1 2 B+

2
1 2

4.7U_1206_25V6K
SI4800BDY-T1-E3_SO8
BST_1.5V-1

1
4.7U_1206_25V6K
JUMP_43X118

PC111

PC93
D 5
D 6
D 7
D 8
PC164

2
1000P_0402_50V7K

PQ30
+5VALW

16

15

14

13

4 G
3 S
2 S
1 S
PR126 PC100
BST_1.5V 1 2 1 2

EN/PSV
TON

NC

BST
0_0603_5% Maximum continuous current=>6A

1
Vout_1.5V 1 12 DH_1.5V 0.1U_0603_25V7K PL6
VOUT DH
PR214
100K_0402_5% VCCA_1.5V 2 11 LX_1.5V
1.8UH_1164AY-1R8N=P3_9.5A_30%
1 2 Vout_1.5V
+1.5VSP
VCCA LX PR128

5
6
7
8

20K_0402_1%
FB_1.5V 3 10 ILIM_1.5V 1 2

2
FB ILIM

1
26.1K_0402_1% SI4810BDY-T1-E3_SO8

D
D
D
D

PR132

470U_D2_2.5VM
PGOOD2_1.5V 4 9 +5VALW PQ31 PC101 1
PGD VDDP

PGND
VSSA
33P_0402_50V8K

PC96
+

NC
TP

DL

G
S
S
S

2
PU9 FB_1.5V

17

4
3
2
1
SC411MLTRT_MLPQ16_4X4 DL_1.5V 2

1
VFB=0.5V
PR133

1
10K_0402_1%
PC108
1U_0603_10V6K

2
C C

Close to IC Side
+3VS Differential routing of feedback to VSSA2 and VOUT2 PIN

VFB=0.5V, Ipeak=14.02A, Imax=9.814A

1

PJ18 The current rating of +1.05VSP include +VCC_GFX current.

1

JUMP_43X79 +5VS
Vo=VFB*(1+PR146/PR147)=1.05V
2

Ton=(3.3E-12*(PR142+37K)*(Vout/VBat))+50ns=0.2391us
2

PC154 1U_0603_6.3V6M
SI4810BDY:Rds(on)=>Typ:9mOhm
2
1

Max:11.5 mOhm
PC159
10U_0805_6.3V6M PU13 Ivalleymin=9*10E-6*(PR145/Rds(ON)max*1.5)
2

6 VCNTL
5 VIN VOUT 3 +2.5VSP =9*10E-6*(26.1K/(0.0115*1.5))=13.617A
9 VIN VOUT 4

1
Ivalleymax=11*10E-6*(PR145/Rds(ON)min*1.2)

22U_1206_6.3V6M
1 2 8 PR205
<16,24,31,36,40,42> SUSP# EN

PC158
7 2 PC155 =11*10E-6*(26.1K/(0.009*1.3))=20.076A
GND

2
0_0402_5% PR204 POK FB 2.15K_0402_1%

2
1

Iripple=(vin-vout)*(Ton/L)=4.292A, 1/2Iripple=2.146A

2
B PC160 APL5913-KAC-TRL_SO8 B
1

@0.1U_0402_16V7K Iocp=Ivalley+  Iripple  /2

2

1
0.01U_0402_25V7K

PR203
OCP==>15.763A~22.222A
1K_0402_1%
2

+1.8V
1

PJ19
1

JUMP_43X118
2
2

PU14
1 VIN VCNTL 6 +3VALW
2 GND NC 5
1

1
1

PC161 3 7 PC162
10U_0805_6.3V6M REFEN NC 1U_0603_6.3V6M
2

PR206 4 8
1K_0402_1% VOUT NC
9
2

GND
RT9173DPSP_SO8
PR207
A A
+0.9VSP
1

0_0402_5% PQ41 D
1

1 2 2
1

<36> SUSP G PR215

S 1K_0402_1% PC165
3

2
1

22U_1206_6.3V6M
2

PC166
@ 0.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
2

PC167 2005/10/17 2006/10/17 Title

0.1U_0402_16V7K
Issued Date Deciphered Date
<BOM
2N7002W-T/R7_SOT323-3
Structure>
1.5VSP/2.5VSP/0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 43 of 46
5 4 3 2 1
 5 4 3 2 1

+5VS

CPU_B+ B+
PR156 PL8
5VS12 1 HCB4532KF-800T90_1812
1 2

0.01U_0402_25V7K
0_1206_5%

2200P_0402_50V7K
0.1U_0603_25V7K
PR157

PC127
10_0402_5% 1

1
10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

220U_25V_M
200K_0402_1%

PC128

PC129

PC130

PC131

PC132

PC133
+

2
2 PR158 1

2
D D

2
PC135

2
2.2U_0603_6.3V6K 2

2
PR159 PC134

1
13K_0402_5% 1U_0603_6.3V6M

5
PQ35
PU12 SI7686DP-T1-E3_SO8

1
NTC 0_0603_5%
100K_0402_5% V CC 19 25 PR161
Vcc VDD
PR160 1 2DH1_CPU-2
4
1 2 6 8 0_0603_5% 0.22U_0603_16V7K
THRM TON PR163 PC136
PR162 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
<5> CPU_VID0 D0 BST1 +CPU_CORE

3
2
1
PR164 0_0402_5% 2 1 32 29 DH1__CPU-1 PL9
<5> CPU_VID1 D1 DH1 0.36H_ETQP4LR36WFC_24A_20%

4.7_1206_5%
PR165 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
<5> CPU_VID2 D2 LX1

680P_0603_50V7K 2.1K_0402_1%
PR166 0_0402_5% 2 1 34 26 DL1__CPU
<5> CPU_VID3 D3 DL1

2
SI4856DY-T1-E3_SO8

SI4856DY-T1-E3_SO8
5
6
7
8

5
6
7
8

10_0402_5%
PR169

PR170
PR167 0_0402_5% 2 1 35 27
<5> CPU_VID4 D4 PGND1

D
D
D
D

D
D
D
D
PQ36

PQ37
PR168 0_0402_5% 2 1 36 18
<5> CPU_VID5

2
D5 GND

1
3.48K_0402_1%

1
PR171 0_0402_5% 1 2 37 17 CSP1__CPU PR174 PH2 NTC
<5> CPU_VID6 D6 CSP1

1
G

G
S
S
S

S
S
S
1 2 1 2
PR1732 71.5K_0402_1%
1 7 16 CSN1_CPU @

4
3
2
1

4
3
2
1
TIME CSN1 10KB_0603_5%_ERTJ1VR103J<5> VCCSENSE

PC137
DL1__CPU

2
2 1 9 12 FB_CPU 1 2
CCV FB

PR172
47P_0402_50V8J PC139
1 2 11 10 C CI_CPU PC140 0.22U_0603_16V7K
C REF CCI C

1 2 PC138 0.22U_0603_16V7K 39 21 DH2_CPU-1

<7,21> PM_DPRSLPVR DPRSLPVR DH2
PR175 499_0402_1%

2
1 2 40 20 BST2_CPU
<4,20> H_DPRSTP# DPRSTP BST2
PR176 0_0402_5% PR178
1 2 3 22 LX2_CPU PR179 0_0402_5% 0_0402_5%
<5> H_PSI# PSI LX2
PR177 0_0402_5% 1 2
+3VS 2 24 DL2__CPU

1
PWRGD DL2 PR181 @ 3K_0603_1% PC141 0.022U_0402_16V7K

0_0603_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2

PR180
2

38 14 CSP2_CPU PR184 3.92K_0402_1%

PR182 PR183 SHDN CSP2
1 2 1 2
PR186 10K_0402_1% @ 2K_0402_1% 5 15 CSN2__CPU

1
0_0402_5% VRHOT CSN2 PR185 100_0402_1%

2
4 13
1

POUT GNDS PC142

1 2 1 2 1 2

BSTM2_CPU
<15,21> VGATE 0_0402_5% 4700P_0402_25V7K

1
@ PR189 TP NTC PR187 PR188 @
1 2 @ 3K_0603_1% @ 3K_0603_1%
<15> CLK_ENABLE# MAX8770GTL+_TQFN40
41

2
<BOM Structure> @ 1 2 1 2
<31> VR_ON 1 2
PC143 PC144
1
2

CPU_B+

0.22U_0603_16V7K
PR190 PR191 470P_0603_50V8J

1
0_0402_5% PR192 +3VS 4700P_0402_25V7K 2 20K_0402_1%

PC145
@ 10K_0402_5%
1

PR194

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

0.1U_0603_25V7K
@ PR193 100_0402_1%
1

56_0402_5%

1
PC146

PC147
1

PC148

PC149

PC150
B PR195 0_0402_5% PQ38 B
2

1 2 VSSSENSE SI7686DP-T1-E3_SO8

2
<4> H_PROCHOT# <5> VSSSENSE 0_0603_5%
PR196
1

1 2 DH2_CPU-2 4
1 2 PR198
POUT
@ 10_0402_5%
2

PR197 10K_0402_1%
PC151
2

3
2
1
0.1U_0402_16V7K 2 1
1

4.7_1206_5%
PL10

1
SI4856DY-T1-E3_SO8
0.36H_ETQP4LR36WFC_24A_20%

PR199
5
6
7
8

5
6
7
8
PQ39

PQ40

2.1K_0402_1%
D
D
D
D

D
D
D
D

1
SI4856DY-T1-E3_SO8

PR200
G

G
S
S
S

S
S
S

680P_0603_50V7K
4
3
2
1

4
3
2
1

2
1

PC152
DL2__CPU PR201
3.48K_0402_1% NTC PH3

2
1 2 1 2

10KB_0603_5%_ERTJ1VR103J

1 2

A PR202 0_0402_5% PC153 0.22U_0603_16V7K A

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 44 of 46
5 4 3 2 1
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Rev. PG# Modify List

1 1
0.2 P.35 Change U17 P/N SA005280110 to SA00001H600
1 USB port 2 and 4 can't work

2 Change symbol 0.2 P.20.31 Change Y4 and X1 to SJ132P7K220

3 CRT wave 0.2 P.10 Change L41 to R878 and reserve C619

4 To meet INTEL SPEC 0.2 Change C148.C442.C171.C400.C606.C607 from 2200P to 22N

5 Delete reserve 0.2 P.17 Delete R71,74 Delete C171

6 FACTORY REQUEST 0.2 P.35 Delete JP5 PIN3

7 To meet CRT SPEC 0.2 P.18 Remove C7

2 2
8 Tune frequency 0.2 P.28 Change C511;515 from 27p to 18p

9 EMI Request 0.2 change C632 to 2.2nF Remove R441,R145,C6,12,13, change L2,3,4 to SM01000AL00

10 EMI Request 0.2 P.30 LAN RX TX change

11 EMI Request 0.2 P.32 ADD D22;23;24

12 EMI Request 0.2 P.4 Delete ITP_BPM0-5 and R515

13 FAN issue 0.2 P.4 Change R276 from 10k to 1k ohm C341 from 1000p to 100p

Change USB port 2 to NEW card port 7 to USB

14 USB issue 1.0 P.21
Change R322 to 22 ohm
3 3

15 Remove LPC debug connect 1.0 P.33 Remove JP13,R265,R441,R145

16 ESD Request and reserve 1.0 ADD T48 AND R515 AND JP9 29,30 pin to GND

17 Power improve 1.0 P.6 RemoveC26,31,314,315

18 0.2

19 0.2

20 0.2
4 4

Compal Electronics, Inc.

Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 18, 2007 Sheet 45 of 46
A B C D E
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D D

1
+1.5VSP output voltage is 2V. BOM error for +1.5VSP output. 0.2 6 1.Change the PR132 for 30K to 20K. 03/20/07 DVT

1.Add the PC163 0.1u_0402_16V.

2
0.2 6 04/09/07 PVT
Power sequence update for 1.5VS. HW request. 2.Change the PR212 from O to 47K.
1.Add the PC97 0.1u_0402_16V.
3
HW request. 0.2 5 04/09/07 PVT
Power sequence update for +VCCPP. 2.Change the PR103 from O to 56K.

4
Reduce the overshoot on P2 point. IFL01 issue. 0.2 1 1.Add the PR1 10_1206 and PD1 RZ24B. 04/09/07 PVT

5
Symbol issue. DFB team request. 0.2 1/3 1.Change the symbol for the PZD1,PD2,PD3,PD4 and PQ21. 04/09/07 PVT

6
Noise issue for idle. Noise issue for idle. 0.2 7 1.Change the PC133 from 100U to 220U 25V. 04/09/07 PVT

C C

B B

A A

Compal Electronics, Inc.

Title
PIR (PWR)
Size Document Number Rev
IHL00 LA-3581P 0.2

Date: Friday, May 18, 2007 Sheet 46 of 46

5 4 3 2 1