A B C D E

1 1

Compal Confidential
2 2

NAWE5 Schematics Document

AMD Danube
Champlain Processor with RS880M/SB820/Park VGA

3
2010-04-29 3

LA5753 REV: 1.A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 1 of 48
A B C D E
 A B C D E

Compal Confidential ZZZ1 ZZZ2

CAP SENSOR BD: CARD READER BD:
POWER BD: ZZZ3
ZZZ4
Model Name : AMD Danube + Park VOLUME UP
POWER BTN RTS5159
LA5753P LS-5751P 4 layer
VOLUME DOWN
NOVO BTN HP JACK
MUTE
DAZ@
@ POWER MANAGE BTN LS5756P MIC JACK
DA80000IK10
DA40000PW10
@
AUDIO ENHANCE LS5753P
DAZ0E500100 DA40000T310 BUTTON & LED @
DA40000Q210
1
Danube 1

VRAM 512MB
64M16 x 4 AMD S1G4 Processor
page 18 Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2
uPGA-638 Package Dual Channel BANK 0, 1, 2, 3 page 8,9
DDR3 Champlain page 4,5,6,7 1.5V DDRIII 800~1333MHz

ATI Park - S3 Hyper Transport Link

uFCBGA-631 PCI-Express x 16 16 x 16
Page 13,14,15,16,17
Gen2 Thermal Sensor Clock Generator
ATI RS880M
ADM1032 ICS9LPRS488
page 6 page 19
LVDS uFCBGA-528
page 27
2 2
page 10,11,12,13 page 37 page 37 page 27 page 37 page 28 page 28 page 28
CRT
page 25
A link Express2 USB USB CMOS Bluetooth Mini 3G/GPS
Gen1 PORT conn Camera Conn card WWAN New Card
HDMI Conn. (LEFT) (Right) <Option> (WL)X1 <Option>
page 26 USB port 0 USB port 12 USB port 5 USB port 6 USB port 11 USB port 10 USB port 7
ATI SB820M 3.3V 48MHz USB
S-ATA Gen2
LAN(GbE) uFCBGA-605
New Card 3G/WWAN MINI Card Atheros 3.3V 24.576MHz/48Mhz
WLAN WLAN page 20,21,22,23,24
MINI Card AR8151/8152
page 28 page 28 page 28 page 29
HD Audio ESATA &
GPP3 GPP2 GPP1 GPP0 SATA HDD CDROM
USB
SIM RJ45 Conn. page 32 Conn.
page 32 Combine CON
3 3

Card page 30 LPC BUS port 0 port 1 USB port 4

page28 page28
LED USB(WWAN)
page 36
USB port 2
Audio Codec Card Reader /
ENE KB926
LID SW / IO BD page 34
Realtec ALC259 Audio Jack SB CONN
page33
page 32 RTS5159-GR
HP X 1+
MS/MS
MIC_Ext X1
pro/SD/SD
Power On/Off CKT. Touch Pad Int.KBD pro/mmc/XD page38
page 35 page 35
page 32 Analog 2Channel
MIC_Int Speaker
BIOS page33 page33
DC/DC Interface CKT. Fan Control page 34
page 31
4 4
page 38

Power Circuit
page 39,40,41,42,43,
Security Classification Compal Secret Data Compal Electronics, Inc.
44,45,46,47,48,49 Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 2 of 48
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 A B C D E

Voltage Rails
Power Plane Description S1 S3 S5

VIN Adapter power supply (19V) N/A N/A N/A

B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF
+0.75VS +0.75VS LDO power rail for DDR3 VTT ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF

+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF

SIGNAL
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V for CPU_VDDA ON OFF OFF S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VALW 3.3V always on power rail ON ON ON*
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS 3.3V switched power rail ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON*
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VS 5V switched power rail ON OFF OFF
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

EC SM Bus1 address EC SM Bus2 address

3 3

Device Address HEX Device Address HEX BOM Config

Smart Battery 0001 011X b 16H EMC1402-1 (CPU) 100_1100b 4CH
EMC1412-A (GPU) 111_1100b 7CH
EXT CLK Mode:EXT@
TMP411C (GPU) 100_1110b 4EH
INT CLK mode:INT@
EMC1403-2 (DDR,WWAN) 100_1101b 4DH
UMA only SKU: UMA@
DIS ONLY (Park S3): DIS@
SB820 SB820 LAN GIGA: 8151@
CMOS@
SM Bus 0 address SM Bus 1 address BT@
Device Address HEX Device Address
3G@
S@
Clock Generator 1101 001Xb
(SILEGO SLG8SP626)
D2 H@
DDR DIMM1 1001 000Xb
LAN 100: 8152@
90
DDR DIMM2 1001 010Xb
ESATA@
94
HDMI@+HDMI_UMA@
HDMI@+HDMI_DIS@
4 4
Express Card: EXP@
KB_LED: E7@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 3 of 48
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 A B C D E

1 1

+1.1VS
VLDT CAP.
250 mil

2 2 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
[10] H_CADIP[0..15] H_CADOP[0..15] [10]
10U_0805_10V4Z 10U_0805_10V4Z
H_CADIN[0..15] H_CADON[0..15] 1 1 2 2 2 2
[10] H_CADIN[0..15] H_CADON[0..15] [10]

Near CPU Socket

+1.1VS +1.1VS
JCPU1A
C7
2
TBD 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 2 1
D2 AE3
VLDT_A1 VLDT_B1 10U_0805_10V4Z
D3 AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 W3
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 V1
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 U2
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 AD4
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 AD3
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 AD5
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 AC5
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 AB4
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 V4
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15

[10] H_CLKIP0 J3 Y1 H_CLKOP0 [10]

L0_CLKIN_H0 L0_CLKOUT_H0
[10] H_CLKIN0 J2 W1 H_CLKON0 [10]
L0_CLKIN_L0 L0_CLKOUT_L0
[10] H_CLKIP1 J5 Y4 H_CLKOP1 [10]
L0_CLKIN_H1 L0_CLKOUT_H1
[10] H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 [10]

[10] H_CTLIP0 N1 R2 H_CTLOP0 [10]

L0_CTLIN_H0 L0_CTLOUT_H0
[10] H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 [10]
[10] H_CTLIP1 P3 T5 H_CTLOP1 [10]
L0_CTLIN_H1 L0_CTLOUT_H1
[10] H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 [10]

FOX_PZ6382A-284S-41F_Champlian
ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 HT I/F
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 4 of 48
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 A B C D E

Processor DDR3 Memory Interface

JCPU1C
[9] DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] [8]
DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.5V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2

DDRB_SDQ4 G11 H11 DDRA_SDQ4

R1 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 H12
1K_0402_1% DDRB_SDQ6 MB_DATA5 MA_DATA5 DDRA_SDQ6
D12 MB_DATA6 MA_DATA6 C13
DDRB_SDQ7 A13 E13 DDRA_SDQ7
DDRB_SDQ8 MB_DATA7 MA_DATA7 DDRA_SDQ8
A15 H15
1

MEM_VREF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9

A16 MB_DATA9 MA_DATA9 E15
1000P_0402_50V7K
0.01U_0402_25V7K

DDRB_SDQ10 A19 E17 DDRA_SDQ10

MB_DATA10 MA_DATA10
2

1 1 DDRB_SDQ11 A20 H17 DDRA_SDQ11

R2 DDRB_SDQ12 MB_DATA11 MA_DATA11 DDRA_SDQ12
C14 E14
MB_DATA12 MA_DATA12
C9

C8

1K_0402_1% DDRB_SDQ13 D14 F14 DDRA_SDQ13

DDRB_SDQ14 MB_DATA13 MA_DATA13 DDRA_SDQ14
C18 C17
2 2 DDRB_SDQ15 MB_DATA14 MA_DATA14 DDRA_SDQ15
D18 G17
1

DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16

D20 G18
DDRB_SDQ17 MB_DATA16 MA_DATA16 DDRA_SDQ17
A21 MB_DATA17 MA_DATA17 C19
DDRB_SDQ18 D24 D22 DDRA_SDQ18
DDRB_SDQ19 MB_DATA18 MA_DATA18 DDRA_SDQ19
C25 MB_DATA19 MA_DATA19 E20
DDRB_SDQ20 B20 E18 DDRA_SDQ20
DDRB_SDQ21 MB_DATA20 MA_DATA20 DDRA_SDQ21
C20 F18
DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 B22
DDRB_SDQ23 MB_DATA22 MA_DATA22 DDRA_SDQ23
C24 MB_DATA23 MA_DATA23 C23
DDRB_SDQ24 E23 F20 DDRA_SDQ24
DDRB_SDQ25 MB_DATA24 MA_DATA24 DDRA_SDQ25
E24 F22
DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
G25 MB_DATA26 MA_DATA26 H24
DDRB_SDQ27 G26 J19 DDRA_SDQ27
DDRB_SDQ28 MB_DATA27 MA_DATA27 DDRA_SDQ28
C26 E21
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+1.5V +CPU_VDDR +CPU_VDDR DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
G24 H22
JCPU1B DDRB_SDQ32 MB_DATA31 MA_DATA31 DDRA_SDQ32
AA24 Y24
2 DDRB_SDQ33 MB_DATA32 MA_DATA32 DDRA_SDQ33 2
Place them 1.5A AA23 MB_DATA33 MA_DATA33 AB24
2

close to CPU D10 W10 FOR DDR3 1066, VDDR is 0.9V DDRB_SDQ34 AD24 AB22 DDRA_SDQ34
R368 VDDR1 MEM:CMD/CTRL/CLK
VDDR5 DDRB_SDQ35 MB_DATA34 MA_DATA34 DDRA_SDQ35
within 1" C10 AC10 AE24 AA21
VDDR2 VDDR6 DDRB_SDQ36 MB_DATA35 MA_DATA35 DDRA_SDQ36
B10 VDDR3 VDDR7 AB10 FOR DDR3 1333, VDDR it should be 1.05V AA26 MB_DATA36 MA_DATA36 W22
0_0402_5% AD10 AA10 DDRB_SDQ37 AA25 W21 DDRA_SDQ37
R4 39.2_0402_1% VDDR4 VDDR8 DDRB_SDQ38 MB_DATA37 MA_DATA37 DDRA_SDQ38
A10 AD26 Y22
1

MEMZP AF10 VDDR9 DDRB_SDQ39 MB_DATA38 MA_DATA38 DDRA_SDQ39

1 2 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
1 2 MEMZN AE10 Y10 VTT_SENSE DDRB_SDQ40 AC22 Y20 DDRA_SDQ40
MEMZN VDDR_SENSE PAD T1 DDRB_SDQ41 MB_DATA40 MA_DATA40 DDRA_SDQ41
2 R5 39.2_0402_1% AD22 AA20
C588 MEM_MA_RST# MEM_VREF DDRB_SDQ42 MB_DATA41 MA_DATA41 DDRA_SDQ42
[8] MEM_MA_RST# H16 W17 AE20 AA18
MA_RESET_L MEMVREF DDRB_SDQ43 MB_DATA42 MA_DATA42 DDRA_SDQ43
AF20 MB_DATA43 MA_DATA43 AB18
10U_0805_10V4Z DDRA_ODT0 T19 B18 MEM_MB_RST# DDRB_SDQ44 AF24 AB21 DDRA_SDQ44
[8] DDRA_ODT0 MA0_ODT0 MB_RESET_L MEM_MB_RST# [9] MB_DATA44 MA_DATA44
@ 1 DDRA_ODT1 V22 DDRB_SDQ45 AF23 AD21 DDRA_SDQ45
[8] DDRA_ODT1 MA0_ODT1 DDRB_ODT0 DDRB_SDQ46 MB_DATA45 MA_DATA45 DDRA_SDQ46
U21 W26 DDRB_ODT0 [9] AC20 AD19
MA1_ODT0 MB0_ODT0 DDRB_ODT1 DDRB_SDQ47 MB_DATA46 MA_DATA46 DDRA_SDQ47
V19 W23 DDRB_ODT1 [9] AD20 Y18
MA1_ODT1 MB0_ODT1 DDRB_SDQ48 MB_DATA47 MA_DATA47 DDRA_SDQ48
Y26 AD18 AD17
DDRA_SCS0# MB1_ODT0 DDRB_SDQ49 MB_DATA48 MA_DATA48 DDRA_SDQ49
[8] DDRA_SCS0# T20 AE18 W16
DDRA_SCS1# MA0_CS_L0 DDRB_SCS0# DDRB_SDQ50 MB_DATA49 MA_DATA49 DDRA_SDQ50
[8] DDRA_SCS1# U19 V26 DDRB_SCS0# [9] AC14 W14
MA0_CS_L1 MB0_CS_L0 DDRB_SCS1# DDRB_SDQ51 MB_DATA50 MA_DATA50 DDRA_SDQ51
U20 W25 DDRB_SCS1# [9] AD14 Y14
MA1_CS_L0 MB0_CS_L1 DDRB_SDQ52 MB_DATA51 MA_DATA51 DDRA_SDQ52
V20 MA1_CS_L1 MB1_CS_L0 U22 AF19 MB_DATA52 MA_DATA52 Y17
DDRB_SDQ53 AC18 AB17 DDRA_SDQ53
DDRA_CKE0 DDRB_CKE0 DDRB_SDQ54 MB_DATA53 MA_DATA53 DDRA_SDQ54
[8] DDRA_CKE0 J22 J25 DDRB_CKE0 [9] AF16 AB15
DDRA_CKE1 MA_CKE0 MB_CKE0 DDRB_CKE1 DDRB_SDQ55 MB_DATA54 MA_DATA54 DDRA_SDQ55
[8] DDRA_CKE1 J20 H26 DDRB_CKE1 [9] AF15 AD15
MA_CKE1 MB_CKE1 DDRB_SDQ56 MB_DATA55 MA_DATA55 DDRA_SDQ56
AF13 AB13
DDRA_CLK0 DDRB_CLK0 DDRB_SDQ57 MB_DATA56 MA_DATA56 DDRA_SDQ57
[8] DDRA_CLK0 N19 P22 DDRB_CLK0 [9] AC12 AD13
DDRA_CLK0# MA_CLK_H5 MB_CLK_H5 DDRB_CLK0# DDRB_SDQ58 MB_DATA57 MA_DATA57 DDRA_SDQ58
[8] DDRA_CLK0# N20 R22 DDRB_CLK0# [9] AB11 Y12
MA_CLK_L5 MB_CLK_L5 DDRB_SDQ59 MB_DATA58 MA_DATA58 DDRA_SDQ59
E16 MA_CLK_H1 MB_CLK_H1 A17 Y11 MB_DATA59 MA_DATA59 W11
F16 A18 DDRB_SDQ60 AE14 AB14 DDRA_SDQ60
MA_CLK_L1 MB_CLK_L1 DDRB_SDQ61 MB_DATA60 MA_DATA60 DDRA_SDQ61
Y16 AF18 AF14 AA14
MA_CLK_H7 MB_CLK_H7 DDRB_SDQ62 MB_DATA61 MA_DATA61 DDRA_SDQ62
AA16 AF17 AF11 AB12
DDRA_CLK1 MA_CLK_L7 MB_CLK_L7 DDRB_CLK1 DDRB_SDQ63 MB_DATA62 MA_DATA62 DDRA_SDQ63
[8] DDRA_CLK1 P19 R26 DDRB_CLK1 [9] AD11 AA12
DDRA_CLK1# MA_CLK_H4 MB_CLK_H4 DDRB_CLK1# MB_DATA63 MA_DATA63
[8] DDRA_CLK1# P20 R25 DDRB_CLK1# [9] [9] DDRB_SDM[7..0] DDRA_SDM[7..0] [8]
3 MA_CLK_L4 MB_CLK_L4 DDRB_SDM0 DDRA_SDM0 3
[8] DDRA_SMA[15..0] DDRB_SMA[15..0] [9] A12 MB_DM0 MA_DM0 E12
DDRA_SMA0 N21 P24 DDRB_SMA0 DDRB_SDM1 B16 C15 DDRA_SDM1
DDRA_SMA1 MA_ADD0 MB_ADD0 DDRB_SMA1 DDRB_SDM2 MB_DM1 MA_DM1 DDRA_SDM2
M20 N24 A22 E19
DDRA_SMA2 MA_ADD1 MB_ADD1 DDRB_SMA2 DDRB_SDM3 MB_DM2 MA_DM2 DDRA_SDM3
N22 MA_ADD2 MB_ADD2 P26 E25 MB_DM3 MA_DM3 F24
DDRA_SMA3 M19 N23 DDRB_SMA3 DDRB_SDM4 AB26 AC24 DDRA_SDM4
DDRA_SMA4 MA_ADD3 MB_ADD3 DDRB_SMA4 DDRB_SDM5 MB_DM4 MA_DM4 DDRA_SDM5
M22 N26 AE22 Y19
DDRA_SMA5 MA_ADD4 MB_ADD4 DDRB_SMA5 DDRB_SDM6 MB_DM5 MA_DM5 DDRA_SDM6
L20 L23 AC16 AB16
DDRA_SMA6 MA_ADD5 MB_ADD5 DDRB_SMA6 DDRB_SDM7 MB_DM6 MA_DM6 DDRA_SDM7
M24 N25 AD12 Y13
DDRA_SMA7 MA_ADD6 MB_ADD6 DDRB_SMA7 MB_DM7 MA_DM7
L21 L24
DDRA_SMA8 MA_ADD7 MB_ADD7 DDRB_SMA8 DDRB_SDQS0 DDRA_SDQS0
L19 MA_ADD8 MB_ADD8 M26 [9] DDRB_SDQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDRA_SDQS0 [8]
DDRA_SMA9 K22 K26 DDRB_SMA9 DDRB_SDQS0# B12 H13 DDRA_SDQS0#
MA_ADD9 MB_ADD9 [9] DDRB_SDQS0# MB_DQS_L0 MA_DQS_L0 DDRA_SDQS0# [8]
DDRA_SMA10 R21 T26 DDRB_SMA10 DDRB_SDQS1 D16 G16 DDRA_SDQS1
DDRA_SMA11 MA_ADD10 MB_ADD10 DDRB_SMA11 [9] DDRB_SDQS1 DDRB_SDQS1# MB_DQS_H1 MA_DQS_H1 DDRA_SDQS1# DDRA_SDQS1 [8]
L22 MA_ADD11 MB_ADD11 L26 [9] DDRB_SDQS1# C16 MB_DQS_L1 MA_DQS_L1 G15 DDRA_SDQS1# [8]
DDRA_SMA12 K20 L25 DDRB_SMA12 DDRB_SDQS2 A24 C22 DDRA_SDQS2
MA_ADD12 MB_ADD12 [9] DDRB_SDQS2 MB_DQS_H2 MA_DQS_H2 DDRA_SDQS2 [8]
DDRA_SMA13 V24 W24 DDRB_SMA13 DDRB_SDQS2# A23 C21 DDRA_SDQS2#
DDRA_SMA14 MA_ADD13 MB_ADD13 DDRB_SMA14 [9] DDRB_SDQS2# DDRB_SDQS3 MB_DQS_L2 MA_DQS_L2 DDRA_SDQS3 DDRA_SDQS2# [8]
K24 J23 [9] DDRB_SDQS3 F26 G22 DDRA_SDQS3 [8]
DDRA_SMA15 MA_ADD14 MB_ADD14 DDRB_SMA15 DDRB_SDQS3# MB_DQS_H3 MA_DQS_H3 DDRA_SDQS3#
K19 J24 [9] DDRB_SDQS3# E26 G21 DDRA_SDQS3# [8]
MA_ADD15 MB_ADD15 DDRB_SDQS4 MB_DQS_L3 MA_DQS_L3 DDRA_SDQS4
[9] DDRB_SDQS4 AC25 AD23 DDRA_SDQS4 [8]
DDRA_SBS0# DDRB_SBS0# DDRB_SDQS4# MB_DQS_H4 MA_DQS_H4 DDRA_SDQS4#
[8] DDRA_SBS0# R20 R24 DDRB_SBS0# [9] [9] DDRB_SDQS4# AC26 AC23 DDRA_SDQS4# [8]
DDRA_SBS1# MA_BANK0 MB_BANK0 DDRB_SBS1# DDRB_SDQS5 MB_DQS_L4 MA_DQS_L4 DDRA_SDQS5
[8] DDRA_SBS1# R23 U26 DDRB_SBS1# [9] [9] DDRB_SDQS5 AF21 AB19 DDRA_SDQS5 [8]
DDRA_SBS2# MA_BANK1 MB_BANK1 DDRB_SBS2# DDRB_SDQS5# MB_DQS_H5 MA_DQS_H5 DDRA_SDQS5#
[8] DDRA_SBS2# J21 J26 DDRB_SBS2# [9] [9] DDRB_SDQS5# AF22 AB20 DDRA_SDQS5# [8]
MA_BANK2 MB_BANK2 DDRB_SDQS6 MB_DQS_L5 MA_DQS_L5 DDRA_SDQS6
[9] DDRB_SDQS6 AE16 MB_DQS_H6 MA_DQS_H6 Y15 DDRA_SDQS6 [8]
DDRA_SRAS# R19 U25 DDRB_SRAS# DDRB_SDQS6# AD16 W15 DDRA_SDQS6#
[8] DDRA_SRAS# DDRA_SCAS# MA_RAS_L MB_RAS_L DDRB_SCAS# DDRB_SRAS# [9] [9] DDRB_SDQS6# DDRB_SDQS7 MB_DQS_L6 MA_DQS_L6 DDRA_SDQS7 DDRA_SDQS6# [8]
[8] DDRA_SCAS# T22 MA_CAS_L MB_CAS_L U24 DDRB_SCAS# [9] [9] DDRB_SDQS7 AF12 MB_DQS_H7 MA_DQS_H7 W12 DDRA_SDQS7 [8]
DDRA_SWE# T24 U23 DDRB_SWE# DDRB_SDQS7# AE12 W13 DDRA_SDQS7#
[8] DDRA_SWE# MA_WE_L MB_WE_L DDRB_SWE# [9] [9] DDRB_SDQS7# MB_DQS_L7 MA_DQS_L7 DDRA_SDQS7# [8]

FOX_PZ6382A-284S-41F_Champlian FOX_PZ6382A-284S-41F_Champlian
ME@ ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 DDRII I/F
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 5 of 48
A B C D E
 A B C D E

Champlain: C1E
C1E: LDT_REQ# no connect +1.5V
+2.5VDDA
CLMC: LDT_REQ# connect to NB
L1 VDDA=0.25A
+2.5VS 1 2 3300P_0402_50V7K

1
1 FBMA-L11-201209-221LMA30T_0805 1 1 1 LDT_RES# / MEMHOT# R6

2
no support in S1g4 10K_0402_5%
+ C11 4.7U_0805_10V4Z C12 C13 C14 R7
150U_B_6.3VM_R40M 0.22U_0603_16V4Z

2 2
2 2 2 1K_0402_5%
2

B
1
Q1
JCPU1D

E
1 CPU_THERMTRIP#_R 1
3 1 1 2 H_THERMTRIP# [21]

C
R8 0_0402_5%
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 VSS
F9 W18 1 2 MAINPWON [39,40,42]
VDDA2 RSVD11 R9 @ 0_0402_5%
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC
[19] CLK_CPU_BCLK CPU_CLKIN_SC_N CLKIN_H SVC CPU_SVD CPU_SVC [47]
C16 A8 A4 +1.5V 1 2
CLKIN_L SVD CPU_SVD [47]

1
R11 300_0402_5%
LDT_RST# B7
R10 H_PWRGD RESET_L
A7
169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R
F10 LDTSTOP_L THERMTRIP_L AF6
C6 AC7 H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT_R# [20]

2
T2 PAD LDTREQ_L PROCHOT_L R13 0_0402_5%
[19] CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 PAD T3
C15 3900P_0402_50V7K 1 2 CPU_SIC AF4
+1.5V SIC
R12 1 2 1K_0402_5% CPU_SID AF5 PROCHOT:
+1.5V SID
R14 1K_0402_5% AE6 W7 THERMDC_CPU
+1.5VS ALERT_L THERMDC
W8 THERMDA_CPU Input: For HTC Function 1 2 EC_PROCHOT# [34]
THERMDA
R15 1 2 44.2_0402_1% CPU_HTREF0 R6 Output: Over Temperature Condition R71 @ 0_0402_5%
HT_REF0
+1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 HT_REF1
2

R17 F6 W9 VDDIO_FB_H
[47] CPU_VDD0_FB_H VDD0_FB_H VDDIO_FB_H PAD T14
300_0402_5% E6 Y9 VDDIO_FB_L
[47] CPU_VDD0_FB_L VDD0_FB_L VDDIO_FB_L PAD T16
Y6 H6 CPU_VDDNB_FB_H
[47] CPU_VDD1_FB_H CPU_VDDNB_FB_H [47]
1

LDT_RST# VDD1_FB_H VDDNB_FB_H CPU_VDDNB_FB_L

[20] LDT_RST# [47] CPU_VDD1_FB_L AB6 G6 CPU_VDDNB_FB_L [47]
VDD1_FB_L VDDNB_FB_L
+1.5VS CPU_DBRDY G10
1 DBRDY
C17 CPU_TMS AA9 E10 CPU_DBREQ#
0.01U_0402_25V4Z CPU_TCK TMS DBREQ_L
AC9 TCK
2

@ CPU_TRST# AD9 AE9 CPU_TDO

2 R18 CPU_TDI TRST_L TDO
AF9
TDI +1.5V
300_0402_5%
2 CPU_TEST23 2
AD7 TEST23 TEST28_H J7
H8
1

LDT_STOP# CPU_TEST18 TEST28_L CPU_SVC

H10 1 2
+1.5VS [11,20] LDT_STOP# CPU_TEST19 G9
TEST18
D7 CPU_TEST17 R19 1K_0402_5%
TEST19 TEST17 CPU_TEST16 PAD T5 CPU_SVD
1 TEST16 E7 PAD T6 1 2
C18 CPU_TEST25H E9 F7 CPU_TEST15 R20 1K_0402_5%
TEST25_H TEST15 PAD T7
2

0.01U_0402_25V4Z CPU_TEST25L E8 C7 CPU_TEST14

TEST25_L TEST14 PAD T8
R21 @
2 CPU_TEST21 +1.5V
300_0402_5% AB8 TEST21 TEST7 C3
CPU_TEST20 AF7 K8
CPU_TEST24 TEST20 TEST10 CPU_TEST25H
AE7 1 2
1

H_PWRGD CPU_TEST22 TEST24 R22 510_0402_5%

[20] H_PWRGD AE8 C4
CPU_TEST12 TEST22 TEST8
AC8 TEST12 1 2
1 CPU_TEST27 AF8 R23 @ 510_0402_5%
C19 TEST27 CPU_TEST29_H_FBCLKOUT_P +1.5V
C9
0.01U_0402_25V4Z TEST29_H CPU_TEST29_L_FBCLKOUT_N
1 2 C2 C8 2 1
@ R24 0_0402_5% TEST9 TEST29_L R25 80.6_0402_1% CPU_TEST25L
AA6 1 2
2 TEST6 R26 @ 510_0402_5%
A3 H18 1 2
RSVD1 RSVD10 R27 510_0402_5%
A5 RSVD2 RSVD9 H19
B3 AA7
+3VS RSVD3 RSVD8
B5 D5
RSVD4 RSVD7
C1 C5
RSVD5 RSVD6
+1.5V
0.1U_0402_16V4Z

1 FOX_PZ6382A-284S-41F_Champlian
ME@
C20 CPU_TEST27 1 2
R28 1K_0402_5%
2 U1
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 [14,31,34]
3 THERMDA_CPU EC_SMB_DA2 3
2 D+ SDATA 7 EC_SMB_DA2 [14,31,34] For SCAN connect use
THERMDC_CPU 3 6 CPU_TEST12 1 2
D- ALERT# R29 1K_0402_5%
1 2
C21 100P_0402_50V8J 4 5 CPU_TEST18 1 2
@ THERM# GND R30 1K_0402_5%
R1A CPU_TEST19 1 2
EMC1402-1-ACZL-TR-MSOP-8P R31 1K_0402_5%
+1.5V CPU_TEST20 1 2
TI EMC1402-1 R32 1K_0402_5%
TMP411ADGKR MSOP 8P (SA00001Z700) CPU_TEST21 1 2
SA00002DE10 Address 100_1100b R33 1K_0402_5%

220_0402_5% R36

220_0402_5% R37

220_0402_5% R38

300_0402_5% R39

300_0402_5% R40
Address: 100 1100 S IC EMC1402-1-ACZL-TR MSOP 8P SENSOR CPU_TEST22 1 2
R34 1K_0402_5%
1

2
CPU internal thermal sensor CPU_TEST24 1 2
R35 1K_0402_5%
C22 @ 0.1U_0402_16V4Z CPU_TEST23 1 2
1 2 FDV301N, the Vgs is: R265 1K_0402_5%
min = 0.65V
2

1
JP17
R41 Typ = 0.85V @ @ @ @ 1
@ R42 @ Max = 1.5V 1
2 2
2 1 2 1 CPU_DBREQ# 3 1 2
+3VS 3
CPU_TCK 4 R43 @ 0_0402_5%
20K_0402_5% 34.8K_0402_1% CPU_TDI 4
5
CPU_TMS 5 +3VS
6
CPU_TRST# 6
7 7
2.09V for Gate HDT_RST# 8
8
2

5
G

CPU_DBRDY 9 U2 @
CPU_TDO 9 LDT_RST#
10 2

P
CPU_SID 3 EC_SMB_DA SB_SID 10 HDT_RST# B
1 1 2 SB_SID [21] T0 SB +1.5V 11
11 GND
13 4
Y
R44 @ 0_0402_5%
S

12 12 GND 14 A 1 SB_PWRGD [11,21,34]

G
4 EC_SMB_DA2 4
1 2 TO EC
Q2 @ FDV301N_NL_SOT23-3 R45 @ 0_0402_5% NC7SZ08P5X_NL_SC70-5

3
ACES_87212-12G0
ME@
2
G

CPU_SIC 3 EC_SMB_CK SB_SIC T0 SB

1 1
R46 @
2
0_0402_5%
SB_SIC [21] Security Classification Compal Secret Data Compal Electronics, Inc.
S

1 2 EC_SMB_CK2 TO EC 2008/10/06 2010/04/30 Title

Issued Date Deciphered Date
Q3 @ FDV301N_NL_SOT23-3 R47 @ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 CTRL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 6 of 48
A B C D E
 A B C D E

JCPU1F

VDD(+CPU_CORE) decoupling. +CPU_CORE JCPU1E +CPU_CORE

AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
36A AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE J9 R4 AA19 J16
R1.0 VDD0_3 VDD1_3 VSS6 VSS71
J11 R7 AB2 J18
VDD0_4 VDD1_4 VSS7 VSS72
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 R11 AB9 K7
VDD0_6 VDD1_6 VSS9 VSS74
1 1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 T6 AB25 K11
+ C23 + C24 @ + C25 + C26 + C27 VDD0_8 VDD1_8 VSS11 VSS76
K12 VDD0_9 VDD1_9 T8 AC11 VSS12 VSS77 K13
1 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2 2 L7 T14 AC17 L6
VDD0_12 VDD1_12 VSS15 VSS80
L9 U7 AC19 L8
VDD0_13 VDD1_13 VSS16 VSS81
Near CPU Socket L11
L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15
U9
U11
AC21
AD6
VSS17
VSS18
VSS82
VSS83
L10
L12
L15 U13 AD8 L14
VDD0_16 VDD1_16 VSS19 VSS84
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 V8 AE13 M7
+CPU_CORE VDD0_19 VDD1_19 VSS22 VSS87
M10 VDD0_20 VDD1_20 V10 AE15 VSS23 VSS88 M9
+CPU_CORE N7 V12 AE17 AC6
VDD0_21 VDD1_21 VSS24 VSS89
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 4A VDD1_24
Y2 AE23
VSS27 VSS92
N8
C28 C29 C30 C35 1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C31 C32 C33 C34 VDDNB_1 VDD1_25 +1.5V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 TBD B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.5V V16 V25 B11 P7
VDDNB_5 VDDIO26 VSS32 VSS97
V23 B13 P9
+CPU_CORE VDDIO25 VSS33 VSS98
H25 V21 B15 P11
+CPU_CORE VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 T25 B21 R10
VDDIO4 VDDIO21 VSS37 VSS102
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C36 C37 C38 C39 C40 C41 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 T18 D6 T7
VDDIO7 VDDIO18 VSS40 VSS105
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2 M21 P25 D9 T11
VDDIO9 VDDIO16 VSS42 VSS107
Under CPU Socket M23
M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14
P23
P21
D11
D13
VSS43
VSS44
VSS108
VSS109
T13
T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 U4
VSS46 VSS111
D19 U6
FOX_PZ6382A-284S-41F_Champlian VSS47 VSS112
D21 VSS48 VSS113 U8
Athlon 64 S1 ME@ D23 U10
VDDIO decoupling. Processor Socket D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 U16

+1.5V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 V9
+CPU_CORE_NB VSS56 VSS121
F19 VSS57 VSS122 V11
F21 V13
VSS58 VSS123
1 1 1 1 1 1 F23 V15
C44 C45 C46 C47 C48 C50 VSS59 VSS124
1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C42 C43 C49 VSS60 VSS125
H7 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VSS61 VSS126
H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 Y23
2 2 2 VSS63 VSS128
H23 VSS64 VSS129 N6
J4
VSS65
FOX_PZ6382A-284S-41F_Champlian
Under CPU Socket Athlon 64 S1 ME@
Processor Socket

Between CPU Socket and DIMM

+1.5V +CPU_VDDR
3 3
Near Power Supply
1
C51
1
C52
1
C53
1
C54
1
C354
1
C355
VDDR decoupling. 1 1
C55
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z + C56 22U_0805_6.3V6M
150U_B_6.3VM_R40M
2 2 2 2 2 2 2
2

180PF Qt'y follow the distance between

+1.5V +1.5V CPU socket and DIMM0. <2.5inch> +CPU_VDDR

1 1 2 2 1 1
C64 C65 C68 C69 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z C66 C67 180P_0402_50V8J 180P_0402_50V8J C57 C58 C59 C60 C61 C62 C63 C70
0.1U_0402_16V7K 0.1U_0402_16V7K 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 1 1 2 2
2 2 2 2 2 2 2 2

+1.5V
Near CPU Socket Right side.
+CPU_VDDR
1 R1.0
1 1 1 1
+ C75
C71 C72 C73 C74 330U_D2E_2.5VM_R9M 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C76 C77 C78 C79 C80 C81 C82 C83
2 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G4 PWR & GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 7 of 48
A B C D E
 A B C D E

+VREF_DQ +1.5V +1.5V

JDIMM1
1 VREF_DQ VSS1 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS2 DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8
DQ1 VSS3 DDRA_SDQS0#
9 10 DDRA_SDQS0# [5]
DDRA_SDM0 VSS4 DQS#0 DDRA_SDQS0
11 DM0 DQS0 12 DDRA_SDQS0 [5]
13 14 DDRA_SDQ[0..63]
DDRA_SDQ2 VSS5 VSS6 DDRA_SDQ6 DDRA_SDQ[0..63] [5]
15 DQ2 DQ6 16
DDRA_SDQ3 17 18 DDRA_SDQ7 DDRA_SDM[0..7]
DQ3 DQ7 DDRA_SDM[0..7] [5]
19 VSS7 VSS8 20
1 DDRA_SDQ8 DDRA_SDQ12 1
21 DQ8 DQ12 22
DDRA_SDQ9 23 24 DDRA_SDQ13
DQ9 DQ13 DDRA_SMA[0..15]
25 VSS9 VSS10 26 DDRA_SMA[0..15] [5]
DDRA_SDQS1# 27 28 DDRA_SDM1
[5] DDRA_SDQS1# DDRA_SDQS1 DQS#1 DM1 MEM_MA_RST#
[5] DDRA_SDQS1 29 30 MEM_MA_RST# [5]
DQS1 RESET#
31 VSS11 VSS12 32
DDRA_SDQ10 33 34 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRA_SDQ16 39 40 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 DQ17 DQ21 42
43 44
DDRA_SDQS2# VSS15 VSS16 DDRA_SDM2
[5] DDRA_SDQS2# 45 DQS#2 DM2 46
DDRA_SDQS2 47 48
[5] DDRA_SDQS2 DQS2 VSS17 DDRA_SDQ22
49 50
DDRA_SDQ18 VSS18 DQ22 DDRA_SDQ23
51 52
DDRA_SDQ19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDRA_SDQ28
DDRA_SDQ24 VSS20 DQ28 DDRA_SDQ29
57 DQ24 DQ29 58
DDRA_SDQ25 59 60
DQ25 VSS21 DDRA_SDQS3# +VREF_CA +1.5V
61 62 DDRA_SDQS3# [5]
DDRA_SDM3 VSS22 DQS#3 DDRA_SDQS3 +VREF_DQ +1.5V
63 64 DDRA_SDQS3 [5]
DM3 DQS3
65 VSS23 VSS24 66

2
DDRA_SDQ26 67 68 DDRA_SDQ30
DQ26 DQ30

2
DDRA_SDQ27 69 70 DDRA_SDQ31 R310
DQ27 DQ31 R48 1K_0402_1%
71 VSS25 VSS26 72
1K_0402_1%

1
+VREF_CA

1
DDRA_CKE0 73 74 DDRA_CKE1 +VREF_DQ
[5] DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 [5]

1000P_0402_50V7K
0.01U_0402_25V7K
75 76
VDD1 VDD2

0.01U_0402_25V7K
DDRA_SMA15

4.7U_0805_10V4Z
77 78
NC1 A15

1000P_0402_50V7K
2 2

4.7U_0805_10V4Z
DDRA_SBS2# 79 80 DDRA_SMA14 1 2 1
[5] DDRA_SBS2# BA2 A14

2
81 82 1 2 1 C235 C485 C838
VDD3 VDD4

2
DDRA_SMA12 83 84 DDRA_SMA11 C84 C85 C10 @ R315
DDRA_SMA9 A12/BC# A11 DDRA_SMA7 @ R49 1K_0402_1%
85 A9 A7 86
87 88 1K_0402_1% 2 1 2
DDRA_SMA8 VDD5 VDD6 DDRA_SMA6 2 1 2
89 90

1
DDRA_SMA5 A8 A6 DDRA_SMA4
91 92

1
A5 A4
93 94
DDRA_SMA3 VDD7 VDD8 DDRA_SMA2
95 A3 A2 96
DDRA_SMA1 97 98 DDRA_SMA0
A1 A0
99 VDD9 VDD10 100
DDRA_CLK0 101 102 DDRA_CLK1
[5] DDRA_CLK0 CK0 CK1 DDRA_CLK1 [5]
DDRA_CLK0# 103 104 DDRA_CLK1#
[5] DDRA_CLK0# CK0# CK1# DDRA_CLK1# [5]
105 106
DDRA_SMA10 VDD11 VDD12 DDRA_SBS1#
107 108 DDRA_SBS1# [5]
DDRA_SBS0# A10/AP BA1 DDRA_SRAS#
[5] DDRA_SBS0# 109 110 DDRA_SRAS# [5]
BA0 RAS#
111 112
DDRA_SWE# VDD13 VDD14 DDRA_SCS0#
113 114 DDRA_SCS0# [5]
[5] DDRA_SWE# DDRA_SCAS# WE# S0# DDRA_ODT0
[5] DDRA_SCAS# 115 116 DDRA_ODT0 [5]
CAS# ODT0
117 VDD15 VDD16 118
DDRA_SMA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 [5]
DDRA_SCS1# 121 122
[5] DDRA_SCS1# S1# NC2
123 124
VDD17 VDD18
125 126 +VREF_CA
NCTEST VREF_CA
127 128
DDRA_SDQ32 VSS27 VSS28 DDRA_SDQ36
129 130
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
131 DQ33 DQ37 132 1
133 134 C89
DDRA_SDQS4# VSS29 VSS30 DDRA_SDM4
[5] DDRA_SDQS4# 135 136
DDRA_SDQS4 DQS#4 DM4 1000P_0402_50V7K
[5] DDRA_SDQS4 137 138
DQS4 VSS31 DDRA_SDQ38 2
139 140
DDRA_SDQ34 VSS32 DQ38 DDRA_SDQ39 +1.5V
141 142
3 DDRA_SDQ35 DQ34 DQ39 3
143 DQ35 VSS33 144
145 146 DDRA_SDQ44 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ40 VSS34 DQ44 DDRA_SDQ45
147 148 2 2 2 2 2 2 2 2 2 2
DDRA_SDQ41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDRA_SDQS5# C87 C840 C88 C839 C836 C833 C831 C837 C834 C832
DDRA_SDM5 VSS36 DQS#5 DDRA_SDQS5 DDRA_SDQS5# [5]
153 154 DDRA_SDQS5 [5]
DM5 DQS5 1 1 1 1 1 1 1 1 1 1
155 156
DDRA_SDQ42 VSS37 VSS38 DDRA_SDQ46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
157 158
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
159 160
DQ43 DQ47
161 VSS39 VSS40 162
DDRA_SDQ48 163 164 DDRA_SDQ52
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
165 166
DQ49 DQ53
167 VSS41 VSS42 168
DDRA_SDQS6# 169 170 DDRA_SDM6 +0.75VS
[5] DDRA_SDQS6# DQS#6 DM6
DDRA_SDQS6 171 172
[5] DDRA_SDQS6 DQS6 VSS43 DDRA_SDQ54
173 174 0.1U_0402_16V4Z
DDRA_SDQ50 VSS44 DQ54 DDRA_SDQ55
175 176 2 2 1
DDRA_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRA_SDQ60 C830 C835 C961
179 180
DDRA_SDQ56 VSS46 DQ60 DDRA_SDQ61 2.2U_0603_6.3V4Z
181 182
DDRA_SDQ57 DQ56 DQ61 1 1 2 R1.0
183 184
DQ57 VSS47 DDRA_SDQS7# 0.1U_0402_16V4Z
185 VSS48 DQS#7 186 DDRA_SDQS7# [5] Place near DIMM1
DDRA_SDM7 187 188 DDRA_SDQS7
DM7 DQS7 DDRA_SDQS7 [5]
189 VSS49 VSS50 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DDRA_SDQ59 DQ58 DQ62 DDRA_SDQ63
193 194
R50 10K_0402_5% DQ59 DQ63
195 VSS51 VSS52 196
1 2 197 198 PAD T10
SA0 EVENT#
+3VS 199 200 SB_SMDAT0 [9,19,21,28]
VDDSPD SDA
201 202 SB_SMCLK0 [9,19,21,28]
SA1 SCL
203 204 +0.75VS
VTT1 VTT2
1

4 R51 4
205 206
+3VS G1 G2
10K_0402_5% FOX_AS0A626-U4RN-7F
ME@
2

1 1
C90 C91

2.2U_0603_6.3V4Z 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
2008/10/06 2010/04/30 Title
DIMM_A Rervse H:4mm Issued Date Deciphered Date
DDRII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 8 of 48
A B C D E
 A B C D E

+VREF_DQ +1.5V +1.5V

JDIMM2
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5
5 DQ0 DQ5 6
DDRB_SDQ1 7 8
DQ1 VSS3 DDRB_SDQS0#
9 10 DDRB_SDQS0# [5]
DDRB_SDM0 VSS4 DQS#0 DDRB_SDQS0
11 DM0 DQS0 12 DDRB_SDQS0 [5]
13 14 DDRB_SDQ[0..63]
DDRB_SDQ2 VSS5 VSS6 DDRB_SDQ6 DDRB_SDQ[0..63] [5]
15 DQ2 DQ6 16
DDRB_SDQ3 17 18 DDRB_SDQ7 DDRB_SDM[0..7]
DQ3 DQ7 DDRB_SDM[0..7] [5]
19 VSS7 VSS8 20
1 DDRB_SDQ8 DDRB_SDQ12 1
21 DQ8 DQ12 22
DDRB_SDQ9 23 24 DDRB_SDQ13
DQ9 DQ13 DDRB_SMA[0..15]
25 VSS9 VSS10 26 DDRB_SMA[0..15] [5]
DDRB_SDQS1# 27 28 DDRB_SDM1
[5] DDRB_SDQS1# DDRB_SDQS1 DQS#1 DM1 MEM_MB_RST#
[5] DDRB_SDQS1 29 30 MEM_MB_RST# [5]
DQS1 RESET#
31 VSS11 VSS12 32
DDRB_SDQ10 33 34 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRB_SDQ16 39 40 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 DQ17 DQ21 42
43 44
DDRB_SDQS2# VSS15 VSS16 DDRB_SDM2
[5] DDRB_SDQS2# 45 DQS#2 DM2 46
DDRB_SDQS2 47 48
[5] DDRB_SDQS2 DQS2 VSS17 DDRB_SDQ22
49 50
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 52
DDRB_SDQ19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDRB_SDQ28
DDRB_SDQ24 VSS20 DQ28 DDRB_SDQ29
57 DQ24 DQ29 58
DDRB_SDQ25 59 60
DQ25 VSS21 DDRB_SDQS3#
61 62 DDRB_SDQS3# [5]
DDRB_SDM3 VSS22 DQS#3 DDRB_SDQS3
63 64 DDRB_SDQS3 [5]
DM3 DQS3
65 VSS23 VSS24 66
DDRB_SDQ26 67 68 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31
69 70
DQ27 DQ31
71 VSS25 VSS26 72

DDRB_CKE0 73 74 DDRB_CKE1
[5] DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 [5]
75 76
VDD1 VDD2 DDRB_SMA15
77 78
2 DDRB_SBS2# NC1 A15 DDRB_SMA14 2
[5] DDRB_SBS2# 79 BA2 A14 80
81 82
DDRB_SMA12 VDD3 VDD4 DDRB_SMA11
83 84
DDRB_SMA9 A12/BC# A11 DDRB_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6 +VREF_DQ +VREF_CA
DDRB_SMA5 A8 A6 DDRB_SMA4
91 A5 A4 92
93 94
DDRB_SMA3 VDD7 VDD8 DDRB_SMA2 +VREF_DQ +VREF_CA
95 A3 A2 96
DDRB_SMA1 97 98 DDRB_SMA0
A1 A0

1000P_0402_50V7K

1000P_0402_50V7K
99 VDD9 VDD10 100

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0805_10V4Z

4.7U_0805_10V4Z
DDRB_CLK0 101 102 DDRB_CLK1
[5] DDRB_CLK0 CK0 CK1 DDRB_CLK1 [5]
DDRB_CLK0# 103 104 DDRB_CLK1# 1 1 1 1 1 1
[5] DDRB_CLK0# CK0# CK1# DDRB_CLK1# [5]
105 106 C92 C93 C852 C486 C487 C844
DDRB_SMA10 VDD11 VDD12 DDRB_SBS1#
107 108 DDRB_SBS1# [5]
DDRB_SBS0# A10/AP BA1 DDRB_SRAS#
[5] DDRB_SBS0# 109 110 DDRB_SRAS# [5]
BA0 RAS# 2 2 2 2 2 2
111 112
DDRB_SWE# VDD13 VDD14 DDRB_SCS0#
113 114 DDRB_SCS0# [5]
[5] DDRB_SWE# DDRB_SCAS# WE# S0# DDRB_ODT0
[5] DDRB_SCAS# 115 116 DDRB_ODT0 [5]
CAS# ODT0
117 VDD15 VDD16 118
DDRB_SMA13 119 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 [5]
DDRB_SCS1# 121 122
[5] DDRB_SCS1# S1# NC2
123 124
VDD17 VDD18
125 126 +VREF_CA
NCTEST VREF_CA
127 128
DDRB_SDQ32 VSS27 VSS28 DDRB_SDQ36
129 130
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
131 DQ33 DQ37 132 1
133 134 C94
DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4 1000P_0402_50V7K
[5] DDRB_SDQS4# 135 136
DDRB_SDQS4 DQS#4 DM4
[5] DDRB_SDQS4 137 138
DQS4 VSS31 DDRB_SDQ38 2
139 140
DDRB_SDQ34 VSS32 DQ38 DDRB_SDQ39
141 142
3 DDRB_SDQ35 DQ34 DQ39 3
143 DQ35 VSS33 144
145 146 DDRB_SDQ44
DDRB_SDQ40 VSS34 DQ44 DDRB_SDQ45
147 148
DDRB_SDQ41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDRB_SDQS5#
DDRB_SDM5 VSS36 DQS#5 DDRB_SDQS5 DDRB_SDQS5# [5]
153 154 +1.5V
DM5 DQS5 DDRB_SDQS5 [5]
155 156
DDRB_SDQ42 VSS37 VSS38 DDRB_SDQ46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
157 158
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
159 160 2 2 2 2 2 2 2 2 2 2
DQ43 DQ47
161 VSS39 VSS40 162
DDRB_SDQ48 163 164 DDRB_SDQ52 C846 C847 C851 C848 C854 C849 C842 C850 C845 C853
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 166
DQ49 DQ53 1 1 1 1 1 1 1 1 1 1
167 VSS41 VSS42 168
DDRB_SDQS6# 169 170 DDRB_SDM6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
[5] DDRB_SDQS6# DQS#6 DM6
DDRB_SDQS6 171 172
[5] DDRB_SDQS6 DQS6 VSS43 DDRB_SDQ54
173 174
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 176
DDRB_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRB_SDQ60
179 180
DDRB_SDQ56 VSS46 DQ60 DDRB_SDQ61 +0.75VS
181 182
DDRB_SDQ57 DQ56 DQ61 +1.5V
183 184
DQ57 VSS47 DDRB_SDQS7# 0.1U_0402_16V4Z
185 VSS48 DQS#7 186 DDRB_SDQS7# [5]
DDRB_SDM7 187 188 DDRB_SDQS7 2 2 1 1
DM7 DQS7 DDRB_SDQS7 [5]
189 VSS49 VSS50 190
DDRB_SDQ58 191 192 DDRB_SDQ62 C843 C841 C925 + C86 @
DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63 2.2U_0603_6.3V4Z 330U_D2E_2.5VM_R9M
193 194
R52 10K_0402_5% DQ59 DQ63 1 1 2
195 VSS51 VSS52 196
1 2 197 198 0.1U_0402_16V4Z R1.0 2
SA0 EVENT# PAD T11
+3VS 199 200 SB_SMDAT0 [8,19,21,28]
VDDSPD SDA
201
SA1 SCL
202 SB_SMCLK0 [8,19,21,28] Place near DIMM2
203 204 +0.75VS
VTT1 VTT2
1

4 R53 4
205 206
G1 G2
10K_0402_5% FOX_AS0A626-U8RN-7F
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

DIMM_B Reverse H:8mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 9 of 48
A B C D E
 A B C D E

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
[13] PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] [13]
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
[13] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] [13]

1 1

UMA HDMI
R1.0

PCIE_MTX_GRX_P0 C488 1 2 0.1U_0402_16V7K UMA_HDMI_P0 [26]

PCIE_MTX_GRX_N0 C489 1 2 0.1U_0402_16V7K HDMI_UMA@
PCIE_MTX_GRX_P1 UMA_HDMI_N0 [26]
HDMI_UMA@ C491 1 2 0.1U_0402_16V7K
PCIE_MTX_GRX_N1 UMA_HDMI_P1 [26]
C490 1 2 0.1U_0402_16V7K HDMI_UMA@
PCIE_MTX_GRX_P2 UMA_HDMI_N1 [26]
HDMI_UMA@ C497 1 2 0.1U_0402_16V7K UMA_HDMI_P2 [26]
PCIE_MTX_GRX_N2 C500 1 2 0.1U_0402_16V7K HDMI_UMA@
PCIE_MTX_GRX_P3 UMA_HDMI_N2 [26]
HDMI_UMA@ C499 1 2 0.1U_0402_16V7K UMA_HDMI_P3 [26]
PCIE_MTX_GRX_N3 C498 1 2 0.1U_0402_16V7K HDMI_UMA@
UMA_HDMI_N3 [26]
HDMI_UMA@

PCIE_GTX_C_MRX_P0
U3B
PCIE_MTX_GRX_P0
Cap close NB C95 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
D4 GFX_RX0P GFX_TX0P A5 2DIS@
PCIE_GTX_C_MRX_N0 C4 PART 2 OF 6 B5 PCIE_MTX_GRX_N0 C96 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_GTX_C_MRX_P1 GFX_RX0N GFX_TX0N PCIE_MTX_GRX_P1 C97 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
A3 A4 2DIS@
PCIE_GTX_C_MRX_N1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C98 PCIE_MTX_C_GRX_N1
B3 GFX_RX1N GFX_TX1N B4 1 2DIS@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P2 C2 C3 PCIE_MTX_GRX_P2 C99 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_GTX_C_MRX_N2 GFX_RX2P GFX_TX2P PCIE_MTX_GRX_N2 C100 1 PCIE_MTX_C_GRX_N2
C1 B2 2DIS@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C101 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 2DIS@
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C102 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C103 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
G5 E2 2DIS@
PCIE_GTX_C_MRX_N4 GFX_RX4P GFX_TX4P PCIE_MTX_GRX_N4 C104 1 PCIE_MTX_C_GRX_N4 H_CADOP[0..15] H_CADIP[0..15]
G6 E1 2DIS@ 0.1U_0402_16V7K
[4] H_CADOP[0..15] H_CADIP[0..15] [4]
2 PCIE_GTX_C_MRX_P5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C105 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5 2
H5 GFX_RX5P GFX_TX5P F4 2DIS@
PCIE_GTX_C_MRX_N5 H6 F3 PCIE_MTX_GRX_N5 C106 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5 H_CADON[0..15] H_CADIN[0..15]
PCIE_GTX_C_MRX_P6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 [4] H_CADON[0..15] H_CADIN[0..15] [4]
J6 F1 C107 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 GFX_RX6P GFX_TX6P PCIE_MTX_GRX_N6 C108 1 PCIE_MTX_C_GRX_N6
J5 GFX_RX6N GFX_TX6N F2 2DIS@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P7 J7 H4 PCIE_MTX_GRX_P7 C109 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C110 1 PCIE_MTX_C_GRX_N7
J8 H3 2DIS@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P8 GFX_RX7N GFX_TX7N PCIE_MTX_GRX_P8 C111 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
L5 GFX_RX8P GFX_TX8P H1 2DIS@ U3A
PCIE_GTX_C_MRX_N8 L6 H2 PCIE_MTX_GRX_N8 C112 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 H_CADOP0 Y25 D24 H_CADIP0
PCIE_GTX_C_MRX_P9 GFX_RX8N GFX_TX8N PCIE_MTX_GRX_P9 C113 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9 H_CADON0 HT_RXCAD0P HT_TXCAD0P H_CADIN0
M8 GFX_RX9P GFX_TX9P J2 2DIS@ Y24 HT_RXCAD0N PART 1 OF 6 HT_TXCAD0N D25
PCIE_GTX_C_MRX_N9 L8 J1 PCIE_MTX_GRX_N9 C114 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9 H_CADOP1 V22 E24 H_CADIP1
PCIE_GTX_C_MRX_P10 GFX_RX9N GFX_TX9N PCIE_MTX_GRX_P10 C115 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 H_CADON1 HT_RXCAD1P HT_TXCAD1P H_CADIN1
2DIS@
PCIE I/F GFX

P7 GFX_RX10P GFX_TX10P K4 V23 HT_RXCAD1N HT_TXCAD1N E25

PCIE_GTX_C_MRX_N10 M7 K3 PCIE_MTX_GRX_N10 C116 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 H_CADOP2 V25 F24 H_CADIP2
PCIE_GTX_C_MRX_P11 GFX_RX10N GFX_TX10N PCIE_MTX_GRX_P11 C117 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11 H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
P5 GFX_RX11P GFX_TX11P K1 2DIS@ V24 HT_RXCAD2N HT_TXCAD2N F25
PCIE_GTX_C_MRX_N11 M5 K2 PCIE_MTX_GRX_N11 C118 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11 H_CADOP3 U24 F23 H_CADIP3
PCIE_GTX_C_MRX_P12 GFX_RX11N GFX_TX11N PCIE_MTX_GRX_P12 C119 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
R8 M4 2DIS@ U25 F22
PCIE_GTX_C_MRX_N12 GFX_RX12P GFX_TX12P PCIE_MTX_GRX_N12 C120 1 PCIE_MTX_C_GRX_N12 H_CADOP4 HT_RXCAD3N HT_TXCAD3N H_CADIP4
P8 M3 2DIS@ 0.1U_0402_16V7K T25 H23
PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13 C121 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13 H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
R6 M1 2DIS@ T24 H22
PCIE_GTX_C_MRX_N13 GFX_RX13P GFX_TX13P PCIE_MTX_GRX_N13 C122 1 PCIE_MTX_C_GRX_N13 H_CADOP5 HT_RXCAD4N HT_TXCAD4N H_CADIP5
2DIS@ 0.1U_0402_16V7K

HYPER TRANSPORT CPU I/F

R5 M2 P22 J25
PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14 C123 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P4 N2 2DIS@ P23 J24
PCIE_GTX_C_MRX_N14 GFX_RX14P GFX_TX14P PCIE_MTX_GRX_N14 C124 1 PCIE_MTX_C_GRX_N14 H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6
P3 GFX_RX14N GFX_TX14N N1 2DIS@ 0.1U_0402_16V7K P25 HT_RXCAD6P HT_TXCAD6P K24
PCIE_GTX_C_MRX_P15 T4 P1 PCIE_MTX_GRX_P15 C125 1 2DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15 H_CADON6 P24 K25 H_CADIN6
PCIE_GTX_C_MRX_N15 GFX_RX15P GFX_TX15P PCIE_MTX_GRX_N15 C126 1 PCIE_MTX_C_GRX_N15 H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
T3 P2 2DIS@ 0.1U_0402_16V7K N24 K23
GFX_RX15N GFX_TX15N H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
N25 K22
HT_RXCAD7N HT_TXCAD7N
AE3 AC1
GPP_RX0P GPP_TX0P H_CADOP8 H_CADIP8
AD4 AC2 AC24 F21
GPP_RX0N GPP_TX0N PCIE_ITX_PRX_P1 C201 1 0.1U_0402_16V7K H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8
[28] PCIE_PTX_C_IRX_P1 AE2 AB4 2 PCIE_ITX_C_PRX_P1 [28] AC25 G21
GPP_RX1P GPP_TX1P PCIE_ITX_PRX_N1 H_CADOP9 HT_RXCAD8N HT_TXCAD8N H_CADIP9
[28] PCIE_PTX_C_IRX_N1 AD3 GPP_RX1N GPP_TX1N AB3 C200 1 2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_N1 [28] WLAN AB25 HT_RXCAD9P HT_TXCAD9P G20
AD1 AA2 PCIE_ITX_PRX_P2 C482 1 2 0.1U_0402_16V7K H_CADON9 AB24 H21 H_CADIN9
[29] PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_PRX_N2 PCIE_ITX_C_PRX_P2 [29] H_CADOP10 HT_RXCAD9N HT_TXCAD9N H_CADIP10
[29] PCIE_PTX_C_IRX_N2 AD2
GPP_RX2N PCIE I/F GPP GPP_TX2N
AA1 C481 1 2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_N2 [29] GLAN AA24
HT_RXCAD10P HT_TXCAD10P
J20
V5 Y1 PCIE_ITX_PRX_P3 C484 1 2 3G@ 0.1U_0402_16V7K H_CADON10 AA25 J21 H_CADIN10
[28] PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_PRX_N3 PCIE_ITX_C_PRX_P3 [28] H_CADOP11 HT_RXCAD10N HT_TXCAD10N H_CADIP11
[28] PCIE_PTX_C_IRX_N3 W6
GPP_RX3N GPP_TX3N
Y2 C483 1 2 3G@ 0.1U_0402_16V7K PCIE_ITX_C_PRX_N3 [28] WWAN Y22
HT_RXCAD11P HT_TXCAD11P
J18
U5 Y4 H_CADON11 Y23 K17 H_CADIN11
3 GPP_RX4P GPP_TX4P H_CADOP12 HT_RXCAD11N HT_TXCAD11N H_CADIP12 3
U6 GPP_RX4N GPP_TX4N Y3 W21 HT_RXCAD12P HT_TXCAD12P L19
U8 V1 H_CADON12 W20 J19 H_CADIN12
GPP_RX5P GPP_TX5P H_CADOP13 HT_RXCAD12N HT_TXCAD12N H_CADIP13
U7 V2 V21 M19
GPP_RX5N GPP_TX5N H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
[20] SB_RX0P AA8 AD7 SB_TX0P_C C133 1 2 0.1U_0402_16V7K H_CADOP14 U20 M21 H_CADIP14
SB_RX0P SB_TX0P SB_TX0N_C SB_TX0P [20] H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
[20] SB_RX0N Y8 AE7 C134 1 2 0.1U_0402_16V7K U21 P21
SB_RX0N SB_TX0N SB_TX0N [20] HT_RXCAD14N HT_TXCAD14N
[20] SB_RX1P AA7 AE6 SB_TX1P_C C135 1 2 0.1U_0402_16V7K H_CADOP15 U19 P18 H_CADIP15
SB_RX1P SB_TX1P SB_TX1N_C SB_TX1P [20] H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
[20] SB_RX1N Y7 AD6 C136 1 2 0.1U_0402_16V7K U18 M18
SB_RX1N SB_TX1N SB_TX2P_C SB_TX1N [20] HT_RXCAD15N HT_TXCAD15N
[20] SB_RX2P AA5 PCIE I/F SB AB6 C137 1 2 0.1U_0402_16V7K
SB_RX2P SB_TX2P SB_TX2P [20]
[20] SB_RX2N AA6 AC6 SB_TX2N_C C138 1 2 0.1U_0402_16V7K T22 H24
SB_RX2N SB_TX2N SB_TX3P_C SB_TX2N [20] [4] H_CLKOP0 HT_RXCLK0P HT_TXCLK0P H_CLKIP0 [4]
[20] SB_RX3P W5 AD5 C139 1 2 0.1U_0402_16V7K T23 H25
SB_RX3P SB_TX3P SB_TX3P [20] [4] H_CLKON0 HT_RXCLK0N HT_TXCLK0N H_CLKIN0 [4]
[20] SB_RX3N Y5 AE5 SB_TX3N_C C140 1 2 0.1U_0402_16V7K AB23 L21
SB_RX3N SB_TX3N SB_TX3N [20] [4] H_CLKOP1 HT_RXCLK1P HT_TXCLK1P H_CLKIP1 [4]
[4] H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 [4]
AC8 R59 1 2 1.27K_0402_1%
PCE_CALRP(PCE_BCALRP) R58 2K_0402_1% H_CTLOP0 H_CTLIP0
PCE_CALRN(PCE_BCALRN) AB8 1 2 +1.1VS [4] H_CTLOP0 M22 HT_RXCTL0P HT_TXCTL0P M24 H_CTLIP0 [4]
H_CTLON0 M23 M25 H_CTLIN0
[4] H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 [4]
RS880M_FCBGA528 H_CTLOP1 R21 P19 H_CTLIP1
[4] H_CTLOP1 H_CTLON1 HT_RXCTL1P HT_TXCTL1P H_CTLIN1 H_CTLIP1 [4]
[4] H_CTLON1 R20 R18 H_CTLIN1 [4]
HT_RXCTL1N HT_TXCTL1N
RS880 A11(SA000032710) 1 R60 2 HT_RXCALP C23 B24 HT_TXCALP 1 R61 2
HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 B25
301_0402_1% HT_RXCALN HT_TXCALN 301_0402_1%
Place within 1" layout 1:2 RS880M_FCBGA528 Place within 1" layout 1:2

RS880 A11(SA000032710)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880-HT/PCIE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 10 of 48
A B C D E
 A B C D E

+1.8VS +1.8VS +1.8VS

0.1U_0402_16V4Z +1.8VS

2
1 2
R417 R63 U4

5
+1.1VS +NB_PLLVDD @ C684 2.2K_0402_5% NC7SZ08P5X_NL_SC70-5

5
L2 300_0402_5% NB_PWRGD 2

P
B
1 2 2 4 NB_PWRGD_R

P
1

1
+3VS B NB_LDTSTOP# Y
1 1 4 [6,21,34] SB_PWRGD 1
Y A

G
FBMA-L11-160808-221LMT 0603 L3 1
[6,20] LDT_STOP# A

G
C141 C142 1 2 C679 C144 C143 U8 @

3
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z

+AVDD1
1 1 1

3
1 2 2 FBMA-L11-160808-221LMT 0603 NC7SZ08P5X_NL_SC70-5 1

2.2U_0603_6.3V4Z
2
22U_0805_6.3V6M 2 2 1 2
1U_0402_6.3V4Z R64 @ 0_0402_5%
+1.8VS
L4 AMD suggest
+1.8VS +NB_HTPVDD 1 2 +AVDDDI
L5 1

125mA
1 2 FBMA-L11-160808-221LMT 0603
1 1 C145
FBMA-L11-160808-221LMT 0603 0.1U_0402_16V4Z
C146 C147 2 U3C
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F12 A22 GMCH_TXOUT0+ [27]
2 2 +1.8VS AVDD1(NC) TXOUT_L0P(NC)
20mA E12
AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC)
B22 GMCH_TXOUT0- [27]
F14 A21 GMCH_TXOUT1+ [27]
L6 AVDDDI(NC) TXOUT_L1P(NC)
+AVDDQ
4mA G15 AVSSDI(NC) TXOUT_L1N(NC) B21 GMCH_TXOUT1- [27]
1 2 H15 B20 GMCH_TXOUT2+ [27]
AVDDQ(NC) TXOUT_L2P(NC)
1 1 H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 GMCH_TXOUT2- [27]
FBMA-L11-160808-221LMT 0603 A19
C148 C149 TXOUT_L3P(NC)
E17 B19
+1.8VS +VDDA18HTPLL 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
F17

CRT/TVOUT
L7 2 2 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
1 2 TXOUT_U0N(NC) A18
1 1 1 UMA@ 2 GMCH_CRT_R GMCH_CRT_R G18 A17
[25] GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
FBMA-L11-160808-221LMT 0603 R87 140_0402_1% G17 B17 L8
C150 C151 GMCH_CRT_G GMCH_CRT_G REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) +VDDLTP18
1 UMA@ 2 [25] GMCH_CRT_G E18 D20 1 2 +1.8VS
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z R88 150_0402_1% GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 D21 1 1
2 2 GMCH_CRT_B GMCH_CRT_B GREENb(NC) TXOUT_U2N(NC)
1 UMA@ 2 [25] GMCH_CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18 FBMA-L11-160808-221LMT 0603
R89 150_0402_1% F19 D19 C152 C153
BLUEb(NC) TXOUT_U3N(NC) 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
GMCH_CRT_HSYNC A11 B16 2 2
2 [12,25] GMCH_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) GMCH_TXCLK+ [27] 2
GMCH_CRT_VSYNC B11 A16
[12,25] GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) GMCH_TXCLK- [27]
GMCH_CRT_CLK F8 D16
+1.8VS +VDDA18PCIEPLL [25] GMCH_CRT_CLK GMCH_CRT_DATA DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
[25] GMCH_CRT_DATA E8 D17
L9 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
1 2 1 2 DAC_RSET 10mil G14 15mA L10
R65 715_0402_1% DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLT18
1 1
+NB_PLLVDD
65mA VDDLTP18(NC)
A13 1 2 +1.8VS
FBMA-L11-160808-221LMT 0603 +NB_PLLVDD A12 B13 1 1 BLM18AG601SN1D_2P
C154 C155 +NB_HTPVDD 20mA PLLVDD(NC) VSSLTP18(NC) C156
+NB_HTPVDD D14
PLLVDD18(NC) 300mA +VDDLT18
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z B12 A15 0.1U_0402_16V4Z C157

LVTM
2 2 PLLVSS(NC) VDDLT18_1(NC) 4.7U_0805_10V4Z
20mA B15

PLL PWR
VDDLT18_2(NC) 2 2
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
120mA VDDLT33_2(NC)
B14
+VDDA18PCIEPLL D7 VDDA18PCIEPLL1
E7 C14
VDDA18PCIEPLL2 VSSLT1(VSS)
D15
R66 NB_RESET# VSSLT2(VSS)
[12,13,20,28,29,34] PLT_RST# 1 2 0_0402_5% D8 C16
NB_PWRGD_R A10 SYSRESETb VSSLT3(VSS)
[21] NB_PWRGD 1 2 C18
R67 0_0402_5% NB_LDTSTOP# POWERGOOD VSSLT4(VSS)
C10 C20
NB_ALLOW_LDTSTOP C12 LDTSTOPb VSSLT5(VSS)
2 1 E20

PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R68 300_0402_5% C22
CLK_NBHT VSSLT7(VSS)
[19] CLK_NBHT C25
R536 1 EXT@ CLK_NBHT# HT_REFCLKP
[19] CLK_NB_14.318M 2 0_0402_5% [19] CLK_NBHT# C24
HT_REFCLKN
R456 1 INT@ 2 0_0402_5% NB_REFCLK_P E11
[20] NB_DISP_CLKP REFCLK_P/OSCIN(OSCIN)

CLOCKs
R439 1 INT@ 2 0_0402_5% NB_REFCLK_N F11 E9
[20] NB_DISP_CLKN REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) GMCH_ENVDD [27]
F7 GMCH_INVT_PWM [27]
CLK_NBGFX LVDS_BLON(PCE_RCALRP) ENBKL
+1.1VS 1 EXT@ 2 1 EXT@ 2 [19] CLK_NBGFX T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 R76 1 UMA@ 2 0_0402_5%
+3VS R69 R70 CLK_NBGFX# T1
[19] CLK_NBGFX# GFX_REFCLKN

1
1
4.7K_0402_5% 4.7K_0402_5% DIS@
2 INT@ 1 U1 [14] VGA_ENBKL 1 2 ENBKL [34]
R77 GMCH_LCD_CLK GPP_REFCLKP
1 2 4.7K_0402_5% CLK_NBGFX R504 2 INT@4.7K_0402_5%
1 U2 R73 @ R74 @ R102
R506 4.7K_0402_5% GPP_REFCLKN 4.7K_0402_5% 4.7K_0402_5% 0_0402_5%
3 USE INT CLK GEN. PD 4.7k PD. 3
R78 1 2 4.7K_0402_5% GMCH_LCD_DATA [19] CLK_SBLINK_BCLK
CLK_SBLINK_BCLK V4

2
2
CLK_SBLINK_BCLK# GPPSB_REFCLKP(SB_REFCLKP) R75 2
[19] CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN) 1
R79 1 @ 2 4.7K_0402_5% GMCH_CRT_CLK 4.7K_0402_5%
GMCH_LCD_CLK B9
[27] GMCH_LCD_CLK I2C_CLK
R80 @ 2 4.7K_0402_5% GMCH_CRT_DATA GMCH_LCD_DATA 1 R642
1 [27] GMCH_LCD_DATA A9
B8
I2C_DATA MIS. TMDS_HPD(NC)
D9
D10
2
HDMI_UMA@ 0_0402_5%
HDMI_DET [14,26]
DDC_DATA0/AUX0N(NC) HPD(NC)
R1.0 HDMI_UMA@ A8
DDC_CLK0/AUX0P(NC)
R1.0 To SB
GMCH_HDMI_CLK 1 R641 2 0_0402_5% GMCH_HDMI_CLK_R1 B7 D12 1 R81 2 0_0402_5%
[26] GMCH_HDMI_CLK DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) SUS_STAT# [21]
GMCH_HDMI_DATA 1 R640 2 0_0402_5% GMCH_HDMI_DATA_R1 A7 Strap pin
[26] GMCH_HDMI_DATA DDC_DATA1/AUX1N(NC) SUS_STAT_R# [12]
HDMI_UMA@ AE8
POWER_SEL THERMALDIODE_P
[45] POWER_SEL B10 STRP_DATA THERMALDIODE_N AD8
1 R82 2
2K_0402_5% G11 D13 1 2
RSVD TESTMODE
EMI R84
1 R85 2 C8 1.8K_0402_5%
@ R86 @ C158 150_0402_1% AUX_CAL(NC)
CLK_NB_14.318M 1 2 1 2 RS880M_FCBGA528
100_0402_5% 100P_0402_25V8K
RS880 A11(SA000032710)

+1.8VS
1

R90
1K_0402_5%
R91 0_0402_5%
1 2 NB_ALLOW_LDTSTOP
[20] ALLOW_LDTSTOP
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 VEDIO/CLK GEN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 11 of 48
A B C D E
 A B C D E

1.3A L11 0.1U_0402_16V4Z 1U_0402_6.3V4Z R1.0

2 1 +VDDHT L28 @
+1.1VS U3F
1 2
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 FBMA-L11-201209-221LMA30T_0805 A25 A2
VSSAHT1 VSSAPCIE1

600mA
L12 D23 PART 6/6 B1
C165 C166 C159 C167 VSSAHT2 VSSAPCIE2
1 2 +1.1VS E22 D3
FBMA-L11-201209-221LMA30T_0805 VSSAHT3 VSSAPCIE3
G22 VSSAHT4 VSSAPCIE4 D5
2 2 2 2 U3E
2.5A +VDDA11PCIE
G24
VSSAHT5 VSSAPCIE5
E4
4.7U_0805_10V4Z 0.1U_0402_16V4Z J17 A6 C160 1 2 10U_0805_10V4Z G25 G1
1 VDDHT_1 VDDPCIE_1 C162 VSSAHT6 VSSAPCIE6 1
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1 2 10U_0805_10V4Z H19 VSSAHT7 VSSAPCIE7 G2
L16 VDDHT_3 VDDPCIE_3 C6 J22 VSSAHT8 VSSAPCIE8 G4
L13 1U_0402_6.3V4Z M16 D6 L17 H7
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C163 VSSAHT9 VSSAPCIE9
2 1 P16 E6 1 2 4.7U_0805_10V4Z L22 J4
VDDHT_5 VDDPCIE_5 VSSAHT10 VSSAPCIE10
R16 F6 L24 R7
FBMA-L11-201209-221LMA30T_0805 VDDHT_6 VDDPCIE_6 C168 VSSAHT11 VSSAPCIE11
1 1 1 1 T16 VDDHT_7 VDDPCIE_7 G7 1 2 1U_0402_6.3V4Z L25 VSSAHT12 VSSAPCIE12 L1
700mA H8 C171 1 2 1U_0402_6.3V4Z M20 L2
C164 C169 C170 C161 VDDPCIE_8 VSSAHT13 VSSAPCIE13
H18 VDDHTRX_1 VDDPCIE_9 J9 N22 VSSAHT14 VSSAPCIE14 L4
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 P20 VSSAHT15 VSSAPCIE15 L7
2 2 2 2 C172
F20 M9 1 2 0.1U_0402_16V4Z R19 M6
4.7U_0805_10V4Z 0.1U_0402_16V4Z VDDHTRX_3 VDDPCIE_11 C173 0.1U_0402_16V4Z VSSAHT16 VSSAPCIE16
E21 VDDHTRX_4 VDDPCIE_12 L9 R22 VSSAHT17 VSSAPCIE17 N4
D22 P9 R24 P6
VDDHTRX_5 VDDPCIE_13 VSSAHT18 VSSAPCIE18
B23 VDDHTRX_6 VDDPCIE_14 R9 R25 VSSAHT19 VSSAPCIE19 R1
A23 T9 H20 R2
L14 VDDHTRX_7 VDDPCIE_15 VSSAHT20 VSSAPCIE20
680mA VDDPCIE_16
V9 U22
VSSAHT21 VSSAPCIE21
R4
+1.1VS 2 1 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX AE25 U9 V19 V7
VDDHTTX_1 VDDPCIE_17 VSSAHT22 VSSAPCIE22
AD24 W22 U4

GROUND
FBMA-L11-201209-221LMA30T_0805 VDDHTTX_2 VSSAHT23 VSSAPCIE23
2 1 1 1 1 1 AC23 K12 W24 V8
@ VDDHTTX_3 VDDC_1 VSSAHT24 VSSAPCIE24
AB22 VDDHTTX_4 VDDC_2 J14 W25 VSSAHT25 VSSAPCIE25 V6
C261 C174 C175 C176 C177 C178 AA21 U16 Y21 W1
VDDHTTX_5 VDDC_3 VSSAHT26 VSSAPCIE26
Y20 J11 AD25 W2
1 2 2 2 2 2 W19
VDDHTTX_6
VDDHTTX_7
VDDC_4
VDDC_5
K15 12A +NB_CORE VSSAHT27 VSSAPCIE27
VSSAPCIE28
W4

POWER
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 L12 W7
VDDHTTX_8 VDDC_6 VSS11 VSSAPCIE29
U17 VDDHTTX_9 VDDC_7 L14 M14 VSS12 VSSAPCIE30 W8
T17 L11 N13 Y6
VDDHTTX_10 VDDC_8 VSS13 VSSAPCIE31
R17 VDDHTTX_11 VDDC_9 M13 P12 VSS14 VSSAPCIE32 AA4
P17 M15 P15 AB5
VDDHTTX_12 VDDC_10 VSS15 VSSAPCIE33
M17 N12 R11 AB1
VDDHTTX_13 VDDC_11 VSS16 VSSAPCIE34

C189
C191

C182

C187

C193

C194

C180

C188

C183

C195

C184

C196
L15 700mA N14 1 R14 AB7
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS17 VSSAPCIE35
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 T12 VSS18 VSSAPCIE36 AC3
FBMA-L11-201209-221LMA30T_0805 P10 P13 + R1.0 U14 AC4
VDDA18PCIE_2 VDDC_14 VSS19 VSSAPCIE37
1 1 1 1 1 1 K10 P14 U11 AE1
2 VDDA18PCIE_3 VDDC_15 VSS20 VSSAPCIE38

220U_D2_4VM_R15
2

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 U15 VSS21 VSSAPCIE39 AE4
C181 C179 C192 C185 C190 C186 L10 R15 2 2 2 2 2 2 2 2 2 2 2 2 V12 AB2
4.7U_0805_10V4Z VDDA18PCIE_5 VDDC_17 VSS22 VSSAPCIE40
W9 T11 W11
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS23
H9 VDDA18PCIE_7 VDDC_19 T15 W15 VSS24
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 AC12 AE14
VDDA18PCIE_8 VDDC_20 VSS25 VSS1
R10 T14 AA14 D11
VDDA18PCIE_9 VDDC_21 VSS26 VSS2
Y9 VDDA18PCIE_10 VDDC_22 J16 Y18 VSS27 VSS3 G8
AA9
VDDA18PCIE_11 23mA AB11
VSS28 VSS4
E14
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 AB15 VSS29 VSS5 E15
AD9 AA11 AB17 J15
VDDA18PCIE_13 VDD_MEM2(NC) VSS30 VSS6
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11 AB19 VSS31 VSS7 J12
U10 AD10 AE20 K14
VDDA18PCIE_15 VDD_MEM4(NC) VSS32 VSS8
10mA VDD_MEM5(NC) AB10 AB21 VSS33 VSS9 M11
+1.8VS F9 AC10 K11 L15
VDD18_1 VDD_MEM6(NC) VSS34 VSS10
G9
VDD18_2 60mA RS880M_FCBGA528
AE11 H11 +3VS
VDD18_MEM1(NC) VDD33_1(NC)
AD11 H12
VDD18_MEM2(NC) VDD33_2(NC)
5mA 1 1 RS880 A11(SA000032710)
1 RS880M_FCBGA528
C197 C198 C199
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RS880 A11(SA000032710) 2 2
2

3 U3D 3

PAR 4 OF 6
Side port and Strap setting AB12
AE16
V11
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
AA18
AA20
AA19
AE15 Y19
MEM_A3(NC) MEM_DQ3/DVO_D0(NC)
AA12 V17
MEM_A4(NC) MEM_DQ4(NC)
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb AB16
MEM_A5(NC) MEM_DQ5/DVO_D1(NC)
AA17
Debug Mode AB14
MEM_A6(NC) MEM_DQ6/DVO_D2(NC)
AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
[11,25] GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC) AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
R92 3K_0402_5% 1 : Disable AD15 AD19
MEM_A9(NC) MEM_DQ9/DVO_D5(NC)
2 1 AC16 AE22

SBD_MEM/DVO_I/F
R93 @ 3K_0402_5% 0 : Enable AE13
MEM_A10(NC) MEM_DQ10/DVO_D6(NC)
AC18
MEM_A11(NC) MEM_DQ11/DVO_D7(NC)
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 AD22
MEM_A13(NC) MEM_DQ13/DVO_D9(NC)
AC22
MEM_DQ14/DVO_D10(NC)
DFT_GPIO1: LOAD_EEPROM_STRAPS AD16
MEM_BA0(NC) MEM_DQ15/DVO_D11(NC)
AD21
Load EEPROM Strap AE17
MEM_BA1(NC)
Selects Loading of STRAPS from EPROM AD17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC)
Y17
D1 @ 1 : Bypass the loading of EEPROM straps and use Hardware Default Values W18
CH751H-40PT_SOD323-2 MEM_DQS0N/DVO_IDCKN(NC)
0 : I2C Master can load strap values from EEPROM if connected, or use W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
[11] SUS_STAT_R# 2 1 PLT_RST# [11,13,20,28,29,34] Y12 AE21
default values if not connected MEM_CASb(NC) MEM_DQS1N(NC)
AD18 MEM_WEb(NC)
2 1 AB13 W17
R264 @ 3K_0402_5% MEM_CSb(NC) MEM_DM0(NC)
AB18 AE19
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
V14 MEM_ODT(NC) 15mA
AE23 +1.8VS
IOPLLVDD18(NC)
V15 AE24 +1.1VS
MEM_CKP(NC) IOPLLVDD(NC)
Enable Side Port Memory W14
MEM_CKN(NC) 26mA
Enable Side Port Memory IOPLLVSS(NC)
AD23
AE12 MEM_COMPP(NC)
4 4
RS880: HSYNC# AD12
MEM_COMPN(NC) MEM_VREF(NC)
AE18
[11,25] GMCH_CRT_HSYNC 2 1 +3VS 0: Enable Register Readback of strap:
R94 3K_0402_5% NB_CLKCFG:CLK_TOP_SPARE_D[1] RS880M_FCBGA528
@ 1 : Disable
2
R95
1
3K_0402_5% RS880 A11(SA000032710)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 PWR/GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 12 of 48
A B C D E
 5 4 3 2 1

PCIE LANE REVERSAL

U6A [10] PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15] [10]
[10] PCIE_MTX_C_GRX_N[0..15] PCIE_GTX_C_MRX_N[0..15] [10]

PCIE_MTX_C_GRX_P15 AF30 AH30 PCIE_GTX_MRX_P15 C269

1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P15
PCIE_MTX_C_GRX_N15 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N15 DIS@ PCIE_GTX_C_MRX_N15
D AE31 PCIE_RX0N PCIE_TX0N AG31 1 2 D
C270 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P14 AE29 AG29 PCIE_GTX_MRX_P14 C267

1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P14
PCIE_MTX_C_GRX_N14 PCIE_RX1P PCIE_TX1P PCIE_GTX_MRX_N14 DIS@ PCIE_GTX_C_MRX_N14
AD28 PCIE_RX1N PCIE_TX1N AF28 1 2
C268 0.1U_0402_10V7K U6F
R103
PCIE_MTX_C_GRX_P13 AD30 AF27 PCIE_GTX_MRX_P13 C265
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P13 1 @ 2
PCIE_MTX_C_GRX_N13 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N13 DIS@ PCIE_GTX_C_MRX_N13 10K_0402_5%
AC31 PCIE_RX2N PCIE_TX2N AF26 1 2
C266 0.1U_0402_10V7K LVDS CONTROL AB11
VARY_BL VGA_PNL_PWM [27]
DIGON AB12 VGA_ENVDD [27]
PCIE_MTX_C_GRX_P12 AC29 AD27 PCIE_GTX_MRX_P12 C494
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P12
PCIE_MTX_C_GRX_N12 PCIE_RX3P PCIE_TX3P PCIE_GTX_MRX_N12 DIS@ PCIE_GTX_C_MRX_N12
AB28 PCIE_RX3N PCIE_TX3N AD26 1 2 1 @ 2
C264 0.1U_0402_10V7K R104
10K_0402_5%
PCIE_MTX_C_GRX_P11 AB30 AC25 PCIE_GTX_MRX_P11 C262
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P11 AH20
PCIE_RX4P PCIE_TX4P TXCLK_UP_DPF3P

PCI EXPRESS INTERFACE

PCIE_MTX_C_GRX_N11 AA31 AB25 PCIE_GTX_MRX_N11 1 2 DIS@ PCIE_GTX_C_MRX_N11 AJ19
PCIE_RX4N PCIE_TX4N C263 0.1U_0402_10V7K TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P AL21
PCIE_MTX_C_GRX_P10 AA29 Y23 PCIE_GTX_MRX_P10 C259
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P10 AK20
PCIE_MTX_C_GRX_N10 PCIE_RX5P PCIE_TX5P PCIE_GTX_MRX_N10 DIS@ PCIE_GTX_C_MRX_N10 TXOUT_U0N_DPF2N
Y28 PCIE_RX5N PCIE_TX5N Y24 1 2
C260 0.1U_0402_10V7K AH22
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N AJ21
PCIE_MTX_C_GRX_P9 Y30 AB27 PCIE_GTX_MRX_P9 C257
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9 PCIE_RX6P PCIE_TX6P PCIE_GTX_MRX_N9 DIS@ PCIE_GTX_C_MRX_N9
C
W31 PCIE_RX6N PCIE_TX6N AB26 1 2 TXOUT_U2P_DPF0P AL23 C
C258 0.1U_0402_10V7K AK22
TXOUT_U2N_DPF0N
PCIE_MTX_C_GRX_P8 W29 Y27 PCIE_GTX_MRX_P8 C255
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P8 AK24
PCIE_MTX_C_GRX_N8 PCIE_RX7P PCIE_TX7P PCIE_GTX_MRX_N8 DIS@ PCIE_GTX_C_MRX_N8 TXOUT_U3P
V28 PCIE_RX7N PCIE_TX7N Y26 1 2 TXOUT_U3N AJ23
C256 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P7 V30 W24 PCIE_GTX_MRX_P7 C253

1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P7 LVTMDP
PCIE_MTX_C_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N7 DIS@ PCIE_GTX_C_MRX_N7
U31 PCIE_RX8N PCIE_TX8N W23 1 2
C254 0.1U_0402_10V7K AL15
TXCLK_LP_DPE3P VGA_TXCLK+ [27]
TXCLK_LN_DPE3N AK14 VGA_TXCLK- [27]
PCIE_MTX_C_GRX_P6 U29 V27 PCIE_GTX_MRX_P6 C251
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_GTX_MRX_N6 DIS@ PCIE_GTX_C_MRX_N6
T28 PCIE_RX9N PCIE_TX9N U26 1 2 TXOUT_L0P_DPE2P AH16 VGA_TXOUT0+ [27]
C252 0.1U_0402_10V7K AJ15
TXOUT_L0N_DPE2N VGA_TXOUT0- [27]
PCIE_MTX_C_GRX_P5 T30 U24 PCIE_GTX_MRX_P5 C249
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P5 AL17
PCIE_RX10P PCIE_TX10P TXOUT_L1P_DPE1P VGA_TXOUT1+ [27]
PCIE_MTX_C_GRX_N5 R31 U23 PCIE_GTX_MRX_N5 1 2 DIS@ PCIE_GTX_C_MRX_N5 AK16
PCIE_RX10N PCIE_TX10N TXOUT_L1N_DPE1N VGA_TXOUT1- [27]
C250 0.1U_0402_10V7K
TXOUT_L2P_DPE0P AH18 VGA_TXOUT2+ [27]
PCIE_MTX_C_GRX_P4 R29 T26 PCIE_GTX_MRX_P4 C247
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P4 AJ17
PCIE_RX11P PCIE_TX11P TXOUT_L2N_DPE0N VGA_TXOUT2- [27]
PCIE_MTX_C_GRX_N4 P28 T27 PCIE_GTX_MRX_N4 1 2 DIS@ PCIE_GTX_C_MRX_N4
PCIE_RX11N PCIE_TX11N C248 0.1U_0402_10V7K
TXOUT_L3P AL19
TXOUT_L3N AK18
PCIE_MTX_C_GRX_P3 P30 T24 PCIE_GTX_MRX_P3 C245
1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P3
PCIE_MTX_C_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N3 DIS@ PCIE_GTX_C_MRX_N3
N31 PCIE_RX12N PCIE_TX12N T23 1 2
B C246 0.1U_0402_10V7K B

PCIE_MTX_C_GRX_P2 N29 P27 PCIE_GTX_MRX_P2 C243

1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P2 Park-S3 DIS@
PCIE_MTX_C_GRX_N2 PCIE_RX13P PCIE_TX13P PCIE_GTX_MRX_N2 DIS@ PCIE_GTX_C_MRX_N2
M28 PCIE_RX13N PCIE_TX13N P26 1 2
C244 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P1 M30 P24 PCIE_GTX_MRX_P1 C241

1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 PCIE_RX14P PCIE_TX14P PCIE_GTX_MRX_N1 DIS@ PCIE_GTX_C_MRX_N1
L31 PCIE_RX14N PCIE_TX14N P23 1 2
C242 0.1U_0402_10V7K

PCIE_MTX_C_GRX_P0 L29 M27 PCIE_GTX_MRX_P0 C239

1 0.1U_0402_10V7K
2 DIS@ PCIE_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N0 DIS@ PCIE_GTX_C_MRX_N0
K30 PCIE_RX15N PCIE_TX15N N26 1 2
C240 0.1U_0402_10V7K

CLOCK
T26 PAD
[19] CLK_PEG_VGA AK30 PCIE_REFCLKP
[19] CLK_PEG_VGA# AK32 PCIE_REFCLKN
T25 PAD
CALIBRATION
PCIE_CALRP Y22 1.27K_0402_1% 1 DIS@ 2 R107

R108 2 DIS@ 110K_0402_5% N10 AA22 2K_0402_5% 1 DIS@ 2 R109 +VGA_PCIE

PWRGOOD PCIE_CALRN
A A

[11,12,20,28,29,34] PLT_RST# AL27 PERSTB

Park-S3 DIS@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 PCIE/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 13 of 48
5 4 3 2 1
 5 4 3 2 1

Transmitter Power Saving Enable

TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode CONFIGURATION STRAPS RECOMMENDED SETTINGS
1: full Tx output swing (Default setting for Desktop) 0= DO NOT INSTALL RESISTOR

U6B
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 10K RESISTOR
PCI Express Transmitter De-emphasis Enable X = DESIGN DEPENDANT
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
1: Tx de-emphasis enabled (Defailt setting for desktop)
L17 M93-S3/M92-S2 AF2 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
TXCAP_DPA3P VGA_HDMI_TXC+ [26]
+1.8VSG 2 1 +DPC_VDD18 AE9 AF4
DVCNTL_0/ DVPDATA_18 TXCAM_DPA3N VGA_HDMI_TXC- [26]
BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ L9
DIS@ DVCNTL_1 / NC TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0

C271

C272

C275
1 1 1 130mA N9 AG3

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
DVCNTL_2 / TESTEN#2 TX0P_DPA2P VGA_HDMI_TXD0+ [26]
AE8
DVDATA_12 / DVPDATA_16 DPA TX0M_DPA2N
AG5 VGA_HDMI_TXD0- [26]
AD9
DVDATA_11 / DVPDATA_20 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1
AC10 AH3 VGA_HDMI_TXD1+ [26]
2 2 2 DVDATA_10 / DVPDATA_22 TX1P_DPA1P
AD7 AH1 VGA_HDMI_TXD1- [26]
DVDATA_9 / DVPDATA_12 TX1M_DPA1N
AC8
DVDATA_8 / DVPDATA_14 BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 0
AC7 AK3 VGA_HDMI_TXD2+ [26]
D DVDATA_7 / DVPCNTL_0 TX2P_DPA0P D
AB9 AK1 VGA_HDMI_TXD2- [26]
DVDATA_6 / DVPDATA_8 TX2M_DPA0N
AB8
DVDATA_5 / DVPDATA_6 GPIO8 0
AB7 AK5
DVDATA_4 DVPDATA_4 TXCBP_DPB3P
AB4 AM3
+VGA_PCIE VRAM_ID2 DVDATA_3 / DVPDATA_19 TXCBM_DPB3N
[15] VRAM_ID2 AB2
VRAM_ID1 DVDATA_2 / DVPDATA_21 +3VSG BIF_VGA DIS GPIO9 VGA ENABLED 0
Y8 AK6
L16
[15] VRAM_ID1
[15] VRAM_ID0
VRAM_ID0 Y7
DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0
TX3P_DPB2P
TX3M_DPB2N
AM5 STRAPS
2 1 +DPC_VDD10 DPB GPU_GPIO0 R111 2 @ 1 10K_0402_5%
BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ AJ7 GPU_GPIO1 R112 2 DIS@ 1 10K_0402_5% GPIO21 0
TX4P_DPB1P
DIS@ DVO
C277

C274

C278

1 1 1 200mA AH6
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K
TX4M_DPB1N
AK8 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
TX5P_DPB0P GPU_GPIO2 R113 @
AL7 2 1 10K_0402_5%
2 2 2 TX5M_DPB0N
M93-S3/M92-S2 GPU_GPIO8 R114 2 @ 1 10K_0402_5% ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 001
+DPC_PVDD W6 GPU_GPIO9 R115 2 @ 1 10K_0402_5%
DPC_PVDD / DVPDATA_11
V6
DPC_PVSS / GND M92-S2/M93-S3
V4 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
+DPC_VDD18 DVPDATA_3/TXCCP_DPC3P GPU_GPIO11 R117
AC6 U5 2 DIS@ 1 10K_0402_5%
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N GPU_GPIO12 R118 @
AC5 2 1 10K_0402_5%
DPC_VDD18#2/DVPDAT23 GPU_GPIO13 R119 @
W3 2 1 10K_0402_5% H2SYNC 0
L18 +DPC_VDD10 DVPDATA_7 / TX0P_DPC2P
AA5 V2
+DPC_PVDD DPC_VDD10#1/DVPDAT15 DVPDATA_1 / TX0M_DPC2N R120;R121 NC on PAWE7&PAWE8 DIS
+1.8VSG 2 1 AA6
BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ DPC_VDD10#2/DVPDAT17 VGA_CRT_HSYNC R120 DIS@ 1 10K_0402_5% GENERICC 0
Y4 2
DIS@ DVPCNTL_MV1 / TX1P_DPC1P VGA_CRT_VSYNC R121 DIS@ 1 10K_0402_5%
C279

C280

C281

1 1 1 20mA W5 2
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K

DVPDATA_9 / TX1M_DPC1N VGA_CRT_VSYNC2 R122 @

2 1 10K_0402_5% AUD[1] AUD[0]
U1 AA3 VGA_CRT_HSYNC2 R123 2 @ 1 10K_0402_5% AUD[1] HSYNC 0 0 No audio function
DPC_VSSR#1 / DVPCLK DVPDATA_13 / TX2P_DPC0P 11
W1 Y2 0 1 Audio for DisplayPort and HDMI if dongle is detected
2 2 2 DPC_VSSR#2 / DVPDAT5 DVPCNTL_1 / TX2M_DPC0N AUD[0] VSYNC
U3 1 0 Audio for DisplayPort only
DPC_VSSR#3 / GND
Y6 AA12 1 1 Audio for both DisplayPort and HDMI
DPC_VSSR#4 / GND VDDR4 / DPCD_CALR
AA1
DPC_VSSR#5/ DVPCNTL_MV0

1
R124 AMD RESERVED CONFIGURATION STRAPS
DPC 150_0402_1%
DIS@ ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,

2
THEY MUST NOT CONFLICT DURING RESET
C VGA_LCD_CLK R1 C
[27] VGA_LCD_CLK SCL
VGA_LCD_DAT R3 I2C
[27] VGA_LCD_DAT SDA H2SYNC GENERICC
AM26 VGA_CRT_R
GENERAL PURPOSE I/O R VGA_CRT_R [25]
AK26
GPU_GPIO0 RB
GPU_GPIO1
U6
GPIO_0 VGA_CRT_G
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
@ U10 AL25
GPIO_1 G VGA_CRT_G [25] THEY MUST NOT CONFLICT DURING RESET
+3VSG 1 R125 2 GPU_GPIO2 T10 AJ25
10K_0402_5% GPU_GPIO3 GPIO_2 GB
U8
RB751V_SOD323 D4 GPU_GPIO4 GPIO_3_SMBDATA VGA_CRT_B
U7 AH24 VGA_CRT_B [25]
GPIO_4_SMBCLK B GPIO21_BB_EN
[34,39] ACIN 1 2 T9 AG25
GPIO_5_AC_BATT BB
@ T8
GPIO_6 DAC1
T7 AH26 VGA_CRT_HSYNC
[11] VGA_ENBKL GPIO_7_BLON HSYNC VGA_CRT_HSYNC [25] +3VSG
GPU_GPIO8 P10 AJ27 VGA_CRT_VSYNC L19
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC [25]
GPU_GPIO9 P4 +3VSG 2 1 +A2VDD
GPIO_9_ROMSI L20 BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ R129 @ 10K_0402_5% GPU_GPIO3
P2 1 2
GPU_GPIO11 GPIO_10_ROMSCK +AVDD GPU_GPIO4
1 R126 2 DIS@ DIS@ R127 @ 10K_0402_5%

C282

C286

C287
N6 AD22 +1.8VSG 2 1 1 1 1 1 2

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
GPU_GPIO12 GPIO_11 RSET
N5
GPIO_12 70mA499_0402_1% BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ R130 1 @ 2 10K_0402_5% GPU_VID0
GPU_GPIO13 +AVDD DIS@ R151 @ 10K_0402_5% GPU_VID1

C283

C284

C285
N3 AG24 1 1 1 1 2

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
@ GPIO_13 AVDD
R149 Y9 AE22
GPIO_14_HPD2 AVSSQ 2 2 2
1 2 GPIO24_TRSTB [44] GPU_VID0
GPU_VID0 N1 45mA
10K_0402_5% T12 GPIO_15_PWRCNTL_0 +VDD1DI R131 1 @ GPIO24_TRSTB
M4 AE23 2 10K_0402_5%
THM_ALERT# GPIO_16_SSIN VDD1DI 2 2 2 R132 1 @
R6 AD23 2 10K_0402_5% GPIO25_TDI
@ R134 10K_0402_5% GPIO_17_THERMAL_INT VSS1DI R133 1 @ GPIO26_TCK
W10 2 10K_0402_5%
GPIO27_TMS GPIO_18_HPD3
+3VSG 1 R135 2 1 @ 2 M2 M92-S2/M93-S3
10K_0402_5% GPU_VID1 GPIO_19_CTF R136 1 @
[44] GPU_VID1 P8 AM12 2 10K_0402_5% GPIO28_TDO
GPIO_20_PWRCNTL_1 R2 / NC L21
P7 AK12
GPIO26_TCK GPIO_21_BB_EN R2B / NC L22 +A2VDDQ R138 2 DIS@
[19] 27M_NSSC N8 +1.8VSG 2 1 1 4.7K_0402_5% VGA_LCD_DAT
GPIO_22_ROMCSB +VDD1DI BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ R139 2 DIS@ VGA_LCD_CLK
N7 AL11 +1.8VSG 2 1 1 4.7K_0402_5%
GPIO_23_CLKREQB G2 / NC BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ DIS@

C291

C292

C293
AJ11 1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
G2B / NC DIS@ R140 2 DIS@ 1 10K_0402_5% VGA_CRT_CLK

C288

C289

C290
1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
+3VSG 2 R137 1 @ TEST_EN AK10 R142 2 DIS@ 1 10K_0402_5% VGA_CRT_DATA
10K_0402_5% GPIO24_TRSTB B2 / NC
L6 AL9
JTAG_TRSTB B2B / NC
2

GPIO25_TDI L5 2 2 2
GPIO26_TCK JTAG_TDI 2 2 2
L3
R141 GPIO27_TMS JTAG_TCK
L1 AH12
GPIO28_TDO JTAG_TMS C / NC
10K_0402_5% K4
JTAG_TDO DAC2 Y / NC
AM10
+3VSG
DIS@ TEST_EN AF24 AJ9
[15] TEST_EN
1

B TESTEN COMP / NC B

AB13 VGA_CRT_R
GENERICA VGA_CRT_HSYNC2 L23
W8 AL13
GENERICB H2SYNC VGA_CRT_VSYNC2 +VDD2DI +3VSG VGA_CRT_G
W9 AJ13 +1.8VSG 2 1
GENERICC V2SYNC

1
W7 BLM15BD121SN1D_0402 DIS@ DIS@ DIS@
GENERICD DIS@ R143 R144 VGA_CRT_B

C294

C295

C296
AD10 50mA 1 1 1

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z
GENERICE_HPD4 +VDD2DI 10K_0402_5% 10K_0402_5%
AD19
VDD2DI / NC

R147 1

R148 1

R145 1
AC14 AC19 DIS@ DIS@

150_0402_1%

150_0402_1%

150_0402_1%
[11,26] HDMI_DET HPD1 VSS2DI / NC

2
2

2
2 2 2
130mA
+1.8VSG AE20 +A2VDD VGA_SMB_CK2_R 1 6
A2VDD / NC EC_SMB_CK2 [6,31,34]
1.5mA

2
5
DIS@ 0.60 V level AE17 +A2VDDQ Q7A
+VREFG_GPU A2VDDQ / NC
1 R146 2 AC16 2N7002DW-T/R7_SOT363-6
499_0402_1% VREFG VGA_SMB_DA2_R DIS@
AE19 4 3 EC_SMB_DA2 [6,31,34] DIS@ DIS@ DIS@
A2VSSQ
1

Q7B DIS@
C297

1
R272 DIS@ AG13 1 R150 2 DIS@ 2N7002DW-T/R7_SOT363-6
249_0402_1% 0.1U_0402_10V6K R2SET / NC 715_0402_1%
DIS@
+1.8VSG +DPLL_PVDD 2
M92-S2/M93-S3 M92-S2/M93-S3
2

L24 +DPLL_PVDD AE6 VGA_CRT_CLK

PLL/CLOCK DDC1CLK VGA_CRT_CLK [25] +3VSG
2 1 1U_0402_6.3V4Z 120mA AE5 VGA_CRT_DATA
BLM15BD121SN1D_0402 DDC1DATA VGA_CRT_DATA [25]
1 1 1 AF14
DIS@ C298 C299 C300 DPLL_PVDD
AE14 AD2
DIS@
10U_0603_6.3V6M DIS@
DIS@
0.1U_0402_10V6K 300mA
DPLL_PVSS
DDC/AUX
AUX1P
AUX1N
AD4
C301
2 VGA Thermal Sensor
2 2 2
+DPLL_VDDC AD14
DPLL_VDDC DDC2CLK
DDC2DATA
AC11
AC13
VGA_HDMI_SCLK [26]
VGA_HDMI_SDATA [26]
0.1U_0402_16V4Z
DIS@ 1
ADM1032 Closed to GPU
XTALIN 27MCLK AM28 AD13 +VGA_PCIE +DPLL_VDDC U7 DIS@
XTALOUT XTALIN AUX2P L25 VGA_SMB_CK2_R
Voltage Swing: 1.8 V AK28 AD11 1 8
XTALOUT AUX2N +1.8VSG VDD SCLK
2 1
AE16 L26 BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ GPU_THERMAL_D+ 2 7 VGA_SMB_DA2_R
DIS@ DDCCLK_AUX5P BLM18AG121SN1D_0603 DIS@ D+ SDATA
C302

C303

C305
AD16 1 1 1
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K
0_0402_5% 1 R62 2 DDCDATA_AUX5N +TSVDD
AC22 2 1 1 2 3 6
0_0402_5% 1 R105 2 NC#2/XO_IN DIS@ C304 DIS@ D- ALERT#
AB22 AC1 1 1 1
NC#1/XO_IN2 DDC6CLK
10U_0603_6.3V6M
C308

1U_0402_6.3V4Z
C309

0.1U_0402_16V4Z
C310

A DIS@ AC3 2200P_0402_50V7K 4 5 THM_ALERT# A

DIS@ DDC6DATA 2 2 2 GPU_THERMAL_D- THERM# GND
XTALOUT 27MCLK
Suggest connect to GND by AMD DIS@ DIS@
AD20
1M_0603_5% R152 NC/DDCCLK_AUX3P 2 2 2
AC20 +3VSG 1 R643 2 EMC1402-2-ACZL-TR MSOP 8P 2 R155 1 +3VSG
THERMAL NC/DDCDATA_AUX3N DIS@ DIS@ DIS@ 4.7K_0402_5% 4.7K_0402_5%
Y1 DIS@ GPU_THERMAL_D+ T4
GPU_THERMAL_D- DPLUS EMC1412-A (SA00003YA00)
2 1 T2
DMINUS TMP411C (GPU)
100_1110b Address 1111_100xb
27MHZ_16PF_X5H027000FG1H S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
R5
C307 C306 +TSVDD TS_FDO
DIS@ DIS@ 20mA
AD17
AC17
TSVDD
TSVSS
Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 18P_0402_50V8J 2008/10/06 2010/04/30 Title
Issued Date Deciphered Date
Park-S3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 Main Generic/MSIC
DIS@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 14 of 48
5 4 3 2 1
 5 4 3 2 1

U6C
M_DA[63..0]
[18] M_DA[63..0]
M_MA[13..0] M_DA0 K27 K17 M_MA0 +1.8VSG
[18] M_MA[13..0] DQA_0 MAA_0
M_DA1 J29 J20 M_MA1
M_DQM[7..0] M_DA2 DQA_1 MAA_1 M_MA2 R157 H@ 10K_0402_5% VRAM_ID0
[18] M_DQM[7..0] H30 DQA_2 MAA_2 H23 1 2 VRAM_ID0 [14]
M_DA3 H32 G23 M_MA3 R158 1 2 S@ 10K_0402_5%
M_DQS[7..0] M_DA4 DQA_3 MAA_3 M_MA4 R159 S@ 10K_0402_5% VRAM_ID1
[18] M_DQS[7..0] G29 DQA_4 MAA_4 G24 1 2 VRAM_ID1 [14]
M_DA5 F28 H24 M_MA5 R160 1 2 H@ 10K_0402_5%

MEMORY INTERFACE
M_DQS#[7..0] M_DA6 DQA_5 MAA_5 M_MA6 R161 @ 10K_0402_5% VRAM_ID2
[18] M_DQS#[7..0] F32 DQA_6 MAA_6 J19 1 2 VRAM_ID2 [14]
M_DA7 F30 K19 M_MA7 R162 1 2 DIS@ 10K_0402_5%
D M_DA8 DQA_7 MAA_7 M_MA8 D
C30 DQA_8 MAA_8 J14
M_DA9 F27 K14 M_MA9
M_DA10 DQA_9 MAA_9 M_MA10
A28 DQA_10 MAA_10 J11
M_DA11 C28 J13 M_MA11
M_DA12 DQA_11 MAA_11 M_MA12
E27 DQA_12 MAA_12 H11
M_DA13 G26 G11 M_BA2
DQA_13 MAA_13/BA2 M_BA2 [18]
M_DA14 D26 J16 M_BA0
DQA_14 MAA_14/BA0 M_BA0 [18]
M_DA15 F25 L15 M_BA1
DQA_15 MAA_15/BA1 M_BA1 [18]
M_DA16 A25 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
M_DA17 DQA_16 M_DQM0
C25 DQA_17 DQMA_0 E32
M_DA18 E25 E30 M_DQM1
M_DA19 DQA_18 DQMA_1 M_DQM2
D24 DQA_19 DQMA_2 A21 Hynix H5TQ1G63BFR-12C 1 0 0
M_DA20 E23 C21 M_DQM3
M_DA21 DQA_20 DQMA_3 M_DQM4
F23 DQA_21 DQMA_4 E13
M_DA22 D22 D12 M_DQM5
M_DA23 DQA_22 DQMA_5 M_DQM6
F21 DQA_23 DQMA_6 E3 Samsung K4W1G1646E-HC12 0 1 0
M_DA24 E21 F4 M_DQM7
M_DA25 DQA_24 DQMA_7
D20 DQA_25
M_DA26 F19 H28 M_DQS0
M_DA27 DQA_26 RDQSA_0 M_DQS1
A19 DQA_27 RDQSA_1 C27
M_DA28 D18 A23 M_DQS2
M_DA29 DQA_28 RDQSA_2 M_DQS3
F17 DQA_29 RDQSA_3 E19
M_DA30 A17 E15 M_DQS4
M_DA31 DQA_30 RDQSA_4 M_DQS5
C C17 DQA_31 RDQSA_5 D10 C
M_DA32 E17 D6 M_DQS6
M_DA33 DQA_32 RDQSA_6 M_DQS7
D16 DQA_33 RDQSA_7 G5
M_DA34 F15
M_DA35 DQA_34 M_DQS#0
A15 DQA_35 WDQSA_0 H27
M_DA36 D14 A27 M_DQS#1
M_DA37 DQA_36 WDQSA_1 M_DQS#2
F13 DQA_37 WDQSA_2 C23
+1.5VSG M_DA38 A13 C19 M_DQS#3
M_DA39 DQA_38 WDQSA_3 M_DQS#4
C13 DQA_39 WDQSA_4 C15
M_DA40 E11 E9 M_DQS#5
M_DA41 DQA_40 WDQSA_5 M_DQS#6
A11 DQA_41 WDQSA_6 C5
1

M_DA42 C11 H4 M_DQS#7

R165 M_DA43 DQA_42 WDQSA_7
F11 DQA_43
DIS@ M_DA44 A9 L18 M_ODT0
DQA_44 ODTA0 M_ODT0 [18]
40.2_0402_1% M_DA45 C9 K16 M_ODT1
DQA_45 ODTA1 M_ODT1 [18]
M_DA46 F9
2

MVREFSA M_DA47 DQA_46 M_CLK0

D8 DQA_47 CLKA0 H26 M_CLK0 [18]
M_DA48 E7 H25 M_CLK#0
DQA_48 CLKA0B M_CLK#0 [18]
1

1 M_DA49 A7
+1.5VSG R166 C312 M_DA50 DQA_49 M_CLK1
C7 DQA_50 CLKA1 G9 M_CLK1 [18]
DIS@ M_DA51 F7 H9 M_CLK#1
DQA_51 CLKA1B M_CLK#1 [18]
100_0402_1% 0.1U_0402_16V4Z M_DA52 A5
2 DIS@ M_DA53 DQA_52 M_RAS#0
E5 G22 M_RAS#0 [18]
2

DQA_53 RASA0B
1

M_DA54 C3 G17 M_RAS#1

DQA_54 RASA1B M_RAS#1 [18]
B R163 M_DA55 E1 B
DIS@ M_DA56 DQA_55 M_CAS#0
G7 DQA_56 CASA0B G19 M_CAS#0 [18]
40.2_0402_1% M_DA57 G6 G16 M_CAS#1
DQA_57 CASA1B M_CAS#1 [18] +VGA_CORE
M_DA58 G1
2

MVREFDA M_DA59 DQA_58 M_CS#0

G3 DQA_59 CSA0B_0 H22 M_CS#0 [18]
M_DA60 J6 J22
DQA_60 CSA0B_1
1

1 M_DA61 J1 DQA_61

1
R164 C311 M_DA62 J3 G13 M_CS#1
DQA_62 CSA1B_0 M_CS#1 [18]
DIS@ 0.1U_0402_16V4Z M_DA63 J5 K13 R167
100_0402_1% DIS@ DQA_63 CSA1B_1 2.2K_0402_5%
2 +1.5VSG MVREFDA K26 K20 M_CKE0 @
M_CKE0 [18]
2

MVREFSA MVREFDA CKEA0 M_CKE1 R169 DIS@

J26 J17 M_CKE1 [18]

2
MVREFSA CKEA1 51.1_0402_1%
240_0402_1%1 DIS@ 2 R168 J25 G25 M_WE#0 DRAM_RST 1 2
MEM_CALRN0 WEA0B M_WE#0 [18] DRAM_RST# [18]
R170 1 DIS@ 2 0_0402_5% K7 H10 M_WE#1
[14] TEST_EN NC/TESTEN#2 WEA1B M_WE#1 [18]

1
R171 1 DIS@ 2 150_0402_1% J8 AB16 1
R172 1 DIS@ MEM_CALRP1/DPC_CALR PX_EN
2 240_0402_1%K25 MEM_CALRP0
R273 C313
10K_0402_5% 68P_0402_50V8J
DRAM_RST L10 DIS@
R174 C314DIS@ DRAM_RST DIS@ 2
G14

2
DIS@ 2 51.1_0402_1% RSVD#2
1 1 20.1U_0402_16V4Z K8 CLKTESTA
1 2 1 2 L7 G20 M_MA13
DIS@ 51.1_0402_1% DIS@ 0.1U_0402_16V4Z CLKTESTB RSVD#3
A R175 C315 A
Park-S3
DIS@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 15 of 48
5 4 3 2 1
 5 4 3 2 1

DPE_VDD10
DPF_VDD10 Park-S3: TMDS/DP=110mA@1.0V : LVDS=120mA@1.0V

D U6G D
+1.8VSG +1.8VSG
DP E/F POWER DP A/B POWER
L54 DIS@
200mA 130mA C319 DIS@ L27 DIS@
2 1 +DPE_VDD18 AG15 AE11 +DPA_VDD18 0.1U_0402_10V6K 2 1
BLM15BD121SN1D_0402 DPE_VDD18#1 DPA_VDD18#1 MBK1608121YZF_0603
1 1 1 AG16 DPE_VDD18#2 DPA_VDD18#2 AF11
C316 C320 C321DIS@ 1 1 1
DIS@ DIS@ 0.1U_0402_10V6K +VGA_PCIE C318 DIS@
10U_0603_6.3V6M 0.2A L29 10U_0603_6.3V6M
2 2 2 0.17A AG20 AF6 +DPA_VDD10 1 2 DIS@
+VGA_PCIE 1U_0402_6.3V4Z +DPE_VDD10 DPE_VDD10#1 DPA_VDD10#1 DIS@ DIS@ DIS@ DIS@ 2 C317 2 2
AG21 DPE_VDD10#2 DPA_VDD10#2 AF7

0.1U_0402_10V6K
10U_0603_6.3V6M
C322

C323

C324
1U_0402_6.3V4Z
1 1 1 MBK1608121YZF_0603 1U_0402_6.3V4Z
L31
1 2 AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
MBK1608121YZF_0603
C328 AH14 AE3
DIS@ 1 C3291 DPE_VSSR#2 DPA_VSSR#2 2 2 2
1 AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
1U_0402_6.3V4Z DIS@ C330DIS@ AM16 AG6
10U_0603_6.3V6M DPE_VSSR#4 DPA_VSSR#4
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5
+1.8VSG
+1.8VSG 2 2 2 C327
0.1U_0402_10V6K
130mA DIS@ BLM15BD121SN1D_0402
L55 DIS@
0.11A AF16 AE13 +DPB_VDD18 0.1U_0402_10V6K 1 2
+DPF_VDD18 DPF_VDD18#1 DPB_VDD18#1 DIS@ L30
2 1 AG17 DPF_VDD18#2 DPB_VDD18#2 AF13
C
BLM15BD121SN1D_0402 1 1 1 1 1 1 C
C502 C503 C501DIS@ +VGA_PCIE
0.2A
DIS@ DIS@ 0.1U_0402_10V6K L32 C326 C325
10U_0603_6.3V6M
0.17A AF22 AF8 +VPB_VDD10 2 1 DIS@ DIS@
2 2 2 +DPF_VDD10 DPF_VDD10#1 DPB_VDD10#1 DIS@ DIS@ BLM15BD121SN1D_0402 2 2 2 10U_0603_6.3V6M
AG22 DPF_VDD10#2 DPB_VDD10#2 AF9
+VGA_PCIE

0.1U_0402_10V6K
10U_0603_6.3V6M

1U_0402_6.3V4Z
1U_0402_6.3V4Z 1 1 1 DIS@ 1U_0402_6.3V4Z
L49

C331

C332

C333
DIS@
1 2 AF23 DPF_VSSR#1 DPB_VSSR#1 AF10
MBK1608121YZF_0603 C506 AG23 AG9 DIS@
DIS@ 1 C5041 DPF_VSSR#2 DPB_VSSR#2 2 2 2
1 AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
1U_0402_6.3V4Z DIS@ C505DIS@ AM22 AM6
10U_0603_6.3V6M DPF_VSSR#4 DPB_VSSR#4
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8
2 2 2
0.1U_0402_10V6K
R176 DIS@
2 1 AF17 AE10 DIS@ 1 R177 2
+1.8VSG 150_0402_1% DPEF_CALR DPAB_CALR 150_0402_1% +1.8VSG
L33
DIS@
0.02A L34
2 1 +DPE_PVDD AG18 DP PLL POWER AG8 +DPA_PVDD 2 1
BLM15BD121SN1D_0402 DPE_PVDD DPA_PVDD DIS@ DIS@ BLM15BD121SN1D_0402
AF19 DPE_PVSS 20mA 20mA DPA_PVSS AG7

10U_0603_6.3V6M

1U_0402_6.3V4Z
1 1 1 DIS@

0.1U_0402_10V6K
C338

C337

C339
C334 C335 C336 1 1 1
B DIS@ DIS@ DIS@ DIS@ B
1U_0402_6.3V4Z 10U_0603_6.3V6M +DPF_PVDD AG19 20mA 20mA AG10
+1.8VSG 2 2 2 DPF_PVDD DPB_PVDD
AF20 DPF_PVSS DPB_PVSS AG11
L50 0.1U_0402_10V6K 2 2 2
DIS@
2 1
BLM15BD121SN1D_0402 Park-S3 DIS@
1 1 1 +1.8VSG
C509 C508 C507
DIS@ DIS@ DIS@
1U_0402_6.3V4Z 10U_0603_6.3V6M
0.02A L35
2 2 2 +DPB_PVDD 2 1
0.1U_0402_10V6K DIS@ DIS@ DIS@ BLM15BD121SN1D_0402

0.1U_0402_10V6K
10U_0603_6.3V6M
C340

C341

C342
1U_0402_6.3V4Z
1 1 1 DIS@

2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 DPX Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 16 of 48
5 4 3 2 1
 5 4 3 2 1

+1.5VSG

2.2A
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

0.1U_0402_10V6K
C343

C344

C345

C346

C347

C348

C349

C350

C351

C352

C353

C493

C492

C356
1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.8VSG

R1.0
0.4A L36
U6D +PCIE_GDDR 1 2 U6E
DIS@ DIS@ DIS@ DIS@ DIS@ MBK1608221YZF_0603

C363

C357

C369

C364

C358
+1.5VSG MEM I/O 1 1 1 1 1 DIS@

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
0.1U_0402_10V6K
D D
PCIE
H13 AB23 AA27 A3
DIS@ DIS@ DIS@ DIS@ VDDR1#1 PCIE_VDDR#1 PCIE_VSS#1 GND#1
H16 AC23 AB24 A30
+VDDC_CT VDDR1#2 PCIE_VDDR#2 2 2 2 2 2 PCIE_VSS#2 GND#2

C365

C366

C370

C371
1 1 1 1 H19 AD24 AB32 AA13

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDR1#3 PCIE_VDDR#3 PCIE_VSS#3 GND#3 / EVDDQ#2
J10 AE24 AC24 AA16
L37 R1.0 VDDR1#4 PCIE_VDDR#4 PCIE_VSS#4 GND#4
1 2
0.136A J23
J24
VDDR1#5 PCIE_VDDR#5
AE25
AE26 +VGA_PCIE
AC26
AC27
PCIE_VSS#5 GND#5
AB10
AB15
+1.8VSG 2 2 2 2 VDDR1#6 PCIE_VDDR#6 PCIE_VSS#6 GND#6 / EVDDQ#3
BLM15BD121SN1D_0402 DIS@ @ DIS@ DIS@ J9 AF25 AD25 AB6
VDDR1#7 PCIE_VDDR#7 PCIE_VSS#7 GND#7
C359

C367

C368

C360
DIS@ 1 1 1 1 K10 AG26 AD32 AC9
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDR1#8 PCIE_VDDR#8 PCIE_VSS#8 GND#8
K23
K24
VDDR1#9 2A AE27
AF32
PCIE_VSS#9 GND#9
AD6
AD8
VDDR1#10 PCIE_VSS#10 GND#10
K9 L23 AG27 AE7
2 2 2 2 VDDR1#11 PCIE_VDDC#1 DIS@ DIS@ DIS@ DIS@ DIS@ PCIE_VSS#11 GND#11
L11 L24 AH32 AG12
VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12

C372

C373

C374

C361

C362
L12 L25 1 1 1 1 1 K28 AH10

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDR1#13 PCIE_VDDC#3 PCIE_VSS#13 GND#13
L13 L26 K32 AH28
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#14 GND#14
L20 M22 L27 B10
VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
L21 N22 M32 B12
+3VSG VDDR1#16 PCIE_VDDC#6 2 2 2 2 2 PCIE_VSS#16 GND#16
L22 N23 N25 B14
VDDR1#17 PCIE_VDDC#7 PCIE_VSS#17 GND#17
0.06A PCIE_VDDC#8
N24
R22
N27
P25
PCIE_VSS#18 GND#18
B16
B18
R1.0 PCIE_VDDC#9 PCIE_VSS#19 GND#19
T22 P32 B20
+VDDC_CT LEVEL PCIE_VDDC#10 PCIE_VSS#20 GND#20
17mA TRANSLATION PCIE_VDDC#11
U22
+VGA_CORE
R27
PCIE_VSS#21 GND#21
B22
DIS@ DIS@ DIS@ @ V22 T25 B24
PCIE_VDDC#12 PCIE_VSS#22 GND#22
C375

C376

C377

1 1 1 C378 1 AA20 9A(RMS)/14A(Peak) T32 B26

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDD_CT#1 PCIE_VSS#23 GND#23
AA21 U25 B6
VDD_CT#2 PCIE_VSS#24 GND#24
AB20 AA15 U27 B8
VDD_CT#3 CORE VDDC#1 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ PCIE_VSS#25 GND#25
AB21 N15 V32 C1
2 2 2 2 VDD_CT#4 VDDC#2 PCIE_VSS#26 GND#26

C379

C380

C381

C382

C383

C384

C385

C386

C387

C388
N17 1 1 1 1 1 1 1 1 1 1 W25 C32

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
VDDC#3 PCIE_VSS#27 GND#27
M93-S3/M92-S2 VDDC#4
R13 W26
PCIE_VSS#28 GND#28
E28

POWER
R16 W27 F10
VDDC#5 PCIE_VSS#29 GND#29
AA17 R18 Y25 F12
VDDR3#1 VDDC#6 2 2 2 2 2 2 2 2 2 2 PCIE_VSS#30 GND#30
AA18
VDDR3#2 I/O VDDC#7
Y21 Y32
PCIE_VSS#31 GND#31
F14
AB17 T12 F16
VDDR3#3 VDDC#8 GND#32
AB18 T15 F18
R1.0 VDDR3#4 VDDC#9 GND#33
T17 F2
VDDC#10 GND#34
+1.8VSG V12 T20 F20
@ DIS@ DIS@ VDDR4#1 / VDDR5 VDDC#11 +VGA_CORE GND#35
Y12 U13 M6 F22
VDDR4#2 VDDC#12 GND#56 GND#36
C U12 U16 N11 F24 C
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

VDDR4#3 / VDDR5 VDDC#13 GND#57 GND#37

C389

C390

C391

1 1 1 U18 N12 F26

+VDDR VDDC#14 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ GND#58 GND#38
AA11 V21 N13 F6
NC#1 / VDDR4 VDDC#15 GND#59 GND#39

C392

C393

C394

C395

C396

C397

C398

C399

C400

C401
Y11 V15 N16 F8
1 1 1 1 1 1 1 1 1 1
GND

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
DVCLK / VDDR4 VDDC#16 GND#60 GND#40
V17 N18 G10
2 2 2 VDDC#17 GND#61 GND#41
V11 V20 N21 G27
NC#3 / VDDR5 VDDC#18 GND#62 GND#42
U11 Y13 P6 G31
TESTEN#2 / VDDR5 VDDC#20 2 2 2 2 2 2 2 2 2 2 GND#63 GND#43
Y16 P9 G8
VDDC#21 GND#64 GND#44
Y18 R12 H14
1U_0402_6.3V4Z @ VDDC#22 GND#65 GND#45
R21 R15 H17
VDDC#23 /BIF_VDDC GND#66 GND#46
+1.5VSG 2 1C402 0.04A U21 R17 H2
L38 MEM CLK VDDC#19/BIF_VDDC GND#67 GND#47
R20 H20
+VDDRHA GND#68 GND#48
1 2 L17 T13 H6
@ BLM15BD121SN1D_0402 VDDRHA GND#69 GND#49
T16 J27
R185 @ ISOLATED GND#70 GND#50
0_0402_5%
L16
VSSRHA CORE I/O 2A(RMS)/3A(Peak) T18
T21
GND#71 GND#51
J31
K11
+1.8VSG GND#72 GND#52
M13 +VGA_CORE T6 K2
L39 PLL VDDCI#1 DIS@ DIS@ DIS@ DIS@ GND#73 GND#53
40mA VDDCI#2
M15 U15
GND#74 GND#54
K22

C406

C407

C408

C409
1 2 +PCIE_PVDD AM30 M16 1 1 1 1 U17 K6

10U_0603_6.3V6M
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
BLM15BD121SN1D_0402 DIS@ DIS@ DIS@ PCIE_PVDD VDDCI#3 GND#75 GND#55
M17 U20 T11
VDDCI#4 GND#76 GND#85
C403

C404

C405

DIS@ 1 1 1 75mA M18 U9 R11

10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

+MPV18 VDDCI#5 GND#77 GND#86

L8 M20 V13
MPV18 VDDCI#6 2 2 2 2 GND#78
M21 V16
VDDCI#7 GND#79
2 2 2 50mA VDDCI#8
N20 V18
GND#80
+SPV18 H7 Y10
SPV18 GND#81
100mA Y15
GND#82
+SPV10 H8 Y17 A32
+VGA_PCIE SPV10 GND#83 VSS_MECH#1
Y20 AM1
GND#84 VSS_MECH#2
J7 AM32
DIS@ L40 SPVSS VSS_MECH#3
1 2
BLM15BD121SN1D_0402 DIS@ DIS@ DIS@
C410

C411

C412

1 1 1 BACK BIAS
10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K

M11
BBP#1 Park-S3
+VGA_CORE M12
DIS@ DIS@ BBP#2
2 2 2
C413

C414

1 1 120mA DIS@
0.1U_0402_10V6K
1U_0402_6.3V4Z

B B
Park-S3
DIS@
2 2

+1.8VSG
DIS@ L41
1 2 +MPV18
BLM15BD121SN1D_0402 DIS@ DIS@
C415

C416

1 1
0.1U_0402_10V6K
1U_0402_6.3V4Z

2 2

DIS@ L42
1 2 +SPV18
BLM15BD121SN1D_0402 DIS@ DIS@
C417

C418

1 1
1U_0402_6.3V4Z

0.1U_0402_10V6K

2 2

A A

DIS@ L43
1 2 +VDDR
BLM15BD121SN1D_0402 DIS@ DIS@
C419

C420

1 1
0.1U_0402_10V6K
1U_0402_6.3V4Z

2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 17 of 48
5 4 3 2 1
 5 4 3 2 1

M_DA[63..0]
[15] M_DA[63..0]
M_MA[13..0]
[15] M_MA[13..0]
M_DQM[7..0] U9 U10 U11 U12
[15] M_DQM[7..0]
M_DQS[7..0]
[15] M_DQS[7..0]
M_DQS#[7..0]
[15] M_DQS#[7..0]
SAMSUNG VRAM SAMSUNG VRAM SAMSUNG VRAM SAMSUNG VRAM
S@ S@ S@ S@

U9 U10 U11 U12

VREFC_A1 M9 E4 M_DA16 VREFC_A2 M9 E4 M_DA25 VREFC_A3 M9 E4 M_DA38 VREFC_A4 M9 E4 M_DA54

X76-H X76-S VREFD_Q1 VREFCA DQL0 M_DA23 VREFD_Q2 VREFCA DQL0 M_DA27 VREFD_Q3 VREFCA DQL0 M_DA34 VREFD_Q4 VREFCA DQL0 M_DA52
H2 F8 H2 F8 H2 F8 H2 F8
D VREFDQ DQL1 M_DA19 VREFDQ DQL1 M_DA24 VREFDQ DQL1 M_DA33 VREFDQ DQL1 M_DA53 D
F3 F3 F3 F3
M_MA0 DQL2 M_DA21 M_MA0 DQL2 M_DA31 M_MA0 DQL2 M_DA37 M_MA0 DQL2 M_DA49
N4 F9 N4 F9 N4 F9 N4 F9
M_MA1 A0 DQL3 M_DA17 M_MA1 A0 DQL3 M_DA26 M_MA1 A0 DQL3 M_DA35 M_MA1 A0 DQL3 M_DA51
P8 H4 P8 H4 P8 H4 P8 H4
M_MA2 A1 DQL4 M_DA18 M_MA2 A1 DQL4 M_DA30 M_MA2 A1 DQL4 M_DA39 M_MA2 A1 DQL4 M_DA50
P4 H9 P4 H9 P4 H9 P4 H9
M_MA3 A2 DQL5 M_DA22 M_MA3 A2 DQL5 M_DA28 M_MA3 A2 DQL5 M_DA32 M_MA3 A2 DQL5 M_DA55
N3 G3 N3 G3 N3 G3 N3 G3
M_MA4 A3 DQL6 M_DA20 M_MA4 A3 DQL6 M_DA29 M_MA4 A3 DQL6 M_DA36 M_MA4 A3 DQL6 M_DA48
Hynix Samsung P9
A4 DQL7
H8 P9
A4 DQL7
H8 P9
A4 DQL7
H8 P9
A4 DQL7
H8
X76H@ X76S@ M_MA5 P3 M_MA5 P3 M_MA5 P3 M_MA5 P3
X7622338L02 X7622338L01 M_MA6 A5 M_MA6 A5 M_MA6 A5 M_MA6 A5
R9 R9 R9 R9
M_MA7 A6 M_DA0 M_MA7 A6 M_DA14 M_MA7 A6 M_DA44 M_MA7 A6 M_DA57
R3 D8 R3 D8 R3 D8 R3 D8
M_MA8 A7 DQU0 M_DA4 M_MA8 A7 DQU0 M_DA10 M_MA8 A7 DQU0 M_DA42 M_MA8 A7 DQU0 M_DA58
T9 C4 T9 C4 T9 C4 T9 C4
M_MA9 A8 DQU1 M_DA1 M_MA9 A8 DQU1 M_DA15 M_MA9 A8 DQU1 M_DA47 M_MA9 A8 DQU1 M_DA60
R4 C9 R4 C9 R4 C9 R4 C9
M_MA10 A9 DQU2 M_DA6 M_MA10 A9 DQU2 M_DA11 M_MA10 A9 DQU2 M_DA40 M_MA10 A9 DQU2 M_DA61
L8 C3 L8 C3 L8 C3 L8 C3
M_MA11 A10/AP DQU3 M_DA3 M_MA11 A10/AP DQU3 M_DA12 M_MA11 A10/AP DQU3 M_DA45 M_MA11 A10/AP DQU3 M_DA63
R8 A8 R8 A8 R8 A8 R8 A8
M_MA12 A11 DQU4 M_DA7 M_MA12 A11 DQU4 M_DA8 M_MA12 A11 DQU4 M_DA43 M_MA12 A11 DQU4 M_DA62
N8 A3 N8 A3 N8 A3 N8 A3
M_MA13 A12 DQU5 M_DA2 M_MA13 A12 DQU5 M_DA13 M_MA13 A12 DQU5 M_DA46 M_MA13 A12 DQU5 M_DA56
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 M_DA5 A13 DQU6 M_DA9 A13 DQU6 M_DA41 A13 DQU6 M_DA59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG

M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3

[15] M_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10
[15] M_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8
[15] M_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
K9 K9 K9 K9
VDD VDD VDD VDD
N2 N2 N2 N2
M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
[15] M_CLK0 J8 N10 J8 N10 [15] M_CLK1 J8 N10 J8 N10
M_CLK#0 K8 CK VDD M_CLK#0 CK VDD M_CLK#1 K8 CK VDD M_CLK#1 CK VDD
[15] M_CLK#0 R2 K8 R2 [15] M_CLK#1 R2 K8 R2
M_CKE0 K10 CK VDD M_CKE0 CK VDD M_CKE1 K10 CK VDD M_CKE1 CK VDD
[15] M_CKE0 R10 K10 R10 R10 K10 R10
CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG [15] M_CKE1 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG

M_ODT0 K2 A2 M_ODT0 K2 A2 M_ODT1 K2 A2 M_ODT1 K2 A2

[15] M_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ [15] M_ODT1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L3 A9 M_CS#0 L3 A9 M_CS#1 L3 A9 M_CS#1 L3 A9
[15] M_CS#0 CS VDDQ CS VDDQ [15] M_CS#1 CS VDDQ CS VDDQ
M_RAS#0 J4 C2 M_RAS#0 J4 C2 M_RAS#1 J4 C2 M_RAS#1 J4 C2
[15] M_RAS#0 RAS VDDQ RAS VDDQ [15] M_RAS#1 RAS VDDQ RAS VDDQ
M_CAS#0 K4 C10 M_CAS#0 K4 C10 M_CAS#1 K4 C10 M_CAS#1 K4 C10
[15] M_CAS#0 CAS VDDQ CAS VDDQ [15] M_CAS#1 CAS VDDQ CAS VDDQ
M_WE#0 L4 D3 M_WE#0 L4 D3 M_WE#1 L4 D3 M_WE#1 L4 D3
[15] M_WE#0 WE VDDQ WE VDDQ [15] M_WE#1 WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
M_DQS2 VDDQ M_DQS3 VDDQ M_DQS4 VDDQ M_DQS6 VDDQ
C F4 H3 F4 H3 F4 H3 F4 H3 C
M_DQS0 DQSL VDDQ M_DQS1 DQSL VDDQ M_DQS5 DQSL VDDQ M_DQS7 DQSL VDDQ
C8 H10 C8 H10 C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

M_DQM2 E8 A10 M_DQM3 E8 A10 M_DQM4 E8 A10 M_DQM6 E8 A10

M_DQM0 DML VSS M_DQM1 DML VSS M_DQM5 DML VSS M_DQM7 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
DMU VSS DMU VSS DMU VSS DMU VSS
E2 E2 E2 E2
VSS VSS VSS VSS
G9 G9 G9 G9
M_DQS#2 VSS M_DQS#3 VSS M_DQS#4 VSS M_DQS#6 VSS
G4 J3 G4 J3 G4 J3 G4 J3
M_DQS#0 DQSL VSS M_DQS#1 DQSL VSS M_DQS#5 DQSL VSS M_DQS#7 DQSL VSS
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS
[15] DRAM_RST# T3 P10 P10 P10 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 B2 J2 B2 J2 B2 J2 B2
R189 NC/ODT1 VSSQ R190 NC/ODT1 VSSQ R191 NC/ODT1 VSSQ R192 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2
DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA
H@ H@ H@ H@

B +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG B

1

1
R193 R194 R195 R196 R197 R198 R199 R200
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@
2

2
VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1

1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C421

C422

C423

C424

C425

C426

C427

C428
1 1 1 1 1 1 1 1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R201 R202 R203 R204 R205 R206 R207 R208
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 4.99K_0402_1% DIS@ 4.99K_0402_1% DIS@ 4.99K_0402_1% DIS@
2 2 2 2 2 DIS@ 2 DIS@ 2 DIS@ 2
2

2
+1.5VSG
+1.5VSG
1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VSG 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ 1 DIS@ 1 DIS@ 1 DIS@ 1 DIS@ 1 DIS@ 1 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 1 1 1 1 1 1 1 1 1 1

C440

C441

C451

C442

C443

C444

C452

C453

C454

C445
1 1 1 1 1 1 1 1 1 1
C431

C432

C433

C434

C435

C436

C437

C438

C450

C439
M_CLK0 1 2 C446 C429 C447 C448 C449 C430
R209 DIS@ 56_0402_1% M_CLK1 1 2
R210 DIS@ 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
M_CLK#01 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R211 DIS@ 56_0402_1% M_CLK#11 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 R212 DIS@ 56_0402_1% 1
A C455 C456 A
0.01U_0402_16V7K 0.01U_0402_16V7K
DIS@ DIS@ VRAM P/N :
2 2
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PARK-S3 DDR3 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 18 of 48
5 4 3 2 1
 5 4 3 2 1

Check Timing +1.1VS <50us +3VS for EXT CLKGEN satable

+VDDCLK_IO +3VS_CLK
EXT@ L44 L45 EXT@
+1.1VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 C457 C458 C459 C460 C461 C462 FBMA-L11-201209-221LMA30T_0805 C464 C465 C466 C467 C468 C469 C470 C471 C474
D EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ 22U_0805_6.3V6M EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ 1U_0402_6.3V4Z D
2 2 2 2 2 2 2 EXT@ 2 2 2 2 2 2 2 2 EXT@
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1U CLOSE PIN 69

EXT@ L46
1 2 +3VS_CLKVDDA 100mA
+3VS
FBMA-L11-201209-221LMA30T_0805 +3VS_CLK
1 1 U13
C475 C476

1
22U_0805_6.3V6M 0.1U_0402_16V4Z
EXT@ EXT@ ICS 9LPRS488 R213
2 2 49 1
VDDA SMBCLK SB_SMCLK0 [8,9,21,28] 8.2K_0402_5%
48 2 EXT@
GNDA SMBDAT SB_SMDAT0 [8,9,21,28]

2
100mA
62 41 SRC_SLOW SRC_SLOW
+3VS_CLK VDDREF SB_SRC_SLOW#
EXT@ 66 1 INT@ 2 CPU_HT_CLKP [20]
GNDREF R214 1 INT@ 0_0402_5%
2 1 2 CPU_HT_CLKN [20]

1
C477 0.1U_0402_16V4Z R215 0_0402_5%
+VDDCLK_IO 12 56 R216
VDDSRC_IO CPUKG0T_LPRS CLK_CPU_BCLK [6]
18 55 CPU @ 8.2K_0402_5%
VDDSRC_IO CPUKG0C_LPRS CLK_CPU_BCLK# [6]
100mA 28
VDDATIG_IO
37

2
VDDSB_SRC_IO
53 VDDCPU_IO HTT0T_LPRS / 66 M 60 CLK_NBHT [11]
+3VS HTT0C_LPRS / 66 M
59 CLK_NBHT# [11] NB HT
C
100mA C
+3VS_CLK 3 VDDDOT 1 INT@ 2 NB_HT_CLKP [20]
17 40 R217 1 INT@ 0_0402_5%
2 NB_HT_CLKN [20]
VDDSRC SB_SRC0T_LPRS R218 0_0402_5%
29 39
VDDATIG SB_SRC0C_LPRS +3VS_CLK
R219 8.2K_0402_5%

R220 8.2K_0402_5%

R221 8.2K_0402_5%

R222 8.2K_0402_5%

38 VDDSB_SRC
44 VDDSATA
2

54 35
R1.0 L47 VDDCPU SB_SRC1T_LPRS
61 VDDHTT SB_SRC1C_LPRS 34
@ 1 2 69
EXP@ BLM18AG601SN1D_2P VDD48

2
EXT@ 33 CLK_NBGFX [11]
1

ATIG0T_LPRS R223 R224

ATIG0C_LPRS 32 CLK_NBGFX# [11] NB GFX
8.2K_0402_5% 8.2K_0402_5%
LAN 24 ATIG1 1 EXT@ 2 @ EXT@
[21,29] LAN_CLKREQ# CLKREQ0 # ATIG1# R225 1 EXT@ 0_0402_5% CLK_PEG_VGA [13]
31 2 CLK_PEG_VGA# [13]

1
ATIG1T_LPRS R226 0_0402_5%
Mini Card_WLAN [21,28] WLAN_CLKREQ# 51
CLKREQ1# ATIG1C_LPRS
30 VGA
1 INT@ 2 SEL_SATA
VGA_CLKP [20]
WWAN 50 R227 1 INT@ 0_0402_5%
2 VGA_CLKN [20]
[20,28] WWAN_CLKREQ# CLKREQ2#
26 R228 0_0402_5% 27M_SEL
ATIG2T_LPRS

2
NEW CARD [20,28] EXP_CLKREQ# 43
CLKREQ3# ATIG2C_LPRS
25
1 INT@ 2 GPP_CLK1P [20] R231
42 R229 1 INT@ 0_0402_5%
2 GPP_CLK1N [20] 8.2K_0402_5%
CLKREQ4# R230 0_0402_5% EXT@
SRC0T_LPRS
23 CLK_PCIE_LAN [29] GLAN
22 CLK_PCIE_LAN# [29]

1
SRC0C_LPRS
1 INT@ 2 GPP_CLK3P [20]
R232 1 INT@ 0_0402_5%
2 GPP_CLK3N [20]
EXT@ 27M_SEL R233 0_0402_5%
63
REF2/SEL_27 SRC1T_LPRS
21 CLK_PCIE_WLAN [28] MiniCard_WLAN
1 2 SRC1C_LPRS 20 CLK_PCIE_WLAN# [28]
R234 90.9_0402_1% SEL_SATA 64 1 INT@ 2
REF1/SEL_SATA GPP_CLK5P [20]
EXT@ R235 1 INT@ 0_0402_5%
2 CLK_XTAL_OUT
GPP_CLK5N [20]
CLK_14.318M R236 0_0402_5%
[11] CLK_NB_14.318M
1 2 65
REF0/SEL_HTT66 SRC2T_LPRS
16 CLK_PCIE_WWAN [28] MiniCard_WWAN CLK_XTAL_IN
R237 158_0402_1% 15
SRC2C_LPRS CLK_PCIE_WWAN# [28]
1 INT@ 2 GPP_CLK7P [20]
B R238 1 INT@ 0_0402_5% B
2 GPP_CLK7N [20]
71 14 R239 0_0402_5% New Card Change Y2 to
48MHz_0 SRC3T_LPRS CLK_PCIE_EXP [28]
EXT@ 13
CLK_48M SRC3C_LPRS CLK_PCIE_EXP# [28] TXC-SJ100009R00
2 1 70 48MHz_1
[21] CLK_48M_USB R240 33_0402_5% Y2 EXT@ <20ppm / 20pF>
10 CLK_SBLINK_BCLK [11] 2 1
SRC4T_LPRS
CLK_XTAL_IN SRC4C_LPRS
9 CLK_SBLINK_BCLK# [11] NB A LINK
67 14.318MHZ_16PF_7A14300083
X1
1 1
CLK_XTAL_OUT 68 8
X2 SRC5T_LPRS C478 EXT@ C479 EXT@
SRC5C_LPRS 7
33P_0402_50V8J 33P_0402_50V8J
2 2
6 46 CLK_SBSRC_BCLK [20]
GNDDOT SRC6T/SATAT_LPRS
11 GNDSRC SRC6C/SATAC_LPRS 45 CLK_SBSRC_BCLK# [20] SB RCLK Routing the trace at least 10mil
19
GNDSRC
27
GNDATIG CLK_SRC7C_SS @
36 5 1 2
GNDSB_SRC SRC7T_LPRS/27MHz_SS CLK_SRC7C R276 0_0402_5%
47 4
GNDSATA SRC7C_LPRS/27MHz_NS
52 1 EXT@ 2 27M_CLK 1 EXT@ 2 27M_NSSC [14] CLK_NB_14.318M
GNDCPU R277 0_0402_5% R548 0_0402_5%
58
GNDHTT
72 GND48 RS780 1.1V 158R/90.0R
73 57 2 EXT@ 1 +3VS_CLK 1 @ 2 VGA_DBCLK [34]
GNDPAD PD# R243 8.2K_0402_5% R271 0_0402_5%

1 * NON SPREAD 27M and SPREAD 27M output

SLG8SP626VTR_QFN72_10x10 EXT@ 27M_SEL
1 INT@ 2 CLK_SBLINK_BCLK 0 differential spread SRC_7 output
R244 0_0402_5%

CLK_SB#
1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN CLK_SB 1 INT@ 2 CLK_SBLINK_BCLK#
R246 0_0402_5% 1 single-ended 66MHz HTT output
2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN SEL_HTT66
A CLK_SBSRC_BCLK# A
1 INT@ 2 0* differential 100MHz HTT output
R248 0_0402_5%
1 INT@ 2 CLK_SBSRC_BCLK 1 NON SPREAD 100M SATA SRC6 output
R249 0_0402_5% SEL_SATA *
0 SPREAD 100M SATA SRC6 output
* default

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 19 of 48
5 4 3 2 1
 A B C D E

C572 1 2 150P_0402_50V8J U20A

R325 33_0402_5% P1
SB800 Part 1 of 5
W2
A_RST# T4 PAD PCIE_RST# PCICLK0
2 1 L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 [24]
W3

PCI CLKS
PCICLK2/GPO37 PCI_CLK2 [24] +3VALW
C579 1 2 0.1U_0402_16V7K SB_RX0P_C AD26 W4
[10] SB_RX0P A_TX0P PCICLK3/GPO38 PCI_CLK3 [24]
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1 C581
[10] SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 [24]
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28 1 2
[10] SB_RX1P A_TX1P
C575 1 2 0.1U_0402_16V7K SB_RX1N_C AC29 V2 AMD suggest add GPIO control gate
[10] SB_RX1N SB_RX2P_C A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K AB29 0.1U_0402_16V4Z
[10] SB_RX2P SB_RX2N_C A_TX2P
C580 1 2 0.1U_0402_16V7K AB28 [21] SB_GPIO_A_RST# 1 2
[10] SB_RX2N A_TX2N

5
C577 1 2 0.1U_0402_16V7K SB_RX3P_C AB26 AA1 R427 @ 0_0402_5% U21 @ NC7SZ08P5X_NL_SC70-5
[10] SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4 1 2 2

P
1 [10] SB_RX3N A_TX3N AD1/GPIO1 B 1
AD2/GPIO2 AA3 R425 0_0402_5%
Y 4 PLT_RST# PLT_RST# [11,12,13,28,29,34]
[10] SB_TX0P AE24 AB1 A_RST# 1
A_RX0P AD3/GPIO3 A

G
[10] SB_TX0N AE23 A_RX0N AD4/GPIO4 AA5

1
[10] SB_TX1P AD25 AB2

3
A_RX1P AD5/GPIO5 R328 R1.0

PCI EXPRESS INTERFACES

[10] SB_TX1N AD24 AB6
A_RX1N AD6/GPIO6 8.2K_0402_5% R1193 @
[10] SB_TX2P AC24 A_RX2P AD7/GPIO7 AB5
[10] SB_TX2N AC25 AA6 @ 100K_0402_5%
A_RX2N AD8/GPIO8
[10] SB_TX3P AB25 AC2

2
A_RX3P AD9/GPIO9 R430
[10] SB_TX3N AB24 A_RX3N AD10/GPIO10 AC3
AC4 1 2
R326 590_0402_1% AD29 AD11/GPIO11 0_0402_5%
2 1 PCIE_CALRP AD12/GPIO12 AC1
+1.1VS_PCIE R327 2 1 2K_0402_1% AD28 AD1
PCIE_CALRN AD13/GPIO13
AD14/GPIO14 AD2
[28] PCIE_SB_EXPCARD_TXP
0.1U_0402_16V7K 2 1 C210 EXPCARD_TXP_R AA28 AC6
EXP@ EXPCARD_TXN_R AA29 GPP_TX0P AD15/GPIO15
NEW CARD [28] PCIE_SB_EXPCARD_TXN
0.1U_0402_16V7K 2 1
GPP_TX0N AD16/GPIO16
AE2
C207 EXP@ Y29 AE1 Check the output status of control gate when power on!!
GPP_TX1P AD17/GPIO17
Y28 GPP_TX1N AD18/GPIO18 AF8
Y26 AE3
R1.0 GPP_TX2P AD19/GPIO19
Y27 GPP_TX2N AD20/GPIO20 AF1
W28 AG1
GPP_TX3P AD21/GPIO21
W29 AF2
GPP_TX3N AD22/GPIO22 PCI_AD23
AE9 PCI_AD23 [24]
AD23/GPIO23 PCI_AD24
[28] PCIE_EXPCARD_SB_RXP AA22 GPP_RX0P AD24/GPIO24 AD9 PCI_AD24 [22,24] PCI_AD24 : VDDR Voltage SW
NEW CARD Y21 AC11 PCI_AD25
[28] PCIE_EXPCARD_SB_RXN GPP_RX0N AD25/GPIO25 PCI_AD25 [24]
AA25 AF6 PCI_AD26
GPP_RX1P AD26/GPIO26 PCI_AD26 [24]
AA24 AF4 PCI_AD27 PCI_AD27 [24]
GPP_RX1N AD27/GPIO27 PCI_AD28
W23 AF3 PCI_AD28 [24]
GPP_RX2P AD28/GPIO28 PCI_AD29
V24 AH2 PCI_AD29 [24]
GPP_RX2N AD29/GPIO29
W24 GPP_RX3P AD30/GPIO30 AG2
W25 GPP_RX3N AD31/GPIO31 AH3
Workaround AA8 +3VS
CBE0# +1.5VS
Setting SpreadSpectrum =1 AD5

PCI INTERFACE
2 CBE1# 2
will enable spread spectrum CBE2# AD8

2
AA10
CBE3# R329
AE8
FRAME#
DEVSEL# AB9 4.7K_0402_5%

2
G
[19] CLK_SBSRC_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
[19] CLK_SBSRC_BCLK# P23 AE7

1
PCIE_RCLKN/NB_LNK_CLKN TRDY# H_PWRGD
PAR AC5 3 1 H_PWRGD_L [47]

D
[11] NB_DISP_CLKP U29 AF5
NB_DISP_CLKP STOP# Q21
[11] NB_DISP_CLKN U28 NB_DISP_CLKN PERR# AE6
AE4 FDV301N_NL_SOT23-3
SERR#
[19] NB_HT_CLKP T26 NB_HT_CLKP REQ0# AE11
[19] NB_HT_CLKN T27 AH5
NB_HT_CLKN REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41 AH4 level shift to ISL6265
[19] CPU_HT_CLKP V21 AC12 1 2 WWAN_CLKREQ# [19,28]
CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 INT@
[19] CPU_HT_CLKN T21 AD12
CPU_HT_CLKN GNT0# R527 0_0402_5%
GNT1#/GPO44
AJ5 ISL6265 PWROK input, TTL level: 0.8V~2.0V
[19] VGA_CLKP V23 AH6
SLT_GFX_CLKP GNT2#/GPO45
[19] VGA_CLKN T23
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46
AB12 1 2 EXP_CLKREQ# [19,28] When this pin is high, the SVI interface is
AB11 INT@
L29
CLKRUN#
AD7 R531 0_0402_5% active and I2C protocol is running. While this
GPP_CLK0P LOCK#
L28
GPP_CLK0N pin is low, the SVC, SVD, and VFIXEN input
AJ6
INTE#/GPIO32 states determine the pre-PWROK metal VID or
[19] GPP_CLK1P N29 AG6
GPP_CLK1P INTF#/GPIO33
LAN [19] GPP_CLK1N N28
GPP_CLK1N INTG#/GPIO34
AG4 VFIX mode voltage. This pin must be low prior
AJ4
INTH#/GPIO35
M29
GPP_CLK2P
to the ISL6265 PGOOD output going high
M28 GPP_CLK2N 22_0402_5%
T25 R330
[19] GPP_CLK3P GPP_CLK3P
CLOCK GENERATOR

WLAN V25 H24 LPCCLK0 1 2 LPC_CLK0_EC

[19] GPP_CLK3N GPP_CLK3N LPCCLK0 LPC_CLK0_EC [24,34]
H25 LPC_CLK1 [24]
LPCCLK1 R332 @ 20M_0402_5%
L24 J27 LPC_AD0 [28,34]
3 GPP_CLK4P LAD0 3
L23 GPP_CLK4N LAD1 J26 LPC_AD1 [28,34] 2 1
Close to SB LAD2 H29 LPC_AD2 [28,34]
LPC

[19] GPP_CLK5P P25 H28 LPC_AD3 [28,34]

GPP_CLK5P LAD3 C582 UMA@
WWAN [19] GPP_CLK5N M25 GPP_CLK5N LFRAME# G28 LPC_FRAME# [28,34]
SB_32KHI
J25 <BOM Structure> 2 1
LDRQ0#
P29 AA18
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 Y3 15P_0402_50V8J
P28 AB19 SERIRQ [34]
GPP_CLK6N SERIRQ/GPIO48

1
2 1
NC OSC R335
[19] GPP_CLK7P N26
GPP_CLK7P 20M_0603_5%
New Card [19] GPP_CLK7N N27 GPP_CLK7N 3 NC OSC 4
ALLOW_LDTSTP/DMA_ACTIVE# G21 ALLOW_LDTSTOP [11]
T29 H21 H_PROCHOT_R# [6] 32.768KHZ_12.5PF_Q13MC14610002

2
GPP_CLK8P PROCHOT# H_PWRGD SJ100006600 (MC-146) +-10PPM C586 UMA@
T28 GPP_CLK8N LDT_PG K19 H_PWRGD [6]
CPU

G22 SB_32KHO 2 1
LDT_STP# LDT_STOP# [6,11]
LDT_RST# J24 LDT_RST# [6]
L25 15P_0402_50V8J
14M_25M_48M_OSC
C1 SB_32KHI R1.0
32K_X1
1 2 25M_CLK_X1 L26 C2 SB_32KHO
25M_X1 32K_X2 +RTCBATT C582 DIS@ C586 DIS@
1

C689 1M_0603_5% D2
RTC

RTCCLK PAD T21

22P_0402_50V8J
INTRUDER_ALERT#
B2 W=20mils
Y6 R426 25M_CLK_X2 L27 B1 1 2
C688 25M_X2 VDDBT_RTC_G R333 510_0402_5%
2

22P_0402_50V8J @ C584 1 1 C585

1
0.1U_0402_16V4Z

1U_0402_6.3V4Z

1 2 SB820M_FCBGA605 12P_0402_50V8J 18P_0402_50V8J

CLRP1 @
25MHZ_20PF_7A25000012 SHORT PADS
SB820 A12(SA00003IW10)

2
2 2
for Clear CMOS
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820-PCIE/PCI/ACPI/LPC/RTC
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 20 of 48
A B C D E
 A B C D E

@ @
1 2 C587 1 2 100P_0402_25V8K
R337 100_0402_5%
U20D
J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 CLK_48M_USB [19]
0_0402_5% K1
RI#/GEVENT22#
[28] CPUSB# 1 R545 2 D3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP G19 USB_RCOMP 1 2
F1 Z=35ohm 11.8K_0402_1% R338
[34] PM_SLP_S3# SLP_S3#
[34] PM_SLP_S5# H1 SLP_S5#
F2

ACPI / WAKE UP EVENTS

[34] PBTN_OUT# PWR_BTN#
H5 SB800

USB 1.1 USB MISC

1 [6,11,34] SB_PWRGD SUS_STAT# PWR_GOOD 1
[11] SUS_STAT# G6 SUS_STAT# USB_FSD1P/GPIO186 J10
T24 PAD B3 TEST0 Part 4 of 5 USB_FSD1N H11
T22 PAD C4 TEST1/TMS OHCI4
T23 PAD F6 H9
TEST2 USB_FSD0P/GPIO185
[34] GATEA20 AD21 J8
GA20IN/GEVENT0# USB_FSD0N
[34] KB_RST# AE21 KBRST#/GEVENT1#
[34] EC_SCI# K2 B12
LPC_PME#/GEVENT3# USB_HSD13P
[34] EC_SMI# J29 LPC_SMI#/GEVENT23# USB_HSD13N A12
H2 GEVENT5#
+3VALW 2 R72 @ 1 SYS_RESET# J1 F11
SYS_RESET#/GEVENT19# USB_HSD12P USB20_P12 [37]
[28,29] SB_PCIE_WAKE# 20K_0402_5% H6 E11 Right USB(Sub b/d) EHCI13 / OHCI3
WAKE#/GEVENT8# USB_HSD12N USB20_N12 [37]
F3
+3VS H_THERMTRIP# IR_RX1/GEVENT20#
[6] H_THERMTRIP# J6 THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P E14 USB20_P11 [28]
[11] NB_PWRGD AC19
NB_PWRGD USB_HSD11N
E12 USB20_N11 [28] WLAN
CLK MODE SEL: 1-> INT CLK mode EC_RSMRST# G1 J12
0-> EXT CLK Mode [34] EC_RSMRST# RSMRST# USB_HSD10P USB20_P10 [28]
USB_HSD10N J14 USB20_N10 [28] WWAN
CLK_MODE AD19
R515 1 INT@ CLK_MODE CLK_REQ4#/SATA_IS0#/GPIO64
2 2.2K_0402_5% [19,28] WLAN_CLKREQ#
R516 1 INT@ 2 0_0402_5% AA16 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P A13
[20] SB_GPIO_A_RST# AB21 B13
GPIO60 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N
2 EXT@ 1 AC18
R593 100K_0402_5% CLK_REQ0#/SATA_IS3#/GPIO60
AF20 D13
SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P
AE19 SATA_IS5#/FANIN3/GPIO59 USB_HSD8N C13
[33] SB_SPKR AF19 SPKR/GPIO66 EHCI2 / OHCI2
SB_SMCLK0 AD22 G12
[8,9,19,28] SB_SMCLK0 SCL0/GPIO43 USB_HSD7P USB20_P7 [28]
SB_SMDAT0 New Card

USB 2.0
[8,9,19,28] SB_SMDAT0 AE22 SDA0/GPIO47 USB_HSD7N G14 USB20_N7 [28]
SB_SMCLK1 F5
+3VS UMA/DIS SEL FOR HDMI USE:High: DIS VGA Low: UMA VGA Cinfigure to output or SB_SMDAT1 SCL1/GPIO227
F4 G16 USB20_P6 [37]
reserve SDA1/GPIO228 USB_HSD6P
Internal PU/PD AH21 CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N G18 USB20_N6 [37] BT
1 @ 2 GPIO60 1 2 AB18
[19,29] LAN_CLKREQ# CLK_REQ1#/FANOUT4/GPIO61
R366 10K_0402_5% INT@ E1 D16 USB20_P5 [27]

GPIO
@ R517 0_0402_5% IR_LED#/LLB#/GPIO184 USB_HSD5P
1 2 AJ21
SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N
C16 USB20_N5 [27] Camera
2 R370 10K_0402_5% 2
H4 DDR3_RST#/GEVENT7#
D5 B14 USB20_P4 [37]
GBE_LED0/GPIO183 USB_HSD4P
D7
GBE_LED1/GEVENT9# USB_HSD4N
A14 USB20_N4 [37] ESATA and USB
G5 GBE_LED2/GEVENT10#
K3 GBE_STAT0/GEVENT11# USB_HSD3P E18
AA20 E16
CLK_REQG#/GPIO65/OSCIN USB_HSD3N
EHCI1 / OHCI1
J16 USB20_P2 [32]
USB_HSD2P
H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18 USB20_N2 [32] CardReader <Wake Up support>
EC_LID_OUT# D1
[34] EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6#
E4 USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P B17

USB OC
D4 A17
USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
Chcek leakage from SB internal pull-ups in S4/S5 states. F7 A16
USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_P0 [37]
[37] USB_OC#1 E7
USB_OC1#/TDI/GEVENT13# USB_HSD0N
B16 USB20_N0 [37] Left USB
[37] USB_OC#0 F8
R345 1 USB_OC0#/TRST#/GEVENT12#
[33] HDA_BITCLK_AUDIO 2 33_0402_5%

[24] HDA_SDOUT HDA_BITCLK M3 D25 Check SW:

R346 1 HDA_SDOUT AZ_BITCLK SCL2/GPIO193 Cinfigure to output or Internal PU/PD
[33] HDA_SDOUT_AUDIO 2 33_0402_5% N1 F23
HDA_SDIN0 AZ_SDOUT SDA2/GPIO194 Check SW:
[33] HDA_SDIN0 L2 B26 SB_SIC [6]
HDA_SDIN1 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 Cinfigure to output or Internal PU/PD
M2 E26

HD AUDIO
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 SB_SID [6]
M1 F25
AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
M4 E22
R347 1 HDA_SYNC AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
[33] HDA_SYNC_AUDIO 2 33_0402_5% N2 F22 GPIO199 [24]
AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199
R348 1 2 33_0402_5% HDA_RST#
P2 AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 E21 GPIO200 [24] STRAP PIN
[33] HDA_RST_AUDIO#
G24
GBE_COL KSI_0/GPIO201
T1 G25
GBE_CRS GBE_COL KSI_1/GPIO202
T4 E28
GBE_CRS KSI_2/GPIO203
L6 E29
3 GBE_MDIO GBE_MDCK KSI_3/GPIO204 3
L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 C29
GBE_RXD3 KSI_6/GPIO207
U3 GBE_RXD2 KSI_7/GPIO208 C28
T2
GBE_RXD1

GBE LAN
U2 B28
GBE_RXD0 KSO_0/GPIO209
T5 A27
+3VS GBE_RXERR GBE_RXCTL/RXDV KSO_1/GPIO210
V5 B27

EMBEDDED CTRL
EC_RSMRST# GBE_RXERR KSO_2/GPIO211
1 2 P5 D26
R339 2.2K_0402_5% GBE_TXCLK KSO_3/GPIO212
M5 GBE_TXD3 KSO_4/GPIO213 A26
1 @ 2 HDA_BITCLK R342 1 2 2.2K_0402_5% SB_SMCLK0 P9 C26
R349 10K_0402_5% GBE_TXD2 KSO_5/GPIO214
T7 A24
HDA_SDIN0 GBE_TXD1 KSO_6/GPIO215
1 @ 2 R343 1 2 2.2K_0402_5% SB_SMDAT0 P7 GBE_TXD0 KSO_7/GPIO216 B25
R350 10K_0402_5% M7 A25
@ HDA_SDIN1 R344 1 SUS_STAT# GBE_TXCTL/TXEN KSO_8/GPIO217
1 2 2 4.7K_0402_5% P4 GBE_PHY_PD KSO_9/GPIO218 D24
R351 10K_0402_5% M9 B24
GBE_PHY_INTR GBE_PHY_RST# KSO_10/GPIO219
V7 C24
GBE_PHY_INTR KSO_11/GPIO220
B23
KSO_12/GPIO221
E23 A23
PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
E24 D22
PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 C22
EMBEDDED CTRL

SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224
G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
B22
+3VALW KSO_17/GPIO226
D27 PS2KB_DAT/GPIO189
+3VALW F28
PS2KB_CLK/GPIO190
F29
GBE_MDIO PS2M_DAT/GPIO191
1 2 E27 PS2M_CLK/GPIO192
R352 10K_0402_5%
1 2 SB_PCIE_WAKE# 1 2 GBE_PHY_INTR
R355 10K_0402_5% R358 10K_0402_5% SB820M_FCBGA605
@ EC_LID_OUT#
1
R357
2
100K_0402_5% 1 2 GBE_COL SB820 A12(SA00003IW10)
4 SB_SIC R353 10K_0402_5% 4
1 2
R359 2.2K_0402_5% 1 2 GBE_CRS
1 2 SB_SID R354 10K_0402_5%
R360 2.2K_0402_5% 1 2 GBE_RXERR
1 2 H_THERMTRIP# R356 10K_0402_5%
R361 10K_0402_5%
1 2 SB_SMCLK1
R362 2.2K_0402_5%
1 2 SB_SMDAT1 Security Classification Compal Secret Data Compal Electronics, Inc.
R363 2.2K_0402_5% Issued Date 2008/10/06 2010/04/30 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 USB/HD audio
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 21 of 48
A B C D E
 A B C D E

U20B

AH9
SB800 AH28
1 [32] SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
[32] SATA_STX_DRX_N0 AJ9 SATA_TX0N Part 2 of 5 FC_FBCLKOUT AG28
HDD AJ8
FC_FBCLKIN AF26
[32] SATA_DTX_C_SRX_N0 SATA_RX0N
[32] SATA_DTX_C_SRX_P0 AH8 AF28
SATA_RX0P FC_OE#/GPIOD145
AG29
FC_AVD#/GPIOD146
[32] SATA_STX_DRX_P1 AH10 SATA_TX1P FC_WE#/GPIOD148 AG26
[32] SATA_STX_DRX_N1 AJ10 AF27
SATA_TX1N FC_CE1#/GPIOD149
ODD AG10
FC_CE2#/GPIOD150 AE29
AF29
[32] SATA_DTX_C_SRX_N1 SATA_RX1N FC_INT1/GPIOD144
[32] SATA_DTX_C_SRX_P1 AF10 AH27
SATA_RX1P FC_INT2/GPIOD147

[37] SATA_STX_DRX_P2 AG12 AJ27

SATA_TX2P FC_ADQ0/GPIOD128
[37] SATA_STX_DRX_N2 AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
e-SATA AJ12
FC_ADQ2/GPIOD130
AH25
AH24
[37] SATA_DTX_C_SRX_N2 SATA_RX2N FC_ADQ3/GPIOD131
[37] SATA_DTX_C_SRX_P2 AH12 AG23
SATA_RX2P FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133 AH23
AH14 AJ22
SATA_TX3P FC_ADQ6/GPIOD134
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
AF21
FC_ADQ8/GPIOD136
AG14 AH22
SATA_RX3N FC_ADQ9/GPIOD137
AF14 AJ23

FLASH
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 AJ25
SATA_TX4N FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142 AG25
AJ17 AH26
SATA_RX4N FC_ADQ15/GPIOD143
AH17
SATA_RX4P

SERIAL ATA
AJ18 SATA_TX5P
AH18 W5
SATA_TX5N FANOUT0/GPIO52
W6
2 FANOUT1/GPIO53 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19
SATA_RX5P
W7
R364 1K_0402_1% Z=35ohm FANIN0/GPIO56
FANIN1/GPIO57 V9
2 1 SATA_CALRP AB14 W8
SATA_CALRN SATA_CALRP FANIN2/GPIO58
+1.1VS_SATA 2 1 AA14
R365 931_0402_1% SATA_CALRN
TEMPIN0/GPIO171 B6
A6
TEMPIN1/GPIO172
[36] SATA_LED# AD11 SATA_ACT#/GPIO67 TEMPIN2/GPIO173 A5
B5
TEMPIN3/TALERT#/GPIO174
TEMP_COMM C7
+3VS R367 1 2 10K_0402_5% Check SW:
A3 Cinfigure to output or Internal PU/PD
VIN0/GPIO175
AD16 B4

HW MONITOR
T13 PAD SATA_X1 VIN1/GPIO176
A4
VIN2/GPIO177
C5
VIN3/GPIO178 MEM_1V5
A7
VIN4/GPIO179
B7
VIN5/GPIO180
B8
VIN6/GBE_STAT3/GPIO181
AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8
T15 PAD

J5 G27
SPI_DI/GPIO164 NC1
E2 Y2
SPI_DO/GPIO163 NC2

SPI ROM
K4 SPI_CLK/GPIO162
K9
SPI_CS1#/GPIO165
G2
ROM_RST#/GPIO161

SB820M_FCBGA605
3 3

SB820 A12(SA00003IW10)

MEM_1V5 is for gating the

glitch on PCI_AD24
+3VS
C685
2 1

0.1U_0402_16V4Z

5
U22
MEM_1V5 2

P
B
4 1 2 VDDR_SW [45]
Y R424 33_0402_5%
[20,24] PCI_AD24 1 2 1 A

G
R422 0_0402_5% 2
NC7SZ08P5X_NL_SC70-5

3
C686
150P_0402_50V8J
1
1 @ 2
PCI_AD24 R423 0_0402_5%
1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 SATA/IDE/SPI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 22 of 48
A B C D E
 A B C D E

U20E
+1.1VS_VDDC
510mA SB800
1 2 +1.1VS Y14 VSSIO_SATA_1 VSS_1 AJ2
U20C R369 0_0805_5% Y16 A28
VSSIO_SATA_2 VSS_2
131mA SB800 Part 3 of 5 AB16 VSSIO_SATA_3 VSS_3 A2
+3VS AH1 N13 10U_0603_6.3V6M 1 2 C590 AC14 E5
VDDIO_33_PCIGP_1 VDDCR_11_1 VSSIO_SATA_4 VSS_4
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 AE12 VSSIO_SATA_5 VSS_5 D23
C591 1 2 10U_0603_6.3V6M Y19 N17 1U_0402_6.3V4Z 2 1 C596 AE14 E25
VDDIO_33_PCIGP_3 VDDCR_11_3 1U_0402_6.3V4Z C594 VSSIO_SATA_6 VSS_6

CORE S0
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13 2 1 AF9 VSSIO_SATA_7 VSS_7 E6
1 C592 0.1U_0402_16V4Z 0.1U_0402_16V4Z C597 1
1 2 AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 2 1 AF11 VSSIO_SATA_8 VSS_8 F24
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF13 N15
C599 0.1U_0402_16V4Z VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_9 VSS_9

PCI/GPIO I/O
1 2 AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 AF16 VSSIO_SATA_10 VSS_10 R13
AC8 W12 AG8 R17
VDDIO_33_PCIGP_8 VDDCR_11_8 VSSIO_SATA_11 VSS_11
AA7 W18 AH7 T10
VDDIO_33_PCIGP_9 VDDCR_11_9 VSSIO_SATA_12 VSS_12
AA9 VDDIO_33_PCIGP_10 AH11 VSSIO_SATA_13 VSS_13 P10
+1.1VS_CKVDD L69
AF7
VDDIO_33_PCIGP_11 400mA AH13
VSSIO_SATA_14 VSS_14
V11
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 2 1 +1.1VS AH16 VSSIO_SATA_15 VSS_15 U15
K29 FBMA-L11-201209-221LMA30T_0805 AJ7 M18
VDDAN_11_CLK_2 VSSIO_SATA_16 VSS_16
J28 AJ11 V19
VDDAN_11_CLK_3 10U_0603_6.3V6M VSSIO_SATA_17 VSS_17
VDDAN_11_CLK_4 K26 1 2 C595 AJ13 VSSIO_SATA_18 VSS_18 M11
71mA J21 AJ16 L12

CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_19 VSS_19
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 VSS_20 L18
1U_0402_6.3V4Z C601

FLASH I/O
AE25 K21 2 1 A9 J7
VDDIO_18_FC_2 VDDAN_11_CLK_7 0.1U_0402_16V4Z C602 VSSIO_USB_1 VSS_21
AF24 J22 2 1 B10 P3
VDDIO_18_FC_3 VDDAN_11_CLK_8 0.1U_0402_16V4Z C603 VSSIO_USB_2 VSS_22
1 2 AC22 2 1 K11 V4
R371 0_0402_5% VDDIO_18_FC_4 VSSIO_USB_3 VSS_23
B9 VSSIO_USB_4 VSS_24 AD6
V1 D10 AD4
VDDRF_GBE_S VSSIO_USB_5 VSS_25
D12 AB7
+VDDPL_3V_PCIE POWER VDDIO_33_GBE_S
M10 D14
VSSIO_USB_6
VSSIO_USB_7
VSS_26
VSS_27
AC9
43mA D17
VSSIO_USB_8 VSS_28
V8
AE28 E9 W9
VDDPL_33_PCIE VSSIO_USB_9 VSS_29

GBE LAN
+1.1VS_PCIE F9 W10
L70 R1.0 VSSIO_USB_10 VSS_30
600mA F12 VSSIO_USB_11 VSS_31 AJ28

PCI EXPRESS
+1.1VS 2 1 U26 L7 F14 B29
FBMA-L11-201209-221LMA30T_0805 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 VSSIO_USB_12 VSS_32
V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9 F16 VSSIO_USB_13 VSS_33 U4
V26 C9 Y18
C604 22U_0805_6.3V6M VDDAN_11_PCIE_3 VSSIO_USB_14 VSS_34
1 2 V27 G11 Y10
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 VSSIO_USB_15 VSS_35

GROUND
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 F18 VSSIO_USB_16 VSS_36 Y12
C606 1 2 0.1U_0402_16V4Z V29 P8 D9 Y11
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_17 VSS_37
1 2 W22 H12 AA11
VDDAN_11_PCIE_7 VSSIO_USB_18 VSS_38
W26 H14 AA12
2 VDDAN_11_PCIE_8 VSSIO_USB_19 VSS_39 2
H16 VSSIO_USB_20 VSS_40 G4
+VDDPL_3V_SATA H18 J4
+3VALW VSSIO_USB_21 VSS_41
93mA J11
VSSIO_USB_22 VSS_42
G8
+1.1VS_SATA
AD14 VDDPL_33_SATA 32mA J19 VSSIO_USB_23 VSS_43 G9
L71 A21 K12 M12
VDDIO_33_S_1 VSSIO_USB_24 VSS_44
+1.1VS 2 1 AJ20 D21 K14 AF25
FBMA-L11-201209-221LMA30T_0805 VDDAN_11_SATA_1 VDDIO_33_S_2 2.2U_0603_6.3V4Z C608 VSSIO_USB_25 VSS_45
567mA AF18 VDDAN_11_SATA_4 VDDIO_33_S_3 B21 1 2 K16 VSSIO_USB_26 VSS_46 H7

SERIAL ATA
AH20 K10 2.2U_0603_6.3V4Z 1 2 C609 K18 AH29
C610 22U_0805_6.3V6M VDDAN_11_SATA_2 VDDIO_33_S_4 VSSIO_USB_27 VSS_47
1 2 AG19 L10 H19 V10

3.3V_S5 I/O
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_28 VSS_48
1 2 AE18 J9 P6
C612 1U_0402_6.3V4Z VDDAN_11_SATA_5 VDDIO_33_S_6 +1.1VALW VSS_49
1 2 AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6 VSS_50 N4
C613 1 2 0.1U_0402_16V4Z AE16 T8 Y4 L4
C614 0.1U_0402_16V4Z VDDAN_11_SATA_7 VDDIO_33_S_8 EFUSE VSS_51
1 2 VSS_52 L8
D8
C615 2 VSSAN_HWM
113mA 1 1U_0402_6.3V4Z
L72 +AVDD_USB C616 2 1 1U_0402_6.3V4Z
658mA
CORE S5

F26 M19 M20

VDDCR_11_S_1 VSSXL VSSPL_SYS
+3VALW 2 1 A18 G26
FBMA-L11-201209-221LMA30T_0805 VDDAN_33_USB_S_1 VDDCR_11_S_2
A19
VDDAN_33_USB_S_2 TBD
A20 M8 +VDDIO_AZ P21 H23
C617 10U_0603_6.3V6M VDDAN_33_USB_S_3 VDDIO_AZ_S +1.1VALW VSSIO_PCIECLK_1 VSSIO_PCIECLK_14
1 2 B18 VDDAN_33_USB_S_4 P20 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15 H26
C618 10U_0603_6.3V6M +VDDCR_USB
1 2 B19
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1
A11 197mA M22
VSSIO_PCIECLK_3 VSSIO_PCIECLK_16
AA21
C619 1 2 1U_0402_6.3V4Z B20 B11 2 1 M24 AA23
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
USB I/O

C620 1 2 1U_0402_6.3V4Z C18 L73 FBMA-L11-160808-221LMT 0603 M26 AB23

C621 0.1U_0402_16V4Z VDDAN_33_USB_S_7 C622 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18
1 2 C20 47mA 1 2 10U_0805_10V4Z P22 AD23
VDDAN_33_USB_S_8 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19
D18 M21 +VDDPL_3V P24 AA26
VDDAN_33_USB_S_9 VDDPL_33_SYS C623 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20
D19 62mA 2 1 0.1U_0402_16V4Z P26 AC26
VDDAN_33_USB_S_10 C624 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 +VDDPL_11V 2 1 0.1U_0402_16V4Z T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20
E19
VDDAN_33_USB_S_12 17mA T22
VSSIO_PCIECLK_10 VSSIO_PCIECLK_23
W21
PLL

F19 +VDDPL_3V_USB T24 W20

L74 +1.1V_USB VDDPL_33_USB_S VSSIO_PCIECLK_11 VSSIO_PCIECLK_24
200mA 5mA +3VALW
V20
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
AE26
+1.1VALW 2 1 C11 D6 +3V_HWM J23 L21
FBMA-L11-160808-221LMT 0603 VDDAN_11_USB_S_1 VDDAN_33_HWM_S +VDDLX_3V VSSIO_PCIECLK_13 VSSIO_PCIECLK_26
3
D11
VDDAN_11_USB_S_2 197mA VSSIO_PCIECLK_27
K20
3
VDDXL_33_S L20 2 1
C625 2 1 2.2U_0603_6.3V4Z L75 FBMA-L11-160808-221LMT 0603 Part 5 of 5
C626 2 1 0.1U_0402_16V4Z C627 1 2 2.2U_0603_6.3V4Z
SB820M_FCBGA605 SB820M_FCBGA605

SB820 A12(SA00003IW10) SB820 A12(SA00003IW10)

+VDDPL_11V +1.1VALW +VDDPL_3V_USB +3VALW +3V_HWM +3VALW

+VDDPL_3V_PCIE +3VS +VDDPL_3V +3VS
L76 L77 L78
L79 L80 2 1 2 1 2 1
2 1 2 1 FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
1 1 1 1 1
1 1 1 C630 C632
C628 C629 C631 C633
C634 C635 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
0.1U_0402_16V4Z 2 2 2 2 2
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2

+VDDPL_3V_SATA +3VS +VDDIO_AZ +3VALW

L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5%

1 1 1
C636
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 23 of 48
A B C D E
 A B C D E

REQUIRED STRAPS Check Internal PU/PD

AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LCP_CLK1 GPIO200 GPIO199

PULL LOW POWER ALLOW PCIE WATCHDOG USE CPU/HT CLK EC CLOCKGEN
MODE GEN2 TIMER DEBUG SEL ENABLE ENABLE H,H = Reserved
HIGH
ENABLE STRAP Enable
1 H,L = SPI ROM 1

L,H = LPC ROM (Default L,NC)

PULL Performance FORCE PCIE WATCHDOG IGNORE CPU/HT CLK EC CLOCKGEN
LOW MODE GEN1 TIMER DEBUG SEL DISABLE DISABLE L,L = FWH ROM
DISABLE STRAP Disable
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

+VDDIO_AZ +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%
R385
R377

R378

R379

R380

R381

R382

R383

R384
INT@ INT@

2
@ @ @ @ @ @
[21] HDA_SDOUT
[20] PCI_CLK1
[20] PCI_CLK2
[20] PCI_CLK3
[20] PCI_CLK4
[20,34] LPC_CLK0_EC
[20] LPC_CLK1
[21] GPIO200
2 [21] GPIO199 2

2.2K_0402_5%
1

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%
R393

R394
R386

R387

R388

R389

R390

R391

R392
EXT@ EXT@ @
2

2
+3VS +3VS

DEBUG STRAPS

10K_0402_5%

10K_0402_5%
1

1
R395

R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI [20] PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT [20] PCI_AD28
HIGH [20] PCI_AD27
[20] PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
[20] PCI_AD25
[20,22] PCI_AD24
[20] PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R397

R398

R399

R400

R401
2

2
Check AD29,AD28 strap function @ @ @ @ @
check default

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB820 STRAPS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 24 of 48
A B C D E
 A B C D E

W=40mils
+5VS +R_CRT_VCC +CRT_VCC

CRT Connector

2
D11 F1 W=40mils
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1 1
1
D6 D7
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C550
@ @ 0.1U_0402_16V4Z
2

1
CRT_R L62 1 2 FCM2012CF-800T06_2P CRT_R_2 JCRT1
6
11
CRT_G L63 1 2 FCM2012CF-800T06_2P CRT_G_2 1
7
12
CRT_B L64 1 2 FCM2012CF-800T06_2P CRT_B_2 2
8
13

1
R549 1 1 1 1 1 1 3
R549 R541 R550 C551 C552 C553 C554 C555 C556 9
R549 14 G 16
UMA@ 140 Ohm UMA@ 150_0402_1% 4 G 17
2 2 2 2 2 2 10
DIS @ 150 Ohm
2

2
140_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
150_0402_1% 10P_0402_50V8J 1 5
DIS@ 150_0402_1% 10P_0402_50V8J C557
ME@ TYCO_1775763-1
100P_0402_50V8J
2
+CRT_VCC
L65 1 2 CRT_HSYNC_2
C558 1 2 0.1U_0402_16V4Z R551 2 1 10K_0402_5% FCM2012CF-800T06_2P DSUB_12
2 2
L66 1 2 CRT_VSYNC_2 1
5

U17 FCM2012CF-800T06_2P 1 1
OE#
P

CRT_HSYNC 2 4 CRT_HSYNC_1 C559 C560 DSUB_15

A Y 10P_0402_50V8J 10P_0402_50V8J C561 2
G

2 2 68P_0402_50V8J 1
74AHCT1G125GW_SOT353-5
3

C562
+CRT_VCC 68P_0402_50V8J
2
C563 1 2 0.1U_0402_16V4Z
5

U18
OE#
P

CRT_VSYNC 2 4 CRT_VSYNC_1
A Y
G

74AHCT1G125GW_SOT353-5
3

Close to Conn side

+CRT_VCC

3 For UMA Only +3VS 3

GMCH_CRT_R R677 2 UMA@ 1 0_0402_5% CRT_R
[11] GMCH_CRT_R

1
GMCH_CRT_G R542 2 UMA@ 1 0_0402_5% CRT_G
[11] GMCH_CRT_G
R457 R553
GMCH_CRT_B R679 2 UMA@ 1 0_0402_5% CRT_B 4.7K_0402_5% 4.7K_0402_5%
[11] GMCH_CRT_B
GMCH_CRT_HSYNC R547 2 UMA@ 1 0_0402_5% CRT_HSYNC NOTE:
[11,12] GMCH_CRT_HSYNC

2
GMCH_CRT_VSYNC R543 2 UMA@ 1 0_0402_5% CRT_VSYNC IF RS880M ONLY(NO MXM SUPPORT),
[11,12] GMCH_CRT_VSYNC DAC_SDAT AND DAC_SCL DON'T DSUB_12 CRT_DATA
6 1
GMCH_CRT_DATA R546 2 UMA@ 1 0_0402_5% CRT_DATA NEED LEVEL SHIFT, PU TO +5V DIRECTLY.
[11] GMCH_CRT_DATA
DIS@ Q87A
DAC_SDAT AND DAC_SCL ARE 5V TOLERANCE.

5
GMCH_CRT_CLK R678 2 UMA@ 1 0_0402_5% CRT_CLK 2N7002DW-T/R7_SOT363-6
[11] GMCH_CRT_CLK
DSUB_15 3 4 CRT_CLK

DIS@ Q87B
For VGA Only 2N7002DW-T/R7_SOT363-6
VGA_CRT_R R539 2 DIS@ 1 0_0402_5% CRT_R
[14] VGA_CRT_R
2 UMA@1
VGA_CRT_G R552 2 DIS@ 1 0_0402_5% CRT_G R676 0_0402_5%
[14] VGA_CRT_G
VGA_CRT_B R554 2 DIS@ 1 0_0402_5% CRT_B
[14] VGA_CRT_B
2 UMA@1
VGA_CRT_HSYNC R535 2 DIS@ 1 0_0402_5% CRT_HSYNC R544 0_0402_5%
[14] VGA_CRT_HSYNC
VGA_CRT_VSYNC R557 2 DIS@ 1 0_0402_5% CRT_VSYNC
[14] VGA_CRT_VSYNC
VGA_CRT_DATA R538 2 DIS@ 1 0_0402_5% CRT_DATA
[14] VGA_CRT_DATA
VGA_CRT_CLK R556 2 DIS@ 1 0_0402_5% CRT_CLK
4 [14] VGA_CRT_CLK 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 25 of 48
A B C D E
 5 4 3 2 1

+3VS +3VS +HDMI_5V_OUT

W=40mils +HDMI_5V_OUT
D9
HDMI@ R799 @
+5VS 2 1 +HDMI_5V_OUT_1 1 2

10K_0402_5%

10K_0402_5%
HDMI_DIS@

HDMI_DIS@
0_1206_5% 1

1
R476 R529 RB491D_SC59-3 C568 HDMI@
R460 R459 HDMI@ HDMI@ 1 2 0.1U_0402_16V4Z
HDMI_DIS@ 2K_0402_5% 2K_0402_5% R443
1 2 Q88A R1.0 HDMI@ 2
[14] VGA_HDMI_SCLK

2
R498 0_0402_5% HDMI_DIS@ 0_0805_5%

2
D HDMI_SCLK_1 2 R477 1 HDMI_SCLK D
[11] GMCH_HDMI_CLK 1 6
0_0402_5%
HDMI_DIS@ 2N7002DW-T/R7_SOT363-6 HDMI@

5
1 2 2N7002DW-T/R7_SOT363-6 JHDMI1
[14] VGA_HDMI_SDATA R499 0_0402_5% Q88B R469 HDMI_HPD 19
HDMI_SDATA_1 2 HDMI_SDATA HP_DET
[11] GMCH_HDMI_DATA 4 3 HDMI_DIS@ 1 +HDMI_5V_OUT 18 +5V
0_0402_5% 17
HDMI_SDATA DDC/CEC_GND
HDMI@ 16 SDA
HDMI_SCLK 15
HDMI_UMA@ SCL
2 1
Place closed to JHDMI1 14
13
Reserved
R718 0_0402_5% HDMI_R_CK- CEC
12 20
CK- GND
11 CK_shield GND 21
HDMI_UMA@ HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
2 1 9 23
R606 0_0402_5% D0- GND
8
HDMI_R_D0+ D0_shield
7 D0+
HDMI_R_D1- 6
D1-
5 D1_shield
HDMI_R_D1+ 4
HDMI_R_D2- D1+
3
D2-
2
0_0402_5%1 R490 2 HDMI_UMA@ HDMI_TX2+ HDMI_R_D2+ D2_shield
[10] UMA_HDMI_P0 1 D2+
0_0402_5%1 R497 2 HDMI_UMA@ HDMI_TX2-
[10] UMA_HDMI_N0
TAITW_PDVBR9-19FLBS4NN4N1
0_0402_5%1 R491 2 HDMI_UMA@ HDMI_TX1+ ME@
[10] UMA_HDMI_P1 HDMI_TX1-
0_0402_5%1 R492 2 HDMI_UMA@
[10] UMA_HDMI_N1
R1.0
0_0402_5%1 R494 2 HDMI_UMA@ HDMI_TX0+
[10] UMA_HDMI_P2
0_0402_5%1 R493 2 HDMI_UMA@ HDMI_TX0-
[10] UMA_HDMI_N2
0_0402_5%1 R495 2 HDMI_UMA@ HDMI_CLK+
C [10] UMA_HDMI_P3 HDMI_CLK- C
0_0402_5%1 R496 2 HDMI_UMA@
[10] UMA_HDMI_N3

C569 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_TX2+ HDMI_UMA@1 R479

HDMI_UMA@ 2 715_0402_1% +3VS
[14] VGA_HDMI_TXD2+ HDMI_TX2-
C570 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_UMA@1 R480 2 715_0402_1%
[14] VGA_HDMI_TXD2-
C571 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_TX1+ HDMI_UMA@1 R484 2 715_0402_1%
[14] VGA_HDMI_TXD1+ HDMI_TX1-
C700 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_UMA@1 R481 2 715_0402_1%
[14] VGA_HDMI_TXD1-

1
Q20 C R474 HDMI@
C699 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_TX0+ HDMI_UMA@1 R486 2 715_0402_1% HDMI@ HDMI_HPD
[14] VGA_HDMI_TXD0+
C702 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_TX0- HDMI_UMA@1 R485 2 715_0402_1%
Place closed to JHDMI1 MMBT3904_NL_SOT23-3 B
2 1 2
150K_0402_5%
[14] VGA_HDMI_TXD0- E

1
C701 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_CLK+ HDMI_UMA@1 R488 2 715_0402_1%
[14] VGA_HDMI_TXC+ [11,14] HDMI_DET
C698 2 1 HDMI_DIS@ 0.1U_0402_16V7K HDMI_CLK- HDMI_UMA@ R487
HDMI_UMA@1 2 715_0402_1%
[14] VGA_HDMI_TXC-

1
1
D R470 @
2N7002_SOT23 R478
+HDMI_5V_OUT 2 365K_0402_1%

2
R479 R480 R484 R481 G Q78 HDMI@ 10K_0402_5%

1
S HDMI@

2
R526
HDMI@
100K_0402_5%

2
499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1%

HDMI_DIS@ HDMI_DIS@ HDMI_DIS@ HDMI_DIS@

R486 R485 R488 R487 HDMI_CLK- R475 1 HDMI@ 2 0_0402_5% HDMI_R_CK-

UMA use 715 ohm
B
VGA use 499 ohm L67
1
1 2
2
B
WCM-2012-900T_0805
@ 4 3
4 3
499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1%
HDMI_CLK+ R463 1 HDMI@ 2 0_0402_5% HDMI_R_CK+
HDMI_DIS@ HDMI_DIS@ HDMI_DIS@ HDMI_DIS@
HDMI_TX0- R530 1 HDMI@ 2 0_0402_5% HDMI_R_D0-

4 4 3 3
@
WCM-2012-900T_0805 reverse for layout
L68 1 2
1 2
HDMI_TX0+ R532 1 HDMI@ 2 0_0402_5% HDMI_R_D0+

HDMI_TX1- R533 1 HDMI@ 2 0_0402_5% HDMI_R_D1-

1 2
L86 1 2
WCM-2012-900T_0805
@ 4 3
4 3
HDMI_TX1+ R467 1 HDMI@ 2 0_0402_5% HDMI_R_D1+

HDMI_TX2- R528 1 HDMI@ 2 0_0402_5% HDMI_R_D2-

4 3
@ 4 3
WCM-2012-900T_0805
A L85 1 2 A
1 2
HDMI_TX2+ R468 1 HDMI@ 2 0_0402_5% HDMI_R_D2+

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 26 of 48
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD +5VALW

+3VS

W=60mils CMOS Camera

1
R421 R435
150_0603_1% 100K_0402_5% +5VS Q23 AO3413_SOT23-3
1
C589

D
4.7U_0805_10V4Z 3 1
D D
1

2
1

1
D R433 220K_0402_5%
S
2 CMOS@
G
2 1 2 2 CMOS@ C687

G
2
Q25 G R419 R420 0.1U_0402_16V4Z
2N7002_SOT23 S D AO3413_SOT23-3 100K_0402_5% CMOS@ 0_0603_5% 2 CMOS@
1

1
1
DTC124EK C681 Q26 R604 CMOS@

2
W=60mils 150K_0402_5%

OUT
0.1U_0402_16V4Z 1 2 +CMOS_PW
2 +LCDVDD +LCDVDD_CONN
L84 1 1

1
R434 2 1 0_0402_5% LCD_ENVDD 2 C683
[11] GMCH_ENVDD IN
UMA@ 1 2 CMOS@ C682

GND

OUT
0.01U_0402_16V7K 10U_0805_10V4Z
Q27 FBMA-L11-201209-221LMA30T_0805 2 2 @

2
R428 2 1 0_0402_5% DTC124EKAT146_SC59-3 1 1 2
[13] VGA_ENVDD [34] CMOS_OFF#

3
DIS@ C680 C678 IN

GND
R432
2.2K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 DTC124EKAT146_SC59-3 Q24

3
CMOS@

R1.0
C +INVPWR_B+ +INVPWR_B+ R437 B+ C
0_0603_5%
1 2
W=40mils R440 @
1 1 0_0805_5%
1 2
C691@ C692
INVT_PWM 1 2 INVT_PWM_R 680P_0402_50V7K 4.7U_0805_25V6-K
[34] INVT_PWM 2 2
R451 0_0402_5%
+CMOS_PW

1
VGA_PNL_PWM 1 @ 2 JLVDS1
[13] VGA_PNL_PWM +LCDVDD_CONN
R450 0_0402_5% R442 2 1
2 1
10K_0402_5% 4 4 3 3 USB20_N5 [21]
GMCH_INVT_PWM 1 @ 2 W=60mils 6 5 CMOS
[11] GMCH_INVT_PWM 6 5 USB20_P5 [21]
R452 0_0402_5% 8 7
2
8 7 TXOUT0-
10 9
10 9 TXOUT0+
12 11
12 11
+3VS 14 13
14 13 TXOUT1-
16 15
@ INVT_PWM_R 16 15 TXOUT1+
1 18 18 17 17
680P_0402_50V7K DISPOFF# 20 19
C690 20 19 TXOUT2-
22 21
VGA ONLY 2
[34] DAC_BRIG
24
22
24
21
23
23 TXOUT2+
26 25
26 25 TXCLK-
28 27
+3VS 28 27 TXCLK+
30 29
30 29
32 31
GNDGND
R436 R438 ACES_87142-3041
2.2K_0402_5% 2.2K_0402_5% ME@
TXCLK- DIS@ 1 R466 2 0_0402_5% @
B VGA_TXCLK- [13] @ B
TXCLK+ DIS@ 1 R505 2 0_0402_5%
VGA_TXCLK+ [13]
I2CC_SCL
TXOUT2- DIS@ 1 R509 2 0_0402_5% I2CC_SDA
TXOUT2+ VGA_TXOUT2- [13]
DIS@ 1 R510 2 0_0402_5%
VGA_TXOUT2+ [13]
TXOUT1+ DIS@ 1 R511 2 0_0402_5%
VGA_TXOUT1+ [13]
TXOUT1- DIS@ 1 R512 2 0_0402_5%
VGA_TXOUT1- [13]
TXOUT0+ DIS@ 1 R513 2 0_0402_5%
VGA_TXOUT0+ [13]
TXOUT0- DIS@ 1 R514 2 0_0402_5%
VGA_TXOUT0- [13]

I2CC_SCL DIS@ 2 R455 1 0_0402_5% VGA_LCD_CLK [14] +3VS

I2CC_SDA DIS@ 2 R441 1 0_0402_5%
VGA_LCD_DAT [14]
INVT_PWM_R

UMA ONLY
1
DAC_BRIG
R429

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
TXCLK- UMA@1 R521 2 0_0402_5% D10 DISPOFF#
TXCLK+ GMCH_TXCLK- [11]
UMA@1 R537 2 0_0402_5% CH751H-40PT_SOD323-2 4.7K_0402_5%
GMCH_TXCLK+ [11]
C675
2

TXOUT2- UMA@1 R555 2 0_0402_5% BKOFF# 1 2 DISPOFF# 1 @ 1 @ 1 @

TXOUT2+ GMCH_TXOUT2- [11] [34] BKOFF#
UMA@
UMA@1 R540 2 0_0402_5% C677 C676
GMCH_TXOUT2+ [11]
TXOUT1+ UMA@1 R603 2 0_0402_5%
GMCH_TXOUT1+ [11]
2

TXOUT1- UMA@1 R600 2 0_0402_5% 2 2 2

GMCH_TXOUT1- [11]
R431
TXOUT0+ UMA@1
UMA@ R602 2 0_0402_5% 10K_0402_5% For EMI
TXOUT0- GMCH_TXOUT0+ [11]
UMA@1 R601 2 0_0402_5%
GMCH_TXOUT0- [11]
1

I2CC_SCL UMA@2 R453 1 0_0402_5%

A GMCH_LCD_CLK [11] A
I2CC_SDA UMA@2 R454 1 0_0402_5% GMCH_LCD_DATA [11]

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 27 of 48
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half) Reserve for SW mini-pcie debug card.

+3VALW Series resistors closed to KBC side.
+3VS
R1.0 1 LPC_FRAME#_R R644 1 @ 2 0_0402_5% LPC_FRAME#
+1.5VS LPC_FRAME# [20,34]
LPC_AD3_R R645 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 [20,34]
JP10 C814 @ LPC_AD2_R R647 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 [20,34]
SB_PCIE_WAKE# R648 1 @ 2 0_0402_5% 1 2 0.1U_0402_16V4Z LPC_AD1_R R649 1 @ 2 0_0402_5% LPC_AD1
[21,29] SB_PCIE_WAKE# WAKE# 3.3V 2 LPC_AD1 [20,34]
[37] BT_ACTIVE BT_ACTIVE R650 1 @ 2 0_0402_5% 3 4 LPC_AD0_R R651 1 @ 2 0_0402_5% LPC_AD0
NC GND LPC_AD0 [20,34]
5 6 PCI_RST#_R R652 1 @ 2 0_0402_5% PLT_RST#
NC 1.5V PLT_RST# [11,12,13,20,29,34]
[19,21] WLAN_CLKREQ# 7 8 LPC_FRAME#_R
CLKREQ# NC LPC_AD3_R
9 10
GND NC LPC_AD2_R
[19] CLK_PCIE_WLAN# 11 12
1 REFCLK- NC LPC_AD1_R 1
[19] CLK_PCIE_WLAN 13 14
REFCLK+ NC LPC_AD0_R
15 16
PCI_RST#_R GND NC
17 18
NC GND R653 1 0_0402_5%
19 20 2 WL_OFF# [34]
NC NC PLT_RST#
21 22 PLT_RST# [11,12,13,20,29,34]
GND PERST# R654 1
[10] PCIE_PTX_C_IRX_N1 23 24 2 @ 0_0402_5% +3VALW
PERn0 +3.3Vaux R655 1 0_0402_5%
[10] PCIE_PTX_C_IRX_P1 25 26 2 +3VS
PERp0 GND
27 28
GND +1.5V R656 1
29 30 2 @ 0_0402_5% SB_SMCLK0 [8,9,19,21]
GND SMB_CLK R657 1
[10] PCIE_ITX_C_PRX_N1 31 32 2 @ 0_0402_5% SB_SMDAT0 [8,9,19,21]
PETn0 SMB_DATA
[10] PCIE_ITX_C_PRX_P1 33 34
PETp0 GND
35 36 USB20_N11 [21]
+3VS GND USB_D-
37
NC USB_D+
38 USB20_P11 [21] WLAN
39 40
NC GND R658 1
41 42 2 0_0402_5%
NC LED_WWAN# R659 1 WLAN_LED#
43 44 2 WLAN_LED# [36]
NC LED_WLAN# 0_0402_5%
45 46
R660 100_0402_1% NC LED_WPAN#
47 48
EC_TX_P80_DATA 1 NC +1.5V
[34,35] EC_TX_P80_DATA 2 49 50
EC_RX_P80_CLK 1 NC GND
[34,35] EC_RX_P80_CLK 2 51 52
R661 100_0402_1% NC +3.3V
53 54
GND GND

2
R719
100K_0402_5% TAITW_PFPET0-AFGLBG1ZZ4N0
ME@

1
Mini-Express Card for WWAN(Full)
2 +3VS 2
R1.0 D23 @
Mini-Express Card(WWAN 3G) +3VS CM1293-04SO_SOT23-6
@
1 4 UIM_DATA 2 1 +UIM_PWR
+1.5VS CH1 CH4 R663
1 1
JP9 @ 3G@ +3VS 10K_0402_5%
SB_PCIE_WAKE# R664 1 @ 2 0_0402_5% 1 2 C815 C816
BT_ACTIVE R665 1 @ WAKE# 3.3V
2 0_0402_5% 3 4 10U_0805_10V4Z 10U_0805_10V4Z 2 5
NC GND 2 2 Vn Vp
5 6
NC 1.5V +UIM_PWR
[19,20] WWAN_CLKREQ# 7 8
CLKREQ# NC UIM_DATA
9 10
GND NC UIM_CLK
[19] CLK_PCIE_WWAN# 11 12 3 6
REFCLK- NC UIM_RST CH2 CH3 +3VS
[19] CLK_PCIE_WWAN 13 14
REFCLK+ NC UIM_VPP DAN217T146_SC59-3
15 16
GND NC JP2
17
NC GND
18
+UIM_PWR
40mil 3
19 20 R666 1 3G@ 2 0_0402_5% 4 1 1
NC NC 3G_OFF# [34] GND VCC
21 22 PLT_RST# UIM_VPP 5 2 UIM_RST 2
GND PERST# R667 1 @ UIM_DATA VPP RST UIM_CLK
[10] PCIE_PTX_C_IRX_N3 23 24 2 0_0402_5% +3VALW 6 3
PERn0 +3.3Vaux R668 1 I/O CLK @ D24
[10] PCIE_PTX_C_IRX_P3 25 26 2 0_0402_5% +3VS 7
PERp0 GND DET
27 28
GND +1.5V R669 1 @ SB_SMCLK0
29 30 2 0_0402_5% 3G@ 1 1
GND SMB_CLK

1
31 32 R670 1 @ 2 0_0402_5% SB_SMDAT0 C817

10K_0402_5%
[10] PCIE_ITX_C_PRX_N3 PETn0 SMB_DATA 3G@ 4.7U_0805_10V4Z C818 3G@

R671
Vcc 3.3V +/- 8% [10] PCIE_ITX_C_PRX_P3 33
PETp0 GND
34
GND
8
0.1U_0402_16V4Z
35 36 USB20_N10 [21] 9
Peak Icc 2750mA GND USB_D- GND 2 2
37
NC USB_D+
38 USB20_P10 [21] WWAN
with max supply droop 50mA 39 40

2
NC GND R704 2 0_0402_5%
+3VS 41 42 1
Average Icc 1000mA NC LED_WWAN# R690 1 @
43 44 2 0_0402_5% WWAN_LED# [36]
NC LED_WLAN# +UIM_PWR
45 46
3G@ NC LED_WPAN# TAITW_PMPAT6-06GLBS7N14N0
47 48
EC_TX_P80_DATA R672 1100_0402_1% NC +1.5V ME@ R1.0
2 49 50
EC_RX_P80_CLK NC GND +1.5VS
1 2 51 52
NC +3.3V R1.0
R673 100_0402_1%
3G@ 53 54
GND GND
2

1 1
R724 @
100K_0402_5% TAITW_PFPET0-AFGLBG1ZZ4N0 C819 @ C820 @
3 3
ME@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
1

New Card 34mm Socket (Left/TOP)

JEXP1

+1.5VS Express Card Power Switch R1.0

+1.5VS_CARD1 1
GND
2
1
Imax = 0.75A New Card
[21] USB20_N7
3
USB_D-
[21] USB20_P7 USB_D+
1 1 CPUSB# 4
C821 EXP@ U38 EXP@ CPUSB#
5
0.1U_0402_16V4Z +1.5VS +1.5VS_CARD1 C822 EXP@ C823 EXP@ RSV
6
2 10U_0805_10V4Z 0.1U_0402_16V4Z SB_SMCLK0 RSV
12 11 7
1.5Vin 1.5Vout 2 2 SB_SMDAT0 SMB_CLK
14 13 8
1.5Vin 1.5Vout 40mil 9
SMB_DATA
+3VS_CARD1 +1.5VS_CARD1 +1.5V
10
+3VS SB_PCIE_WAKE# @ +1.5V
2 3 1 2 0_0402_5% 11
+3VS
4
3.3Vin 3.3Vout
5
60mil +3VS_CARD1 R674 12
WAKE#
3.3Vin 3.3Vout +3VALW_CARD1 +3VALW_CARD1 +3.3VAUX
PERST# 13
1
17 15
Imax = 1.35A 14
PERST#
C824 EXP@
+3VALW AUX_IN AUX_OUT 40mil 1 1
+3VS_CARD1
15
+3.3V
0.1U_0402_16V4Z PLT_RST# +3.3V
6 19 [19,20] EXP_CLKREQ# 16
2 SYSRST# OC# C825 EXP@ C826 EXP@ CPUSB# CLKREQ#
17
SYSON PERST# 10U_0805_10V4Z 0.1U_0402_16V4Z CPPE#
[34,38,43] SYSON 20 8 [19] CLK_PCIE_EXP# 18
SHDN# PERST# 2 2 REFCLK-
[19] CLK_PCIE_EXP 19
SUSP# REFCLK+
[34,38,41,44,46] SUSP# 1 16 20
+3VALW STBY# NC GND
[20] PCIE_EXPCARD_SB_RXN 21
R675 1 PERn0
+3VALW 2 @ 100K_0402_5% 10 7 [20] PCIE_EXPCARD_SB_RXP 22
CPPE# GND +3VALW_CARD1 PERp0
1 23
CPUSB# GND
9 24
C827 EXP@
[21] CPUSB# CPUSB# Imax = 0.275A [20] PCIE_SB_EXPCARD_TXN
[20] PCIE_SB_EXPCARD_TXP 25
PETn0
0.1U_0402_16V4Z PETp0
4 18 1 1 26 4
2 RCLKEN @ GND

G577BSR91U_QFN20 C828 C829 EXP@ 27

10U_0805_10V4Z 0.1U_0402_16V4Z GND
28
2 2 GND
SANTA_130801-5_LT
ME@

Security Classification
2007/10/15
Compal Secret Data
2010/04/30 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Nwe Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 28 of 48
A B C D E
 A B C D E

+1.7_VDDCT
+1.7_LX
Layout Notice : Place as close
chip as possible.
J1 @
+3VALW 2 1 JOPEN +1.7_VDDCT 1 2 +1.7_LX
+3V_LAN L53 4.7UH_SIA4012-4R7M_20%

1000P_0402_50V7K
10U_0805_10V4Z

0.1U_0402_16V4Z
3 Q42 @ Note:

S
1 1 1 1
+5VALW

C220

C217

C230
AO3414_SOT23-3 Place Close to LAN chip

4.7U_0805_10V4Z
L53 DCR< 0.15 ohm

G
2
1
4 2 2 2 4

Rate current of L33 > 1A

C496
R274 @
33K_0402_5% Close to Pin40
@

2
2

1
D C495 @
EN_WOL# 2
Power On strapping
[34] EN_WOL#
G 0.1U_0402_16V4Z
@ Q43 1
3 S Pin Description Chip Default
2N7002_SOT23-3
Atheros request can't disable LAN power H:Over Clock Enable
LED0 H
L:Over Clock Disable *
H:SWR Switch mode regulator Select *
U14 8152@

AR8151 Pin23=LED2.
no overclocking --
PD 5.1K AR8152, Pin23 is CLKREQ
S IC AR8152-AL1E QFN 40P E-LAN CTRL
R255
5.1K_0402_5%
1 2
U14 LED0,1,2 intel Pull UP
3
Place Close to Chip 3
[10] PCIE_PTX_C_IRX_N2 C7101 2 0.1U_0402_16V7K PCIE_PTX_IRX_N0 29 38 ACTIVITY R1.0
TX_N LED_0 ACTIVITY [30]
LAN_LINK# R83
C7111 2 0.1U_0402_16V7K PCIE_PTX_IRX_P0 30
Atheros LED_1 39
23
LAN_LINK# [30]
1 8152@ 2 LAN_CLKREQ#
[10] PCIE_PTX_C_IRX_P2 TX_P LED_2
8151-AL1A 0_0402_5%
[10] PCIE_ITX_C_PRX_N2 36 RX_N
12 MDI0-
TRXN0 MDI0- [30]
35 11 MDI0+
[10] PCIE_ITX_C_PRX_P2 RX_P TRXP0 MDI0+ [30]
15 MDI1-
TRXN1 MDI1- [30]
R261 2 1 0_0402_5% CLK_PCIE_LAN#_C 32 14 MDI1+
[19] CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ [30]
R260 2 1 0_0402_5% CLK_PCIE_LAN_C 33 18 MDI2-
[19] CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- [30]
17 MDI2+
MDI2+ [30]
+3V_LAN
PLT_RST# TRXP2 MDI3- R1.0
[11,12,13,20,28,34] PLT_RST# 2 PERST# TRXN3 21 MDI3- [30]
20 MDI3+
TRXP3 MDI3+ [30]
R482 1 @ 2 0_0402_5% PCIE_WAKE# 3 LAN_CLKREQ# 2 R254 1
[21,28] SB_PCIE_WAKE# W AKE# +3V_LAN
R257 4.7K_0402_5%
R483 1 2 0_0402_5% LAN_RBIAS 2 2.37K_0402_1%

1000P_0402_50V7K
[34] EC_PME# 25 SMCLK RBIAS 10 1
PCIE_WAKE# 2 R268

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
26 SMDATA 1
+3V_LAN 4.7K_0402_5%

1U_0402_6.3V4Z
28 TEST_RST VDD33 1
+1.7_LX C233 & C276 Close pin1 < 200mil 1 1 1 1 1

C233

C276

C510

C273

C480
27 @ PLT_RST# 2 R267 @1
TESTMODE C273 & 480 Close pin < 400mil 4.7K_0402_5%
40 +1.7_LX
LAN_XTALO LX +1.7_VDDCT 2 2 2 2 2
7 XTLO
LAN_XTALI 8
R96 XTLI +1.7_VDDCT
VDDCT 5
LAN_CLKREQ# 1 8151@ 2 CLKREQ_LAN#_R 1
[19,21] LAN_CLKREQ#
0_0402_5% 0.1U_0402_16V4Z 4 CLKREQ# +1.1_DVDDL C218 1
1 2 DVDDL 24 2 0.1U_0402_16V4Z C215
C234 8152@ 37 C209 1 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z
2
+1.1_AVDDL DVDDL_REG C224 1 2 2
13 AVDDL 2 0.1U_0402_16V4Z
+1.1_AVDDL 19 AVDDL
31 AVDDL AVDDH 16 Near Pin37
34 22 +2.7_AVDDH
AVDDL AVDDH
8151@

8151@

+1.1_AVDDL 6 9 +2.7_AVDDH
0.1U_0402_16V4Z

AVDDL_REG AVDDH_REG

8151@
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1
41 GND
C212

C205

C208

C222

C223

C216

C219

C225

C221

C211
AR8151-AL1A_QFN40_5X5
2 2 2 2 2 2 8151@ 2 2 2 2 Place Close to LAN chip
LAN_XTALI R98 49.9_0402_1%
MDI0+ 1 2 C204 1000P_0402_50V7K
Near Near Near Near Near LAN_XTALO Near Near Near 49.9_0402_1%
Y4 MDI0- R262 1 2 1 2 C227 0.1U_0402_16V4Z
Pin13 Pin19 Pin31 Pin34 Pin6 1 2
Pin9 Pin22 Pin16 49.9_0402_1%
MDI1+ R97 1 2 C213 1000P_0402_50V7K
25MHZ_20PF_7A25000012 49.9_0402_1%
1 1 MDI1- R100 1 2 1 2 C214 0.1U_0402_16V4Z
49.9_0402_1%
C203 C202 MDI2+ R266 1 2 C231 1000P_0402_50V7K
33P_0402_50V8J 33P_0402_50V8J 8151@ 49.9_0402_1% 8151@
2 2 MDI2- R101 1 2 1 2 C229 0.1U_0402_16V4Z
8151@ 49.9_0402_1% 8151@
MDI3+ R263 1 2 C232 1000P_0402_50V7K
8151@ 49.9_0402_1% 8151@
MDI3- R99 1 2 1 2 C228 0.1U_0402_16V4Z
8151@ 8151@
For AR8152, pin23 is the LDO output. Mount C234
1 and no mount R96.close to this pin4 1
8152 no mount MDI3+,MDI3-,MDI2-,MDI2+ resister and cap
For AR8151, pin4 is the CLKREQn pin, mount R96
and no mount C234.close to this pin4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8151/8152
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NAWE5 LA-5753P 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 29 of 48
A B C D E
 5 4 3 2 1

+1.7_VDDCT

R57 1 2 0_0603_5%
MDI[0..3] +/- Reverse
D C128 2 1 1U_0402_6.3V4Z D
R1.0

Close to T9
8151@ T9
C127 2 1 0.01U_0402_16V7K 1 24 MCT3 R275 2 8151@ 1 75_0402_5%
TCT1 MCT1
8151@ 2 1:1 23 MDO2-
[29] MDI2- TD1+ MX1+
C206 1000P_0402_50V7K

3 22 MDO2+
[29] MDI2+ TD1- MX1-
8151@
C130 2 1 0.01U_0402_16V7K 4 21 MCT2 R56 2 8151@ 1 75_0402_5%
TCT2 MCT2
8151@ 5 1:1 20 MDO3-
[29] MDI3- TD2+ MX2+
C226 1000P_0402_50V7K

6 19 MDO3+
[29] MDI3+ TD2- MX2-
C129 2 1 0.01U_0402_16V7K 7 18 MCT1 R55 2 1 75_0402_5%
TCT3 MCT3
8 1:1 17 MDO0-
[29] MDI0- TD3+ MX3+
C237 1000P_0402_50V7K

C C

9 16 MDO0+
[29] MDI0+ TD3- MX3-
C132 2 1 0.01U_0402_16V7K 10 15 MCT0 R54 2 1 75_0402_5%
TCT4 MCT4
11 1:1 14 MDO1-
[29] MDI1- TD4+ MX4+
C238 1000P_0402_50V7K 1
C131
Place close to TCT pin
1000P_1206_2KV7K
MDO1+ 2
[29] MDI1+ 12 TD4- MX4- 13

LG-2446S
8151@

T9

NS892404
8152@ RJ45 Conn.
B B
JRJ45
12 Amber LED-
R501 2 1 300_0402_5% 11 16
[29] ACTIVITY Amber LED+ SHLD4
1
MDO3- 8 15
@ C644 PR4- SHLD3
68P_0402_50V8K MDO3+ 7
2 PR4+
MDO1- 6 PR2-
MDO2- 5 PR3-
MDO2+ 4 PR3+
MDO1+ 3 PR2+
MDO0- 2 PR1-
SHLD2 14
MDO0+ 1 PR1+
[29] LAN_LINK# R502 2 1 300_0402_5% 10 13
Green LED- SHLD1
1 +3V_LAN 9 Green LED+
C646 FOX_JM36113-P2221-7F
68P_0402_50V8K ME@
2
A @ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/03/20 Deciphered Date 2010/04/30 Title
LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NAWE5 LA-5753P 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 30 of 48
5 4 3 2 1
 A B C D E

1 1

SMSC thermal sensor +3VS +3VS

REMOTE1+
Close to DDR
placed near by VRAM 1

1
@ C
R584 R585 C512 2 Q39
10K_0402_5% 10K_0402_5% 100P_0402_50V8J B MMST3904-7-F_SOT323-3
+3VS @ @ 2 E

3
U23 REMOTE1-

2
1 VDD SMCLK 10 EC_SMB_CK2 [6,14,34]
2 REMOTE1+ 2 9
DP1 SMDATA EC_SMB_DA2 [6,14,34]
2 C511 REMOTE1- 3 8 REMOTE2+
Under WWAN 2
0.1U_0402_16V4Z DN1 ALERT#
1

1
1 REMOTE2+ @ C
4 7
DP2 THERM# C514 Q28
2
REMOTE2- 5 6 100P_0402_50V8J B MMST3904-7-F_SOT323-3
DN2 GND 2 E
Close U23

3
REMOTE2-
REMOTE1+
1 EMC1403-2-AIZL-TR_MSOP10

C513 REMOTE1,2+/-:
2200P_0402_50V7K Address 1001_101xb
2 REMOTE1- Trace width/space:10/10 mil
P/N SA000029210 Trace length:<8"
REMOTE2+
1
C651
2200P_0402_50V7K
2 REMOTE2-

3 3

FAN1 Conn
4 +5VS 4

JP12
1
1
2 [34] FAN_SPEED1 1 R508 2 0_0402_5% FAN_SPEED_R2 2
[34] EC_FAN_PWM 1 R507 2 0_0402_5% FAN_PWM_R 3
C647 3
4 4
10U_0805_10V4Z
1
5
6
G5
G6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title
ACES_85205-04001
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EMC1403_sensor/FAN
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 31 of 48
A B C D E
 A B C D E F G H

ON/OFF switchSW1@ Power Bottom Board Conn. 4pin Cap Sensor Board Conn. 8pin
1 3
Power Button 2 4
SMT1-05_4P JP3
NOVO_BTN# 1

6
5
+3VALW ON/OFFBTN# 1
2 2
PM_BTN# 3
TOP Side J2
@ 4
3
4

2
1 2
1 E&T_6905-E04N-00R 1
SHORT PADS R519 JP1
Bottom Side 100K_0402_5% ME@ 1
D14 1
[34] CAP_INT#
R518 1 2 0_0402_5% CAP_INT#_R 2

1
ON/OFF# R524 1 2
3 2 0_0402_5% 3
ON/OFFBTN# 1
51_ON#
ON/OFF# [34]
Power Bottom Board Conn. 8pin [34] ESB_DAT
[34] ESB_CLK
R525 1 2 0_0402_5% 4
3
4
2 51_ON# [39] [34] CAP_RST# 5 5
+5VS 6
+3VS 6
DAN202UT106_SC70-3 7
JP6 7
+5VS 8 8
1 9
1 GND
[34,35] NUM_LED# 2 2 2 2 10 GND
[34,35] CAPS_LED# 3
PM_BTN# 3 C652 C653 ACES_85201-08051
[34] PM_BTN# 4 4
NOVO_BTN# 5 33P_0402_50V8J R1.0 33P_0402_50V8J ME@
5

1
D ON/OFFBTN# 1 1
6
EC_ON 6
[34] EC_ON 2 7
G 7
8 8
Q37 S 9

3
GND
2

2N7002_SOT23-3 R1.0 10
R520 GND
10K_0402_5% ACES_85201-08051

ME@
Card Reader/Audio Jack SB CONN
1

12/28
+3VALW +3VS
D8
3

1
1
@ R637 R522 2
+3VALW 100K_0402_1% 100K_0402_1%
2 2
PJDLC05C_SOT23-3

2
2

PM_BTN# @
R523 JP8
100K_0402_5% PLUG_IN 1
[33] PLUG_IN 1
HP_OUTR 2
[33] HP_OUTR 2
D17 HP_OUTL 3
[33] HP_OUTL
1

NOVO# 3
[34] NOVO# 2 4
NOVO_BTN# MIC_JD 4
1 [33] MIC_JD 5 5
51_ON# 3 NOVO_BTN# ON/OFFBTN# PM_BTN# EXT_MIC_L 6
[33] EXT_MIC_L EXT_MIC_R 6
[33] EXT_MIC_R 7 7

2
8
DAN202UT106_SC70-3 D15 D16 8
CardReader 9 9
PJSOT24C 3P C/A SOT-23 PJSOT24C 3P C/A SOT-23 +3VALW 10
[21] USB20_P2 10
@ @ 11 13
[21] USB20_N2 11 GND
12 14
12 GND

1
ACES_85201-1205N

ME@
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
SATA HDD Conn.
SATA ODD Conn. JHDD1
1
JODD1 C658 1 SATA_STX_C_DRX_P0 GND
[22] SATA_STX_DRX_P0 2 0.01U_0402_16V7K 2
3 C659 1 SATA_STX_C_DRX_N0 RX+ 3
[22] SATA_STX_DRX_N0 2 0.01U_0402_16V7K 3 RX-
1 GND 4 GND
C654 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P1 2 C660 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N0 5
[22] SATA_STX_DRX_P1 A+ [22] SATA_DTX_C_SRX_N0 TX-
C655 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_N1 3 C661 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P0 6
[22] SATA_STX_DRX_N1 A- [22] SATA_DTX_C_SRX_P0 TX+
4 7
C656 1 SATA_DTX_SRX_N1 GND GND
[22] SATA_DTX_C_SRX_N1 2 0.01U_0402_16V7K 5
C657 1 SATA_DTX_SRX_P1 B-
[22] SATA_DTX_C_SRX_P1 2 0.01U_0402_16V7K 6
B+
7
GND
8 3.3V
R1.0 8 9
DP +3VS 3.3V
+5VS 9 10
+5V 3.3V
10 +5V GND 17 11 GND
11 16 12
MD GND GND
12 GND 13 GND
13 R1.0 14
10U_0805_10V4Z 0.1U_0402_16V4Z GND 5V
+5VS 15
5V
16
OCTEK_SLS-13SB1G_RV 5V
1 1 1 1 17
C668 C666 C669 C667 10U_0805_10V4Z 0.1U_0402_16V4Z GND
ME@ 18
Reserved
19
GND
1 1 1 1 20 12V GND 23
2 2 2 2 C662 C663 C664 C665 21 24
12V GND
22 12V
1U_0402_6.3V4Z 1000P_0402_50V7K
2 2 2 2 OCTEKCONN_SAT-22SW1G
ME@
1U_0402_6.3V4Z 1000P_0402_50V7K
OCTEKCONN
SP01000QT00
SMT, 22P, Standart Type, H:9.2mm, P=1.27
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 32 of 48
A B C D E F G H
 5 4 3 2 1

+3VS +5VS

PC Beep R692

2
+PVDD1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VS

2
R694 1 1 0_0603_1% 1 1
D28 10K_0402_5% 20K_0402_5% C1237 C1239
RB751V_SOD323 R693 C1238 C1240

2
@

1
C1241 1U_0603_10V6K R695 J5 2 2 2 2

2
2

1
PC_BEEP1 2 1 PC_BEEP +3VS 2 1 0.1U_0402_16V4Z JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
0_0603_1%
D D

1
1 1 @ place close to chip

2
C1243 C1244
EC Beep

1
1
C1242 R696 C R697
2 1 1 2 2 2.4K_0402_1% 10U_0805_10V4Z +3VS_DVDD R698
[34] BEEP# 2 2
1 B +PVDD2 2 1 0.1U_0402_16V4Z +5VS
560_0402_5% E place close to chip 1 1 0_0603_1% 1 1

1
@ C1246 1U_0603_10V6K 0.1U_0402_16V4Z C1245 @ C1248
0.1U_0402_16V4Z Q86 @ C1247 @ @ C1249
2 0.1U_0402_16V4Z
C1250 1 1 2 2 2 2
R699 2SC2411KT146_SOT23-3
2 1 1 2 C1251 C1252 +AVDD_HDA 10U_0805_10V4Z 10U_0805_10V4Z
[21] SB_SPKR
10U_0805_10V4Z R700
1U_0603_10V6K 560_0402_5% 1 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS
D29 @ 0_0603_1%
SB Beep RB751V_SOD323

39

46

25

38
1 1 1 1

9
U49 C1253 C1258 C1254 C1255
2

+MIC1_VREFO_L

DVDD

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
+MIC1_VREFO_R 2 2 2 2
place close to chip
10U_0805_10V4Z 0.1U_0402_16V4Z
+MIC2_VREFO

2
23 40 SPK_L2+
R702 R703 LINE1_L SPK_OUT_L+ SPK_L1-
24 LINE1_R SPK_OUT_L- 41

2
4.7K_0402_5% 4.7K_0402_5% Internal SPEAKER
R701 14 45 SPK_R2+
4.7K_0402_5% C517 LINE2_L SPK_OUT_R+ SPK_R1-
15 44

1
1K_0402_5% 2.2U_0603_10V7K LINE2_R SPK_OUT_R-
2 R716 1 1 2 MIC1_L 21 32 HP_OUT_L R705 75_0402_1%
[32] EXT_MIC_L HP_OUTL [32]
1
MIC1_L HP_OUT_L
C
[32] EXT_MIC_R 2 R717 1 1 2 MIC1_R 22 MIC1_R HP_OUT_R 33 HP_OUT_R R706 75_0402_1%
HP_OUTR [32] Headphone C
MIC2_L MIC1 1K_0402_5% 1K_0402_5% C518 2.2U_0603_10V7K
1 INTT_MIC 2 R707 1 1 2 C515 MIC2_L 16 MIC2_L
1

2 1 2 2.2U_0603_10V7K MIC2_R 17
R612 C516 @ MIC2_R
SYNC 10 HDA_SYNC_AUDIO [21]
0_0402_5% WM-64PCY_2P +3VS 2.2U_0603_10V7K
45@ 2 6
GPIO0/DMIC_DATA BCLK HDA_BITCLK_AUDIO [21]
R709 D18 RB751V_SOD323
2

MIC2_R 2 @ 1 1 2 3
R708 0_0402_5% @ GPIO1/DMIC_CLK
SDATA_OUT 5 HDA_SDOUT_AUDIO [21]
4.7K_0402_5% C1262 @
@ 2 R630 1 EC_MUTE#_R 4 8 AZ_SDIN0_HD_R 2 1 2 R792 @1 1 2
[34] EC_MUTE# PD# SDATA_IN HDA_SDIN0 [21]
0_0402_5% R710 33_0402_5% 33_0402_5%
1

22P_0402_50V8J
near pin HDA_RST_AUDIO# 11 47 R711 2 1 0_0402_5%
[21] HDA_RST_AUDIO# RESET# EAPD EAPD [34]
Near PIN
2 SPDIFO 48
1 2 PC_BEEP 12 For EMI
C1264 C1263 100P_0402_50V8J PCBEEP
MONO_OUT 20
100P_0402_50V8J +MIC2_VREFO
1 @ SENSE_A 13 SENSE A
MIC2_VREFO 29
12/28 18
C1266 SENSE B C1267 10U_0805_10V4Z
MIC1_VREFO_R 30 +MIC1_VREFO_R
1 2 +5VS 1 2 36 28 LDO_CAP 1 2
C1265 1 CBP LDO_CAP
2 0.1U_0603_50V7K R720 0_0603_5% C1266 close Codec
ECN for ALC259 2.2U_0603_6.3V4Z 35 27 AC_VREF2.5V
CBN VREF
2

1 2 R723 +MIC1_VREFO_L 31 19 AC_JDREF 2 R712 1 20K_0402_1%

C1268 1 MIC1_VREFO_L JDREF
B
2 0.1U_0603_50V7K R721 0_0603_5% 4.7K_0402_5% 1 1 B
@ 43 34 A_RVO 1 2
PVSS2 CPVEE C1269 2.2U_0603_6.3V4Z C1270 C1271
42
1

PVSS1 @
1 2 49 DVSS2 AVSS1 26
1 2 R722 0_0603_5% 7 37 0.1U_0402_16V4Z 2 2 10U_0805_10V4Z
R713 0_0603_5% EC_MUTE#_R DVSS1 AVSS2
ALC259-GR_QFN48_7X7
place close to chip
GND GNDA DGND SA00003QR10 AGND
R1.0

External MIC
wide 20MIL
JSPK1
SPK_R1- L87 FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN Sense Pin Impedance Codec Signals Function
SPK_R2+ L88
1
1
2
2 FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN
1
2
1 place close to chip
SPK_L1- L89 FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 2
SPK_L2+ L90
1 2
FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN
3 3 39.2K PORT-I (PIN 32, 33) Headphone out SENSE_A
1 2 4 4 [32] MIC_JD 2 1
R714 20K_0402_1%
1000PF_0402_25V7

1000PF_0402_25V7

1000PF_0402_25V7

1000PF_0402_25V7

5 GND1 20K PORT-B (PIN 21, 22) Ext. MIC

6 GND2 SENSE A [32] PLUG_IN
R715 39.2K_0402_1%
1 1 1 1 ACES_88231-04001 10K PORT-C (PIN 23, 24)
C1272

C1273

C1274

C1275

ME@
A A

2 2 2 2 SP02000K200 5.1K (PIN 48)

@ @ @ @

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2010/04/30 Title
ALC259 Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 33 of 48
5 4 3 2 1
 +3VALW
+EC_AVCC
1 1 1 1 1 1

0.1U_0402_16V4Z
C715

0.1U_0402_16V4Z
C716

0.1U_0402_16V4Z
C717

0.1U_0402_16V4Z
C718

1000P_0402_50V7K
C719

1000P_0402_50V7K
C720
L83 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C721 2 2 2 2 2 2
0.1U_0402_16V4Z C722

111
125
1000P_0402_50V7K

22
33
96

67
9
1 2 1 ECAGND 2 U28
L82 FBM-11-160808-601-T_0603 VGA_DBCLK

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
EC must program to 500KHZ output
Start and stop follow SUP high/Low 1 R558 @2 +3VS
1 21 10K_0402_5%
[21] GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# VGA_DBCLK [19]
[21] KB_RST# 2 23 BEEP# [33]
KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_FAN_PWM
[20] SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 EC_FAN_PWM [31]
4 27 ACOFF
[20,28] LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF [39,41]
[20,28] LPC_AD3 5 LAD3
LPC_AD2 7 PWM Output
[20,28] LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
[20,28] LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP [40]
LAD0 LPC & MISC
[20,28] LPC_AD0 10 64
BATT_OVP/AD1/GPIO39
2 1 2 1 65 ADP_I [41]
ADP_I/AD2/GPIO3A
@C724
@ C724 22P_0402_50V8J @ R559 10_0402_5%
[20,24] LPC_CLK0_EC 12
PCICLK AD Input AD3/GPIO3B
66
[11,12,13,20,28,29] PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75
1 2 EC_RST# 37 76
+3VALW ECRST# SELIO2#/AD5/GPIO43 KILL_SW# [35] +5VS
R560 47K_0402_5% EC_SCI# 20
[21] EC_SCI# EC_ID SCI#/GPIO0E
2 38
+3VALW CLKRUN#/GPIO1D DAC_BRIG TP_CLK R561 1
68 DAC_BRIG [27] 2 4.7K_0402_5%
C723 R562 DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D 70
0.1U_0402_16V4Z 1 @ 2 EC_ID DA Output 71 IREF TP_DATA R563 1 2 4.7K_0402_5%
1 KSI0 IREF/DA2/GPIO3E IREF [41]
4.7K_0402_5% 55 72 +3VALW
KSI1 KSI0/GPIO30 DA3/GPIO3F CHGVADJ [41] VDDIO
R564 56 +3VALW @1
@ 2
@ KSI2 KSI1/GPIO31 EC_MUTE# R565 1 @ 10K_0402_5% C725 100P_0402_50V8J
1 2 57 KSI2/GPIO32 2
4.7K_0402_5% KSI3 58 83 BATT_TEMP 1 2
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# [33]
KSI4 59 84 USB_ON# USB_ON# R566 1 2 10K_0402_5% C726 100P_0402_50V8J
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# [37] ACIN
EC_ID to identify KB926 D or E 60
KSI5/GPIO35 PSCLK2/GPIO4C
85 NOVO# [32] 1 2
KSI6 61 PS2 Interface 86 VDDIO C727 100P_0402_50V8J
KSO[0..15] KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK VDDIO [43]
62 87 Reserve 1.5VP control
[35] KSO[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK [35]
KSO0 39 88 TP_DATA
KSI[0..7] KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA [35] BATT_SEL_EC 1
40 KSO1/GPIO21 2
[35] KSI[0..7] KSO2 41 R567 4.7K_0402_5%
KSO3 KSO2/GPIO22
42 KSO3/GPIO23 SDICS#/GPXOA00 97 BT_OFF# [37]
KSO4 43 98
KSO5 KSO4/GPIO24 SDICLK/GPXOA01 BATT_SEL_EC EN_WOL# [29]
KSO5/GPIO25 Int. K/B
+3VALW 44 99
SDIDO/GPXOA02 BATT_SEL_EC [41]
KSO6 45 109 LID_SW#
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW# [35]
46 KSO7/GPIO27 SPI Device Interface
R568 1 2 47K_0402_5% KSO1 KSO8 47 KSO8/GPIO28
+3VS
KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO [36]
R569 1 2 47K_0402_5% KSO2 KSO10 49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI
FWR#SPI_SI [36]

1
KSO11 50 SPI Flash ROM 126 SPICLK
KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# SPICLK [36]
51 128 FSEL#SPICS# [36]
KSO13 KSO12/GPIO2C SPICS# R570
52
KSO14 KSO13/GPIO2D 10K_0402_5%
53 KSO14/GPIO2E
+3VALW KSO15 54 73 PM_BTN#
PM_BTN# [32]

2
KSO15/GPIO2F CIR_RX/GPIO40 CAP_INT# CAP_INT#
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 CAP_INT# [32]
82 89 FSTCHG [41]
EC_SMB_CK1 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0#
2 R579 1 90 CHARGE_LED0# [36]
2.2K_0402_5% BATT_CHGI_LED#/GPIO52
91 CAPS_LED# [32,35]
EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED1#
[40] EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 CHARGE_LED1# [36]
2 R580 1 EC_SMB_DA1 EC_SMB_DA1 78 93 R1.0
[40] EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED# [36]
2.2K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
[6,14,31] EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 VR_ON SYSON [28,38,43] VR_ON 2
[6,14,31] EC_SMB_DA2 80 121 VR_ON [47] 1
+3VS SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN R572 100K_0402_5%
127 ACIN [14,39]
AC_IN/GPIO59

[21] PM_SLP_S3# 6 100 EC_RSMRST# [21]

PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03
2

14 101 EC_LID_OUT#
[21] PM_SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON EC_LID_OUT# [21]
[21] EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON [32]
R571 16 103
LID_SW#/GPIO0A EC_SWI#/GPXO06 CMOS_OFF# [27]
10K_0402_5% ESB_CLK 17 104 EC_PWROK 1 2
[32] ESB_CLK ESB_DAT SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# SB_PWRGD [6,11,21]
[32] ESB_DAT 18 GPO 105 BKOFF# [27]
R573 0_0402_5%
1

PBTN_OUT#/GPIO0C BKOFF#/GPXO08
[47] VGATE 19
EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09
106 WL_OFF# [28]
FAN_SPEED1 25 107
[27] INVT_PWM EC_THERM#/GPIO11 GPXO10
FAN_SPEED1 28 108 CAP_RST#
[31] FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 CAP_RST# [32]
[28] 3G_OFF# 29 FANFB2/GPIO15
EC_TX_P80_DATA 30
[28,35] EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16
[28,35] EC_RX_P80_CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VLDT_EN [38,44,45,46]
[32] ON/OFF# 32 112 ENBKL [11]
ON_OFF/GPIO18 ENBKL/GPXID2
[6] EC_PROCHOT# 34 114 EAPD [33]
PWR_LED#/GPIO19 GPXID3
[32,35] NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115
116 SUSP#
GPXID5 PBTN_OUT# SUSP# [28,38,41,44,46]
R1.0 117
GPXID6 EC_PME# PBTN_OUT# [21]
118
XCLKI GPXID7 EC_PME# [29]
122 XCLK1
+3VALW XCLKO 123 124 1 @
@R574
R574 210K_0402_5% +3VALW
XCLK0 V18R
1
AGND

1 2 FRD#SPI_SO
GND
GND
GND
GND
GND

R575 @ 100K_0402_1% C728

+3VS 4.7U_0805_10V4Z
1 2 FSEL#SPICS# R577 KB926QFA1_LQFP128 2 SUSP#
11
24
35
94
113

69

R576 @ 100K_0402_1% 1 2 ESB_CLK 1

4.7K_0402_5% @
ECAGND

R578 C729
1 2 ESB_DAT 1000P_0402_50V7K
4.7K_0402_5% 2

ENE926 ( E0 ) SA00001J5A0

+3VS

1 2 C730
27P_0402_50V8J
R581 R582 XCLKO
2.2K_0402_5% 2.2K_0402_5%
1

32.768KHZ_12.5PF_1TJS125DJ4A420P
3 NC @
EC_SMB_CK2 OUT 4 R583
EC_SMB_DA2 2 1 20M_0603_5%
NC IN
1 1
2

@ @ XCLKI
C731
100P_0402_50V8J
C732
100P_0402_50V8J
X1 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 C733 Issued Date 2007/10/15 Deciphered Date 2010/04/30 Title
2 2 27P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 34 of 48
 5 4 3 2 1

D D

JP5
KSI1 1
KSI7 1
2
INT_KBD Conn. KSI6
KSO9
3
2
3 EC DEBUG PORT
4 4
KSI[0..7] KSI4 5
KSI[0..7] [34] 5
KSI5 6
KSO[0..15] KSO0 6
KSO[0..15] [34] 7 7
KSI2 8
KSI3 8 JP11
9 9
KSO5 10 +3VALW 1
KSO2 C734 1 10 1
2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J KSO1 11 11 [28,34] EC_TX_P80_DATA
EC_TX_P80_DATA 2 2
KSI0 12 EC_RX_P80_CLK 3
12 [28,34] EC_RX_P80_CLK 3
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSO2 13 4
KSO4 13 4
14 14
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSO7 15 ACES_85205-0400
KSO8 15
16 16 ME@
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO6 17
KSO3 17
18 18
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSO14 21
R1A KSO11 21
22 22
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J +5VS KSO10 23
KSO15 23
24 24
C KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J 300_0402_5% 2 E7@ 1 R153 25 C
300_0402_5% 25
2 E7@ 1 R154 26 26
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J 27

KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J

[32,34] NUM_LED#
[32,34] CAPS_LED# 28
29
27
28
31
Lid Switch
29 G1
30 30 G2 32
KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J R1.0
2 2 ACES_85201-3005N ME@
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J
@ C670 C671 @ +3VALW R587 1 2 100K_0402_5%
100P_0402_50V8J 100P_0402_50V8J
1 1
CONN PIN define need double check

2
A3212ELHLT-T_SOT23W -3

VDD
1
OUTPUT 3 LID_SW # [34]
C760
To TP/B Conn. 0.1U_0402_16V4Z 2

GND
2
+5VS C761
U29 10P_0402_50V8J

1
1

C762

0.1U_0402_16V4Z
JP4
4
B
[34] TP_CLK
TP_CLK
TP_DATA
3
4
3 +3VALW
Kill Switch B

[34] TP_DATA 2 2
1 100K_0402_5% LSSM12-P-V-T-R_3P
1
@
C763
1
@
C764
1
2 R691 1 3 3
Kill
100P_0402_50V8J 100P_0402_50V8J E&T_6905-E04N-00R 2
STATUS
2 2 ME@ [34] KILL_SW # 2
KILL_SW# 1,2(LOW) OFF
CONN PIN define need double check 1 1 2,3(HI) ON

SW 2

12/28
D12
3 TP_CLK
1
2 TP_DATA

PJDLC05C_SOT23-3
@ 12/28
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 35 of 48
5 4 3 2 1
 SA00002TO00 pakage 200mil
S IC FL 16MBIT MX25L1605AM2C-12G SO8 ROM
+3VALW
20mils
1

1
C765
0.1U_0402_16V4Z R589
2 10K_0402_5%

2
U30
FSEL#SPICS# 1 8
[34] FSEL#SPICS# FRD#SPI_SO SPI_SO CS# VCC HOLD#
1 2 2 7 R591 0_0402_5%
[34] FRD#SPI_SO SO HOLD# SPI_CLK_R SPICLK
3 6 1 2 SPICLK [34]
R590 0_0402_5% WP# SCLK SPI_SI_EC FWR#SPI_SI
4 GND SI 5 1 2 FWR#SPI_SI [34]
16M W25Q16BVSSIG SOIC 8P R592 0_0402_5% SPI_CLK_R

1
R594
0_0402_5%
@
Colse to EC

2
1 1
@ C766 C767
10P_0402_50V8J 12P_0402_50V8J
2 @ 2

EMI 3G

LED 1
FD1
1
FD2
1
FD3
1
FD4

LED1
White A:H_2P8
[34] PWR_LED# 1 2 2 1 +5VALW
300_0402_5% R599
H1 H2 H3 H4 H5 H6
19-213A-T1D-CP2Q2HY-3T_WHITE HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

Orange LED2

1
BATT_LOW_LED# 1 2 2 1
[34] CHARGE_LED1# +3VALW
O 300_0402_5% R595
H7 H8 H9
[34] CHARGE_LED0# 3 4 2 1 +5VALW HOLEA HOLEA HOLEA
W 300_0402_5% R596
BATT_CHG_LED#
White
18-225A-S2T3D-C01-3T_ORG-WHITE

1
D19 LED3 I:H_3P0N X1
White H10
[28] WLAN_LED# 1 2 1 2 2 1 +5VS
300_0402_5% R597 HOLEA
RB751V_SOD323
C:H_3P8
19-213A-T1D-CP2Q2HY-3T_WHITE H11 H12 H13 H14
HOLEA HOLEA HOLEA HOLEA

1
[37] BT_LED#

1
D21
1 2
J:H_2P8 X1
[28] WWAN_LED#
D:H_3P8 H16
RB751V_SOD323 HOLEA

LED4 H17 H18 H15

White HOLEA HOLEA HOLEA

1
[22] SATA_LED# 1 2 2 1 +5VS
300_0402_5% R598

1
19-213A-T1D-CP2Q2HY-3T_WHITE

BOTTOM SIDE BOTTOM SIDE

FAN VGA
H19 H20
HOLEA HOLEA
H_4P5X3P0N H_6P0N
H21 H22
HOLEA HOLEA
3P2 X1
1

1
H23
HOLEA

1
H28 H25
HOLEA HOLEA
H_3P0X4P0N

1
H24
BOTTOM SIDE HOLEA
1

WLAN

H_1P9X0P5N

1
EMI on DIMM

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 36 of 48
 A B C D E

Right USB Conn. Right USB(Sub b/d)

+USB_VCCA
W=80mils JUSB1
1 +USB_VCCA 1
USB20_N12_R 1
1 2
C1220 + USB20_P12_R 2
3
C1221 3
4
150U_B2_6.3VM_R35M 470P_0402_50V7K 4
5
G5

2
2 2

PJDLC05_SOT23-3
6
D30 G6
@ ACES_85205-04001
ME@

1 R588 1 2 0_0402_5% USB20_N12_R 1

[21] USB20_N12
1 1 2 2
L91

1
WCM-2012-900T_0805
@ 4 3
4 3
R472 1 2 0_0402_5% USB20_P12_R
+5VALW [21] USB20_P12

U46
+USB_VCCA
[21] USB20_N0
R632 1 2 0_0402_5% USB20_N0_R
+USB_VCCB
Left USB Conn.
W=80mils JUSB2
1
GND OUT
8 RIGHT USB PORT X1 1
1 2
2
C1222 0.1U_0402_16V4Z 2 7 L92 1
IN OUT WCM-2012-900T_0805 USB20_N0_R 1
2 1 3 6 2
USB_ON# 4 IN OUT @ USB20_P0_R 2
[34] USB_ON# 5 USB_OC#1 [21] 4 3 1 3
EN OC# 4 3 3
4
4

2
PJDLC05_SOT23-3
APL3510BKI_SO8 R634 1 2 0_0402_5% USB20_P0_R C1224 5
[21] USB20_P0 GND
470P_0402_50V7K D26 6
2 @ GND
1 7
C1223 GND
8
@ 1000P_0402_50V7K GND
SUYIN_020173MR004S558ZL
2
ME@
ESATA and USB Conn.

1
+USB_VCCB

+USB_VCCB
W=80mils
USB power switch need update symbol
to SA000039E00(Low enable) 1
1
C1225 + C1227 JESAT1
470P_0402_50V7K 1 USB
2
150U_B2_6.3VM_R35M USB20_N4 VBUS 2
2
2 2 [21] USB20_N4
[21] USB20_P4
USB20_P4 3
4
D-
D+
USB
+5VALW
USB20_N4
ESATA and USB
5
GND
A+ = RXP
SATA_STX_C_DRX_P2_R GND
6
+USB_VCCB
USB20_P4 SATA_STX_C_DRX_N2_R 7
A+
A-
ESATA A- = RXN
E-SATA COMBO 8
GND
3

2
PJDLC05_SOT23-3

U47 SATA_DTX_SRX_N2_R 9
1 8
LEFT USB PORT D27 SATA_DTX_SRX_P2_R 10
B-
C1226 0.1U_0402_16V4Z GND OUT @ B+
2 7 11
IN OUT GND
2 1 3 6
USB_ON# 4 IN
EN
OUT
OC#
5 USB_OC#0 [21] 12
13
GND
B- = TXN
APL3510BKI _SO8 GND
14
15
GND
GND
B+ = TXP
1
1

C1228 TYCO_1759576-1
@ 1000P_0402_50V7K ME@
2

+3VS +3VS

2
1 2

2
@ R106
4.7K_0402_5% C1232 C1229 R680 R681
R1.0 0.1U_0402_16V4Z~D 0.01U_0402_16V7K 4.7K_0402_5%
2 @ 1 @ 4.7K_0402_5% @

1
U48 @

1
7 EN VCC 6
3 ESATA@ 10 3
C1230 1 VCC
[22] SATA_STX_DRX_P2 2 0.01U_0402_16V7K SATA_STX_C_DRX_P2 1 16
C1231 1 IN0P VCC
[22] SATA_STX_DRX_N2 2 0.01U_0402_16V7K SATA_STX_C_DRX_N2 2 20
ESATA@ ESATA@ IN0M VCC
C1234 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N2 4 9
[22] SATA_DTX_C_SRX_N2 OUT1P B0
C1233 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P2 5 8
[22] SATA_DTX_C_SRX_P2 OUT1M B1
ESATA@

2
+5VALW 3 SATA_STX_C_DRX_P2_R
GND OUT0P 15 SATA_STX_C_DRX_N2_R R682 R683
18 OUT0M 14
BT MODULE CONN 13
GND
GND 0_0402_5% 0_0402_5%
1

17 SATA_DTX_SRX_P2_R @ @
BT@ GND IN1M 11 SATA_DTX_SRX_N2_R
19
IN1P 12

1
R684 BT@ GND
21
100K_0402_5% PAD
C1235
0.1U_0402_16V4Z MAX4951ETP+T_TQFN20_4X4~D
2

1 R686 2 1 2 @
100K_0402_5%
1

BT@
SATA_STX_C_DRX_P2 R685 1 ESATA@2 0_0402_5% SATA_STX_C_DRX_P2_R
OUT

SATA_STX_C_DRX_N2 R687 1 ESATA@2 0_0402_5% SATA_STX_C_DRX_N2_R

SATA_DTX_SRX_P2 R688 1 ESATA@2 0_0402_5% SATA_DTX_SRX_P2_R
2 BT@ +3VS Q81 +3VS_BT SATA_DTX_SRX_N2 R689 1 ESATA@2 0_0402_5% SATA_DTX_SRX_N2_R
[34] BT_OFF# IN Q80 30mils
GND

DTC124EKAT146_SC59-3 3 1
1
BT@ 0.1U_0402_16V4Z
3

C1236
G
2

AO3413_SOT23-3 BT@
BT@ 2
[36] BT_LED#
Q82 JP16
1

DTC124EKAT146_SC59-3 1
1
2
OUT

2
[21] USB20_P6 3 3
BT [21] USB20_N6 4
4
2 BTON_LED 5
4 IN BT_ACTIVE 5 G1 7 4
[28] BT_ACTIVE 6 8
GND

6 G2
ACES_87213-0600G
ME@
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ports/BT/E-SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 37 of 48
A B C D E
 A B C D E

+5VALW TO +5VS
+5VALW
+1.1VALW TO +1.1VS (NB HT)
+5VS
U36 +1.1VALW +1.1VS
SI4800BDY-T1-GE3_SO8 U40
8 1 AO4430L_SO8
7 2 8 1
+1.5V to +1.5VSG

2
6 3 1 1 7 2

2
1 1 5 C867 R620 @ 6 3 1 1

1
C865 C869 470_0603_5% 5 C872 R622 @ +1.5V +1.5VSG
1
10U_0805_10V4Z C863 R628 C871

4
10U_0805_10V4Z 2 2 1K_0402_5% 10U_0805_10V4Z C874 470_0603_5% PJ507 @

4
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 2 1 1

1
2 1U_0402_6.3V4Z 2

2
1
D 10U_0805_10V4Z JUMP_43X118

1
1 D 1
2 SUSP
R614 G 2 VLDT_EN# U37 DIS@ +1.5VS
B+ 1 2 2 R1191 1 5VS_GATE S Q50 @ G AO4430L_SO8

3
0_0402_5% 2N7002_SOT23 B+ 1 2 1.1VS_GATE S Q53 @ 8 1

3
100K_0402_5% 1 R613 47K_0402_5% 2N7002_SOT23 7 2
1

2
D C870 470_0603_5%
6 3 1 1
SUSP 2 1 1 1 5 R609@

1
Q65G 0.1U_0603_25V7K D C864 C859 C857 DIS@
2N7002_SOT23 S 2 VLDT_EN# 2 DIS@ C860 C858 DIS@ DIS@ 1U_0402_6.3V4Z
3

4
Q47G 0.1U_0603_25V7K 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z2 2

1
2N7002_SOT23 S 2 2 2

1
D
SUSP 2
G
+3VALW TO +3VS B+ 1 DIS@ 2 1.5VSG_GATE @ Q45 S

3
+3VS R608 2N7002_SOT23
+3VALW 100K_0402_5%
U41 1

1
SI4800BDY-T1-GE3_SO8 R610 DIS@ D DIS@
8 1 +5VALW SUSP 2 1 2 C856
7 2 G 0.1U_0603_25V7K

2
6 3 47K_0402_5% S Q46 DIS@ 2
1 1

3
2
1 1 5 C868 R626 @ 1 2N7002_SOT23
470_0603_5% R625 DIS@ C862
C861 C866 10U_0805_10V4Z C875 100K_0402_5% 0.1U_0603_25V7K
4

10U_0805_10V4Z 10U_0805_10V4Z 2 2

1 1
2 2 1U_0402_6.3V4Z 2

1
D VLDT_EN#
2 SUSP
G

1
D
B+ 2 1 2 R1192 1 3VS_GATE S
3 Q54 @
2 R619 0_0402_5% 2N7002_SOT23 Q51 2
[34,44,45,46] VLDT_EN 2
200K_0402_5% 1 G 2N7002_SOT23
1

1
D C873 S

3
SUSP 2
Q52 G
2
0.1U_0603_25V7K R618 +1.8VS to +1.8VSG
2N7002_SOT23 S 10K_0402_5%
3

2
+1.8VS +1.8VSG
U45 DIS@
SI4800BDY-T1-GE3_SO8 1U_0402_6.3V4Z
8 1
7 2

2
RTCVREF +5VALW +5VALW 6 3 R638
1 1
1 1 5 C880 @
C881 C879 DIS@ 470_0603_5%
1

10U_0805_10V4Z C878

4
R627 @ R621 DIS@ DIS@ 2 2 DIS@

1
R110 100K_0402_5% 100K_0402_5% 2 2
100K_0402_5% 10U_0805_10V4Z 10U_0805_10V4Z
+1.5VS

1
D
2

SUSP SUSP 2
[43] SUSP SYSON# G
[43] SYSON#
Q59 B+ 1 DIS@ 2 1.8VSG_GATE @ Q73 S

3
1

D D +1.5V SI2301CDS-T1-GE3_SOT23-3 +1.5VS R633 200K_0402_5% 2N7002_SOT23

[28,34,41,44,46] SUSP# 2 Q57 2 Q30
[28,34,43] SYSON

S
G 2N7002_SOT23 G 2N7002_SOT23 3 1 VLDT_EN#1 R500@ 2

D
1
1

S S 200K_0402_5% C877
3

1
D DIS@
1
R615 R623 R314 C713 R313 @ SUSP 1 DIS@ 2 2 0.1U_0603_25V7K

G
2
10K_0402_5% 10K_0402_5% 470_0603_5% G 2
100K_0402_5% 10U_0805_6.3V6M R1.0 R489 1 Q74 S
2

3
3 2 100K_0402_1% 2N7002_SOT23 3

1
R1.0 C712 DIS@
DIS@

1
D 2
0.1U_0603_25V7K
2 SUSP

1
R639 D G
SUSP# 2 1 2 Q13 S Q14 @

3
47K_0402_5% 1 G 2N7002_SOT23
S 3
C714 SSM3K7002FU_SC70-3
+VGA_PCIE +VGA_CORE +1.8VS
0.22U_0603_16V4Z2 +3VSG
2

R631 R635 @ R616 @ Q58

470_0603_5% 470_0603_5% 470_0603_5% +3VS SI2301CDS-T1-GE3_SOT23-3 +3VSG
@

S
@ 0_0402_5% 3 1

D
1

R402

2
1 2 VLDT_EN C855 1 1
1

D D D DIS@ R270 DIS@ C236 R269 @

G
2
R403 2 SUSP SUSP SUSP DIS@ 470_0603_5%

3VSG_GATE
2 1 2 2
G 0_0402_5% G G 0.1U_0603_25V7K 100K_0402_5% 10U_0805_6.3V6M
S Q67 @ S Q70 @ S Q60 @ 2 2
3

1
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 3VSG_GATE 1 2
R611 10K_0402_5%

1
DIS@ D
2 SUSP
VLDT_EN# 1 R503@ 2 G
200K_0402_5% S Q29 @

3
1
+1.5V +0.75VS +CPU_VDDR +NB_CORE +2.5VS D DIS@ 2N7002_SOT23
SUSP# 1 2 2 Q15
4 10K_0402_5% R607 1 G 4
2

DIS@ S

3
R629 @ R624 @ R605 @ R636 @ R617 @ C876 SSM3K7002FU_SC70-3
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% DIS@
2
0.1U_0603_25V7K
1

R405 @ 0_0402_5%
2 SYSON#
1 Security Classification Compal Secret Data Compal Electronics, Inc.
1

D D D D D
2 SYSON# 2 1 2 SUSP 2 VLDT_EN# 2 VLDT_EN# 2 SUSP Issued Date 2008/10/06 Deciphered Date 2010/04/30 Title
G G R404 @ 0_0402_5% G G G
S Q66 @ S 2N7002_SOT23 S Q56 @ S Q71 @ S Q61 @ DC Interface
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2N7002_SOT23 Q55 @ 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 38 of 48
A B C D E
 A B C D

ACIN BATT ONLY

Precharge detector Precharge detector
DC030006J00 VIN
Min. typ. Max. Min. typ. Max.
PF101 PL101 L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
7A_24VDC_429007.W RML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V
4

3 3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
@ 0.1U_0603_25V7K

@ 0.1U_0603_25V7K
1
2 2 1

PR101

1
1 1K_1206_5%
1 PQ101
1 2

PC104
TP0610K-T1-E3_SOT23-3

2
@ 4602-Q04C-09R 4P P2.5

PC101

PC102

PC103

PC105

PC106
PR102
JDCIN PD101 1K_1206_5%
VIN 2 1 1 2 3 1

LL4148_LL34-2 PR103
1K_1206_5%
1 2

100K_0402_1%
1

1
100K_0402_1%
PR104

PR105

2
Vin Detector

2
Min. typ. Max.
L-->H 17.430V 17.901V 18.384V

100K_0402_1%
H-->L 16.976V 17.262V 17.728V

1
PQ102

PR106
DDTC115EUA-7-F_SOT323-3

1
PR107
1M_0402_1%

1 2
1 2
VINDE-2 VIN 2
VS [34,41] ACOFF PQ103
VIN DDTC115EUA-7-F_SOT323-3
B+
2 2
0.01U_0402_25V7K

10K_0805_5%
2

3
1
1

PC107

PR109
PR108 PR110
84.5K_0402_1% 10K_0402_1%
2

3
1 2

2
PR111 ACIN [14,34]
2

22K_0402_1%
VINDE-1 1 2 3
P

+ PACIN PR113
1
0.068U_0603_16V7K

O PACIN [41]
VINDE-3 2 -
VL 2.2M_0402_5%
G
1

20K_0402_1%

10K_0402_5%
PU101A
0.1U_0402_16V7K

2 1
1

1
LM393DG_SO8
4
PC108

PR112

PC109

PR114
PD102
2

LLZ4V3B_LL34-2

499K_0402_1%
2

1
PR115
2

PR116
10K_0402_5%

100K_0402_1%
2 1 RTCVREF 3.3V

1
PR117

2
2

8
PD103
[6,40,42] MAINPWON 2 5

P
+
VIN 1 7 O

205K_0402_1%

499K_0402_1%
[41] ACON 3 6

0.01U_0402_25V7K
-

1
PU101B

1
PR118

PR119

PC112
BAS40CW _SOT323-3 LM393DG_SO8

1000P_0402_50V7K
4
2

1
3 3

PC111
PD104

0.1U_0603_25V7K

2
LL4148_LL34-2

PRG++ 2

2
1

PC113
PD105
1

LL4148_LL34-2 51ON-1

2
BATT+ 2 1
1

PR121 PR122 PR124 PQ105 PR125

1
PQ104 68_1206_5% 68_1206_5% 10K_0402_5% D 2N7002KW _SOT323-3 47K_0402_5%
TP0610K-T1-E3_SOT23-3 2 1 2 2 1
PR123 RTCVREF G PACIN [41]
2

1
200_0603_5% S

3
CHGRTCP 1 2 51ON-2 3 1 PQ106
VS DDTC115EUA-7-F_SOT323-3
0.22U_0603_25V7K
1

2 +5VALW
2

1
PC114

PR126 PC115
100K_0402_1% 0.1U_0603_25V7K
1

PR127
2

3
22K_0402_1%
1 2 51ON-3
[32] 51_ON# - JRTC + PR129
560_0603_5%
2 1 1 2 +RTCBATT

RTCVREF PD106
1

@ MAXEL_ML1220T10 1 2
PR128 +CHGRTC
PU102 200_0603_5% RB751V-40_SOD323-2
4 +CHGRTC PR130 G920AT24U_SOT89-3 4

560_0603_5% 3.3V
RTC Battery
2

1 2 3 OUT IN 2CHGRTCIN
1

GND PC117
PC116 1U_0805_25V6K
10U_0603_6.3V6M 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 39 of 48
A B C D
 A B C D

1 1

VMB2 VMB
PF201 PL201
JBATT 12A_65V_451012MRL SMB3025500YA_2P
1 1 1 2 1 2 BATT+
2 2
3 EC_SMCA
3 EC_SMDA
4 4
5 5

1
6 6
1

PC201 PC202
7 7
0.01U_0402_25V7K PH1 under CPU botten side :
100_0402_1%

100_0402_1%

8 1000P_0402_50V7K

2
GND
GND 9 CPU thermal protection at 92 degree C
PR204

PR206

TYCO_1775789-1
Recovery at 56 degree C
2

2 2

VL
EC_SMB_CK1 [34]
VL
EC_SMB_DA1 [34]

2
1 2 +3VALW PC208 PR212 PR214
PR209 0.1U_0603_25V7K 10K_0402_1% 21.5K_0402_1% PR215

2
6.49K_0402_1% @ 100K_0402_1%

2
PU202

1
1
PR211
2 BATT_TEMP [34] A/D 1 VCC TMSNS1 8

2
10K_0402_5% 2 7
GND RHYST1 PR213
3 6 9.76K_0402_1%
VS OT1 TMSNS2

@ 47K_0402_1%
4 5

1
OT2 RHYST2

2
+3VALW +3VALW
0.01U_0402_25V7K

1
PR216
G718TM1U_SOT23-8
PH202
1

PC62

100K_0402_1%_TSM0B104F4251RZ
2

VMB2

1
PR84 PR88
2

2
100K_0402_1% 10K_0402_1% MAINPW ON [6,39,42]
PR87 PR83
2

1
649K_0402_1% 5.1M_0402_5%
1

1 2 PH203
BATT_OUT# [41]
@ 100K_0402_1%_TSM0B104F4251RZ
PR86
8

3 3

100K_0402_1% PQ316
1

2
1

D 2N7002KW _SOT323-3
1 2 3
P

+
O 1 2
PR89 2 G
-
G
2

442K_0402_1% PU902A S
3

LM393DG_SO8
4
1

2 1 RTCVREF
PR85
10K_0402_1%
8

5
P

+
O 7
6 -
G

PU902B
LM393DG_SO8
4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 40 of 48
A B C D
 5 4 3 2 1

P3
B+
P2
PQ301 PQ302
FDS6675BZ_SO8 FDS6675BZ_SO8
PR302
VIN 8
7
1
2
1
2
8
7 0.02_1206_1% CHG_B+
6 3 3 6 PJ301
PQ303
5 5 1 4 2 2 1 1
FDS6675BZ_SO8

470P_0603_50V8J
2 3 @ JUMP_43X118 1 8
VIN

1
47K_0402_5%

2 7
1

PC302

2200P_0402_50V7K
3 6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
PR301

0.1U_0603_25V7K
5

2
2

PC303

PC304
1

2
PC306

PC305
PQ304 PR951

200K_0402_1%
0.1U_0603_25V7K

4
1
47K_0402_1% CSIN
2

PC301

PR303
PDTA144EU_SOT323-3 CSIP

1
47K @ PR304

1
PQ913B 47K_0402_1%

2
2 47K 2N7002KDW -2N_SOT363-6 1 2

2
VIN

3
BATT_OUT# [40]
1

2
2 5 PD301
RB751V-40_SOD323-2 PR305
1

1 2 10K_0402_1%

4
6251_VDD PQ21 PQ306
2 PQ913A 2N7002KW _SOT323-3 DDTC115EUA-7-F_SOT323-3 PR308

2.2U_0603_6.3V6K

1 1
PC307
PQ305 2N7002KDW -2N_SOT363-6 PR306 200K_0402_1%

1
10K_0402_1% 1 2 VIN

1
DDTC115EUA-7-F_SOT323-3 PU301 PC309 D
2 1
[34] FSTCHG 0.1U_0603_25V7K ACOFF-12
3

2
1 2 1 24 6251_DCIN2 1 G
VDD DCIN

1
PC308

100K_0402_1%
S 2

3
PQ307 0.1U_0402_16V7K
1

D 2N7002KW _SOT323-3

PR307
150K_0402_1%

2 ACSET ACPRN 23
PR309

2 PR310

SIS412DN-T1-GE3_POWERPAK8-5
G 20_0402_5%

0.1U_0603_25V7K
2

3
5

1
6251_EN CSON D
S 3 22 1 2
3

EN CSON

1
PQ308

PC311
PC310 2 PACIN
2

0.047U_0402_16V7K G
CELLS 4 21 1 2 CSOP S

3
CELLS CSOP PR311 PQ309
C PC312 6800P_0402_25V7K 20_0402_5% 2N7002KW _SOT323-3 C
4
PR313 PQ310 1 2 5 20 2 1
ICOMP CSIN
1

2
3K_0402_1% D 2N7002KW _SOT323-3 PR312
PACIN 1 2 2 PC314 PR314 6.81K_0402_1% PC313 20_0402_5%
[39] PACIN
G 1 2 1 2 6 19 0.1U_0402_16V7K
1 2 PL301 PR317

3
2
1
VCOMP CSIP PR315 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
S
3

0.01U_0402_25V7K 1 2 2.2_0402_5% BATT+

PC315 1 2 7 18 LX_CHG 1 2 CHG
1 4
@ 100P_0402_50V8J PR316 ICM PHASE
[39] ACON

5
[34] ADP_I 100_0402_1% 2 3

SI7716ADN-T1-GE3 _PAK1212-8

1
6251_VREF DH_CHG

@ 4.7_1206_5%
8 VREF UGATE 17

PR319
PR318 PR320 PC317
2N7002KW_SOT323-3

1 2
154K_0402_1% PC316 0_0402_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ312
PQ311 2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1
[34] IREF CHLIM BOOT
1

1
D

PC318
PR321 4

1
PC319

PC320
1 2ACOFF-1 2 16.9K_0402_1% PD303
0.01U_0402_25V7K

[34,39] ACOFF
G 6251_VREF 1 2 10 15 6251_VDDP RB751V-40_SOD323-2
ACLIM VDDP
1

1
PR950 S
3

2
1
PC321

100K_0402_1% PR322 26251_VDD

@ 680P_0603_50V7K
2N7002KW_SOT323-3

3
2
1
1

PC322
100K_0402_1% 11 14 DL_CHG

2
VADJ LGATE

1
PQ20 PR324 PR323
2
1

D 27.4K_0402_1% 4.7_0402_5%
2

2 12 13 PC323
[40] BATT_OUT#

2
G GND PGND 4.7U_0805_6.3V6K
2

S @
3

ISL6251AHAZ-T_QSOP24
PR325
Connect to EC A/D Pin. 15.4K_0402_1%
1 2
[34] CHGVADJ
B B
1

6251_VDD 6251_VDD
PR326
31.6K_0402_1% UMA CP mode

2
Vaclim=2.39*((152K//1.74K)/((152K//1.74K)+(152K//16.9K)))=0.243V PR327 PR328
2

100K_0402_1% 100K_0402_1%
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.243V, Iinput=2.75A @ @

1
CELLS

3
CHGVADJ=(Vcell-4)/0.10627 DIS CP mode PR330 @
Vcell CHGVADJ Vaclim=2.39*((152K//27.4K)/((152K//27.4K)+(152K//16.9K)))=1.44V 0_0402_5% 2 5 2 1
PR331
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)

2
4V 0V 0_0402_5%

4
where Vaclim=1.44V, Iinput=4A [34] BATT_SEL_EC
PQ314 TP0610K-T1-E3_SOT23-3 PR333
4.2V 1.882V PQ313A PQ313B
10_0603_5% 4.35V 3.2935V 2N7002KDW -2N_SOT363-6 2N7002KDW -2N_SOT363-6
3 1 1 2 6251_DCIN @ @
P3
1
100K_0402_1%

CC=0.25A~3A
PR335

IREF=1.016*Icharge
2

PR337 IREF=0.254V~3.048V
2

2 1

100K_0402_1% PQ315
VCHLIM need over 95mV
A A
DDTC115EUA-7-F_SOT323-3
1

PD304
2 FSTCHG
2 1
FSTCHG [34]
3 SUSP# Security Classification Compal Secret Data Compal Electronics, Inc.
SUSP# [28,34,38,44,46] 2007/6/22 2010/04/30 Title
BAS40CW _SOT323-3
Issued Date Deciphered Date
CHARGER
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 41 of 48

5 4 3 2 1
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJ401 PR401
@ JUMP_43X118 0_0402_5%
2 2 1 1 1 2

330P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D

1
PC405

PC401

PC423

PC403

PC404

PC422

PC406
5

1U_0603_10V6K
VL

2
2
2

PC408
PC407
PQ401 0.1U_0603_25V7K 4

4.7U_0805_6.3V6K
3/5V_VCC
1

1
3/5V_VIN
4 SIS412DN-T1-GE3_PAK1212-8

PC409
PQ402 +5VALWP

2
SIS412DN-T1-GE3_PAK1212-8

3
2
1
PL402

1
2
3
PL401 4.7UH_FMJ-0630T-4R7 HF_5.5A_20%

7
4.7UH_FMJ-0630T-4R7 HF_5.5A_20% PU401 PC410 1 2
1 2 1U_0603_10V6K

VIN

V5FILT

LDO
+3VALWP 33 19 1 2
TP V5DRV

1
1

5
UG3 26 15 HG5
PR402 DRVH2 DRVH1 PR404
0_0402_5%

4.7_1206_5% BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 4.7_1206_5% 1

VBST2 VBST1
2

PR403 PR405

15V_SNB
1

2
2

2
+
PR406

2.2_0603_5% 2.2_0603_5% PC413

@ 61.9K_0402_1%
4

13V_SNB
2
+ 4 PC411 150U_B2_6.3VM_R45M

2
PC421 0.1U_0603_25V7K

1
2

PR407
150U_B2_6.3VM_R45M SW 3 25 16 SW 5
1

2 PC414 LL2 LL1 PC412 PC415

3
2
1
330P_0603_50V8 0.1U_0603_25V7K 330P_0603_50V8

1
2
3

2
2 LG3 23 18 LG5

1
PQ403 DRVL2 DRVL1
10K_0402_1%

SI7716ADN-T1-GE3_PAK1212-8
2

PGND 22

2
C C
PR408

FB3 30 PQ404
VOUT2

PR409
0_0402_5%
SI7716ADN-T1-GE3_PAK1212-8
VOUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 VREF2
PC416
0.22U_0603_25V7K 9
VSW
8 LDOREFIN PR410
PD401 29 5V_SKIP 2 1 VL
SKIPSEL @ 0_0402_5%
VL
1 2

100K_0402_1%
1
RB751V-40_SOD323-2 1 PR411 2

PR422
20 28 0_0402_5%
PR412 NC PGOOD2 2VREF_ISL6237
2 PR421 1
VS PD402 100K_0402_1% @ 0_0402_5%
1 2 EN_LDO-1 1 2 EN_LDO 4 13

2
EN_LDO PGOOD1
SPOK [43]
2

LLZ5V1B_LL34-2
200K_0402_1%

2
PR413

PC417 3/5V_EN1 14 12 ILM1 2 1

0.22U_0603_25V7K EN1 TRIP1 PR414
301K_0402_1%

TONSE
VREF3
1

3/5V_EN2 27 31 ILIM2 2 1

GND
1

EN2 TRIP2
2 PR415
RT8206B_QFN32_5X5 301K_0402_1%

21
B VL B
PD403
806K_0603_1%

13/5V_NC
2

1 2 PR416

13/5V_TON
PR417

0_0402_5%
1

RB751V-40_SOD323-2 PR419 1U_0603_10V6K

PC418

@ 47K_0402_1%
2VREF_ISL6237

PR418
1

2 1 1 2
2

0_0402_5% PR420
0.047U_0402_16V7K

0.047U_0402_16V7K

MAINPW ON [6,39,40] 0_0402_5% PJ402

1

+3VALWP 2 1 +3VALW
2

2 1
PC419

PC420

@ JUMP_43X118
2

2VREF_ISL6237

@ PJ403
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/01/06 2010/04/30
Issued Date Deciphered Date Title
3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 42 of 48
5 4 3 2 1
 5 4 3 2 1

PJ501
1.1V_IN 2 1 B+
2 1
@ JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8
PQ501

2200P_0402_50V7K
SI4172DY-T1-GE3_SO8

1
PC502

PC503

PC504
PR502

2
240K_0402_1% 4
1.1V_TON 1 2
PR501 PR503
D PC505 D
0_0402_5% 0_0402_5%
1 2 1.1V_EN BST_1.1V 1 2BST_1.1V-1
1 2
[42] SPOK

3
2
1
0.1U_0603_25V7K

1
PL501

15

14
1
PC501 1.8UH_SIL104R-1R8PF_9.5A_30%
@0.01U_0402_25V7K 1 2

EN_PSV

TP

VBST
+1.1VALW P

1
2 13 UG_1.1V
TON DRVH

220U_B2_2.5VM_R15M
PR505 3 12 SW _1.1V PR504
VOUT LL

5
6
7
8
100_0603_1% 4.7_1206_5%

10U_0805_6.3V6M
1
+5VALW 1 2 1.1V_V5FILT 4 11 1.1V_TRIP
1 2 +5VALW

2
V5FILT TRIP

1
+

PC506

PC507
PR506

1.1V_SNB
1.1V_FB 5 10 11.5K_0402_1% PQ502
VFB V5DRV SI4634DY-T1-E3_SO8

2
1
LG_1.1V 2
6 PGOOD DRVL 9 4

PGND
PC508

GND
4.7U_0603_6.3V6K PC509
2

1
@ 47P_0402_50V8J PC511
1 2 PC510 680P_0603_50V7K

3
2
1
PU501 4.7U_0805_6.3V6K

2
TPS51117RGYR_QFN14_3.5x3.5

PR508
9.76K_0402_1%
1 2
1

PR509 PJ502
C 20.5K_0402_1% 1.5V_IN C
2 2 1 1 B+
2

@
JUMP_43X79

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8
PQ503

2200P_0402_50V7K
SI4172DY-T1-GE3_SO8

1
PC513

PC514
PR522

PC515
@ 0_0402_5% PR510

2
1 2 240K_0402_1% 4
[34] VDDIO
1.5V_TON 1 2
PR511
0_0402_5%
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2
[28,34,38] SYSON

3
2
1
PR512 PC516
0_0402_5% 0.1U_0603_25V7K
1

PL502

15

14
1
PC517 1.0UH_PCMC104T-1R0MN_20A_20%
0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.5VP
2

1
2 13 UG_1.5V
TON DRVH
PR514 SW _1.5V PR513

220U_B2_2.5VM_R15M
3 VOUT LL 12

5
100_0603_1% @ 4.7_1206_5%

10U_0805_6.3V6M
1
+5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW PQ504

1.5V_SNB 2
V5FILT TRIP

1
+

PC518

PC519
PR515

TPCA8028-H_SOP-ADVANCE8-5
1.5V_FB 5 10 11.5K_0402_1%
VFB V5DRV

2
1

LG_1.5V 2
6 PGOOD DRVL 9 4
PGND

PC520
GND

4.7U_0603_6.3V6K PC521
2

1
@ 47P_0402_50V8J PC524
B 1 2 PC523 @ 680P_0603_50V7K B
7

3
2
1
PU502 4.7U_0805_6.3V6K

2
TPS51117RGYR_QFN14_3.5x3.5

PR517
22.1K_0402_1%
1 2
1

PR518
22.1K_0402_1%
2

+1.5V PJ503
+1.1VALWP 2 2 1 1 +1.1VALW
@ JUMP_43X118
1

PJ504
1

@ JUMP_43X79
2

PJ505
PU503 2 1
+1.5VP +1.5V
2

0.75V_IN 2 1
1 VIN VCNTL 6 +3VALW
PC525 @ JUMP_43X118
4.7U_0805_6.3V6K 2 5
GND NC
1

1
1

3 7 PC526
PR523 PR519 VREF NC 1U_0402_6.3V6K
2

0_0402_5% @ 1K_0402_1% 4 8 PJ506

VOUT NC
A [38] SUSP 1 2 +0.75VSP 2 2 1 1 +0.75VS A
9
2

TP @ JUMP_43X79
0.75V_REF G2992F1U_SO8
1

PR520 +0.75VSP
1

0_0402_5% D PR521
1 20.75V_EN 2 1K_0402_1% PC527
[38] SYSON# Security Classification Compal Secret Data Compal Electronics, Inc.
1

G 0.1U_0402_16V7K
2
1

S PQ505 PC530
Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title
3

PC528 SSM3K7002FU_SC70-3 10U_0805_6.3V6M

1.1V/1.5V/0.75V
2

@ 0.1U_0402_16V7K
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
PC529 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
10U_0805_6.3V6M MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 43 of 48
5 4 3 2 1
 5 4 3 2 1

PJ607
2 1 VGA_IN
B+ 2 1
@ JUMP_43X79

UG_VGA

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
1

1
BST_VGA 1 2 BST_VGA-1 1 2

PC630

PC619
PR619 PC633

PC626
0_0402_5% 0.1U_0603_25V7K

2
D D

+5VALW

1
PR50

5
0_0603_5%
PQ603
PR47
4.7_0603_5%

16

15

2
8

1
PU4 1 2 VGA_VCC
4

GND

PGOOD

PHASE

UG

BOOT
3 14 +VGA_PVCC
1 2
VIN PVCC TPCA8030-H_SOP-ADV8-5

3
2
1
PC53
2.2U_0603_6.3V6K
PR623 VGA_VCC 4 13 LG_VGA PL603
@ 0_0402_5% VCC LG 0.88UH_PCMC104T-R88MN_20A_20% +VGA_COREP
2 1 SW _VGA 1 2
[34,38,45,46] VLDT_EN

1
APW 7138NITRL_SSOP16

1
PC51

4.7_1206_5%

150U_B2_6.3VM_R45M
PGND 12
2.2U_0603_6.3V6K PQ604

PR616
1VGA_SNB

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
1 1

330U_D2_2.5VY_R15M
1 2 VGA_EN_2 5 11 ISEN_VGA
1 2
[28,34,38,41,46] SUSP#

2
EN ISEN

1
+ +

PC424
PR614 4

FSET
2.2K_0402_5% PR618

PC627

PC631

PC623

PC629
NC

VO
PC628 2.87K_0402_1%

680P_0603_50V7K
FB

2
2 2

PC632
1U_0402_6.3V6K

2
TPCA8028-H_SOP-ADVANCE8-5 @

FSET_VGA9

10

3
2
1

2
C C

VGA_FB
VGA_COMP @

22.1K_0402_1%

0.01U_0402_25V7K
1

42.2K_0402_1%
22P_0402_50V8J

2
1
PR71
@

1VGA_COMP-1
PC135

PC56

PR76
2

2
1

1
6800P_0402_25V7K
2

@ @
PC57

+3VALW
2

PR183
17.4K_0402_1%
1

VGA_FB-1
10K_0402_1%

1 2 2 1
PR634

VFB=0.6V PR185 PJ606

1
GVID1-2 4.99K_0402_1% 2 1
+VGA_COREP 2 1 +VGA_CORE
6

PR169 PR184
10K_0402_1% 23.2K_0402_1% @ JUMP_43X118
2

2 1GVID1-1 2 PQ912A

2
1

PQ911A 2N7002KDW -2N_SOT363-6 PJ608

6

2N7002KDW -2N_SOT363-6 PR170 PR70 2 1

1

10K_0402_5% 13.7K_0402_1% 2 1
PC133 @ JUMP_43X118
2

B 2 1 2 0.022U_0402_16V7K B
[14] GPU_VID1
2

PR181 +3VALW VGA_PWRSEL0 VGA_PWRSEL1 Park XT

2
1

10K_0402_1% GVID0-2
1

PR186
1

GPU_VID0 GPU_VID1 Core Voltage Level

10K_0402_1%

10K_0402_5% @
PR635

3
2

1 1 0.9V
2

2 1GVID0-1 PQ912B
5
PR182 PC132 2N7002KDW -2N_SOT363-6 1 0 0.95V
3

PQ911B 10K_0402_1% 0.022U_0402_16V7K

4

2N7002KDW -2N_SOT363-6 PR75

10K_0402_5% 0 0 1.12 V
2

2 1 5
[14] GPU_VID0 PR177
2
1

10K_0402_1%
4

PR178
10K_0402_5% @
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 44 of 48
5 4 3 2 1
 5 4 3 2 1

PJ701
NB_CORE_IN 2 1 B+
2 1
D D
@ JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8
PQ701

2200P_0402_50V7K
SI4172DY-T1-GE3_SO8

1
PC702

PC703

PC705
PR702

2
240K_0402_1% 4
NB_CORE_TON 1 2
PR701
0_0402_5%
VLDT_EN 1 2 NB_CORE_EN BST_NB_CORE
1 2BST_NB_CORE-1
1 2
[34,38,44,46] VLDT_EN

3
2
1
PR703 PC706
0_0402_5% 0.1U_0603_25V7K

1
PD804 PL701

15

14
1
RB751V-40_SOD323-2 PC701 1.8UH_SIL104R-1R8PF_9.5A_30%
1 2 0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+NB_COREP

1
2 13 UG_NB_CORE
TON DRVH

220U_B2_2.5VM_R15M
PR705 3 12 NB_CORE_SW PR704
VOUT LL

5
6
7
8
100_0603_1% @ 4.7_1206_5%

NB_CORE_SNB

10U_0805_6.3V6M
1
+5VALW 1 2 NB_CORE_V5FILT4 11 NB_CORE_TRIP
1 2 +5VALW

2
V5FILT TRIP

1
+

PC707

PC708
PR706 PQ702
NB_CORE_FB 5 10 9.1K_0402_1%
VFB V5DRV SI4634DY-T1-E3_SO8

2
1

LG_NB_CORE 2
6 PGOOD DRVL 9 4

PGND
PC709

GND
4.7U_0603_6.3V6K PC710
2

1
@ 47P_0402_50V8J
1 2 PC712 PC713

3
2
1
PU701 4.7U_0805_6.3V6K @ 470P_0402_50V7K

2
C TPS51117RGYR_QFN14_3.5x3.5 C

PR708
+5VALW 31.6K_0402_1%
1 2
1

10K_0402_1%

1
PR709

PJ702
+NB_COREP 2 2 1 1 +NB_CORE
PR710 PR711 POWER_SEL
95.3K_0402_1% 95.3K_0402_1% @ JUMP_43X118
2

11

D
PR712 HIGH 0.95V
2 1PW RSEL-1
2 PJ703
[11] POWER_SEL PQ704 10K_0402_1% G
2N7002KW_SOT323-3

2 2 1 1
1

D
PR713 S PQ703 LOW 1.25V
3

2 1 2 2N7002KW _SOT323-3 @ JUMP_43X118

1

0_0402_5% G
1

+1.5V
PC714

PC715
0.01U_0402_25V7K

S
3

0.1U_0402_16V7K
2

PJ705
2

+5VALW

1
+CPU_VDDRP 2 2 1 1 +CPU_VDDR
PJ704

1
@ JUMP_43X79
@ JUMP_43X79
1

2
PC716
1U_0402_6.3V6K

2
2

PU702
6

APL5912-KAC-TRL_SO8

1
B 5 PC718 B
VCNTL

VIN 4.7U_0805_6.3V6K
7 POK
VOUT 4 2
PR714
3
10K_0402_1% VOUT +CPU_VDDRP

1
VLDT_EN

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 2 8 2

0.01U_0402_25V7K
EN FB

1
GND
1

1
PC719
9 PR716
VIN
1

PR715 @ 31.6K_0402_1%

2
47K_0402_5%

PC711

PC722

PC723
PC717
1

2
0.1U_0402_16V7K
2

+5VALW PR718 PR717

165K_0402_1% 249K_0402_1%
2

@
1

PR719
10K_0402_5%
1

D
2 VDDR_SW
2

[22] VDDR_SW G
S PQ705
3

2N7002KW _SOT323-3 HIGH 1.05V

1

PR720
10K_0402_5% PC721 LOW 0.9V
@0.1U_0402_16V7K
2

A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+NB_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 45 of 48
5 4 3 2 1
 5 4 3 2 1

D D

PU803
APL5508-25DC-TRL_SOT89-3

+3VS 2 3
IN OUT +2.5VSP

1
4.7U_0805_6.3V6K
PC811

1
GND

2
1

PC812
1U_0402_6.3V6K 1 @ PR809
150_1206_5%
2

2
+1.5V

+5VALW

1
PJ806

1
JUMP_43X79
+5VALW
@
1

2
C PC816 C
PD802 1U_0402_6.3V6K

2
2

@ RB751V-40_SOD323-2
1

1 2

1
PR817 PC815
@ 0_0402_5% 4.7U_0805_6.3V6K
6

PR814 PU804 2
@ 0_0402_5% 5
VCNTL
2

VLDT_EN VIN
1 2 7
[34,38,44,45] VLDT_EN POK
4 +VGA_PCIEP
PR813 VOUT
3
VOUT
1

1
15K_0402_5%

22U_0805_6.3V6M
SUSP#

PC817
1 2 8 2
EN FB
1

[28,34,38,41,44] SUSP# PR812

GND

2
1

PD803 9 1.15K_0402_1%
RB751V-40_SOD323-2 PR810 VIN
2

1 2 @ 47K_0402_5% APL5912-KAC-TRL_SO8 PJ805

2

PC814 2 1
+2.5VSP +2.5VS
2

@ 1U_0603_10V6K PC813 2 1
1

0.01U_0402_25V7K @ JUMP_43X79
VGA_PCIE 1.0V 1.1 V
PR811
4.53K_0402_1%
PJ807
2

PR811 4.53K 3K +VGA_PCIEP 2

2 1
1 +VGA_PCIE
@ JUMP_43X118

PJ801
+1.8VSP 2 1 +1.8VS
2 1
@ JUMP_43X118

B B
PU802 PL801
PJ802
4

SY8033BDBC_DFN10_3X3 4.7UH_PCMC063T-4R7MN_5.5A_20%
1 2 10 2 LX_1.8V 1 2
+5VALW
PG

1 2 PVIN LX +1.8VSP
1

9 3 FB_1.8V
4.7_1206_5%

JUMP_43X79 PVIN LX
1

@ PC820
PR822

8
22U_0805_6.3VAM SVIN
6
1.8VSP
2

1 2

FB
5 TDC 2 A
22U_0805_6.3VAM

22U_0805_6.3VAM
EN
1

1
NC

NC
TP

680P_0603_50V7K

Peak Current 3 A
PC822

PC824

PC825

[28,34,38,41,44] SUSP#
11

1 2 EN_1.8V

PR821 0_0402_5%
0.1U_0402_10V7K
1

PC823
1

PR92
PD805 1M_0402_1% FB=0.6V PR819
RB751V-40_SOD323-2 @ 2 1
2

1 2 30K_0402_1%
2

PR818 2 1
@ 14.7K_0402_1%
PC64
@
2

22P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5VS/PCIE/1.8VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 46 of 48
5 4 3 2 1
 8 7 6 5 4 3 2 1

H H

CPU_B+ PL901
LGATE_NB HCB4532KF-800T90_1812
PC901 1 2 B+
33P_0402_50V8K

2200P_0402_50V7K
4.7U_0805_25V6-K

0.01U_0402_25V7K
2 1

100U_25V_M
1

1
PQ901 +

PC903

PC904

PC905

PC906
2 1 2 1 UGATE_NB 8 1
G2 D2
7 2

2
PR901 PC902 S2/D1 D2 2
6 3
44.2K_0402_1% 1200P_0402_50V7K S2/D1 G1
5 4
PR902 S2/D1 S1
2_0603_5% AO4932_SO8
+5VS 1 2 PC907 PL902
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB
2 1 PHASE_NB 1 2
G PR903
+VDDNB G

1
PC908 PR904 0_0603_5%
0.1U_0402_16V7K 22K_0402_1%
2 1
BOOT_NB 1 2 1 2 PR905
4.7_1206_5% 1
Design Current: 2.8A

2
PR906
10_0402_5%
PC909
0.22U_0603_10V7K + PC910
Max current: 4A

1 2
1 2
1 2 +CPU_CORE_NB
PC911
220U_D2_4VM OCP_min:5A
CPU_B+ 2
680P_0603_50V7K
PR907
CPU_VDDNB_FB_H [6]

2
2_0603_5% PR909
+5VS +3VS 11.3K_0402_1%

1
2 1 PHASE_NB
PR908
0_0402_5% LGATE_NB

1
PC912 CPU_B+
0.1U_0402_16V7K PHASE_NB

2
1

2
PR910 PR911 UGATE_NB

2200P_0402_50V7K
0.01U_0402_25V7K
F 0_0402_5% @ 105K_0402_1% F

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
2 1 CPU_VDDNB_FB_L [6]

TPCA8030-H_SOP-ADV8-5
PR912
2

2
1

1
0_0402_5%

PC915

PC913

PC916

PC914
PR914

1
PR913 @ 10K_0402_1% PR915

PQ903

2
105K_0402_1% PR916 10_0402_5% UGATE0 4
@ 105K_0402_1%

48

47

46

45

44

43

42

41

40

39

38

37
2

1
PU901
PHASE0 PL903

VIN

VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
2

PR917 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
2.2_0603_5%
[34] VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 4 +CPU_CORE
PR918 0_0402_5% OFS/VFIXEN BOOT_NB
1 2 2 35 BOOT0 PC917 PR922 2 3
PGOOD BOOT0

2
[20] H_PWRGD_L

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
1 2 0.22U_0603_10V7K 16.2K_0402_1%

1
PR919 0_0402_5% @ 3 34 UGATE0
PWROK UGATE0 PR920
PHASE0 4.7_1206_5%

PQ902

PQ904
E 2 1 4 33 E
[6] CPU_SVD PR921 0_0402_5% SVD PHASE0
1 PR923 2

1
5 32 4 4 4.02K_0402_1%

1 2
SVC PGND0 +5VS
2 1
[6] CPU_SVC PR924 0_0402_5% 6 31 LGATE0 PC918 PC919
ENABLE LGATE0 680P_0603_50V7K 2 1
7 30

3
2
1

3
2
1

2
RBIAS PVCC 0.1U_0402_16V7K
[34] VR_ON 8 29 LGATE1
OCSET LGATE1

1
PR925 PR926 ISL6265IRZ-T_QFN48_6X6~D PC920
2 1 2 1 9 28 1U_0603_16V6K LGATE0
21.5K_0402_1% 95.3K_0402_1% VDIFF0 PGND1

ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE
VW0 BOOT1
Design Current: 25A
COMP1
VDIFF1
VSEN0

VSEN1
RTN0

RTN1
ISN0

ISN1
ISP0

VW1

ISP1

2200P_0402_50V7K
0.01U_0402_25V7K
FB1
Max current: 35A

TP
D D

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5

TPCA8030-H_SOP-ADV8-5
OCP_min:45A
13

14

15

16

17

18

19

20

21

22

23

24

49

1
PC921

PC922

PC923

PC924
ISP0
PR927 0_0402_5%

ISN0

PQ905

2
1

ISN1
ISP1
UGATE1 4
[6] CPU_VDD0_FB_H 0_0402_5%
0_0402_5%
2 PR930 1

2 PR931 1

PR928 PR929
0_0402_5%

+CPU_CORE 2 1 1 2 PHASE1 PL904

10_0402_5% PR932 0.36UH_PCMC104T-R36MN1R17_30A_20%
2

3
2
1
2.2_0603_5%
[6] CPU_VDD0_FB_L BOOT1 1 2 1 2 1 4 +CPU_CORE
PR933 10_0402_5%
2 1 PC925 2 3

2
TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
0.22U_0603_10V7K PR936

1
16.2K_0402_1%
[6] CPU_VDD1_FB_L PR935 10K_0402_1%
PR934

PQ906

PQ907
2 1
C 4.7_1206_5% 1 PR937 2 C

1
@ PR938 1K_0402_1% 4 4 4.02K_0402_1%

1 2
+1.5VS 2 1
PC926 PC927
[6] CPU_VDD1_FB_H 680P_0603_50V7K 2 1
PR939

3
2
1

3
2
1

2
+CPU_CORE 2 10_0402_5%
1 0.1U_0402_16V7K

DIFF_0 VW0 DIFF_1 VW1

LGATE1
PR940 PC928 PR941 PC931

ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1

PC929 PC930 PC932 PC933

180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K

PR942 PR944 PR945 PR947

1K_0402_5% PR943 PC934 6.81K_0402_1% 1K_0402_5% PR946 PC935 6.81K_0402_1%
B B
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

1

PR948
@ 1K_0402_1% PR949
@ 1K_0402_1%
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/06 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, May 18, 2010 Sheet 47 of 48
8 7 6 5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for HW

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
0.2 6
1 Del NC parts cpu internal sensor & debug port parts NC Del U2,R41,R42,C22,Q2,Q3 2010-02-24 PVT_NAWE5

2 Add Park HDMI strap pin DIS park HDMI abnomal 0.2 14 Add R120,121 (10k.0402) 2010-02-24 PVT_NAWE5

D
3 EMC1412-A address resister Reserve thermal sensor address 0.2 14 Add R637 (4.7k.0402) 2010-02-24 PVT_NAWE5 D

4 change to Interanl clk GEN modify Interanl clk PU resister 0.2 19 change R219,R220,R221,R222 Pin 2 2010-02-24 PVT_NAWE5
from +3VS_CLK to +3VS
0.2
change to Interanl clk GEN using internal CLK GEN 19 Del EXT@ parts to INT@ parts 2010-02-24 PVT_NAWE5
5
change new card PCIE new card pcie port from NB to SB 0.2 20 PCIE_SB_EXPCARD_TXP;PCIE_SB_EXPCARD_TXN 2010-02-24 PVT_NAWE5
6 PCIE_EXPCARD_SB_RXP;PCIE_EXPCARD_SB_RXN
2010-02-24 PVT_NAWE5
Reserve UMA/DIS HDMI strap pin BIOS demand 0.2 21 add R366;R370 (10k,0402)
7
add R545 (0R.0402)
new card function ADD CPUSB# signal 0.2 21 2010-02-24 PVT_NAWE5
8
Change Cap footprint size Change footprint for ME interfere 0.2 23 change C590,,C617,C618 from 10uF.0805 to 0603 2010-02-24 PVT_NAWE5
9
C591,C595,22uF Change to 10uF0603
Change Cap footprint size Change footprint for ME interfere 0.2 23 2010-02-24 PVT_NAWE5
10
change R431 location modify BKOFF# PD resister 0.2 27 R431 (10k.0402) 2010-02-24 PVT_NAWE5
11
Add LCD_ENVDD PD Resister to prevent LCD flicker issue 0.2 27 add R432 (2.2k.0402) 2010-02-24 PVT_NAWE5
12
C C
disable VARY_ BL Function back light controll change to EC 0.2 27 add 451 (0ohm.0402) del R450;R452(0ohm.0402) 2010-02-24 PVT_NAWE5
13
Mimi card leakage issue fix Intel WLAN card leagage issue 0.2 28 Add R719 (100k.0402) add R660;R661(100ohm.0402) 2010-02-24 PVT_NAWE5
14
reserve resister for Intel WLAN for Intel WLAN LED use 0.2 28 add R658 (0ohm.0402) 2010-02-24 PVT_NAWE5
15
change CLKREQ_LAN# PU resister flash Lan MAC sometime has fail 0.2 29 Add R254 (4.7k.0402) del R219 (8.2k.0402) 2010-02-24 PVT_NAWE5
16
Del LAN NC parts disable EN_WOL# Function 0.2 29 del Q43,R274,C495,Q42,C496 2010-02-24 PVT_NAWE5
17
LAN Cystal accurate modify cystal 25MHz of CAP 0.2 29 change C203,C202 from( 27pF to 33pF.0402) 2010-02-24 PVT_NAWE5
18
codec common design codec Internal MIC cap del 0.2 33 Add R612 (0ohm.0402) Del (C516 2.2uF.0603) 2010-02-24 PVT_NAWE5
19
KBC Cystal accurate modify cystal 32.768KHz of CAP 0.2 34 change C730,C733 from(15pF to 27pF.0402) 2010-02-24 PVT_NAWE5
20
change ROM footprint ROM pakage from 150mil to 200mil 0.2 36 change U30 pakage size 2010-02-24 PVT_NAWE5
21
BT_LED controll BT_LED no need diode 0.2 36 Del D20 2010-02-24 PVT_NAWE5
22
leakage issue fix +3VS leakage 0.2 38 Del R627 (100k,0402) add R110 (100k,0402) 2010-02-24 PVT_NAWE5
B 23 B
del R620,Q50,R626,Q54,R622,Q53,R313,Q14,R638,Q73,
R269,Q29,R631,Q67,R635,Q70,R616,Q60,R617,Q61,
Disable discharge circuit NC discharge circuit parts 0.2 38 2010-02-24 PVT_NAWE5
24 R636,Q71,R605,Q56,R404,R624,Q55,R629,Q66

Del L28 220 ohm bead NC part 1.0 12 del L28 2010-02-24 MP_NAWE5
25
23,28,
Del test Resister Del test 0 ohm Resister 1.0 R447;R4448;R586;R662;R646;R440,R372,R373,R374,R375 2010-04-28 MP_NAWE5
26 32,35

Reserve JP6 for LED of Num/Cap For NAWE7 power b/d co-lay 1.0 38 Add JP6 Location,ADD R637 100k ohm 2010-04-28 MP_NAWE5
27
ADD R430 0ohm , Del U21 reserve RST_buffer 1.0 20 ADD R430 , Del U21 2010-04-28 MP_NAWE5
28
For VGA timing for VGA timing delay +1.8VS 1.0 38 Change R489 from 84.5K to 100K 2010-04-28 MP_NAWE5
29
Add C652 & C653 33pF EMI demand 1.0 32 Add C652 & C653 33pF 2010-04-28 MP_NAWE5
30
Change C189 from 330uF to 220uF change +NB_CORE CAP 1.0 12 Change C189 from 330uF to 220uF 2010-04-28 MP_NAWE5
A 31 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2010/04/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (HW)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAWE5 LA-5753P
Date: Tuesday, May 18, 2010 Sheet 48 of 48
5 4 3 2 1