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  • Compal Confidential: G470/G570 DIS+UMA+Muxless M/B Schematics Document

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    Chek Omarov
    83 views57 pages
    This document is a schematic for a Compal Electronics motherboard model G470/G570. It contains confidential information about the motherboard design such as the Intel Sandy Bridge processor with DDR3 RAM and Cougar Point chipset. The schematic shows the layout and connections of the various components including audio, LAN, USB, SATA, and expansion card interfaces. It was created by Compal Electronics on July 22, 2010 and contains a warning that the document is proprietary and confidential information of Compal Electronics.

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    Original Title

    LA-6758P

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    This document is a schematic for a Compal Electronics motherboard model G470/G570. It contains confidential information about the motherboard design such as the Intel Sandy Bridge processor with DDR3 RAM and Cougar Point chipset. The schematic shows the layout and connections of the various components including audio, LAN, USB, SATA, and expansion card interfaces. It was created by Compal Electronics on July 22, 2010 and contains a warning that the document is proprietary and confidential information of Compal Electronics.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    83 views57 pages

    Compal Confidential: G470/G570 DIS+UMA+Muxless M/B Schematics Document

    Uploaded by

    Chek Omarov
    This document is a schematic for a Compal Electronics motherboard model G470/G570. It contains confidential information about the motherboard design such as the Intel Sandy Bridge processor with DDR3 RAM and Cougar Point chipset. The schematic shows the layout and connections of the various components including audio, LAN, USB, SATA, and expansion card interfaces. It was created by Compal Electronics on July 22, 2010 and contains a warning that the document is proprietary and confidential information of Compal Electronics.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 57

    A B C D E

    1 1

    2
    Compal Confidential 2

    G470/G570 DIS+UMA+Muxless M/B Schematics Document


    Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
    ATI Robson/PX3.0,PX4.0

    3
    2010-07-22 3

    LA-6758P
    REV:0.1

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Page
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 1 of 57
    A B C D E
    A B C D E

    Compal confidential For 14"(Page 4x) For 15"(Page 4x+1)


    File Name : G470/G570 LS6753P PWR/B LS6753P PWR/B
    LS6751P CardReader/B LS6751P CardReader/B
    Page23-30 LS6754P LED/B
    AMD LS6755P ODD/B
    Intel
    1
    Robson XT Sandy Bridge 1

    VRAM 64*16 PCI-E x16 DDR3 SO-DIMM *2


    DDR3*4 Socket-rPGA988B BANK 0, 1, 2, 3 Page12-13
    37.5mm*37.5mm
    Dual Channel Up to 8GB
    HDMI Page33 Page5-11 DDR3 1066MHz(1.5V)
    DDR3 1333MHz(1.5V)
    Connector
    100MHz
    Page32 2.7GT/s FDI *8 DMI *4
    CRT
    Connector Audio Codec 2 channel speaker
    Intel
    AZALIA Conexant
    LVDS Page31 Cougar Point CX20671
    Int. MIC
    2 Connector FCBGA 989 2

    Audio Jacks
    25mm*25mm Page39

    LAN Page35 PCI-E x1 *6 USB2.0 *14


    Athros Camera Conn.
    AR8151-B(GLAN)
    AR8152-B(10/100) SATA *6 BlueTooth Conn.
    Page42
    Page14-22
    RJ-45 Page36
    SPIROM Mini Card Slot *1
    Page34
    Connector BIOS
    LPC BUS Card Reader
    PCI Express PCI-E(WLAN)
    Page40 Reltek
    Mini Card Slot *1
    EC RTS5139
    3 USB(WiMAX) ENE KB930 SDXC/MMC/MS/xD 3

    WLAN ENE KB9012


    WiMAX Page34 USB2.0 *1(Right)
    USB2.0 *2(Left)
    Touch Pad Int. KBD

    Thermal Sensor SPI ROM


    Page41
    eSATA+USB(Left) Page42
    EMC1403 Page37
    SATA3 HDD (Port 0/Port 1 support SATA3)
    Page38

    SATA ODD Page38


    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Block Diagram
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 2 of 57
    A B C D E
    A B C D E

    SIGNAL
    Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

    Full ON HIGH HIGH HIGH HIGH ON ON ON ON

    +5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW


    +3VS
    power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
    plane +1.5VS
    1
    +VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

    +5VALW +1.5V +CPU_CORE


    S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
    +B +VGA_CORE
    +3VALW +GFX_CORE
    +1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
    State +0.75VS Vcc 3.3V +/- 5%
    +1.05VS
    Board ID PCB Revision
    Ra/Rc/Re 100K +/- 5%
    0 0.1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
    1
    0 0 0 V 0 V 0 V EVT
    2
    1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
    3
    2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
    4
    3 33K +/- 5% 0.712 V 0.819 V 0.875 V MP
    S0
    5
    O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
    6
    5 100K +/- 5% 1.453 V 1.650 V 1.759 V
    7
    6 200K +/- 5% 1.935 V 2.200 V 2.341 V
    S3 7 NC 2.500 V 3.300 V 3.300 V
    O O O X
    2 2

    S5 S4/AC
    O O X X
    USB Port Table BOM Structure Table
    S5 S4/ Battery only
    O X X X 3 External BTO Item BOM Structure
    USB 2.0 USB 1.1 Port USB Port
    S5 S4/AC & Battery
    UMA only PX@
    don't exist X X X X 0 USB/B (Right Side) Muxless PX@+VGA@
    UHCI0
    Address 1 USB Port (Left Side) Discrete Only DIS@+VGA@
    EC SM Bus1 address EC SM Bus2 address 2 USB Port (Left Side) PX3.0 only, not for BACO PX3@
    UHCI1
    3 USB Port (Left Side) BACO BACO@
    Device Device Address EHCI1
    4 COMMON HDMI HDMI@
    Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb UHCI2
    Thermal Sensor EMC1402-1 100_1100 b
    5 Camera UMA HDMI UMA_HDMI@
    6 Discrete HDMI VGA_HDMI@
    UHCI3
    7 eSATA ESATA@
    PCH SM Bus address 8 Mini Card(WLAN) Blue Tooth BT@
    UHCI4
    9 Connector ME@
    Device Address
    DDR DIMM0
    10 45 LEVEL 45@
    3
    1001 000Xb EHCI2 UHCI5 3
    DDR DIMM2 1001 010Xb
    11 Card Reader 10/100 LAN 8152@
    12 GIGA LAN GIGA@
    UHCI6
    13 Blue Tooth Cameara CMOS@

    SMBUS Control Table


    Unpop @
    Thermal
    WLAN Sensor
    SOURCE VGA BATT KE930 SODIMM WWAN PCH

    SMB_EC_CK1
    SMB_EC_DA1
    KB930 X V
    +3VALW
    X X X X X
    +3VALW
    SMB_EC_CK2
    SMB_EC_DA2
    KB930 X X X X X X V
    +3VS
    +3VALW
    SMBCLK
    SMBDATA
    PCH X X X V
    +3VS
    V
    +3VS
    X X
    +3VALW
    SML0CLK
    SML0DATA
    PCH X X X X X X X
    +3VALW
    4 4
    SML1CLK
    SML1DATA
    PCH
    +3VALW +3VS
    V X V
    +3VS
    X X V
    +3VS
    X

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 3 of 57
    A B C D E
    5 4 3 2 1

    Without BACO option :


    Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
    1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
    sequence, though a shorter ramp-up duration is preferred.
    BACO option :
    2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
    PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
    3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
    D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
    D

    4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
    VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
    DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
    5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
    DPLL_PVDD, MPV18, and SPV18
    ramp-up (or vice versa).)
    DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
    SPV10
    PCIE_VDDC 1.0V OFF ON 2A
    VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
    VDDR3 , and A2VDD 3.3V OFF ON 190mA
    BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON 70mA
    PCIE_VDDC(1.0V) BACO mode) VDDC Same as
    PCIE_VDDC
    VDDR1 1.5V OFF OFF 2.8A
    C
    VDDR1(1.5VGS) VDDC/VDDCI 1.12V OFF OFF 12.9A C

    VDDC/VDDCI(1.12V)

    VDD_CT(1.8V)
    PE_GPIO0 PE_EN BACO Switch
    iGPU dGPU
    PERSTb BIF_VDDC

    PE_GPIO1

    REFCLK PX_mode

    B +3.3VALW MOS
    +3.3VGS B

    Straps Reset 1
    +1.5V SI4800
    +1.5VGS
    Straps Valid +1.0V +1.0VGS
    Regulator
    2 3

    Global ASIC Reset


    +B Regulator
    +VGA_CORE
    +1.8V +1.8VGS
    T4+16clock
    SI4800
    5 4
    PWRGOOD

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    dGPU Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 4 of 57
    5 4 3 2 1
    5 4 3 2 1

    D D
    PEG_ICOMPI and RCOMPO signals should be
    shorted and routed
    with - max length = 500 mils - typical
    +1.05VS impedance = 43 mohms
    PEG_ICOMPO signals should be routed with -

    1
    max length = 500 mils
    R1
    24.9_0402_1%
    - typical impedance = 14.5 mohms
    JCPU1A

    2
    J22 PEG_COMP
    PEG_ICOMPI
    J21
    PEG_ICOMPO
    [16] DMI_CRX_PTX_N0 B27 H22
    DMI_RX#[0] PEG_RCOMPO
    [16] DMI_CRX_PTX_N1 B25 DMI_RX#[1]
    [16] DMI_CRX_PTX_N2 A25 PCIE_CRX_GTX_N[0..15] [23]
    DMI_RX#[2] PCIE_CRX_GTX_N15
    [16] DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
    M35 PCIE_CRX_GTX_N14
    PEG_RX#[1] PCIE_CRX_GTX_N13
    [16] DMI_CRX_PTX_P0 B28 L34
    DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
    [16] DMI_CRX_PTX_P1 B26
    DMI_RX[1] PEG_RX#[3]
    J35 PEG Static Lane Reversal - CFG2 is for the 16x

    DMI
    A24 J32 PCIE_CRX_GTX_N11
    [16] DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
    B23 H34 PCIE_CRX_GTX_N10
    [16] DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
    H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
    PEG_RX#[6] PCIE_CRX_GTX_N8
    [16] DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 CFG2 socket pin map definition
    E22 G30 PCIE_CRX_GTX_N7
    [16] DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
    [16] DMI_CTX_PRX_N2 F21 F35
    DMI_TX#[2] PEG_RX#[9] PCIE_CRX_GTX_N5
    D21 E34 0:Lane Reversed
    [16]

    [16]
    DMI_CTX_PRX_N3

    DMI_CTX_PRX_P0 G22
    DMI_TX#[3]

    DMI_TX[0]
    PEG_RX#[10]
    PEG_RX#[11]
    PEG_RX#[12]
    E32
    D33
    PCIE_CRX_GTX_N4
    PCIE_CRX_GTX_N3 *
    D22 D31 PCIE_CRX_GTX_N2
    C [16] DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N1 C

    PCI EXPRESS* - GRAPHICS


    [16] DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
    C21 C32 PCIE_CRX_GTX_N0
    [16] DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
    PCIE_CRX_GTX_P[0..15] [23]
    J33 PCIE_CRX_GTX_P15
    PEG_RX[0] PCIE_CRX_GTX_P14
    PEG_RX[1] L35
    K34 PCIE_CRX_GTX_P13
    PEG_RX[2] PCIE_CRX_GTX_P12
    [16] FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
    H19 H32 PCIE_CRX_GTX_P11
    [16] FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PCIE_CRX_GTX_P10
    [16] FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
    F18 G31 PCIE_CRX_GTX_P9

    Intel(R) FDI
    [16] FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P8
    DISCRETE ONLY [16] FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33
    C20 F30 PCIE_CRX_GTX_P7
    [16] FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
    1K_0402_5% 2 DIS@ 1 R2 FDI_FSYNC0 D18 E35 PCIE_CRX_GTX_P6
    [16] FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PCIE_CRX_GTX_P5
    [16] FDI_CTX_PRX_N7 E17 E33
    1K_0402_5% 2 DIS@ FDI_FSYNC1 FDI1_TX#[3] PEG_RX[10] PCIE_CRX_GTX_P4
    1 R3 F32
    PEG_RX[11] PCIE_CRX_GTX_P3
    D34
    1K_0402_5% 2 DIS@ FDI_INT PEG_RX[12] PCIE_CRX_GTX_P2
    1 R4 [16] FDI_CTX_PRX_P0 A22 E31
    FDI0_TX[0] PEG_RX[13] PCIE_CRX_GTX_P1
    [16] FDI_CTX_PRX_P1 G19 C33
    1K_0402_5% 2 DIS@ FDI_LSYNC0 FDI0_TX[1] PEG_RX[14] PCIE_CRX_GTX_P0
    1 R5 [16] FDI_CTX_PRX_P2 E20 B32 R01
    FDI0_TX[2] PEG_RX[15]
    [16] FDI_CTX_PRX_P3 G18 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] [23]
    1K_0402_5% 2 DIS@ 1 R6 FDI_LSYNC1 B20 M29 PCIE_CTX_GRX_C_N15 C1 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N15
    [16] FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
    C19 M32 PCIE_CTX_GRX_C_N14 C2 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N14
    [16] FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_N13
    D19 M31 C3 VGA@1 2 0.1U_0402_10V6K
    [16] FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
    F17 L32 PCIE_CTX_GRX_C_N12 C4 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N12
    [16] FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_N11
    L29 C5 VGA@
    VGA@1 2 0.1U_0402_10V6K
    FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_N10
    [16] FDI_FSYNC0 J18 K31 2
    +1.05VS FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PCIE_CTX_GRX_C_N9 C7 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_N9
    [16] FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 2
    J30 PCIE_CTX_GRX_C_N8 C8 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N8
    FDI_INT PEG_TX#[7] PCIE_CTX_GRX_C_N7 C9 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_N7
    [16] FDI_INT H20 J28 2
    FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N6 C10 VGA@
    VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_N6
    H29 2
    PEG_TX#[9]
    1

    FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5


    [16] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
    R7 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N4 C12 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N4
    B [16] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] B
    24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N3
    PEG_TX#[12] PCIE_CTX_GRX_C_N2 C14 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_N2
    PEG_TX#[13] D28 2
    F26 PCIE_CTX_GRX_C_N1 C15 VGA@
    VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N1
    2

    PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_N0


    PEG_TX#[15] E25 2
    EDP_COMP A18
    eDP_COMPIO PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P[0..15] [23]
    eDP_COMPIO and ICOMPO signals A17
    eDP_ICOMPO PEG_TX[0]
    M28 C17 VGA@1 2 0.1U_0402_10V6K
    eDP_HPD B16 M33 PCIE_CTX_GRX_C_P14 C18 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P14
    should be shorted near balls eDP_HPD PEG_TX[1]
    M30 PCIE_CTX_GRX_C_P13 C19 VGA@
    VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P13
    PEG_TX[2]
    and routed with typical PEG_TX[3]
    L31 PCIE_CTX_GRX_C_P12 C20 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P12
    C15 L28 PCIE_CTX_GRX_C_P11 C21 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P11
    impedance <25 mohms D15
    eDP_AUX PEG_TX[4]
    K30 PCIE_CTX_GRX_C_P10 C22 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P10
    eDP_AUX# PEG_TX[5]
    eDP

    K27 PCIE_CTX_GRX_C_P9 C23 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P9


    PEG_TX[6] PCIE_CTX_GRX_C_P8 C24 VGA@
    VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P8
    PEG_TX[7] J29 2
    C17 J27 PCIE_CTX_GRX_C_P7 C25 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P7
    eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P6 C26 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P6
    F16 eDP_TX[1] PEG_TX[9] H28 2
    C16 G28 PCIE_CTX_GRX_C_P5 C27 VGA@1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P5
    eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P4 C28 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P4
    G15 E28 2
    eDP_TX[3] PEG_TX[11] PCIE_CTX_GRX_C_P3 C29 VGA@
    VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P3
    F28 2
    PEG_TX[12] PCIE_CTX_GRX_C_P2 C30 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P2
    C18 D27 2
    eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_C_P1 C31 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P1
    E16 E26 2
    eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_C_P0 C32 VGA@1 0.1U_0402_10V6K PCIE_CTX_GRX_P0
    D16 D25 2
    eDP_TX#[2] PEG_TX[15]
    F15 eDP_TX#[3]

    Sandy Bridge_rPGA_Rev1p0
    ME@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(1/7) DMI,FDI,PEG
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 5 of 57
    5 4 3 2 1
    5 4 3 2 1

    JCPU1B
    D D
    R10 0_0402_5% DG1.0
    A28 CLK_CPU_DMI_R 1 2
    BCLK CLK_CPU_DMI [15]

    MISC

    CLOCKS
    C26 A27 CLK_CPU_DMII#_R R11 1 2
    [18] H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# [15]
    0_0402_5%
    AN34
    SKTOCC#
    DPLL_REF_CLK A16 R12 2 1 1K_0402_5% DG1.0
    A15 R13 2 1 1K_0402_5% +1.05VS
    DPLL_REF_CLK#
    +1.05VS
    closs to EC 250~750mils H_CATERR# AL33
    CATERR#
    R9 1 R14

    THERMAL
    62_0402_5% 0_0402_5%
    1 2 H_PECI_ISO AN33 R8 H_DRAMRST#
    [19,40] H_PECI PECI SM_DRAMRST# H_DRAMRST# [7]
    2

    DDR3
    MISC
    R15
    56_0402_5%
    [40] H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R16 2 1 140_0402_1%
    PROCHOT# SM_RCOMP[0] SM_RCOMP1
    SM_RCOMP[1]
    A5 R17 2 1 25.5_0402_1% DDR3 Compensation Signals
    R19 A4 SM_RCOMP2 R18 2 1 200_0402_1%
    0_0402_5% SM_RCOMP[2]
    1 2 H_THEMTRIP#_R AN32
    [19] H_THRMTRIP# THERMTRIP#

    AP29 XDP_PRDY# +1.05VS


    PRDY# XDP_PREQ#
    PREQ# AP27

    R22 AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5%


    TCK

    PWR MANAGEMENT
    C XDP_TMS XDP_TDI C
    0_0402_5% AR27 R21 2 1 51_0402_5% PU/PD for JTAG signals

    JTAG & BPM


    H_PM_SYNC_R TMS XDP_TRST# XDP_TDO R23
    [16] H_PM_SYNC 1 2 AM34 AP30 2 1 51_0402_5%
    PM_SYNC TRST#
    AR28 XDP_TDI XDP_TCK R24 2 1 51_0402_5%
    R26 TDI XDP_TDO XDP_TRST# R25
    TDO AP26 2 1 51_0402_5%
    0_0402_5%1 2 H_CPUPWRGD_R AP33
    [19] H_CPUPWRGD UNCOREPWRGOOD
    2

    R29
    DBR# AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS
    R27 1 2 PM_DRAM_PWRGD_R V8
    130_0402_5% SM_DRAMPWROK
    10K_0402_5%
    AT28 XDP_BPM#0
    BPM#[0] XDP_BPM#1
    AR29
    1

    BPM#[1] XDP_BPM#2
    AR30
    BUF_CPU_RST# BPM#[2] XDP_BPM#3
    AR33 AT30
    RESET# BPM#[3] XDP_BPM#4
    AP32
    BPM#[4] XDP_BPM#5
    AR31
    BPM#[5] XDP_BPM#6
    AT31
    BPM#[6] XDP_BPM#7
    AR32
    BPM#[7]

    Sandy Bridge_rPGA_Rev1p0
    +3VALW ME@

    1 Buffered reset to CPU


    C33
    0.1U_0402_16V4Z
    7/28 Modify follow ORB +1.5V_CPU_VDDQ
    2 +3VS
    B B
    1

    R30
    U1 200_0402_5% +1.05VS
    1
    C34
    5

    R161 0.1U_0402_16V4Z
    R01
    2

    100K_0402_5% 1
    P

    B PM_SYS_PWRGD_BUF R32 2
    +3VS 1 2 4
    O 75_0402_5%
    [16] PM_DRAM_PWRGD 2
    A
    G

    5
    74AHC1G09GW_TSSOP5 R34 U2
    3

    @ 43_0402_1% 1 3V

    P
    R33 BUF_CPU_RST# BUFO_CPU_RST# 4 NC
    1 2 Y
    39_0402_5% 2 PLT_RST#
    A PLT_RST# [18]

    G
    1

    SN74LVC1G07DCKR_SC70-5
    1 2

    3
    D @ R35 @
    SUSP 2 Q1 0_0402_5%
    [10,44,51] SUSP
    G 2N7002_SOT23
    2

    S
    3

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(2/7) PM,XDP,CLK
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 6 of 57
    5 4 3 2 1
    5 4 3 2 1

    JCPU1C JCPU1D

    [12] DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 [12] [13] DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 [13]
    AA6 M_CLK_DDR#0 [12] AD2 M_CLK_DDR#2 [13]
    DDR_A_D0 SA_CLK#[0] DDR_B_D0 SB_CLK#[0]
    C5 SA_DQ[0] SA_CKE[0] V9 DDR_CKE0_DIMMA [12] C9 SB_DQ[0] SB_CKE[0] R9 DDR_CKE2_DIMMB [13]
    DDR_A_D1 D5 DDR_B_D1 A7
    DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
    D3 SA_DQ[2] D10 SB_DQ[2]
    DDR_A_D3 D2 DDR_B_D3 C8
    DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
    D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 [12] A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 [13]
    D DDR_A_D5 DDR_B_D5 D
    C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 [12] A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 [13]
    DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
    DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA [12] DDR_B_D7 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB [13]
    C3 SA_DQ[7] D8 SB_DQ[7]
    DDR_A_D8 F10 DDR_B_D8 G4
    DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
    F8 F4
    DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
    G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
    DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
    DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
    F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
    DDR_A_D13 F7 DDR_B_D13 F5
    DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
    G8 F2
    DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
    G7 SA_DQ[15] G2 SB_DQ[15]
    DDR_A_D16 K4 AB3 DDR_B_D16 J7 AA1
    DDR_A_D17 SA_DQ[16] RSVD_TP[4] DDR_B_D17 SB_DQ[16] RSVD_TP[14]
    K5 SA_DQ[17] RSVD_TP[5] AA3 J8 SB_DQ[17] RSVD_TP[15] AB1
    DDR_A_D18 K1 W10 DDR_B_D18 K10 T10
    DDR_A_D19 SA_DQ[18] RSVD_TP[6] DDR_B_D19 SB_DQ[18] RSVD_TP[16]
    J1 K9
    DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
    J5 J9
    DDR_A_D21 SA_DQ[20] DDR_B_D21 SB_DQ[20]
    J4 SA_DQ[21] J10 SB_DQ[21]
    DDR_A_D22 J2 AK3 DDR_B_D22 K8 AD3
    SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# [12] SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# [13]
    DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
    DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# [12] DDR_B_D24 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# [13]
    M8 AG1 M5 AD6
    DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
    N10 AH1 N4 AE6
    DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D26 SB_DQ[25] RSVD_TP[18]
    N8 N2
    DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
    N7 SA_DQ[27] N1 SB_DQ[27]
    DDR_A_D28 M10 DDR_B_D28 M4
    DDR_A_D29 SA_DQ[28] DDR_B_D29 SB_DQ[28]
    M9 AH3 M_ODT0 [12] N5 AE4 M_ODT2 [13]
    SA_DQ[29] SA_ODT[0] SB_DQ[29] SB_ODT[0]

    DDR SYSTEM MEMORY B


    DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4

    DDR SYSTEM MEMORY A


    DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 [12] DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 [13]
    M7 AG2 M1 AD5
    DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
    AG6 AH2 AM5 AE5
    DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D33 SB_DQ[32] RSVD_TP[20]
    AG5 SA_DQ[33] AM6 SB_DQ[33]
    DDR_A_D34 AK6 DDR_B_D34 AR3
    DDR_A_D35 SA_DQ[34] DDR_B_D35 SB_DQ[34]
    AK5 AP3
    DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
    AH5 DDR_A_DQS#[0..7] [12] AN3 DDR_B_DQS#[0..7] [13]
    C DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 C
    AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
    DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
    DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
    AJ6 J3 AP2 K6
    DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
    AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
    DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
    DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
    AJ9 AM8 AT5 AP9
    DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
    AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
    DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
    DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
    AH9 SA_DQ[45] AN8 SB_DQ[45]
    DDR_A_D46 AL9 DDR_B_D46 AR6
    DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
    AL8 SA_DQ[47] AR5 SB_DQ[47]
    DDR_A_D48 AP11 DDR_B_D48 AR9
    SA_DQ[48] DDR_A_DQS[0..7] [12] SB_DQ[48] DDR_B_DQS[0..7] [13]
    DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
    DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
    AL12 F6 AT8 G3
    DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
    AM12 K3 AT9 J6
    DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
    AM11 N6 AH11 M3
    DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
    AL11 AL5 AR8 AN6
    DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
    AP12 AM9 AJ12 AP8
    DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
    AN12 AR11 AH12 AK11
    DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
    AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
    DDR_A_D57 AH14 DDR_B_D57 AN14
    DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
    AL15 AR14
    DDR_A_D59 SA_DQ[58] DDR_B_D59 SB_DQ[58]
    AK15 AT14
    DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
    AL14 DDR_A_MA[0..15] [12] AT12 DDR_B_MA[0..15] [13]
    DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
    AK14 AD10 AN15 AA8
    DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
    AJ15 W1 AR15 T7
    DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
    AH15 SA_DQ[63] SA_MA[2] W2 AT15 SB_DQ[63] SB_MA[2] R7
    W7 DDR_A_MA3 T6 DDR_B_MA3
    SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
    V3 T2
    SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
    V2 T4
    SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
    W3 T3
    SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
    [12] DDR_A_BS0 AE10 W6 [13] DDR_B_BS0 AA9 R2
    B SA_BS[0] SA_MA[7] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA8 B
    [12] DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 [13] DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
    V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
    [12] DDR_A_BS2 SA_BS[2] SA_MA[9] DDR_A_MA10 [13] DDR_B_BS2 SB_BS[2] SB_MA[9] DDR_B_MA10
    AD8 AB7
    SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
    SA_MA[11] V4 SB_MA[11] R1
    W4 DDR_A_MA12 T1 DDR_B_MA12
    SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
    [12] DDR_A_CAS# AE8 AF8 [13] DDR_B_CAS# AA10 AB10
    SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
    [12] DDR_A_RAS# AD9 V5 [13] DDR_B_RAS# AB8 R5
    SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
    [12] DDR_A_WE# AF9 V7 [13] DDR_B_WE# AB9 R4
    SA_WE# SA_MA[15] SB_WE# SB_MA[15]

    Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0


    ME@ ME@
    +1.5V

    @ R36
    1

    0_0402_5%
    1 2 R37
    1K_0402_5%

    R38
    2

    1K_0402_5%
    S

    [6] H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# [12,13]


    2

    Q2
    R39 BSS138_NL_SOT23-3
    G
    2

    4.99K_0402_1%
    1

    A R40 A
    0_0402_5%
    1 2 DRAMRST_CNTRL
    [15] DRAMRST_CNTRL_PCH

    1
    C35
    Eiffel used 0.01u Security Classification Compal Secret Data Compal Electronics, Inc.
    Module design used 0.047u Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
    0.047U_0402_16V4Z
    2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(3/7) DDRIII
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 7 of 57

    5 4 3 2 1
    5 4 3 2 1

    CFG Straps for Processor

    CFG2

    1
    R41
    1K_0402_1%

    2
    D D

    JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x

    RSVD28
    L7 1: Normal Operation; Lane # definition matches
    RSVD29 AG7 CFG2 socket pin map definition
    AK28 AE7
    CFG[0] RSVD30
    AK29 CFG[1] RSVD31 AK2
    CFG2 AL26 W8 0:Lane Reversed
    CFG4
    CFG5
    AL27
    AK26
    CFG[2]
    CFG[3]
    CFG[4]
    RSVD32
    * CFG4
    AL29 CFG[5] RSVD33 AT26
    CFG6 AL30 AM33
    CFG[6] RSVD34

    1
    CFG7 AM31 AJ27
    CFG[7] RSVD35
    AM32
    CFG[8] @ R42
    AM30
    CFG[9] 1K_0402_1%
    AM28
    CFG[10]
    AM26

    2
    CFG[11]
    AN28 CFG[12]
    AN31 T8
    CFG[13] RSVD37
    AN26 CFG[14] RSVD38 J16
    AM27 H16
    CFG[15] RSVD39
    AK31 G16
    CFG[16] RSVD40
    AN29 CFG[17]
    Display Port Presence Strap

    C C
    AR35 1 : Disabled; No Physical Display Port
    T9
    T10
    PAD
    PAD
    AJ31
    AH31
    VAXG_VAL_SENSE
    VSSAXG_VAL_SENSE
    RSVD41
    RSVD42
    RSVD43
    AT34
    AT33
    CFG4 * attached to Embedded Display Port
    T11 PAD AJ33 AP35
    VCC_VAL_SENSE RSVD44
    T12 PAD AH33 VSS_VAL_SENSE RSVD45 AR34 0 : Enabled; An external Display Port device is
    connected to the Embedded Display Port
    AJ26
    RSVD5

    RESERVED
    B34 CFG6
    RSVD46
    B4 A33
    RSVD6 RSVD47 CFG5
    R01 D1 RSVD7 RSVD48 A34
    B35
    RSVD49

    1
    C35
    RSVD50
    1

    @ R43 @ R44
    R64 R353 F25 1K_0402_1% 1K_0402_1%
    1K_0402_1% 1K_0402_1% RSVD8
    F24
    RSVD9
    F23

    2
    RSVD10
    D24 AJ32
    2

    RSVD11 RSVD51
    G25 AK32
    RSVD12 RSVD52
    G24
    RSVD13
    E23
    RSVD14
    D23
    RSVD15 PAD T13
    C30 AH27
    RSVD16 VCC_DIE_SENSE
    A31
    RSVD17
    B30 RSVD18
    B29
    RSVD19 PCIE Port Bifurcation Straps
    D30 AN35
    RSVD20 RSVD54
    B31 AM35
    RSVD21 RSVD55
    A30 11: (Default) x16 - Device 1 functions 1 and 2 disabled
    B
    C29
    RSVD22
    RSVD23
    CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

    J20
    disabled
    RSVD24
    B18 RSVD25 RSVD56 AT2 01: Reserved - (Device 1 function 1 disabled ; function
    A19 AT1 2 enabled)
    VCCIO_SEL RSVD57
    AR1
    RSVD58
    00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
    J15
    RSVD27

    KEY B1
    CFG7

    1
    @R45
    @ R45
    1K_0402_1%

    Sandy Bridge_rPGA_Rev1p0

    2
    ME@

    PEG DEFER TRAINING

    1: (Default) PEG Train immediately following xxRESETB


    CFG7 de assertion

    A
    0: PEG Wait for BIOS for training A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(4/7) RSVD,CFG
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 8 of 57
    5 4 3 2 1
    5 4 3 2 1

    JCPU1F POWER
    +CPU_CORE Cap quantity follow HR_PDDG_Rev07
    (6/16 change 10uF_0603_6.3V)*5 22uF*7 NO-STUFF
    QC=94A +1.05VS
    18A
    DC=53A AG35
    OSCAN(22uF_0805_6.3V)*13
    VCC1 +1.05VS
    1 1 1 1 1 AG34 AH13
    VCC2 VCCIO1

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M
    AG33 VCC3 VCCIO2 AH10 1 1 1 1 1 1 1 1 1 1

    C36

    C37

    C38

    C39

    C40

    22U_0805_6.3V6M
    C41

    22U_0805_6.3V6M
    C42

    22U_0805_6.3V6M
    C43

    22U_0805_6.3V6M
    C44

    22U_0805_6.3V6M
    C54

    22U_0805_6.3V6M
    C45

    22U_0805_6.3V6M
    C46

    22U_0805_6.3V6M
    C55

    22U_0805_6.3V6M
    C56

    22U_0805_6.3V6M
    C47
    AG32 AG10
    VCC4 VCCIO3
    AG31 VCC5 VCCIO4 AC10
    D 2 2 2 2 2 AG30 Y10 D
    VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
    AG29 VCC7 VCCIO6 U10
    AG28 VCC8 VCCIO7 P10
    AG27 L10
    VCC9 VCCIO8
    AG26 J14
    VCC10 VCCIO9
    AF35 VCC11 VCCIO10 J13
    1 1 1 1 1 1 AF34 J12
    10U_0603_6.3V6M VCC12 VCCIO11
    C48

    10U_0603_6.3V6M
    C49

    10U_0603_6.3V6M
    C50

    10U_0603_6.3V6M
    C51

    10U_0603_6.3V6M
    C52

    10U_0603_6.3V6M
    C53
    AF33 VCC13 VCCIO12 J11 1 1 1 1 1 1 1 1 1

    22U_0805_6.3V6M
    C57

    22U_0805_6.3V6M
    C58

    22U_0805_6.3V6M
    C59

    22U_0805_6.3V6M
    C60

    22U_0805_6.3V6M
    C61

    22U_0805_6.3V6M
    C62

    22U_0805_6.3V6M
    C63

    22U_0805_6.3V6M
    C64

    22U_0805_6.3V6M
    C65
    AF32 VCC14 VCCIO13 H14
    @ AF31 H12 @ @ @ @ @ @ @
    2 2 2 2 2 2 VCC15 VCCIO14
    AF30 VCC16 VCCIO15 H11
    AF29 G14 2 2 2 2 2 2 2 2 2
    VCC17 VCCIO16
    AF28 VCC18 VCCIO17 G13

    PEG AND DDR


    AF27 G12
    VCC19 VCCIO18
    AF26 F14
    VCC20 VCCIO19
    AD35 F13
    VCC21 VCCIO20
    +CPU_CORE (22uF_0805_6.3V)*16 AD34
    AD33
    VCC22 VCCIO21 F12
    F11
    VCC23 VCCIO22
    AD32 VCC24 VCCIO23 E14

    330U_D2_2.5VY_R9M
    AD31 E12 1 1 1
    VCC25 VCCIO24

    C73
    AD30
    VCC26 + C69 + C72 +
    1 1 1 1 1 AD29 E11
    VCC27 VCCIO25
    22U_0805_6.3V6M
    C66

    22U_0805_6.3V6M
    C67

    22U_0805_6.3V6M
    C68

    22U_0805_6.3V6M
    C70

    22U_0805_6.3V6M
    C71
    AD28 D14 220U_6.3V_M 220U_6.3V_M @
    VCC28 VCCIO26
    AD27 VCC29 VCCIO27 D13
    AD26 D12 2 2 2
    2 2 2 2 2 VCC30 VCCIO28
    AC35
    AC34
    VCC31 VCCIO29 D11
    C14
    OSCAN
    VCC32 VCCIO30
    AC33
    AC32
    VCC33 VCCIO31
    C13
    C12
    (220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00)
    VCC34 VCCIO32
    AC31 VCC35 VCCIO33 C11
    AC30 B14
    VCC36 VCCIO34
    1 1 1 1 1 AC29 B12
    VCC37 VCCIO35
    22U_0805_6.3V6M
    C74

    22U_0805_6.3V6M
    C75

    22U_0805_6.3V6M
    C76

    22U_0805_6.3V6M
    C77

    22U_0805_6.3V6M
    C78
    C C
    AC28 VCC38 VCCIO36 A14
    AC27 A13
    VCC39 VCCIO37
    AC26 A12
    2 2 2 2 2 VCC40 VCCIO38
    AA35 VCC41 VCCIO39 A11
    AA34 VCC42
    AA33 J23
    VCC43 VCCIO40
    AA32 VCC44
    AA31
    VCC45
    AA30 VCC46
    1 1 1 1 1 AA29
    VCC47
    22U_0805_6.3V6M
    C79

    22U_0805_6.3V6M
    C80

    22U_0805_6.3V6M
    C81

    22U_0805_6.3V6M
    C82

    22U_0805_6.3V6M
    C83

    AA28 VCC48
    AA27
    VCC49
    AA26 VCC50
    2 2 2 2 2 +1.05VS

    CORE SUPPLY
    Y35
    VCC51
    Y34
    VCC52
    Y33
    VCC53
    Y32
    VCC54

    1
    Y31
    VCC55 R46
    Y30
    VCC56
    1 1 1 1 Y29 VCC57 75_0402_5%
    22U_0805_6.3V6M
    C84

    22U_0805_6.3V6M
    C85

    22U_0805_6.3V6M
    C86

    22U_0805_6.3V6M
    C87

    Y28
    VCC58
    @ @ @ Y27 VR_SVID_CLK series-resistors close to VR

    2
    VCC59
    Y26
    2 2 2 2 VCC60
    V35
    VCC61

    SVID
    V34 AJ29 H_CPU_SVIDALRT# R47 1 2 43_0402_5%
    VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# [53]
    V33 AJ30 R48 1 2 0_0402_5%
    VCC63 VIDSCLK VR_SVID_CLK [53]
    V32 AJ28 H_CPU_SVIDDAT R49 1 2 0_0402_5%
    VCC64 VIDSOUT VR_SVID_DAT [53]
    V31
    +CPU_CORE VCC65
    V30
    VCC66 R50
    V29 2 1 130_0402_5% +1.05VS
    VCC67
    V28
    VCC68
    V27
    B VCC69 B
    V26 VCC70
    330U_X_2VM_R6M

    330U_X_2VM_R6M

    330U_X_2VM_R6M

    330U_X_2VM_R6M

    1 1 1 1 U35 VCC71
    U34
    VCC72
    C88

    C89

    C90

    C91

    + + + + U33 VCC73
    (330uF)*4 U32
    U31
    VCC74
    2 2 2 2 VCC75
    U30
    VCC76
    U29
    U28
    VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
    VCC78
    U27 VCC79
    U26 VCC80
    R35 +CPU_CORE
    VCC81
    R34 VCC82
    R33
    VCC83

    1
    R32 VCC84
    R31 R51
    VCC85
    R30 100_0402_1%
    VCC86
    R29
    VCC87
    SENSE LINES

    R28

    2
    VCC88
    R27 AJ35 VCCSENSE_R R52 1 2 0_0402_5%
    VCCSENSE [53]
    VCC89 VCC_SENSE
    R26 AJ34 VSSSENSE_R R53 1 2 0_0402_5%
    VSSSENSE [53]
    VCC90 VSS_SENSE
    P35 VCC91
    P34 VCCIO_SENSE [51]
    VCC92

    1
    P33 VCC93
    P32 B10 R54
    VCC94 VCCIO_SENSE VSSIO_SENSE
    P31 A10 1 2 100_0402_1%
    VCC95 VSSIO_SENSE R74 @
    P30 VCC96 0_0402_5%
    P29 R01

    2
    VCC97
    P28
    VCC98
    P27
    VCC99
    P26
    VCC100
    A
    8/6 Modify, need follow A
    diffential routing
    VSS_SENCE 100ohm +-1% pull-down to GND near processor

    Sandy Bridge_rPGA_Rev1p0
    ME@ Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(5/7) PWR,BYPASS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 9 of 57
    5 4 3 2 1
    5 4 3 2 1

    +1.5V @ J1 +1.5V_CPU_VDDQ
    1 2
    6/24 R56 change to 15K +1.5V
    PAD-OPEN 4x4m 1

    1
    1 2 R55 @ C92
    [6,44,51] SUSP 0_0402_5% R668 220_0402_5% 0.1U_0402_10V6K
    2 R01
    @

    12
    D

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K
    +VSB

    C95

    C96

    C129

    C396
    +3VALW U3 Q3 2 RUN_ON_CPU1.5VS3# 1 1 1 1
    8 1 2N7002_SOT23 G
    D D S @ @ D
    7 2 S

    3
    D S

    1
    6 D S 3

    1
    R56 5 4 +1.5V_CPU_VDDQ 2 2 2 2
    R667 D G
    100K_0402_5% 15K_0402_1% SI4800BDY-T1-E3_SO8

    2
    2
    RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3

    1
    1

    1
    D D
    1 2 2 Q7 2 Q4 R57 C97
    [40] CPU1.5V_S3_GATE
    0_0402_5% R58 G 2N7002_SOT23 G 2N7002_SOT23 330K_0402_5% 0.1U_0603_25V7K
    S S @ 2

    2
    1 @ 2
    [26,40,44,49,51,52] SUSP#
    0_0402_5% R59

    +VGFX_CORE JCPU1G
    POWER

    SENSE
    LINES
    AT24 AK35 VCC_AXG_SENSE [53]
    VAXG1 VAXG_SENSE
    AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE [53]
    1

    1 1 1 1 1 1 1 1 1 1 AT21
    VAXG3
    22U_0805_6.3V6M
    C98

    22U_0805_6.3V6M
    C99

    22U_0805_6.3V6M
    C100

    22U_0805_6.3V6M
    C101

    22U_0805_6.3V6M
    C102

    22U_0805_6.3V6M
    C103

    22U_0805_6.3V6M
    C104

    22U_0805_6.3V6M
    C105

    22U_0805_6.3V6M
    C106

    22U_0805_6.3V6M
    C107
    AT20
    0_0402_5% VAXG4 +1.5V_CPU_VDDQ
    AT18 VAXG5
    R60 AT17 R61
    DIS@ 2 2 2 2 2 2 2 2 2 2 VAXG6 0_0402_5%
    AR24
    2

    VAXG7

    1
    AR23 2 1
    C PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ VAXG8 R62 C
    AR21 VAXG9
    AR20 100_0402_1%
    VAXG10

    VREF
    AR18
    VAXG11
    AR17

    2
    VAXG12 +V_SM_VREF_CNT +V_SM_VREF
    AP24 VAXG13 SM_VREF AL1 2 3
    AP23
    VAXG14

    1
    AP21 1 100K_0402_5% @ Q5
    @Q5
    VAXG15 C114 R666 AP2302GN-HF_SOT23-3 R63
    1 1 1 1 1 1 AP20
    VAXG16
    22U_0805_6.3V6M
    C108

    22U_0805_6.3V6M
    C109

    22U_0805_6.3V6M
    C110

    22U_0805_6.3V6M
    C111

    22U_0805_6.3V6M
    C112

    22U_0805_6.3V6M
    C113 AP18 0.1U_0402_16V4Z @ 100_0402_1%
    VAXG17 1
    AP17
    VAXG18 2 RUN_ON_CPU1.5VS3
    AN24

    2
    2 2 2 @ 2 @ 2 @ 2 @ VAXG19
    AN23
    VAXG20
    AN21 VAXG21
    PX@ PX@ AN20
    VAXG22

    DDR3 -1.5V RAILS


    AN18
    VAXG23 +1.5V_CPU_VDDQ
    AN17
    VAXG24

    GRAPHICS
    AM24 AF7
    VAXG25 VDDQ1
    AM23 AF4
    VAXG26 VDDQ2
    AM21 AF1 1
    VAXG27 VDDQ3
    330U_D2_2.5VY_R9M

    330U_D2_2.5VY_R9M

    1 1 AM20 VAXG28 VDDQ4 AC7 1 1 1 1 1 1


    C115

    C116

    10U_0603_6.3V6M
    C117

    10U_0603_6.3V6M
    C118

    10U_0603_6.3V6M
    C119

    10U_0603_6.3V6M
    C120

    10U_0603_6.3V6M
    C121

    10U_0603_6.3V6M
    C122
    AM18 AC4 + C123
    + + @ VAXG29 VDDQ5 330U_2.5V_M
    AM17 AC1
    PX@ VAXG30 VDDQ6
    AL24 Y7
    VAXG31 VDDQ7 2 2 2 2 2 2 2
    AL23 Y4
    2 2 VAXG32 VDDQ8
    AL21 Y1
    VAXG33 VDDQ9
    AL20 U7
    VAXG34 VDDQ10
    AL18 VAXG35 VDDQ11 U4
    AL17 U1
    VAXG36 VDDQ12
    AK24 P7
    VAXG37 VDDQ13
    AK23 P4
    VAXG38 VDDQ14
    AK21 P1
    VAXG39 VDDQ15
    AK20
    B VAXG40 B
    AK18 VAXG41
    AK17 VAXG42
    AJ24
    VAXG43
    AJ23 VAXG44
    AJ21
    VAXG45
    AJ20
    VAXG46
    AJ18
    VAXG47
    AJ17
    VAXG48 +VCCSA
    AH24

    SA RAIL
    VAXG49
    AH23 VAXG50
    AH21 M27 +VCCSA
    VAXG51 VCCSA1
    AH20 M26
    VAXG52 VCCSA2
    AH18 VAXG53 VCCSA3 L26
    AH17 J26 1 1 1 1 R65 1 2 0_0402_5% VCCSA_SENSE
    VAXG54 VCCSA4 VCCSA_SENSE [50]

    10U_0805_6.3V6M
    C124

    10U_0805_6.3V6M
    C125

    10U_0805_6.3V6M
    C126

    10U_0805_6.3V6M
    C127
    VCCSA5 J25 1
    Sandy Bridge_rPGA_Rev1p0 J24 @
    ME@ VCCSA6 + C128
    H26
    VCCSA7 2 2 2 2 330U_2.5V_M
    H25
    VCCSA8
    2 R66
    1.8V RAIL

    1 2 0_0402_5% VSSSA_SENSE [50]


    +1.8VS R67
    0_0805_5%
    1 2 +1.8VS_VCCPLL B6 H23 VCCSA_SENSE
    VCCPLL1 VCCSA_SENSE
    MISC

    A6
    VCCPLL2
    10U_0805_6.3V6M
    C130

    1U_0402_6.3V6K
    C131

    1U_0402_6.3V6K
    C132

    1 1 1 1 A2 @
    VCCPLL3
    22U_0805_6.3V6M
    C154

    22U_0805_6.3V6M
    C345

    1 R68 1 2 0_0402_5%
    C22 H_FC_C22
    FC_C22
    C24
    2 @ 2 @ 2 2 VCCSA_VID1
    2 R69 1 2 10K_0402_5%
    A A

    VCCSA_SEL [50]

    6/9 change 330U to 22U X2


    Security Classification Compal Secret Data
    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(6/7) PWR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 10 of 57
    5 4 3 2 1
    5 4 3 2 1

    JCPU1H JCPU1I
    D D
    AT35 VSS1 VSS81 AJ22
    AT32 VSS2 VSS82 AJ19
    AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
    AT27 AJ13 T34 F19
    VSS4 VSS84 VSS162 VSS235
    AT25 AJ10 T33 E30
    VSS5 VSS85 VSS163 VSS236
    AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
    AT19 AJ4 T31 E24
    VSS7 VSS87 VSS165 VSS238
    AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
    AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
    AT10 AJ1 T28 E15
    VSS10 VSS90 VSS168 VSS241
    AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
    AT4 AH34 T26 E10
    VSS12 VSS92 VSS170 VSS243
    AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
    AR25 AH30 P8 E8
    VSS14 VSS94 VSS172 VSS245
    AR22 AH29 P6 E7
    VSS15 VSS95 VSS173 VSS246
    AR19 AH28 P5 E6
    VSS16 VSS96 VSS174 VSS247
    AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5
    AR13 AH25 P2 E4
    VSS18 VSS98 VSS176 VSS249
    AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3
    AR7 AH19 N34 E2
    VSS20 VSS100 VSS178 VSS251
    AR4 AH16 N33 E1
    VSS21 VSS101 VSS179 VSS252
    AR2 AH7 N32 D35
    VSS22 VSS102 VSS180 VSS253
    AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
    AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
    AP28 AG8 N29 D26
    VSS25 VSS105 VSS183 VSS256
    AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
    AP22 AF6 N27 D17
    VSS27 VSS107 VSS185 VSS258
    AP19 AF5 N26 C34
    VSS28 VSS108 VSS186 VSS259
    AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
    AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
    AP10 AE35 L30 C27
    VSS31 VSS111 VSS189 VSS262
    AP7 AE34 L27 C25
    C VSS32 VSS112 VSS190 VSS263 C
    AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
    AP1 AE32 L8 C10
    VSS34 VSS114 VSS192 VSS265
    AN30 AE31 L6 C1
    VSS35 VSS115 VSS193 VSS266
    AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
    AN25 AE29 L4 B19
    AN22
    AN19
    VSS37
    VSS38
    VSS39
    VSS VSS117
    VSS118
    VSS119
    AE28
    AE27
    L3
    L2
    VSS195
    VSS196
    VSS197
    VSS VSS268
    VSS269
    VSS270
    B17
    B15
    AN16 AE26 L1 B13
    VSS40 VSS120 VSS198 VSS271
    AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
    AN10 AD7 K32 B9
    VSS42 VSS122 VSS200 VSS273
    AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8
    AN4 AC8 K26 B7
    VSS44 VSS124 VSS202 VSS275
    AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5
    AM25 AC5 J31 B3
    VSS46 VSS126 VSS204 VSS277
    AM22 AC3 H33 B2
    VSS47 VSS127 VSS205 VSS278
    AM19 AC2 H30 A35
    VSS48 VSS128 VSS206 VSS279
    AM16 AB35 H27 A32
    VSS49 VSS129 VSS207 VSS280
    AM13 AB34 H24 A29
    VSS50 VSS130 VSS208 VSS281
    AM10 AB33 H21 A26
    VSS51 VSS131 VSS209 VSS282
    AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23
    AM4 AB31 H15 A20
    VSS53 VSS133 VSS211 VSS284
    AM3 AB30 H13 A3
    VSS54 VSS134 VSS212 VSS285
    AM2 AB29 H10
    VSS55 VSS135 VSS213
    AM1 AB28 H9
    VSS56 VSS136 VSS214
    AL34 AB27 H8
    VSS57 VSS137 VSS215
    AL31 AB26 H7
    VSS58 VSS138 VSS216
    AL28 VSS59 VSS139 Y9 H6 VSS217
    AL25 Y8 H5
    VSS60 VSS140 VSS218
    AL22 Y6 H4
    VSS61 VSS141 VSS219
    AL19 Y5 H3
    VSS62 VSS142 VSS220
    AL16 Y3 H2
    VSS63 VSS143 VSS221
    AL13 Y2 H1
    B VSS64 VSS144 VSS222 B
    AL10 VSS65 VSS145 W35 G35 VSS223
    AL7 VSS66 VSS146 W34 G32 VSS224
    AL4 W33 G29
    VSS67 VSS147 VSS225
    AL2 VSS68 VSS148 W32 G26 VSS226
    AK33 W31 G23
    VSS69 VSS149 VSS227
    AK30 W30 G20
    VSS70 VSS150 VSS228
    AK27 W29 G17
    VSS71 VSS151 VSS229
    AK25 W28 G11
    VSS72 VSS152 VSS230
    AK22 W27 F34
    VSS73 VSS153 VSS231
    AK19 VSS74 VSS154 W26 F31 VSS232
    AK16 VSS75 VSS155 U9 F29 VSS233
    AK13 U8
    VSS76 VSS156
    AK10 VSS77 VSS157 U6
    AK7 U5
    VSS78 VSS158
    AK4 VSS79 VSS159 U3
    AJ25 U2
    VSS80 VSS160

    Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0


    ME@ ME@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PROCESSOR(7/7) VSS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 11 of 57
    5 4 3 2 1
    5 4 3 2 1

    +VREF_DQ_DIMMA +1.5V +1.5V +1.5V


    3A@1.5V
    [7] DDR_A_D[0..63]
    DDR3 SO-DIMM A

    1
    [7] DDR_A_DQS[0..7]
    R70
    JDIMM1 1K_0402_1%
    [7] DDR_A_DQS#[0..7] +VREF_DQ_DIMMA
    +VREF_DQ_DIMMA 1 2
    VREF_DQ VSS1 DDR_A_D4
    3 4 [7] DDR_A_MA[0..15]

    2
    VSS2 DQ4

    0.1U_0402_10V6K

    2.2U_0603_6.3V4Z
    DDR_A_D0 5 6 DDR_A_D5
    DQ0 DQ5

    C133

    C134
    1 1 DDR_A_D1 7 8
    DQ1 VSS3 DDR_A_DQS#0
    9 VSS4 DQS#0 10

    1
    DDR_A_DM0 11 12 DDR_A_DQS0
    DM0 DQS0
    13 VSS5 VSS6 14
    2 2 DDR_A_D2 DDR_A_D6 R71
    15 DQ2 DQ6 16
    D DDR_A_D3 17 18 DDR_A_D7 1K_0402_1% D
    DQ3 DQ7
    19 20

    2
    DDR_A_D8 VSS7 VSS8 DDR_A_D12
    21 DQ8 DQ12 22
    DDR_A_D9 23 24 DDR_A_D13
    DQ9 DQ13
    25 VSS9 VSS10 26
    DDR_A_DQS#1 27 28 DDR_A_DM1
    DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
    29 DQS1 RESET# 30 DDR3_DRAMRST# [7,13]
    31 VSS11 VSS12 32
    DDR_A_D10 33 34 DDR_A_D14
    DDR_A_D11 DQ10 DQ14 DDR_A_D15
    35 DQ11 DQ15 36
    37 VSS13 VSS14 38
    DDR_A_D16 39 40 DDR_A_D20
    DDR_A_D17 DQ16 DQ20 DDR_A_D21
    41 DQ17 DQ21 42
    43 VSS15 VSS16 44
    DDR_A_DQS#2 45 46 DDR_A_DM2
    DDR_A_DQS2 DQS#2 DM2
    47 DQS2 VSS17 48
    49 50 DDR_A_D22
    DDR_A_D18 VSS18 DQ22 DDR_A_D23
    51 DQ18 DQ23 52
    DDR_A_D19 53 54
    DQ19 VSS19 DDR_A_D28
    55 VSS20 DQ28 56
    DDR_A_D24 57 58 DDR_A_D29
    DDR_A_D25 DQ24 DQ29
    59 DQ25 VSS21 60
    61 62 DDR_A_DQS#3
    DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
    63 DM3 DQS3 64
    65 VSS23 VSS24 66
    DDR_A_D26 67 68 DDR_A_D30
    DDR_A_D27 DQ26 DQ30 DDR_A_D31
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72

    [7] DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA


    C CKE0 CKE1 DDR_CKE1_DIMMA [7] C
    75 VDD1 VDD2 76
    77 78 DDR_A_MA15
    DDR_A_BS2 NC1 A15 DDR_A_MA14
    [7] DDR_A_BS2 79 BA2 A14 80
    81 VDD3 VDD4 82
    DDR_A_MA12 83 84 DDR_A_MA11
    DDR_A_MA9 A12/BC# A11 DDR_A_MA7
    85 A9 A7 86
    87 VDD5 VDD6 88
    DDR_A_MA8 89 90 DDR_A_MA6
    DDR_A_MA5 A8 A6 DDR_A_MA4
    91 A5 A4 92
    93 VDD7 VDD8 94
    DDR_A_MA3 95 96 DDR_A_MA2
    DDR_A_MA1 A3 A2 DDR_A_MA0
    97 A1 A0 98
    99 VDD9 VDD10 100
    M_CLK_DDR0 M_CLK_DDR1
    [7] M_CLK_DDR0
    [7] M_CLK_DDR#0 M_CLK_DDR#0
    101
    103
    CK0 CK1 102
    104 M_CLK_DDR#1
    M_CLK_DDR1 [7] OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
    CK0# CK1# M_CLK_DDR#1 [7]
    105 VDD11 VDD12 106
    DDR_A_MA10 DDR_A_BS1
    [7] DDR_A_BS0 DDR_A_BS0
    107
    109
    A10/AP BA1 108
    110 DDR_A_RAS#
    DDR_A_BS1 [7] +1.5V Layout Note: (10uF_0603_6.3V)*8
    BA0 RAS# DDR_A_RAS# [7]
    111 112 Place near DIMM
    DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
    [7] DDR_A_WE# 113 WE# S0# 114 DDR_CS0_DIMMA# [7] (0.1uF_402_10V)*4

    1
    [7] DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
    CAS# ODT0 M_ODT0 [7]
    117 118 R72
    DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
    119 A13 ODT1 120 M_ODT1 [7]
    [7] DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
    S1# NC2
    123 124

    2
    VDD17 VDD18 +VREF_CA +1.5V
    125 NCTEST VREF_CA 126
    127 VSS27 VSS28 128

    0.1U_0402_10V6K

    2.2U_0603_6.3V4Z
    DDR_A_D32 129 130 DDR_A_D36
    DQ32 DQ36

    1
    C135

    C136

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    DDR_A_D33 131 132 DDR_A_D37 1 1
    DQ33 DQ37

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K
    133 VSS29 VSS30 134 1

    C137

    C138

    C139

    C140

    C141

    C142

    C143

    C144

    C145

    C146

    C147

    C148
    DDR_A_DQS#4 135 136 DDR_A_DM4 R73 1 1 1 1 1 1 1 1 1 1 1 1
    DDR_A_DQS4 DQS#4 DM4 1K_0402_1% + C149
    137 DQS4 VSS31 138
    B DDR_A_D38 2 2 220U_6.3V_M B
    139 140

    2
    DDR_A_D34 VSS32 DQ38 DDR_A_D39 @ @
    141 DQ34 DQ39 142
    DDR_A_D35 2 2 2 2 2 2 2 2 2 2 2 2 2
    143 DQ35 VSS33 144
    145 146 DDR_A_D44
    DDR_A_D40 VSS34 DQ44 DDR_A_D45
    147 DQ40 DQ45 148
    DDR_A_D41 149 150
    DQ41 VSS35 DDR_A_DQS#5
    151 VSS36 DQS#5 152
    DDR_A_DM5 153 154 DDR_A_DQS5
    DM5 DQS5
    155 VSS37 VSS38 156 VDDQ(1.5V) =
    DDR_A_D42 157 158 DDR_A_D46
    DDR_A_D43 DQ42 DQ46 DDR_A_D47
    159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
    161 VSS39 VSS40 162
    DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR)
    DDR_A_D49 DQ48 DQ52 DDR_A_D53
    165 DQ49 DQ53 166 Layout Note:
    167 VSS41 VSS42 168
    DDR_A_DQS#6 169 170 DDR_A_DM6 VTT(0.75V) = Place near DIMM
    DDR_A_DQS6 DQS#6 DM6
    171 DQS6 VSS43 172
    173 174 DDR_A_D54 3*0805 10uf 4*0402 1uf 7/28 Update connect GND directly
    DDR_A_D50 VSS44 DQ54 DDR_A_D55
    175 DQ50 DQ55 176
    DDR_A_D51 177 178 VREF =
    DQ51 VSS45 DDR_A_D60 +0.75VS
    179 VSS46 DQ60 180
    DDR_A_D56 181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf DDR_A_DM0
    DDR_A_D57 DQ56 DQ61 DDR_A_DM1
    183 DQ57 VSS47 184
    185 186 DDR_A_DQS#7 VDDSPD (3.3V)= DDR_A_DM2
    DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7 DDR_A_DM3
    187 DM7 DQS7 188

    C150

    1U_0402_6.3V6K
    C151

    1U_0402_6.3V6K
    C152

    1U_0402_6.3V6K
    C153

    1U_0402_6.3V6K
    189 190 1*0402 0.1uf 1*0402 2.2uf DDR_A_DM4
    DDR_A_D58 VSS49 VSS50 DDR_A_D62 DDR_A_DM5
    191 DQ58 DQ62 192 1 1 1 1
    DDR_A_D59 193 194 DDR_A_D63 DDR_A_DM6
    DQ59 DQ63
    1 R81 2 195 VSS51 VSS52 196 DDR_A_DM7
    10K_0402_5% 197 198
    SA0 EVENT# SMB_DATA_S3 2 2 2 2
    +3VS 199 VDDSPD SDA 200 SMB_DATA_S3 [13,15,34]
    2.2U_0603_6.3V4Z

    0.1U_0402_10V6K

    201 202 SMB_CLK_S3 Layout Note:


    SA1 SCL SMB_CLK_S3 [13,15,34]
    C155

    C156

    A 203 204 A
    1 1 VTT1 VTT2 +0.75VS
    1

    Place near DIMM


    10K_0402_5%
    R83

    205 206 0.65A@0.75V


    G1 G2
    2 2 FOX_AS0A626-U4SN-7F
    ME@
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDRIII-SODIMM SLOT1
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 12 of 57
    5 4 3 2 1
    5 4 3 2 1

    +VREF_DQ_DIMMB 3A@1.5V
    [7] DDR_B_D[0..63]
    +1.5V +1.5V
    [7] DDR_B_DQS[0..7]
    JDIMM2 +1.5V
    [7] DDR_B_DQS#[0..7]
    +VREF_DQ_DIMMB 1 2
    VREF_DQ VSS1 DDR_B_D4
    3 VSS2 DQ4 4 [7] DDR_B_MA[0..15]

    1
    2.2U_0603_6.3V4Z

    0.1U_0402_10V6K
    DDR_B_D0 5 6 DDR_B_D5
    DDR_B_D1 DQ0 DQ5 R84
    1 1 7 DQ1 VSS3 8
    9 10 DDR_B_DQS#0 1K_0402_1%
    C158 VSS4 DQS#0 +VREF_DQ_DIMMB

    C157
    DDR_B_DM0 11 12 DDR_B_DQS0
    DM0 DQS0
    13 14

    2
    2 2 DDR_B_D2 VSS5 VSS6 DDR_B_D6
    15 DQ2 DQ6 16
    DDR_B_D3 17 18 DDR_B_D7
    D DQ3 DQ7 D
    19 VSS7 VSS8 20

    1
    DDR_B_D8 21 22 DDR_B_D12
    DDR_B_D9 DQ8 DQ12 DDR_B_D13
    23 DQ9 DQ13 24
    25 26 R85
    DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1 1K_0402_1%
    27 DQS#1 DM1 28
    DDR_B_DQS1 29 30 DDR3_DRAMRST#
    DDR3_DRAMRST# [7,12]

    2
    DQS1 RESET#
    31 VSS11 VSS12 32
    DDR_B_D10 33 34 DDR_B_D14
    DDR_B_D11 DQ10 DQ14 DDR_B_D15
    35 DQ11 DQ15 36
    37 VSS13 VSS14 38
    DDR_B_D16 39 40 DDR_B_D20
    DDR_B_D17 DQ16 DQ20 DDR_B_D21
    41 DQ17 DQ21 42 For Arranale only +VREF_DQ_DIMMB
    43 VSS15 VSS16 44
    DDR_B_DQS#2 45 DQS#2 DM2 46 DDR_B_DM2 supply from a external 1.5V voltage divide
    DDR_B_DQS2 47 48
    DQS2 VSS17 DDR_B_D22
    circuit.
    49 VSS18 DQ22 50
    DDR_B_D18 51 DQ18 DQ23 52 DDR_B_D23 07/17/2009
    DDR_B_D19 53 54
    DQ19 VSS19 DDR_B_D28
    55 VSS20 DQ28 56
    DDR_B_D24 57 58 DDR_B_D29
    DDR_B_D25 DQ24 DQ29
    59 DQ25 VSS21 60
    61 62 DDR_B_DQS#3
    DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
    63 DM3 DQS3 64
    65 VSS23 VSS24 66
    DDR_B_D26 67 68 DDR_B_D30
    DDR_B_D27 DQ26 DQ30 DDR_B_D31
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72

    [7] DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB


    CKE0 CKE1 DDR_CKE3_DIMMB [7]
    75 VDD1 VDD2 76
    C 77 78 DDR_B_MA15 C
    DDR_B_BS2 NC1 A15 DDR_B_MA14
    [7] DDR_B_BS2 79 BA2 A14 80
    81 VDD3 VDD4 82
    DDR_B_MA12 83 84 DDR_B_MA11
    DDR_B_MA9 A12/BC# A11 DDR_B_MA7
    85 A9 A7 86
    87 VDD5 VDD6 88
    DDR_B_MA8 89 90 DDR_B_MA6
    DDR_B_MA5 A8 A6 DDR_B_MA4
    91 A5 A4 92
    93 VDD7 VDD8 94
    DDR_B_MA3 95 96 DDR_B_MA2
    DDR_B_MA1 A3 A2 DDR_B_MA0
    97 A1 A0 98
    99 VDD9 VDD10 100
    [7] M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
    CK0 CK1 M_CLK_DDR3 [7]
    [7] M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
    CK0# CK1# M_CLK_DDR#3 [7]
    105 VDD11 VDD12 106
    DDR_B_MA10 107 108 DDR_B_BS1
    A10/AP BA1 DDR_B_BS1 [7] +1.5V
    DDR_B_BS0 DDR_B_RAS#
    [7] DDR_B_BS0 109
    111
    BA0 RAS# 110
    112
    DDR_B_RAS# [7] Layout Note: (10uF_0603_6.3V)*8
    DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB# Place near DIMM
    [7] DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB# [7]

    1
    DDR_B_CAS# M_ODT2
    [7] DDR_B_CAS# 115
    117
    CAS# ODT0 116
    118
    M_ODT2 [7]
    R86 (0.1uF_402_10V)*4
    DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1%
    119 A13 ODT1 120 M_ODT3 [7]
    [7] DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
    S1# NC2
    123 124

    2
    VDD17 VDD18 +VREF_CB
    125 NCTEST VREF_CA 126
    +1.5V
    0.1U_0402_10V6K

    2.2U_0603_6.3V4Z
    127 VSS27 VSS28 128
    DDR_B_D32 129 130 DDR_B_D36
    DQ32 DQ36

    1
    C159

    C160
    DDR_B_D33 131 132 DDR_B_D37 1 1
    DQ33 DQ37

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    133 VSS29 VSS30 134

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K
    DDR_B_DQS#4 135 136 DDR_B_DM4 R87
    DQS#4 DM4

    C161

    C162

    C163

    C164

    C165

    C166

    C167

    C168

    C169

    C170

    C171

    C172
    DDR_B_DQS4 137 138 1K_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1
    DQS4 VSS31 DDR_B_D38 2 2
    139 140

    2
    B DDR_B_D34 VSS32 DQ38 DDR_B_D39 B
    141 DQ34 DQ39 142
    DDR_B_D35 143 144 @ @
    DQ35 VSS33 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
    145 VSS34 DQ44 146
    DDR_B_D40 147 148 DDR_B_D45
    DDR_B_D41 DQ40 DQ45
    149 DQ41 VSS35 150
    151 152 DDR_B_DQS#5
    DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
    153 DM5 DQS5 154 VDDQ(1.5V) =
    155 VSS37 VSS38 156
    DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
    DDR_B_D43 DQ42 DQ46 DDR_B_D47
    159 DQ43 DQ47 160
    161 VSS39 VSS40 162 6*0603 10uf (PER CONNECTOR)
    DDR_B_D48 163 164 DDR_B_D52
    DDR_B_D49 DQ48 DQ52 DDR_B_D53
    165 DQ49 DQ53 166 Layout Note:
    167 VSS41 VSS42 168 VTT(0.75V) =
    DDR_B_DQS#6 169 DQS#6 DM6 170 DDR_B_DM6 Place near DIMM
    DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf
    DQS6 VSS43 DDR_B_D54
    173 VSS44 DQ54 174 7/28 Update connect GND directly
    DDR_B_D50 175 176 DDR_B_D55
    DDR_B_D51 DQ50 DQ55
    177 DQ51 VSS45 178
    DDR_B_D60 +0.75VS
    179 VSS46 DQ60 180 1*0402 0.1uf 1*0402 2.2uf
    DDR_B_D56 181 182 DDR_B_D61
    DDR_B_D57 DQ56 DQ61 DDR_B_DM0
    183 DQ57 VSS47 184 VDDSPD (3.3V)=
    185 186 DDR_B_DQS#7 DDR_B_DM1
    DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7 DDR_B_DM2
    187 DM7 DQS7 188 1*0402 0.1uf 1*0402 2.2uf

    C173

    1U_0402_6.3V6K
    C174

    1U_0402_6.3V6K
    C175

    1U_0402_6.3V6K
    C176

    1U_0402_6.3V6K
    189 190 DDR_B_DM3
    DDR_B_D58 VSS49 VSS50 DDR_B_D62 DDR_B_DM4
    191 DQ58 DQ62 192 1 1 1 1
    DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
    DQ59 DQ63 DDR_B_DM6
    195 VSS51 VSS52 196
    1 R95 2 197 SA0 EVENT# 198 DDR_B_DM7
    10K_0402_5% SMB_DATA_S3 2 2 2 2
    199 VDDSPD SDA 200 SMB_DATA_S3 [12,15,34]
    1 2 201 202 SMB_CLK_S3
    +3VS SA1 SCL SMB_CLK_S3 [12,15,34]
    2.2U_0603_6.3V4Z

    0.1U_0402_10V6K

    R97 10K_0402_5% 203 204 +0.75VS


    VTT1 VTT2 0.65A@0.75V
    C177

    C178

    A A
    1 1 Layout Note:
    205 G1 G2 206
    Place near DIMM
    FOX_AS0A626-U8SN-7F
    2 2 ME@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDRIII-SODIMM SLOT2
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 13 of 57
    5 4 3 2 1
    5 4 3 2 1

    PCH_RTCX1 1 @ 2 R663 0_0402_5% PCH_RTCX1_OUT [40]


    W=20mils W=20mils 1 2 PCH_RTCX2 1 @ 2 R670 0_0402_5% PCH_RTCX2_OUT [40]
    R98 10M_0402_5%
    +RTCVCC +RTCBATT

    R99 6/24 Update R663,R670 must be close Y1


    1K_0402_5%

    32.768KHZ_12.5PF_9H03200413
    1 2

    4
    18P_0402_50V8J
    1
    1 Y1

    OSC

    OSC
    C179 CLRP1 1 1
    1U_0603_10V4Z SHORT PADS C181

    2
    C180 18P_0402_50V8J
    2

    NC

    NC
    D 2 2 D

    3
    CMOS

    U4A
    +RTCVCC

    SHORT PADS
    CLRP2
    +RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
    1 RTCX1 FWH0 / LAD0 LPC_AD0 [34,40]

    1
    R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1

    LPC
    PCH_RTCX2 FWH1 / LAD1 LPC_AD2 LPC_AD1 [34,40]
    C183 C20 B37 EC and Mini card debug port
    PCH_INTVRMEN RTCX2 FWH2 / LAD2 LPC_AD3 LPC_AD2 [34,40]
    R102 1 2 330K_0402_5% 1U_0603_10V4Z C37 LPC_AD3 [34,40]

    2
    2 PCH_RTCRST# FWH3 / LAD3
    1 2 D20
    R103 20K_0402_5% RTCRST# LPC_FRAME#
    INTVRMEN FWH4 / LFRAME#
    D36 LPC_FRAME# [34,40]
    ：Integrated 1 2 PCH_SRTCRST# G22
    SRTCRST#
    * LH： Integrated VRM enable R100 20K_0402_5% E36 +3VS
    1

    RTC
    LDRQ0#

    1
    SHORT PADS
    CLRP3
    VRM disable SM_INTRUDER# K22 K36 R104 2 1 10K_0402_5%
    C182 INTRUDER# LDRQ1# / GPIO23
    (INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ [40]

    2
    2 INTVRMEN SERIRQ

    AM3 SATA_DTX_C_IRX_N0
    +3VS SATA0RXN SATA_DTX_C_IRX_N0 [38]
    HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
    HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 [38]

    SATA 6G
    AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0 HDD
    SATA0TXN SATA_ITX_DRX_N0 [38]
    R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 [38]
    HDA_SYNC SATA0TXP
    HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10
    [39] HDA_SPKR SPKR SATA1RXN
    LOW= Disable (Default)
    * HDA_RST# K34 HDA_RST#
    SATA1RXP
    SATA1TXN
    AM8
    AP11
    AP10
    SATA1TXP
    C +3VALW HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
    [39] HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 [56]
    AD5 SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 [56] ODD
    R106 2 @ 1 1K_0402_5% HDA_SDOUT SATA2RXP SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 SATA_ITX_DRX_N2_CONN
    G34 AH5 1 C186 SATA_ITX_DRX_N2_CONN [56]
    HDA_SDIN1 SATA2TXN SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2 SATA_ITX_DRX_P2_CONN
    SATA2TXP AH4 1 C187 SATA_ITX_DRX_P2_CONN [56]
    Low = Disabled (Default)
    * C34

    IHDA
    HDA_SDIN2
    High = Enabled [Flash Descriptor Security Overide] AB8
    SATA3RXN
    A34 HDA_SDIN3 SATA3RXP AB10
    AF3
    R109 SATA3TXN
    SATA3TXP AF1
    ME_FLASH 1 2 HDA_SDOUT A36
    [40] ME_FLASH

    SATA
    +3VALW 0_0402_5% HDA_SDO SATA_DTX_C_IRX_N4
    SATA4RXN Y7 SATA_DTX_C_IRX_N4 [42]
    Y5 ESATA@ SATA_DTX_C_IRX_P4 ESATA
    SATA4RXP SATA_DTX_C_IRX_P4 [42]
    R108 2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 AD3 SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C188 SATA_ITX_DRX_N4
    HDA_DOCK_EN# / GPIO33 SATA4TXN SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 SATA_ITX_DRX_P4 SATA_ITX_DRX_N4 [42] R01
    AD1 1 C189 SATA_ITX_DRX_P4 [42]
    Kill_SW# SATA4TXP ESATA@
    This signal has a weak internal pull-down [56] Kill_SW# N32
    HDA_DOCK_RST# / GPIO13
    Y3
    R110 SATA5RXN
    Y1
    On Die PLL VR Select is supplied by 51_0402_5% SATA5RXP
    AB3 7/28 change from port 5 to port 4
    1.5V when smapled high PCH_JTAG_TCK SATA5TXN
    * 1.8V when sampled low
    2 1 J3
    JTAG_TCK SATA5TXP
    AB1

    PCH_JTAG_TMS H7 Y11 R111


    Needs to be pulled High for Huron River platfrom

    JTAG
    JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA
    PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
    JTAG_TDI SATAICOMPI
    R112 PCH_JTAG_TDO H1
    33_0402_5% +3VS JTAG_TDO R113 +1.05VS_SATA3
    AB12
    HDA_BIT_CLK SATA3RCOMPO 49.9_0402_1%
    [39] HDA_BITCLK_AUDIO 1 2
    2
    G

    R114 Q10 AB13 SATA3_COMP 1 2


    33_0402_5% BSS138_NL_SOT23-3 SATA3COMPI
    1 2 HDA_SYNC_R 3 1 HDA_SYNC
    [39] HDA_SYNC_AUDIO
    R116 SPI_CLK_PCH_R RBIAS_SATA3 R115 1 2 750_0402_1%
    S

    T3 AH1
    33_0402_5% SPI_CLK SATA3RBIAS
    B HDA_RST# SPI_SB_CS0# B
    [39] HDA_RST_AUDIO# 1 2 Y14 SPI_CS0#
    R118 1 2 R117 2 1 10K_0402_5% +3VS
    33_0402_5% T1
    SPI

    HDA_SDOUT @ R325 SPI_CS1# HDD_LED#


    [39] HDA_SDOUT_AUDIO 1 2 SATALED# P3 HDD_LED# [56]
    0_0402_5%
    SPI_SI V4 V14 PCH_GPIO21 2 R119 1
    SPI_MOSI SATA0GP / GPIO21 +3VS
    10K_0402_5%
    +3VALW +3VALW +3VALW
    SPI_SO_R U3
    SPI_MISO SATA1GP / GPIO19
    P1 PCH_GPIO19 4MB SPI ROM FOR ME SPI_CLK_PCH
    6/17 follow module design
    COUGARPOINT_FCBGA989 & Non-share ROM.
    1

    1
    R121 R122 R123 R124
    200_0402_5% 200_0402_5% 200_0402_5% 33_0402_5%
    +3VS @
    2

    2
    PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI
    1

    R127 1 2 SPI_WP# C190


    R125 R126 R128 3.3K_0402_5% 22P_0402_50V8J
    100_0402_1% 100_0402_1% 100_0402_1% @
    R129 1 2 SPI_HOLD# +3VS
    3.3K_0402_5%
    2

    C191
    DPDG1.1 1 2
    R130
    6/30 update R121, R122, R123 0_0402_5% U5 0.1U_0402_16V4Z
    SPI_SB_CS0# 1 2 1 8
    SPI_SO_R SPI_SO_L CS# VCC SPI_HOLD# 0_0402_5% R132
    1 2 2 7
    SPI_WP# SO HOLD# SPI_CLK_PCH 1
    3 6 2 SPI_CLK_PCH_R
    33_0402_5% WP# SCLK SPI_SI_R
    4 5 1 2 SPI_SI
    R131 GND SI
    A S IC FL 32M W25Q32BVSSIG SOIC 8P 33_0402_5% A
    R133

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (1/8) SATA,HDA,SPI, LPC, XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 14 of 57
    5 4 3 2 1
    5 4 3 2 1

    10K_0402_5%
    U4B Q60A
    2 1 +3VALW 2N7002DW-T/R7_SOT363-6
    PCIE_PRX_DTX_N1 BG34 R134 6 1 SMB_CLK_S3
    [35] PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 [12,13,34]
    LAN [35] PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34 E12 EC_LID_OUT#
    PERP1 SMBALERT# / GPIO11 EC_LID_OUT# [40]
    C192 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 2.2K_0402_5% 2.2K_0402_5%
    [35] PCIE_PTX_C_DRX_N1
    [35] PCIE_PTX_C_DRX_P1
    C193
    1
    1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1
    AV32
    AU32
    PETN1
    H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1

    2
    PETP1 SMBCLK

    [34] PCIE_PRX_DTX_N2
    PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA
    +3VALW
    1 2 1
    +3VS
    2 DIMM2

    5
    PCIE_PRX_DTX_P2 R135 R138
    WLAN
    [34] PCIE_PRX_DTX_P2
    [34] PCIE_PTX_C_DRX_N2
    C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2
    BF34
    BB32
    PERP2
    PETN2
    2.2K_0402_5% 2.2K_0402_5% MINI CARD
    C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3

    SMBUS
    [34] PCIE_PTX_C_DRX_P2 PETP2 DRAMRST_CNTRL_PCH SMB_DATA_S3 [12,13,34]
    SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH [7]
    BG36 2N7002DW-T/R7_SOT363-6
    PERN3 PCH_SML0CLK
    BJ36 PERP3 SML0CLK C8 Q60B
    D D
    AV34 PETN3 2 R139 1 +3VALW
    AU34 G12 PCH_SML0DATA 1K_0402_5%
    PETP3 SML0DATA Q61A
    7/5 change to 1K 2N7002DW-T/R7_SOT363-6
    BF36
    PERN4 7/28 reserved
    BE36 10K_0402_5% 6 1 EC_SMB_CK2
    PERP4 EC_SMB_CK2 [24,37,40]
    AY34 C13 PCH_GPIO74 2 1 +3VALW
    PETN4 SML1ALERT# / PCHHOT# / GPIO74 2.2K_0402_5%
    BB34
    PETP4
    E14 PCH_SML1CLK R140 1 R141 2 VGA

    PCI-E*

    2
    SML1CLK / GPIO58
    BG37
    BH37
    PERN5
    PERP5 SML1DATA / GPIO75
    M16 PCH_SML1DATA
    +3VALW
    1 2
    +3VS EC

    5
    R142
    AY36
    BB36
    PETN5
    PETP5
    2.2K_0402_5% thermal sensor
    3 4 EC_SMB_DA2
    EC_SMB_DA2 [24,37,40]
    BJ38
    PERN6 2N7002DW-T/R7_SOT363-6
    BG38

    Controller
    PERP6
    AU36 M7 Q61B
    PETN6 CL_CLK1 +3VALW
    AV36 PETP6 +3VALW

    Link
    BG40 PERN7 CL_DATA1 T11

    2
    BJ40
    PERP7 R143
    AY40
    PETN7

    2
    BB40 P10 10K_0402_5%
    PETP7 CL_RST1# @ R544 R545
    BE38 R144 2.2K_0402_5% 2.2K_0402_5%

    1
    PERN8 0_0402_5%
    BC38
    PERP8 @
    AW38 1 2 PEG_CLKREQ# [24]

    1
    PETN8 PCH_SML0CLK
    AY38
    PETP8 10K_0402_5% R145
    PEG_A_CLKRQ# / GPIO47 M10 PEG_CLKREQ#_R 1 2 PCH_SML0DATA
    Desktop Only Y40
    Y39
    CLKOUT_PCIE0N
    CLKOUT_PCIE0P CLK_PCIE_VGA#_R CLK_PCIE_VGA#
    CLKOUT_PEG_A_N
    AB37 R146 1 DIS@ 2 0_0402_5% CLK_PCIE_VGA# [23] 7/28 reserved

    CLOCKS
    C R147 PCH_GPIO73 CLK_PCIE_VGA_R CLK_PCIE_VGA C
    +3VALW 2 1 10K_0402_5% J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 R148 1 2 0_0402_5% CLK_PCIE_VGA [23]
    DIS@
    @
    [34] CLK_PCIE_WLAN1#
    R149 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 CLK_CPU_DMI#
    CLK_CPU_DMI# [6]
    CLK_CPU_DMI# R349 1 2 10K_0402_5%
    [34] CLK_PCIE_WLAN1
    R150 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLK_CPU_DMI
    CLK_CPU_DMI [6]
    CLK_CPU_DMI R347 1 2 10K_0402_5%
    WLAN
    [34] WLAN_CLKREQ1# R156 1 2 0_0402_5% WLAN_CLKREQ1#_R M1 @
    R158 PCIECLKRQ1# / GPIO18
    +3VS 2 1 10K_0402_5% AM12
    CLKOUT_DP_N / CLKOUT_BCLK1_N
    AA48
    CLKOUT_DP_P / CLKOUT_BCLK1_P AM13 6/30 Update to @
    CLKOUT_PCIE2N
    AA47 CLKOUT_PCIE2P
    BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
    R301 CLKIN_DMI_N CLK_BUF_CPU_DMI
    +3VS 2 1 10K_0402_5% V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 R157 1 2 10K_0402_5%

    R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%


    [35] CLK_PCIE_LAN# CLKOUT_PCIE3N CLKIN_DMI2_N
    LAN R154 1 2 0_0402_5% CLK_PCIE_LAN_R Y36 BG30 CLKIN_DMI2 R160 1 2 10K_0402_5%
    [35] CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_DMI2_P
    R151 1 2 0_0402_5% PCH_GPIO25 A8
    [35] CLKREQ_LAN# PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M#
    +3VALW R152 2 1 10K_0402_5% G24 R162 1 2 10K_0402_5%
    CLKIN_DOT_96N CLK_BUF_DREF_96M R163 1 10K_0402_5%
    E24 2
    CLKIN_DOT_96P
    Y43
    CLKOUT_PCIE4N
    Y45
    CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R164 1 10K_0402_5%
    AK7 2
    R165 PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_BUF_PCIE_SATA R166 1
    +3VALW 2 1 10K_0402_5% L12 AK5 2 10K_0402_5%
    PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P

    V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%


    CLKOUT_PCIE5N REFCLK14IN
    V46
    CLKOUT_PCIE5P
    R168 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
    +3VALW PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK [18]
    B XTAL25_IN B
    AB42 V47 XTAL25_IN
    CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_OUT
    AB40 V49 1 2
    CLKOUT_PEG_B_P XTAL25_OUT R169 1M_0402_5%
    R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
    +3VALW PEG_B_CLKRQ# / GPIO56 90.9_0402_1% Y2
    Y47 XCLK_RCOMP 1 2 2 1
    XCLK_RCOMP
    V40 1 1
    @ CLKOUT_PCIE6N
    1 R520 2 100K_0402_5% V42 25MHZ_20PF_7A25000012
    CLKOUT_PCIE6P C196 C197
    +3VALW 2 R172 1 10K_0402_5% PCH_GPIO45 T13 PCIECLKRQ6# / GPIO45
    18P_0402_50V8J 18P_0402_50V8J
    2 2
    PE_GPIO0 1 @ 2 V38 K43
    [18] PE_GPIO0 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
    R700 0_0402_5% R173
    FLEX CLOCKS

    V37
    CLKOUT_PCIE7P CLK_PCI_DB_R
    CLKOUTFLEX1 / GPIO65 F47 1 2 22_0402_5% CLK_PCI_DB [34]
    +3VALW R174 2 1 10K_0402_5% PCH_GPIO46 K12 @
    PCIECLKRQ7# / GPIO46
    H47
    PE_GPIO1 PCIE_CLK_8N CLKOUTFLEX2 / GPIO66
    [18,25,26,52] PE_GPIO1 1 2 AK14
    R701 0_0402_5% PCIE_CLK_8P CLKOUT_BCLK0_N / CLKOUT_PCIE8N
    AK13 K49
    @ CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 @ R175 @ C198
    33_0402_5% 22P_0402_50V8J
    COUGARPOINT_FCBGA989 CLK_BUF_ICH_14M 2 1 1 2

    6/23 for GPU Reserve for EMI please close to PCH

    @ R176 @ C199
    33_0402_5% 22P_0402_50V8J
    CLK_PCI_LPBACK 2 1 1 2
    A A

    Reserve for EMI please close to PCH

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (2/8) PCIE, SMBUS, CLK
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 15 of 57
    5 4 3 2 1
    5 4 3 2 1

    D D

    U4C

    DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0


    [5] DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 [5]
    MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
    [5] DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 [5]
    3

    DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2


    [5] DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 [5]
    VGATE 1 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
    G

    A [5] DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 [5]


    SYS_PWROK FDI_CTX_PRX_N4
    PCH_POK 2
    Y 4 R01 DMI_CTX_PRX_P0 BE24
    FDI_RXN4 BC12
    BJ12 FDI_CTX_PRX_N5
    FDI_CTX_PRX_N4 [5]
    B [5] DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 [5]
    P

    DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6


    [5] DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 [5]
    U6 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
    [5] DMI_CTX_PRX_P2 FDI_CTX_PRX_N7 [5]
    5

    DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7


    [5] DMI_CTX_PRX_P3 BJ20
    DMI3RXP FDI_CTX_PRX_P0
    * 7/28 Defult use AND Gate FDI_RXP0
    BG14 FDI_CTX_PRX_P0 [5]
    DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
    [5] DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 [5]
    +3VS DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
    [5] DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 [5]
    DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 [5]
    [5] DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
    R180 2 1 100K_0402_1% SYS_PWROK DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4

    DMI
    FDI
    [5] DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 [5]
    BG12 FDI_CTX_PRX_P5
    FDI_RXP5 FDI_CTX_PRX_P5 [5]
    DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
    [5] DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 [5]
    DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
    [5] DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 [5]
    DMI_CRX_PTX_P2 AY18
    [5] DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI2TXP
    [5] DMI_CRX_PTX_P3 AU18
    DMI3TXP FDI_INT
    FDI_INT AW16 FDI_INT [5]
    R743 +RTCVCC
    PCH_POK_R 1 2 @ SYS_PWROK +1.05VS_PCH BJ24 AV12 FDI_FSYNC0
    DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 [5]
    0_0402_5%

    1
    1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
    DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [5]
    R742 R177 49.9_0402_1% R179
    1 2 @ 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 330K_0402_5%
    C [40] SYS_PWROK_EC DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [5] C
    0_0402_5% R178 750_0402_1%
    4mil width and place BB10 FDI_LSYNC1
    FDI_LSYNC1 [5]

    2
    FDI_LSYNC1
    within 500mil of the PCH
    7/22 modify SUSACK# is only used on platform A18 DSWODVREN
    DSWVRMEN

    1
    that support the Deep Sx state. 0_0402_5% 1 R181 2 @ PCH_RSMRST#_R

    System Power Management


    R183
    T72 PAD SUSACK# C12 E22 PCH_DPWROK_R 0_0402_5% 1 R182 2 330K_0402_5%
    SUSACK# DPWROK PCH_DPWROK [40]
    R185 @
    0_0402_5% 7/28 Update

    2
    +3VS 2 1 SYS_RST# K3 B9 WAKE# 1 2 PCIE_WAKE# [34,35]
    R184 10K_0402_5% SYS_RESET# WAKE#
    1 2 10K_0402_5% +3VALW
    R186
    SYS_PWROK P12 N3 PM_CLKRUN# PAD T73

    ：
    SYS_PWROK CLKRUN# / GPIO32
    R188 1 @ 2 0_0402_5% R189 2 DSWODVREN - On Die DSW VR Enable
    [53] VGATE 1 +3VS *
    ：
    8.2K_0402_5% H Enable
    AEPWROK can be connect to R190 1 2 0_0402_5% PCH_POK_R L22 G8 SUS_STAT# L Disable
    [40] PCH_POK PWROK SUS_STAT# / GPIO61
    PWROK if iAMT disable
    R191 R302 1 2 0_0402_5% APWROK L10 N14 SUSCLK
    [40] PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK [40]
    PCH_POK_R 1 2 APWROK

    0_0402_5% @ PM_DRAM_PWRGD B13 SLP_S5#


    7/22 modify [6] PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63
    D10 SLP_S5# [40]

    1 2 PCH_RSMRST#_R C21 H4 SLP_S4#


    +3VALW [40] EC_RSMRST# RSMRST# SLP_S4# SLP_S4# [40]
    R193 0_0402_5%

    1 2 SUSWARN#_R K16 F4 SLP_S3#


    [40] SUSWARN# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# SLP_S3# [40]
    @ R196 0_0402_5%
    R192 2 1 200_0402_5% PM_DRAM_PWRGD Can be left NC
    B PBTN_OUT#_R B
    [40] PBTN_OUT# 1 2 E20 PWRBTN# SLP_A# G10 when IAMT is not
    R194 2 1 10K_0402_5% SUSWARN# R198 0_0402_5% support on the
    R195 ACIN_R ACIN_R PM_SLP_SUS# platfrom
    2 1 10K_0402_5% [24,40,47] ACIN
    D29 1 @ 2 RB751V_SOD323 H20 ACPRESENT / GPIO31 SLP_SUS# G16 PAD T71

    1 2
    R197 2 1 10K_0402_5% PCH_RSMRST#_R R01 R199 @ 0_0402_5%
    1 R200 2 PCH_GPIO72 E10 AP14 H_PM_SYNC
    BATLOW# / GPIO72 PMSYNCH H_PM_SYNC [6]
    8.2K_0402_5%
    R201 Can be left NC if no use
    +3VALW 2 1 RI# A10 RI# SLP_LAN# / GPIO29 K14 integrated LAN.
    10K_0402_5%

    COUGARPOINT_FCBGA989
    7/28 modify

    +3VS

    R546 2 1 200_0402_5% PM_DRAM_PWRGD

    7/28 Modify follow CRB & ORB

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (3/8) DMI,FDI,PM,
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 16 of 57
    5 4 3 2 1
    5 4 3 2 1

    D D
    +3VS

    1
    R234 R523
    2.2K_0402_5% 2.2K_0402_5%
    PX@ PX@ U4D
    PCH_ENBKL J47 AP43
    [31] PCH_ENBKL

    2
    PCH_ENVDD L_BKLTEN SDVO_TVCLKINN +3VS
    [31] PCH_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45
    EDID_CLK
    EDID_DATA P45 AM42
    [31] PCH_PWM L_BKLTCTL SDVO_STALLN
    AM40
    SDVO_STALLP

    1
    EDID_CLK T40
    [31] EDID_CLK L_DDC_CLK
    Pull up R for Chipset SIDE EDID_DATA K47 AP39 R202 R203
    [31] EDID_DATA L_DDC_DATA SDVO_INTN
    AP40 2.2K_0402_5% 2.2K_0402_5%
    R204 1 CTRL_CLK SDVO_INTP
    +3VS 2 2.2K_0402_5% T45 UMA_HDMI@ UMA_HDMI@
    R205 1 CTRL_DATA L_CTRL_CLK
    2 2.2K_0402_5% P39

    2
    2.37K_0402_1% L_CTRL_DATA
    R206 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
    LVD_IBG SDVO_CTRLCLK HDMICLK_NB [33]
    PX@ AF36 M39 HDMIDAT_NB
    LVD_VBG SDVO_CTRLDATA HDMIDAT_NB [33]
    0_0402_5% LVD_VREF AE48
    R207 LVD_VREFH
    2 1 AE47 AT49
    PX@ LVD_VREFL DDPB_AUXN
    DDPB_AUXP AT47
    AT40 TMDS_B_HPD# [33]
    DDPB_HPD
    AK39

    LVDS
    [31] LVDS_ACLK# LVDSA_CLK#
    [31] LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCH UMA_HDMI@ C200 1 2 0.1U_0402_10V6K
    HDMI_TX2-_CK [33]
    DDPB_0P AV40 TMDS_B_DATA2_PCH UMA_HDMI@ C201 1 2 0.1U_0402_10V6K
    HDMI_TX2+_CK [33]
    [31] LVDS_A0# AN48 AV45 TMDS_B_DATA1#_PCH UMA_HDMI@ C202 1 2 0.1U_0402_10V6K
    HDMI_TX1-_CK [33]
    LVDSA_DATA#0 DDPB_1N
    AM47 AV46 TMDS_B_DATA1_PCH UMA_HDMI@ C203 1 2 0.1U_0402_10V6K

    Digital Display Interface


    C [31] LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK [33] C
    [31] LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCH UMA_HDMI@ C204 1 2 0.1U_0402_10V6K
    HDMI_TX0-_CK [33] HDMI
    AJ48 AU47 TMDS_B_DATA0_PCH UMA_HDMI@ C205 1 2 0.1U_0402_10V6K
    HDMI_TX0+_CK [33]
    LVDSA_DATA#3 DDPB_2P
    AV47 TMDS_B_CLK#_PCH UMA_HDMI@ C206 1 2 0.1U_0402_10V6K
    HDMI_CLK-_CK [33]
    DDPB_3N
    [31] LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH UMA_HDMI@ C207 1 2 0.1U_0402_10V6K
    HDMI_CLK+_CK [33]
    [31] LVDS_A1 AM49 LVDSA_DATA1
    [31] LVDS_A2 AK49
    LVDSA_DATA2 UMA_HDMI@
    AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
    P42
    DDPC_CTRLDATA
    R01 AF40
    [31] LVDS_BCLK# LVDSB_CLK#
    [31] LVDS_BCLK AF39 LVDSB_CLK DDPC_AUXN AP47
    07/16 [31] LVDS_B0# AH45 LVDSB_DATA#0
    DDPC_AUXP
    DDPC_HPD
    AP49
    AT38
    For PIWG4(17") Dual channel Use [31] LVDS_B1#
    [31] LVDS_B2#
    AH47
    AF49
    LVDSB_DATA#1
    LVDSB_DATA#2 DDPC_0N
    AY47
    AF45 AY49
    LVDSB_DATA#3 DDPC_0P
    AY43
    DDPC_1N
    [31] LVDS_B0 AH43 AY45
    LVDSB_DATA0 DDPC_1P
    [31] LVDS_B1 AH49 BA47
    LVDSB_DATA1 DDPC_2N
    [31] LVDS_B2 AF47 LVDSB_DATA2 DDPC_2P BA48
    AF43 BB47
    DAC_BLU LVDSB_DATA3 DDPC_3N
    [32] DAC_BLU BB49
    R208 2 DDPC_3P
    1 150_0402_1%
    PX@ DAC_GRN
    [32] DAC_GRN
    R209 2 1 150_0402_1% N48 M43
    PX@ DAC_RED CRT_BLUE DDPD_CTRLCLK
    [32] DAC_RED P49 M36
    R210 2 CRT_GREEN DDPD_CTRLDATA
    1 150_0402_1% T49 CRT_RED
    PX@
    AT45

    CRT
    +3VS CRT_DDC_CLK DDPD_AUXN
    [32] CRT_DDC_CLK T39 AT43
    CRT_DDC_DATA CRT_DDC_CLK DDPD_AUXP
    Pull up R for Chipset SIDE [32] CRT_DDC_DATA M40
    CRT_DDC_DATA DDPD_HPD
    BH41
    B B
    DDPD_0N BB43
    1

    [32] CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45


    R524 R559 M49 BF44
    [32] CRT_VSYNC CRT_VSYNC DDPD_1N
    2.2K_0402_5% 2.2K_0402_5% BE44
    PX@ PX@ DDPD_1P
    BF42
    CRT_IREF DDPD_2N
    T43 BE42
    2

    DAC_IREF DDPD_2P
    T42 BJ42
    CRT_DDC_CLK CRT_IRTN DDPD_3N
    BG42
    DDPD_3P
    1

    CRT_DDC_DATA
    COUGARPOINT_FCBGA989
    R211
    1K_0402_1%
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (4/9) LVDS,CRT,DP,HDMI
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 17 of 57
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    RP2
    8 1 PCI_PIRQA# U4E
    7 2 PCI_PIRQD# AY7
    PCI_PIRQC# NV_CE#0
    6 3 NV_CE#1 AV7
    5 4 PCI_PIRQB# BG26 AU3
    TP1 NV_CE#2
    BJ26 TP2 NV_CE#3 BG4
    8.2K_0804_8P4R_5% BH25
    TP3
    BJ16 TP4 NV_DQS0 AT10
    BG16 BC8
    RP1 TP5 NV_DQS1
    AH38 TP6
    8 1 PCH_GPIO2 AH37 AU2
    PCH_GPIO54 TP7 NV_DQ0 / NV_IO0
    7 2 AK43 TP8 NV_DQ1 / NV_IO1 AT4
    D PCH_GPIO4 D
    6 3 AK45 TP9 NV_DQ2 / NV_IO2 AT3
    5 4 PCH_GPIO3 C18 AT1
    TP10 NV_DQ3 / NV_IO3
    N30 TP11 NV_DQ4 / NV_IO4 AY3
    8.2K_0804_8P4R_5% H3 AT5
    TP12 NV_DQ5 / NV_IO5
    AH12 AV3

    NVRAM
    R225 WL_OFF# TP13 NV_DQ6 / NV_IO6
    1 2 8.2K_0402_5% AM4 TP14 NV_DQ7 / NV_IO7 AV1
    AM5 BB1
    TP15 NV_DQ8 / NV_IO8
    Y13 TP16 NV_DQ9 / NV_IO9 BA3
    R212 1 2 8.2K_0402_5% PCH_GPIO52 K24 BB5
    TP17 NV_DQ10 / NV_IO10
    L24 BB3
    R213 PCH_GPIO5 TP18 NV_DQ11 / NV_IO11
    1 2 8.2K_0402_5% AB46 TP19 NV_DQ12 / NV_IO12 BB7
    AB45 BE8

    RSVD
    TP20 NV_DQ13 / NV_IO13
    NV_DQ14 / NV_IO14 BD4
    BF6
    R214 PCH_GPIO50 NV_DQ15 / NV_IO15
    1 2 8.2K_0402_5%
    B21 AV5
    @ TP21 NV_ALE NV_CLE
    M20 TP22 NV_CLE AY1
    AY16
    TP23
    BG46 TP24 NV_RCOMP AV10

    GPIO55 NV_RB#
    AT8
    PCH_GPIO51 R221 1 @ 2 1K_0402_5% DMI Termination Voltage
    WL_OFF# R215 1 @ 2 1K_0402_5% BE28 AY5
    TP25 NV_RE#_WRB0
    BC30 TP26 NV_RE#_WRB1 BA2 Set to Vcc when HIGH
    BE32
    TP27
    NV_CLE
    BJ32 TP28 NV_WE#_CK0 AT12 Set to Vss when LOW
    Boot BIOS Strap bit1 BBS1 A16 swap overide Strap/Top-Block BC28
    TP29 NV_WE#_CK1
    BF3
    Swap Override jumper BE30
    TP30 USB DEBUG=PORT1 AND PORT9
    Boot BIOS BF32 +1.8VS
    TP31 USB20_N0
    Destination Low=A16 swap BG32 TP32 USBP0N C24 USB20_N0 [43]
    Bit11 Bit10 override/Top-Block AV26 A24 USB20_P0 RIGHT USB
    TP33 USBP0P USB20_P0 [43]

    1
    PCI_GNT3# Swap Override enabled BB26 C25 USB20_N1 6/24 change to 1K
    C TP34 USBP1N USB20_P1 USB20_N1 [38] C
    0 1 Reserved High=Default * AU28 TP35 USBP1P B25 USB20_P1 [38] LEFT USB USB charger R216
    GNT1#/ AY30 C26 USB20_N2 1K_0402_5%
    TP36 USBP2N USB20_P2 USB20_N2 [42]
    GPIO51 1 0 Reserved AU26
    TP37 USBP2P
    A26 USB20_P2 [42] LEFT USB
    AY26 K28 USB20_N3
    USB20_N3 [42]

    2
    TP38 USBP3N USB20_P3 NV_CLE
    1 1 * SPI (Default) AV28 TP39 USBP3P H28 USB20_P3 [42] LEFT USB (COMBO) 2 1 H_SNB_IVB# [6]
    AW30 E28 R217 4.7K_0402_5%
    TP40 USBP4N
    0 0 LPC USBP4P D28
    C28 USB20_N5 CLOSE TO THE BRANCHING POINT
    USBP5N USB20_P5 USB20_N5 [31]
    USBP5P A28 USB20_P5 [31] USB Camera
    C29
    USBP6N
    USBP6P B29
    PCI_PIRQA# K40 N28
    PCI_PIRQB# PIRQA# USBP7N
    6/23 Reserve for GPU? K38 M28

    PCI
    PCI_PIRQC# PIRQB# USBP7P USB20_N8
    H38 L30
    PCI_PIRQD# PIRQC# USBP8N USB20_P8
    G38 K30
    @ PIRQD# USBP8P USB20_N9
    G30 USB20_N9 [34]
    PE_GPIO0 PCH_GPIO50 USBP9N USB20_P9 +3VALW
    1 2 C46 E30 WLAN R01

    USB
    [15] PE_GPIO0 REQ1# / GPIO50 USBP9P USB20_P9 [34]
    R553 0_0402_5% PCH_GPIO52 C44 C30 USB20_N10
    REQ2# / GPIO52 USBP10N USB20_N10 [43]
    PE_GPIO1 1 2 PCH_GPIO54 E40 A30 USB20_P10 07/16 FOR PIWG4 EXT USB RP3
    [15,25,26,52] PE_GPIO1 REQ3# / GPIO54 USBP10P USB20_N11 USB20_P10 [43] USB_OC0#
    R691 0_0402_5% L32 CARD READER 4 5
    PCH_GPIO51 USBP11N USB20_P11 USB20_N11 [43] USB_OC2#
    @ D47 K32 3 6
    GNT1# / GPIO51 USBP11P USB20_P11 [43]
    PCH_GPIO53 E42 G32 USB_OC7# 2 7
    WL_OFF# GNT2# / GPIO53 USBP12N USB_OC5#
    [34] WL_OFF# F46 E32 1 8
    GNT3# / GPIO55 USBP12P USB20_N13
    C32 USB20_N13 [42]
    USBP13N USB20_P13 10K_1206_8P4R_5%
    GPIO53=This Signal has a weak internal pull-up. PCH_GPIO2 USBP13P
    A32 USB20_P13 [42] Bluetooth
    G42
    NOTE: The internal pull-up is disabled after ODD_DA# @ PCH_GPIO3 PIRQE# / GPIO2
    [40,56] ODD_DA# 1 2
    PCH_GPIO4
    G40 PIRQF# / GPIO3 USBRBIAS
    Within 500 mils
    PLTRST# deasserts. 0_0402_5% R715 C42 C33 1 2
    PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R218 22.6_0402_1% RP4
    D44
    PIRQH# / GPIO5 USB_OC1# 4 5
    B33 USB_OC4# 3 6
    USBRBIAS USB_OC3#
    [40] PCI_PME# K10 2 7
    B PME# USB_OC6# B
    1 8
    PLT_RST# C6 A14 USB_OC0#
    [6] PLT_RST# PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# [38,43]
    K20 10K_1206_8P4R_5%
    OC1# / GPIO40 USB_OC2# USB_OC1# [42]
    R219 22_0402_5% B17
    CLK_PCI_LPBACK_R H49 OC2# / GPIO41 USB_OC3#
    [15] CLK_PCI_LPBACK 1 2 C16
    CLK_PCI_LPC_R CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#
    [40] CLK_PCI_LPC 1 2 H43 L16
    R220 22_0402_5% CLKOUT_PCI1 OC4# / GPIO43 USB_OC5#
    J48 A16
    CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
    K42 D14
    CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
    H40 C14
    CLKOUT_PCI4 OC7# / GPIO14

    COUGARPOINT_FCBGA989

    7/12 For DIS only


    1 2
    R690 2 DIS@ 1 R222 0_0402_5%
    0_0402_5%
    1 R487 2 +3VGS
    10K_0402_5% +3VGS

    MC74VHC1G08DFT2G SC70 5P
    D27

    3
    R693 @ @
    5

    PE_GPIO0 1 2 2 1 VGA_RST# U12 1 PLT_RST#

    G
    PLT_RST# @ R682 A
    2 4
    P

    B [34,35,40] BUF_PLT_RST# Y
    CH751H-40PT_SOD323-2 0_0402_5% 4 VGA_RST#_R 2 1 2
    Y VGA_RST# [23] B

    P
    PE_GPIO0 1 0_0402_5%
    A
    G

    1
    7/12 Reserve for BACO suggestion 1 U7

    5
    NC7SZ08P5X_NL_SC70-5 @ @ R684 1U_0402_6.3V4Z
    3

    100K_0402_5% C208 R223


    @ 100K_0402_5%
    A 2 +3VS A
    2

    2
    R741 @
    7/12 U12 Reserve from module design
    PE_GPIO0 2 1 VGA_RST#

    0_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    7/12 Reserve for PX3.0 Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (5/9) PCI, USB
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 18 of 57
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    PCH_GPIO69 PCH_GPIO70 PCH_GPIO71 Function

    R702 R703 R704


    0 0 0 UMA

    2
    10K_0402_5%

    10K_0402_5%

    10K_0402_5%
    1 0 0 DIS *

    1
    PCH_GPIO69
    0 1 0 PX3.0 @ @
    PCH_GPIO70
    D D
    1 1 0 PX4.0 PCH_GPIO71 R707 R705 R706

    2
    10K_0402_5%

    10K_0402_5%

    10K_0402_5%
    +3VS R233 1 2 10K_0402_5% PCH_GPIO0

    U4F
    ICC_EN# ESATA_DET# 1 @ 2
    Integrated Clock Chip Enable 0_0402_5% R303 T7 C40 PCH_GPIO68

    1
    BMBUSY# / GPIO0 TACH4 / GPIO68
    H ; Disable 7/22 update to reserve only R227 1 2 10K_0402_5% A42 B41 PCH_GPIO69 @
    L ; Enable TACH1 / GPIO1 TACH5 / GPIO69
    * +3VS R228 1 2 10K_0402_5% PCH_GPIO6 H36
    TACH2 / GPIO6 TACH6 / GPIO70
    C41 PCH_GPIO70 +3VS
    @ 6/23 update for MB ID
    R235 1 2 1K_0402_5% EC_SMI# EC_SCI# E38 A40 PCH_GPIO71
    [40] EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71

    2
    [40] EC_SMI# EC_SMI# C10 R236
    GPIO8
    Weak internal pull-high 10K_0402_5%
    R229 1 @ 2 10K_0402_5% CPUSB# C4
    +3VALW LAN_PHY_PWR_CTRL / GPIO12

    1
    R230 1 2 1K_0402_5% PCH_GPIO15 G2 P4
    GPIO15 A20GATE GATEA20 [40] +3VS
    GPIO28 AU16 PCH_PECI_R 1 @ 2

    CPU/MISC
    PCH_GPIO16 PECI H_PECI [6,40] PCH_GPIO68 R224
    On-Die PLL Voltage Regulator +3VS R231 1 2 10K_0402_5% U2 SATA4GP / GPIO16
    0_0402_5% R237 1 2 10K_0402_5%
    This signal has a weak internal pull up P5 KB_RST#

    ：：On-Die
    RCIN# KB_RST# [40] KB_RST#
    [42] ESATA_DET# R542 1 2 0_0402_5% R226 1 2 10K_0402_5%

    GPIO
    H voltage regulator enable R232 2 10K_0402_1% GPIO17
    * L On-Die PLL Voltage Regulator disable
    +3VS 1 D40 TACH0 / GPIO17 PROCPWRGD AY11 H_CPUPWRGD [6]
    R238 1 2 10K_0402_5% PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
    +3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# [6]
    R240 1 @ 2 1K_0402_5% PCH_GPIO28 R239 390_0402_5%
    7/22 update to used ODD_EN E8 T14
    +3VALW [38] ODD_EN GPIO24 / MEM_LED INIT3_3V#
    intel function INIT3_3V
    PCH_GPIO27 E16
    C GPIO27 C
    R241 This signal has weak internal
    1 2 10K_0402_5% PCH_GPIO28 P8 PU, can't pull low
    GPIO28
    [42] BT_OFF# AH8
    @ BT_OFF# NC_1
    +3VS 1 2 10K_0402_5% K1 STP_PCI# / GPIO34
    R242 AK11
    PCH_GPIO35 NC_2
    PCH_GPIO27 (Have internal Pull-High) R243 1 2 10K_0402_5% K4
    GPIO35
    AH10
    *High: VCCVRM VR Enable
    Low: VCCVRM VR Disable
    PCH_GPIO36 V8
    SATA2GP / GPIO36
    NC_3

    NC_4 AK10 Intel schematic reviwe recommand.


    R244 1 2 10K_0402_5% PCH_GPIO37 M5
    +3VS SATA3GP / GPIO37
    NC_5 P37
    R245 1 @ 2 10K_0402_5% PCH_GPIO27 R246 1 2 10K_0402_5% PCH_GPIO38 N2
    SLOAD / GPIO38
    R247 1 2 10K_0402_5% PCH_GPIO39 M3
    SDATAOUT0 / GPIO39
    R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2 @ T15 PAD
    SDATAOUT1 / GPIO48 VSS_NCTF_15
    R249 1 2 10K_0402_5% ESATA_DET#_R V3 BG48 @ T16 PAD
    +3VS SATA5GP / GPIO49 VSS_NCTF_16
    PCH_GPIO57 D6 BH3 @ T17 PAD
    R250 1 @ PCH_GPIO36 GPIO57 VSS_NCTF_17
    +3VS 2 10K_0402_5%
    BH47 @ T18 PAD
    R251 VSS_NCTF_18
    +3VALW 1 2 10K_0402_5%
    1 R547 2 10K_0402_5% PAD T19 @ A4 BJ4 @ T20 PAD
    VSS_NCTF_1 VSS_NCTF_19
    7/22 update to used intel function
    PAD T21 @ A44 BJ44 @ T22 PAD
    VSS_NCTF_2 VSS_NCTF_20
    PAD T23 @ @ T24 PAD
    R01 A45
    VSS_NCTF_3 VSS_NCTF_21
    BJ45

    NCTF
    PAD T25 @ A46 BJ46 @ T26 PAD
    VSS_NCTF_4 VSS_NCTF_22
    PAD T27 @ A5 BJ5 @ T28 PAD
    B VSS_NCTF_5 VSS_NCTF_23 B
    PAD T29 @ A6 BJ6 @ T30 PAD
    VSS_NCTF_6 VSS_NCTF_24
    PAD T31 @ B3 C2 @ T32 PAD
    VSS_NCTF_7 VSS_NCTF_25
    PAD T33 @ B47 C48 @ T34 PAD
    VSS_NCTF_8 VSS_NCTF_26
    PAD T35 @ BD1 D1 @ T36 PAD
    VSS_NCTF_9 VSS_NCTF_27
    PAD T37 @ BD49 D49 @ T38 PAD
    VSS_NCTF_10 VSS_NCTF_28
    PAD T39 @ BE1 E1 @ T40 PAD
    VSS_NCTF_11 VSS_NCTF_29
    PAD T41 @ BE49 E49 @ T42 PAD
    VSS_NCTF_12 VSS_NCTF_30
    PAD T43 @ BF1 F1 @ T44 PAD
    VSS_NCTF_13 VSS_NCTF_31
    PAD T45 @ BF49 F49 @ T46 PAD
    VSS_NCTF_14 VSS_NCTF_32

    COUGARPOINT_FCBGA989

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (6/9) GPIO, CPU, MISC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 19 of 57
    5 4 3 2 1
    5 4 3 2 1

    PCH Power Rail Table


    +1.05VS U4G POWER +3VS S0 Iccmax
    L1 Voltage Rail Voltage Current (A)
    @ PJP1 1300mA MBK1608221YZF_2P
    +1.05VS_PCH +VCCADAC
    2 1 AA23
    AC23
    VCCCORE[1] 1mA VCCADAC
    U48 2 1 R01 V_PROC_IO 1.05 0.001
    VCCCORE[2] 1 1 1 1

    1U_0402_6.3V6K
    C210

    1U_0402_6.3V6K
    C211

    1U_0402_6.3V6K
    C212

    0.01U_0402_16V7K
    C213

    0.1U_0402_10V7K
    C214
    CRT
    AD21 C215 C395 @
    PAD-OPEN 4x4m 1 1 1 1 VCCCORE[3]

    10U_0603_6.3V6M
    C209
    AD23 U47 10U_0805_6.3V6M 10U_0805_6.3V6M
    VCCCORE[4] VSSADAC
    V5REF 5 0.001

    VCC CORE
    AF21
    VCCCORE[5] 2 2 2 2
    AF23 VCCCORE[6]
    D 2 2 2 2 AG21 R252 +3VS D
    VCCCORE[7]
    AG23 VCCCORE[8]
    0.022_0805_1% V5REF_Sus 5 0.001
    AG24 AK36 +VCCA_LVDS 1 2
    VCCCORE[9] 1mA VCCALVDS PX@
    AG26
    VCCCORE[10]

    1
    AG27
    VCCCORE[11] VSSALVDS
    AK37 Vcc3_3 3.3 0.266
    AG29 DIS@
    VCCCORE[12] R253
    AJ23

    LVDS
    VCCCORE[13]
    AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 0_0402_5% VccADAC 3.3 0.001
    AJ27 +1.8VS

    2
    VCCCORE[15] L2 PX@
    AJ29 AM38
    VCCCORE[16] VCCTX_LVDS[2]
    AJ31 VCCCORE[17]
    0.1UH_MLF1608DR10KT_10%_1608 VccADPLLA 1.05 0.08
    +1.05VS_PCH AP36 +VCCTX_LVDS 2 1
    60mA VCCTX_LVDS[3] 0.1uH inductor, 200mA
    1 1 1

    1
    22U_0805_6.3V6M
    C218
    VCCTX_LVDS[4]
    AP37 VccADPLLB 1.05 0.08
    R254 2 1 0_0603_5% +1.05VS_VCCDPLLEXP AN19 C216 C217 DIS@
    VCCIO[28] 0.01U_0402_16V7K 0.01U_0402_16V7K PX@ R255
    2 PX@ 2 PX@ 2 0_0402_5% VccCore 1.05 1.3
    PAD T47 @ +VCCAPLLEXP BJ22 R256 +3VS

    2
    VCCAPLLEXP 0_0805_5%
    This pin can be left as no connect in V33 +3VS_VCC3_3_6 1 2 VccDMI 1.05 0.042

    HVCMOS
    VCC3_3[6]
    AN16
    On-Die VR enabled mode (default). VCCIO[15]
    1
    AN17 VCCIO[16]
    VccIO 1.05 2.925
    V34 C219
    VCC3_3[7]
    0.1U_0402_10V7K
    2 VccASW 1.05 1.01
    AN21 VCCIO[17]
    @ J12
    2 1 AN26
    VCCIO[18]
    VccSPI 3.3 0.02
    AN27 2925mA AT16 +VCCAFDI_VRM
    PAD-OPEN 4x4m VCCIO[19] VCCVRM[3]
    +1.05VS_PCH AP21 +VCCP_VCCDMI +1.05VS VccDSW 3.3 0.003
    C VCCIO[20] R258 C
    @
    1 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2
    VCCIO[21] VCCDMI[1]
    1 VccpNAND 1.8 0.19

    DMI
    +1.05VS_PCH
    1U_0402_6.3V6K
    C222

    1U_0402_6.3V6K
    C223

    1U_0402_6.3V6K
    C224

    1U_0402_6.3V6K
    C225

    R257 0_0805_5% 1 1 1 1 1 AP24 R259 0_0805_5%

    VCCIO
    VCCIO[22]
    10U_0805_6.3V6M
    C221

    0_0805_5% C220
    AP26 AB36 +1.05VS_VCC_DMI_CCI 1 2 1U_0402_6.3V6K VccRTC 3.3 6 uA
    VCCIO[23] 20mA VCCIO[1] 2
    2 2 2 2 2 1
    AT24
    VCCIO[24] C226 VccSus3_3 3.3 0.119
    1U_0402_6.3V6K
    AN33 2
    VCCIO[25]
    VccSusHDA 3.3 / 1.5 0.01
    AN34 VCCIO[26] VCCPNAND[1] AG16
    +3VS R260 +VCCPNAND R261 +1.8VS
    0_0805_5% 0_0805_5% VccVRM 1.8 / 1.5 0.16

    NAND / SPI
    1 2 +3VS_VCCA3GBG BH29 AG17 1 2
    VCC3_3[3] 190mA VCCPNAND[2]
    1
    C227 VccCLKDMI 1.05 0.02
    0.1U_0402_10V7K AJ16 1
    VCCPNAND[3] C228
    2 +VCCAFDI_VRM AP16 0.1U_0402_10V7K VccSSC 1.05 0.095
    +1.05VS_PCH @ R262 VCCVRM[2]
    AJ17
    VCCPNAND[4] 2
    0_0603_5% Place CH53 Near BG6 pin
    2 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
    VCCFDIPLL
    +1.05VS_PCH R263
    1
    1 2 +1.05VS_VCCDPLL_FDI AP17 VCCIO[27]
    VccALVDS 3.3 0.001
    FDI

    @C229
    @ C229 0_0805_5% V1 +3V_VCCPSPI 1 R399 2
    20mA VCCSPI +3VS
    1U_0402_6.3V6K 0_0805_5%
    2 AU20 VccTX_LVDS 1.8 0.06
    +VCCP_VCCDMI VCCDMI[2] 1
    C230
    R01
    B COUGARPOINT_FCBGA989 1U_0402_6.3V6K B
    2

    +VCCAFDI_VRM
    +1.5VS

    R265 2 1 0_0603_5% +VCCAFDI_VRM

    +1.8VS

    R266 2 @ 1 0_0603_5%

    Intel recommand VCCVRM==>1.5V FOR MOBILE


    stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
    VCCVRM = 160mA detal waiting for newest spec

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (7/9) PWR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 20 of 57
    5 4 3 2 1
    5 4 3 2 1

    Have internal VRM


    +3VS +1.05VS_PCH @ R268
    @ R267 VCC3_3 = 266mA detal waiting for newest spec
    0_0805_5% 0_0603_5%
    1 2 2 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
    L3
    10UH_LBR2012T100M_20%
    +3VS_VCC_CLKF33 +3VALW R269
    1 2
    1 1 0_0603_5% U4J POWER R270 +1.05VS_PCH

    10U_0805_10V4Z
    C231

    1U_0402_6.3V6K
    C232
    1 2 +VCCPDSW 0_0603_5%
    1 AD49 N26 +1.05VS_VCCUSBCORE 2 1
    VCCACLK VCCIO[29]
    2 2
    7/1 update to @ 1
    C234 P26
    0.1U_0402_10V7K VCCIO[30] C233
    T16 VCCDSW3_3 3mA
    D @ C235 2 P28 1U_0402_6.3V6K D
    0.1U_0402_10V7K VCCIO[31] 2
    2 1 +PCH_VCCDSW V12 T27
    DCPSUSBYP VCCIO[32]
    T29
    +3VS_VCC_CLKF33 VCCIO[33] R272 +3VALW
    T38 VCC3_3[5]
    +1.05VS_PCH @ R271 @ L4 0_0603_5%
    0_0603_5% 10UH_LBR2012T100M_20% T23 +3V_VCCPUSB 2 1
    1 2 +VCCAPLL_CPY 1 2 +VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7]
    VCCAPLLDMI2 +3VALW

    0.1U_0402_10V7K
    C236
    T24 1 R273
    R274 +VCCDPLL_CPY VCCSUS3_3[8] +5VALW +3VALW
    1 +1.05VS_PCH 1 2 0_0603_5% AL29 VCCIO[14]
    0_0603_5%
    V23 +3V_VCCAUBG 2 1

    USB
    VCCSUS3_3[9]

    C237
    10U_0805_6.3V6M
    1

    2
    @ +VCCSUS1 AL24 V24 2 C238
    2 DCPSUS[3] VCCSUS3_3[10] 0.1U_0402_10V7K R275 D1
    1
    P24 100_0402_5% CH751H-40PT_SOD323-2
    @ C239 VCCSUS3_3[6] 2 R276 +1.05VS_PCH
    1U_0402_6.3V6K AA19 0_0603_5%

    1
    2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
    VCCIO[34] T26 2 1
    +1.05VS_PCH R277 AA21 1010mA
    VCCASW[2] 1
    0_0805_5%
    1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
    VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
    1 1 2

    22U_0805_6.3V6M
    C241

    22U_0805_6.3V6M
    C242

    Clock and Miscellaneous


    AA26 @
    VCCASW[4] +VCCA_USBSUS C243
    AN23 1 2 1U_0402_6.3V6K
    DCPSUS[4]
    AA27 VCCASW[5]
    2 2 AN24 +3V_VCCPSUS
    VCCSUS3_3[1]
    AA29
    VCCASW[6]
    AA31 +5VS +3VS
    VCCASW[7]
    AC26 P34 +PCH_V5REF_RUN R278 +3VALW
    VCCASW[8] 1mA V5REF

    2
    C 0_0603_5% C
    1 1 1

    1U_0402_6.3V6K
    C244

    1U_0402_6.3V6K
    C245

    1U_0402_6.3V6K
    C246
    AC27 2 1 R279 D2
    VCCASW[9] +3V_VCCPSUS 100_0402_5% CH751H-40PT_SOD323-2
    N20 1
    VCCSUS3_3[2]

    PCI/GPIO/LPC
    AC29 C247
    2 2 2 VCCASW[10] 1U_0402_6.3V
    N22

    1
    +1.05VS_PCH VCCSUS3_3[3] +PCH_V5REF_RUN
    AC31
    R280 L5 VCCASW[11] 2 R281 +3VS
    VCCSUS3_3[4] P20 1
    0_0805_5% 10UH_LB2012T100MR_20% AD29 0_0805_5%
    +VCCA_DPLL_L +1.05VS_VCCA_A_DPL VCCASW[12] C248
    1 2 1 2 VCCSUS3_3[5] P22 2 1
    AD31 1 1U_0603_10V6K
    VCCASW[13] C249 2
    1 2 +1.05VS_VCCA_B_DPL W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
    L6 VCCASW[14] VCC3_3[1]
    2 +3VS
    220U_B2_2.5VM_R35
    C250

    1U_0402_6.3V6K
    C251

    220U_B2_2.5VM_R35
    C252

    1U_0402_6.3V6K
    C253

    10UH_LB2012T100MR_20% 1 1 W23 W16 R282


    VCCASW[15] VCC3_3[8] 0_0603_5%
    1 1
    + + W24 T34 +3VS_VCCPPCI 2 1
    VCCASW[16] VCC3_3[4]
    1
    W26 C254
    2 2 2 2 VCCASW[17] 0.1U_0402_10V7K
    W29 R283 +3VS
    VCCASW[18] 0_0603_5% 2
    W31 AJ2 +VCC3_3_2 2 1
    R284 VCCASW[19] VCC3_3[2] +1.05VS_SATA3 R285 +1.05VS_PCH
    1
    0_0603_5% W33 0_0805_5%
    +VCCDIFFCLK VCCASW[20] C255
    +1.05VS_PCH 2 1 AF13 2 1
    VCCIO[5] 0.1U_0402_10V7K
    2 1
    1 +VCCRTCEXT N16
    C256 DCPRTC C257
    1 AH13
    1U_0402_6.3V6K C258 VCCIO[12] 1U_0402_6.3V6K
    0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
    R286 2 VCCVRM[4] VCCIO[13]
    0_0603_5% +1.05VS_VCCDIFFCLKN 2
    B
    2 1 +1.05VS_VCCDIFFCLKN AF14 L7 @ @ R287 +1.05VS_PCH B
    +1.05VS_PCH VCCIO[6]
    1 +1.05VS_VCCA_A_DPL BD47 10UH_LB2012T100MR_20% 0_0805_5%

    SATA
    VCCADPLLA 80mA +VCCSATAPLL +VCCSATAPLL_R2
    AK1 1 2 1
    C259 +1.05VS_VCCA_B_DPL VCCAPLLSATA +VCCAFDI_VRM
    BF47
    1U_0402_6.3V6K VCCADPLLB 80mA
    2 1
    AF11 +VCCAFDI_VRM @ C260
    R288 +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA R289 +1.05VS_PCH 10U_0805_6.3V6M
    AF17
    VCCIO[7]
    0_0603_5% AF33
    VCCIO[8]
    0_0805_5% Place CH80 Near AK1 pin
    2 1 +1.05VS_SSCVCC AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2
    +1.05VS_PCH VCCIO[9] VCCIO[2]
    1 +1.05VS_VCCDIFFCLKN AG34 VCCIO[11]
    VCCIO[3] AC17 1
    C262 C261
    1U_0402_6.3V6K +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
    2 VCCIO[10] 95mA VCCIO[4]
    @ R290 2
    0_0603_5% +VCCSST V16 +1.05VS_PCH
    +1.05VM_VCCSUS DCPSST
    +1.05VS_PCH 2 1 1

    1 C263 +1.05VM_VCCSUS T17 T21 +VCCME_22 R291 2 1 0_0603_5%


    0.1U_0402_10V7K DCPSUS[1] VCCASW[22]
    V19
    DCPSUS[2]
    MISC

    C264 @ 2
    1U_0402_6.3V6K +1.05VS R293 V21 +VCCME_23 R292 2 1 0_0603_5%
    2 0_0603_5% VCCASW[23]
    CPU

    +V_CPU_IO
    R01 1 2 BJ8 V_PROC_IO 1mA
    T19 +VCCME_21 R294 2 1 0_0603_5%
    VCCASW[21]
    1 1 1
    +RTCVCC +3VALW
    4.7U_0603_6.3V6K
    C265

    0.1U_0402_10V7K
    C266

    0.1U_0402_10V7K
    C267

    RTC

    A22 P32 +VCCSUSHDA R295 2 1 0_0603_5%


    HDA

    2 2 2 VCCRTC 10mA VCCSUSHDA


    1U_0402_6.3V6K
    C268

    0.1U_0402_10V7K
    C269

    0.1U_0402_10V7K
    C270

    1 1 1 1
    COUGARPOINT_FCBGA989 C271
    A 0.1U_0402_16V4Z A

    2 2 2 2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    2010/07/12 2012/07/11 Title
    Issued Date Deciphered Date PCH (8/9) PWR
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 21 of 57
    5 4 3 2 1
    5 4 3 2 1

    U4I

    AY4 VSS[159] VSS[259] H46


    AY42 K18
    VSS[160] VSS[260]
    AY46 VSS[161] VSS[261] K26
    AY8 K39
    VSS[162] VSS[262]
    B11 VSS[163] VSS[263] K46
    D U4H D
    B15 VSS[164] VSS[264] K7
    H5 VSS[0] B19 VSS[165] VSS[265] L18
    B23 VSS[166] VSS[266] L2
    AA17 AK38 B27 L20
    VSS[1] VSS[80] VSS[167] VSS[267]
    AA2 AK4 B31 L26
    VSS[2] VSS[81] VSS[168] VSS[268]
    AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
    AA33 AK46 B39 L36
    VSS[4] VSS[83] VSS[170] VSS[270]
    AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
    AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
    AB14 AL17 BB12 P16
    VSS[7] VSS[86] VSS[173] VSS[273]
    AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
    AB4 AL2 BB20 M22
    VSS[9] VSS[88] VSS[175] VSS[275]
    AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
    AB5 AL23 BB24 M30
    VSS[11] VSS[90] VSS[177] VSS[277]
    AB7 AL26 BB28 M32
    VSS[12] VSS[91] VSS[178] VSS[278]
    AC19 AL27 BB30 M34
    VSS[13] VSS[92] VSS[179] VSS[279]
    AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
    AC21 AL33 BB4 M4
    VSS[15] VSS[94] VSS[181] VSS[281]
    AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
    AC33 AL48 BC14 M46
    VSS[17] VSS[96] VSS[183] VSS[283]
    AC34 AM11 BC18 M8
    VSS[18] VSS[97] VSS[184] VSS[284]
    AC48 AM14 BC2 N18
    VSS[19] VSS[98] VSS[185] VSS[285]
    AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
    AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
    AD12 AM43 BC32 P11
    VSS[22] VSS[101] VSS[188] VSS[288]
    AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
    AD19 AM46 BC36 T33
    VSS[24] VSS[103] VSS[190] VSS[290]
    AD24 AM7 BC40 P40
    VSS[25] VSS[104] VSS[191] VSS[291]
    AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
    AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
    AD33 AN3 BD46 P7
    VSS[28] VSS[107] VSS[194] VSS[294]
    AD34 AN31 BD5 R2
    C VSS[29] VSS[108] VSS[195] VSS[295] C
    AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
    AD37 AP19 BE26 T12
    VSS[31] VSS[110] VSS[197] VSS[297]
    AD38 AP28 BE40 T31
    VSS[32] VSS[111] VSS[198] VSS[298]
    AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
    AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
    AD40 AP38 BF16 W34
    VSS[35] VSS[114] VSS[201] VSS[301]
    AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
    AD43 AP42 BF22 T47
    VSS[37] VSS[116] VSS[203] VSS[303]
    AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
    AD46 AP8 BF26 V11
    VSS[39] VSS[118] VSS[205] VSS[305]
    AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
    AE2 AR48 BD3 V26
    VSS[41] VSS[120] VSS[207] VSS[307]
    AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
    AF10 AT13 BF38 V29
    VSS[43] VSS[122] VSS[209] VSS[309]
    AF12 AT18 BF40 V31
    VSS[44] VSS[123] VSS[210] VSS[310]
    AD14 AT22 BF8 V36
    VSS[45] VSS[124] VSS[211] VSS[311]
    AD16 AT26 BG17 V39
    VSS[46] VSS[125] VSS[212] VSS[312]
    AF16 AT28 BG21 V43
    VSS[47] VSS[126] VSS[213] VSS[313]
    AF19 AT30 BG33 V7
    VSS[48] VSS[127] VSS[214] VSS[314]
    AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
    AF26 AT34 BG8 W19
    VSS[50] VSS[129] VSS[216] VSS[316]
    AF27 AT39 BH11 W2
    VSS[51] VSS[130] VSS[217] VSS[317]
    AF29 AT42 BH15 W27
    VSS[52] VSS[131] VSS[218] VSS[318]
    AF31 AT46 BH17 W48
    VSS[53] VSS[132] VSS[219] VSS[319]
    AF38 AT7 BH19 Y12
    VSS[54] VSS[133] VSS[220] VSS[320]
    AF4 AU24 H10 Y38
    VSS[55] VSS[134] VSS[221] VSS[321]
    AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
    AF46 AV16 BH31 Y42
    VSS[57] VSS[136] VSS[223] VSS[323]
    AF5 AV20 BH33 Y46
    VSS[58] VSS[137] VSS[224] VSS[324]
    AF7 AV24 BH35 Y8
    VSS[59] VSS[138] VSS[225] VSS[325]
    AF8 AV30 BH39 BG29
    VSS[60] VSS[139] VSS[226] VSS[328]
    AG19 AV38 BH43 N24
    B VSS[61] VSS[140] VSS[227] VSS[329] B
    AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
    AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
    AG48 AV8 D12 B43
    VSS[64] VSS[143] VSS[230] VSS[333]
    AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
    AH3 AW18 D18 BG41
    VSS[66] VSS[145] VSS[232] VSS[335]
    AH36 AW2 D22 G14
    VSS[67] VSS[146] VSS[233] VSS[337]
    AH39 AW22 D24 H16
    VSS[68] VSS[147] VSS[234] VSS[338]
    AH40 AW26 D26 T36
    VSS[69] VSS[148] VSS[235] VSS[340]
    AH42 AW28 D30 BG22
    VSS[70] VSS[149] VSS[236] VSS[342]
    AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
    AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
    AJ19 AW36 D38 AP13
    VSS[73] VSS[152] VSS[239] VSS[345]
    AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
    AJ24 AW48 D8 AP3
    VSS[75] VSS[154] VSS[241] VSS[347]
    AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
    AJ34 AY12 E26 BE16
    VSS[77] VSS[156] VSS[243] VSS[349]
    AK12 AY22 G18 BC16
    VSS[78] VSS[157] VSS[244] VSS[350]
    AK3 AY28 G20 BG28
    VSS[79] VSS[158] VSS[245] VSS[351]
    G26 BJ28
    COUGARPOINT_FCBGA989 VSS[246] VSS[352]
    G28
    VSS[247]
    G36
    VSS[248]
    G48 VSS[249]
    H12
    VSS[250]
    H18 VSS[251]
    H22
    VSS[252]
    H24
    VSS[253]
    H26 VSS[254]
    H30
    VSS[255]
    H32
    VSS[256]
    H34
    VSS[257]
    F3
    VSS[258]
    A A

    COUGARPOINT_FCBGA989

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PCH (9/9) VSS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 22 of 57
    5 4 3 2 1
    5 4 3 2 1

    PCIE_CTX_GRX_P[15..0] U8A VGA@ PCIE_CRX_GTX_P[15..0]


    [5] PCIE_CTX_GRX_P[15..0] PCIE_CRX_GTX_P[15..0] [5]
    U8F
    PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] R296VGA@
    [5] PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] [5]
    1 2
    R01 10K_0402_5%
    LVDS CONTROL AB11
    VARY_BL VGA_ENVDD
    DIGON AB12 VGA_ENVDD [31]
    PCIE_CTX_GRX_P0 AF30 PCIE_RX0P PCIE_TX0P AH30 PCIE_CRX_C_GTX_P0 0.1U_0402_10V7K
    2 1 VGA@
    C273 PCIE_CRX_GTX_P0
    PCIE_CTX_GRX_N0 AE31 AG31 PCIE_CRX_C_GTX_N0 2 1 VGA@ PCIE_CRX_GTX_N0 1 2
    PCIE_RX0N PCIE_TX0N 0.1U_0402_10V7K C272 R297VGA@
    D 10K_0402_5% D
    PCIE_CTX_GRX_P1 AE29 PCIE_RX1P PCIE_TX1P AG29 PCIE_CRX_C_GTX_P1 0.1U_0402_10V7K
    2 1 VGA@
    C274 PCIE_CRX_GTX_P1
    TXCLK_UP_DPF3P AH20 VGA_LVDS_BCLK [31]
    PCIE_CTX_GRX_N1 AD28 AF28 PCIE_CRX_C_GTX_N1 2 1 VGA@ PCIE_CRX_GTX_N1 AJ19
    PCIE_RX1N PCIE_TX1N TXCLK_UN_DPF3N VGA_LVDS_BCLK# [31]
    0.1U_0402_10V7K C275
    TXOUT_U0P_DPF2P AL21 VGA_LVDS_B0 [31]
    PCIE_CTX_GRX_P2 AD30 PCIE_RX2P PCIE_TX2P AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_10V7K
    2 1 VGA@
    C276 PCIE_CRX_GTX_P2
    TXOUT_U0N_DPF2N AK20 VGA_LVDS_B0# [31] R01
    PCIE_CTX_GRX_N2 AC31 AF26 PCIE_CRX_C_GTX_N2 2 1 VGA@ PCIE_CRX_GTX_N2
    PCIE_RX2N PCIE_TX2N 0.1U_0402_10V7K C277
    TXOUT_U1P_DPF1P
    TXOUT_U1N_DPF1N
    AH22
    AJ21
    VGA_LVDS_B1 [31]
    VGA_LVDS_B1# [31]
    07/16
    PCIE_CTX_GRX_P3 AC29 PCIE_RX3P PCIE_TX3P AD27 PCIE_CRX_C_GTX_P3 0.1U_0402_10V7K
    2 1 VGA@
    C278 PCIE_CRX_GTX_P3
    PCIE_CTX_GRX_N3 AB28 AD26 PCIE_CRX_C_GTX_N3 2 1 VGA@ PCIE_CRX_GTX_N3 AL23
    PCIE_RX3N PCIE_TX3N TXOUT_U2P_DPF0P VGA_LVDS_B2 [31]
    0.1U_0402_10V7K C279 AK22
    TXOUT_U2N_DPF0N VGA_LVDS_B2# [31]
    1 VGA@

    PCI EXPRESS INTERFACE


    PCIE_CTX_GRX_P4 AB30 AC25 PCIE_CRX_C_GTX_P4 0.1U_0402_10V7K
    2 C280 PCIE_CRX_GTX_P4 AK24
    PCIE_CTX_GRX_N4 PCIE_RX4P PCIE_TX4P TXOUT_U3P
    AA31 PCIE_RX4N PCIE_TX4N AB25 PCIE_CRX_C_GTX_N4 2 1 VGA@ PCIE_CRX_GTX_N4
    TXOUT_U3N AJ23
    0.1U_0402_10V7K C281
    For PIWG4(17") Dual channel Use
    PCIE_CTX_GRX_P5 AA29 PCIE_RX5P PCIE_TX5P Y23 PCIE_CRX_C_GTX_P5 0.1U_0402_10V7K
    2 1 VGA@
    C282 PCIE_CRX_GTX_P5 LVTMDP
    PCIE_CTX_GRX_N5 Y28 Y24 PCIE_CRX_C_GTX_N5 2 1 VGA@ PCIE_CRX_GTX_N5
    PCIE_RX5N PCIE_TX5N 0.1U_0402_10V7K C283
    TXCLK_LP_DPE3P AL15 VGA_LVDS_ACLK [31]
    TXCLK_LN_DPE3N AK14 VGA_LVDS_ACLK# [31]
    PCIE_CTX_GRX_P6 Y30 PCIE_RX6P PCIE_TX6P AB27 PCIE_CRX_C_GTX_P6 0.1U_0402_10V7K
    2 1 VGA@
    C284 PCIE_CRX_GTX_P6
    PCIE_CTX_GRX_N6 W31 AB26 PCIE_CRX_C_GTX_N6 2 1 VGA@ PCIE_CRX_GTX_N6 AH16
    PCIE_RX6N PCIE_TX6N TXOUT_L0P_DPE2P VGA_LVDS_A0 [31]
    0.1U_0402_10V7K C285 AJ15
    C TXOUT_L0N_DPE2N VGA_LVDS_A0# [31] C

    PCIE_CTX_GRX_P7 W29 PCIE_RX7P PCIE_TX7P Y27 PCIE_CRX_C_GTX_P7 0.1U_0402_10V7K


    2 1 VGA@
    C286 PCIE_CRX_GTX_P7
    TXOUT_L1P_DPE1P AL17 VGA_LVDS_A1 [31]
    PCIE_CTX_GRX_N7 V28 Y26 PCIE_CRX_C_GTX_N7 2 1 VGA@ PCIE_CRX_GTX_N7 AK16
    PCIE_RX7N PCIE_TX7N TXOUT_L1N_DPE1N VGA_LVDS_A1# [31]
    0.1U_0402_10V7K C287
    TXOUT_L2P_DPE0P AH18 VGA_LVDS_A2 [31]
    PCIE_CTX_GRX_P8 V30 PCIE_RX8P PCIE_TX8P W24 PCIE_CRX_C_GTX_P8 0.1U_0402_10V7K
    2 1 VGA@
    C288 PCIE_CRX_GTX_P8
    TXOUT_L2N_DPE0N AJ17 VGA_LVDS_A2# [31]
    PCIE_CTX_GRX_N8 U31 W23 PCIE_CRX_C_GTX_N8 2 1 VGA@ PCIE_CRX_GTX_N8
    PCIE_RX8N PCIE_TX8N 0.1U_0402_10V7K C289
    TXOUT_L3P AL19
    TXOUT_L3N AK18
    PCIE_CTX_GRX_P9 U29 PCIE_RX9P PCIE_TX9P V27 PCIE_CRX_C_GTX_P9 0.1U_0402_10V7K
    2 1 VGA@
    C290 PCIE_CRX_GTX_P9
    PCIE_CTX_GRX_N9 T28 U26 PCIE_CRX_C_GTX_N9 2 1 VGA@ PCIE_CRX_GTX_N9
    PCIE_RX9N PCIE_TX9N 0.1U_0402_10V7K C291

    PCIE_CTX_GRX_P10 T30 PCIE_RX10P PCIE_TX10P U24 PCIE_CRX_C_GTX_P10 0.1U_0402_10V7K


    2 1 VGA@
    C292 PCIE_CRX_GTX_P10 216-0774207-A11ROB_FCBGA631 VGA@
    PCIE_CTX_GRX_N10 R31 U23 PCIE_CRX_C_GTX_N10 2 1 VGA@ PCIE_CRX_GTX_N10
    PCIE_RX10N PCIE_TX10N 0.1U_0402_10V7K C293

    PCIE_CTX_GRX_P11
    PCIE_CTX_GRX_N11
    R29
    P28
    PCIE_RX11P
    PCIE_RX11N
    PCIE_TX11P
    PCIE_TX11N
    T26
    T27
    PCIE_CRX_C_GTX_P11
    PCIE_CRX_C_GTX_N11
    0.1U_0402_10V7K
    2
    2
    1 VGA@
    C294
    1 VGA@
    PCIE_CRX_GTX_P11
    PCIE_CRX_GTX_N11 LVDS
    0.1U_0402_10V7K C295

    PCIE_CTX_GRX_P12 P30 PCIE_RX12P PCIE_TX12P T24 PCIE_CRX_C_GTX_P12 0.1U_0402_10V7K


    2 1 VGA@
    C296 PCIE_CRX_GTX_P12
    PCIE_CTX_GRX_N12 N31 T23 PCIE_CRX_C_GTX_N12 2 1 VGA@ PCIE_CRX_GTX_N12
    PCIE_RX12N PCIE_TX12N 0.1U_0402_10V7K C297
    B B

    PCIE_CTX_GRX_P13 N29 PCIE_RX13P PCIE_TX13P P27 PCIE_CRX_C_GTX_P13 0.1U_0402_10V7K


    2 1 VGA@
    C298 PCIE_CRX_GTX_P13
    PCIE_CTX_GRX_N13 M28 P26 PCIE_CRX_C_GTX_N13 2 1 VGA@ PCIE_CRX_GTX_N13
    PCIE_RX13N PCIE_TX13N 0.1U_0402_10V7K C299

    PCIE_CTX_GRX_P14 M30 PCIE_RX14P PCIE_TX14P P24 PCIE_CRX_C_GTX_P14 0.1U_0402_10V7K


    2 1 VGA@
    C300 PCIE_CRX_GTX_P14
    PCIE_CTX_GRX_N14 L31 P23 PCIE_CRX_C_GTX_N14 2 1 VGA@ PCIE_CRX_GTX_N14
    PCIE_RX14N PCIE_TX14N 0.1U_0402_10V7K C301

    PCIE_CTX_GRX_P15 L29 PCIE_RX15P PCIE_TX15P M27 PCIE_CRX_C_GTX_P15 0.1U_0402_10V7K


    2 1 VGA@
    C302 PCIE_CRX_GTX_P15
    PCIE_CTX_GRX_N15 K30 N26 PCIE_CRX_C_GTX_N15 2 1 VGA@ PCIE_CRX_GTX_N15
    PCIE_RX15N PCIE_TX15N 0.1U_0402_10V7K C303

    @ CLOCK
    T48 PAD
    CLK_PCIE_VGA
    [15] CLK_PCIE_VGA AK30 PCIE_REFCLKP
    CLK_PCIE_VGA# AK32
    [15] CLK_PCIE_VGA# PCIE_REFCLKN
    @ T49 PAD
    CALIBRATION
    VGA_PWRGD Y22 1.27K_0402_1% 1 VGA@ 2 R298
    [25] VGA_PWRGD PCIE_CALRP
    2 R299 1 N10 PWRGOOD PCIE_CALRN AA22 2K_0402_5% 1 VGA@ 2 R300 +1.0VGS VGA 0609
    A 10K_0402_5% A
    VGA@
    [18] VGA_RST# AL27 PERSTB
    Security Classification Compal Secret Data Compal Electronics, Inc.
    216-0774207-A11ROB_FCBGA631 2010/07/12 2012/07/11 Title
    Issued Date Deciphered Date
    RobsonXT-S3 PCIE/LVDS
    PCIE LANE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
    Document Number Rev
    0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 23 of 57
    5 4 3 2 1
    5 4 3 2 1

    Transmitter Power Saving Enable U8B CONFIGURATION STRAPS RECOMMENDED SETTINGS


    TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
    1: full Tx output swing (Default setting for Desktop) 1 = INSTALL 10K RESISTOR
    GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
    PCI Express Transmitter De-emphasis Enable TXCAP_DPA3P
    AF2 VGA_HDMI_CLK+ [33] NA = NOT APPLICABLE
    TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode TXCAM_DPA3N
    AF4 VGA_HDMI_CLK- [33]
    1: Tx de-emphasis enabled (Defailt setting for desktop) T52 Y11
    T53 DVCLK RECOMMENDED
    AE9 AG3 VGA_HDMI_TX0+ [33]
    T54 DVCNTL_0 TX0P_DPA2P STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
    L9 AG5 VGA_HDMI_TX0- [33] SETTINGS
    T55 DVCNTL_1 DVO DPA TX0M_DPA2N
    N9
    DVCNTL_2
    AH3 VGA_HDMI_TX1+ [33]
    T50 TX1P_DPA1P TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING X
    AE8 AH1 VGA_HDMI_TX1- [33]
    T56 DVDATA_12 TX1M_DPA1N
    AD9
    T57 DVDATA_11
    AC10 AK3 VGA_HDMI_TX2+ [33]
    +1.8VGS +DPC_VDD18 T51 DVDATA_10 TX2P_DPA0P TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED X
    AD7 AK1 VGA_HDMI_TX2- [33]
    L8 VGA@ T58 DVDATA_9 TX2M_DPA0N
    150mA +DPC_VDD18 T59
    AC8
    DVDATA_8
    2 1 AC7 AK5
    BLM15BD121SN1D_0402 T60 DVDATA_7 TXCBP_DPB3P RSVD GPIO2 RESERVED 0
    AB9 AM3
    10U_0603_6.3V6M

    1U_0402_6.3V4Z

    0.1U_0402_10V6K
    D
    T61 DVDATA_6 TXCBM_DPB3N D
    C304

    C305

    C306
    1 1 1 AB8
    T62 DVDATA_5
    AB7 AK6
    T70 DVDATA_4 TX3P_DPB2P RSVD GPIO8 RESERVED 0
    AB4 AM5
    VGA@ VGA@ VGA@ VRAM_ID2 DVDATA_3 DPB TX3M_DPB2N
    [29] VRAM_ID2 AB2
    2 2 2 VRAM_ID1 DVDATA_2
    [29] VRAM_ID1 Y8 AJ7
    VRAM_ID0 DVDATA_1 TX4P_DPB1P BIF_VGA DIS GPIO9 VGA ENABLED 0
    [29] VRAM_ID0 Y7 AH6
    DVDATA_0 TX4M_DPB1N
    AK8
    TX5P_DPB0P RSVD GPIO21 RESERVED 0
    AL7
    TX5M_DPB0N

    +DPC_VDD18 +DPC_VDD18 W6 DPC BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM X


    DPC_PVDD
    V6
    +1.0VGS +DPC_VDD10 DPC_PVSS
    V4
    L9
    VGA@ +DPC_VDD18 TXCCP_DPC3P ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
    110mA +DPC_VDD10 +DPC_VDD18 AC6
    DPC_VDD18#1 TXCCM_DPC3N
    U5
    2 1 AC5
    BLM15BD121SN1D_0402 DPC_VDD18#2
    W3
    10U_0603_6.3V6M

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    +DPC_VDD10 TX0P_DPC2P VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0


    C307

    C308

    C309

    1 1 1 +DPC_VDD10 AA5 V2
    DPC_VDD10#1 TX0M_DPC2N
    AA6
    DPC_VDD10#2
    Y4
    VGA@ VGA@ VGA@ TX1P_DPC1P RSVD H2SYNC 0
    W5
    2 2 2 TX1M_DPC1N
    U1 AA3
    DPC_VSSR#1 TX2P_DPC0P RSVD GENERICC 0
    W1 Y2
    DPC_VSSR#2 TX2M_DPC0N VGA@
    U3
    DPC_VSSR#3
    Y6 J8 1 R305 2 AUD[1] AUD[0]
    DPC_VSSR#4 DPC_CALR 150_0402_1% VGA_CRT_R AUD[1] HSYNC 11
    AA1 0 0 No audio function
    DPC_VSSR#5
    0 1 Audio for DisplayPort and HDMI if dongle is detected
    VGA_CRT_G AUD[0] VSYNC 1 0 Audio for DisplayPort only
    1 1 Audio for both DisplayPort and HDMI
    VGA_CRT_B

    R318 1

    R320 1

    R541 1
    +3VGS I2C
    AMD RESERVED CONFIGURATION STRAPS

    150_0402_1%

    150_0402_1%

    150_0402_1%
    @ 1R306 4.7K_0402_5%
    2 VGA_SMB_CK2_R VGA_SMB_CK2_R R1 VGA@ ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
    @ SCL
    1R307 4.7K_0402_5%
    2 VGA_SMB_DA2_R VGA_SMB_DA2_R R3
    SDA RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND

    2
    AM26 VGA_CRT_R
    GENERAL PURPOSE I/O R VGA_CRT_R [32] NOT CONFLICT DURING RESET
    C AK26 C
    GPU_GPIO0 RB
    U6 VGA@ VGA@
    GPU_GPIO1 GPIO_0 VGA_CRT_G GPIO21 H2SYNC GENERICC GPIO2 GPIO8
    U10 AL25 VGA_CRT_G [32]
    GPU_GPIO2 GPIO_1 G
    T10 AJ25
    GPIO_2 GB
    U8
    VGA@ D3 GPIO_3_SMBDATA VGA_CRT_B
    U7 AH24 VGA_CRT_B [32]
    GPU_GPIO5 GPIO_4_SMBCLK B +AVDD +1.8VGS
    1 2 T9 AG25
    @
    [16,40,47] ACIN
    RB751V_SOD323 T8
    GPIO_5_AC_BATT
    GPIO_6
    DAC1 BB
    65mA VGA@ L10 STRAPS +3VGS
    1 R662 2 VGA_ENBKL VGA_ENBKL T7 AH26 VGA_HSYNC +AVDD 1 2
    [31] VGA_ENBKL GPIO_7_BLON HSYNC VGA_HSYNC [32]
    10K_0402_5% GPU_GPIO8 P10 AJ27 VGA_VSYNC BLM15BD121SN1D_0402 GPU_GPIO0 R309 2 @ 1 10K_0402_5%

    10U_0603_6.3V6M
    0.1U_0402_10V6K

    1U_0402_6.3V4Z
    GPIO_8_ROMSO VSYNC VGA_VSYNC [32]
    GPU_GPIO9 GPU_GPIO1 R310 2 VGA@ 10K_0402_5%

    C310

    C311

    C312
    P4 1 1 1 1
    GPIO_9_ROMSI VGA@ GPU_GPIO2 R311
    P2 2 VGA@ 1 10K_0402_5%
    GPU_GPIO11 GPIO_10_ROMSCK +3VGS
    N6 AD22 1 R312 2 VGA@ GPU_GPIO5 R308 2 @ 1 10K_0402_5%
    GPU_GPIO12 GPIO_11 RSET 499_0402_1%
    N5
    GPU_GPIO13 GPIO_12 +AVDD +AVDD 2 2 2 GPU_GPIO8 R313 @
    N3 AG24 R01 2 1 10K_0402_5%
    GPIO_13 AVDD GPU_GPIO9 R314 @
    Y9 AE22 2 1 10K_0402_5%
    GPIO_14_HPD2 AVSSQ

    1
    GPU_VID0 N1
    [52] GPU_VID0 GPIO_15_PWRCNTL_0

    1
    T63 M4 AE23 +VDD1DI +VDD1DI R548 R549 VGA@ VGA@ GPU_GPIO11 R315 2 VGA@ 1 10K_0402_5%
    THM_ALERT# GPIO_16_SSIN VDD1DI 10K_0402_5% GPU_GPIO12 R316 @
    R6 AD23 10K_0402_5% 2 1 10K_0402_5%
    VGA@ GPIO_17_THERMAL_INT VSS1DI VGA@ GPU_GPIO13 R317 @
    W10 VGA@ 2 1 10K_0402_5%
    R319 1 10K_0402_5% GPIO_18_HPD3 +VDD1DI +1.8VGS
    2 M2

    2
    GPU_VID1 GPIO_19_CTF L11
    [52] GPU_VID1 P8 AM12 110mA

    2
    GPIO_20_PWRCNTL_1 R2 VGA_HSYNC +VDD1DI
    P7 AK12 1 2
    GPIO_21_BB_EN R2B VGA_VSYNC BLM15BD121SN1D_0402
    N8

    10U_0603_6.3V6M
    0.1U_0402_10V6K

    1U_0402_6.3V4Z
    PEG_CLKREQ# GPIO_22_ROMCSB VGA@ +3VGS

    C313

    C314

    C315
    [15] PEG_CLKREQ# N7 AL11 1 1 1
    +3VGS GPIO_23_CLKREQB G2
    AJ11
    GPIO24_TRSTB G2B VGA@ VGA@
    L6
    VGA@ 1 R321 JTAG_TRSTB
    2 10K_0402_5% GPIO24_TRSTB GPIO25_TDI L5 AK10 VGA_HDMI_SCL R714 2DIS_HDMI@1 10K_0402_5%
    VGA@ 1 R322 GPIO25_TDI GPIO26_TCK JTAG_TDI B2 2 2 2 VGA_HDMI_SDA
    2 10K_0402_5% L3 AL9 R713 2DIS_HDMI@1 10K_0402_5%
    VGA@ 1 R323 GPIO27_TMS GPIO27_TMS JTAG_TCK B2B VGA_LVDS_SCL
    2 10K_0402_5% L1 R712 2 DIS@ 1 10K_0402_5%
    T64 GPIO28_TDO JTAG_TMS VGA_LVDS_SDA R711
    K4 2 DIS@ 1 10K_0402_5%
    VGA@ 1 R324 GPIO26_TCK TEST_EN K7 JTAG_TDO VGA_DDCCLK
    2 10K_0402_5% 2 1 AH12 VGA@ R621 2 DIS@ 1 10K_0402_5%
    R326 10K_0402_5% T65 TESTEN C VGA_DDCDATA R426
    AF24 AM10 2 DIS@ 1 10K_0402_5%
    VGA@ TESTEN_LEGACY Y
    AJ9
    COMP +VDD2DI VGA@ +1.8VGS
    DAC2 L12
    AB13
    GENERICA +VDD2DI
    2mA
    W8 AL13 1 2
    +1.8VGS +DPLL_PVDD GENERICB H2SYNC BLM15BD121SN1D_0402
    W9 AJ13

    10U_0603_6.3V6M
    1U_0402_6.3V4Z
    0.1U_0402_10V6K
    B
    L14 VGA@ GENERICC V2SYNC +3VGS B

    C316

    C317

    C318
    75mA +DPLL_PVDD
    W7
    GENERICD 1 1 1
    2 1 AD10
    BLM15BD121SN1D_0402 GENERICE_HPD4
    AD19 +VDD2DI +VDD2DI VGA@ VGA@
    10U_0603_6.3V6M

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    VDD2DI
    C323

    C324

    C325

    1 1 1 [33] HDMI_DETECT_VGA AC14 AC19


    PX_EN HPD1 VSS2DI 2 2 2 +3VGS
    [25] PX_EN AB16
    PX_EN

    1
    VGA@ VGA@ VGA@
    VGA@ 1 R613 2 VGA@ AE20 +A2VDD +A2VDD R327 R328
    2 2 2 4.7K_0402_5% A2VDD VGA@ 10K_0402_5% 10K_0402_5%
    0.60 V level, Please AE17 +A2VDDQ +A2VDDQ
    A2VDDQ

    2
    VGA@
    VREFG Divider ans

    2
    +1.8VGS AE19 +A2VDD +3VGS
    VGA@ cap close to ASIC A2VSSQ L13 VGA_SMB_CK2_R
    100mA 1 6 EC_SMB_CK2 [15,37,40]
    2 R329 1 499_0402_1% +VREFG_GPU AC16 VGA@ +A2VDD 1 2
    VREFG

    5
    +1.0VGS +DPLL_VDDC VGA@ AG13 1 R330 2 BLM15BD121SN1D_0402 VGA@ Q64A

    10U_0603_6.3V6M
    0.1U_0402_10V6K

    1U_0402_6.3V4Z
    L16 VGA@ R2SET
    2 R331 1 249_0402_1% 715_0402_1% VGA@ 2N7002DW-T/R7_SOT363-6

    C319

    C320

    C321
    125mA +DPLL_VDDC 1 1 1
    VGA_SMB_DA2_R
    2 1 4 3 EC_SMB_DA2 [15,37,40]
    BLM15BD121SN1D_0402 2 1 VGA@ VGA@
    10U_0603_6.3V6M

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    C322 0.1U_0402_10V6K DDC/AUX VGA_HDMI_SCL Q64B VGA@


    C330

    C331

    C332

    1 1 1 AE6 VGA_HDMI_SCL [33]


    VGA@ PLL/CLOCK DDC1CLK VGA_HDMI_SDA 2 2 2 2N7002DW-T/R7_SOT363-6
    AE5
    VGA@ VGA@ +DPLL_PVDD DDC1DATA VGA_HDMI_SDA [33]
    +DPLL_PVDD AF14
    DPLL_PVDD
    AE14 AD2
    2 2 2 DPLL_PVSS AUX1P VGA@
    AD4
    AUX1N +3VGS
    VGA@ +DPLL_VDDC +DPLL_VDDC AD14 AC11 VGA_LVDS_SCL
    DPLL_VDDC DDC2CLK VGA_LVDS_SCL [31] +A2VDDQ +1.8VGS
    AC13 VGA_LVDS_SDA

    XTALIN XTALIN AM28


    DDC2DATA
    AD13
    VGA_LVDS_SDA [31]
    130mA
    +A2VDDQ 1
    L15
    2
    VGA@ 2
    C329
    VGA Thermal Sensor
    +1.8VGS @ +TSVDD XTALOUT XTALIN AUX2P BLM15BD121SN1D_0402 0.1U_0402_16V4Z
    Voltage Swing: 1.8 V AK28 AD11
    EMC1402-1 Closed to GPU

    10U_0603_6.3V6M
    0.1U_0402_10V6K

    1U_0402_6.3V4Z
    L17 VGA@ XTALOUT AUX2N VGA@

    C326

    C327

    C328
    20mA +TSVDD
    1 1 1 1
    2 1 2 R332 10_0402_5% AC22 AD20
    BLM18AG121SN1D_0603 XO_IN DDCCLK_AUX3P
    2 R333 10_0402_5% AB22 AC20 VGA@ VGA@ U9 VGA@
    10U_0603_6.3V6M

    1U_0402_6.3V4Z

    0.1U_0402_16V4Z

    VGA@ XO_IN2 DDCDATA_AUX3N VGA_SMB_CK2_R


    C334

    C335

    C336

    1 1 1 1 8
    2 2 2 VDD SCLK
    AE16
    DDCCLK_AUX5P GPU_THERMAL_D+ VGA_SMB_DA2_R
    AD16 2 7
    DDCDATA_AUX5N D+ SDATA
    2 2 2 AC1 VGA_DDCCLK VGA@ 1 2 3 6
    DDC6CLK VGA_DDCCLK [32] D- ALERT#
    @

    GPU_THERMAL_D+ T4 THERMAL AC3 VGA_DDCDATA VGA@ C333


    L17 VGA@ GPU_THERMAL_D- DPLUS DDC6DATA VGA_DDCDATA [32] 2200P_0402_50V7K THM_ALERT#
    A T2 4 5 A
    DMINUS GPU_THERMAL_D- THERM# GND
    VGA@ R334 2.61K_0402_5%
    +3VGS 1 2 R5 +3VGS 1 R335 2 EMC1402-2-ACZL-TR MSOP 8P 2 R336 1 +3VGS
    VGA@ +TSVDD TS_FDO 4.7K_0402_5%
    +TSVDD AD17
    XTALOUT R337 XTALIN TSVDD @ 4.7K_0402_5%
    AC17 VGA@
    1M_0603_5% TSVSS EMC1412-A (SA00003YA00)
    0_0603 5%
    Address 1111_100xb
    SD013000080 Y3 VGA@ S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
    2 1 216-0774207-A11ROB_FCBGA631

    27MHZ_16PF_X5H027000FG1H VGA@
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
    VGA@ C337 C338 VGA@
    18P_0402_50V8J 18P_0402_50V8J
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    RobsonXT-S3 Main Generic/MSIC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 24 of 57
    5 4 3 2 1
    5 4 3 2 1

    @ 0_0402_5%
    [52] VGA_CORE_PG 1 2 VGA_PWRGD VGA_PWRGD [23]
    R689
    R01
    VGA_CORE_PG +3VGS +5VS +5VS
    D D

    1
    0.1U_0402_10V6K
    R338

    1
    BACO@
    10K_0402_5%

    C339
    1 R339 BACO@
    10K_0402_5%

    2
    BACO@ VDDC_ON#

    2
    2 1.0V_ON#
    BACO@

    5
    +3VGS 1 R612 2 U10

    1
    10K_0402_5% BACO@ D D
    2

    P
    R692 B
    @ Q66 Q67
    PX_MODE Y 4 2 2
    +3VS 1 R340 2 1 2 1 A
    G 2N7002_SOT23 G 2N7002_SOT23

    G
    S BACO@ S BACO@

    3
    @ 10K_0402_5% 0_0402_5% MC74VHC1G08DFT2G SC70 5P

    3
    1

    1
    D
    1 2 2 Q68
    R01 C382 C386
    [24] PX_EN
    R341 G 2N7002_SOT23 0.1U_0402_10V6K @ 0.1U_0402_10V6K
    0_0402_5% S BACO@ 1 2 2 @
    +3VGS
    3

    C
    BACO@ C
    U37 BSS138_NL_SOT23-3 BSS138_NL_SOT23-3

    5
    +1.0VGS +BIF_VDDC +VGA_CORE

    D
    R01 2 3 1 1 3

    S
    P
    B PX_MODE
    Y 4 PX_MODE [26,52]
    +3VGS 1 Q69 Q70
    A

    G
    C731 VGA@ VGA@

    G
    1 2

    G
    2

    0.1U_0402_10V6K
    1 2 BACO@ 1.0V_ON# R342

    BACO@ C343
    @ MC74VHC1G08DFT2G SC70 5P 1 0_0402_5%
    1

    BACO@ 0.1U_0402_10V6K PX3@


    R872 BSS138_NL_SOT23-3
    20K_0402_5% Q71 VGA@
    5

    BACO@ +VGA_CORE 2

    D
    1 NC 3 1 1 3

    S
    P
    2

    @ 4 RUNPWROK
    PE_GPIO1 1 Y Q72
    [15,18,26,52] PE_GPIO1 2 2 A
    G

    D28 U40 VGA@

    G
    2

    2
    CH751H-40PT_SOD323-2 SN74LVC1G07DCKR_SC70-5 VDDC_ON#
    3

    1 BSS138_NL_SOT23-3
    Add when verify BACO
    C732
    1U_0603_10V4Z
    2 2 1
    @
    @R873
    B 0_0402_5% 7/28 modify to N-MOS follow Spec B

    D28 with leakage need to check

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PARK-S3 Main Generic/MSIC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 25 of 57
    5 4 3 2 1
    5 4 3 2 1

    EVT Short J2 for DIS only +1.8VS J5 @ +1.8VGS


    +1.8VS TO +1.8VGS 2 1
    D 2MM D
    +VGA_PCIE +1.0VGS
    +VGA_PCIE TO +1.0VGS @ U13 VGA@
    2 1 10U_0805_10V4Z 1U_0603_10V4Z 8 1
    D S
    1 1 7 2 1 1
    D S

    1
    2MM J2 VGA@ 6
    C346
    1
    C375
    1
    C368 R664 C348 D S 3 C349 VGA@ C350 VGA@
    U14 5 4
    10U_0805_10V4Z VGA@ VGA@ VGA@ 470_0603_5% 10U_0805_10V4Z D G 10U_0805_10V4Z 1U_0603_10V4Z R348
    8 D S 1
    2 7 2 2 SI4800BDY-T1-E3_SO8 2 2 470_0603_5%
    D S 2 2 @ +VSB @
    6 3

    1 2

    1 2
    D S
    5 D G 4
    D D

    1
    SI4800BDY-T1-E3_SO8 2 VGA@ 2
    R01 @ G G
    Q75 330K_0402_5% Q76
    S R01 S

    3
    2N7002_SOT23 R350 2N7002_SOT23
    +VSB @ VGA@ @

    2
    1 R352 2
    VGA@ 0_0402_5% 0_0402_5%

    2
    R640 1 2 1 @ 0_0402_5%

    1
    R687 VGA@ D R354 C352 VGA@ PE_GPIO1# 1 2
    VGA@ @ 0_0402_5% PE_GPIO1# 1 2 2 Q78 VGA@ 0_0402_5% 0.1U_0603_25V7K R678
    20K_0402_5% PE_GPIO1# 1 R673 G 2N7002_SOT23 @
    2
    2
    1 VGA@ R683 0_0402_5% S

    1
    1

    0_0402_5% D VGA@ C730


    PE_GPIO1# 1 2 2 Q85 0.1U_0603_25V7K
    R671 G 2N7002_SOT23
    VGA@ S 2
    3

    C C

    +1.5V +1.5VGS
    +1.5VS TO +1.5VGS
    2 1

    2MM J3 @
    +3.3VS TO +3.3VGS +3VS +3VGS U11 VGA@
    @ 8
    10U_0805_10V4Z 1U_0603_10V4Z D S 1
    2 1 7
    1 D S 2 1 1

    1
    6 C341 VGA@ C342 VGA@
    D S 3
    1

    2MM J4 VGA@ C340 5 10U_0805_10V4Z 1U_0603_10V4Z R343


    1
    C376
    1
    C377 R686 10U_0805_10V4Z D G 4 470_0603_5%
    2 2 2
    S

    VGA@ VGA@ 470_0603_5% SI4800BDY-T1-E3_SO8 @


    D

    3 1
    @

    1 2
    SI2301BDS-T1-E3_SOT23-3 Q65 2 2
    2

    +5VALW VGA@ +VSB D


    G
    2

    2
    1

    D G
    2 R344 VGA@ S Q73

    3
    VGA@ VGA@ G 20K_0402_5% 2N7002_SOT23
    R641 R688 S Q77 R01 @
    3

    2N7002_SOT23 PX3@ 0_0402_5% R345


    20K_0402_5% 20K_0402_5% @ PE_GPIO1# 1 2 1 VGA@ 2 @ 0_0402_5%

    2
    R674 200K_0402_1% 1 PE_GPIO1# 1 2

    1
    D
    1 VGA@ @ 0_0402_5% @ 0_0402_5% R346 R680
    1

    0_0402_5% D VGA@ C351 PE_GPIO1# 1 PX_MODE# Q74 VGA@ 0_0402_5% C344 VGA@ @ 0_0402_5%
    2 1 2 2
    B PE_GPIO1 1 Q86 0.1U_0603_25V7K R685 R677 G 2N7002_SOT23 @ 0.1U_0603_25V7K PX_MODE# 1 B
    2 2 2
    R672 G 2N7002_SOT23 S 2 R681

    1
    VGA@ S 2
    3

    Add when verify BACO

    0_0402_5%
    1 2 PE_GPIO1
    [10,40,44,49,51,52] SUSP#
    R744
    VGA@
    +3VALW
    +3VALW
    1
    1

    VGA@
    VGA@ R676
    R718 100K_0402_5%
    100K_0402_5%
    2
    2

    PX_MODE# PE_GPIO1#
    VGA@
    Q121
    1

    D VGA@ DTC124EKAT146_SC59-3
    PX_MODE 2 Q87
    OUT

    [25,52] PX_MODE
    G 2N7002_SOT23
    1

    S
    3

    @ PE_GPIO1 2
    [15,18,25,52] PE_GPIO1 IN
    R719
    GND

    100K_0402_5%
    2

    A A
    3

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PARK-S3 Main Generic/MSIC
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 26 of 57
    5 4 3 2 1
    5 4 3 2 1

    +1.8VGS +DPEF_VDD18 +DPAB_VDD18 +1.8VGS

    VGA@ L18
    total:440mA@LVDS VGA@ L19
    total:300mA@DP VGA@
    total:300mA
    2 1 2 1

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    C353

    C354

    C355

    C357

    C358

    C359
    0.1U_0402_10V6K

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    MBK1608121YZF_0603 1 1 1 1 1 1 MBK1608121YZF_0603
    D D
    VGA@ VGA@ U8G VGA@
    2 2 2 DP E/F POWER DP A/B POWER 2 2 2
    130mA
    +1.0VGS AG15 AE11 +DPAB_VDD18
    VGA@ DPE_VDD18#1 DPA_VDD18#1 VGA@
    AG16 DPE_VDD18#2 DPA_VDD18#2 AF11
    +DPEF_VDD10 +DPAB_VDD10 +1.0VGS
    total:240mA@LVDS
    VGA@ L20 total:220mA@DP 110mA total:220mA VGA@ L21
    2 1 AG20 DPE_VDD10#1 DPA_VDD10#1 AF6 1 2

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    C356

    C360

    C361

    C362

    C363

    C364
    0.1U_0402_10V6K

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    MBK1608121YZF_0603 1 1 1 AG21 AF7 1 1 1 MBK1608121YZF_0603
    DPE_VDD10#2 DPA_VDD10#2
    VGA@ VGA@ VGA@ VGA@
    AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
    2 2 2 AH14 AE3 2 2 2
    DPE_VSSR#2 DPA_VSSR#2
    AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
    AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
    VGA@ AM18 AH5 VGA@
    DPE_VSSR#5 DPA_VSSR#5
    +DPEF_VDD18 +DPAB_VDD18
    130mA
    AF16 AE13 +DPAB_VDD18
    DPF_VDD18#1 DPB_VDD18#1
    C AG17 DPF_VDD18#2 DPB_VDD18#2 AF13 C

    +DPEF_VDD10 +DPAB_VDD10
    110mA
    AF22 AF8 +DPAB_VDD10
    DPF_VDD10#1 DPB_VDD10#1
    AG22 DPF_VDD10#2 DPB_VDD10#2 AF9

    AF23 DPF_VSSR#1 DPB_VSSR#1 AF10


    AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
    AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
    AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
    AM24 DPF_VSSR#5 DPB_VSSR#5 AM8

    R355 VGA@ VGA@


    2 1 AF17 DPEF_CALR DPAB_CALR AE10 1 R356 2
    150_0402_1% 150_0402_1%
    +DPEF_VDD18 +DPAB_VDD18
    20mA 20mA
    +DPEF_VDD18 AG18 DP PLL POWER AG8 +DPAB_VDD18
    DPE_PVDD DPA_PVDD
    AF19 DPE_PVSS DPA_PVSS AG7

    B +DPEF_VDD18 +DPAB_VDD18 B
    20mA 20mA
    +DPEF_VDD18 AG19 AG10 +DPAB_VDD18
    DPF_PVDD DPB_PVDD
    AF20 DPF_PVSS DPB_PVSS AG11

    216-0774207-A11ROB_FCBGA631

    VGA@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    RobsonXT-S3 DP PWR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 27 of 57
    5 4 3 2 1
    5 4 3 2 1

    +1.5VGS

    2.3A(RMS)/2.8A(Peak)

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    C365

    C366

    C369

    C370

    C371

    C372

    C373

    C374

    C389

    C390

    C391

    C381

    C392
    1 1 1 1 1 1 1 1 1 1 1 1 1

    2 2 2 2 2 2 2 2 2 2 2 2 2
    +PCIE_VDDR +1.8VGS
    504mA VGA@
    L22
    U8D +PCIE_VDDR 2 1 U8E
    VGA@ VGA@ VGA@ VGA@ VGA@ MBK1608121YZF_0603

    10U_0603_6.3V6M
    0.1U_0402_10V6K

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ MEM I/O

    C385

    C387

    C388

    C380
    D 1 1 1 1 D
    PCIE
    H13 AB23 AA27 A3
    VDDR1#1 PCIE_VDDR#1 PCIE_VSS#1 GND#1
    H16 AC23 AB24 A30
    VDDR1#2 PCIE_VDDR#2 2 2 2 2 PCIE_VSS#2 GND#2
    H19 AD24 AB32 AA13
    VDDR1#3 PCIE_VDDR#3 PCIE_VSS#3 GND#3
    J10 AE24 AC24 AA16
    VDDR1#4 PCIE_VDDR#4 PCIE_VSS#4 GND#4
    J23 AE25 AC26 AB10
    VDDR1#5 PCIE_VDDR#5 PCIE_VSS#5 GND#5
    J24 AE26 AC27 AB15
    VDDR1#6 PCIE_VDDR#6 PCIE_VSS#6 GND#6
    J9 AF25 AD25 AB6
    VDDR1#7 PCIE_VDDR#7 +1.0VGS PCIE_VSS#7 GND#7
    K10 AG26 VGA@ VGA@ AD32 AC9
    VDDR1#8 PCIE_VDDR#8 VGA@ VGA@ PCIE_VSS#8 GND#8
    K23 AE27 AD6
    VDDR1#9 PCIE_VSS#9 GND#9
    K24
    K9
    VDDR1#10
    L23
    1920mA AF32
    AG27
    PCIE_VSS#10 GND#10
    AD8
    AE7
    VDDR1#11 PCIE_VDDC#1 PCIE_VSS#11 GND#11
    L11 L24 AH32 AG12

    10U_0603_6.3V6M
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12

    C398

    C399

    C383

    C403

    C384
    L12 L25 1 1 1 1 1 K28 AH10
    +1.8VGS +VDDC_CT VDDR1#13 PCIE_VDDC#3 PCIE_VSS#13 GND#13
    L13 L26 K32 AH28
    VDDR1#14 PCIE_VDDC#4 PCIE_VSS#14 GND#14
    L20 M22 L27 B10
    VGA@ L23 VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
    110mA L21
    VDDR1#16 PCIE_VDDC#6
    N22
    2 2 2 2 2
    M32
    PCIE_VSS#16 GND#16
    B12
    1 2 L22 N23 N25 B14
    BLM15BD121SN1D_0402 VDDR1#17 PCIE_VDDC#7 PCIE_VSS#17 GND#17
    N24 N27 B16
    10U_0603_6.3V6M

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    +3VGS PCIE_VDDC#8 PCIE_VSS#18 GND#18


    C404

    C405

    C408

    1 1 1 R22 P25 B18


    PCIE_VDDC#9 PCIE_VSS#19 GND#19
    T22 P32 B20
    LEVEL PCIE_VDDC#10 PCIE_VSS#20 GND#20
    U22 R27 B22
    TRANSLATION PCIE_VDDC#11 +VGA_CORE PCIE_VSS#21 GND#21
    V22 VGA@ VGA@ VGA@ VGA@ VGA@ T25 B24
    10U_0603_6.3V6M

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    2 2 2 PCIE_VDDC#12 PCIE_VSS#22 GND#22
    17mA
    C409

    C410

    C411
    1 1 1 AA20 T32 B26
    VDD_CT#1 PCIE_VSS#23 GND#23
    AA21
    AB20
    VDD_CT#2
    AA15
    11.8A(RMS)/12.9A(Peak) U25
    U27
    PCIE_VSS#24 GND#24
    B6
    B8
    VDD_CT#3 CORE VDDC#1 PCIE_VSS#25 GND#25
    AB21 N15 V32 C1

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    2 2 2 VDD_CT#4 VDDC#2 PCIE_VSS#26 GND#26

    C413

    C414

    C415

    C416

    C417

    C418

    C419

    C420

    C423

    C424

    C425

    C426
    N17 1 1 1 1 1 1 1 1 1 1 1 1 W25 C32
    VDDC#3 PCIE_VSS#27 GND#27
    VGA@ R13 W26 E28
    VGA@ VGA@ I/O VDDC#4 PCIE_VSS#28 GND#28
    R16 W27 F10
    VDDC#5 PCIE_VSS#29 GND#29
    60mA AA17
    VDDR3#1 VDDC#6
    R18 Y25
    PCIE_VSS#30 GND#30
    F12
    AA18 Y21 2 2 2 2 2 2 2 2 2 2 2 2 Y32 F14
    VDDR3#2 VDDC#7 PCIE_VSS#31 GND#31
    VGA@ VGA@ AB17 T12 F16
    VGA@ VDDR3#3 VDDC#8 GND#32
    AB18 T15 F18
    VGA@ L24 VDDR3#4 VDDC#9 GND#33
    T17 F2
    VDDC#10 GND#34
    1 2 170mA V12
    VDDR4#1 VDDC#11
    T20
    GND#35
    F20
    BLM15BD121SN1D_0402 Y12 U13 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ M6 F22
    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    VDDR4#2 VDDC#12 VGA@ VGA@ VGA@ VGA@ GND#56 GND#36


    C U12 U16 N11 F24 C
    VDDR4#3 VDDC#13 GND#57 GND#37

    POWER
    C429

    C430

    1 1
    AA11
    VDDC#14
    U18
    V21
    7/22 modify N12
    N13
    GND#58 GND#38
    F26
    F6
    VGA@ VGA@ NC#1 VDDC#15 GND#59 GND#39
    AA12 V15 N16 F8
    2 2 V11
    NC#2

    NC#3
    VDDC#16
    VDDC#17
    VDDC#18
    V17
    V20
    N18
    N21
    GND#60
    GND#61
    GND#62
    GND GND#40
    GND#41
    GND#42
    G10
    G27
    U11 Y13 P6 G31
    NC#4 VDDC#19 GND#63 GND#43
    Y16 P9 G8
    VDDC#20 GND#64 GND#44
    Y18 R12 H14
    VDDC#21 GND#65 GND#45
    M11 R15 H17
    VGA@ L25 VDDC#22 GND#66 GND#46
    M12 R17 H2
    MEM CLK VDDC#23 GND#67 GND#47
    1 2 R20 H20
    BLM15BD121SN1D_0402 GND#68 GND#48
    L17 T13 H6
    10U_0603_6.3V6M

    1U_0402_6.3V4Z

    0.1U_0402_10V6K

    NC_VDDRHA GND#69 GND#49


    C446

    C447

    C449

    1 1 1 T16 J27
    +BIF_VDDC GND#70 GND#50
    L16 T18 J31
    +1.8VGS NC_VSSRHA GND#71 GND#51
    T21 K11
    GND#72 GND#52
    T6 K2

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    2 2 2 For Seymour, PCIE_PVDD is PCIE_VDDR. PLL GND#73 GND#53

    C451

    C452
    1 1 U15 K22
    GND#74 GND#54
    AM30 U17 K6
    PCIE_PVDD VGA@ VGA@ GND#75 GND#55
    R21 U20
    BIF_VDDC#1 GND#76
    U21 U9
    +MPV18 BIF_VDDC#2 2 2 GND#77
    75mA L8 NC_MPV18
    V13
    GND#78
    VGA@ V16
    VGA@ L26 VGA@ VGA@ GND#79
    V18
    +SPV18 GND#80
    1 2 75mA H7 SPV18
    Y10
    GND#81
    BLM15BD121SN1D_0402 ISOLATED Y15
    10U_0603_6.3V6M

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    +SPV10 CORE I/O GND#82


    120mAH8 VGA@
    C453

    C454

    C455

    1 1 1 M13 Y17 A32


    SPV10 VDDCI#1 +VDDCI R745 +VGA_CORE GND#83 VSS_MECH#1
    M15 Y20 AM1
    +1.0VGS VDDCI#2 0_0603_5% GND#84 VSS_MECH#2
    J7 M16 R11 AM32
    L28 SPVSS VDDCI#3 GND#85 VSS_MECH#3
    M17 1 2 T11
    2 2 2 VDDCI#4 GND#86
    1 2 M18

    10U_0603_6.3V6M
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    BLM15BD121SN1D_0402 VDDCI#5

    C459

    C460

    C461

    C466
    M20 1 1 1 1
    10U_0603_6.3V6M

    0.1U_0402_10V6K
    1U_0402_6.3V4Z

    VDDCI#6
    C456

    C457

    C458

    1 1 1 M21
    VGA@ VDDCI#7
    N20
    VGA@ VGA@ VDDCI#8 216-0774207-A11ROB_FCBGA631
    2 2 2 2
    VGA@ 2 2 2
    VGA@ VGA@
    VGA@
    B B
    216-0774207-A11ROB_FCBGA631

    VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    RobsonXT-S3 PWR/GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 28 of 57
    5 4 3 2 1
    5 4 3 2 1

    U8C +1.8VGS
    M_DA[63..0]
    [30] M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3 R357 1 X76@ 2 10K_0402_5% VRAM_ID0
    M_MA[13..0] VRAM_ID0 [24]
    M_DA0 K27 K17 M_MA0 R358 1 X76@ 2 10K_0402_5%
    [30] M_MA[13..0] DQA0_0/DQA_0 MAA0_0/MAA_0
    M_DA1 J29 J20 M_MA1 R359 1 X76@ 2 10K_0402_5% VRAM_ID1
    M_DQM[7..0] DQA0_1/DQA_1 MAA0_1/MAA_1 VRAM_ID1 [24]
    M_DA2 H30 H23 M_MA2 R360 1 X76@ 2 10K_0402_5%
    [30] M_DQM[7..0] DQA0_2/DQA_2 MAA0_2/MAA_2
    M_DA3 H32 G23 M_MA3 R361 1 X76@ 2 10K_0402_5% VRAM_ID2
    M_DQS[7..0] DQA0_3/DQA_3 MAA0_3/MAA_3 VRAM_ID2 [24]
    M_DA4 G29 G24 M_MA4 R362 1 X76@ 2 10K_0402_5%
    [30] M_DQS[7..0] DQA0_4/DQA_4 MAA0_4/MAA_4

    MEMORY INTERFACE
    M_DA5 F28 H24 M_MA5
    M_DQS#[7..0] M_DA6 DQA0_5/DQA_5 MAA0_5/MAA_5 M_MA6
    [30] M_DQS#[7..0] F32 DQA0_6/DQA_6 MAA0_6/MAA0_6 J19
    M_DA7 F30 K19 M_MA7
    D M_DA8 DQA0_7/DQA_7 MAA0_7/MAA0_7 M_MA8 D
    C30 DQA0_8/DQA_8 MAA1_0/MAA_8 J14
    M_DA9 F27 K14 M_MA9
    M_DA10 DQA0_9/DQA_9 MAA1_1/MAA_9 M_MA10
    A28 DQA0_10/DQA_10 MAA1_2/MAA_10 J11
    M_DA11 C28 J13 M_MA11 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
    M_DA12 DQA0_11/DQA_11 MAA1_3/MAA_11 M_MA12
    E27 DQA0_12/DQA_12 MAA1_4/MAA_12 H11
    M_DA13 G26 G11 M_BA2
    DQA0_13/DQA_13 MAA1_5/MAA_13/BA2 M_BA2 [30]
    M_DA14 D26 J16 M_BA0 Hynix 512MB
    DQA0_14/DQA_14 MAA1_6/MAA_14/BA0 M_BA0 [30]
    M_DA15 F25 L15 M_BA1 R357 R360 R362
    DQA0_15/DQA_15 MAA1_7/MAA_15/BA1 M_BA1 [30] PN:SA000032460
    M_DA16 A25
    M_DA17 DQA0_16/DQA_16 M_DQM0
    C25 DQA0_17/DQA_17 WCKA0_0/DQMA_0 E32
    M_DA18 E25 E30 M_DQM1 Samsung 512MB
    M_DA19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 M_DQM2
    M_DA20
    D24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 A21
    M_DQM3 PN:SA000035700 R358 R359 R362
    E23 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C21
    M_DA21 F23 E13 M_DQM4
    M_DA22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 M_DQM5
    M_DA23
    D22 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 D12
    M_DQM6
    Hynix 1GB
    M_DA24
    F21 DQA0_23/DQA_23 WCKA1_1/DQMA_6 E3
    M_DQM7 PN:SA00003VS20 R357 R360 R361
    E21 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 F4
    M_DA25 D20
    M_DA26 DQA0_25/DQA_25 M_DQS0
    M_DA27
    F19 DQA0_26/DQA_26 EDCA0_0/RDQSA_0 H28
    M_DQS1
    Samsung 1GB
    M_DA28
    A19 DQA0_27/DQA_27 EDCA0_1/RDQSA_1 C27
    M_DQS2 PN:SA00003MQ20 R358 R359 R361
    D18 DQA0_28/DQA_28 EDCA0_2/RDQSA_2 A23
    M_DA29 F17 E19 M_DQS3
    M_DA30 DQA0_29/DQA_29 EDCA0_3/RDQSA_3 M_DQS4
    A17 DQA0_30/DQA_30 EDCA1_0/RDQSA_4 E15
    C
    M_DA31 C17 D10 M_DQS5 C
    +1.5VGS M_DA32 DQA0_31/DQA_31 EDCA1_1/RDQSA_5 M_DQS6
    E17 DQA1_0/DQA_32 EDCA1_2/RDQSA_6 D6
    +1.5VGS M_DA33 D16 G5 M_DQS7
    M_DA34 DQA1_1/DQA_33 EDCA1_3/RDQSA_7
    F15 DQA1_2/DQA_34
    1

    M_DA35 A15 H27 M_DQS#0


    DQA1_3/DQA_35 DDBIA0_0/WDQSA_0
    1

    VGA@ VGA@ R365 M_DA36 D14 A27 M_DQS#1


    R363 40.2_0402_1% M_DA37 DQA1_4/DQA_36 DDBIA0_1/WDQSA_1 M_DQS#2
    F13 DQA1_5/DQA_37 DDBIA0_2/WDQSA_2 C23
    40.2_0402_1% M_DA38 A13 C19 M_DQS#3
    M_DA39 DQA1_6/DQA_38 DDBIA0_3/WDQSA_3 M_DQS#4
    C13 C15
    2

    M_DA40 DQA1_7/DQA_39 DDBIA1_0/WDQSA_4 M_DQS#5


    E11 E9
    2

    MVREFDA MVREFSA M_DA41 DQA1_8/DQA_40 DDBIA1_1/WDQSA_5 M_DQS#6


    A11 DQA1_9/DQA_41 DDBIA1_2/WDQSA_6 C5
    M_DA42 C11 H4 M_DQS#7
    DQA1_10/DQA_42 DDBIA1_3/WDQSA_7
    1

    VGA@ 1 1 M_DA43 F11


    R364 C467 VGA@ VGA@ R367 C468 VGA@ M_DA44 DQA1_11/DQA_43 VRAM_ODT0
    A9 DQA1_12/DQA_44 ADBIA0/ODTA0 L18 VRAM_ODT0 [30]
    100_0402_1% 0.1U_0402_16V4Z 100_0402_1% 0.1U_0402_16V4Z M_DA45 C9 K16 VRAM_ODT1
    DQA1_13/DQA_45 ADBIA1/ODTA1 VRAM_ODT1 [30]
    M_DA46 F9
    2 2 M_DA47 DQA1_14/DQA_46 M_CLK0
    D8 H26 M_CLK0 [30]
    2

    M_DA48 DQA1_15/DQA_47 CLKA0 M_CLK#0


    E7 DQA1_16/DQA_48 CLKA0B H25 M_CLK#0 [30]
    M_DA49 A7
    M_DA50 DQA1_17/DQA_49 M_CLK1
    C7 DQA1_18/DQA_50 CLKA1 G9 M_CLK1 [30]
    M_DA51 F7 H9 M_CLK#1
    DQA1_19/DQA_51 CLKA1B M_CLK#1 [30]
    M_DA52 A5
    M_DA53 DQA1_20/DQA_52 M_RAS#0
    PARK SCL has different M_DA54
    E5 DQA1_21/DQA_53 RASA0B G22
    M_RAS#1
    M_RAS#0 [30]
    C3 DQA1_22/DQA_54 RASA1B G17 M_RAS#1 [30]
    B recommand M_DA55 E1 B
    M_DA56 DQA1_23/DQA_55 M_CAS#0
    G7 DQA1_24/DQA_56 CASA0B G19 M_CAS#0 [30]
    VGA@ VGA@ R369 M_DA57 G6 G16 M_CAS#1
    DQA1_25/DQA_57 CASA1B M_CAS#1 [30]
    R366 10_0402_1% M_DA58 G1
    DRAM_RST M_DA59 DQA1_26/DQA_58 M_CS#0
    [30] DRAM_RST# 2 1 2 1 G3 DQA1_27/DQA_59 CSA0B_0 H22 M_CS#0 [30]
    M_DA60 J6 J22
    49.9_0402_1% M_DA61 DQA1_28/DQA_60 CSA0B_1
    J1 DQA1_29/DQA_61
    1

    1 M_DA62 J3 G13 M_CS#1


    DQA1_30/DQA_62 CSA1B_0 M_CS#1 [30]
    VGA@ C469 R371 M_DA63 J5 K13
    120P_0402_50V8J VGA@ 4.99K_0402_1% DQA1_31/DQA_63 CSA1B_1
    MVREFDA K26 K20 M_CKE0
    2 +1.5VGS MVREFDA CKEA0 M_CKE0 [30]
    MVREFSA J26 J17 M_CKE1
    M_CKE1 [30]
    2

    R368 VGA@ MVREFSA CKEA1


    1 243_0402_1%
    2 J25 G25 M_WE#0
    MEM_CALRN0 WEA0B M_WE#0 [30]
    1 2 K25 H10 M_WE#1
    MEM_CALRP0 WEA1B M_WE#1 [30]
    R370 VGA@
    243_0402_1%
    MAA1_8 G14
    GDDR5 G20 M_MA13
    DRAM_RST L10 MAA0_8
    DRAM_RST
    1R372@ 51.1_0402_1%
    2 1C470@20.1U_0402_16V4Z K8 CLKTESTA
    1 2 1 2 L7 CLKTESTB
    R373@ 51.1_0402_1% C471@ 0.1U_0402_16V4Z
    A A

    Route 50ohms single-ended/100ohm diff and keep short 216-0774207-A11ROB_FCBGA631 VGA@

    debug only, for clock observation,if not need, Security Classification Compal Secret Data Compal Electronics, Inc.
    DNI. Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    RobsonXT-S3 MEM Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 29 of 57
    5 4 3 2 1
    5 4 3 2 1

    M_DA[63..0]
    [29] M_DA[63..0]
    M_MA[13..0]
    [29] M_MA[13..0]
    M_DQM[7..0]
    [29] M_DQM[7..0]
    M_DQS[7..0]
    [29] M_DQS[7..0]
    M_DQS#[7..0]
    [29] M_DQS#[7..0]

    U19 U20 U18 U21

    VREFC_A1 M9 E4 M_DA22 VREFC_A2 M9 E4 M_DA25 VREFC_A3 M9 E4 M_DA35 VREFC_A4 M9 E4 M_DA52


    VREFD_Q1 VREFCA DQL0 M_DA20 VREFD_Q2 VREFCA DQL0 M_DA28 VREFD_Q3 VREFCA DQL0 M_DA34 VREFD_Q4 VREFCA DQL0 M_DA48
    H2 F8 H2 F8 H2 F8 H2 F8
    H1G S1G VREFDQ DQL1 M_DA19 VREFDQ DQL1 M_DA27 VREFDQ DQL1 M_DA36 VREFDQ DQL1 M_DA54
    F3 F3 F3 F3
    D
    M_MA0 DQL2 M_DA18 M_MA0 DQL2 M_DA31 M_MA0 DQL2 M_DA37 M_MA0 DQL2 M_DA50 D
    N4 F9 N4 F9 N4 F9 N4 F9
    M_MA1 A0 DQL3 M_DA21 M_MA1 A0 DQL3 M_DA24 M_MA1 A0 DQL3 M_DA32 M_MA1 A0 DQL3 M_DA53
    P8 H4 P8 H4 P8 H4 P8 H4
    M_MA2 A1 DQL4 M_DA17 M_MA2 A1 DQL4 M_DA29 M_MA2 A1 DQL4 M_DA38 M_MA2 A1 DQL4 M_DA49
    P4 H9 P4 H9 P4 H9 P4 H9
    M_MA3 A2 DQL5 M_DA23 M_MA3 A2 DQL5 M_DA26 M_MA3 A2 DQL5 M_DA33 M_MA3 A2 DQL5 M_DA55
    N3 G3 N3 G3 N3 G3 N3 G3
    M_MA4 A3 DQL6 M_DA16 M_MA4 A3 DQL6 M_DA30 M_MA4 A3 DQL6 M_DA39 M_MA4 A3 DQL6 M_DA51
    P9 H8 P9 H8 P9 H8 P9 H8
    M_MA5 A4 DQL7 M_MA5 A4 DQL7 M_MA5 A4 DQL7 M_MA5 A4 DQL7
    Hynix Samsung P3
    A5
    P3
    A5
    P3
    A5
    P3
    A5
    H1G@ S1G@ M_MA6 R9 M_MA6 R9 M_MA6 R9 M_MA6 R9
    X7624938L01 X7624938L02 M_MA7 A6 M_DA3 M_MA7 A6 M_DA14 M_MA7 A6 M_DA47 M_MA7 A6 M_DA60
    R3 D8 R3 D8 R3 D8 R3 D8
    M_MA8 A7 DQU0 M_DA1 M_MA8 A7 DQU0 M_DA10 M_MA8 A7 DQU0 M_DA42 M_MA8 A7 DQU0 M_DA58
    T9 C4 T9 C4 T9 C4 T9 C4
    M_MA9 A8 DQU1 M_DA0 M_MA9 A8 DQU1 M_DA15 M_MA9 A8 DQU1 M_DA45 M_MA9 A8 DQU1 M_DA56
    0706 update M_MA10
    R4
    A9 DQU2
    C9
    M_DA5 M_MA10
    R4
    A9 DQU2
    C9
    M_DA11 M_MA10
    R4
    A9 DQU2
    C9
    M_DA41 M_MA10
    R4
    A9 DQU2
    C9
    M_DA61
    L8 C3 L8 C3 L8 C3 L8 C3
    M_MA11 A10/AP DQU3 M_DA6 M_MA11 A10/AP DQU3 M_DA12 M_MA11 A10/AP DQU3 M_DA43 M_MA11 A10/AP DQU3 M_DA63
    update X76 PN M_MA12
    R8
    A11 DQU4
    A8
    M_DA7 M_MA12
    R8
    A11 DQU4
    A8
    M_DA8 M_MA12
    R8
    A11 DQU4
    A8
    M_DA40 M_MA12
    R8
    A11 DQU4
    A8
    M_DA62
    N8 A3 N8 A3 N8 A3 N8 A3
    M_MA13 A12 DQU5 M_DA2 M_MA13 A12 DQU5 M_DA13 M_MA13 A12 DQU5 M_DA46 M_MA13 A12 DQU5 M_DA57
    T4 B9 T4 B9 T4 B9 T4 B9
    A13 DQU6 M_DA4 A13 DQU6 M_DA9 A13 DQU6 M_DA44 A13 DQU6 M_DA59
    T8 A4 T8 A4 T8 A4 T8 A4
    A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
    M8 M8 M8 M8
    H512 S512 A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS

    M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3


    [29] M_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
    M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10
    [29] M_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
    M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8
    [29] M_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
    K3 K3 K3 K3
    VDD VDD VDD VDD
    Hynix Samsung VDD
    K9
    VDD
    K9
    VDD
    K9
    VDD
    K9
    H512@ S512@ N2 N2 N2 N2
    X7624938L03 X7624938L04 M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
    [29] M_CLK0 J8 N10 J8 N10 [29] M_CLK1 J8 N10 J8 N10
    M_CLK#0 K8 CK VDD M_CLK#0 CK VDD M_CLK#1 K8 CK VDD M_CLK#1 CK VDD
    [29] M_CLK#0 R2 K8 R2 [29] M_CLK#1 R2 K8 R2
    M_CKE0 K10 CK VDD M_CKE0 CK VDD M_CKE1 K10 CK VDD M_CKE1 CK VDD
    [29] M_CKE0 R10 K10 R10 [29] M_CKE1 R10 K10 R10
    CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS

    VRAM_ODT0K2 A2 VRAM_ODT0 K2 A2 VRAM_ODT1K2 A2 VRAM_ODT1 K2 A2


    [29] VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ [29] VRAM_ODT1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
    M_CS#0 L3 A9 M_CS#0 L3 A9 M_CS#1 L3 A9 M_CS#1 L3 A9
    [29] M_CS#0 CS VDDQ CS VDDQ [29] M_CS#1 CS VDDQ CS VDDQ
    M_RAS#0 J4 C2 M_RAS#0 J4 C2 M_RAS#1 J4 C2 M_RAS#1 J4 C2
    [29] M_RAS#0 RAS VDDQ RAS VDDQ [29] M_RAS#1 RAS VDDQ RAS VDDQ
    M_CAS#0 K4 C10 M_CAS#0 K4 C10 M_CAS#1 K4 C10 M_CAS#1 K4 C10
    [29] M_CAS#0 CAS VDDQ CAS VDDQ [29] M_CAS#1 CAS VDDQ CAS VDDQ
    M_WE#0 L4 D3 M_WE#0 L4 D3 M_WE#1 L4 D3 M_WE#1 L4 D3
    [29] M_WE#0 WE VDDQ WE VDDQ [29] M_WE#1 WE VDDQ WE VDDQ
    E10 E10 E10 E10
    VDDQ VDDQ VDDQ VDDQ
    F2 F2 F2 F2
    M_DQS2 VDDQ M_DQS3 VDDQ M_DQS4 VDDQ M_DQS6 VDDQ
    F4 H3 F4 H3 F4 H3 F4 H3
    M_DQS0 DQSL VDDQ M_DQS1 DQSL VDDQ M_DQS5 DQSL VDDQ M_DQS7 DQSL VDDQ
    C C8 H10 C8 H10 C8 H10 C8 H10 C
    DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

    M_DQM2 E8 A10 M_DQM3 E8 A10 M_DQM4 E8 A10 M_DQM6 E8 A10


    M_DQM0 DML VSS M_DQM1 DML VSS M_DQM5 DML VSS M_DQM7 DML VSS
    D4 B4 D4 B4 D4 B4 D4 B4
    DMU VSS DMU VSS DMU VSS DMU VSS
    E2 E2 E2 E2
    VSS VSS VSS VSS
    G9 G9 G9 G9
    M_DQS#2 VSS M_DQS#3 VSS M_DQS#4 VSS M_DQS#6 VSS
    G4 J3 G4 J3 G4 J3 G4 J3
    M_DQS#0 DQSL VSS M_DQS#1 DQSL VSS M_DQS#5 DQSL VSS M_DQS#7 DQSL VSS
    B8 J9 B8 J9 B8 J9 B8 J9
    DQSU VSS DQSU VSS DQSU VSS DQSU VSS
    M2 M2 M2 M2
    VSS VSS VSS VSS
    M10 M10 M10 M10
    VSS VSS VSS VSS
    P2 P2 P2 P2
    VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS
    [29] DRAM_RST# T3 P10 P10 P10 P10
    RESET VSS RESET VSS RESET VSS RESET VSS
    T2 T2 T2 T2
    VSS VSS VSS VSS
    L9 T10 L9 T10 L9 T10 L9 T10
    ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
    1

    1
    J2 B2 J2 B2 J2 B2 J2 B2
    VGA@ R374 NC/ODT1 VSSQ VGA@ R375 NC/ODT1 VSSQ VGA@ R376 NC/ODT1 VSSQ VGA@ R377 NC/ODT1 VSSQ
    L2 B10 L2 B10 L2 B10 L2 B10
    243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
    J10 D2 J10 D2 J10 D2 J10 D2
    NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
    L10 D9 L10 D9 L10 D9 L10 D9
    NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
    E3 E3 E3 E3
    2

    2
    VSSQ VSSQ VSSQ VSSQ
    A1 E9 A1 E9 A1 E9 A1 E9
    NC VSSQ NC VSSQ NC VSSQ NC VSSQ
    A11 F10 A11 F10 A11 F10 A11 F10
    NC VSSQ NC VSSQ NC VSSQ NC VSSQ
    T1 G2 T1 G2 T1 G2 T1 G2
    NC VSSQ NC VSSQ NC VSSQ NC VSSQ
    T11 G10 T11 G10 T11 G10 T11 G10
    NC VSSQ NC VSSQ NC VSSQ NC VSSQ
    100-BALL 100-BALL 100-BALL 100-BALL
    SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
    64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA
    X76@ X76@ X76@ X76@

    +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS


    B B
    1

    1
    VGA@
    R378 R379 VGA@ R380 VGA@ R381 R382 R383 R384 R385
    4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@
    VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
    2

    2
    VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
    1

    1
    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K
    VGA@ 1 VGA@ 1 VGA@ VGA@ 1 VGA@ 1 VGA@ VGA@
    C472

    C473

    C474

    C475

    C476

    C477

    C478

    C479
    1 1 1 1
    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K

    0.1U_0402_10V6K
    R386 VGA@ R387 VGA@ R388 R389 R390 R391 VGA@ R392 VGA@ R393
    0.1U_0402_10V6K

    4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@


    VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
    2 2 2 2 2 2 2 2
    2

    2
    M_CLK0 1 2
    R394 VGA@ 56_0402_1%

    M_CLK#0 1 2 +1.5VGS
    R396 VGA@ 56_0402_1% +1.5VGS
    1 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    C506 VGA@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    0.01U_0402_16V7K +1.5VGS 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

    C500

    C501

    C484

    C485

    C486

    C502

    C503

    C504

    C505

    C487
    1 1 1 1 1 1 1 1 1 1
    C492

    C482

    C483

    C493

    C494

    C495

    C496

    C497

    C498

    C499
    C488 C489 C490 C480 C491 C481
    VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    10U_0603_6.3V6M 10U_0603_6.3V6M10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    M_CLK1 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    R395 VGA@ 56_0402_1% VGA@ VGA@ VGA@
    VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
    A A
    VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
    M_CLK#1 VGA@ VGA@
    1 2
    R397 VGA@ 56_0402_1% 1
    C507 VGA@
    0.01U_0402_16V7K
    2
    ref 139-02 recommand VRAM P/N :
    add off page Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! ) Security Classification Compal Secret Data Compal Electronics, Inc.
    Park SCL recommand pu 60.4 ohm to Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! ) Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    1.5VGS
    0619 update update VRAM PN 0619 update THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    RobsonXT-S3 VRAM
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 30 of 57
    5 4 3 2 1
    5 4 3 2 1

    +LEDVDD
    INVPWM VGA LCD/PANEL BD. Conn. B+

    1 R398 2
    1 1 0_0805_5%
    DISPOFF#

    470P_0402_50V7K

    470P_0402_50V7K
    C508
    680P_0402_50V7K C512
    C509 @ 4.7U_0805_25V6-K
    2 2
    1 @ 1 @
    C511
    LCD POWER CIRCUIT R01
    2 2
    +LCDVDD_CONN
    +LCDVDD +5VALW +3VS_CMOS +LEDVDD
    For EMI +3VS
    JLVDS1
    +3VS
    D W=60mils CMOS USB20_N5
    1
    1 2
    2 D
    [18] USB20_N5 3 3 4 4 1

    1
    R400 R401 [18] USB20_P5 USB20_P5 5 6
    150_0603_1% 100K_0402_5% 5 6 @ C514
    1 7 7 8 8 (60 MIL)
    C513 CONN_LVDS_A0# 9 10 680P_0402_50V7K
    4.7U_0805_10V4Z CONN_LVDS_A0 9 10 2
    11 12
    11 12
    13 14

    2
    13 14

    3
    D R403 220K_0402_5%
    S
    2 CONN_LVDS_A1# 15 16 CE_EN [40]
    G
    CONN_LVDS_A1 15 16 INVPWM
    2 1 2 2 17 17 18 18 2 R402 1 INVT_PWM [40]
    Q79 G 19 20 DISPOFF# 0_0402_5%
    2N7002_SOT23 S AO3413_SOT23-3 CONN_LVDS_A2# 19 20 +3VS
    1
    D 21 22

    1
    21 22

    1
    DTC124EK C515 Q80 CONN_LVDS_A2 23 24 Pull high at chipset/VGA side
    23 24
    W=60mils 25 26

    OUT
    0.1U_0402_16V4Z CONN_LVDS_ACLK# 25 26 CONN_LVDS_SCL R404 2.2K_0402_5% @
    27 28
    2 +LCDVDD +LCDVDD_CONN CONN_LVDS_ACLK 27 28 CONN_LVDS_SDA R405 2.2K_0402_5% @
    L29 29 30
    R406 2 0_0402_5% LCD_ENVDD 29 30 CONN_LVDS_B2#
    [17] PCH_ENVDD 1 2 IN 31 31 32 32
    PX@ 1 2 CONN_LVDS_B0 33 34 CONN_LVDS_B2

    GND
    CONN_LVDS_B0# 33 34
    35 35 36 36
    Q81 FBMA-L11-201209-221LMA30T_0805 CONN_LVDS_B1# 37 38 CONN_LVDS_BCLK
    37 38
    1

    [23] VGA_ENVDD R407 2 1 0_0402_5% DTC124EKAT146_SC59-3 1 1 CONN_LVDS_B1 39 40 CONN_LVDS_BCLK#

    3
    DIS@ C516 C517 39 40
    R408 @ 41 42
    100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z GND GND
    2 2 ACES_87142-4041
    2

    [24] VGA_LVDS_SCL VGA_LVDS_SCL 0_0402_5% 2 DIS@ 1 R409 CONN_LVDS_SCL


    [24] VGA_LVDS_SDA VGA_LVDS_SDA 0_0402_5% 2 DIS@ 1 R410 CONN_LVDS_SDA

    VGA_LVDS_A0 0_0402_5% 2 DIS@ 1 R411 CONN_LVDS_A0


    [23] VGA_LVDS_A0
    VGA_LVDS_A0# 0_0402_5% 2 DIS@ 1 R412 CONN_LVDS_A0#
    [23] VGA_LVDS_A0#
    VGA_LVDS_A1 0_0402_5% 2 DIS@ 1 R413 CONN_LVDS_A1
    [23] VGA_LVDS_A1
    C VGA_LVDS_A1# 0_0402_5% 2 DIS@ 1 R414 CONN_LVDS_A1# C
    [23] VGA_LVDS_A1#
    VGA_LVDS_A2 0_0402_5% 2 DIS@ 1 R415 CONN_LVDS_A2
    [23] VGA_LVDS_A2
    VGA_LVDS_A2# 0_0402_5% 2 DIS@ 1 R416 CONN_LVDS_A2#
    [23] VGA_LVDS_A2#
    +3VS VGA_LVDS_ACLK 0_0402_5% CONN_LVDS_ACLK
    [23] VGA_LVDS_ACLK 2 DIS@ 1 R417
    VGA_LVDS_ACLK#0_0402_5% 2 DIS@ 1 R418 CONN_LVDS_ACLK#
    [23] VGA_LVDS_ACLK#

    U22
    5

    VGA_LVDS_B0 0_0402_5% 2 DIS@ 1 R722 CONN_LVDS_B0


    [23] VGA_LVDS_B0
    1 VGA_LVDS_B0# 0_0402_5% 2 DIS@ 1 R723 CONN_LVDS_B0#
    P

    NC [23] VGA_LVDS_B0#
    2 4 INVPWM
    [17] PCH_PWM A Y VGA_LVDS_B1 0_0402_5% 2 DIS@ 1 R725 CONN_LVDS_B1
    [23] VGA_LVDS_B1
    G

    VGA_LVDS_B1# 0_0402_5% 2 DIS@ 1 R598 CONN_LVDS_B1#


    [23] VGA_LVDS_B1#
    TC7SZ14FU_SSOP5
    3

    @ VGA_LVDS_B2 0_0402_5% 2 DIS@ 1 R720 CONN_LVDS_B2


    [23] VGA_LVDS_B2
    VGA_LVDS_B2# 0_0402_5% 2 DIS@ 1 R721 CONN_LVDS_B2#
    [23] VGA_LVDS_B2#
    VGA_LVDS_BCLK 0_0402_5% 2 DIS@ 1 R726 CONN_LVDS_BCLK
    [23] VGA_LVDS_BCLK
    PX@ VGA_LVDS_BCLK#0_0402_5% 2 DIS@ 1 R724 CONN_LVDS_BCLK#
    [23] VGA_LVDS_BCLK#
    1 R430 2
    2
    G

    0_0402_5%
    [17] EDID_CLK EDID_CLK 0_0402_5% 2 PX@ 1 R419 CONN_LVDS_SCL
    3 1 INVPWM 2 R431 1 +3VS [17] EDID_DATA EDID_DATA 0_0402_5% 2 PX@ 1 R420 CONN_LVDS_SDA
    10K_0402_5% @
    S

    LVDS_A0 0_0402_5% 2 PX@ 1 R421 CONN_LVDS_A0


    [17] LVDS_A0
    2N7002_SOT23 LVDS_A0# 0_0402_5% 2 PX@ 1 R422 CONN_LVDS_A0#
    [17] LVDS_A0#
    Q82
    @ LVDS_A1 0_0402_5% 2 PX@ 1 R423 CONN_LVDS_A1
    [17] LVDS_A1
    LVDS_A1# 0_0402_5% 2 PX@ 1 R424 CONN_LVDS_A1#
    For GMCH DPST [17] LVDS_A1#
    LVDS_A2 0_0402_5% 2 PX@ 1 R425 CONN_LVDS_A2
    [17] LVDS_A2
    LVDS_A2# 0_0402_5% 2 PX@ 1 R427 CONN_LVDS_A2#
    [17] LVDS_A2#
    LVDS_ACLK 0_0402_5% 2 PX@ 1 R428 CONN_LVDS_ACLK
    [17] LVDS_ACLK
    LVDS_ACLK# 0_0402_5% 2 PX@ 1 R429 CONN_LVDS_ACLK#
    [17] LVDS_ACLK#
    +3VS
    B B
    LVDS_B0 0_0402_5% 2 PX@ 1 R727 CONN_LVDS_B0
    [17] LVDS_B0
    LVDS_B0# 0_0402_5% 2 PX@ 1 R730 CONN_LVDS_B0#
    [17] LVDS_B0#
    1

    R717 0_0402_5%
    1 2 R433 @ LVDS_B1 0_0402_5% 2 PX@ 1 R732 CONN_LVDS_B1
    [17] LVDS_B1
    LVDS_B1# 0_0402_5% 2 PX@ 1 R731 CONN_LVDS_B1#
    [17] LVDS_B1#
    4.7K_0402_5%
    D4
    LVDS_B2 0_0402_5% 2 PX@ 1 R734 CONN_LVDS_B2
    [17] LVDS_B2
    2

    BKOFF# 1 2 DISPOFF# LVDS_B2# 0_0402_5% 2 PX@ 1 R733 CONN_LVDS_B2#


    [40] BKOFF# [17] LVDS_B2#
    @ CH751H-40PT_SOD323-2 LVDS_BCLK 0_0402_5% 2 PX@ 1 R728 CONN_LVDS_BCLK
    [17] LVDS_BCLK
    1

    LVDS_BCLK# 0_0402_5% 2 PX@ 1 R729 CONN_LVDS_BCLK#


    [17] LVDS_BCLK#
    R716
    10K_0402_5%
    2

    (20 MIL)
    R539 @
    CMOS Camera Conn (20 MIL)
    R436 DIS@ 0_0402_5% 0_0603_5%
    [24] VGA_ENBKL 1 2 +5VS 1 2 CMOS@
    ENBKL [40]
    R596 R432 +3VS_CMOS
    PX@ 0_0603_5% 0_0603_5%

    S
    R437 1 2 0_0402_5% 1 2 3 1 1 2

    D
    [17] PCH_ENBKL +3VS
    1 1
    2

    CMOS@ CMOS@ CMOS@


    R438 +5VALW CMOS@ Q83 C518 C519

    G
    2
    100K_0402_1% R434 100K_0402_5% SI2301BDS-T1-E3_SOT23-3 0.1U_0402_16V4Z 10U_0805_10V4Z
    CMOS@ 2 2
    4.7V
    1

    R435 1
    1

    R543 @ 150K_0402_5% CMOS@


    C520
    R01 0_0402_5%
    OUT

    CMOS@
    0.1U_0402_16V4Z
    2
    2

    A [40] CMOS_OFF# 2 IN A
    GND

    Q84
    DTC124EKAT146_SC59-3
    3

    CMOS@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LVDS/CAMERA
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6758P
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 31 of 57
    5 4 3 2 1
    A B C D E

    +5VS +5VS +5VS +5VS +5VS

    3 3 3 3 3

    1 BLUE 1 GREEN 1 RED 1 JVGA_HS 1 JVGA_VS

    2 2 2 BAT54S-7-F_SOT23-3 2 2
    @ @ @ @ @
    D5 D6 D7 D8 D9
    BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

    1 UMA only +5VS


    D10
    +CRT_VCC
    CRT Connector
    F1
    1

    2 1 1 2
    1
    DAC_RED 1 2 CRT_R RB491D_SC59-3
    [17] DAC_RED
    R439 PX@ 0_0402_5% 1.1A_6V_SMD1812P110TF C521
    DAC_GRN 1 2 CRT_G
    [17] DAC_GRN
    R440 PX@ 0_0402_5% FCM1608CF-121T03 0603 W=40mils 2
    0.1U_0402_16V4Z

    DAC_BLU 1 2 CRT_B CRT_R 1 2 RED


    [17] DAC_BLU
    R441 PX@ 0_0402_5% L30
    FCM1608CF-121T03 0603
    CRT_G 1 2 GREEN
    L31
    DIS only FCM1608CF-121T03 0603 JCRT1
    CRT_B 1 2 BLUE 6
    L32 11

    1
    VGA_CRT_R 1 2 CRT_R 1 1 1 1 1 1 RED 1
    [24] VGA_CRT_R
    R442 DIS@ 0_0402_5% 7
    VGA_CRT_G 1 2 CRT_G R445 R443 R446 C522 C523 C524 C525 C526 C527 CRT_DDC_DAT_CONN 12
    [24] VGA_CRT_G
    R444 DIS@ 0_0402_5% 150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J GREEN 2
    VGA_CRT_B CRT_B 2 2 2 2 2 2
    [24] VGA_CRT_B 1 2 8 G 16

    2
    R447 DIS@ 0_0402_5% JVGA_HS 13 17
    10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J BLUE G
    3
    CLOSE TO CONN 9
    JVGA_VS 14
    4
    10
    CRT_DDC_CLK_CONN 15
    2 5 2
    +CRT_VCC 1
    R448
    C528 CONTE_80431-5K1-152
    1 2
    1 100P_0402_50V8J ME@
    2
    C529 1K_0402_5%
    0.1U_0402_16V4Z
    2

    1
    PX@ FCM1608CF-121T03 0603

    OE#
    P
    R449 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 JVGA_HS
    [17] CRT_HSYNC A Y L33
    Check CRT footprint 7/20_OTIS

    G
    DIS@ U23
    R450 1 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5 1
    [24] VGA_HSYNC

    3
    @
    C530
    10P_0402_50V8J
    +CRT_VCC 2
    R451
    1 2
    1
    C531 1K_0402_5%
    0.1U_0402_16V4Z
    2
    5

    1
    PX@ FCM1608CF-121T03 0603
    OE#
    P
    R4521 2 0_0402_5% VSYNC_G 2 4 CRT_VSYNC_1 1 2 JVGA_VS
    3 [17] CRT_VSYNC A Y 3
    L34
    G

    DIS@ U24 1
    R4531 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5
    [24] VGA_VSYNC
    3

    @ C532
    10P_0402_50V8J
    2

    +3VS +3VGS
    7/21 modify
    2

    R736 R735
    +3VS 0_0402_5% 0_0402_5% +CRT_VCC
    Pull high at chipset/VGA side PX@ DIS@
    1

    1
    1

    1
    @ @
    R454 R455
    2.2K_0402_5% 2.2K_0402_5% R456 R457
    5

    2.2K_0402_5% 2.2K_0402_5%
    2

    [17] CRT_DDC_DATA CRT_DDC_DATA 2 PX@ 1 CRT_DDC_DATA_R 4 3 CRT_DDC_DAT_CONN


    R458 0_0402_5%
    [24] VGA_DDCDATA VGA_DDCDATA 2 DIS@ 1 2N7002DW -T/R7_SOT363-6
    2

    R459 0_0402_5% Q62B

    [17] CRT_DDC_CLK CRT_DDC_CLK 2 PX@ 1 CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN


    R460 0_0402_5% 1 1
    4 [24] VGA_DDCCLK VGA_DDCCLK 2 DIS@ 1 2N7002DW -T/R7_SOT363-6 @ @ 4
    R461 0_0402_5% Q62A C533 C534
    100P_0402_50V8J 68P_0402_50V8K
    2 2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CRT Connector
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 32 of 57
    A B C D E
    5 4 3 2 1

    HDMI_CLK+_CONN 1 2 @ L35
    R462 UMA_HDMI@ 680_0402_1% HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN
    HDMI_CLK-_CONN 1 2
    1 2
    R463 UMA_HDMI@ 680_0402_1% [17] HDMI_CLK+_CK HDMI_CLK+_CK HDMI@ R464 1 2 0_0402_5% HDMI_CLK+_CONN
    [17] HDMI_CLK-_CK HDMI_CLK-_CK HDMI@ R465 1 2 0_0402_5% HDMI_CLK-_CONN HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN
    HDMI_TX0+_CK HDMI@ R466 0_0402_5% HDMI_TX0+_CONN 4 3
    [17] HDMI_TX0+_CK 1 2
    [17] HDMI_TX0-_CK HDMI_TX0-_CK HDMI@ R467 1 2 0_0402_5% HDMI_TX0-_CONN W CM-2012-900T_4P
    [17] HDMI_TX1+_CK HDMI_TX1+_CK HDMI@ R468 1 2 0_0402_5% HDMI_TX1+_CONN
    [17] HDMI_TX1-_CK HDMI_TX1-_CK HDMI@ R469 1 2 0_0402_5% HDMI_TX1-_CONN @ L36
    D [17] HDMI_TX2+_CK HDMI_TX2+_CK HDMI@ R470 1 2 0_0402_5% HDMI_TX2+_CONN HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN D
    HDMI_TX0+_CONN HDMI_TX2-_CK HDMI@ R471 0_0402_5% HDMI_TX2-_CONN 1 2
    1 2 [17] HDMI_TX2-_CK 1 2
    R472 UMA_HDMI@ 680_0402_1%
    HDMI_TX0-_CONN 1 2 HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN
    R473 UMA_HDMI@ 680_0402_1% C535 DIS_HDMI@ 0.1U_0402_16V7K HDMI_CLK+_CK 4 3
    [24] VGA_HDMI_CLK+ 1 2
    C536 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_CLK-_CK W CM-2012-900T_4P
    [24] VGA_HDMI_CLK-
    C537 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX0+_CK
    [24] VGA_HDMI_TX0+
    C538 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX0-_CK @ L37
    [24] VGA_HDMI_TX0-
    C539 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN
    [24] VGA_HDMI_TX1+ 1 2
    C540 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX1-_CK
    [24] VGA_HDMI_TX1-
    C541 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX2+_CK
    [24] VGA_HDMI_TX2+
    C542 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX2-_CK HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN
    [24] VGA_HDMI_TX2- 4 3
    HDMI_TX1+_CONN 1 2
    R474 UMA_HDMI@ 680_0402_1% W CM-2012-900T_4P
    HDMI_TX1-_CONN 1
    R475 UMA_HDMI@
    2
    680_0402_1%
    R01 @ L38
    HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN
    1 2

    HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN
    4 3
    W CM-2012-900T_4P

    HDMI_TX2+_CONN 1 2
    R476 UMA_HDMI@ 680_0402_1% +3VS +3VGS
    HDMI_TX2-_CONN 1 2
    R477 UMA_HDMI@ 680_0402_1%
    D
    1

    2
    C 2 R738 R739 +5VS +5VS C
    +3VS
    G 0_0402_5% 0_0402_5%
    S UMA_HDMI@ DIS_HDMI@ 3 3
    3

    Q95

    1
    2N7002W -T/R7_SOT323-3 1 HDMIDAT_R 1 HDMICLK_R
    UMA_HDMI@
    2 @ 2 @
    D11 D12
    Pull up R for PCH OR VGA SIDE BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

    2
    HDMI@

    [17] HDMICLK_NB R478 1 2 0_0402_5% 1 6 HDMICLK_R


    UMA_HDMI@

    5
    [24] VGA_HDMI_SCL R479 1 2 0_0402_5% HDMI@ 2N7002DW -T/R7_SOT363-6
    DIS_HDMI@ Q63A
    R480 1 2 0_0402_5% 4 3 HDMIDAT_R +5VS
    [17] HDMIDAT_NB
    UMA_HDMI@
    [24] VGA_HDMI_SDA R481 1 2 0_0402_5% Q63B 2N7002DW -T/R7_SOT363-6
    DIS_HDMI@

    2
    HDMI@
    R482 @ D13
    0_0805_5% RB491D_SC59-3

    1
    +5VS_HDMI
    +3VS
    1 C543
    +5VS 0.1U_0402_16V4Z

    2
    B HDMI@ B
    2

    2
    R485 R483 R484 2
    1M_0402_5% 2.2K_0402_5% 2.2K_0402_5%
    UMA_HDMI@ HDMI@ HDMI@

    1
    2
    G

    Q93
    1

    UMA_HDMI@
    TMDS_B_HPD# 3 1 R486 1 2 0_0402_5% @
    [17] TMDS_B_HPD#

    1
    UMA_HDMI@ D14
    S

    2N7002_SOT23 BAT54S-7-F_SOT23-3 JHDMI1


    HDMI_DET 19 HP_DET
    18 +5V
    2

    17 DDC/CEC_GND
    R696 +3VS HDMIDAT_R 16
    HDMICLK_R SDA
    0_0402_5% 15 SCL

    2
    @ 14 Reserved
    R697 DIS_HDMI@ 13
    1

    CEC
    1

    C 150K_0402_5% R488 HDMI_CLK-_CONN 12 20


    Q28 DIS_HDMI@ 100K_0402_5% CK- G1
    2 1 2 11 CK_shield G2 21
    MMBT3904_G_SOT23-3 B 1 HDMI_CLK+_CONN 10 22
    E HDMI@ HDMI_TX0-_CONN CK+ G3
    9 23
    3

    D0- G4
    [24] HDMI_DETECT_VGA 8 D0_shield
    HDMI_CLK+_CONN 1 2 HDMI_TX0+_CONN 7 D0+
    1

    R489 DIS_HDMI@ 499_0402_1% HDMI_TX1-_CONN 6


    HDMI_CLK-_CONN R698 DIS_HDMI@ D1-
    1 2 5 D1_shield
    R490 DIS_HDMI@ 499_0402_1% 10K_0402_5% HDMI_TX1+_CONN 4
    HDMI_TX0+_CONN HDMI_TX2-_CONN D1+
    1 2 3 D2-
    R491 DIS_HDMI@ 499_0402_1% 2N7002W -T/R7_SOT323-3 2
    2

    D D2_shield
    1

    A
    HDMI_TX0-_CONN 1 2 HDMI_TX2+_CONN 1 A
    R492 DIS_HDMI@ 499_0402_1% D2+
    2 +5VS
    HDMI_TX1+_CONN 1 2 G SUYIN_100042GR019M23DZL
    R493 DIS_HDMI@ 499_0402_1% S DIS_HDMI@
    3

    HDMI_TX1-_CONN 1 2 Q94
    R494 DIS_HDMI@ 499_0402_1% R874
    HDMI_TX2+_CONN 1 2 100K_0402_5%
    R495 DIS_HDMI@ 499_0402_1% DIS_HDMI@ Security Classification Compal Secret Data Compal Electronics,Ltd.
    HDMI_TX2-_CONN 1 2 2010/07/12 2012/07/11 Title
    Issued Date Deciphered Date
    2

    R496 DIS_HDMI@ 499_0402_1%


    HDMI CONN
    NEAR CONNECT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size
    Custom
    Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 33 of 57
    5 4 3 2 1
    A B C D E

    Mini-Express Card for WLAN/WiMAX(Half)

    1 1

    +1.5VS
    +3VALW +1.5VS_CONN
    +3VS +3VS_WLAN
    J6

    1
    1 1 1
    Mini-Express Card(WLAN/WiMAX) 1 2 J7

    1
    1 2

    @
    JUMP_43X79 C544 C545 C546
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

    @
    JUMP_43X79 2 2 2

    2
    @
    JWLN1

    2
    [16,35] PCIE_WAKE# PCIE_WAKE# R514 1 2 0_0402_5% 1 2
    BT_ACTIVE R497 1 WAKE# 3.3V
    [42] BT_ACTIVE 2 @ 0_0402_5% 3 NC GND 4
    5 6 +1.5VS_CONN
    WLAN_CLKREQ1# NC 1.5V LPC_FRAME#_R
    [15] WLAN_CLKREQ1# 7 CLKREQ# NC 8
    9 10 LPC_AD3_R
    GND NC LPC_AD2_R
    [15] CLK_PCIE_WLAN1# 11 REFCLK- NC 12
    13 14 LPC_AD1_R
    [15] CLK_PCIE_WLAN1 REFCLK+ NC
    15 16 LPC_AD0_R
    PCI_RST#_R GND NC
    17 NC GND 18
    CLK_PCI_DB 19 20 R498 1 2 0_0402_5%
    NC NC WL_OFF# [18]
    21 GND PERST# 22 BUF_PLT_RST# [18,35,40]
    23 24 R499 1 2 @ 0_0402_5% +3VALW
    2 [15] PCIE_PRX_DTX_N2 PERn0 +3.3Vaux 2
    25 26 R500 1 2 0_0402_5% +3VS
    [15] PCIE_PRX_DTX_P2 PERp0 GND
    27 GND +1.5V 28
    29 30 R501 1 2 @ 0_0402_5% SMB_CLK_S3 [12,13,15]
    GND SMB_CLK R502 1
    [15] PCIE_PTX_C_DRX_N2 31 PETn0 SMB_DATA 32 2 @ 0_0402_5% SMB_DATA_S3 [12,13,15]
    [15] PCIE_PTX_C_DRX_P2 33 PETp0 GND 34
    35 GND USB_D- 36 USB20_N9 [18]
    +3VS_WLAN 37
    39
    NC USB_D+ 38
    40
    USB20_P9 [18] R01
    NC GND 0_0402_5% @
    41 NC LED_WWAN# 42 2 1 R503
    43 44 0_0402_5% 2 1 R504 WLAN_LED# WLAN_LED# [56]
    100_0402_1% NC LED_WLAN# @
    45 NC LED_WPAN# 46
    R505 47 48
    EC_TX_P80_DATA NC +1.5V
    [40,41] EC_TX_P80_DATA 1 2 49 NC GND 50
    EC_RX_P80_CLK 1 2 51 52
    [40,41] EC_RX_P80_CLK NC +3.3V
    R506
    100_0402_1% 53 54
    GND GND

    TAITW_PFPET0-AFGLBG1ZZ4N0

    2
    For EC to detect ME@
    R507
    debug card insert. 100K_0402_5%

    3 3

    Reserve for SW mini-pcie debug card.


    Series resistors closed to KBC side.
    LPC_FRAME#_R R508 1 @ 2 0_0402_5% LPC_FRAME#
    LPC_FRAME# [14,40]
    LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3
    LPC_AD3 [14,40]
    LPC_AD2_R R510 1 @ 2 0_0402_5% LPC_AD2
    LPC_AD2 [14,40]
    LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1
    LPC_AD1 [14,40]
    LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0
    LPC_AD0 [14,40]
    PCI_RST#_R R513 1 @ 2 0_0402_5% BUF_PLT_RST#
    CLK_PCI_DB CLK_PCI_DB [15]
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Mini-Card/NEW Card/SIM
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 34 of 57
    A B C D E
    5 4 3 2 1

    Power On strapping
    +3VALW +3V_LAN +1.7_VDDCT +1.7_LX Pin Description Chip Default
    Close together
    H:Over Clock Enable
    Layout Notice : Place as close LED0 H
    J8 chip as possible. L39 L:Over Clock Disable *
    +1.7_VDDCT 1 2 +1.7_LX

    1000P_0402_50V7K
    H:SWR Switch mode regulator Select

    10U_0805_10V4Z
    4.7UH_SIA4012-4R7M_20%

    0.1U_0402_16V4Z
    1 1 2 2
    *

    @ C549

    C548

    C547
    1 1 LED2 --
    JUMP_43X79 AR8151 Pin23=LED2.
    @ Note: Place Close to LAN chip
    2 2 L39 DCR< 0.15 ohm AR8152, Pin23 is CLKREQ
    D Atheros request can't disable LAN power Rate current > 1A D

    Close to
    Pin40

    U26 8152@

    S IC AR8152-AL1E QFN 40P E-LAN CTRL


    no overclocking
    PD 5.1K
    U26 LED0,1,2 intel Pull UP
    Place Close to Chip 1 2
    R515 5.1K_0402_5%
    C C5531 20.1U_0402_16V7K PCIE_PRX_C_DTX_N129 38 ACTIVITY
    Place Close to LAN chip C
    [15] PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY [36]
    LAN_LINK# 49.9_0402_1%
    C5521 20.1U_0402_16V7K PCIE_PRX_C_DTX_P130
    Atheros LED_1 39
    23 1 8152@ 2
    LAN_LINK# [36]
    CLKREQ_LAN# MDI0+ R526 1 2 1@ 2 C574 1000P_0402_50V7K
    [15] PCIE_PRX_DTX_P1 TX_P LED_2
    8151-AL1A R516 0_0402_5% 49.9_0402_1%
    36 MDI0- R527 1 2 1 2 C575 0.1U_0402_16V4Z
    [15] PCIE_PTX_C_DRX_N1 RX_N
    12 MDI0- 49.9_0402_1%
    TRXN0 MDI0- [36]
    35 11 MDI0+ MDI1+ R528 1 2 1@ 2 C576 1000P_0402_50V7K
    [15] PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ [36]
    15 MDI1- 49.9_0402_1%
    TRXN1 MDI1- [36]
    2R517 0_0402_5%
    1 CLK_PCIE_LAN#_C32 14 MDI1+ MDI1- R529 1 2 1 2 C577 0.1U_0402_16V4Z
    [15] CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ [36]
    2R518 0_0402_5%
    1 CLK_PCIE_LAN_C 33 18 MDI2- 49.9_0402_1%
    [15] CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- [36]
    17 MDI2+ MDI2+ R530 1 2 1@ 2 C580 1000P_0402_50V7K
    TRXP2 MDI2+ [36]
    BUF_PLT_RST# 2 21 MDI3- GIGA@49.9_0402_1%
    [18,34,40] BUF_PLT_RST# PERST# TRXN3 MDI3- [36]
    20 MDI3+ MDI2- R531 1 2 1 2 C581 0.1U_0402_16V4Z
    TRXP3 MDI3+ [36]
    1R519 @ 0_0402_5%
    2 PCIE_WAKE#_R 3 GIGA@ 49.9_0402_1% GIGA@
    [16,34] PCIE_WAKE# W AKE#
    1R521 0_0402_5%
    2 Close Pin 10 MDI3+ R532 1 2 1@ 2 C582 1000P_0402_50V7K
    [40] LAN_WAKE# +3V_LAN
    25 10 LAN_RBIAS 1 2 GIGA@ 49.9_0402_1%
    SMCLK RBIAS MDI3-
    26 SMDATA
    R522 2.37K_0402_1% C554 & C555 Close pin1 < 200mil R533 1 2 1 2 C583 0.1U_0402_16V4Z
    GIGA@ GIGA@
    +3V_LAN
    C557 & C558 Close pin < 400mil
    28 TEST_RST VDD33 1

    C554

    C555

    C557

    @ C558
    Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+

    10U_0805_10V4Z

    10U_0805_10V4Z
    0.1U_0402_16V4Z

    1U_0402_6.3V4Z
    27 TESTMODE 1 1 1 1
    +1.7_LX
    resister and cap
    LX 40 +1.7_LX
    1 2 8152@ LAN_XTALO 7
    LAN_XTALI XTLO 2 2 2 2
    C559 0.1U_0402_16V4Z 8 XTLI Note 2 : C574, C576, C580, C582, reserved for EMI.
    5 +1.7_VDDCT
    VDDCT +1.7_VDDCT
    R525 GIGA@ 1 2C561
    CLKREQ_LAN# 1 2 CLKREQ_LAN#_R 4 0.1U_0402_16V4Z
    [15] CLKREQ_LAN# CLKREQ#
    0_0402_5% 24 +1.1_DVDDL
    DVDDL +1.1_DVDDL
    DVDDL_REG 37
    +1.1_AVDDL 13
    B
    +1.1_AVDDL AVDDL B
    19 AVDDL
    +1.1_AVDDL 31 16 +2.7_AVDDH
    +1.1_AVDDL AVDDL AVDDH +2.7_AVDDH
    34 AVDDL AVDDH 22
    +1.1_AVDDL 6 9 +2.7_AVDDH
    AVDDL_REG AVDDH_REG
    C564

    C565

    C566

    C567

    C568

    C569
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    1U_0402_6.3V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    1U_0402_6.3V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 1 1 1 1 1
    C571

    C570

    C572

    GIGA@ C573

    C563

    C562

    C560
    1U_0402_6.3V4Z
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    41 GND 1 1 1 1 1 1 2
    AR8151-AL1A_QFN40_5X5
    2 2 2 2 2 2
    GIGA@

    GIGA@

    GIGA@
    LAN_XTALI 2 2 2 2 2 2 1

    LAN_XTALO
    Y4
    1 2
    Near Near Near Near Near Near Near Near Near Near
    27P_0402_50V8J

    25MHZ_20PF_7A25000012
    Pin13 Pin19 Pin31 Pin34 Pin6 Pin9 Pin22 Pin16 Pin37 Pin24
    27P_0402_50V8J

    1 1
    C578

    C579

    2 2

    A A

    Configure Configure
    Pin4 R525 C559 Pin23 R516
    Security Classification Compal Secret Data Compal Electronics, Inc.
    AR8152 VDDCT_REG * CLKREQn * Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LAN-AR8151/8152
    AR8151 CLKREQn * LED[2] AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 35 of 57
    5 4 3 2 1
    5 4 3 2 1

    +1.7_VDDCT T1
    D D
    2
    C435 GIGA@ MDI3+ 1 16 MDO3+
    [35] MDI3+ TD+ TX+
    R304 0.1U_0402_16V4Z MDI3- 2 15 MDO3-
    [35] MDI3- TD- TX-
    2 1 3 14 MCT3 2 R534 1 GIGA@
    0_0603_5% 1 CT CT 75_0402_5%
    4 NC NC 13
    1 5 NC NC 12
    @C427
    @ C427 1 6 11 MCT2 2 R535 1 GIGA@
    MDI2+ CT CT MDO2+ 75_0402_5%
    [35] MDI2+ 7 RD+ RX+ 10
    C436 GIGA@ MDI2- 8 9 MDO2-
    2 [35] MDI2- RD- RX-
    1U_0402_6.3V4Z 0.1U_0402_16V4Z
    2
    BOTHHAND_NS0013LF
    GIGA@
    6/23 update
    1 2

    T2 C585
    2 1000P_1206_2KV7K
    C438 MDI0+ 1 16 MDO0+
    [35] MDI0+ TD+ TX+
    0.1U_0402_16V4Z MDI0- 2 15 MDO0-
    [35] MDI0- TD- TX-
    3 14 MCT0 2 R536 1
    1 CT CT 75_0402_5%
    4 NC NC 13
    5 NC NC 12
    C 1 6 11 MCT1 2 R537 1 C
    MDI1+ CT CT 75_0402_5% MDO1+
    [35] MDI1+ 7 RD+ RX+ 10
    C440 MDI1- 8 9 MDO1-
    [35] MDI1- RD- RX-
    0.1U_0402_16V4Z
    2
    BOTHHAND_NS0013LF

    JRJ2
    LAN_LINK# 12
    [35] LAN_LINK# Green LED-
    1 220_0402_5%
    @ +3V_LAN 2 1 11
    C378 R699 Green LED+
    SHLD2 16
    470P_0402_50V7K MDO3- 8
    2 PR4-
    SHLD1 15
    MDO3+ 7 PR4+
    MDO1- 6 PR2-
    B MDO2- 5 B
    PR3-
    MDO2+ 4 PR3+
    MDO1+ 3 PR2+
    MDO0- 2 PR1-
    SHLD2 14
    MDO0+ 1 PR1+
    SHLD1 13
    10 Yellow LED-
    ACTIVITY R538 2 1 220_0402_5% 9
    [35] ACTIVITY Yellow LED+
    1 LIYO_101007-08203-033
    @
    C379 ME@
    470P_0402_50V7K
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
    LAN_Transformer
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
    Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 36 of 57
    5 4 3 2 1
    5 4 3 2 1

    D D

    +3VS REMOTE1+
    Close to DDR
    Close U20 SMSC thermal sensor 1

    1
    @ C

    1
    1
    REMOTE1+
    +3VS placed near by VRAM R540
    C586
    100P_0402_50V8J
    2
    B
    Q97
    MMST3904-7-F_SOT323-3
    2 E
    10K_0402_5%

    3
    C587 @ REMOTE1-
    2200P_0402_50V7K U27

    2
    2 REMOTE1-

    1 10 EC_SMB_CK2
    VDD SMCLK EC_SMB_CK2 [15,24,40]
    REMOTE1+ EC_SMB_DA2
    REMOTE2+ 2
    2 DP1 SMDATA 9 EC_SMB_DA2 [15,24,40]
    REMOTE2+
    Under WWAN
    1 REMOTE1- 3 8 1
    DN1 ALERT#

    1
    C590 @ C @
    C588 0.1U_0402_16V4Z REMOTE2+ 4 7 C589 2 Q98
    2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
    2 REMOTE2- REMOTE2- 2 E
    5 6

    3
    DN2 GND REMOTE2-

    EMC1403-2-AIZL-TR_MSOP10
    REMOTE1,2+/-:
    C Address 1001_101xb Trace width/space:10/10 mil C

    Trace length:<8"

    B B

    FAN1 Conn
    +5VS R01
    R581
    0_0603_5% JFAN1
    2 1 1 1
    [40] EC_TACH 2 2
    [40] EC_FAN_PW M 3 3
    4 4
    2 5 G5
    6 G6
    C591
    10U_0805_10V4Z ACES_85205-04001
    1 ME@

    A A

    Security Classification Compal Secret Data Compal Electronics,Ltd.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
    EMC1403_Thermal sensor/FAN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 37 of 57
    5 4 3 2 1
    A B C D E F G H

    Left USB Conn.


    +USB_VCCB
    W=80mils
    JUSB1
    1 VCC
    1 USB20_N1 1 2 USB20_N1_C 2
    [18] USB20_N1 D-
    1 USB20_P1 R660 1 2 0_0402_5% USB20_P1_C 3
    + [18] USB20_P1 D+
    C592 R661 0_0402_5% 4
    C593 GND

    PJDLC05_SOT23-3
    220U_6.3V_M 470P_0402_50V7K 5
    2 2 D16 GND1
    6
    WCM-2012-900T_4P @ GND2
    7 GND3
    1 USB20_N1 USB20_N1_C 1
    4 4 3 3 8 GND4
    SUYIN_020173GR004M58BZL
    USB20_P1 1 2 USB20_P1_C
    1 2
    L65 @ ME@

    1
    +5VALW +USB_VCCB
    E-SATA COMBO
    U29
    1 8
    RIGHT USB PORT
    C594 0.1U_0402_16V4Z GND OUT
    2 7
    IN OUT
    2 1 3 6
    USB_ON# 4 IN OUT USB_OC0#
    [40,42,43] USB_ON# 5 USB_OC0# [18,43]
    EN OC#
    APL3510BKI_SO8
    Low Active
    1
    C595
    @ 1000P_0402_50V7K
    2

    SATA HDD Conn.


    2 JHDD1 2
    1
    SATA_ITX_DRX_P0 GND
    [14] SATA_ITX_DRX_P0 2
    SATA_ITX_DRX_N0 RX+
    [14] SATA_ITX_DRX_N0 3 RX-
    4 GND
    SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5
    [14] SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 SATA_DTX_IRX_P0 TX-
    2 0.01U_0402_16V7K 6 TX+
    [14] SATA_DTX_C_IRX_P0
    7
    GND

    8 3.3V
    +3VS 9
    3.3V
    10
    3.3V
    11
    GND
    12
    R550 GND
    R01 0_0805_5%
    13
    14
    GND
    5V
    +5VS 1 2 15 5V
    16
    5V
    17
    GND
    18
    Reserved
    19
    +5VS +3VS GND
    20 23
    12V GND
    21 24
    12V GND
    22 12V
    1 1 1 1 1 1
    @ SUYIN_127043FB022G278ZR
    C598 C599 C600 C601 C602 C603
    1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 2
    3 3

    ODD Power Control


    @ J9
    1 2
    1 2

    +5VS JUMP_43X79 +5V_ODD


    Q99

    D
    3 1
    1

    1
    AO3413_SOT23-3
    C604

    G
    2
    R552 0.1U_0402_16V4Z
    10K_0402_5% 2
    C607
    0.01U_0402_16V7K 1

    2
    1 R675 2 1 2
    100K_0402_5% C608

    1
    10U_0805_10V4Z
    2

    OUT
    [19] ODD_EN 2
    IN
    4 GND 4
    Q100
    DTC124EKAT146_SC59-3
    3

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDD/ODD Connector
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 38 of 57
    A B C D E F G H
    5 4 3 2 1

    CX20671
    High Definition Audio Codec SoC HDA_RST_AUDIO#
    With Integrated Class-D Stereo
    HDA_SYNC_AUDIO
    EMI
    Amplifier.
    HDA_SDOUT_AUDIO_R
    An integrated 5 V to 3.3 V Low-dropout
    voltage regulator (LDO). 1
    33_0402_5%
    2
    R556
    HDA_BITCLK_AUDIO

    An integrated 3.3 V to 1.8V Low-dropout @


    1 1 1 1
    voltage regulator (LDO).

    C609

    C610

    C611

    C612
    22P_0402_50V8J

    22P_0402_50V8J

    22P_0402_50V8J

    22P_0402_50V8J
    2 2 2 2
    D D
    @ @ @ @

    R01
    R584
    +3VS 2 1
    0_0402_5%
    R01

    10U_0805_10V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 1 1
    R586

    C613

    C614

    C615
    2 1 +LDO_OUT_3.3V
    +3VS 2 1 +VAUX_3.3 0_0402_5%
    0_0402_5% R557 2 2 2

    1U_0603_10V4Z

    10U_0805_10V4Z
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    +3VALW 2 @ 1 1 1 1 1 AVDD_3.3 pinis output of

    10U_0805_10V4Z

    0.1U_0402_16V4Z
    0_0402_5% R558

    C618

    C619

    C620

    C621
    1 1 internal LDO. NOT connect
    6/24 change +3VS To support Wake-on-Jack or Wake-on-Ring, the CODEC

    C616

    C617
    VAUX_3.3 & VDD_IO pins must be powerd by a rail that to external supply.
    is not removed unless AC power is removed. 2 2 2 2
    *DSH page42 has more detail. 2 2

    2 1
    R01 +CLASSD_5VS
    +3VS
    0_0402_5% R560 R587
    +3VALW 2 @ 1 2 1 +5VS

    1U_0603_10V4Z

    0.1U_0402_16V4Z
    0_0402_5% R561 1 1 10K only needed if supply to VAUX_3.3 0_0402_5%
    1 R562

    C622

    C623
    is removed during system re-start. 2 +5VS

    10U_0805_10V4Z

    0.1U_0402_16V4Z
    1 1
    0.1_1206_1%

    C624

    C625

    10U_0805_10V4Z

    10U_0805_10V4Z
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    2 2
    1 1 1 1
    Layout Note:Path from +5VS to LPWR_5.0

    C626

    C627

    C628

    C629
    10U_0805_10V4Z

    0.1U_0402_16V4Z
    1
    2 2

    10K_0402_5%
    1 1 RPWR_5.0 must be very low

    C630

    C631
    R563 2 2 2 2 resistance (<0.01 ohms)

    0.1U_0402_16V4Z
    2 2

    18

    29

    27
    28
    26
    C 1 C

    3
    7
    2
    U30

    C632
    FILT_1.8

    VAUX_3.3
    DVDD_3.3

    FILT_1.65

    AVDD_3.3
    VDD_IO

    AVDD_5V
    AVDD_HP
    Please bypass caps very close to device.
    HDA_SYNC_AUDIO 12 2
    [14] HDA_SYNC_AUDIO LPWR_5.0
    15
    +3VS HDA_RST_AUDIO# RPWR_5.0
    [14] HDA_RST_AUDIO# 9 17
    RESET# CLASS-D_REF R564 1 2 5.11K_0402_1% +VAUX_3.3
    HDA_BITCLK_AUDIO 5 Sense resistors must be
    [14] HDA_BITCLK_AUDIO BIT_CLK
    2

    R565 2 10K_0402_1% Port C


    G

    8 36 1 MIC_JD [43] connected same power


    SYNC SENSE_A
    [14] HDA_SDIN0 1 R566 2 33_0402_5% 6 R567 1 2 39.2K_0402_1% PLUG_IN [43] Port A
    HDA_SDOUT_AUDIO 1 3 HDA_SDOUT_AUDIO_R 4
    SDATA_IN that is used for VAUX_3.3
    [14] HDA_SDOUT_AUDIO SDATA_OUT
    35 MIC_INR Internal MIC
    D

    PORTB_R MIC_INL
    34
    2N7002_SOT23 PORTB_L
    33 +MICBIASB
    PC_BEEP B_BIAS R568 2.2K_0402_5%
    Q9 10 +MICBIASC
    PC_BEEP R569 2.2K_0402_5%
    1R669 @ 2 32 +MICBIASC
    C_BIAS C633
    31 1 2 2.2U_0603_10V7K R570 100_0402_1%
    EXT_MIC_R [43]
    0_0402_5% PORTC_R C634
    30 1 2 2.2U_0603_10V7K EXT_MIC_L [43] External MIC
    0_0402_5% PORTC_L
    [40] EAPD 1 2 R572 38 R571 100_0402_1%
    EC_MUTE# GPIO0/EAPD#
    [40] EC_MUTE# 2 1 37
    0_0402_5% R573 GPIO1/SPK_MUTE# HP_OUTR_R R575 15_0402_5%
    23 1 2 HP_OUTR [43]
    PORTA_R HP_OUTL_R R574 15_0402_5%
    PORTA_L
    22 1 2 HP_OUTL [43] Headphone
    40
    DMIC_CLK
    1 24
    DMIC_1/2 NC
    NC
    25 Changed from 5.1ohm to 15ohm
    39 for "zi zi"noise.
    R01 SPK_L2+ NC
    11
    SPK_L1- LEFT+
    EAPD active low 13
    LEFT-
    C637 @ 0=power down ex AMP Internal SPEAKER AVEE
    21
    19
    SPK_R2+ FLY_P
    1 2 1=power up ex AMP 16 20 1 2

    10U_0805_10V4Z
    0.1U_0402_16V4Z
    0.1U_0402_16V4Z SPK_R1- RIGHT+ FLY_N C638 1U_0603_10V4Z
    14 1 1
    RIGHT-

    C639

    C641
    GND

    C640 @ +3VS
    1 2
    1

    B 2 2 B
    0.1U_0402_16V4Z CX20671-11Z_QFN40_6X6
    41

    R576 R351
    1 @ 2 @ 4.7K_0402_5%
    0_0402_5% +MICBIASB
    R577 @
    2

    1 2

    1
    0_0402_5% HDA_RST_AUDIO# MIC_INR 2 1 MIC_INL
    R579 R580 0_0402_5% R578
    1 @ 2 1 4.7K_0402_5%
    0_0402_5% C584
    @

    2
    1 @ 2 100P_0402_50V8J MIC1
    2 1 C642 1 2 2.2U_0603_10V7K MIC_INR
    J10 2MM 2 GNDA
    GND GNDA C643 1 2 2.2U_0603_10V7K MIC_INL
    WM-64PCY_2P
    45@ @

    EC Beep [40] BEEP# 2 1 wide 20MIL R01


    D17 RB751V_SOD323 JSPK1
    R582 SPK_R1- L40 1 2 0_0603_5% SPK_R1-_CONN 1
    1
    ICH Beep [14] HDA_SPKR 2 1PC_BEEP1 1 2 1 2 PC_BEEP SPK_R2+ L41 1 2 0_0603_5% SPK_R2+_CONN 2
    33_0402_5% C645 0.1U_0402_16V4Z SPK_L1- L42 0_0603_5% SPK_L1-_CONN 2
    1 2 3
    D30 RB751V_SOD323 SPK_L2+ L43 0_0603_5% SPK_L2+_CONN 3
    1 2 4
    4
    1

    5
    R585 GND1
    6
    PC Beep

    1000P_0402_50V7K

    1000P_0402_50V7K

    1000P_0402_50V7K

    1000P_0402_50V7K
    10K_0402_5% GND2
    A 1 1 1 1 A
    ACES_88231-04001

    C649

    C650

    C647

    C651
    2

    ME@
    2 2 2 2

    Security Classification Compal Secret Data @ @ @ @ Compal Electronics,Ltd.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
    CX20671 Codec
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 39 of 57
    5 4 3 2 1
    +3VALW 3.3V +/- 5%
    +EC_AVCC Vcc
    1 1 1 1 1 1 R694 100K +/- 5%

    0.1U_0402_16V4Z
    C653

    0.1U_0402_16V4Z
    C654

    0.1U_0402_16V4Z
    C662

    0.1U_0402_16V4Z
    C655

    1000P_0402_50V7K
    C657

    1000P_0402_50V7K
    C658
    L44 1 2
    +3VALW +EC_AVCC
    FBM-11-160808-601-T_0603 2 1 Board ID R695 VAD_BID min V AD_BID typ VAD_BID max
    C656 2 2 2 2 2 2
    C659
    0.1U_0402_16V4Z 0 0 0 V 0 V 0 V EVT

    111
    125
    1000P_0402_50V7K

    22
    33
    96

    67
    9
    1 2 1 ECAGND 2 U31
    1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
    L45 FBM-11-160808-601-T_0603

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AVCC
    2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
    3 33K +/- 5% 0.712 V 0.819 V 0.875 V MP
    1 21 CPU1.5V_S3_GATE
    [19] GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# CPU1.5V_S3_GATE [10]
    [19] KB_RST# 2 23 BEEP# [39]
    KBRST#/GPIO01 BEEP#/PWM2/GPIO10 PCH_DPWROK
    [14] SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 PCH_DPWROK [16]
    4 27 ACOFF +3VS +3VALW
    [14,34] LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF [45,47]
    [14,34] LPC_AD3 5 LAD3

    2
    LPC_AD2 7 PWM Output
    [14,34] LPC_AD2 LAD2

    1
    LPC_AD1 8 63 BATT_TEMP
    [14,34] LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP [46] 100K_0402_1%
    LAD0 LPC & MISC
    [14,34] LPC_AD0 10 64
    BATT_OVP/AD1/GPIO39 R588 R694
    2 1 2 1 65 ADP_I [46,47]
    ADP_I/AD2/GPIO3A
    @ C660 22P_0402_50V8J @ R589 10_0402_5%
    [18] CLK_PCI_LPC 12 AD Input 66 IMVP_IMON [53]
    10K_0402_5%

    1
    PCICLK AD3/GPIO3B BRDID @ BRDID
    [18,34,35] BUF_PLT_RST# 13 75

    2
    EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_FAN_PWM
    +3VALW 1 2 37 ECRST# SELIO2#/AD5/GPIO43 76 R01

    2
    R590 47K_0402_5% EC_SCI# 20
    [19] EC_SCI# SCI#/GPIO0E
    2 38 R695
    CLKRUN#/GPIO1D
    68 8.2K_0402_5%
    C661 DAC_BRIG/DA0/GPIO3C CHG_ON# +3VALW
    EN_DFAN1/DA1/GPIO3D 70 CHG_ON#
    0.1U_0402_16V4Z DA Output 71 IREF
    IREF [47]

    1
    1 KSI0 IREF/DA2/GPIO3E +3VALW
    55 72 CHGVADJ [47]
    KSI1 KSI0/GPIO30 DA3/GPIO3F
    56 KSI1/GPIO31
    KSI2 57 EC_MUTE# R593 1 2 10K_0402_5%
    KSO[0..15] KSI3 KSI2/GPIO32
    [56] KSO[0..15] [56] KSI3 58
    KSI3/GPIO33 PSCLK1/GPIO4A
    83 EC_MUTE# [39] 6/19 Add BRDID
    KSI4 59 84 USB_ON# USB_ON# R594 1 2 10K_0402_5%
    KSI[0..7] [56] KSI4 KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# [38,42,43] +5VS
    60 85
    [56] KSI[0..7] KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
    61
    KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
    86 CMOS_OFF# [31]
    KSI7 62 87 TP_CLK TP_CLK R591 1 2 4.7K_0402_5%
    KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK [56]
    +3VALW KSO0 39 88 TP_DATA
    KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA [56]
    R595 1 2 47K_0402_5% KSO1 KSO1 40 KSO1/GPIO21 7/23 Modify TP_DATA R592 1 2 4.7K_0402_5%
    KSO2 41
    KSO2/GPIO22
    R597 1 2 47K_0402_5% KSO2 KSO3 42 KSO3/GPIO23 SDICS#/GPXOA00 97 SYS_PWROK_EC [16]
    KSO4 43 98 CE_EN_EC 2 1
    KSO5 KSO4/GPIO24 SDICLK/GPXOA01 CE_EN [31] BATT_TEMP
    KSO5/GPIO25 Int. K/B
    0_0402_5% R746 +3VALW
    ENE UPDATE 08/10/21 KSO6
    44
    45 KSO6/GPIO26 Matrix
    SDIDO/GPXOA02
    SDIDI/GPXID0
    99
    109 LID_SW#
    ME_FLASH [14]
    LID_SW# [56]
    1
    C663
    2
    100P_0402_50V8J
    KSO7 46 SPI Device Interface FRD#SPI_SO 2 1 ACIN 1 2
    +3VS +3VALW KSO8 KSO7/GPIO27 100K_0402_1%@ R599 C664 100P_0402_50V8J
    47 KSO8/GPIO28
    R600 KSO9 48 119 FRD#SPI_SO
    KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO [41]
    1 2 EC_SMB_CK1 KSO10 49 120 FWR#SPI_SI FSEL#SPICS# 2 1
    KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR#SPI_SI [41]
    4.7K_0402_5% 50
    KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
    126 SPI_CLK [41]
    100K_0402_1%@ R603
    R604 KSO12 51 128 FSEL#SPICS#
    EC_SMB_DA1 KSO13 KSO12/GPIO2C SPICS# FSEL#SPICS# [41]
    R601 R602 1 2 52
    4.7K_0402_5% KSO14 KSO13/GPIO2D R737
    2.2K_0402_5% 2.2K_0402_5% 53 KSO14/GPIO2E
    KSO15 54 73 H_PROCHOT#_EC 0_0402_5%
    KSO16 KSO15/GPIO2F CIR_RX/GPIO40 H_PECI_R R665 1 VR_HOT#
    81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 2 43_0402_1% H_PECI [6,19] [46,53] VR_HOT# 2 1 H_PROCHOT# [6]
    EC_SMB_CK2 [56] KSO16 KSO17 82 89
    EC_SMB_DA2 [56] KSO17 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0# FSTCHG [47]
    90 CHARGE_LED0# [56]
    BATT_CHGI_LED#/GPIO52

    1
    CAPS_LED# D
    1 1 91 CAPS_LED# [43]
    EC_SMB_CK1 CAPS_LED#/GPIO53 H_PROCHOT#_EC
    @ @
    [46] EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 PWR_LED# [43,56] 2
    C665 C666 EC_SMB_DA1 78 93 CHARGE_LED1# G
    [46] EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 CHARGE_LED1# [56]
    100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON Q37 S
    [15,24,37] EC_SMB_CK2 SYSON [44,49]

    3
    2 2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 2N7002_SOT23
    [15,24,37] EC_SMB_DA2 80 121 VR_ON [53]
    SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN
    127 ACIN [16,24,47]
    AC_IN/GPIO59
    0_0402_5% R747
    [16] SLP_S3# 6 100 EC_RSMRST# [16] 2 1
    PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT#
    +3VS
    [16] SLP_S5# 14
    PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04
    101 EC_LID_OUT# [15] 7/23 Modify @ 7/28 Modify
    EC_SMI# 15 102 EC_ON @
    [19] EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON [43,48]
    16 103 D18 RB751V_SOD323
    LID_SW#/GPIO0A EC_SWI#/GPXO06 BATT_SEL_EC [47]
    1

    17 104 PCH_POK_EC 1 2 PCH_POK


    SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PCH_POK [16]
    18
    PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
    105 BKOFF# [31]
    R605 SUSWARN# 19 GPIO 106 RF_LED# 1 2 1 2
    [16] SUSWARN# EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_LED# [56] +3VS
    10K_0402_5% INVT_PWM 25 107 PCH_APWROK [16] R607 R608 10K_0402_5%
    [31] INVT_PWM EC_THERM#/GPIO11 GPXO10
    EC_TACH 28 108 SA_PGOOD [50] 0_0402_5% @
    [37] EC_TACH
    2

    EC_TACH ODD_DA# FAN_SPEED1/FANFB1/GPIO14 GPXO11


    [18,56] ODD_DA# 29 FANFB2/GPIO15
    EC_TX_P80_DATA 30
    [34,41] EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16
    [34,41] EC_RX_P80_CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# [16]
    32 112 +3VALW
    [43] ON/OFF# EC_FAN_PWM ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL [31]
    [37] EC_FAN_PWM 34 114 EAPD [39]
    PWR_LED#/GPIO19 GPXID3 NOVO#
    [43] NUM_LED# 36
    NUMLED#/GPIO1A GPI GPXID4
    115 NOVO# [43]

    2
    116 SUSP#
    GPXID5 PBTN_OUT# SUSP# [10,26,44,49,51,52]
    117 R606
    GPXID6 PBTN_OUT# [16]
    118 10K_0402_5%
    @ EC_RTCX1 122 GPXID7
    SUSCLK_R 123 XCLK1
    [16] SUSCLK 2 1 124

    1
    0_0402_5% R611 XCLK0 V18R
    1
    AGND
    GND
    GND
    GND
    GND
    GND
    1

    C667
    1

    4.7U_0805_10V4Z 2 1
    R740 C93 KB930QF A0 LQFP 128P 2 0_0402_5% R609 LAN_WAKE# [35]
    11
    24
    35
    94
    113

    69

    100K_0402_5% 20P_0402_50V8
    2

    2 1
    2

    ECAGND

    0_0402_5%@ R610
    @
    R01 @ EC_PME#
    7/21 modify 1 3

    S
    PCI_PME# [18]
    Q102 @
    2N7002_SOT23

    G
    2
    +3VALW

    EC_RTCX1 1 @ 2 R708 0_0402_5% PCH_RTCX1_OUT [14]


    1 2 SUSCLK_R 1 @ 2 R709 0_0402_5% PCH_RTCX2_OUT [14]
    R120 10M_0402_5%
    @
    6/24 Update R708,R709 must be close Y5
    32.768KHZ_12.5PF_9H03200413
    1

    4
    18P_0402_50V8J

    Y5
    OSC

    OSC

    1 1
    C367
    C347 18P_0402_50V8J
    NC

    NC

    2 2
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    BIOS & EC I/O Port
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    6/15 add XTAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Custom
    LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 40 of 57
    FOR EC 256KB SPI ROM
    (150mil PACKAGE)
    +3VALW
    20mils
    1

    1
    C699
    0.1U_0402_16V4Z R617
    2 10K_0402_5%

    2
    U33
    [40] FSEL#SPICS#
    FSEL#SPICS# 1 8
    FRD#SPI_SO R618 1 SPI_SO CS# VCC HOLD#
    [40] FRD#SPI_SO 2 15_0402_5% 2 DO HOLD# 7 R619 0_0402_5%
    3 6 SPI_CLK_R 1 2 SPI_CLK
    WP# CLK SPI_CLK [40]
    4 5
    GND DIO R620
    MX25L2005CMI-12G SOP SPI_SI_EC 1 2 15_0402_5% FWR#SPI_SI SPI_CLK_R
    FWR#SPI_SI [40]

    Colse to EC
    1
    @
    C700
    EC DEBUG PORT 10P_0402_50V8J
    2

    1
    JP3 EMI
    +3VALW 1
    EC_TX_P80_DATA 2
    [34,40] EC_TX_P80_DATA EC_RX_P80_CLK 2
    [34,40] EC_RX_P80_CLK 3 3
    4
    4
    ACES_85205-0400
    ME@
    FD1 FD2 FD3 FD4
    1 1 1 1

    H_3P8
    H1 H2 H3 H4
    HOLEA HOLEA HOLEA HOLEA

    1
    H_3P3 H_3P0x4P5N H_3P0N
    H6 H5
    HOLEA H15 H16 HOLEA
    HOLEA HOLEA

    1
    1

    1
    H_2P8
    H12 H11 H10 H9 H13 H8 H7
    H_3P0
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H14
    HOLEA

    1
    R01

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LED/EC SPI ROM
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 41 of 57
    A B C D E

    1 1

    WCM-2012-900T_4P
    USB20_N2 4 3 USB20_N2_C
    4 3

    USB20_P2 1 2 USB20_P2_C
    1 2
    L63 @
    Left USB Conn.
    +USB_VCCC
    W=80mils JUSB2
    1 VCC
    USB20_N2 2 R862 1 0_0402_5% USB20_N2_C
    +5VALW (220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00) 1
    [18] USB20_N2
    USB20_P2 2 R863 1 0_0402_5% USB20_P2_C
    2
    3
    D-
    [18] USB20_P2 D+
    4 GND
    C702

    PJDLC05_SOT23-3
    470P_0402_50V7K 5
    +USB_VCCC 2 D21 GND1
    E-SATA COMBO 6 GND2
    U34 @ 7
    1 8
    RIGHT USB PORT 8
    GND3
    C703 0.1U_0402_16V4Z GND OUT GND4
    2 IN OUT 7
    2 1 3 6 SUYIN_020173GR004M58BZL
    USB_ON# 4 IN OUT
    [38,40,43] USB_ON# EN OC# 5 USB_OC1# [18]
    APL3510BKI_SO8 ESATA and USB Conn. ME@

    1
    2 Low Active 2
    1
    C704 +USB_VCCC
    @ 1000P_0402_50V7K W=80mils
    +USB_VCCC
    2
    1
    USB20_N3_C 1
    + C706 C705 0_0402_5% JESAT1
    USB20_P3_C
    WCM-2012-900T_4P
    220U_6.3V_M 470P_0402_50V7K
    USB20_N3 2 R865 1USB20_N3_C
    1
    2
    VBUS
    USB USB
    [18] USB20_N3 D-
    3

    2 2
    PJDLC05_SOT23-3

    USB20_N3 4 3 USB20_N3_C USB20_P3 2 1USB20_P3_C 3


    D22
    @
    4 3 [18] USB20_P3
    0_0402_5% R864 4
    D+
    GND
    A+ = RXP
    USB20_P3 1 2 USB20_P3_C 5
    1
    L64 @
    2
    [14] SATA_ITX_DRX_P4 SATA_ITX_DRX_P4 R627
    SATA_ITX_DRX_N4 R628
    1 ESATA@2 0_0402_5% SATA_ITX_DRX_P4_R
    0_0402_5% SATA_ITX_DRX_N4_R
    6
    GND
    A+ ESATA
    A- = RXN
    [14] SATA_ITX_DRX_N4 1 2 7 A-
    ESATA@ ESATA@ ESATA_DET#_CONN 8 12
    SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 GND SHIELD
    [14] SATA_DTX_C_IRX_N4 1 C707 SATA_DTX_IRX_N4 R629 1 ESATA@2 0_0402_5% SATA_DTX_IRX_N4_R 9 B- SHIELD 13
    SATA_DTX_C_IRX_P4 2 1 C708 SATA_DTX_IRX_P4 R630 1 2 0_0402_5% SATA_DTX_IRX_P4_R 10 14
    1

    [14] SATA_DTX_C_IRX_P4 0.01U_0402_16V7K ESATA@ ESATA@ B+ SHIELD


    11 15
    GND SHIELD
    FOX_3Q38111-RB1C3-7HC
    B- = TXN
    +5VALW 0_0402_5% 2 R866 1 ESATA_DET#_CONN
    [19] ESATA_DET#
    1 ESATA@ B+ = TXP
    1

    BT@ R631
    BT MODULE CONN C735
    0.1U_0402_16V4Z
    2 R867 1
    100K_0402_5% 2 @ @ 0_0402_5%
    3 C709 3
    0.1U_0402_16V4Z
    2

    1 R632 2 1 2
    100K_0402_5% +3VS +3VS
    1

    BT@ BT@
    @ R877
    1

    2
    0_0402_5% +3VS_BT 1 2
    OUT

    2
    R633
    R01
    2

    Q104 @ 4.7K_0402_5% C710 C711 R634 R635


    2 +3VS AO3413_SOT23-3 R583 BT@ 0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7K_0402_5% 4.7K_0402_5%
    [19] BT_OFF# IN 2 @ 1 @
    Q103 0_0603_5% 30mils @ @
    GND

    1
    S

    DTC124EKAT146_SC59-3 3 1 2 1 U35

    1
    BT@ 1 7 6
    BT@ 0.1U_0402_16V4Z EN VCC
    10
    3

    C712 SATA_ITX_DRX_P4 VCC


    1 16
    G
    2

    BT@ SATA_ITX_DRX_N4 RX_0P VCC


    2 RX_0N VCC 20
    2
    [56] BT_LED#
    Q105 JBT1 SATA_DTX_IRX_P4 5 9
    TX_1P D0
    1

    DTC124EKAT146_SC59-3 1 SATA_DTX_IRX_N4 4 8
    @ 1 TX_1N D1
    2
    OUT

    2
    [18] USB20_P13 USB20_P13 3 3 15 SATA_ITX_DRX_P4_R
    USB20_N13 3 GND TX_0P SATA_ITX_DRX_N4_R R636 R637
    [18] USB20_N13 4 4 13 GND TX_0N 14
    2 BTON_LED 5 7 17 0_0402_5% 0_0402_5%
    IN BT_ACTIVE 5 G1 GND SATA_DTX_IRX_N4_R @ @
    [34] BT_ACTIVE 6 8 18 12
    GND

    6 G2 GND RX_1N SATA_DTX_IRX_P4_R


    19 11

    1
    ACES_87213-0600G GND RX_1P
    21 PAD
    4 ME@ 4
    3

    SN75LVCP412RTJR_QFN20_4X4
    @

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB ports/BT/E-SATA
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 42 of 57
    A B C D E
    ON/OFF switchSW 3
    1 3
    Power Button Power Bottom Board Conn. 8pin
    2 4
    SMT1-05_4P

    6
    5
    +3VALW

    TOP Side J11 +5VALW

    2
    1 2

    SHORT PADS R638 JPW RB1


    Bottom Side 100K_0402_5% 1 Card Reader/Audio Jack SB CONN
    D23 1
    [40] NUM_LED# 2

    1
    ON/OFF# 2
    3 ON/OFF# [40] [40] CAPS_LED# 3 3
    ON/OFFBTN# 1 [40,56] PW R_LED# 4 JCR1
    51_ON# 4 HP_OUTL
    2 51_ON# [45] 5 5 [39] HP_OUTL 1 1
    NOVO_BTN# 6 2 HP_OUTR
    6 [39] HP_OUTR 2
    DAN202UT106_SC70-3 ON/OFFBTN# 7 [39] PLUG_IN 3 PLUG_IN
    7 3
    8 8 R01 EXT_MIC_L
    4
    5
    4
    [39] EXT_MIC_L 5
    9 EXT_MIC_R 6
    GND [39] EXT_MIC_R 6
    10 [39] MIC_JD MIC_JD 7
    GND 7
    8 8
    USB20_P11 2 R871 1 0_0402_5% USB20_P11_C 9
    D [18] USB20_P11 9

    1
    USB20_N11 2 R870 1 0_0402_5% USB20_N11_C10
    +USB_VCCA [18] USB20_N11 10
    EC_ON 2 +3VS 11
    [40,48] EC_ON 11
    G ACES_88058-080N W=80mils 12
    Q106 +USB_VCCA 12
    S 13

    3
    13
    2

    2N7002_SOT23-3 ME@ 1 14
    R639 USB20_P10 2 R875 0_0402_5% USB20_P10_C 15 14
    1 [18] USB20_P10 1 15
    10K_0402_5% C734 + USB20_N10 2 R876 1 0_0402_5% USB20_N10_C16
    [18] USB20_N10 16
    C733 17
    150U_B2_6.3VM_R35M 470P_0402_50V7K 17
    18
    1

    2 2 18
    19 19
    20 20
    21 G1
    W CM-2012-900T_4P 22
    +3VS USB20_N11 4 USB20_N11_C G2
    4 3 3
    R01

    1000P_0603_50V7K
    R01

    C635
    NOVO_BTN# ON/OFFBTN# USB20_P11 1 2 USB20_P11_C ACES_85201-2005N
    +3VALW 1 2

    2
    @ L67 @
    EMI request ME@

    2
    D24
    2

    PJSOT24C 3P C/A SOT-23


    R642 @ W CM-2012-900T_4P
    100K_0402_5% USB20_N10 4
    4 3 3 USB20_N10_C 07/16

    1
    D26
    FOR PIWG4 USE
    1

    NOVO# 2 USB20_P10 1 2 USB20_P10_C


    [40] NOVO# 1 2
    1 NOVO_BTN#
    51_ON# 3 L68 @

    DAN202UT106_SC70-3
    EMI REQUEST 1ST = SCA00000E00
    2ST = SCA00000R00

    +5VALW 07/16
    FOR PIWG4 USE
    +USB_VCCA
    U36
    1 8 RIGHT USB PORT X1 Right USB Conn. R01
    C713 0.1U_0402_16V4Z GND OUT
    2 IN OUT 7 JUSB3
    +USB_VCCA
    2 1 3
    USB_ON# 4 IN OUT 6 W=80mils
    [38,40,42] USB_ON# EN OC# 5 USB_OC0# [18,38] 1 1
    +USB_VCCA 2
    APL3510BKI_SO8 USB20_N0 2
    [18] USB20_N0 2 R868 1 0_0402_5% USB20_N0_C 3 3
    1 1 USB20_P0 2 R869 1 0_0402_5% USB20_P0_C 4
    [18] USB20_P0 4
    1 5 5
    C716 C714 + C715 6
    @ 1000P_0402_50V7K 470P_0402_50V7K 6
    150U_B2_6.3VM_R35M 2
    7 GND
    2 2
    8 GND
    ACES_88058-060N
    6/9 change to B2 150U
    ME@
    W CM-2012-900T_4P
    (220uF_6.3V_5.8L_ESR17m)*1=(SF000001500) USB20_N0 4 3 USB20_N0_C USB20_N0_C
    4 3
    USB20_P0_C
    USB20_P0 1 2 USB20_P0_C
    1 2

    2
    PJDLC05_SOT23-3
    L66 @ D25
    @

    1
    Security Classification Compal Secret Data Compal Electronics,Ltd.
    Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
    other IO connector
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 43 of 57
    A B C D E

    +1.5V to +1.5VS
    +5VALW TO +5VS +3VALW TO +3VS
    +1.5V +1.5VS

    +5VALW

    S
    +5VS +3VALW +3VS

    D
    3 1
    U38 U39 1 1 1

    1
    8 1 8 D 1 Q8
    D S S C717 C718 C719

    G
    1 7 2 1 1 1 7 D S 2 1 1

    2
    D S

    1
    6 3 6 D 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R643
    C720 D S C721 C722 C723 S 3 C724 C725 2 2 2 470_0603_5%
    5 D G 4 5 D G 4
    10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R644 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R645 SI2301BDS-T1-E3_SOT23-3 @

    2
    1 2 2 2 2 2 2 1
    SI4800BDY-T1-E3_SO8 470_0603_5% SI4800BDY-T1-E3_SO8 470_0603_5%
    @ @

    1 2

    1 2

    1
    +3VALW D
    +VSB D +VSB D
    2 SUSP
    2 SUSP 2 SUSP G

    1
    G G S Q109

    3
    S Q107 S Q108 2N7002_SOT23

    3
    R646 2N7002_SOT23 R647 2N7002_SOT23 100K_0402_5% @
    20K_0402_5% @ 47K_0402_5% @ R648

    2
    5VS_GATE2 R649 15VS_GATE_R 2 R651 1 1.5VS_GATE

    2
    1 1 Q112 1 1
    1

    1
    D 10K_0402_5% D R650 D
    SUSP Q110 C726 SUSP Q111 C727 SUSP# 2 0_0402_5% C728 C729
    2 2 0_0402_5%
    G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K G 0.1U_0603_25V7K
    S 2 S @ 2 2N7002_SOT23S 2 2
    3

    3
    0.1U_0603_25V7K

    6/13 change SI4800 to SI2301

    2 2

    +RTCVCC +5VALW
    +5VALW

    1
    +1.8VS +1.5V +1.05VS +0.75VS +1.05VS @
    R652 R653 @
    100K_0402_5% 100K_0402_5% R654
    1

    1
    100K_0402_5%

    2
    SUSP
    [6,10,51] SUSP

    2
    R655 R656 R657 R658 R659 SYSON#
    470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 470_0603_5% Q117 Q119

    1
    @ @ @ @ DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
    1 2

    1 2

    1 2

    1 2

    1 2
    @

    OUT

    OUT
    D D D D D

    3
    2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP 3
    G G G G G 2 SYSON 2
    [10,26,40,49,51,52] SUSP# IN [40,49] SYSON IN
    S Q113 S Q114 S Q118 S Q115 S Q116

    GND

    GND
    3

    2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 3 2N7002_SOT23


    @ @ @ @

    3
    For Intel S3 Power Reduction.

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 44 of 57
    A B C D E
    5 4 3 2 1

    DC030006J00 VIN
    Precharge detector
    PF101 PL101 15.97V/14.84V FOR
    4 APDIN
    7A_24VDC_429007.WRML
    1 2 APDIN1
    SMB3025500YA_2P
    1 2
    ADAPTOR
    4
    3
    3

    1000P_0402_50V7K

    1000P_0402_50V7K
    100P_0402_50V8J

    100P_0402_50V8J
    2
    2

    1
    D D
    1 1 PreCHG PQ102
    TP0610K-T1-E3_SOT23-3

    2
    @ 4602-Q04C-09R 4P P2.5

    PC101

    PC102

    PC103

    PC104
    PR102
    JDCIN1 1K_1206_5% PD102
    1 2 2 1 3 1
    VIN
    PR103 LL4148_LL34-2
    1K_1206_5%
    1 2

    100K_0402_1%
    1

    1
    100K_0402_1%
    PR104

    PR105

    PR106
    1K_1206_5%

    2
    1 2

    PR107

    2
    1K_1206_5%
    1 2
    VIN

    100K_0402_1%
    1
    PD103 PQ103

    PR108
    LL4148_LL34-2 DDTC115EUA-7-F_SOT323-3

    1
    1
    PD101 PD104

    1 2
    LL4148_LL34-2 2
    2 1 [40,47] ACOFF 1 2
    BATT+

    1
    3 PQ104
    PR109 PR110 [48] +5VALWP DDTC115EUA-7-F_SOT323-3
    68_1206_5% 68_1206_5% RB715F_SOT323-3
    PQ101 VS 2

    3
    C TP0610K-T1-E3_SOT23-3 C
    2

    2
    N1 3 1
    0.22U_0603_25V7K

    3
    1

    PR101 PC106
    PC105

    100K_0402_5% 0.1U_0603_25V7K
    B+
    2

    PR111
    2

    22K_0402_5% PR112
    1 2 2.2M_0402_5%
    [43] 51_ON#
    2 1

    VL
    VS

    @ 499K_0402_1%
    @ 0.01U_0402_25V7K

    1
    PR113
    1

    1
    PC107
    PR114
    100K_0402_1%

    2
    2
    PU101A

    8
    PD105 LM393DG_SO8
    2 3

    P
    [46,48] MAINPWON +
    1 1 O

    205K_0402_1%

    499K_0402_1%

    0.01U_0402_25V7K
    3 2
    -

    1
    +RTCBATT ACON
    - +

    1
    1000P_0402_50V7K

    PR115

    PR116

    PC110
    JRTC1 PR117 PR118 @ RB715F_SOT323-3

    4
    1

    1
    560_0603_5% 560_0603_5%

    PC109
    2 1 +RTCBATT 1 2 1 2 PC108
    +CHGRTC

    2
    B 0.1U_0603_25V7K B

    PRG++ 2

    2
    ML1220T13RE
    45@
    2N7002W-T/R7_SOT323-3
    1 2 PR119 PR120
    +3VLP [47] PACIN

    1
    34K_0402_1% D PQ105 47K_0402_5%
    2 1 2 2 1
    PD106 6251VREF G

    1
    RB751V-40_SOD323-2 S

    3
    PQ106

    2
    66.5K_0402_1%
    DTC115EUA_SC70-3

    PR121
    2

    +5VALWP

    3
    ACIN BATT ONLY
    Precharge detector Precharge detector
    Min. typ. Max. Min. typ. Max.
    L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
    A A
    H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V

    Security Classification Compal Secret Data Compal Electronics, Inc.


    2010/01/25 2010/12/31 Title
    Issued Date Deciphered Date PWR DCIN / Vin Detector /Pre-charge
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIWG4 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 45 of 57
    5 4 3 2 1
    5 4 3 2 1

    PH201 under CPU botten side :


    VMB2 VMB
    CPU thermal protection at 92 degree C
    PF201 PL201
    JBATT1 12A_65V_451012MRL SMB3025500YA_2P Recovery at 56 degree C
    1 1 2 1 2 BATT+
    1
    2 2
    D EC_SMCA D
    3 3
    4 EC_SMDA
    4
    5 5

    1
    6
    6

    1
    7 PC201 PC202
    7

    100_0402_1%

    100_0402_1%
    8 1000P_0402_50V7K 0.01U_0402_25V7K VL

    2
    GND
    9 ADP_I [40,47]
    GND
    VL

    PR201

    PR202
    TYCO_1775789-1
    2

    2
    @

    1
    @ 0_0402_5%

    2
    PR222
    PC203 PR203 PR204
    0.1U_0603_25V7K 10K_0402_1% 21.5K_0402_1% PR205

    2
    VL @ 100K_0402_1%

    2
    @ 100K_0402_1%
    PU201

    1
    1
    EC_SMB_CK1 [40] 1 8
    VCC TMSNS1

    PR221

    2
    [40,53] VR_HOT#

    @ 2N7002KW_SOT323-3
    2 7
    GND RHYST1 PR206
    EC_SMB_DA1 [40]
    3 6 9.76K_0402_1%

    2
    OT1 TMSNS2

    1
    D

    PQ204

    @ 47K_0402_1%
    1 2 +3VALW 2 4 5

    1
    OT2 RHYST2

    2
    PR207 G

    1
    PR208
    6.49K_0402_1% S G718TM1U_SOT23-8

    3
    PR223 PH201
    0_0402_5% 100K_0402_1%_TSM0B104F4251RZ
    1 2 BATT_TEMP [40] A/D

    1
    PR209

    2
    10K_0402_5% MAINPWON [45,48]

    1
    C C
    PH202
    @ 100K_0402_1%_TSM0B104F4251RZ

    2
    VS

    +3VALW +3VALW
    0.01U_0402_25V7K
    1

    PC204

    VMB2
    PR210 PR211
    2

    100K_0402_1% 10K_0402_1%
    PR212 PR213
    2

    649K_0402_1% 5.1M_0402_5%
    1

    1 2 BATT_OUT [47]
    PR214 PQ202
    10K_0402_1% TP0610K-T1-E3_SOT23-3
    8

    1 2 PQ201
    1

    D 2N7002KW_SOT323-3
    5
    P

    +
    7 2 B+ 3 1 +VSBP
    PR215 O G
    6
    -
    G
    2

    100K_0402_1%
    B B

    0.22U_0603_25V7K
    232K_0402_1% PU101B S
    3

    1
    LM393DG_SO8
    4

    1
    PR216

    PC205
    PC206
    0.1U_0603_25V7K
    1

    2
    2

    2
    2 1 PR218
    6251VREF VL 22K_0402_1%
    PR217 1 2
    10K_0402_1%
    2

    PR219
    100K_0402_1%

    PR220
    1

    1
    1K_0402_5% D PJ201
    1 2 2 PQ203 @ JUMP_43X39
    [48] SPOK
    G 2N7002W-T/R7_SOT323-3 1 1
    1U_0402_6.3V6K
    +VSBP 2 2 +VSB
    S

    3
    1

    PC207
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR-BATTERY CONN/OTP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIWG4 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 46 of 57
    5 4 3 2 1
    5 4 3 2 1

    P3
    B+
    P2 65W:0.020
    PQ301 PQ302 90W:0.015
    AO4407A_SO8 AO4407A_SO8
    PR302
    VIN 8
    7
    1
    2
    1
    2
    8
    7 0.015_1206_1% CHG_B+
    6 3 3 6 PJ301
    5 5 1 4 2 1 PQ303
    2 1 AO4407A_SO8
    2 3 @ JUMP_43X118 1 8
    VIN

    4
    2 7
    3 6

    2200P_0402_50V7K
    PQ304

    0.1U_0603_25V7K
    5

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    D D

    2
    200K_0402_5%
    1

    2
    PC302
    PR303

    200K_0402_1%
    0.1U_0603_25V7K

    PC306

    4
    1
    PR301

    PC303

    PC304

    PC305
    DTA144EUA_SC70-3 @47K_0402_1% CSIN DISCHG_G

    PC301

    PR304
    CSIP

    1
    @ PR305

    1
    PQ317B 47K_0402_1%
    VIN PreCHG
    2

    2
    2 @ 2N7002KDW -2N_SOT363-6 1 2

    2
    VIN

    2ACOFF-1
    @ 191K_0402_1%

    2
    1

    1
    2 5 BATT_OUT [46] PR307 PR308

    1DISCHG_G-1
    PR306
    191K_0402_1% 10K_0402_1%
    1

    2
    PD302

    4
    @ 1SS355_SOD323-2 PR309

    1
    BATT_ON 2 P2-1 PQ317A PD301 @ 200K_0402_1%

    2
    PQ305 @ 2N7002KDW -2N_SOT363-6 6251_VDD RB751V-40_SOD323-2 ACSETIN PQ306
    DTC115EUA_SC70-3

    1 1

    1
    1
    DTC115EUA_SC70-3 PR310

    1
    0_0402_5% PR312 PD303
    3

    FSTCHG
    2 1 PR311 14.3K_0402_1% PC307 @ 1SS355_SOD323-2

    2.2U_0603_6.3V6K
    1 [40] FSTCHG 10_1206_5% 1000P_0402_25V8J 2 1 2

    2
    6

    2
    PC308

    2
    1

    PR313
    150K_0402_1%

    2200P_0402_50V7K
    2

    2
    PR314

    PQ307A PU301 PC309 PQ309

    100K_0402_5%
    10K_0402_1%

    1
    PC322
    2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K
    12

    1
    D D @ 2N7002W -T/R7_SOT323-3

    PR316
    6251_DCIN

    0.1U_0603_25V7K
    1 VDD DCIN 24 2 1

    1
    2 PACIN

    100K_0402_1%
    2 BATT_OUT [46]
    1

    1
    PC310
    G G

    1
    PR315
    ACSETIN

    BATT_ON
    S 2 23 ACPRN [48] S
    3

    3
    PQ308 ACSET ACPRN PR317

    2N7002W-T/R7_SOT323-3

    2
    P2-2

    2N7002KW _SOT323-3 20_0402_5%

    5
    6
    7
    8
    C 6251_EN 6251_CSON CSON C
    3 EN CSON 22 1 2

    1
    D

    PQ310
    PC311

    AO4466L_SO8
    3

    PQ311
    0.047U_0402_16V7K ACPRN 2 @
    PR319 CELLS 4 21 6251_CSOP 1 2 CSOP G

    2
    47K_0402_1% PQ307B CELLS CSOP PR318 S

    3
    PACIN 1 2 5 2N7002KDW -2N_SOT363-6 PC312 6800P_0402_25V7K 20_0402_5% 4
    [45] PACIN
    1 2 6251_ICOMP 5 20 6251_CSIN 2 1
    ICOMP CSIN

    2
    PC313 PR320
    4

    PC314 PR321 10K_0402_1% 0.1U_0402_16V7K 20_0402_5%


    1 26251_VCOMP-1
    1 2 6251_VCOMP 6 19 6251_CSIP 1 2 PL301 PR324

    3
    2
    1
    VCOMP CSIP
    1

    PQ312 PR322 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%


    DTC115EUA_SC70-3 0.01U_0402_25V7K 2_0402_5% BATT+
    1 26251_ICM 7 ICM PHASE 18 LX_CHG 1 2 CHG
    1 4
    PR325 PR323

    5
    6
    7
    8
    [40,45] ACOFF 1 2ACOFF-1 2 [40,46] ADP_I 100_0402_1% 2 3

    1
    PQ313
    10K_0402_5% DH_CHG

    AO4466L_SO8

    4.7_1206_5%
    8 VREF UGATE 17

    PR326
    PR327 PR328 PC316

    10U_0805_25V6K
    1 2 6251VREF
    1

    154K_0402_1% PC315 0_0603_5% 0.1U_0603_25V7K

    10U_0805_25V6K
    6251_CHLIM BST_CHG 1 BST_CHGA 2

    16251_SN
    PR343 2 1 0.1U_0402_16V7K 9 16 2 1
    3

    [40] IREF CHLIM BOOT

    1
    PC318
    0_0402_5% PR329 4

    1
    PC317
    25.5K_0402_1% PD304
    0.01U_0402_25V7K

    2 6251_ACLIM 6251_VDDP
    2N7002KW_SOT323-3

    1 10 15 RB751V-40_SOD323-2
    2

    2
    ACLIM VDDP
    1

    6251VREF

    2
    1
    PC319

    PQ314 PR330

    680P_0603_50V7K
    1 2 6251_VDD

    3
    2
    1
    1

    PC320
    100K_0402_1% 6251_VADJ
    11 14 DL_CHG

    2
    VADJ LGATE

    1
    2 PR332 PR331
    [46] BATT_OUT
    2

    G 3.9K_0402_1% 4.7_0402_5%
    2

    S 12 13 PC321
    3

    2
    GND PGND 4.7U_0805_6.3V6K
    2

    ISL6251AHAZ-T_QSOP24
    B PR333 B
    Connect to EC A/D Pin. 15.4K_0402_1%
    1 2
    [40] CHGVADJ
    1

    PR334
    31.6K_0402_1%
    CHGVADJ=(Vcell-4)/0.10627 3cell : GND
    6251_VDD 6251_VDD
    Vcell CHGVADJ UMA CP mode 4cell : VDD
    2

    4V 0V Vaclim=2.39*(1.4K/(1.4K+13.7K))=0.2376V 6251_VDD

    2
    Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) PR339 PR335 PR336
    4.2V 1.882V
    where Vaclim=0.2376V, Iinput=2.75A 10K_0402_1% @ 100K_0402_1%@ 100K_0402_1%
    1

    4.35V 3.2935V 1 2 ACIN [16,24,40]


    PR338

    1
    PR337 10K_0402_1% CELLS
    DIS CP mode 47K_0402_1%

    3
    CC=0.25A~3A PACIN
    2

    1 2

    Vaclim=2.39*(3.9K/(3.9K+16.9K))=0.478V
    IREF=1.016*Icharge PR340
    Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05)
    1

    0_0402_5% 2 5 2 1
    IREF=0.254V~3.048V where Vaclim=0.478V, Iinput=4A PR341

    2
    PR342 @ 0_0402_5%

    4
    [48] ACPRN
    VCHLIM need over 95mV 2 [40] BATT_SEL_EC
    14.3K_0402_1%
    2

    PQ316
    PQ315A PQ315B
    DTC115EUA_SC70-3 @ 2N7002KDW -2N_SOT363-6 @ 2N7002KDW -2N_SOT363-6
    3

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CHARGER
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PIWG4
    Date: Tuesday, August 17, 2010 Sheet 47 of 57

    5 4 3 2 1
    5 4 3 2 1

    Note:
    Use TPS51125 IC can remove RTC refernece LDO
    Use TPS51427 IC must keep RTC refernece LDO

    2VREF_8205 PJ401
    +3VALW P 2 2 1 1 +3VALW
    @ JUMP_43X118

    1U_0603_10V6K
    D D

    1
    PJ402

    PC402
    +5VALW P 2 1 +5VALW

    2
    2 1
    @ JUMP_43X118

    PR401 PR402
    13K_0402_1% 30K_0402_1%
    1 2 1 2

    PR403 PR404
    RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
    1 2 1 2
    PJ403 Typ: 175mA
    B+ 2 1 +3VLP
    2 1

    ENTRIP2

    ENTRIP1
    @ JUMP_43X118 PR405 PR406
    2200P_0402_50V7K

    2200P_0402_50V7K
    0.1U_0603_25V7K

    0.1U_0603_25V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    1

    110K_0402_1% 154K_0402_1%
    @ 680P_0402_50V7K
    PC401

    PC403

    PC411
    1 2 1 2

    4.7U_0805_10V6K
    1

    1
    PC404

    PC405

    PC406

    PC408

    PC409

    PC410
    2

    8
    7
    6
    5

    5
    6
    7
    8
    PU401 PQ402
    2

    2
    AO4466L_SO8

    PC407

    ENTRIP2

    FB2

    TONSEL

    FB1

    ENTRIP1
    REF
    1
    C PQ401 C
    25 P PAD
    AO4466L_SO8

    2
    4 4
    7 VO2 VO1 24
    SPOK [46]
    8 23 PR408 PC413
    PR407 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K
    1
    2
    3

    3
    2
    1
    1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
    0_0603_5% BOOT2 BOOT1
    PL401 PC412 UG_3V 10
    VFB=2.0V 21 UG_5V PL402
    4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH +-20% PCMC063T-4R7MN 5.5A
    1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
    +3VALWP PHASE2 PHASE1
    1

    8
    7
    6
    5

    1
    LG_3V LG_5V
    4.7_1206_5%

    12 19

    4.7_1206_5%
    LGATE2 LGATE1

    5
    6
    7
    8
    PQ403
    PR409

    PR410
    SKIPSEL
    AO4712_SO8 PR411 @

    VREG5
    0_0402_5%

    GND

    VIN
    MAINPW ON 2 RT8205EGQW _W QFN24_4X4

    NC
    EN
    1 1 1
    2

    2
    4
    + PC414 4 + PC416

    13

    14

    15

    16

    17

    18
    1

    1
    220U_6.3V_M PR412 220U_6.3V_M
    PC415
    680P_0603_50V7K

    499K_0402_1% AO4712_SO8

    680P_0603_50V7K
    2 PQ404 2

    PC417
    1 2
    2

    1
    2
    3

    2
    B+

    3
    2
    1
    1
    100K_0402_1%

    1U_0603_10V6K
    VL

    1
    PC418

    1
    PR413

    PC419
    Typ: 175mA

    4.7U_0805_10V6K
    B B

    2
    ENTRIP1 ENTRIP2
    2

    2
    RT8205_B+
    6

    1
    PQ405B
    PQ405A 2N7002KDW -2N_SOT363-6

    0.1U_0603_25V7K
    2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A

    2
    PC420
    +5VALWP OCP(min)=8.44A
    [45,46] MAINPWON
    1

    PR414
    0_0402_5%
    2 1

    PR415
    100K_0402_1%
    2 1
    VL
    1
    2N7002W-T/R7_SOT323-3

    PR418
    D
    1

    200K_0402_1%
    47] ACPRN
    PQ406

    2 1 2 1 2 2 PQ407
    G VS DTC115EUA_SC70-3
    S PR416
    40.2K_0402_1%

    2.2U_0603_10V7K
    3

    A A
    1

    100K_0402_1%
    1

    1
    PR417

    PC421

    3
    2

    [40,43] EC_ON
    2

    2
    PQ408
    DTC115EUA_SC70-3
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

    3VALWP/5VALWP
    3

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PIWG4
    Date: Tuesday, August 17, 2010 Sheet 48 of 57
    5 4 3 2 1
    A B C D

    1 1

    PJ505
    1.5_51117_B+ 2 1
    2 1 B+

    5
    6
    7
    8
    @ JUMP_43X118

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    1

    1
    PC502

    PC503
    @ PC504
    PQ501 680P_0402_50V7K
    AO4406AL 1N SO8

    2
    PR503
    267K_0402_1% 4
    PR501 1 2
    0_0402_5%
    1 2
    [40,44] SYSON

    3
    2
    1
    2
    47K_0402_5%

    PR504 PC505 PL502


    PR505

    0_0603_5% 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%

    15

    14
    +1.5VP
    1

    1
    PU501 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
    PC501 @

    EN/DEM

    NC

    BOOT
    .1U_0402_16V7K
    1

    2 13 DH_1.5V
    TON UGATE

    4.7_1206_5%
    1
    3 12 LX_1.5V 1
    VOUT PHASE

    5
    6
    7
    8

    PR506
    VFB=0.75V PQ502 + PC506
    4 VDD CS 11 +5VALW AO4456_SO8 220U_6.3V_M
    2 2
    5 10

    2
    FB VDDP 2
    DL_1.5V

    1000P_0603_50V7K
    6 PGOOD LGATE 9 4

    PGND
    PR507

    GND

    PC508
    100_0603_5%

    9.76K_0402_1%
    PR508
    1 2 @ PC509 PC507
    +5VALW 47P_0402_50V8J RT8209BGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K

    3
    2
    1

    2
    1 2
    1

    2
    PC510
    4.7U_0603_6.3V6K
    2

    PR509
    +1.5VP OCP(min)=15.6A
    1 2
    1.8VSP max current=4A
    10K_0402_1%
    1

    PR510
    10K_0402_1%
    2

    PJ501
    2 2 1 1

    @ JUMP_43X118

    PJ502 +1.5V
    +1.5VP 2 1
    2 1
    @ JUMP_43X118
    3 3

    PU502 PL503 PJ504


    4

    PJ503 1UH_PCMC063T-1R0MN_11A_20% +1.8VSP 2 1 +1.8VS


    LX_1.8V 2 1
    +5VALW 2 1 10 2 1 2
    PG

    2 1 PVIN LX +1.8VSP @ JUMP_43X118


    @ JUMP_43X118

    68P_0402_50V8J
    9 PVIN LX 3
    1

    1
    680P_0603_50V7K 4.7_1206_5%
    1

    1
    PC512
    PC511 8 SVIN
    PR511

    22U_0805_6.3VAM PR512
    6 30K_0402_1%
    2

    2
    FB

    22U_0805_6.3VAM

    22U_0805_6.3VAM
    5
    1 2

    EN 2

    1
    NC

    NC
    TP

    PC514

    PC515
    FB=0.6Volt
    [10,26,40,44,51,52] SUSP#
    PC513
    11

    2
    1 2 EN_1.8V
    2

    PR513 100K_0402_1%
    0.1U_0402_10V7K
    2

    PC516

    SY8033BDBC_DFN10_3X3
    1

    PR514
    1M_0402_5%
    FB_1.8V
    2
    1

    4
    PR515 4

    14.7K_0402_1%
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR-+1.5VP/+1.8VSP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PIWG4
    Date: Tuesday, August 17, 2010 Sheet 49 of 57
    A B C D
    5 4 3 2 1

    D D

    B+
    @ PJ601
    51117_VCCSAP_B+ 2 1
    2 1
    JUMP_43X118

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    PC602

    PC603
    1

    1
    5
    6
    7
    8
    PQ601

    2
    AO4466L_SO8

    C PR602 4 C
    280K_0402_1%
    1 2
    +VCCSAP OCP(min)=6.28A

    3
    2
    1
    EN_VCCSAP BST_VCCSAP

    PR601 PR603 PC604 PL601


    15

    14
    1

    0_0402_5% PU601 0_0603_5% 0.1U_0603_25V7K 2.2UH_PCMC063T-2R2MN_8A_20%


    [51] VCCPPWRGOOD 1 2 1 2 BST_VCCSAP-1
    1 2 1 2
    NC

    BOOT
    EN/DEM

    +VCCSAP
    1

    @ PR604 2 13 UG_VCCSAP
    TON UGATE

    1
    47K_0402_5% PC601 1
    @ 0.1U_0402_16V7K 3 12 LX_VCCSAP
    2

    VOUT PHASE

    5
    6
    7
    8
    PR605 + PC605
    2

    4 11 +5VALW 4.7_1206_5% 220U_6.3V_M


    VDD CS PQ602

    2
    5 10 AO4712_SO8 2
    FB VDDP

    2
    PR606 PJ602

    1
    100_0603_1% +3VS 6 9 LG_VCCSAP 4 PR607 +VCCSAP 2 1 +VCCSA
    PGOOD LGATE 2 1
    PGND

    1 2 PC606 0_0402_5% PR608


    GND

    +5VALW
    470P_0603_50V8J 1 2 VSSSA_SENSE [10] @ JUMP_43X118

    2
    2

    1
    PR610 0_0402_5%
    10K_0402_5%

    13K_0402_1%

    1
    1

    RT8209BGQW_WQFN14_3P5X3P5 PC607
    7

    3
    2
    1
    1

    4.7U_0805_10V6K
    PR609

    2
    PC608 0_0402_5%
    2

    4.7U_0603_6.3V6K PR611
    2

    2 1 SA_PGOOD [40]

    PR612
    PR613
    2K_0402_1%
    1 2 1 2 VCCSA_SENSE [10]
    VFB=0.75V
    10_0402_5%

    B B
    +3VS
    1

    PR615
    1

    PR614 15K_0402_1%
    30K_0402_1% PR616
    10K_0402_5%
    2

    PQ603 PR617
    2
    1

    D 2N7002W-T/R7_SOT323-3 10K_0402_5% PMBT2222A_SOT23-3


    2 2 1
    G PQ604 PR619
    1

    S 0_0402_5%
    3

    2 2 1
    PC609 PR618 @ VCCSA_SEL [10]
    1

    @ 4700P_0402_25V7K 100K_0402_5%
    2

    PR620
    2

    @ 10K_0402_5%
    2

    VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required


    0 0 0.9 V Yes/Yes
    0 1 0.8 V Yes/Yes
    1 1 0.75V No/Yes
    1 1 0.65V No/Yes
    A A

    Note:Use VCCSA_SEL to switch High & Low Level for VID[1]


    (ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR +VCCSAP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PIWG4
    Date: Tuesday, August 17, 2010 Sheet 50 of 57
    5 4 3 2 1
    5 4 3 2 1

    +1.5V

    1
    PJ701

    1
    D JUMP_43X118 D
    @

    2
    2
    PU701
    1 VIN VCNTL 6 +3VALW PJ702
    +0.75VSP 2 2 1 1 +0.75VS
    PC701 2 5
    GND NC

    1
    4.7U_0805_6.3V6K @ JUMP_43X118

    1
    3 7 PC702
    PR701 VREF NC

    2
    1K_0402_1% 4 8 1U_0603_10V6K
    VOUT NC
    9

    2
    PQ701 TP PJ703
    2N7002W -T/R7_SOT323-3 G2992F1U_SO8 2 1
    2 1
    PR702 @ JUMP_43X118

    0.1U_0402_16V7K
    D
    +0.75VSP

    1
    0_0402_5% +1.05VS_VCCPP PJ704 +1.05VS

    10U_0603_6.3V6M
    [6,10,44] SUSP

    PC703
    1K_0402_1%
    1 2 2 2 2 1 1

    10U_0603_6.3V6M
    1

    1
    PC705

    PC716
    G

    2
    1
    S PR703 @ JUMP_43X118

    3
    PC704

    2
    @ 1U_0402_6.3V6K

    2
    C C

    +1.05VS_VCCPP OCP(min)=20.75A

    PJ705
    1.05VS_B+ 2 1 B+

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    2 1
    B+
    @ JUMP_43X118

    1
    @ PC708

    PC706

    PC707

    100U_25V_M
    1

    5
    6
    7
    8
    680P_0402_50V7K
    PR704 +

    PC717
    2

    2
    267K_0402_1% PQ702
    1 2 AO4406AL 1N SO8
    PR705 2
    120K_0402_1% 4
    1 2
    6,40,44,49,52] SUSP#
    1

    PR706 PC710
    15

    14
    1

    PC709 PU702 0_0603_5% 0.1U_0603_25V7K PL702

    3
    2
    1
    .1U_0402_16V7K BST_1.05VS_VCCP
    1 2 1 2 1.0UH +-20% PCMC104T-1R0MN 20A
    EN/DEM

    NC

    BOOT
    2

    2 1 +1.05VS_VCCPP
    B DH_1.05VS_VCCP B
    2 TON UGATE 13

    1
    3 12 LX_1.05VS_VCCP

    1000P_0603_50V7K 4.7_1206_5%
    VOUT PHASE

    5
    6
    7
    8

    PR707
    4 11 +5VALW PQ703 1
    VDD CS AO4456_SO8

    330U_X_2VM_R6M
    5 VFB=0.75V 10 +

    1 2
    FB VDDP

    PC711
    PR709 6 9 DL_1.05VS_VCCP 4
    PGOOD LGATE 2
    PGND

    100_0603_5% PR708

    PC712
    GND

    1 2 0_0603_5%
    +5VALW

    1
    1

    1
    RT8209BGQW _W QFN14_3P5X3P5
    13.7K_0402_1%
    7

    3
    2
    1
    1

    @ PC715 PC714
    PR710

    PC713 47P_0402_50V8J 4.7U_0805_10V6K


    2

    4.7U_0603_6.3V6K 1 2
    2

    PR711
    4.02K_0402_1%
    1 2

    PR714
    1

    10_0402_5%
    [50] VCCPPW RGOOD PR713 2 1 VCCIO_SENSE [9]
    PR712 1 2 +3VS
    10K_0402_1%
    A A
    10K_0402_1%
    2

    PR715 @
    10K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title
    1

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR +1.05VS_VCCPP/+0.75VSP
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PIWG4
    Date: Tuesday, August 17, 2010 Sheet 51 of 57
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    D D

    2
    PR803
    PR801 PR802 205K_0402_1% PJ801
    @ 0_0402_5% @ 10K_0402_5% VGA_TON 1 2 VGA_IN 2 1 B+
    2 1
    2 1

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    [25,26] PX_MODE
    PD801 @ JUMP_43X118

    5
    PR804 1SS355_SOD323-2

    TPCA8030-H_SOP-ADV8-5

    1
    PC802

    PC803
    1 2 VGA_EN 1 2 +5VALW
    [15,18,25,26] PE_GPIO1

    PQ801
    120K_0402_1%

    2
    PC801 PR805
    PC804
    2 1 0.1U_0402_16V7K 0_0603_5% 4

    2
    [10,26,40,44,49,51] SUSP# BST_VGA 1 2BST_VGA-1
    1 2
    PR831
    @ 120K_0402_1% 0.1U_0603_25V7K
    PL801

    15

    14

    3
    2
    1
    1
    PU801 0.88UH +-20% PCMC104T-R88MN 20A
    1 2

    EN/DEM

    NC

    BOOT
    +VGA_COREP
    2 13 UG_VGA
    TON UGATE

    680P_0603_50V7K @ 4.7_1206_5%
    PR807 3 12 SW _VGA
    VOUT PHASE

    PR806
    100_0603_1%

    10U_0805_6.3V6M

    10U_0805_6.3V6M

    10U_0805_6.3V6M
    1

    330U_D2_2.5VY_R15M
    1 2 VGA_V5FILT 4 11 VGA_TRIP
    1 2 +5VALW

    TPCA8028-H 1N SOP
    +5VALW VDD CS

    1
    +

    PC806

    PC807

    PC808

    PC809
    PR808

    1VGA_SNB
    2
    VGA_FB 5 10 9.1K_0402_1%
    FB VDDP

    PQ802
    1 2 PR834

    2
    LG_VGA 2
    +3VS 2 1 6 PGOOD LGATE 9 4

    PGND
    PC805 @ 10K_0402_1%

    GND

    PC811
    4.7U_0603_6.3V6K

    1
    2 PR829 1
    [25] VGA_CORE_PG 0_0402_5% RT8209BGQW _W QFN14_3P5X3P5 PC810

    3
    2
    1

    2
    2
    C 4.7U_0805_6.3V6K C

    2
    PR830
    PC812 @ 10K_0402_1%
    @ 47P_0402_50V8J @
    1 2

    1
    1 2
    PR809
    2K_0402_1%
    1 2
    +3VALW PR810
    10K_0402_1%
    PR811
    30K_0402_1%
    1

    10K_0402_1%

    1 2
    PR812

    GVID1-2 PJ802
    6

    PR813 2 1
    10K_0402_1% +VGA_COREP 2 1 +VGA_CORE
    2

    VGA_PWRSEL0 VGA_PWRSEL1 Robson XT @ JUMP_43X118


    2 1GVID1-1 2 PQ803A
    1

    PQ803B 2N7002KDW -2N_SOT363-6


    3

    2N7002KDW -2N_SOT363-6 PR814 PR815 GPU_VID0 GPU_VID1 Core Voltage Level PJ803
    1

    @ 10K_0402_5% 8.66K_0402_1% 2 1
    PC813 2 1
    2

    [24] GPU_VID1
    2 1 5 0.022U_0402_16V7K 1 1 0.9V @ JUMP_43X118
    2

    PR816 +3VALW
    2
    1

    10K_0402_1% GVID0-2
    4

    PR817 1 0 0.95V PJ804


    1

    10K_0402_1%

    10K_0402_5% 2 1
    +VGA_PCIEP 2 1 +VGA_PCIE
    PR818

    B 0 0 1.12 V @ JUMP_43X118 B
    2

    +1.5V
    2

    2 1GVID0-1 2 PQ804A
    PR819 PC814 2N7002KDW -2N_SOT363-6 +5VALW
    3

    1
    PQ804B 10K_0402_1% 0.022U_0402_16V7K
    1

    2N7002KDW -2N_SOT363-6 PR820 PJ805

    1
    @ 10K_0402_5% JUMP_43X79
    2

    2 1 5 +5VALW
    [24] GPU_VID0 @

    2
    PR821 PC815
    2
    1

    10K_0402_1% PD802 1U_0402_6.3V6K


    4

    2
    PR822

    2
    10K_0402_5% @ RB751V-40_SOD323-2

    1
    1 2

    1
    PR823 PC816
    2

    @ 0_0402_5% 4.7U_0805_6.3V6K

    6
    PR824 PU802

    2
    47K_0402_5% 5

    VCNTL
    2

    PE_GPIO1 VIN
    1 2 7 POK
    [15,18,25,26] PE_GPIO1 4
    VOUT +VGA_PCIEP
    PR825 3
    VOUT

    1
    @ 0_0402_5%

    22U_0805_6.3V6M
    PC818
    SUSP# 1 2 8 2
    EN FB
    1

    [10,26,40,44,49,51] SUSP# PR826


    0.1U_0603_25V7K

    GND

    2
    1
    PC819

    9 1.15K_0402_1%
    PD803 PR827 VIN

    2
    1 2 @ 47K_0402_5% APL5912-KAC-TRL_SO8 VGA_PCIE 1.0V 1.1 V
    2

    1
    2

    @ RB751V-40_SOD323-2 PC817

    1
    0.01U_0402_25V7K
    A PR828 4.53K 3K A
    PR828
    4.53K_0402_1%

    2
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VGA_CORE/PCIE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 PIWG4Sheet 52 of 57

    5 4 3 2 1
    5 4 3 2 1

    Alert# PU resister need close CPU, PC902 470P_0402_50V7K CPU_B+ 1 2 B+

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    so the PU resister in HW schematic. 2 1 NTCG PL901
    B+ HCB4532KF-800T90_1812
    but DAT and CLK need close PWM-IC,

    TPCA8030-H_SOP-ADV8-5
    PR902 PQ901

    1
    so the PU resister in POWER schematic.

    PC903

    PC904
    3.83K_0402_1% PH901

    100U_25V_M
    2 1 2 1 1

    2
    1000P_0402_50V7K
    8.06K_0402_1%
    +

    PC905
    470KB_0402_5%_ERTJ0EV474J
    UGATEG 4

    1
    1 2

    1
    2

    PR903
    PR904 Choke PN:SH000005680

    PC901
    27.4K_0402_1%
    PL902

    3
    2
    1
    +VGFX_CORE 0.36UH_ETQP4LR36WFC_24A_20% +VGFX_CORE

    2
    PR905 PHASEG 4 1
    2 1 PC907 1

    5
    330P_0402_50V7K

    10K_0402_1%
    PC906 10_0402_1% BOOTG 2 PR906 1 2 PQ902 PQ903

    TPCA8028-H 1N SOP

    @TPCA8028-H 1N SOP
    D 1 3 2 D

    330U_X_2VM_R6M
    +5VS

    4.7_1206_5%
    1 2 2.2_0603_5% +
    1

    PC910
    PC911 PC912 0.22U_0603_10V7K
    VCC_AXG_SENSE [10]

    1 2PR907
    PR901 @ 39P_0402_50V7K PR909 680P_0402_50V7K 330P_0402_50V7K @ PR908
    2

    PC908

    PR910
    499K_0402_1% 2 1 2 1 2 1 PC909 1_0402_5%
    VSS_AXG_SENSE [10]

    680P_0603_50V7K
    @ 1U_0603_10V6K
    422_0402_1% 2 1 LGATEG 4 4

    2
    PC913 PH902
    2

    2
    PC915
    150P_0402_50V8J 1000P_0402_50V7K PR913 10K +-5% ERTJ0ER103J 0402

    PC914
    2 1 2 1 2 1 2 1 PR915 1 PR914 21 2

    1
    @ 0_0603_5%

    @ 0.22U_0603_10V7K
    PR911 PR912 10_0402_1% 2 1 7.5K_0402_1%

    3
    2
    1

    3
    2
    1

    2
    PR916
    475K_0402_1% 2.55K_0402_1% @ 2.2_0603_5%

    BOOT3
    PC917 1 PR917 2 .1U_0402_16V7K

    ISNG
    GFXVR_IMON

    ISPG
    1

    2
    18.2K_0402_1%

    PR919 11K_0402_1% PC919


    +1.05VS_VCCPP
    0.047U_0603_16V7K
    @ 16.5K_0402_1% @ 1 2 1 2

    2
    1

    @.1U_0402_16V7K
    PR918

    PC916

    PC918 .1U_0402_16V7K

    1
    UGATEG

    PHASEG
    PU902 100_0402_1%

    LGATEG
    BOOTG

    470P_0402_50V7K
    PC920

    PC921 @ PR922

    NTCG
    5 1
    2

    1
    2 VCC BOOT
    2 PR920 1

    1
    130_0402_1%

    54.9_0402_1%
    1 2 1 2

    @ 43_0402_1%

    PC922
    @ TPCA8030-H_SOP-ADV8-5
    6 8 UGATE3 CPU_B+
    [10] VSS_AXG_SENSE FCCM UGATE

    2 PR924 1
    590_0402_1%
    @4.7U_0805_25V6-K

    @4.7U_0805_25V6-K
    PR967

    PR921
    @ 0.01U_0402_16V7K

    ISPG
    1

    1
    2 7 PHASE3 PQ904
    For shortage changed +3VS PWM PHASE
    Parallel and tune length

    1
    +5VS

    PC923

    PC924
    LGATE3

    49

    48

    47

    46

    45

    44

    43

    42

    41

    40

    39

    38

    37
    3 4
    2

    2
    GND LGATE

    @
    1.91K_0402_1%
    PR923 9 2 PR925 1ISNG

    GND

    COMPG

    FBG

    VSENG

    RTNG

    ISPG

    ISNG

    NTCG

    PROG2

    BOOTG

    UGG

    PHG

    LGG

    2
    [9] VR_SVID_DAT PGND

    1
    @ 0_0402_5% 4 @ 0_0402_5%
    1 36 BOOT2 @ISL6208ACRZ-T_QFN8_3X3
    @ ISL6208ACRZ-T_QFN8_3X3
    [9] VR_SVID_ALRT# VWG BOOT2

    2
    PR926
    2 35 UGATE2
    [9] VR_SVID_CLK 2 IMONG UG2 PL903

    3
    2
    1
    PR927 3 34 PHASE2 PR928 @ 0.36UH_ETQP4LR36WFC_24A_20%
    PGOODG PH2
    +3VS 1 2 1 2 +5VS 4 1 +CPU_CORE
    SVID_SDA 4 33
    SDA VSSP2

    5
    GFX_CORE_PWRGD

    @ 4.7_1206_5%
    1.91K_0402_1% 0_0402_5% PQ905 PQ906 ISEN32 PR929 1 3 2 2 PR930 1ISEN1

    1 2 PR932 1
    SVID_ALERT# LGATE2 @ 10K_0402_1% @ 10K_0402_1%

    @TPCA8028-H 1N SOP

    @TPCA8028-H 1N SOP
    5 32
    C ALERT# LG2 PR931 C

    SVID_SCLK 6 31 1 2
    [9] VSSSENSE VGATE [16] SCLK VDDP

    680P_0603_50V7K
    [40] VR_ON 1 PR933 2 7 VR_ON PWM3 30 PWM3 0_0402_5% 4 4 PR935
    VSUM+ 2 PR934 1 2 1ISEN2
    0.033U_0603_16V7K

    PC925
    0_0402_5% 8 29 LGATE1 @ 3.65K_0402_1% @ 10K_0402_1%
    0] IMVP_IMON PGOOD LG1
    19.1K_0402_1%

    PC926

    ISL95831CRZ-T_TQFN48_6X6
    1

    2.2U_0603_10V6K
    PC927
    9 28

    3
    2
    1

    3
    2
    1

    2
    IMON VSSP1
    1

    PR937

    1
    PR936

    10 27 PHASE1 VSUM- 2 1
    VR_HOT# PH1 @ 1_0402_5%
    2

    11 26 UGATE1 @
    2

    2
    NTC
    ISEN3/ FB2

    For shortage changed UG1


    12 25 BOOT1

    PROG1
    ISUMN

    ISUMP
    VW BOOT1
    COMP

    ISEN2

    ISEN1

    VSEN

    VDD
    RTN
    [40,46] VR_HOT#

    VIN
    PC929 CPU_B+
    FB
    1

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    PR938 2 470P_0402_50V7K
    1

    5
    TPCA8030-H_SOP-ADV8-5
    1 2 PU901 PQ907
    13

    14

    15

    16

    17

    18

    19

    20

    21

    22

    23

    24
    499_0402_1% PR939 PH903
    2

    1
    PC930

    PC931
    +1.05VS_VCCPP @ 1 2 1 2
    3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J

    2
    UGATE2 4
    PC928 2 1

    1
    47P_0402_50V8J PR940 27.4K_0402_1%
    PR941
    PR942
    1000P_0402_50V7K
    8.06K_0402_1%

    change from 43P to 47P 1 2 7.87K_0402_1% PL904


    CPU_B+

    3
    2
    1
    1

    (Ipeak=56A) 0.36UH_ETQP4LR36WFC_24A_20%
    for shortage problem

    4.7_1206_5%
    PR943

    PC932

    PHASE2 4 1 +CPU_CORE

    2
    2010-03-15 PC933 0_0603_5%
    2

    @ 22P_0402_50V8J PR945 2.2_0603_5% 3 2

    1
    0.22U_0603_25V7K

    PR944 PQ908 PQ909

    @TPCA8028-H 1N SOP

    TPCA8028-H 1N SOP
    2 1 +5VS
    2

    PC935

    PR946
    2 1 BOOT2 2 1 2 1
    1U_0603_10V6K

    1_0603_5%
    ISEN2

    ISEN1

    PC934 @ 10K_0402_1% 10K_0402_1%


    ISEN3

    B B

    680P_0603_50V7K
    PC936

    0.22U_0402_6.3V6K PC937 0.22U_0603_10V7K PR947 PR948

    1 2
    2 1 LGATE2 4 4 ISEN2 2 1 2 1ISEN1
    2

    PC939
    PC938
    33P_0402_50V8J PC941
    PR950
    PR949 PC940 VSUM- 2 1 VSUM+ 3.65K_0402_1% 1_0402_5%

    2
    1 2 2 1 2 1 2 1 0.22U_0402_6.3V6K PR951 PR952

    3
    2
    1

    3
    2
    1
    1
    2.61K_0402_1%
    499_0402_1% PC942 VSUM+ 2 1 2 1 VSUM-
    @ 0.068U_0402_16V7K

    PR953

    470P_0402_50V7K 2 1
    499K_0402_1%
    0.33U_0603_10V7K

    PC943 PR954 PR955 0.22U_0402_6.3V6K @


    @ 2 1 2 1 2 1
    2.15K_0402_1%
    1 2
    1

    1
    11K_0402_1%

    150P_0402_50V8J 316K_0402_1% PR955 CPU_B+

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    PC944

    PC945

    PR957

    TPCA8030-H_SOP-ADV8-5
    PR956 QC:3.83K PR958

    5
    +CPU_CORE 2 1 QC:1.24K PH904 PQ910
    DC:2.15K
    2

    10_0402_1% 10K +-5% ERTJ0ER103J 0402


    DC:698

    1
    330P_0402_50V7K

    PC948

    PC949
    PC947
    2
    1

    2 1 PR958
    2
    PC946

    330P_0402_50V7K 2 1 VSUM-

    2
    [9] VCCSENSE 698_0402_1% UGATE1 4
    2

    .1U_0402_16V7K

    2 1 PC951 PR959
    [9] VSSSENSE
    PC952

    PC950 2 1 2 1
    PR960 1000P_0402_50V7K @ 100_0402_1%
    2

    2 1 @ 330P_0402_50V7K PL905

    3
    2
    1
    10_0402_1% 0.36UH_ETQP4LR36WFC_24A_20%
    PHASE1 4 1 +CPU_CORE

    4.7_1206_5%
    5

    5
    PR961 PQ911 PQ912 10K_0402_1% 3 2 10K_0402_1%

    1
    PR962
    2.2_0603_5% PC953 PR963 PR964

    TPCA8028-H 1N SOP

    @TPCA8028-H 1N SOP
    BOOT1 2 1 2 1 ISEN1 2 1 2 1 ISEN2
    *Iccmax in Turbo Mode for SV (35W) is 53A
    0.22U_0603_10V7K

    680P_0603_50V7K
    LGATE1 4 4 @ 3.65K_0402_1% 1_0402_5%

    1 2
    +CPU_CORE +VGFX_COREP PR965 PR966

    PC954
    VSUM+ 2 1 2 1 VSUM-
    A A
    Icc-max=53A Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A
    3
    2
    1

    3
    2
    1

    2
    Rdson=3.6~4.5m ohm Rdson=3.6~4.5m ohm
    DCR=1.1m ohm DCR=1.1m ohm
    HW output cap: HW output cap: @
    (1)10U_0805_4V *10 (1)22U_0805_6.3V *12
    (2)22U_0805_6.3V *15 (2)470U_D2_2V *2(ESR=4.5m ohm)
    (3)470U_D2_2V *4(ESR=4.5m ohm) Security Classification
    2010/01/25
    Compal Secret Data
    2010/12/31 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date PWR +CPU_CORE/+VGFX_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    *OCP setting value=71.5A *OCP setting value=37A Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIWG4 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 53 of 57
    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List) Page 1 of 1


    for PWR
    Item Reason for change PG# Modify List Date Phase

    1
    D D

    7
    C C

    10

    11
    B B

    12

    13

    14

    15

    16

    17
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/01/06 Deciphered Date 2009/01/06 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR (PWR)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PIWG4
    Date: Tuesday, August 17, 2010 Sheet 54 of 57
    5 4 3 2 1
    5 4 3 2 1

    D D

    PCH_PWR_EN# 2
    U14,+3VALW_PCH

    V
    AC A1
    MODE VIN QH4,+5VALW_PCH

    V V
    A2 A3 B5

    VV
    PU2 A5 2

    V
    PU3

    V
    B+ +3VALW_PCH
    +3VALW B7 2 3
    BATT V +5VALW_PCH
    BATT
    MODE
    B1
    B2
    B+ B4 V
    V

    V
    EC 4 SYS_PWROK
    13
    PQ2 PCH_RSMRST# PM_DRAM_PWRGD

    V
    V V PCH
    B3 A5 B7 5 14
    PBTN_OUT# H_CPUPWRGD
    CPU

    V V
    V
    51ON# EC_ON
    PM_SLP_S3#
    PM_SLP_S4# PLT_RST# 15
    C C
    PM_SLP_S5#
    A4 B6 PM_SLP_A# 6
    PM_SLP_SUS#

    V
    V
    ON/OFF V
    SYSON 7 SYSON# +1.5V

    V
    PU5
    DGPU_PWR_EN 8a (DIS) VGA_ON
    +3VSDGPU

    V
    8
    Q6 11
    SUSP#,SUSP U49

    V
    VGATE
    +5VS

    V
    +1.5VSDGPU
    U40

    V
    U20

    V
    +3VS +1.8VSDGPU VGA
    U37
    B B

    V
    U13

    V
    +1.5VS +1.0VSDGPU
    PU28

    V
    PU8

    V
    +0.75V +VGA_CORE
    VCCPPWRGOOD
    PU998
    V

    V
    PU9 PU7
    +1.05VS_VCCP +VCCSA 8b (DIS)
    VGA_PWROK

    U47
    CK505
    VR_ON 9 PU1000
    V
    10
    V

    +CPU_CORE

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power sequence
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6758P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 17, 2010 Sheet 55 of 57
    5 4 3 2 1
    5 4 3 2 1

    JKB1 ZZZ
    KSI1 1
    KSI7 1
    2 2
    KSI[0..7]
    INT_KBD
    KSI[0..7]
    [40] Conn. KSI6
    KSO9
    3
    4
    3
    4
    KSO[0..17] KSO16 C693 1 2 @ 100P_0402_50V8J KSI4 5
    KSO[0..17] [40] 5
    KSI5 6 PCB
    KSO17 C692 1 6
    2 @ 100P_0402_50V8J KSO0 7 7
    KSI2 8
    KSO2 C668 1 8
    2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSI3 9 9
    KSO5 10
    KSO15 C670 1 10
    2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSO1 11 11
    D KSI0 12 D
    KSO6 C672 1 12
    2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSO2 13 13
    KSO4 14
    KSO8 C674 1 14
    2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO7 15 15
    KSO8 16
    KSO13 C676 1 16
    2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J KSO6 17 17
    KSO3 18
    KSO12 C678 1 18
    2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSO12 19 19
    KSO13 20
    KSO11 C680 1 20
    2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO14 21 21
    KSO11 22
    KSO10 C682 1 22
    2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J KSO10 23 23
    KSO15 24
    KSO3 C684 1 24
    2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J [40] KSO16
    KSO16 25 25
    KSO17 26
    [40] KSO17 26
    KSO4 C686 1 2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J 27 27
    28 28
    KSI0 C688 1 2 @ 100P_0402_50V8J KSO9 C689 1 2 @ 100P_0402_50V8J 29 31
    29 GND
    30 30 GND 32
    KSO0 C690 1 2 @ 100P_0402_50V8J KSI1 C691 1 2 @ 100P_0402_50V8J
    ACES_88514-3001

    CONN PIN define need double check Reserve for ESD. ME@

    +5VS
    JP13
    +5VALW 1 1
    C 2 C
    +3VALW 2
    3
    To TP/B Conn. C696
    [40] LID_SW #
    +5VS
    4
    3
    4
    [14] KILL_SW # 5 5
    0.1U_0402_16V4Z [40,43] PW R_LED# 6
    JTP1 D19 6
    @ White [40] CHARGE_LED1# 7
    RF_LED#_R 7
    1 1 [34] W LAN_LED# 1 2 [40] CHARGE_LED0# 8 8
    TP_CLK 2 RF_LED#_R 9
    [40] TP_CLK 2 9
    TP_DATA 3 RB751V_SOD323 [14] HDD_LED# 10
    [40] TP_DATA 3 10
    1 1 SW /L 4 SW /L 11
    4 D20 11
    @ @ SW /R 5 @ SW /R 12
    C697 C698 5 12
    6 6 [42] BT_LED# 1 2 13 13 G1 15
    100P_0402_50V8J 100P_0402_50V8J 14 16
    2 2 RB751V_SOD323 +3VALW 14 G2
    7 GND
    8 ACES_85202-1405L
    GND ME@
    [40] RF_LED# 1 2
    ACES_88058-060N R679 0_0402_5% R615
    LID_SW #
    1 2 R01
    ME@ 100K_0402_5%
    TP_CLK
    7/22 modify
    TP_DATA For 17" M/B to LED/B
    3

    D15
    PSOT24C_SOT23-3
    @
    B button move to LED B/D B
    1

    VRAM
    screw hole Fan screw hole
    CONN PIN define need double check
    H19 H18 H20
    HOLEA HOLEA HOLEA

    SATA ODD FFC Conn.

    1
    JP2

    [14] SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_P2_CONN 1


    SATA_ITX_DRX_N2_CONN 1
    [14] SATA_ITX_DRX_N2_CONN 2 2
    SATA_DTX_C_IRX_N2 C605 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2
    3
    4
    3 H_2P8 H_5P5N H_3P2
    [14] SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C606 1 4
    [14] SATA_DTX_C_IRX_P2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 5 5
    ODD_DETECT# R710 1 2 0_0402_5% 6 6
    +5V_ODD 7 7
    8 8
    ODD_DA# 1 2 9
    [18,40] ODD_DA# R554 0_0402_5% 9
    10 10
    R555
    +3VS 1 2 11 GND
    10K_0402_5% 12 GND

    A A
    ACES_87056-01001-001

    ME@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KB /SW /LPC Debug Conn.
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 56 of 57
    5 4 3 2 1
    5 4 3 2 1

    PHASE PAGE Modification list PURPOSE


    0.2 P31 Change CRT Symbol For CRT footprint issue
    0.2 P31 Del C510 For Non-used part
    0.2 P39 change C610 pin 1 net name change C610 pin 1 net name to correct
    0.2 P35 U25 change to U26 For co-lay 10/100 and GIGA
    0.2 P32 Add R735,R736 For DIS only SMBus pull high
    0.2 P33 Add R738,R739 For DIS only SMBus pull high
    D D
    0.2 P33 Change Q63 BOM structure to HDMI@ For DIS HDMI function
    0.2 P40 Add R740, C93 For EC request
    0.2 P18 Change R215 pin1 net name Change R215 pin1 net name to correct
    0.2 P18 Add R741 Add R741 for Reserved PE_GPIO0
    0.2 P16 Add R742, R743 For PCH power sequence
    0.2 P38 Del U28, R542~R551 , J12 Del USB charger circuit
    0.2 P40 Add EC pin 97,98,103 Add EC pin 97 for SYS_PWROK_EC , pin 98 for CE_EN , pin 103 for BATT_SEL_EC
    0.2 P24 Change R662 pin 2 net name Change R662 pin 2 net name to correct
    0.2 P28 Del C421,C422,C431,C432,C433, L27, Add R745, U8 pin N11,N12 change to NC For AMD new document suggestion
    0.2 P26 Add R744 Add R744 for control PE_GPIO1 from SUSP#
    0.2 P39 Change J10 footprint and Add J13 Change J10 footprint by DFx request and Add J13 by vendor suggestion
    0.2 P39 Change PC_Beep circuit Change PC_Beep circuit
    0.2 P6 Add R161, R182, R192 BOM structure hange to @ Follow ORB circuit
    0.2 P58/59 Add R615 in 15" and 17" page Pull high LID_SW# at M/B side
    C 0.2 P31 Add Q83 pin 1 power net name +CMOS_PW For power trace net C

    0.2 P56/57/58 Change JP21 to JKB1 Change connector to standard name


    0.2 P56/57/58 Change JP4 to JTP1 Change connector to standard name
    0.2 P43/60 Change JP6 to JPWRB1 Change connector to standard name
    0.2 P34 Change JP1 to JWLN1 Change connector to standard name
    0.2 P42 Change JP5 to JBT1 Change connector to standard name
    0.2 P43/60 Change JP7 to JCR1 Change connector to standard name
    0.2 P19 Add R542 For ESATA detect function
    0.2 P42 Add R886, R887 , C735 For ESATA detect function
    0.2 P31 Add R543 For reserve EC control directly
    0.2 P39 Change J10 footprint, Del C635, C636 Change J10 for DFx and Del component for layout
    0.2 P42 Add R877 For reserve EC control directly
    0.2 P42 SW3 BOM structure change to @ For ME ASSY concern
    0.2 P24 R324 BOM structure change, del @ For AMD update
    B
    0.2 P25 Change Q69,Q70,Q71,Q72 to BSS138, change Q66,Q67 pin 1 net name, D28 change to @ For Change BACO part follow AMD reference DATA ,D28 change to @ for leakage B

    0.2 P42 Change ESATA from port 5 to port 4 For intel risk
    0.2 P15 Add R544,R545 For Pull high SMBus
    0.2 P12/13 Del R74~R80,R82 R88~R94,R96 For DDR3 DM Bus to GND
    0.2 P16 Add R182,R546 Add 186 for reserve sequence, Add R546 for follow CRB & ORB
    0.2 P20 Del Add J12, R257 change to @ For voltage drop

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KB /SW /LPC Debug Conn.
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-6758P
    Date: Tuesday, August 17, 2010 Sheet 57 of 57
    5 4 3 2 1

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