Laptop Lenovo Foxcon-S09

S09 Block Diagram
SYSTEM DC/DC
MAX1999 36
INPUTS OUTPUTS
5V_S5
www.hocnghetructuyen.vn 3V_S5
Thermal DCBATOUT
Mobile CPU
5V_AUX
G768D 18 3D3V_AUX
CLK GEN Dothan T8 SYSTEM DC/DC

OZ824 37
ICS954226 03 04.05 MAX651018
INPUTS OUTPUTS
1D05V_S0
HOST BUS 400/533MHz DCBATOUT
1D5V_S0
RGB CRT
12 SC486 38
1D8V_S3
DCBATOUT
DDR2 Alviso GM LVDS LCD
XGA
0D9V_S0
400/533 13 MAXIM CHARGER

11 GML OZ8604
35
S-Video TV-OUT
06,07,08,09,10 12 INPUTS OUTPUTS
DMI I/F 100MHz BT+

19V 3.0A
DCBATOUT
PWR SW 5V_AUX
LPC BUS PCI BUS Cardbus CP2211 23
5V 100mA
LCD/BTN Audio DJ28
ENE CB851 CARDBUS
ONE SLOT CPU DC/DC
Ext /CB1410 22
23 SC450
AC'97 AC-Link 39
MIC In 27
CODEC 1394 INPUTS OUTPUTS
23
LineOut27 RTLALC655 Mini-PCI VCC_CORE
26
MODEM
1.0
ICH6-M 802.11 B/G 29
DCBATOUT
0.844~1.3V
27A
20
Intel LAN PCB LAYER

OP AMP LCI TXFM25 RJ45
82562GT 25 L1: Signal 1
Speaker27 TPA6017A2
27
24
L2: VCC
USB LPC BUS L3: Signal 2

USB XD BIOS
3 PORT L4: Signal 3
14.15.16.17
21 8/4Mb L5: GND
30
PATA KBC L6: Signal 4
ENE MXA
6999MP
391030 32
HDD ODD
SMBus EEPROM
(master) (slave) AT24C01A TECHNOLOGY COPR.
19 19
32
Touch INT_KB Title
Block Diagram
Pad 31 31 Document Number
S09 MAINBOARD
Rev
A
Date: Sunday, March 13, 2005 Sheet 1 of 45
A B C D E
Alviso Strapping Signals ICS954226 Spread Spectrum ICH6-M Integrated Pull-up
and Configuration page 7 Select page 3
and Pull-down Resistors
ICH6-M EDS 15851 1.5V1
Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0]
CFG[2:0] FSB Frequency Select 000 = Reserved Pin17/18
001 = FSB533 Byte 6b7 Byte 6b6 byte 6b5 Byte 6b4 Spread Mode Spread Amount% Mhz GNT[4]#/GPO[48], GNT[5]#/GPO[17],
101 = FSB400
011-111 = Reversed 1 0 0 0 Down 0.8 100 GNT[6]#/GPO[16], GPIO[25] ICH6 internal 20K pull-ups
4 CFG[3:4] Reversed 1 0 0 1 Down 1.25 100 LAD[3:0]#/FB[3:0]#, LAN_RXD[2:0],
4
CFG5 DMI x2 Select 0 = DMI x2 1 0 1 0 Down 1.75 100 LDRQ[0], LDRQ[1]/GPI[41],PME#,
1 = DMI x4 (Default)
0 = DDR II (Default) 1 0 1 1 Down 2.5 100 PWRBTN#, TP[3]
CFG6 DDR I / DDR II 1 = DDR I
1 1 0 0 Center +-0.3 100 (Default)
CFG7 CPU Strap 0= Reserved
1=Dothan (Default) 1 1 0 1 Center +-0.5 100
ACZ_BITCLK, ACZ_RST#, ACZ_SDIN[2:0], ICH6 internal 20K pull-downs
CFG8 Reversed 1 1 1 0 Center +-0.8 100
ACZ_SDOUT, ACZ_SYNC, DPRSTP#
1 1 1 1 Center +-1.25 100
CFG9 PCI Express Graphics 0=Reverse Lanes DPRSLPVR, EE_CS, SPKR,
Lane reverse option
1=Normal Operation
for layout convenience (Default) PCI Routing USB[7:0][P,N] SATALED# ICH6 internal 15K pull-downs
CFG10 Reversed
IDSEL IRQ REQ/GNT DD[7], DDREQ ICH6 internal 11.5K pull-downs
CFG11 Reversed
CB851 25 E 0 LAN_CLK ICH6 internal 100K pull-downs

00 = Reserved
CFG[13:12] XOR/ALL Z test 01 = XOR mode enabled
straps 10 = All Z mode enabled MiniPCI 21 C 1
11 = Normal Operation
(Default)
ICH6-M Strapping Options
3 CFG[14:15] Reversed
1394 19 E 3 REF FUNCTION DEFAULT OPTIONAL OVERRIDE 3
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled R275 No Reboot Dummy Reserved
(Default)
A16 Swap
CFG17 Reversed R279 Override Dummy Reserved
CFG18 GMCH core VCC 0 = 1.05V (For GML)
ICH6-M IDE Integrated Series
Select R282 Boot BIOS Dummy Reserved
CFG19 CPU VTT Select
1 = 1.5V (For GM)
Termination Resistors
0 = 1.05V (Default)
1 = 1.2V
CFG20 Reversed DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
SDVO SDVO Present 0 = No SDVO device present DDACK#, IORDY, DA[2:0], DCS1#,
CRTL_DATA (Default)
1= SDVO device present DCS3#, IDEIRQ
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal. I2C/SMB Addresses
www.hocnghetructuyen.vn
KBC Hardware Strap page 30 Device Address Bus
Clock Generator 1101 001x SMB_ICH_S0
2 PinNumber PinName Function 2
SO-DIMM0 1010 000x SMB_ICH_S0
125 A1 High:Enable the internal pull-up resistors on XIOCS [F:0] pins
Low:Disable the internal pull-up resistors on XIOCS [F:0] SO-DIMM1 1010 010x SMB_ICH_S0
Thermal Sensor 0111 101x SMB_KBC_S0
128 A4 High: Diasble DMPP(Recommended)
Low : Enable DMPP Battery 0001 000x SMB_KBC_S5
131 A5 High:Enable EMWB(Recommended for application using shared BIOS Antitheft 1010 000x SMB_KBC_S5
Low:Disable EMWB Light Sensor 0111 001x SMB_KBC_S0
11 GPIO05 High:Test Mode
Low:32KHz clock in normal running(Recommend)
12 GPIO06 High:Test Mode(KSOUT0~15 become DPLL internal data outputs,

KSO16 becomes internal power-on reset output
1 Low:Normal operation(Recommended) www.hocnghetructuyen.vn 1
105 GPIO20 High:Normal operation(Recommended)

TECHNOLOGY COPR.
Low:Enable ISP mode during which the RD#,WR#,MEMSEL#,A[20:0]
Title
andD[7:0}will be controlled by ISP COntriller
Table of content
Document Number Rev
S09 MAINBOARD A
Date: Tuesday, March 15, 2005 Sheet 2 of 45
5 4 3 2 1
3D3V_S0
3D3V_S0 FB1 FB L0603 180 Ohm
R1 R0603 3D3V_APWR_S0
0 +/-5% BC1 BC2 1 2 3D3V_CLKGEN_S0
4.7uF 0.1uF BC3 BC4 BC5 BC6 BC7 BC8 BC9 BC10
10V, Y5V, +80%/-20% * * 16V, Y5V, +80%/-20%
* 10uF
* 0.1uF 0.1uF
* * 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
C0805 C0402
C0805 C0402 C0402 C0402 C0402 C0402 C0402 C0402
10V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%
D
www.hocnghetructuyen.vn D
3D3V_S0
R2 R0603 3D3V_48MPWR_S0
0 +/-5% BC11 BC12
4.7uF 0.1uF
* *16V, Y5V, +80%/-20%
U1
C0805 C0402
10V, Y5V, +80%/-20%
3D3V_APWR_S0 37 54
VDDA CPU_STP# PM_STPCPUJ 15,39
3D3V_CLKGEN_S0 1 44 RN1 1 4 4P2R0402V CLK_CPU_BCLK 4
VDDPCI CPUT0 33
7 VDDPCI CPUC0 43 2 3 +/-5% CLK_CPU_BCLKJ 4
3D3V_S0 21 41 RN2 1 4 4P2R0402V CLK_MCH_BCLK 6
VDDPCIEX CPUT1 33
28 VDDPCIEX CPUC1 40 2 3 +/-5% CLK_MCH_BCLKJ 6
34 VDDPCIEX
36 CLK_XDP_CPU 1 TP1
R626 CPUT2_ITP/PCIEXT6 CLK_XDP_CPUJ 1 TP2
42 VDDCPU CPUC2_ITP/PCIEXC6 35
10K 48
+/-5% VDDREF RN3
ITP_EN 0=PCIEX_6 1=CPU_2_ITP LCDCLK_SS/PCIEX0T 17 2 3 4P2R0402V DREFSSCLK 7
R0402 3D3V_48MPWR_S0 11 18 33 1 4 +/-5%
SS_SEL 0=LCDCLK 1=PCIEX/free running VDD_48 LCDCLK_SS/PCIEX0C DREFSSCLKJ 7
Dummy
3.3V PCI clock output PCIEXT1 19
R6 33 R0402 +/-5% 56 20
C
29
22
PCLK_MINI
PCLK_PCM R7 33 R0402 +/-5% 3
PCICLK2/REQ_SEL
PCICLK3
** PCIEXC1
C
3D3V_S0 30 PCLK_KBC R8 33 R0402 +/-5% 4 22 RN4 2 3 4P2R0402V CLK_MCH_3GPLL 7
PCICLK4 PCIEXT2 33
28 CLK33_AUDIODJ R9 33 R0402 +/-5% 5 PCICLK5 PCIEXC2 23 1 4 +/-5% CLK_MCH_3GPLLJ 7
H/L: 100/96MHz
SS_SEL 9 24
SELPCIEX_LCDCLK#/PCICLK_F1 PCIEXT3
55 25
R12 R13
15 PM_STPPCIJ
15 CLK_ICHPCI R11 33 R0402 +/-5% ITP_EN 8
PCI/SRC_STP#
ITP_EN/PCICLK_F0
** PCIEXC3
10K 10K H/L : CPU_ITP/SRC7 26
+/-5% +/-5% SATACLKT
SATACLKC 27
R0402 R0402 39 VTT_PWRGDJ VTT_PWRGDJ 10
Dummy VTT_PWRGD#/PD RN6
PCIEXC4 30 2 3 4P2R0402V CLK_PCIE_ICHJ 15
R14 22R0402 +/-5% FS_A 12 31 33 1 4 +/-5%
15 CLK48_ICH USB_48/FS_A PCIEXT4 CLK_PCIE_ICH 15
ITP_EN
SS_SEL RN7 1 4 4P2R0402V 14 32
7 DREFCLK
33 2 3 +/-5% 15
DOT96T * PEREQ2#/PCIEXC5
33
R15 R16
7 DREFCLKJ DOT96C * PEREQ1#/PCIEXT5
10K 10K 11,17 SMBC_ICH 46
+/-5% +/-5% SCLK
11,17 B_SMBD_ICH 47 SDATA GND 13
R0402 R0402
*
Dummy BC13 50V, NPO, +/-5% X2_ICS 49 51

1D05V_S0 C0603 X1_ICS XOUT GND
50 XIN GND 45
2
33pF GND 29
R18 X1 BSEL0 53
1K BSEL1 REF1/FS_C/TEST_SEL
X-14D318MHz 16 FS_B/TEST_MODE GND 2
+/-5% 6
1
GND
*
R0402 BC14 R19 R0402 39

Dummy C0603 50V, NPO, +/-5% 475 +/-1% 52 IREF
REF0 GNDA 38
B 4 CPU_SEL0 R21 0 +/-5% R627 2.2K BSEL0 B
R0402 R0402 +/-5% 33pF R22 47R0402 +/-5%
15 CLK_ICH14
R24 FS_C ICS954226
7 MCH_BSEL0 R23 1K+/-5% 2.2K
R0402 +/-5%
R0402 *internal Pull-Up resistors
Dummy EMI capacitor
**internal Pull-Down resistor
1D05V_S0 BSEL0 R518 22R0402 +/-5% AC_CLK 26
CLK_ICH14 C1 10pF C0402 50V, NPO, +/-5% Dummy
********
R26
1K
To external AC'97 CLK PCLK_PCM C2 10pF C0402 50V, NPO, +/-5% Dummy
+/-5%
R0402 PCLK_MINI C3 10pF C0402 50V, NPO, +/-5% Dummy
Dummy
4 CPU_SEL1 R27 0 +/-5% BSEL1 CLK_PCIE_ICH R28 49.9 R0402 +/-1% CLK_CPU_BCLK R29 49.9 R0402 +/-1% PCLK_KBC C4 10pF C0402 50V, NPO, +/-5% Dummy
R0402 FS_B
R33 CLK_PCIE_ICHJ R30 49.9 R0402 +/-1% CLK_CPU_BCLKJ R31 49.9 R0402 +/-1% CLK_ICHPCI C5 10pF C0402 50V, NPO, +/-5% Dummy
7 MCH_BSEL1 R32 1K+/-5% 2.2K
R0402 +/-5% DREFSSCLKJ R34 49.9 R0402 +/-1% CLK_MCH_BCLK R35 49.9 R0402 +/-1% CLK48_ICH C6 10pF C0402 50V, NPO, +/-5% Dummy
R0402
Dummy DREFSSCLK R36 49.9 R0402 +/-1% CLK_MCH_BCLKJ R37 49.9 R0402 +/-1% CLK33_AUDIODJ C7 10pF C0402 50V, NPO, +/-5% Dummy
DREFCLK R38 49.9 R0402 +/-1% CLK_MCH_3GPLL R39 49.9 R0402 +/-1% AC_CLK C8 10pF C0402 50V, NPO, +/-5% Dummy
3D3V_S0
DREFCLKJ R40 49.9 R0402 +/-1% CLK_MCH_3GPLLJ R41 49.9 R0402 +/-1%
A R42 A
10K FS_C FS_B FS_A CPU
+/-5%
R0402 0 0 0 266M
FS_A 0 0 1 133M
0 1 0 200M TECHNOLOGY COPR.
R45 0 1 1 166M
10K 1 0 0 333M Title
+/-5% 1 0 1 100M
R0402
Dummy
1 1 0 400M Clock Generator
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
U2A TP3
1
1D05V_S0
6 B_H_AJ[31..3] B_H_AJ3 P4
A3# ADS# N2 B_H_ADSJ 6
B_H_AJ4 U4 L1
A4# BNR# B_H_BNRJ 6
ADDR GROUP 0
B_H_AJ5 V3 J3
A5# BPRI# H_BPRIJ 6
B_H_AJ6 R3 R46
B_H_AJ7 V2 A6# 56
A7# DEFER# L4 H_DEFERJ 6
B_H_AJ8 W1 H2 B_H_DRDYJ 6 +/-5%
B_H_AJ9 T4 A8# DRDY# R0402
A9# DBSY# M2 B_H_DBSYJ 6
B_H_AJ10 W2
B_H_AJ11 Y4 A10# Place testpoint on
A11# BR0# N4 B_H_BREQJ0 6
B_H_AJ12 Y1 H_IERR# with a GND
CONTROL
D A12# D
B_H_AJ13 U1 A4 H_IERRJ 0.1" away
B_H_AJ14 AA3 A13# IERR#
A14# INIT# B5 H_INITJ 14
B_H_AJ15 Y3
B_H_AJ16 AA2 A15#
A16# LOCK# J2 B_H_LOCKJ 6
6 B_H_ADSTBJ0 U3 ADSTB#0 H_CPURSTJ 6
6 B_H_REQJ[4..0] RESET# B11 H_RSJ[2..0] 6
B_H_REQJ0 R2 H1 H_RSJ0 B_H_DJ[63..0] 6
B_H_REQJ1 REQ0# RS0# H_RSJ1
P3 REQ1# RS1# K1
B_H_REQJ2 T2 L2 H_RSJ2
B_H_REQJ3 REQ2# RS2#
P1 REQ3# TRDY# M3 H_TRDYJ 6 U2B
B_H_REQJ4 T1 REQ4#
K3
XTP/ITP SIGNALS
HIT# B_H_HITJ 6
B_H_AJ17 AF4 K4 B_H_DJ0 A19 Y26 B_H_DJ32
A17# HITM# B_H_HITMJ 6 D0# D32#
B_H_AJ18AC4 Put these Caps near B_H_DJ1 A25 AA24 B_H_DJ33
B_H_AJ19AC7 A18# B_H_DJ2 D1# D33# B_H_DJ34
C8 A22 T25
ADDR GROUP 1
B_H_AJ20AC3 A19# BPM#0 the thermal diode. B_H_DJ3 D2# D34# B_H_DJ35
B8 B21 U23
DATA GRP 0
DATA GRP 2
B_H_AJ21AD3 A20# BPM#1 B_H_DJ4 D3# D35# B_H_DJ36
A21# BPM#2 A9 A24 D4# D36# V23
B_H_AJ22 AE4 C9 THERMDP1 B_H_DJ5 B26 R24 B_H_DJ37
B_H_AJ23AD2 A22# BPM#3 B_H_DJ6 D5# D37# B_H_DJ38
A23# PRDY# A10 A21 D6# D38# R26
B_H_AJ24 AB4 B10 BC15 B_H_DJ7 B20 R23 B_H_DJ39
B_H_AJ25AC6 A24# PREQ# XDP_TCK 470pF B_H_DJ8 D7# D39# B_H_DJ40
B_H_AJ26AD5 A25#
A26#
TCK
TDI
A13
C12 XDP_TDI * 50V, X7R, +/-10% B_H_DJ9
C20
B24
D8#
D9#
D40#
D41#
AA23
U26 B_H_DJ41
B_H_AJ27 AE2 A12 XDP_TDO C0402 B_H_DJ10 D24 V24 B_H_DJ42
B_H_AJ28AD6 A27# TDO XDP_TMS B_H_DJ11 D10# D42# B_H_DJ43
A28# TMS C11 E24 D11# D43# U25
B_H_AJ29 AF3 B13 XDP_TRSTJ THERMDN B_H_DJ12 C26 V26 B_H_DJ44
B_H_AJ30 AE1 A29# TRST# XDP_DBRESETJ B_H_DJ13 D12# D44# B_H_DJ45
A30# DBR# A7 B23 D13# D45# Y23
C B_H_AJ31 AF1 B_H_DJ14 E23 AA26 B_H_DJ46 C
A31# CPU_PROCHOTJ B_H_DJ15 D14# D46# B_H_DJ47
6 B_H_ADSTBJ1 AE5 ADSTB#1 PROCHOT# B17 C25 D15# D47# Y25
B18 C23 W25
HCLK THERM
THERMDA THERMDP1 18 6 B_H_DSTBNJ0 DSTBN0# DSTBN2# B_H_DSTBNJ2 6
14 H_A20MJ C2 A20M# THERMDC A18 THERMDN 18 6 B_H_DSTBPJ0 C22 DSTBP0# DSTBP2# W24 B_H_DSTBPJ2 6
14 H_FERRJ D3 FERR# 6 B_H_DINVJ0 D25 DINV0# DINV2# T24 B_H_DINVJ2 6
14 H_IGNNEJ A3 IGNNE# THERMTRIP# C17 PM_THRMTRIPJ 7,14
14 H_STPCLKJ C6 A15 1 TP17 B_H_DJ16 H23 AB25 B_H_DJ48

STPCLK# ITP_CLK1 TP18 B_H_DJ17 D16# D48# B_H_DJ49
14 H_INTR D1 LINT0 ITP_CLK0 A16 1 G25 D17# D49# AC23
D4 B14 PM_THRMTRIP# B_H_DJ18 L23 AB24 B_H_DJ50
14 H_NMI LINT1 BCLK1 CLK_CPU_BCLKJ 3 D18# D50#
B4 B15 should connect to B_H_DJ19 M26 AC20 B_H_DJ51
DATA GRP 1
DATA GRP 3
14 H_SMIJ SMI# BCLK0 CLK_CPU_BCLK 3 D19# D51#
ICH6 and Alviso B_H_DJ20 H24 AC22 B_H_DJ52
without T-ing B_H_DJ21 D20# D52# B_H_DJ53
F25 D21# D53# AC25
( No stub) B_H_DJ22 G24 AD23 B_H_DJ54
Dothan_Socket479 D22# D54#
B_H_DJ23 J23 AE22 B_H_DJ55
B_H_DJ24 D23# D55# B_H_DJ56
M23 D24# D56# AF23
B_H_DJ25 J25 AD24 B_H_DJ57 Layout Note:
B_H_DJ26 D25# D57# B_H_DJ58 Comp0, 2 connect with Zo=27.4 ohm, make
L26 D26# D58# AF20
B_H_DJ27 N24 AE21 B_H_DJ59 trace length shorter than 0.5" .
B_H_DJ28 D27# D59# B_H_DJ60 Comp1, 3 connect with Zo=55 ohm, make
M25 D28# D60# AD21
1D05V_S0 B_H_DJ29 H26 AF25 B_H_DJ61 trace length shorter than 0.5" .
B_H_DJ30 D29# D61# B_H_DJ62
N25 D30# D62# AF22
B_H_DJ31 K25 AF26 B_H_DJ63
CPU_PROCHOTJ R519 56 R0402 +/-5% D31# D63#
6 B_H_DSTBNJ1 K24 DSTBN1# DSTBN3# AE24 B_H_DSTBNJ3 6
6 B_H_DSTBPJ1 L24 DSTBP1# DSTBP3# AE25 B_H_DSTBPJ3 6
XDP_TDI R47 150 R0402 +/-5% J26 AD20
6 B_H_DINVJ1 DINV1# DINV3# B_H_DINVJ3 6 1D05V_S0
B XDP_TMS R48 39.2 R0402 +/-1% To V-CORE SWITCH 1E1 P25 COMP0 R50 27.4 R0402 +/-1% B
TP20 PSI# COMP0 COMP1 R51 54.9 R0402 +/-1%
COMP1 P26
XDP_TDO R52 54.9 R0402 +/-1% 3 CPU_SEL0 C16 AB2 COMP2 R53 27.4 R0402 +/-1%
BSEL0 COMP2 COMP3 R54 54.9 R0402 +/-1% R56
3 CPU_SEL1 C14 BSEL1 COMP3 AB1
H_CPURSTJ R55 54.9 R0402 +/-1% 200
+/-1%
XDP_DBRESETJ R57 150 R0402 +/-5% 1D05V_S0 MISC G1 R0402
DPRSTP# H_DPRSLPJ 14
C3 RSVD2 DPSLP# B7 H_DPSLPJ 14
AF7 RSVD3 DPWR# C19 H_DPWRJ 6
R58 AC1 E4
RSVD4 PWRGOOD H_PWRGD 14
1K E26 A6
RSVD5 SLP# H_CPUSLPJ 6,14
+/-1%
R0402 GTLREF0 AD26 C5 TEST1
XDP_TCK R59 27.4 R0402 +/-1% GTLREF0 TEST1 TEST2
TEST2 F23
Layout Note:
XDP_TRSTJ R60 680 R0402 +/-5% R61 0.5" max length.
2K Dothan_Socket479
All place within 2" to CPU +/-1% R62 R63
R0603 1K 1K
+/-5% +/-5%
R0402 R0402
Dummy Dummy
A A
TECHNOLOGY COPR.
Title
Document Number
CPU(1 of 2) Rev
S09 MAINBOARD A
Date: Monday, March 14, 2005 Sheet 4 of 45
5 4 3 2 1
5 4 3 2 1
1D05V_S0 U2D
VCC_CORE_S0
A2 VSS0 VSS97 D13
VCC_CORE_S0 A5 D15
VSS1 VSS98
U2C A8 VSS2 VSS99 D17
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
TC1 A11 D19
VSS3 VSS100
1
*
BC16
BC17
BC18
BC19
BC20
BC21
BC22
BC23
BC24
BC25
220uF
AA11 VCC0 VCC59 G5
* * * * * * * * * * 2.5V, +/-20%
A14
A17
VSS4
VSS5
VSS101
VSS102
D21
D23
AA13 H22 ctbh20 A20 D26
2
VCC1 VCC60 VSS6 VSS103
AA15 VCC2 VCC61 H6 A23 VSS7 VSS104 E3
AA17 VCC3 VCC62 J21 A26 VSS8 VSS105 E6
AA19 VCC4 VCC63 J5 AA1 VSS9 VSS106 E8
D AA21 VCC5 VCC64 K22 AA4 VSS10 VSS107 E10 D
AA5 VCC6 VCC65 U5 AA6 VSS11 VSS108 E12
AA7 V22 1D5V_S0 AA8 E14
VCC7 VCC66 VSS12 VSS109
AA9 VCC8 VCC67 V6 AA10 VSS13 VSS110 E16
AB10 VCC9 VCC68 W21 AA12 VSS14 VSS111 E18
AB12 W5 R504 AA14 E20
VCC10 VCC69 +/-5% VSS15 VSS112
AB14 VCC11 VCC70 Y22 0 AA16 VSS16 VSS113 E22
AB16 VCC12 VCC71 Y6 R0603 AA18 VSS17 VSS114 E25
AB18 VCC13 1D5V_VCCA_S0 AA20 VSS18 VSS115 F1
AB20 F26 BC26 BC27 Place these AA22 F4
VCC14 VCCA0 10nF 10uF VSS19 VSS116
AB22
AB6
VCC15
VCC16
VCCA1
VCCA2
B1
N1
* * 10V, Y5V, +80%/-20%
and dummy AA25
AB3
VSS20
VSS21
VSS117
VSS118
F5
F7
AB8 AC26 1D05V_S0 C0402 C0805 12K7R3F for AB5 F9
VCC17 VCCA3 VSS22 VSS119
AC11 VCC18 1D8V_VCCA_S0 AB7 VSS23 VSS120 F11
AC13 D10 R510 R0603 +/-5% AB9 F13
VCC19 VCCP0 0 VSS24 VSS121
AC15 VCC20 VCCP1 D12 AB11 VSS25 VSS122 F15
AC17 VCC21 VCCP2 D14 12.7K 1.56V AB13 VSS26 VSS123 F17
AC19 VCC22 VCCP3 D16 AB15 VSS27 VSS124 F19
AC9 E11 11K 1.52V AB17 F21
VCC23 VCCP4 1D5V_VCCA_S0 VSS28 VSS125
AD10 VCC24 VCCP5 E13 AB19 VSS29 VSS126 F24
AD12 VCC25 VCCP6 E15 AB21 VSS30 VSS127 G2
AD14 VCC26 VCCP7 F10 AB23 VSS31 VSS128 G6
AD16 VCC27 VCCP8 F12 AB26 VSS32 VSS129 G22
AD18 F14 BC551 R599 AC2 G23
VCC28 VCCP9 22pF 11K VSS33 VSS130
AD8
AE11
VCC29
VCC30
VCCP10
VCCP11
F16
K6
I max = 120 mA *
C0402 +/-1%
AC5
AC8
VSS34
VSS35
VSS131
VSS132
G26
H3
AE13 L21 U27 50V, NPO, +/-5% R0402 AC10 H5
VCC31 VCCP12 Dummy Dummy VSS36 VSS133
C AE15 L5 AC12 H21 C
AE17
AE19
VCC32
VCC33
VCC34
VCCP13
VCCP14
VCCP15
M22
M6
3D3V_S0 1
2
SHDN#
GND
SET 5 AC14
AC16
VSS37
VSS38
VSS39
VSS134
VSS135
VSS136
H25
J1
10V, Y5V, +80%/-20%

AE9 VCC35 VCCP16 N21 3 IN OUT 4 AC18 VSS40 VSS137 J4
AF10 N5 R505 AC21 J6
VCC36 VCCP17 BC552 BC553 49.9K VSS41 VSS138
AF12 VCC37 VCCP18 P22 AC24 VSS42 VSS139 J22
1uF 1uF +/-1%
AF14
AF16
VCC38
VCC39
VCCP19
VCCP20
P6
R21 10V, Y5V, +80%/-20% * G913C
* R0402
AD1
AD4
VSS43
VSS44
VSS140
VSS141
J24
K2
AF18 R5 C0603 Dummy C0603 Dummy AD7 K5
VCC40 VCCP21 Dummy Dummy VSS45 VSS142
AF8 VCC41 VCCP22 T22 AD9 VSS46 VSS143 K21
D18 VCC42 VCCP23 T6 AD11 VSS47 VSS144 K23
D20 VCC43 VCCP24 U21 AD13 VSS48 VSS145 K26
D22 VCC44 AD15 VSS49 VSS146 L3
D6 VCC45 VCCQ0 P23 AD17 VSS50 VSS147 L6
D8 VCC46 VCCQ1 W4 AD19 VSS51 VSS148 L22
E17 VCC47 AD22 VSS52 VSS149 L25
E19 E2 VCC_CORE_S0 AD25 M1
VCC48 VID0 H_VID0 39 VSS53 VSS150
E21 VCC49 VID1 F2 H_VID1 39 AE3 VSS54 VSS151 M4
E5 VCC50 VID2 F3 H_VID2 39 AE6 VSS55 VSS152 M5
10uF C0805
10uF C0805
10uF C0805
10uF C0805
C0805
E7 VCC51 VID3 G3 H_VID3 39 AE8 VSS56 VSS153 M21
BC28
BC29
BC30
BC31
BC32
E9
F18
VCC52
VCC53
VID4
VID5
G4
H4
H_VID4
H_VID5
39
39
* * * * * AE10
AE12
VSS57
VSS58
VSS154
VSS155
M24
N3
10uF
F20 VCC54 AE14 VSS59 VSS156 N6
F6 AE7 TP_VCCSENSE AE18 N23
VCC56 VCCSENSE VSS61 VSS158
G21 AF6 TP_VSSSENSE AE23 P2
VCC58 VSSSENSE VSS63 VSS160
B AE26 VSS64 VSS161 P5 B
AF2 VSS65 VSS162 P21
Dothan_Socket479 R64 R65 AF5 P24
54.9 54.9 VSS66 VSS163
AF9 VSS67 VSS164 R1
+/-1% +/-1% AF11 R4
R0402 R0402 VCC_CORE_S0 VSS68 VSS165
AF13 VSS69 VSS166 R6
Dummy Dummy AF15 R22
VSS70 VSS167
AF17 VSS71 VSS168 R25
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
AF19 VSS72 VSS169 T3
BC624
BC625
BC626
BC627
Layout Note: BC628

Provide a test point (with * * * * * AF21
AF24
VSS73
VSS74
VSS170
VSS171
T5
T21
no stub) to connect a B3 T23
Layout Note: differential probe VSS75 VSS172
B6 VSS76 VSS173 T26
VCCSENSE and VSSSENSE lines between VCCSENSE and B9 U2
should be of equal length. VSSSENSE at the location VSS77 VSS174
B12 VSS78 VSS175 U6
where the two 54.9ohm B16 U22
resistors terminate the VSS79 VSS176
B19 VSS80 VSS177 U24
VCC_CORE_S0 55 ohm transmission line. B22 V1
VSS81 VSS178
B25 VSS82 VSS179 V4
10V, Y5V, +80%/-20% C1 V5
VSS83 VSS180
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
C4 VSS84 VSS181 V21

BC33
BC34
BC35
BC36
BC37
BC38
BC39
BC40
BC41
BC42
BC43
BC44
BC45
BC46
BC47
BC48
BC49
BC50
* * * * * * * * * * * * * * * * * * C7
C10
VSS85
VSS86
VSS182
VSS183
V25
W3
C13 VSS87 VSS184 W6
C15 VSS88 VSS185 W22
A C24 VSS91 VSS188 Y2 A
D2 VSS92 VSS189 Y5
VCC_CORE_S0 D5 Y21
VSS93 VSS190
D7 VSS94 VSS191 Y24
10V, X5R, +/-10% D9 VSS95
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
0.1uF C0402
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
10uF C0805
D11 VSS96 TECHNOLOGY COPR.

BC51
BC52
BC53
BC54
BC55
BC56
BC57
BC58
BC59
BC60
BC61
BC62
BC63
BC64
BC65
BC66
BC67
* * * * * * * * * * * * * * * * * Title
Dothan_Socket479
Document Number
CPU(2 of 2) Rev
Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
S09 MAINBOARD A
Date: Thursday, March 17, 2005 Sheet 5 of 45
5 4 3 2 1
5 4 3 2 1
H_XRCOMP
R66 U3A
4 B_H_DJ[63..0]
24.9 B_H_AJ[31..3] 4
+/-1% B_H_DJ0 E4 G9 B_H_AJ3
R0402 B_H_DJ1 HD0# HA3# B_H_AJ4
E1 HD1# HA4# C9
B_H_DJ2 F4 E9 B_H_AJ5
B_H_DJ3 HD2# HA5# B_H_AJ6
H7 HD3# HA6# B7
D B_H_DJ4 E2 A10 B_H_AJ7 D
Place them near to the chip B_H_DJ6
F1
E3
HD5# HA8# F9
D8 B_H_AJ9
D3 HD7# HA10# B10
1D05V_S0 B_H_DJ8 K7 E10 B_H_AJ11
F2 HD9# HA12# G10
B_H_DJ10 J7 D9 B_H_AJ13
HD10# HA13#
B_H_DJ11
B_H_DJ12
J8
H6
HD11#
HD12#
HA14#
HA15#
E11
F10
B_H_AJ14
B_H_AJ15 www.hocnghetructuyen.vn
R67 B_H_DJ13 F3 G11 B_H_AJ16
54.9 B_H_DJ14 HD13# HA16# B_H_AJ17
K8 HD14# HA17# G13
+/-1% B_H_DJ15 H5 C10 B_H_AJ18
R0402 B_H_DJ16 HD15# HA18# B_H_AJ19
H1 HD16# HA19# C11
B_H_DJ17 H2 D11 B_H_AJ20
H_XSCOMP B_H_DJ18 HD17# HA20# B_H_AJ21
K5 HD18# HA21# C12
B_H_DJ19 B_H_AJ22
K6
J4
HD19# HA22# B13
A12 B_H_AJ23
G3 HD21# HA24# F12
1D05V_S0 B_H_DJ22 H3 G12 B_H_AJ25
J1 HD23# HA26# E12
B_H_DJ24 L5 C13 B_H_AJ27 1D05V_S0
R68 B_H_DJ25 HD24# HA27# B_H_AJ28
K4 HD25# HA28# B11
221 B_H_DJ26 J5 D13 B_H_AJ29
+/-1% B_H_DJ27 HD26# HA29# B_H_AJ30
P7 HD27# HA30# A13
R0603 B_H_DJ28 L7 F13 B_H_AJ31 R69
B_H_DJ29 HD28# HA31# 100
J3 HD29#
H_XSWING B_H_DJ30 P5 F8 B_H_ADSJ 4 +/-1%
B_H_DJ31 HD30# HADS# R0402
C L3 HD31# HADSTB#0 B9 B_H_ADSTBJ0 4 C
BC68 B_H_DJ32 U7 E13 B_H_ADSTBJ1 4
R70 0.1uF B_H_DJ33 HD32# HADSTB#1 H_VREF
100 * 10V, X7R, +/-10% B_H_DJ34
V6
R6
HD33#
HD34#
HVREF
HBNR#
J11
A5 B_H_BNRJ 4
+/-1% C0402 B_H_DJ35 R5 D5 H_BPRIJ 4 BC69
R0402 B_H_DJ36 HD35# HBPRI# 0.1uF R71
B_H_DJ37
P3
T8
HD36#
HD37#
HBREQ0#
HCPURST#
E7
H10
B_H_BREQJ0
H_CPURSTJ
4
4
* 10V, X7R, +/-10% 200
B_H_DJ38 R7 C0402 +/-1%
B_H_DJ39 HD38# R0402
R8 HD39#
B_H_DJ40
Place them near to the chip U8
HOST
B_H_DJ41 HD40#
R4 HD41# HCLKINN AB1 CLK_MCH_BCLKJ 3
B_H_DJ42
B_H_DJ43
T4
T5
HD42# HCLKINP AB2 CLK_MCH_BCLK 3 Place them near to the chip
H_YRCOMP B_H_DJ44 HD43#
R1 HD44# HDBSY# C6 B_H_DBSYJ 4
B_H_DJ45 T3 E6 H_DEFERJ 4
B_H_DJ46 HD45# HDEFER# B_H_DINVJ0
V8 HD46# HDINV#0 H8 B_H_DINVJ0 4
B_H_DJ47 U6 K3 B_H_DINVJ1
R72 B_H_DJ48 HD47# HDINV#1 B_H_DINVJ2 B_H_DINVJ1 4
W6 HD48# HDINV#2 T7 B_H_DINVJ2 4
24.9 B_H_DJ49 U3 U5 B_H_DINVJ3
+/-1% B_H_DJ50 HD49# HDINV#3 B_H_DINVJ3 4
V5 HD50# HDPWR# G6 H_DPWRJ 4
R0402 B_H_DJ51 W8 F7 B_H_DRDYJ 4
B_H_DJ52 HD51# HDRDY# B_H_DSTBNJ0
W7 HD52# HDSTBN#0 G4 B_H_DSTBNJ0 4
B_H_DJ53 U2 K1 B_H_DSTBNJ1
B_H_DJ54 HD53# HDSTBN#1 B_H_DSTBNJ2 B_H_DSTBNJ1 4
U1
Y5
HD54# HDSTBN#2 R3
V3 B_H_DSTBNJ3 B_H_DSTBNJ2 4
B_H_DJ56 HD55# HDSTBN#3 B_H_DSTBPJ0 B_H_DSTBNJ3 4
Y2 HD56# HDSTBP#0 G5 B_H_DSTBPJ0 4
1D05V_S0 B_H_DJ57 V4 K2 B_H_DSTBPJ1
B_H_DJ58 HD57# HDSTBP#1 B_H_DSTBPJ2 B_H_DSTBPJ1 4
B Y7 HD58# HDSTBP#2 R2 B_H_DSTBPJ2 4 B
B_H_DJ59 W1 W4 B_H_DSTBPJ3
B_H_DJ60 HD59# HDSTBP#3 TP_H_EDRDYJ TP25 B_H_DSTBPJ3 4
W3 HD60# HEDRDY# F6 1
B_H_DJ61 Y3 D4
HD61# HHIT# B_H_HITJ 4
R73 B_H_DJ62 Y6 D6
HD62# HHITM# B_H_HITMJ 4
54.9 B_H_DJ63 W2 B3
HD63# HLOCK# B_H_LOCKJ 4
+/-1% A11 TP_H_PCREQJ
1 B_H_REQJ[4..0] 4
R0402 H_XRCOMP HPCREQ# B_H_REQJ0 TP26
C1 HXRCOMP HREQ#0 A7
H_XSCOMP C2 D7 B_H_REQJ1
H_YSCOMP H_XSWING HXSCOMP HREQ#1 B_H_REQJ2
D1 HXSWING HREQ#2 B8
H_YRCOMP T1 C7 B_H_REQJ3
H_YSCOMP HYRCOMP HREQ#3 B_H_REQJ4
Place them near to the chip H_YSWING
L1
P1
HYSCOMP HREQ#4 A8
A4 H_RSJ0
H_RSJ[2..0] 4
1D05V_S0 HYSWING HRS0# H_RSJ1
HRS1# C5
B4 H_RSJ2
HRS2# H_CPUSLPJ_0 R74 0 R0402 +/-5%
HCPUSLP# G8 H_CPUSLPJ 4,14
R75 B5 H_TRDYJ 4
221 HTRDY#
+/-1%
R0603 DUMMY FOR DOTHAN A STEPPING
ALVISO-GM
H_YSWING 71.0GMCH.08U
BC70
R76 0.1uF
100 * 10V, X7R, +/-10%
+/-1% C0402
A R0402 A
Place them near to the chip TECHNOLOGY COPR.

Title
Document Number
GMCH(1 of 5) Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
Alviso will provide SDVO_CTRLCLK

and CTRLDATA pulldowns on-die 1D5V_PCIE_S0
1D05V_S0 U3G
U3B R0402
H24 SDVOCTRL_DATA EXP_COMPI D36 PEG_COMP R80 24.9 +/-1%
DMI_TXN0 R81 10K +/-5% R0402
MISC
15 DMI_TXN0 AA31 DMIRXN0 CFG0 G16 H25 SDVOCTRL_CLK EXP_ICOMPO D34
DMI_TXN1 AB35 H13 3 CLK_MCH_3GPLLJ AB29
15 DMI_TXN1 DMIRXN1 CFG1 MCH_BSEL1 3 GCLKN
DMI_TXN2 AC31 G14 3 CLK_MCH_3GPLL AC29 E30
15 DMI_TXN2 DMIRXN2 CFG2 MCH_BSEL0 3 GCLKP EXP_RXN0
DMI_TXN3 AD35 F16 F34
15 DMI_TXN3 DMIRXN3 CFG3 EXP_RXN1
F15 TP_CFG4 1 TP29 A15 G30
DMI_TXP0 CFG4 CFG5 33 GMCH_TV_COM TVDAC_A EXP_RXN2
15 DMI_TXP0 Y31 DMIRXP0 CFG5 G15 33 GMCH_TV_LUMA C16 TVDAC_B EXP_RXN3 H34
DMI_TXP1 AA35 E16 CFG6 33 GMCH_TV_CRMA A17 J30
15 DMI_TXP1 DMIRXP1 CFG6 TVDAC_C EXP_RXN4
DMI_TXP2 AB31 D17 CFG7 1 TP30 GMCH_TV_RST J18 K34
15 DMI_TXP2 DMIRXP2 CFG7 TV_REFSET EXP_RXN5
TV
D DMI_TXP3 CFG8 R84 R85 R86 D
15 DMI_TXP3 AC35 DMIRXP3 CFG8 J16 B15 TV_IRTNA EXP_RXN6 L30
D15 150 150 150 R83 B16 M34
DMI
CFG9 TV_IRTNB EXP_RXN7
CFG/RSVD
DMI_RXN0 AA33 E15 TP_CFG10 1 TP31 +/-5% +/-5% +/-5% 4.99K B17 N30
15 DMI_RXN0 DMI_RXN1 DMITXN0 CFG10 R0402 R0402 R0402 TV_IRTNC EXP_RXN8
15 DMI_RXN1 AB37 DMITXN1 CFG11 D14 +/-1% EXP_RXN9 P34
DMI_RXN2 AC33 E14 R30
15 DMI_RXN2 DMI_RXN3 DMITXN2 CFG12 EXP_RXN10
15 DMI_RXN3 AD37 DMITXN3 CFG13 H12 EXP_RXN11 T34
C14 TP_CFG14 1 TP32 Layout Note:place this 3 U30
DMI_RXP0 CFG14 EXP_RXN12
15 DMI_RXP0 Y33 DMITXP0 CFG15 H15 resistors beside GMCH in 0.5 iches EXP_RXN13 V34
DMI_RXP1 AA37 J15 CFG16 W30
15 DMI_RXP1 DMI_RXP2 DMITXP1 CFG16 EXP_RXN14
15 DMI_RXP2 AB33 DMITXP2 CFG17 H14 12 GMCH_DDCCLK E24 DDCCLK EXP_RXN15 Y34
DMI_RXP3 AC37 G22 CFG18 12 B_GMCH_DDCDATA E23
15 DMI_RXP3 DMITXP3 CFG18 DDCDATA
CFG19 G23 12 GMCH_BLUE E21 BLUE EXP_RXP0 D30
CFG20 D23 D21 BLUE# EXP_RXP1 E34
AM33 G25 C20 F30
VGA
11 CLK_DDR0 SM_CK0 RSVD21 12 GMCH_GREEN GREEN EXP_RXP2
11 CLK_DDR1 AL1 SM_CK1 RSVD22 G24 B20 GREEN# EXP_RXP3 G34
AE11 SM_CK2 RSVD23 J17 12 GMCH_RED A19 RED EXP_RXP4 H30
11 CLK_DDR3 AJ34 SM_CK3 RSVD24 A31 B19 RED# EXP_RXP5 J34
11 CLK_DDR4 AF6 A30 12 GMCH_VSYNC R88 39R0402 +/-5% VSYNC H21 K30
SM_CK4 RSVD25 R89 39R0402 +/-5% HSYNC VSYNC EXP_RXP6
AC10 SM_CK5 RSVD26 D26 12 GMCH_HSYNC G21 HSYNC EXP_RXP7 L34
D25 R90 255 R0402 +/-1% CRTIREF J20 M30
PCI-EXPRESS GRAPHICS
RSVD27 REFSET EXP_RXP8
11 CLK_DDR0J AN33 SM_CK0# EXP_RXP9 N34
11 CLK_DDR1J AK1 SM_CK1# EXP_RXP10 P30
AE10 SM_CK2# EXP_RXP11 R34
11 CLK_DDR3J AJ33 SM_CK3# EXP_RXP12 T30
11 CLK_DDR4J AF5 SM_CK4# EXP_RXP13 U34
AD10 SM_CK5# 13 LBKLT_CRTL E25 LBKLT_CRTL EXP_RXP14 V30
30 GMCH_BL_ON F25 LBKLT_EN EXP_RXP15 W34
11 M_CKE0_RJ AP21 LCTLA_CLK C23
SM_CKE0 LCTLA_CLK
MUXING
11 M_CKE1_RJ AM21 LCTLB_DATA C22 E32

SM_CKE1 LDDC_NB_CLK LCTLB_DATA EXP_TXN0
11 M_CKE2_RJ AH21 SM_CKE2 BM_BUSY# J23 PM_BMBUSYJ 15 F23 LDDC_CLK EXP_TXN1 F36
11 M_CKE3_RJ AK21 SM_CKE3 EXT_TS0# J21 PM_EXTTSJ0 B_LDDC_NB_DATA F22
LDDC_DATA EXP_TXN2 G32
EXT_TS1# H22 PM_EXTTSJ1 13 GMCH_LCDVDD_ON F26 LVDD_EN EXP_TXN3 H36
C LIBG C
AN16 F5 C33 J32
PM
11 M_CS0_RJ SM_CS0# THRMTRIP# PM_THRMTRIPJ 4,14 LIBG EXP_TXN4

11 M_CS1_RJ AM14 AD30 TP33 1 L_LVBG C31 K36
SM_CS1# PWROK VROK 15,16 LVBG EXP_TXN5
DDR
11 M_CS2_RJ AH15 AE29 R94 100 TP34 1 L_VREFH F28 L32

SM_CS2# RSTIN# PLT_RST1J 15,17,30 NO STUFF LVREFH EXP_TXN6
11 M_CS3_RJ AG16 R0402 +/-5% TP35 1 L_VREFL F27 M36
SM_CS3# LVREFL EXP_TXN7
LVDS
DREF_CLKN A24 DREFCLKJ 3 EXP_TXN8 N32
M_OCDCOMP0 AF22 A23 GMCH_TXACLK- B30 P36
CLK
SM_OCDCOMP0 DREF_CLKP DREFCLK 3 13 GMCH_TXACLK- LACLKN EXP_TXN9

M_OCDCOMP1 AF16 C37 13 GMCH_TXACLK+ GMCH_TXACLK+ B29 R32
SM_OCDCOMP1 DREF_SSCLKN DREFSSCLKJ 3 LACLKP EXP_TXN10
DREF_SSCLKP D37 DREFSSCLK 3 C25 LBCLKN EXP_TXN11 T36
R95 R96 AP14 C24 U32
11 M_ODT0 SM_ODT0 LBCLKP EXP_TXN12
40.2 40.2 AL15 AP37 V36
11 M_ODT1 SM_ODT1 NC1 EXP_TXN13
+/-1% +/-1% AM11 AN37 13 GMCH_TXAOUT0- GMCH_TXAOUT0- B34 W32
11 M_ODT2 SM_ODT2 NC2 LADATAN0 EXP_TXN14
R0402 R0402 AN10 AP36 13 GMCH_TXAOUT1- GMCH_TXAOUT1- B33 Y36
11 M_ODT3 SM_ODT3 NC3 LADATAN1 EXP_TXN15
Dummy Dummy AP2 13 GMCH_TXAOUT2- GMCH_TXAOUT2- B32
M_RCOMPN NC4 LADATAN2
AK10 SMRCOMPN NC5 AP1 EXP_TXP0 D32
M_RCOMPP AK11 AN1 E36
SMRCOMPP NC6 GMCH_TXAOUT0+ EXP_TXP1
AF37 B1 A34 F32
NC
DDR_VREF SMVREF0 NC7 13 GMCH_TXAOUT0+ LADATAP0 EXP_TXP2

AD1 A2 13 GMCH_TXAOUT1+ GMCH_TXAOUT1+ A33 G36
SMVREF1 NC8 LADATAP1 EXP_TXP3
2.2uF
0.1uF
2.2uF
0.1uF
SMXSLEW AE27 B37 13 GMCH_TXAOUT2+ GMCH_TXAOUT2+ B31 H32

SMXSLEWIN NC9 LADATAP2 EXP_TXP4
AE28 SMXSLEWOUT NC10 A36 EXP_TXP5 J36
SMYSLEW AF9 A37 C29 K32
SMYSLEWIN NC11 LBDATAN0 EXP_TXP6
* * * * AF10 SMYSLEWOUT D28
C27
LBDATAN1
LBDATAN2
EXP_TXP7
EXP_TXP8
L36
M32
C0805
C0402
C0805
C0402
BC96
BC97
BC98
BC99
EXP_TXP9 N36
ALVISO-GM C28 LBDATAP0 EXP_TXP10 P32
71.0GMCH.08U D27 LBDATAP1 EXP_TXP11 R36
C26 LBDATAP2 EXP_TXP12 T32
EXP_TXP13 U36
EXP_TXP14 V32
2D5V_S0 W36
EXP_TXP15
CFG18 R632 2.2K +/-5% R0402 @GM

For NB_CORE=1.5V Strap
B
ALVISO-GM B
2D5V_S0 CFG5 R102 2.2K +/-5% R0402 Dummy 71.0GMCH.08U
R98 10K PM_EXTTSJ0 CFG6 R103 2.2K +/-5% R0402

R0402 +/-5%
For DDR2 Strap
CFG7 R105 2.2K +/-5% R0402 Dummy 2D5V_S0 2D5V_S0 3D3V_S0
R101 10K PM_EXTTSJ1 CFG8 R108 2.2K +/-5% R0402 Dummy

R0402 +/-5% R506
CFG16 R109 2.2K +/-5% R0402 Dummy 2.2K
+/-5%
R0402
R507 R508
R106 R107 2.2K 2.2K
2.2K 2.2K +/-5% +/-5%
G
VDIMM www.hocnghetructuyen.vn LDDC_NB_CLK
+/-5%
R0402
+/-5%
R0402
Q18
S D
R0402
LDDC_CLK
R0402
LDDC_CLK 13
R104
80.6 2N7002EPT
G
+/-1%
R0402 Layout Note:place this 3 Q19
M_RCOMPN resistors beside GMCH in 0.5 iches B_LDDC_NB_DATA S D LDDC_DATA
LDDC_DATA 13
M_RCOMPP
GMCH_BLUE 2N7002EPT
R110
80.6 GMCH_GREEN 2D5V_S0
+/-1%
R0402 GMCH_RED LCTLA_CLK R111 2.2K R0402 +/-5%
A R113 R114 R115 LCTLB_DATA R112 2.2K R0402 +/-5% A

150 150 150
+/-5% +/-5% +/-5%
R0402 R0402 R0402
GMCH_BL_ON R117 100KR0402 +/-5%

TECHNOLOGY COPR.
LBKLT_CRTL R119 100KR0402 +/-5%
Title
LIBG R120 1.5K R0603 +/-1%
Document Number
GMCH(2 of 5) Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
M_A_DQ[63:0] 11
U3C M_B_DQ[63:0] 11
U3D
D M_A_DQ0 AG35 AK15 D
SADQ0 SA_BS0# M_A_BSJ0 11
M_A_DQ1 AH35 AK16 M_B_DQ0 AE31 AJ15
SADQ1 SA_BS1# M_A_BSJ1 11 SBDQ0 SB_BS0# M_B_BSJ0 11
M_A_DQ2 AL35 AL21 M_B_DQ1 AE32 AG17
SADQ2 SA_BS2# M_A_BSJ2 11 SBDQ1 SB_BS1# M_B_BSJ1 11
M_A_DQ3 AL37 M_B_DQ2 AG32 AG21
SADQ3 M_A_DM[7:0] 11 SBDQ2 SB_BS2# M_B_BSJ2 11
M_A_DQ4 AH36 AJ37 M_A_DM0 M_B_DQ3 AG36
SADQ4 SA_DM0 SBDQ3 M_B_DM[7:0] 11
M_A_DQ5 AJ35 AP35 M_A_DM1 M_B_DQ4 AE34 AF32 M_B_DM0
M_A_DQ6 SADQ5 SA_DM1 M_A_DM2 M_B_DQ5 SBDQ4 SB_DM0 M_B_DM1
AK37 SADQ6 SA_DM2 AL29 AE33 SBDQ5 SB_DM1 AK34
M_A_DQ7 AL34 AP24 M_A_DM3 M_B_DQ6 AF31 AK27 M_B_DM2
AM36 SADQ8 SA_DM4 AP9 AF30 SBDQ7 SB_DM3 AK24
M_A_DQ9 AN35 AP4 M_A_DM5 M_B_DQ8 AH33 AJ10 M_B_DM4
AP32 SADQ10 SA_DM6 AJ2 AH32 SBDQ9 SB_DM5 AK5
M_A_DQ11 AM31 AD3 M_A_DM7 M_B_DQ10 AK31 AE7 M_B_DM6
M_A_DQ12 SADQ11 SA_DM7 M_B_DQ11 SBDQ10 SB_DM6 M_B_DM7
AM34 SADQ12 M_A_DQS[7:0] 11 AG30 SBDQ11 SB_DM7 AB7
M_A_DQ13 AM35 AK36 M_A_DQS0 M_B_DQ12 AG34
SADQ13 SA_DQS0 SBDQ12 M_B_DQS[7:0] 11
M_A_DQ14 AL32 AP33 M_A_DQS1 M_B_DQ13 AG33 AF34 M_B_DQS0
M_A_DQ15 SADQ14 SA_DQS1 M_A_DQS2 M_B_DQ14 SBDQ13 SB_DQS0 M_B_DQS1
AM32 SADQ15 SA_DQS2 AN29 AH31 SBDQ14 SB_DQS1 AK32
M_A_DQ16 AN31 AP23 M_A_DQS3 M_B_DQ15 AJ31 AJ28 M_B_DQS2
AP31 SADQ17 SA_DQS4 AM8 AK30 SBDQ16 SB_DQS3 AK23
M_A_DQ18 AN28 AM4 M_A_DQS5 M_B_DQ17 AJ30 AM10 M_B_DQS4
AP28 SADQ19 SA_DQS6 AJ1 AH29 SBDQ18 SB_DQS5 AH6
M_A_DQ20 AL30 AE5 M_A_DQS7 M_B_DQ19 AH28 AF8 M_B_DQS6
M_A_DQ21 SADQ20 SA_DQS7 M_B_DQ20 SBDQ19 SB_DQS6 M_B_DQS7
AM30 SADQ21 M_A_DQSJ[7:0] 11 AK29 SBDQ20 SB_DQS7 AB4
M_A_DQ22 AM28 AK35 M_A_DQSJ0 M_B_DQ21 AH30
SADQ22 SA_DQS0# SBDQ21 M_B_DQSJ[7:0] 11
M_A_DQ23 AL28 AP34 M_A_DQSJ1 M_B_DQ22 AH27 AF35 M_B_DQSJ0
SADQ23 SA_DQS1# SBDQ22 SB_DQS0#
DDR SYSTEM MEMORY A
M_A_DQ24 AP27 AN30 M_A_DQSJ2 M_B_DQ23 AG28 AK33 M_B_DQSJ1

M_A_DQ25 SADQ24 SA_DQS2# M_A_DQSJ3 M_B_DQ24 SBDQ23 SB_DQS1# M_B_DQSJ2
AM27 SADQ25 SA_DQS3# AN23 AF24 SBDQ24 SB_DQS2# AK28
M_A_DQ26 AM23 AN8 M_A_DQSJ4 M_B_DQ25 AG23 AJ23 M_B_DQSJ3
DDR SYSTEM MEMORY B

C AM22 SADQ27 SA_DQS5# AM5 AJ22 SBDQ26 SB_DQS4# AL10 C
M_A_DQ28 AL23 AH1 M_A_DQSJ6 M_B_DQ27 AK22 AH7 M_B_DQSJ5
AM24 SADQ29 SA_DQS7# AE4 AH24 SBDQ28 SB_DQS6# AF7
M_A_DQ30 AN22 M_B_DQ29 AH23 AB5 M_B_DQSJ7
SADQ30 M_A_A[13:0] 11 SBDQ29 SB_DQS7#
M_A_DQ31 AP22 AL17 M_A_A0 M_B_DQ30 AG22
SADQ31 SA_MA0 SBDQ30 M_B_A[13:0] 11
M_A_DQ32 AM9 AP17 M_A_A1 M_B_DQ31 AJ21 AH17 M_B_A0
M_A_DQ33 SADQ32 SA_MA1 M_A_A2 M_B_DQ32 SBDQ31 SB_MA0 M_B_A1
AL9 SADQ33 SA_MA2 AP18 AG10 SBDQ32 SB_MA1 AK17
M_A_DQ34 AL6 AM17 M_A_A3 M_B_DQ33 AG9 AH18 M_B_A2
AP7 SADQ35 SA_MA4 AN18 AG8 SBDQ34 SB_MA3 AJ18
M_A_DQ36 AP11 AM18 M_A_A5 M_B_DQ35 AH8 AK18 M_B_A4
AP10 SADQ37 SA_MA6 AL19 AH11 SBDQ36 SB_MA5 AJ19
M_A_DQ38 AL7 AP20 M_A_A7 M_B_DQ37 AH10 AK19 M_B_A6
AM7 SADQ39 SA_MA8 AM19 AJ9 SBDQ38 SB_MA7 AH19
M_A_DQ40 AN5 AL20 M_A_A9 M_B_DQ39 AK9 AJ20 M_B_A8
AN6 SADQ41 SA_MA10 AM16 AJ7 SBDQ40 SB_MA9 AH20
M_A_DQ42 AN3 AN20 M_A_A11 M_B_DQ41 AK6 AJ16 M_B_A10
AP3 SADQ43 SA_MA12 AM20 AJ4 SBDQ42 SB_MA11 AG18
M_A_DQ44 AP6 AM15 M_A_A13 M_B_DQ43 AH5 AG20 M_B_A12
M_A_DQ45 SADQ44 SA_MA13 M_B_DQ44 SBDQ43 SB_MA12 M_B_A13
AM6 SADQ45 AK8 SBDQ44 SB_MA13 AG15
M_A_DQ46 AL4 AN15 M_B_DQ45 AJ8
SADQ46 SA_CAS# M_A_CASJ 11 SBDQ45
M_A_DQ47 AM3 AP16 M_B_DQ46 AJ5
SADQ47 SA_RAS# M_A_RASJ 11 SBDQ46
M_A_DQ48 AK2 AF29 TP_MA_RCVENINJ 1 TP40 M_B_DQ47 AK4 AH14
SADQ48 SA_RCVENIN# SBDQ47 SB_CAS# M_B_CASJ 11
M_A_DQ49 AK3 AF28 TP_MA_RCVENOUTJ 1 TP42 M_B_DQ48 AG5 AK14
SADQ49 SA_RCVENOUT# SBDQ48 SB_RAS# M_B_RASJ 11
M_A_DQ50 AG2 AP15 M_B_DQ49 AG4 AF15 TP_MB_RCVENINJ 1 TP41
SADQ50 SA_WE# M_A_WEJ 11 SBDQ49 SB_RCVENIN#
M_A_DQ51 AG1 M_B_DQ50 AD8 AF14 TP_MB_RCVENOUTJ 1 TP43
M_A_DQ52 SADQ51 M_B_DQ51 SBDQ50 SB_RCVENOUT#
AL3 SADQ52 AD9 SBDQ51 SB_WE# AH16 M_B_WEJ 11
M_A_DQ53 AM2 M_B_DQ52 AH4
M_A_DQ54 SADQ53 M_B_DQ53 SBDQ52
B AH3 SADQ54 AG6 SBDQ53 B
M_A_DQ55 AG3 M_B_DQ54 AE8 Place Test PAD Near to Chip
AF3 SADQ56 AD7 SBDQ55 ascould as possible
M_A_DQ57 AE3 M_B_DQ56 AC5
AD6 SADQ58 AB8 SBDQ57
M_A_DQ59 AC4 M_B_DQ58 AB6
AF2 SADQ60 AA8 SBDQ59
M_A_DQ61 AF1 M_B_DQ60 AC8
AD4 SADQ62 AC7 SBDQ61
M_A_DQ63 AD5 M_B_DQ62 AA4
SADQ63 M_B_DQ63 SBDQ62
AA5 SBDQ63
ALVISO-GM
ALVISO-GM
A A
TECHNOLOGY COPR.
Title
GMCH(3 of 5)
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
A
B
C
D
3D3V_S0
BC136
5
5
10uF C0805
R0603
10V, Y5V, +80%/-20%
R138
R136
R130
R126
R121
NB_CORE_S0
BC137
*
10
10uF C0805
10V, Y5V, +80%/-20%
*
*
*
*
+/-1%
BC138
*
0.1uF
0.1uF
0.1uF
0.1uF
0 R0603 +/-5%
0 R0603 +/-5%
0 R0603 +/-5%
0 R0603 +/-5%
C0402
C0402
C0402
C0402
BC126
BC123
BC116
BC112
then connect to the gnd plane

decoupling cap groung lead and
10uF C0805
Route ASSATVBG gnd from GMCH to

10V, Y5V, +80%/-20%
BC139
10V, X5R, +/-10%

10V, X5R, +/-10%
10V, X5R, +/-10%
10V, X5R, +/-10%
*
1D5V_S0_L 2
0.1uF C0402
3D3V_TVDACB_S0
3D3V_TVDACC_S0
3D3V_ATVBG_S0
3D3V_TVDACA_S0
D1
BC140
SSM5818
T29 VCC0 VCCA_TVDACA0 F17

R29 E17
1
*
VCC1 VCCA_TVDACA1
N29 VCC2 VCCA_TVDACB0 D18
0.1uF C0402 M29 C18
VCC3 VCCA_TVDACB1
K29 VCC4 VCCA_TVDACC0 F18
J29 VCC5 VCCA_TVDACC1 E18
BC141 V28
1D5V_S0
VCC6
U28 H18
*
VCC7 VCCA_TVBG
T28 VCC8 VSSA_TVBG G18
0.1uF C0402 R28 VCC9
P28 VCC10 VCCD_TVDAC D19
N28 VCC11 VCCDQ_TVDAC H17
BC142 M28 VCC12
L28 B26
*
VCC13 VCCD_LVDS0
4
4
K28 VCC14 VCCD_LVDS1 B25

0.1uF C0402
Dummy
J28 VCC15 VCCD_LVDS2 A25
1D5V_S0
10V, X5R, +/-10% H28 VCC16
G28 VCC17 VCCA_LVDS A35
V27 2D5V_ALVDS_S0
VCC18
U27 B22
1D5V_DLVDS_S0
VCC19 VCCHV0
T27 VCC20 VCCHV1 B21
R27 VCC21 VCCHV2 A21
* * * * P27 VCC22 V1.8_DDR_CAP1
L5
L4
L3
L2
N27 AM37
1D5V_TVDAC_S0
VCC23 VCCSM0 V1.8_DDR_CAP2

*
M27 AH37
1D5V_QTVDAC_S0
VCC24 VCCSM1
*
L27 AP29 V1.8_DDR_CAP5

*
*
VCC25 VCCSM2
K27 AD28
L0805 1uH
L0805 1uH
L0805 1uH
L0805 1uH
VCC26 VCCSM3
0.1uF
J27 AD27
C0402
BC124
VCC27 VCCSM4
0.1uF
H27 AC27
C0402
0.1uF
0.1uF
BC127
VCC28 VCCSM5
C0402
C0402
BC115
BC110
K26 AP26
*
*
*
*
VCC29 VCCSM6
H26 VCC30 VCCSM7 AN26
*
R128
K25 VCC31 VCCSM8 AM26
10uF
10uF
10uF
10uF
J25 AL26
0.1uF
VCC32 VCCSM9
C0805
C0805
C0805
C0805
C0402
BC558
BC557
BC556
BC555
BC133
K24 VCC33 VCCSM10 AK26

C0402
K23 AJ26
*
VCC34 VCCSM11
internally
K22 VCC35 VCCSM12 AH26

pins shorted
K21 VCC36 VCCSM13 AG26

W20 AF26
Note: All VCCSM
VCC37 VCCSM14
0.1uF
BC155 BC154 BC150 BC148

2D5V_TVDAC_S0
U20 AE26
BC119
VCC38 VCCSM15
10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
R123
T20 AP25
*
*
*
*
VCC39 VCCSM16
K20 VCC40 VCCSM17 AN25
0.1uF C0402 0.1uF C0402 0.1uF C0402 0.1uF C0402 V19 AM25
*
0 R0603 +/-5%
10V, X5R, +/-10%10V, X5R, +/-10%10V, X5R, +/-10%10V, X5R, +/-10% VCC41 VCCSM18
U19 VCC42 VCCSM19 AL25
K19 VCC43 VCCSM20 AK25
10uF
R134
W18 AJ25
POWER
VCC44 VCCSM21
C0805
BC120
V18 VCC45 VCCSM22 AH25

T18 VCC46 VCCSM23 AG25
K18 VCC47 VCCSM24 AF25
K17 AE25
1D5V_S0
VCC48 VCCSM25
1D5V_HPLL_S0
1D5V_MPLL_S0
AE24
0 R0603 +/-5%
3
3
1D5V_DPLLB_S0
1D5V_DPLLA_S0
VCCSM26 BC131
AC2 VCCH_MPLL1 VCCSM27 AE23
10V, Y5V, +80%/-20%
AC1 AE22
*
VCCH_MPLL0 VCCSM28
B23 VCCA_DPLLA VCCSM29 AE21
C35 AE20 10uF C0805
2D5V_S0
VCCA_DPLLB VCCSM30 10V, Y5V, +80%/-20%

AA1 AE19
0 R0603 +/-5%
VCCA_HPLL VCCSM31
AA2 VCCA_MPLL VCCSM32 AE18
AE17 BC132
VCCSM33
F19 AE16
*
VCCA_CRTDAC0 VCCSM34
E19 VCCA_CRTDAC1 VCCSM35 AE15
10uF C0805
R135
R129
R122
G19 AE14
2D5V_S0
2D5V_S0
1D5V_S0
VSSA_CRTDAC VCCSM36 10V, Y5V, +80%/-20%

VCCSM37 AP13
VCCSM38 AN13
H20 VCC_SYNC VCCSM39 AM13
AL13
*
VCCSM40
K13 VTT0 VCCSM41 AK13
VDIMM
J13 AJ13
0.1uF
0.1uF
0.1uF
VTT1 VCCSM42
C0402
C0402
C0402
BC121
BC113
BC108
10uF
K12 VTT2 VCCSM43 AH13

C0805
1.8v_s3
BC554
W11 AG13
*
*
*
VTT3 VCCSM44
V11 VTT4 VCCSM45 AF13
U11 AE13
of Alviso. Route FB
0 R0603 +/-5%
0 R0603 +/-5%
0 R0603 +/-5%
VTT5 VCCSM46
within 3" of Alviso.

T11 VTT6 VCCSM47 AP12
2D5V_CRTDAC_S0
R11 AN12
*
*
*
*
Route caps within 250mil VTT7 VCCSM48

P11 AM12
Layout Notes: VSSA_CRTDAC
VTT8 VCCSM49
10V, Y5V, +80%/-20%
N11 VTT9 VCCSM50 AL12

10uF
10uF
M11 AK12
4.7uF
VTT10 VCCSM51
C0805
C0805
C0805
BC122
BC114
BC549
2D5V_ALVDS_S0
L11 AJ12
0.1uF
2D5V_TXLVDS_S0
VTT11 VCCSM52
C0402
BC147
K11 AH12
*
VTT12 VCCSM53
R144
W10 AG12
1D5V_DLVDS_S0
VTT13 VCCSM54
V10 VTT14 VCCSM55 AF12
U10 AE12
0.1uF
VTT15 VCCSM56
C0402
BC149
T10 VTT16 VCCSM57 AD11 *

10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
R10 AC11
0.1uF
VTT17 VCCSM58
C0402
BC134
internally
P10 VTT18 VCCSM59 AB11

pins shorted
N10 VTT19 VCCSM60 AB10

M10 AB9
Note: All VCCSM
VTT20 VCCSM61
2
2
K10 VTT21 VCCSM62 AP8 V1.8_DDR_CAP6

J10 AM1 V1.8_DDR_CAP4
connect to the gnd plane.
*
VTT22 VCCSM63 V1.8_DDR_CAP3

10
R146
Y9 AE1
*
0 R0603 +/-5%
VTT23 VCCSM64
W9 VTT24
U9 B28
0.1uF
+/-5%
VTT25 VCCTX_LVDS0
R0402
C0402
BC125
R9 A28
0.1uF
VTT26 VCCTX_LVDS1
Route VSSA_CRTDAC gnd from GMCH to
C0402
BC128
decoupling cap ground lead and then
P9 VTT27 VCCTX_LVDS2 A27

N9 VTT28
2D5V_S0
M9 VTT29 VCCA_SM0 AF20

L9 VTT30 VCCA_SM1 AP19
2D5V_TXLVDS_S0
J9 VTT31 VCCA_SM2 AF19

N8 VTT32 VCCA_SM3 AF18
M8 VTT33
N7 VTT34 VCC3G0 AE37
M7 VTT35 VCC3G1 W37
N6 VTT36 VCC3G2 U37
C0603
BC143
0.47uF
16V, Y5V, +80%/-20%
M6 R37
*
VCCP_GMCH_CAP1 VTT37 VCC3G3

A6 N37
*
*
VTT38 VCC3G4
NB_CORE_S0_L
1D5V_PCIE_S0
N5 VTT39 VCC3G5 L37

Title
10uF
Date:
M5 J37
*
VTT40 VCC3G6
C0805
BC117
N4
0.1uF
VTT41
C0402
BC111
M4 Y29
1D5V_DDRDLL_S0
VTT42 VCCA_3GPLL0
C0603
BC144
0.47uF
N3 Y28
*
4.7uF
0.1uF
VTT43 VCCA_3GPLL1
C0805
C0402
BC151
BC129
16V, Y5V, +80%/-20%

1D05V_S0
M3 Y27 2 1
*
VTT44 VCCA_3GPLL2
N2
*
Document Number
VTT45
10uF
M2 F37
*
VTT46 VCCA_3GBG
C0805
TC2
BC118
0.22uF VCCP_GMCH_CAP2 B2 G37

D2
220uF
VTT47 VSSA_3GBG
ctbh20
VCCP_GMCH_CAP3
SSM5818
V1
2.2uF
VTT48
C0805
BC152
BC145
10uF
N1
1
*
VTT49
C0805
BC130
1D5V_3GPLL_S0
M1
2.5V, +/-20%
VCCP_GMCH_CAP4 VTT50
G1
* *
*
VTT51
TC3
Monday, March 14, 2005

10uF
R125
C0805
NB_CORE_S0
0.22uF BC146
16V, Y5V, +80%/-20%
0.1uF
C0402
BC135
2D5V_3GBG_S0
R141
R133
U3E
10V, Y5V, +80%/-20%
1
1
R140
R0805
GMCH(4 of 5)
Note:3GIO: 1A
10V, Y5V, +80%/-20%
ALVISO-GM
0.1uF
0 +/-5%
C0402
BC153
Sheet
71.0GMCH.08U
S09 MAINBOARD
1D5V_S0
9
1D5V_S0
Note:VCCASM: 0.76A
10V, X5R, +/-10%

2D5V_S0
1D5V_S0
0 R0603 +/-5%
0 R0805 +/-5%
of
0 R0805 +/-5%
45
Rev
A
TECHNOLOGY COPR.
A
B
C
D
A
B
C
D
U3F
ALVISO-GM
B36 VSSALVDS
AL24
71.0GMCH.08U
VSS267
U3H
VSS266 AN24
Y1 VSS271 VSS265 A26
ALVISO-GM
D2 VSS270 VSS264 E26
G2 G26
71.0GMCH.08U
VSS269 VSS263
VCCSM_NCTF31 AB12 J2 VSS268 VSS262 J26
VCCSM_NCTF30 AC12 L2 VSS260 VSS261 B27
VDIMM
VCCSM_NCTF29 AD12 P2 VSS259 VSS129 E27
AB13 T2 G27
5
5
VCCSM_NCTF28 VSS258 VSS128

VCCSM_NCTF27 AC13 V2 VSS257 VSS127 W27
AD13 AD2 AA27
*
Dummy
VCCSM_NCTF25 AC14 AE2 VSS255 VSS125 AB27
BC156
AD14 10uF AH2 AF27
VCCSM_NCTF23 AC15 AL2 VSS253 VSS123 AG27
AD15 10V, Y5V, +80%/-20% AN2 AJ27
1.8v_s3
VCCSM_NCTF21 AC16 A3 VSS251 VSS121 AL27
AD16 C3 AN27
*
Dummy
VCCSM_NCTF19 AC17 AA3 VSS249 VSS119 E28
BC157
AD17 10uF AB3 W28
VCCSM_NCTF17 AC18 AC3 VSS247 VSS117 AA28
AD18 10V, Y5V, +80%/-20% AJ3 AB28
VCCSM_NCTF15 AC19 C4 VSS245 VSS115 AC28
1D05V_S0
AD19 H4 A29
*
Dummy
VCCSM_NCTF13 AC20 L4 VSS243 VSS113 D29
BC158
AD20 10uF P4 E29
L12 VTT_NCTF17 VCCSM_NCTF11 AC21 U4 VSS241 VSS111 F29
M12 AD21 10V, Y5V, +80%/-20% Y4 G29
VTT_NCTF16 VCCSM_NCTF10 VSS240 VSS110

N12 VTT_NCTF15 VCCSM_NCTF9 AC22 AF4 VSS239 VSS109 H29
P12 AD22 AN4 L29
*
Dummy
R12 VTT_NCTF13 VCCSM_NCTF7 AC23 E5 VSS237 VSS107 P29
BC159
T12 AD23 10uF W5 U29
U12 VTT_NCTF11 VCCSM_NCTF5 AC24 AL5 VSS235 VSS105 V29
V12 AD24 10V, Y5V, +80%/-20% AP5 W29
W12 VTT_NCTF9 VCCSM_NCTF3 AC25 B6 VSS233 VSS103 AA29
L13 AD25 J6 AD29
*
Dummy
M13 VTT_NCTF7 VCCSM_NCTF1 AC26 L6 VSS231 VSS101 AG29
BC160
N13 AD26 10uF P6 AJ29
P13 VTT_NCTF5 T6 VSS229 VSS99 AM29
R13 L17 10V, Y5V, +80%/-20% AA6 C30
VTT_NCTF4 VCC_NCTF78 VSS228 VSS98
T13 VTT_NCTF3 VCC_NCTF77 M17 AC6 VSS227 VSS97 Y30
4
4
U13 N17 AE6 AA30

VTT_NCTF2 VCC_NCTF76 * VSS226 VSS96
Dummy
V13 VTT_NCTF1 VCC_NCTF75 P17 AJ6 VSS225 VSS95 AB30
BC161
W13 T17 10uF G7 AC30

VTT_NCTF0 VCC_NCTF74 VSS224 VSS94
VCC_NCTF73 U17 V7 VSS223 VSS93 AE30
V17 10V, Y5V, +80%/-20% AA7 AP30
VCC_NCTF72 VSS222 VSS92
VCC_NCTF71 W17 AG7 VSS221 VSS91 D31
L18 AK7 E31
*
VCC_NCTF70 VSS220 VSS90

VCC_NTTF69 M18 AN7 VSS219 VSS89 F31
0.1uF C0402
Dummy
Y12 VSS_NCTF68 VCC_NCTF68 N18 C8 VSS218 VSS88 G31
AA12 VSS_NCTF67 VCC_NCTF67 P18 E8 VSS217 VSS87 H31
BC162
Y13 VSS_NCTF66 VCC_NCTF66 R18 L8 VSS216 VSS86 J31

AA13 VSS_NCTF65 VCC_NCTF65 Y18 P8 VSS215 VSS85 K31
L14 L19 Y8 L31
*
VSS_NCTF64 VCC_NCTF64 VSS214 VSS84

M14 VSS_NCTF63 VCC_NCTF63 M19 AL8 VSS213 VSS83 M31
0.1uF C0402
Dummy
N14 VSS_NCTF62 VCC_NCTF62 N19 A9 VSS212 VSS82 N31

P14 VSS_NCTF61 VCC_NCTF61 P19 H9 VSS211 VSS81 P31
BC163
R14 VSS_NCTF60 VCC_NCTF60 R19 K9 VSS210 VSS80 R31

T14 Y19 T9 T31
Place these Hi-Freq decoupling caps near GMCH

U14 L20 V9 U31
*

V14 VSS_NCTF57 VCC_NCTF57 M20 AA9 VSS207 VSS77 V31
0.1uF C0402
Dummy
W14 VSS_NCTF56 VCC_NCTF56 N20 AC9 VSS206 VSS76 W31

Y14 VSS_NCTF55 VCC_NCTF55 P20 AE9 VSS205 VSS75 AD31
BC164
AA14 VSS_NCTF54 VCC_NCTF54 R20 AH9 VSS204 VSS74 AG31

AB14
NCTF
VSS_NCTF53 VCC_NCTF53 Y20 AN9 VSS203 VSS73 AL31
L15 L21 D10 A32
*
VSS

M15 VSS_NCTF51 VCC_NCTF51 M21 L10 VSS201 VSS71 C32
0.1uF C0402
Dummy
N15 VSS_NCTF50 VCC_NCTF50 N21 Y10 VSS200 VSS70 Y32

P15 VSS_NCTF49 VCC_NCTF49 P21 AA10 VSS199 VSS69 AA32
BC165
R15 VSS_NCTF48 VCC_NCTF48 T21 F11 VSS198 VSS68 AB32

T15 VSS_NCTF47 VCC_NCTF47 U21 H11 VSS197 VSS67 AC32
U15 VSS_NCTF46 VCC_NCTF46 V21 Y11 VSS196 VSS66 AD32
V15 W21 AA11 AJ32
3
3

W15 VSS_NCTF44 VCC_NCTF44 L22 AF11 VSS194 VSS64 AN32
Y15 VSS_NCTF43 VCC_NCTF43 M22 AG11 VSS193 VSS63 D33
AA15 VSS_NCTF42 VCC_NCTF42 N22 AJ11 VSS192 VSS62 E33
AB15 VSS_NCTF41 VCC_NCTF41 P22 AL11 VSS191 VSS61 F33
L16 VSS_NCTF40 VCC_NCTF40 R22 AN11 VSS190 VSS60 G33
M16 VSS_NCTF39 VCC_NCTF39 T22 B12 VSS189 VSS59 H33
N16 VSS_NCTF38 VCC_NCTF38 U22 D12 VSS188 VSS58 J33
P16 VSS_NCTF37 VCC_NCTF37 V22 J12 VSS187 VSS57 K33
R16 VSS_NCTF36 VCC_NCTF36 W22 A14 VSS186 VSS56 L33
T16 VSS_NCTF35 VCC_NCTF35 L23 B14 VSS185 VSS55 M33
U16 VSS_NCTF34 VCC_NCTF34 M23 F14 VSS184 VSS54 N33
V16 VSS_NCTF33 VCC_NCTF33 N23 J14 VSS183 VSS53 P33
W16 VSS_NCTF32 VCC_NCTF32 P23 K14 VSS182 VSS52 R33
Y16 VSS_NCTF31 VCC_NCTF31 R23 AG14 VSS181 VSS51 T33
AA16 VSS_NCTF30 VCC_NCTF30 T23 AJ14 VSS180 VSS50 U33
AB16 VSS_NCTF29 VCC_NCTF29 U23 AL14 VSS179 VSS49 V33
R17 VSS_NCTF28 VCC_NCTF28 V23 AN14 VSS178 VSS48 W33
Y17 VSS_NCTF27 VCC_NCTF27 W23 C15 VSS177 VSS47 AD33
AA17 VSS_NCTF26 VCC_NCTF26 L24 K15 VSS176 VSS46 AF33
AB17 VSS_NCTF25 VCC_NCTF25 M24 A16 VSS175 VSS45 AL33
AA18 VSS_NCTF24 VCC_NCTF24 N24 D16 VSS174 VSS44 C34
AB18 VSS_NCTF23 VCC_NCTF23 P24 H16 VSS173 VSS43 AA34
AA19 VSS_NCTF22 VCC_NCTF22 R24 K16 VSS172 VSS42 AB34
AB19 VSS_NCTF21 VCC_NCTF21 T24 AL16 VSS171 VSS41 AC34
AA20 VSS_NCTF20 VCC_NCTF20 U24 C17 VSS170 VSS40 AD34
NB_CORE_S0
AB20 VSS_NCTF19 VCC_NCTF19 V24 G17 VSS169 VSS39 AH34

R1206
R1206
R1206
R1206
R631
R630
R148
R149
R21 VSS_NCTF18 VCC_NCTF18 W24 AF17 VSS168 VSS38 AN34

@GM Y21 L25 AJ17 B35
@GM

@GML
@GML
AA21 VSS_NCTF16 VCC_NCTF16 M25 AN17 VSS166 VSS36 D35

AB21 N25 A18 E35
0
0
0
0

Y22 P25 B18 F35
+/-5%
+/-5%
+/-5%
+/-5%
2
2
AA22 VSS_NCTF13 VCC_NCTF13 R25 U18 VSS163 VSS33 G35

AB22 VSS_NCTF12 VCC_NCTF12 T25 AL18 VSS162 VSS32 H35
Y23 VSS_NCTF11 VCC_NCTF11 U25 C19 VSS161 VSS31 J35
AA23 VSS_NCTF10 VCC_NCTF10 V25 H19 VSS160 VSS30 K35
1D05V_S0
AB23 VSS_NCTF9 VCC_NCTF9 W25 J19 VSS159 VSS29 L35

Y24 VSS_NCTF8 VCC_NCTF8 L26 T19 VSS158 VSS28 M35
AA24 VSS_NCTF7 VCC_NCTF7 M26 W19 VSS157 VSS27 N35
AB24 VSS_NCTF6 VCC_NCTF6 N26 AG19 VSS156 VSS26 P35
1D5V_S0
Y25 VSS_NCTF5 VCC_NCTF5 P26 AN19 VSS155 VSS25 R35

AA25 VSS_NCTF4 VCC_NCTF4 R26 A20 VSS154 VSS24 T35
AB25 VSS_NCTF3 VCC_NCTF3 T26 D20 VSS153 VSS23 U35
Y26 VSS_NCTF2 VCC_NCTF2 U26 E20 VSS152 VSS22 V35
AA26 VSS_NCTF1 VCC_NCTF1 V26 F20 VSS151 VSS21 W35
Title
Date:
AB26 VSS_NCTF0 VCC_NCTF0 W26 G20 VSS150 VSS20 Y35
V20 VSS149 VSS19 AE35
AK20 VSS148 VSS18 C36
C21 VSS147 VSS17 AA36
NB_CORE_S0
F21 VSS146 VSS16 AB36

AF21 AC36
Document Number
VSS145 VSS15
AN21 VSS144 VSS14 AD36
A22 VSS143 VSS13 AE36
D22 VSS142 VSS12 AF36
E22 VSS141 VSS11 AJ36
J22 VSS140 VSS10 AL36
AH22 VSS139 VSS9 AN36
Monday, March 14, 2005
AL22 VSS138 VSS8 E37

H23 VSS137 VSS7 H37
AF23 K37
GM: NB_CORE=1.5V
VSS136 VSS6
B24 VSS135 VSS5 M37
GML: NB_CORE=1.05V
D24 VSS134 VSS4 P37

F24 VSS133 VSS3 T37
J24 V37
1
1
VSS132 VSS2
GMCH(5 of 5)
AG24 VSS131 VSS1 Y37

AJ24 AG37
Sheet
VSS130 VSS0
S09 MAINBOARD
10
of
45
Rev
A
TECHNOLOGY COPR.
A
B
C
D
5 4 3 2 1
CN1
CN2
8 M_B_A[13:0] M_B_DQ[63:0] 8
M_B_A0 102 5 M_B_DQ0
M_B_A1 A0 DQ0 M_B_DQ1
8 M_A_A[13:0] M_A_DQS[7:0] 8 101 A1 DQ1 7
M_A_A0 102 13 M_A_DQS0 M_B_A2 100 17 M_B_DQ2
M_A_A1 A0 DQS0 M_A_DQS1 M_B_A3 A2 DQ2 M_B_DQ3
101 A1 DQS1 31 99 A3 DQ3 19
99 A3 DQS3 70 97 A5 DQ5 6
M_A_A4 98 131 M_A_DQS4 M_B_A6 94 14 M_B_DQ6 VTT_MEM
97 A5 DQS5 148 92 A7 DQ7 16
M_A_A7 A6 DQS6 M_A_DQS7 M_B_A9 A8 DQ8 M_B_DQ9 10V, X7R, +/-10%
92 A7 DQS7 188 M_A_DQSJ[7:0] 8 91 A9 DQ9 25
M_A_A8 93 11 M_A_DQSJ0 M_B_A10 105 35 M_B_DQ10 RN67
A8 DQS0# A10/AP DQ10
*
**
M_A_A9 91 29 M_A_DQSJ1 M_B_A11 90 37 M_B_DQ11 0.1uF BC559 1 2 M_CKE2_RJ
M_A_A10 A9 DQS1# M_A_DQSJ2 M_B_A12 A11 DQ11 M_B_DQ12 C0402 M_B_BSJ2
105 A10/AP DQS2# 49 89 A12 DQ12 20 3 4
M_A_A11 90 68 M_A_DQSJ3 M_B_A13 116 22 M_B_DQ13 0.1uF BC560 5 6 M_B_A12
D
M_A_A12 A11 DQS3# M_A_DQSJ4 A13 DQ13 M_B_DQ14 C0402 M_B_A9 D
89 A12 DQS4# 129 86 A14 DQ14 36 7 8
M_A_A13 116 146 M_A_DQSJ5 84 38 M_B_DQ15
A13 DQS5# M_A_DQSJ6 A15 DQ15 M_B_DQ16 RN68 56 +/-5% 8P4R0402
86 A14 DQS6# 167 8 M_B_BSJ2 85 A16_BA2 DQ16 43
*
**
84 186 M_A_DQSJ7 45 M_B_DQ17 0.1uF BC561 1 2 M_B_A8
A15 DQS7# DQ17 M_B_DQ18 C0402 M_B_A5
8 M_A_BSJ2 85 A16_BA2 8 M_B_BSJ0 107 BA0 DQ18 55 3 4
106 57 M_B_DQ19 0.1uF BC562 5 6 M_B_A3
M_A_DM[7:0] 8 8 M_B_BSJ1 BA1 DQ19
10 M_A_DM0 110 44 M_B_DQ20 C0402 7 8 M_B_A1
DM0 7 M_CS2_RJ S0# DQ20
107 26 M_A_DM1 115 46 M_B_DQ21
8 M_A_BSJ0 BA0 DM1 7 M_CS3_RJ S1# DQ21
106 52 M_A_DM2 30 56 M_B_DQ22 RN69 56 +/-5% 8P4R0402
8 M_A_BSJ1 BA1 DM2 7 CLK_DDR3 CK0 DQ22
*
**
67 M_A_DM3 32 58 M_B_DQ23 0.1uF BC563 1 2 M_B_A10
8 M_A_DQ[63:0] DM3 7 CLK_DDR3J CK0# DQ23
M_A_DQ0 5 130 M_A_DM4 164 61 M_B_DQ24 C0402 3 4 M_B_BSJ0
DQ0 DM4 7 CLK_DDR4 CK1 DQ24
M_A_DQ1 7 147 M_A_DM5 166 63 M_B_DQ25 0.1uF BC564 5 6 M_B_WEJ
DQ1 DM5 7 CLK_DDR4J CK1# DQ25
M_A_DQ2 17 170 M_A_DM6 79 73 M_B_DQ26 C0402 7 8 M_B_CASJ
DQ2 DM6 7 M_CKE2_RJ CKE0 DQ26
M_A_DQ3 19 185 M_A_DM7 80 75 M_B_DQ27
DQ3 DM7 7 M_CKE3_RJ CKE1 DQ27
M_A_DQ4 4 113 62 M_B_DQ28 RN70 56 +/-5% 8P4R0402
DQ4 8 M_B_CASJ CAS# DQ28
HIGH 9.0mm DDRII SDRAM SO-DIMM (200P)

*
**
M_A_DQ5 6 30 108 64 M_B_DQ29 0.1uF BC565 1 2 M_B_A6
DQ5 CK0 CLK_DDR0 7 8 M_B_RASJ RAS# DQ29
M_A_DQ6 14 32 R0402 109 74 M_B_DQ30 C0402 3 4 M_B_A7
DQ6 CK0# CLK_DDR0J 7 8 M_B_WEJ WE# DQ30
M_A_DQ7 16 164 R520 10K +/-1% SA0_DIM2 198 76 M_B_DQ31 0.1uF BC566 5 6 M_B_A11
DQ7 CK1 CLK_DDR1 7 SA0 DQ31
M_A_DQ8 23 166 R522 10K +/-1% SA1_DIM2 200 123 M_B_DQ32 C0402 7 8 M_CKE3_RJ
DQ8 CK1# CLK_DDR1J 7 3D3V_S0 SA1 DQ32
M_A_DQ9 25 R0402 197 125 M_B_DQ33
DQ9 3,17 SMBC_ICH SCL DQ33
M_A_DQ10 35 198 SA0_DIM1 +/-1% 10K R521 R0402 195 135 M_B_DQ34 RN71 56 +/-5% 8P4R0402
DQ10 SA0 3,17 B_SMBD_ICH SDA DQ34
*
**
M_A_DQ11 37 200 SA1_DIM1 +/-1% 10K R523 114 137 M_B_DQ35 0.1uF BC567 1 2 M_A_WEJ
DQ11 SA1 7 M_ODT2 ODT0 DQ35
M_A_DQ12 20 R0402 119 124 M_B_DQ36 C0402 3 4 M_A_BSJ0
DQ12 7 M_ODT3 ODT1 DQ36
M_A_DQ13 22 199 3D3V_S0 126 M_B_DQ37 0.1uF BC568 5 6 M_A_CASJ
DQ13 VDD_SPD 8 M_B_DM[7:0] DQ37
10V, Y5V, +80%/-20%

M_A_DQ14 36 BC582 M_B_DM0 10 134 M_B_DQ38 C0402 7 8 M_ODT1
DQ14 DM0 DQ38
10V, X7R, +/-10%

M_A_DQ15
M_A_DQ16
38
43
DQ15
DQ16 VDD 81
BC583
2.2uF * 0.1uF
* M_B_DM1
M_B_DM2
26
52
DM1
DM2
DQ39
DQ40
136
141
M_B_DQ39
M_B_DQ40 RN72 56 +/-5% 8P4R0402
*
**
M_A_DQ17 45 82 C0603 C0402 M_B_DM3 67 143 M_B_DQ41 0.1uF BC569 1 2 M_A_A13
M_A_DQ18 DQ17 VDD M_B_DM4 DM3 DQ41 M_B_DQ42 C0402 M_ODT0
55 DQ18 VDD 87 130 DM4 DQ42 151 3 4
M_A_DQ19 57 88 M_B_DM5 147 153 M_B_DQ43 0.1uF BC570 5 6 M_CS0_RJ
DQ19 VDD DM5 DQ43
LOW 4.0mm DDRII SDRAM SO-DIMM (200P)
M_A_DQ20 44 95 M_B_DM6 170 140 M_B_DQ44 C0402 7 8 M_A_RASJ

M_A_DQ21 DQ20 VDD M_B_DM7 DM6 DQ44 M_B_DQ45
46 DQ21 VDD 96 8 M_B_DQS[7:0] 185 DM7 DQ45 142
M_A_DQ22 56 103 M_B_DQS0 13 152 M_B_DQ46 56 +/-5% 8P4R0402
M_A_DQ23 DQ22 VDD M_B_DQS1 DQS0 DQ46 M_B_DQ47
58 DQ23 VDD 104 VDIMM 31 DQS1 DQ47 154
M_A_DQ24 61 111 M_B_DQS2 51 157 M_B_DQ48
63 DQ25 VDD 112 70 DQS3 DQ49 159
M_A_DQ26 73 117 M_B_DQS4 131 173 M_B_DQ50
C 75 DQ27 VDD 118 148 DQS5 DQ51 175 C
M_A_DQ28 62 M_B_DQS6 169 158 M_B_DQ52 10V, X7R, +/-10% RN73
DQ28 DQS6 DQ52
*
**
M_A_DQ29 64 2 M_B_DQS7 188 160 M_B_DQ53 0.1uF BC571 1 2 M_B_BSJ1
DQ29 VSS 8 M_B_DQSJ[7:0] DQS7 DQ53
M_A_DQ30 74 3 M_B_DQSJ0 11 174 M_B_DQ54 C0402 3 4 M_B_A0
M_A_DQ31 DQ30 VSS M_B_DQSJ1 DQS#0 DQ54 M_B_DQ55 0.1uF BC572 M_B_A2
76 DQ31 VSS 8 29 DQS#1 DQ55 176 5 6
M_A_DQ32 123 9 M_B_DQSJ2 49 179 M_B_DQ56 C0402 7 8 M_B_A4
M_A_DQ33 DQ32 VSS M_B_DQSJ3 DQS#2 DQ56 M_B_DQ57
125 DQ33 VSS 12 68 DQS#3 DQ57 181
M_A_DQ34 135 15 M_B_DQSJ4 129 189 M_B_DQ58 RN74 56 +/-5% 8P4R0402
DQ34 VSS DQS#4 DQ58
*
**
M_A_DQ35 137 18 M_B_DQSJ5 146 191 M_B_DQ59 0.1uF BC573 1 2 M_ODT2
M_A_DQ36 DQ35 VSS M_B_DQSJ6 DQS#5 DQ59 M_B_DQ60 C0402 M_B_A13
124 DQ36 VSS 21 167 DQS#6 DQ60 180 3 4
M_A_DQ37 126 24 M_B_DQSJ7 186 182 M_B_DQ61 0.1uF BC574 5 6 M_CS2_RJ
M_A_DQ38 DQ37 VSS DQS#7 DQ61 M_B_DQ62 C0402 M_B_RASJ
134 27 192 7 8
M_A_DQ39
M_A_DQ40
136
141
DQ38
DQ39
DQ40
VSS
VSS
VSS
28
33 www.hocnghetructuyen.vn VDIMM 112
111
VDD1
VDD2
DQ62
DQ63 194 M_B_DQ63
RN75 56 +/-5% 8P4R0402
*
**
M_A_DQ41 143 34 117 41 0.1uF BC575 1 2 M_A_A6
M_A_DQ42 DQ41 VSS VDD3 VSS18
151 DQ42 VSS 39 96 VDD4 VSS19 53 C0402 3 4 M_A_A7
M_A_DQ43 153 40 95 42 0.1uF BC576 5 6 M_A_A11
M_A_DQ44 DQ43 VSS VDD5 VSS20
140 DQ44 VSS 41 118 VDD6 VSS21 54 C0402 7 8 M_CKE1_RJ
M_A_DQ45 142 42 81 59
M_A_DQ46 DQ45 VSS VDD7 VSS22 56 +/-5% 8P4R0402
152 DQ46 VSS 47 82 VDD8 VSS23 65
*
M_A_DQ47 154 48 87 60 0.1uF BC577 R524 56 M_CS3_RJ
M_A_DQ48 DQ47 VSS VDD9 VSS24 C0402 R0402 +/-5%
157 DQ48 VSS 53 103 VDD10 VSS25 66
M_A_DQ49 159 54 3D3V_S0 88 127 R525 56 M_ODT3
M_A_DQ50 DQ49 VSS VDD11 VSS26 R0402 +/-5%
173 DQ50 VSS 59 104 VDD12 VSS27 139
M_A_DQ51 RN76
10V, X7R, +/-10%

175 DQ51 VSS 60 VSS28 128
*
**
M_A_DQ52 158 65 199 145 0.1uF BC578 1 2 M_A_BSJ2
M_A_DQ53 DQ52 VSS VDDSPD VSS29
160 DQ53 VSS 66 BC580 BC581 83 NC1 VSS30 165 C0402 3 4 M_A_A12
M_A_DQ54
M_A_DQ55
174
176
DQ54
DQ55
VSS
VSS
71
72
* 0.1uF
* 2.2uF 120
50
NC2
NC3
VSS31
VSS32
171
172
0.1uF
C0402
BC579 5
7
6 M_A_A9
8 M_A_A8
M_A_DQ56 179 77 C0402 C0603 69 177
M_A_DQ57 DQ56 VSS NC4 VSS33 RN77 56 +/-5% 8P4R0402
181 DQ57 VSS 78 163 NCTEST VSS34 187
*
**
M_A_DQ58 189 121 1 178 0.1uF BC584 1 2 M_A_BSJ1
DQ58 VSS DDR_VREF VREF VSS35
M_A_DQ59 191 122 190 C0402 3 4 M_A_A0
M_A_DQ60 DQ59 VSS BC586 BC587 VSS36 0.1uF BC585 M_A_A2
10V, X7R, +/-10%
180 127 201 9 5 6

16V, Y5V, +80%/-20%
M_A_DQ61 DQ60 VSS GND0 VSS37

M_A_DQ62
182
192
DQ61
DQ62
VSS
VSS
128
132
* 0.1uF
* 2.2uF 202
47
GND1
VSS1
VSS38
VSS39
21
33
C0402 7 8 M_A_A4
M_A_DQ63 194 133 C0402 C0805 133 155 RN78 56 +/-5% 8P4R0402
DQ63 VSS VSS2 VSS40
*
**
138 183 34 0.1uF BC590 1 2 M_A_A5
B VSS VSS3 VSS41 C0402 M_A_A3 B
50 NC#50 VSS 139 77 VSS4 VSS42 132 3 4
69 144 12 144 0.1uF BC591 5 6 M_A_A1
NC#69 VSS VSS5 VSS43 C0402 M_A_A10
83 NC#83 VSS 145 48 VSS6 VSS44 156 7 8
120 NC#120 VSS 149 184 VSS7 VSS45 168
163 150 78 2 56 +/-5% 8P4R0402
NC#163/TEST VSS VSS8 VSS46
*
155 71 3 0.1uF BC592 R526 56 M_CKE0_RJ
VSS VSS9 VSS47 C0402 R0402 +/-5%
7 M_CS0_RJ 110 CS0# VSS 156 72 VSS10 VSS48 15
115 161 121 27 R527 56 M_CS1_RJ
7 M_CS1_RJ CS1# VSS VSS11 VSS49
79 162 122 39 R0402 +/-5%
7 M_CKE0_RJ CKE0 VSS VSS12 VSS50
7 M_CKE1_RJ 80 CKE1 VSS 165 196 VSS13 VSS51 149
8 M_A_RASJ 108 RAS# VSS 168 193 VSS14 VSS52 161
8 M_A_CASJ 113 CAS# VSS 171 8 VSS15 VSS53 28
8 M_A_WEJ 109 WE# VSS 172 24 VSS17 VSS54 40
VSS 177 18 VSS16 VSS55 138
3,17 SMBC_ICH 197 SCL VSS 178 162 VSS57 VSS56 150
3,17 B_SMBD_ICH 195 SDA VSS 183
DDR_VREF 184 DDR_SO-DIMM
VSS
7 M_ODT0 114 ODT0 VSS 187
7 M_ODT1 119 ODT1 VSS 190
VSS 193
1 VREF VSS 196
10V, X7R, +/-10%
10V, Y5V, +80%/-20%
201 GND GND 202

* BC588
0.1uF * BC589
2.2uF
C0402 C0603 DDR_SO-DIMM
A A
VDIMM
VDIMM
10V, X7R, +/-10%

16V, Y5V, +80%/-20%
VDIMM
16V, Y5V, +80%/-20%
10V, X7R, +/-10%
BC593 BC594 BC595 BC596 BC597 BC598 BC599 BC600 BC601 BC602 BC603 BC604
BC605 BC606 BC607 BC608 BC609 BC610 BC611 BC612 BC613 BC614 BC615 BC616 TC15
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
1
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF
* 2.2uF
* 0.1uF * 220uF
4V, +/-20% C0805 C0402 C0805 C0402 C0805 C0402 C0805 C0402 C0805 C0402 C0805 C0402
C0805 C0402 C0805 C0402 C0805 C0402 C0805 C0402 C0805 C0402 C0805 C0402 ctdh19 TECHNOLOGY COPR.
2
Title
DDR2_SOCKET
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
5V_S0 5V_CRT_S0
D4
CRT I/F & CONNECTOR *

F1
F1210_1.1A
1
CH501H-40
2
*
BC248
10nF
25V, X7R, +/-10%
Ferrite bead impedance: 47ohm@100MHz C0402
D D
L6 VGA_CN1
1 2 CRT_R
7 GMCH_RED
FB L0603 47 Ohm R172 R173 17
L7 3.3K 3.3K
+/-5% +/-5%
1 2 CRT_G R0402 R0402
7 GMCH_GREEN
5
FB L0603 47 Ohm CLK_DDC1_5 15
L8 10
4
1 2 CRT_B JVGA_VS 14
7 GMCH_BLUE
9
R178
150
R179
150
R180
150 * C9 * C10 * C11
FB L0603 47 Ohm
* C12 * C13 * C14
CRT_B
JVGA_HS
3
13
+/-5% R0402 +/-5% 3.3pF 3.3pF 3.3pF 3.3pF 3.3pF 3.3pF 8
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF

R0402 +/-5% R0402 C0402 C0402 C0402 C0402 C0402 C0402 CRT_G 2
Dummy Dummy Dummy Dummy Dummy Dummy DAT_DDC1_5 12
7
CRT_R 1
Layout Note: 11
Place these resistors
50V, NPO, +/-5%
50V, NPO, +/-5%

6
close to the CRT-out
connector
Layout Note:
2D5V_S0
C15
100pF * * C16
100pF * BC249
33pF * BC250
33pF 16
C0402 C0402 C0603 C0603
50V, NPO, +/-5% 50V, NPO, +/-5%
* Must be a ground return path between this ground and the ground on VGA15P
2
C
the VGA connector. D5
C
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CRT_R 3 BAV99
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN. DDC_CLK & DATA level shift
1
2D5V_S0 2D5V_S0
2
Hsync & Vsync level shift 5V_S0 D6
CRT_G BAV99
16V, Y5V, +80%/-20%
BC251 R181 0 R0402 JVGA_HS

* 0.1uF +/-5%
1
R183 0 R0402 JVGA_VS R184
C0402 +/-5% 2.2K
+/-5%
2
R185 R186 R0402
D7 2.2K 2.2K
5
1
U38 CRT_B 3 BAV99 +/-5% +/-5%
G
R0402 R0402 Q1
2 4 HSYNC_5
7 GMCH_HSYNC
S D DAT_DDC1_5
7 B_GMCH_DDCDATA
1
74HCT1G125
3
5
1
U39 2N7002EPT
G
2 4 VSYNC_5 Q2
7 GMCH_VSYNC
7 GMCH_DDCCLK S D CLK_DDC1_5
74HCT1G125
3
B B
2N7002EPT
5V @ ext. CRT side
A A
TECHNOLOGY COPR.
Title
Document Number
CRT Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
LCDVDD_S0
3D3V_S0
LCD / INVERTER
CN17
3D3V_S5
WLANONLEDJ
U5
1 TO ALARM BOARD
5
LCDVDD_S0 BC283 BC284 BC285 R20
2
WLANONLED
1 802.11_LINK 29 3 * 10uF
* 0.1uF
* 0.1uF
ALARM_J1
10K
+/-5%
10
2 4 2 802.11_ACT 29 4 3D3V_S0
1 TP19 C0805 C0402 C0402 R0402
Q3 NC7SZ32 5 ANTI_THEFTR_LEDJ
LDDC_CLK 7 8
3
6
25V, Y5V, +80%/-20%

DTC144EUA R204 R205 LDDC_DATA 7 BC370 7 ANTI_THEFT_ARMJ 30
1
7
100K
+/-5%
100K
+/-5% 8 GMCH_TXAOUT0- 7
GMCH_TXAOUT0+ 7
* 0.1uF 6
5
3D3V_S5
3D3V_S0 BC529 10nF
*
R0402 R0402 9 C0603 C0402 Dummy
10 4
D D
11 GMCH_TXAOUT1- 7 3 B_KBC_SCL1 18,30
12 GMCH_TXAOUT1+ 7 2 B_KBC_DAT1 18,30
13 1
14 GMCH_TXAOUT2- 7
GMCH_TXAOUT2+ 7 WTB CONN_8P BC527 BC528
9
15
16
17 GMCH_TXACLK- 7
* 10nF
* 10nF
GMCH_TXACLK+ 7 C0402 C0402

18 Dummy Dummy
19 25V, X7R, +/-10%
20 FB L0805 300 Ohm 25V, X7R, +/-10%
21 INVT_PWR
22 2 1 FB9 DCBATOUT
23 BC266 BC265 BC264
24
LED 31
32
PAD1
25
26
BRIGHTNESS_PWM_1
EC_BLON
0.1uF
C0603
** 1nF
C0402
* 10uF
25V, Y5V, +80%/-20%
C1210
PAD2 27 Dummy
33 PAD3 28
34 PAD4 29
30
3D3V_S5 3D3V_S0 3D3V_S0 3D3V_S5 3D3V_S0 3D3V_S0
LVDS-CON30-LF
PWM from KBC
R208 0
BRIGHTNESS_PWM 30
R0402 +/-5%
R206 0
LBKLT_CRTL 7
R0402 +/-5%
Dummy
R213 R212 R214 R215 R216 R217 PWM from Alviso
16V, Y5V, +80%/-20%

R223 330 R211 330 330 330 330 330 BC269
330
+/-5%
330
+/-5%
+/-5%
R0603
+/-5%
R0603
+/-5%
R0603
+/-5%
R0603
+/-5%
R0603 * 0.1uF
C0402
C R0603 +/-5% R0603 C
R0603
1
1
Orange
BLUE
LED_Blue 2
LED_Blue 2
LED_Blue 2
LED_Blue 2
LED_Blue 2
LED_Blue 2
LED_Blue 2
MEDIA_LED1
NUM_LED1
CAP_LED1
PWR_LED1
PWR_LED2
PWR_LED3
WLAN_LED1
LED_Blue Yellow Orange2
Pull High IN EC page

CHG_LED1
30 EC_BLON
MEDIA_LEDJ
19 MEDIA_LEDJ CVR1
30 NUMJ
30 CAPSJ 4 NC 2
BRIGHTNESS_PWM_1 3 NC 1 COVER_SWJ COVERUP COVERUP 30
PWR_LEDRJ C18
30 CHG_LED2J
WLANONLEDJ
MEDIA_LEDJ
30 CHG_LEDJ
30 PWR_LED
PWR_LED Header_1X2 * C17
1nF
R218
100 * 0.22uF
16V, Y5V, +80%/-20%
CHG_LEDJ WLANONLEDJ 50V, X7R, +/-10% R0402 C0603
CHG_LED2J C0402 +/-5%
CAPSJ
3D3V_S5
NUMJ
* BC372
1nF * BC271
1nF * BC273
1nF * BC692
1nF * BC275
1nF * BC276
1nF * BC277
1nF * BC267
1nF * BC278
1nF
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
2
D18
COVER_SWJ 3 BAV99
Dummy
1
B B
For Another SKU
www.hocnghetructuyen.vn 3D3V_S0 LCDVDD_S0
BC279 5.6nF
3D3V_S0 3D3V_S0 3D3V_S5 3D3V_S0 3D3V_S0 SI3865_R1C1 C0603 50V, X7R, +/-10%
*
Layout 40 mil
U6
3D3V_S5
R219 100K 6 1 SI3865_R2
R220 1K R0402 +/-5% 5 R1/C1 R2
2
7 GMCH_LCDVDD_ON ON/OFF D2
R0402 +/-5% 4 S2 3
D2
R233
330
R224
330
R226
330
R221
330
R225
330
R971
100K
* BC280
1uF
*
BC281
0.1uF R222
*
BC282
1uF
+/-5% +/-5% +/-5% +/-5% +/-5% R0402 C0603 16V, Y5V, +80%/-20% Si3865DV 47K 10V, Y5V, +80%/-20%
R0603 R0603 R0603 R0603 R0603 +/-5% C0402 +/-5% C0603
PWR_LEDRJ R0402
Dummy Dummy Dummy Dummy Dummy
D
Green for Another Sku
Q13 3D3V_S5
1
2N7002EPT
Y
PWR_LED G
R972
100K
S
R0402
LED_Green 2
LED_Green 2
LED_Green 2
LED_Green 2
NUM_LED2
MEDIA_LED2
CAP_LED2
WLAN_LED2
+/-5%
LED_Yellow Green
CHG_LED2
ANTI_THEFTR_LEDJ
D
Dummy Dummy Dummy
Dummy Dummy Q20
A MEDIA_LEDJ A
2N7002EPT
WLANONLEDJ NUMJ G
30 ANTI_THEFT_LED
MEDIA_LEDJ CAPSJ
CHG_LEDJ CHG_LED2J
* BC380
S
CHG_LED2J CHG_LEDJ 1nF
CAPSJ WLANONLEDJ C0402
NUMJ
TECHNOLOGY COPR.
Title
* BC286
1nF * BC274
1nF * BC693
1nF * BC371
1nF * BC379
1nF * BC268
1nF LCD/Inverter
C0402 C0402 C0402 C0402 C0402 C0402 Document Number Rev
S09 MAINBOARD A
Dummy Dummy Dummy Dummy Dummy Dummy Date: Monday, March 14, 2005 Sheet 13 of 45
5 4 3 2 1
5 4 3 2 1
BC287 4.7pF
C0402 50V, NPO, +/-0.25pF
RTC circuitry
4
3D3V_AUX_S5
RTC_AUX_S5 R227
10M
+/-5%
C19 R0402
1uF X2
D D37
* D
1
1 10V, Y5V, +80%/-20% XTAL-32.768kHz U7A
3 C0603
BAT_D
2
*
X1_RTC Y1 P2 B_LPC_LAD0
BC288 4.7pF X2_RTC Y2 RTCX1 LAD[0]/FWH[0] B_LPC_LAD1 B_LPC_LAD0 28,30
RTCX2 LAD[1]/FWH[1] N3 B_LPC_LAD1 28,30
BAT54C C0402 50V, NPO, +/-0.25pF B_LPC_LAD2
LPC
N5
RTC
R229 180K RCT_RSTJ LAD[2]/FWH[2] B_LPC_LAD3 B_LPC_LAD2 28,30
AA2 RTCRST# LAD[3]/FWH[3] N4 B_LPC_LAD3 28,30
R0402 +/-5% 3D3V_S0
R231 R230 1M INTRUDERJ AA3 N6
1K R0402 +/-5% BC289 INTRUDER# LDRQ[0]# LPC_LDRQ1J 28
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4
+/-5% 0.1uF R232
R0402 RTC_SENSEJ 30 * 16V, Y5V, +80%/-20%
LFRAME#/FWH[4] P3 B_LPC_LFRAMEJ 28,30
10K
BAT
C0402 D12 +/-5%

R625 24 EEP_CS EE_CS R0402 D21
24 EEP_SK B12 EE_SHCLK
100K D11 AF22 H_A20GATE_1 1 2
24 EEP_DOUT EE_DOUT A20GATE H_A20GATE 30 1D05V_S0
+/-5% F13 AF23
24 EEP_DIN EE_DIN A20M# H_A20MJ 4
4
1
2
3
5
R0402 3D3V_S0 CH501H-40
LAN
LAN_CLK F12 AE27 R234
24 LAN_CLK LAN_CLK CPUSLP# H_CPUSLPJ 4,6 56
R989 22R0402 +/-5% LAN_RSTSYNC_R B11 AE24 H_DPRSLPJ +/-5%
24 LAN_RSTSYNC LAN_RSTSYNC DPRSLP# H_DPSLPJ H_DPRSLPJ 4 R0402
RTC_J1 DPSLP# AD27 H_DPSLPJ 4
R_LAN_RXD0 E12 R236 56
CPU
Header_1X3 24 R_LAN_RXD0 LANRXD[0]
R_LAN_RXD1 E11 AF24 H_FERR_R R0402 +/-5%
24 R_LAN_RXD1 LANRXD[1] FERR# H_FERRJ 4
R_LAN_RXD2 C13
24 R_LAN_RXD2 LANRXD[2]
CPUPWRGD/GPO[49] AG25 H_PWRGD 4
R986 22R0402 +/-5% LAN_TXD0_R C12 3D3V_S0
24 LAN_TXD0 R987 22R0402 +/-5% LAN_TXD1_R LANTXD[0]
C 24 LAN_TXD1 C11 LANTXD[1] IGNNE# AG26 H_IGNNEJ 4 C
R988 22R0402 +/-5% LAN_TXD2_R E13 AE22 R237
24 LAN_TXD2 LANTXD[2] INIT3_3V# 10K
INIT# AF27 H_INITJ 4
ACZ_BITCLK C10 AG24 +/-5% 1D05V_S0
26 ACZ_BITCLK ACZ_BIT_CLK INTR H_INTR 4
R239 39 R0402 +/-5% ACZ_SYNC_R B9 R0402 D22
AC-97/AZALIA
20,28 ACZ_SYNC ACZ_SYNC H_RCINJ_1
RCIN# AD23 1 2 H_RCINJ 30
R240 39 R0402 +/-5%ACZ_RSTJ_R A10
20,28 ACZ_RSTJ ACZ_RST# CH501H-40 R241
NMI AF25 H_NMI 4
F11 AG27 75
26,28 ACZ_SDATAIN0 ACZ_SDIN[0] SMI# H_SMIJ 4
F10 +/-5%
20 ACZ_SDATAIN1 ACZ_SDIN[1]
1 B10 AE26 R0402
ACZ_SDIN[2] STPCLK# H_STPCLKJ 4 R243
TP44
R242 39 R0402 +/-5% ACZ_SDATAOUT_R C9 AE23 H_THERMTRIP_R
20,28 ACZ_SDATAOUT ACZ_SDO THRMTRIP# PM_THRMTRIPJ 4,7
56 Layout Note: R632 needs to placed

AC19 SATALED# DA[0] AC16 IDE_A0 19
AB17 R0402 within 2" of ICH6, R634 must be placed
DA[1] IDE_A1 19 +/-5% within 2" of R632 w/o stub.
AE3 SATA[0]RXN DA[2] AC17 IDE_A2 19
AD3 SATA[0]RXP
AG2 SATA[0]TXN DCS1# AD16 IDE_CSJ0 19
AF2 SATA[0]TXP DCS3# AE17 IDE_CSJ1 19
AD7 SATA[2]RXN DD[0] AD14 IDE_D0 19
AC7 AF15
SATA
SATA[2]RXP DD[1] IDE_D1 19
AF6 SATA[2]TXN DD[2] AF14 IDE_D2 19
IDE
AG6 SATA[2]TXP DD[3] AD12 IDE_D3 19
DD[4] AE14 IDE_D4 19
B AC2 SATA_CLKN DD[5] AC11 IDE_D5 19 B
AC1 SATA_CLKP DD[6] AD11 IDE_D6 19
DD[7] AB11 IDE_D7 19
AG11 SATARBIAS# DD[8] AE13 IDE_D8 19
www.hocnghetructuyen.vn AF11 SATARBIAS DD[9]
DD[10]
AF13
AB12
IDE_D9
IDE_D10
19
19
AB13 1D05V_S0
DD[11] IDE_D11 19
DD[12] AC13 IDE_D12 19
AF16 AE15 NO_STUFF
19 IDE_IORDY IORDY DD[13] IDE_D13 19
AB16 AG15 R511
19 IDE_IRQ14 IDEIRQ DD[14] IDE_D14 19
AB15 AD13 56
19 IDE_DACKJ DDACK# DD[15] IDE_D15 19 +/-5%
19 IDE_IOWJ AC14 DIOW#
AE16 AB14 R0402
19 IDE_IORJ DIOR# DDREQ IDE_DREQ 19
Dummy
H_DPSLPJ
ICH6-M
A A
TECHNOLOGY COPR.
Title
ICH6(1 of 4)
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
U7C
3D3V_S0
U7B
22,29 B_PCI_AD[31..0] PM_RIJ T2 RI# PERn[1] H25
B_PCI_AD0 E2 L5 PCI_REQJ0 H24
AD[0] REQ[0]# PCI_REQJ0 22 PERp[1]
B_PCI_AD1 E5 PCI C1 SATA0_R0 AF17 G27
B_PCI_AD2 AD[1] GNT[0]# PCI_REQJ1 PCI_GNTJ0 22 R255 R254 10K R0402 +/-5% ICH_GID1 SATA[0]GP/GPI[26] PETn[1]
C2 AD[2] REQ[1]# B5 PCI_REQJ1 29 AE18 SATA[1]GP/GPI[29] PETp[1] G26
B_PCI_AD3 F5 B6 33 R256 10K R0402 +/-5% ICH_GID0 AF18
B_PCI_AD4 AD[3] GNT[1]# PCI_REQJ2 PCI_GNTJ1 29 +/-5% PLANARID2 SATA[2]GP/GPI[30]
F3 AD[4] REQ[2]# M5 AG18 SATA[3]GP/GPI[31] PERn[2] K25
PCI-EXPRESS
B_PCI_AD5 E9 F1 PCI_GNTJ2 R0402 K24
B_PCI_AD6 AD[5] GNT[2]# PCI_REQJ3 PERp[2]
F2 AD[6] REQ[3]# B8 PCI_REQJ3 22 17 B_SMB_CLK Y4 SMBCLK PETn[2] J27
B_PCI_AD7 D6 C8 PCI_GNTJ3 CLK_ICHPCI W5 J26
D B_PCI_AD8 AD[7] GNT[3]# PCI_REQJ4 PCI_GNTJ3 22 17 B_SMB_DATA SMB_LINK_ALERTJ Y5 SMBDATA PETp[2] D
E6 AD[8] REQ[4]#/GPI[40] F7 LINKALERT#
B_PCI_AD9 D3 E7 PCI_GNTJ4 R257 SMLINK0 W4 M25
GPIO
B_PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQJ5 33 SMLINK1 SMLINK[0] PERn[3]
A2 AD[10] REQ[5]#/GPI[1] E8 U6 SMLINK[1] PERp[3] M24
B_PCI_AD11 D2 F6 PCI_GNTJ5 +/-5% MCH_SYNCJ AG21 L27
B_PCI_AD12 AD[11] GNT[5]#/GPO[17] PCI_REQJ6 R0402 MCH_SYNC# PETn[3]
D5 AD[12] REQ[6]#/GPI[0] B7 26 ICH_SPKR F8 SPKR PETp[3] L26
B_PCI_AD13 H3 D8 FWH_WPJ 1 TP59 Dummy
B_PCI_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14] 30 PM_SUS_STATJ W3 SUS_STAT#/LPCPD# PERn[4] P24
B_PCI_AD15 J5 J6 BC290 P23
AD[15] C/BE[0]# B_PCI_C/BEJ0 22,29 PERp[4]
B_PCI_AD16
B_PCI_AD17
K2
K5
AD[16]
AD[17]
C/BE[1]#
C/BE[2]#
H6
G4
B_PCI_C/BEJ1
B_PCI_C/BEJ2
22,29
22,29
* 33pF
50V, NPO, +/-5%
DBRESETJ U2 SYS_RESET# PETn[4]
PETp[4]
N27
N26
B_PCI_AD18 D4 G2 C0603 AD19
AD[18] C/BE[3]# B_PCI_C/BEJ3 22,29 7 PM_BMBUSYJ BMBUSY#
B_PCI_AD19 L6 Dummy T25
AD[19] DMI[0]RXN DMI_RXN0 7
B_PCI_AD20 G3 A3 AE19 T24
AD[20] IRDY# B_PCI_IRDYJ 22,29 30 SMC_RUNTIME_SCIJ GPI[7] DMI[0]RXP DMI_RXP0 7
B_PCI_AD21 H4 E1 R1 R27
Direct Media Interface

B_PCI_AD22 AD[21] PAR R258 47 R0402 +/-5% B_PCI_PAR 22,29 30 SMC_EXTSMIJ_R GPI[8] DMI[0]TXN DMI_TXN0 7
H2 AD[22] PCIRST# R2 PCIRST1J 22,28,29 DMI[0]TXP R26 DMI_TXP0 7
B_PCI_AD23 H5 C3 SMB_ALERTJ W6
B_PCI_AD24 AD[23] DEVSEL# B_PCI_DEVSELJ 22,29 SMBALERT#/GPI[11]
B3 AD[24] PERR# E3 B_PCI_PERRJ 22,29 DMI[1]RXN V25 DMI_RXN1 7
B_PCI_AD25 M6 C5 PCI_LOCKJ ICH_GPI22 M2 V24
AD[25] PLOCK# GPI[12] DMI[1]RXP DMI_RXP1 7
B_PCI_AD26 B2 G5 R6 U27
B_PCI_AD27 AD[26] SERR# B_PCI_SERRJ 22,29 30 SMC_WAKE_SCIJ_R GPI[13] DMI[1]TXN DMI_TXN1 7
K6 AD[27] STOP# J1 B_PCI_STOPJ 22,29 DMI[1]TXP U26 DMI_TXP1 7
B_PCI_AD28 K3 J2 AC21
B_PCI_AD29 AD[28] TRDY# B_PCI_TRDYJ 22,29 3 PM_STPPCIJ STP_PCI#
A5 AD[29] DMI[2]RXN Y25 DMI_RXN2 7
B_PCI_AD30 L1 AB21 Y24
AD[30] GPO[19] DMI[2]RXP DMI_RXP2 7
B_PCI_AD31 K4 R5 R259 47 R0402 +/-5% W27
AD[31] PLTRST# D23 PLT_RST1J 7,17,30 DMI[2]TXN DMI_TXN2 7
PCICLK G6 CLK_ICHPCI 3 3,39 PM_STPCPUJ AD22 STP_CPU# DMI[2]TXP W26 DMI_TXP2 7
J3 P6 B_ICH_PMEJ_1 1 2
22,29 B_PCI_FRAMEJ FRAME# PME# Int. PH B_ICH_PMEJ 22,30
AD20 GPO[21] DMI[3]RXN AB24 DMI_RXN3 7
Interrupt I/F CH501H-40 AD21 AB23 1D5V_S0
GPO[23] DMI[3]RXP DMI_RXP3 7
INT_PIRQAJ N2 D9 INT_PIRQEJ AA27
PIRQ[A]# PIRQ[E]#/GPI[2] INT_PIRQEJ 22 DMI[3]TXN DMI_TXN3 7 Place within 500 mils of ICH
INT_PIRQBJ L2 C7 INT_PIRQFJ B_PM_CLKRUNJ V3 AA26
INT_PIRQCJ PIRQ[B]# PIRQ[F]#/GPI[3] INT_PIRQGJ GPIO[24] DMI[3]TXP DMI_TXP3 7
29 INT_PIRQCJ M1 PIRQ[C]# PIRQ[G]#/GPI[4] C6
INT_PIRQDJ L3 M3 INT_PIRQHJ P5 AD25 R261
C PIRQ[D]# PIRQ[H]#/GPI[5] GPIO[25] DMI_CLKN CLK_PCIE_ICHJ 3 C
R262 PLANARID3 R3 AC25 24.9
GPIO[27] DMI_CLKP CLK_PCIE_ICH 3
RESERVED 10K PLANARID4 T3 +/-1%
R263 100 R0402 +/-5% R264 100 R0402 +/-5% +/-5% GPIO[28] R0402
AC5 RSVD[1] RSVD[6] AD9 22,28,29,30 B_PM_CLKRUNJ AF19 CLKRUN# DMI_ZCOMP F24
R265 100 R0402 +/-5% AD5 AF8 R0402 PLANARID0 AF20
RSVD[2] RSVD[7] Dummy PLANARID1 AC18 GPIO[33] DMI_IRCOMP_R
AF4 RSVD[3] RSVD[8] AG8 GPIO[34] DMI_IRCOMP F23
AG4 RSVD[4] TP[3] U3
R266 100 R0402 +/-5% AC9 PCIE_WAKEJ U5 C23 USB_OCJ4
RSVD[5] WAKE# OC[4]#/GPI[9] USB_OCJ5
OC[5]#/GPI[10] D23
AB20 C25 USB_OCJ6
22,28,29,30 INT_SERIRQ SERIRQ OC[6]#/GPI[14]
ICH6-M C24 USB_OCJ7
3D3V_S0 OC[7]#/GPI[15] USB_OCJ7 33
3D3V_S5 AC20
RN58
3D3V_S0
ICH6 Pullups 18 THRMJ THRM#
OC[0]# C27 USB_OCJ0
USB_OCJ0 21
*
B_PCI_FRAMEJ PM_RIJ R267 10K PCI_REQJ6 R268 10K AF21 B27 USB_OCJ1
1 10 7,16 VROK VRMPWRGD OC[1]#
B_PCI_IRDYJ INT_PIRQDJ R0402 +/-5% R0402 +/-5% B26 USB_OCJ2 R981 0
B_PCI_TRDYJ 2 9 INT_PIRQEJ SMB_ALERTJ R269 10K PCI_REQJ1 R270 10K OC[2]# USB_OCJ3 R0402 +/-5%
E10 C26
CLOCKS
3 8 3 CLK_ICH14 CLK14 OC[3]#
B_PCI_STOPJ INT_PIRQFJ R0402 +/-5% R0402 +/-5%
4 7 INT_PIRQGJ SMB_LINK_ALERTJ R271 10K PCI_REQJ4 R272 10K
3D3V_S0 5 6 3 CLK48_ICH A27 CLK48 USBP[0]N C21 B_USB_PN0 21
R0402 +/-5% R0402 +/-5% D21
USBP[0]P B_USB_PP0 21 RN57
10K 10P8R0603 +/-5% SMLINK0 R273 10K V6 A20
17 PM_SUS_CLK SUSCLK USBP[1]N 3D3V_S0
*
R0402 +/-5% B20
RN59 USBP[1]P 1 10
SMLINK1 R276 10K T4 D19 USB_OCJ1
3D3V_S0 30 PM_SLP_S3J_ICH SLP_S3# USBP[2]N B_USB_PN1 21 2 9
*
B_PCI_SERRJ R0402 +/-5% T5 C19 USB_OCJ6

INT_PIRQHJ 1 10 B_PCI_DEVSELJ PCIE_WAKEJ R277 1K 30 PM_SLP_S4J_ICH SLP_S4# USBP[2]P B_USB_PP1 21 USB_OCJ3 3 8 USB_OCJ5
2 9 1 T6 SLP_S5# USBP[3]N A18 4 7
B_PCI_PERRJ PCI_REQJ2 R0402 +/-5% TP73 B18 USB_OCJ4
3 8 USBP[3]P 3D3V_S0 5 6
PCI_LOCKJ PCI_REQJ3 PM_BATLOWJ_R R278 8.2K AA1 E17
POWER MGT
4 7 18 PWROK PWROK USBP[4]N
B_PM_CLKRUNJ R0402 +/-5% D17 10K 10P8R0603 +/-5%
3D3V_S0 5 6 USBP[4]P
DBRESETJ R280 10K R281 100 R0402 +/-5% PM_DPRSLPVR_R AE20 B16
39 PM_DPRSLPVR DPRSLPVR USBP[5]N
USB
10K 10P8R0603 +/-5% R0402 +/-5% A16
ICH_GPI22 R512 10K PM_BATLOWJ_R USBP[5]P
RN60 3D3V_S0 V2 BATLOW# USBP[6]N C15
R0402 +/-5% D24 CH501H-40 D15
USBP[6]P
*
PCI_REQJ0 2 1 PWRBTNJ_ICH-1 U1 A14

1 10 30 PWRBTNJ_ICH PWRBTN# USBP[7]N B_USB_PN7 33
THRMJ INT_PIRQBJ 3D3V_S5 B14
B PCI_REQJ5 2 9 INT_PIRQCJ PLT_RST1J USBP[7]P B_USB_PP7 33 B
3 8 V5 LAN_RST#
MCH_SYNCJ INT_PIRQAJ A22 R285 22.6
4 7 INT_SERIRQ USBRBIAS# USB_RBIAS_PN R0402 +/-1%
3D3V_S0 5 6 Y3 RSMRST# USBRBIAS B22
10K 10P8R0603 +/-5% CLK48_ICH CLK_ICH14 R286 3D3V_S5 R287 R288 R289
2
4.7K 10K 10K 100K ICH6-M Place within 500 mils of ICH
R290 R291 +/-5% D38 +/-5% +/-5% +/-5%
33 33 R0402 CH501H-40 R0402 R0402 R0402
+/-5% +/-5% Dummy Dummy
R0402 R0402 T=22ms 3D3V_S0
1
Dummy Dummy PM_RSMRSTJ R7F9

BC291 R275 1K ICH_SPKR
*
BC292
33pF
*
BC293
33pF
R292
100K * 4.7uF
10V, Y5V, +80%/-20% 3D3V_S0
Planar ID(4,3,2,1,0)
R0402
Dummy
+/-5%
50V, NPO, +/-5% 50V, NPO, +/-5% +/-5% C0805 R7F8

C0603 C0603 R0402 R279 1K FWH_WPJ
Dummy Dummy R0402 +/-5%
Dummy
R293 R294 R295 R300 R296 R7F7
10K 10K 10K 10K 10K R282 1K PCI_GNTJ5
+/-5% +/-5% +/-5% +/-5% +/-5% R0402 +/-5%
R0402 R0402 R0402 R0402 R0402 Dummy
D26 Dummy Dummy Dummy Dummy Dummy
2 1 PLANARID0 R513 1K PCI_GNTJ4
18 PURE_HW_SHUTDOWNJ
PLANARID1 R0402 +/-5%
CH501H-40 PLANARID2 Dummy
PLANARID3 R528 1K PCI_GNTJ2
D
www.hocnghetructuyen.vn Q4
PLANARID4
R297 R298 R299 R348 R325

R0402 +/-5%
Dummy
G 10K 10K 10K 10K 10K
18 HW_SHUT
2N7002EPT +/-5% +/-5% +/-5% +/-5% +/-5%
A Dummy R0402 R0402 R0402 R0402 R0402 A
S
TECHNOLOGY COPR.
Title
ICH6(2 of 4)
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
Layout Note:
Place above caps within
100 mils of ICH near F27, P27, AB27 1D5V_S0
BC298
U7E * BC294 BC295

0.1uF 0.1uF * BC296
0.1uF * BC297
0.1uF * * 10nF
25V, X7R, +/-10%
*Within a given well, 5VREF needs to be up before the
corresponding 3.3V rail
C0603 C0603 C0603 C0603 C0402
1D5V_S0
Layout Note:
Place near pin AA19
AA22 F9 3D3V_S0 5V_S0
TC9 VCC1_5_B VCC1_5_A
AA23 VCC1_5_B VCC1_5_A U17
1
D
* 220uF
* BC299
* BC300 BC301
* AA24 VCC1_5_B VCC1_5_A U16 D
1
4V, +/-20%
ctdh19
0.1uF
C0603
0.1uF 0.1uF
C0603 C0603
AA25
AB25
VCC1_5_B VCC1_5_A U14
U12
BC302
0.1uF* BC303
0.1uF * BC304
0.1uF * BC305
0.1uF * BC306
0.1uF * * BC307
22uF D27
R301
100
2
VCC1_5_B VCC1_5_A C0603 C0603 C0603 C0603 C0603 10V, Y5V, +80%/-20% +/-5%
AB26 VCC1_5_B VCC1_5_A U11 CH501H-40
AB27 T17 Dummy Dummy Dummy Dummy Dummy C1206 R0402
VCC1_5_B VCC1_5_A Dummy
F25 T11
2
VCC1_5_B VCC1_5_A V5REF_S0
F26 P17
CORE
VCC1_5_B VCC1_5_A BC308 BC309
F27 VCC1_5_B VCC1_5_A P11
G22
G23
VCC1_5_B
VCC1_5_B
VCC1_5_A
VCC1_5_A
M17
M11 ALL NO_STUFF Caps do
0.1uF
16V, Y5V, +80%/-20% * * 1uF
10V, Y5V, +80%/-20%
G24 L17 not have layout C0402 C0603
Layout Note: VCC1_5_B VCC1_5_A
G25 VCC1_5_B VCC1_5_A L16 requirements but if
IDE decoupling H21 L14 layout allows then place
3D3V_S0 VCC1_5_B VCC1_5_A
H22 VCC1_5_B VCC1_5_A L12 next to ICH6
J21 L11 3D3V_S5 5V_S5
VCC1_5_B VCC1_5_A
* BC310
0.1uF * BC311
0.1uF * BC312
0.1uF * BC313
0.1uF
J22
K21
VCC1_5_B
VCC1_5_B
VCC1_5_A
VCC1_5_A
AA21
AA20 Place within 100
1
C0603 C0603 C0603 C0603 1D5V_S0 K22 AA19 mils of ICH pin 3D3V_S0 R302
VCC1_5_B VCC1_5_A AG13, AG16 Layout Note: D28 10
L21 VCC1_5_B Place near ICH6
BC314
* L22 AA10 CH501H-40 +/-5%
PCIE
VCC1_5_B VCC3_3
0.1uF
C0603
M21
M22
VCC1_5_B VCC3_3 AG19
AG16
BC315
0.1uF * BC316
0.1uF * R0402
2
Dummy VCC1_5_B VCC3_3 C0603 C0603 V5REF_S5
N21 VCC1_5_B VCC3_3 AG13
N22 AD17 BC317 BC318
Layout Note: VCC1_5_B VCC3_3
N23 AC15 0.1uF
* * 1uF
IDE
PCI decoupling VCC1_5_B VCC3_3 16V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
N24 VCC1_5_B VCC3_3 AA17
3D3V_S0 N25 AA15 C0402 C0603
BC322 BC323 VCC1_5_B VCC3_3 Layout Note: 3D3V_S0
P21 VCC1_5_B VCC3_3 AA14
Distribute in PCI section
BC319
0.1uF * BC320
0.1uF * BC321
0.1uF * * 10uF
C0805 * 10uF
C0805
P25
P26
VCC1_5_B
VCC1_5_B
VCC3_3 AA12
near pin A2-A6 near D1-H1
C0603 C0603 C0603 Dummy Dummy P27 P1
VCC1_5_B VCC3_3
C
Dummy Dummy Dummy R21
R22
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
M7
L7
BC324
0.1uF * * BC325 BC326
0.1uF 0.1uF * C
T21 L4 C0603 C0603 C0603
VCC1_5_B VCC3_3
T22 VCC1_5_B VCC3_3 J7
PCI
U21 VCC1_5_B VCC3_3 H7
U22 H1 1D5V_S5
VCC1_5_B VCC3_3
V21 VCC1_5_B VCC3_3 E4
V22
W21
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
B1
A6
BC327
0.1uF * * BC328
0.1uF
W22 C0603 C0603
1D5V_S0 VCC1_5_B 3D3V_S0
Y21 VCC1_5_B VCCSUS1_5 U7
Y22 VCC1_5_B VCCSUS1_5 R7 R600
1D5V_S5
AA6 VCC1_5_A
USB
AB4 VCC1_5_A VCCSUS1_5 G19
Place within 100 1D5V_S0
mils of ICH
BC329
0.1uF * BC330
0.1uF * BC331
0.1uF * AB5
AB6
VCC1_5_A
VCC1_5_A VCC1_5_A G20 BC332
* R601
0 U35
5
near pin AG5 R0402
C0603 C0603 C0603 AC4
AD4
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
F20
E24
BC333
0.1uF * * BC334
0.1uF
0.1uF
C0603
39 VRMPWRGD
+/-5% 1
AE4 E23 C0603 C0603 4
USB CORE
VCC1_5_A VCC1_5_A VROK 7,15
AE5 VCC1_5_A VCC1_5_A E22 10K 2
AF5 E21 Place both BC677
VCC1_5_A VCC1_5_A
1
1D5V_S0 within 100 mils R0402
AG5 E20
* 1uF NC7SZ08
SATA
3
VCC1_5_A VCC1_5_A of ICH near D27 +/-5% 10V, Y5V, +80%/-20% Dummy
VCC1_5_A D27
Place within 100 AA7 D26 Dummy C0402
2
mils of ICH VCC1_5_A VCC1_5_A Dummy
AA8 VCC1_5_A VCC1_5_A D25
near pin AG9 BC335
1D5V_GPLL_ICH_S0 0.1uF * BC336
0.1uF * BC337
0.1uF * AA9
AB8
VCC1_5_A
VCC1_5_A
VCC1_5_A D24
1D5V_S0 C0603 C0603 C0603 AC8 G8 V2D5S_PCI_IDE 2D5V_S0
R303 VCC1_5_A VCC1_5_A
AD8 VCC1_5_A
R0603 0 +/-5% 1D5V_GPLL_ICH_S0 AE8 AB18 R304 0
PCI/IDE
VCC1_5_A VCC2_5 1D5V_ICH_S0

Place within 100
*
BC339
10uF
*
BC340
0.1uF
AE9
AF9
VCC1_5_A
VCC1_5_A
VCC2_5 P7 BC338
0.1uF * R0603 +/-5%
Place within 100
REF
B mils of ICH C0805 16V, X7R, +/-10% C0603 Layout Note: mils of ICH B
AG9 VCC1_5_A
C0603 AA18 Place near AB18
V5REF
3D3V_S0
AC27
E26
VCCDMIPLL
VCC3_3
V5REF A8
V5REF_S0
BC341
0.1uF *
F21 V5REF_S5 3D3V_ICH_S5 C0603
V5REF_SUS
AE1 VCCSATAPLL
Place within 100
BC342
0.1uF * 1D5V_S0
R305 0
1D5V_ICH_S0 AG10 VCC3_3 VCCUSBPLL
VCCSUS3_3
A25
A24
mils of ICH C0603 R0603 +/-5% A13 Place within 100
near E26, E27 VCCLAN3_3/VCCSUS3_3 mils of ICH
BC343
0.1uF * F14
G13
VCCLAN3_3/VCCSUS3_3
VCCLAN3_3/VCCSUS3_3
VCCRTC AB3 BC344
0.1uF *
Place within 100
C0603 G14 1D5V_S5 C0603
mils of ICH VCCLAN3_3/VCCSUS3_3
3D3V_S0 pin AE1 A11
U4
VCCSUS3_3
VCCSUS3_3
VCCLAN1_5/VCCSUS1_5
VCCLAN1_5/VCCSUS1_5
G11
G10 BC345
0.1uF * Place within 100 RTC_AUX_S5 www.hocnghetructuyen.vn
V1 AG23 C0603 mils of ICH Layout Note:
VCCSUS3_3 V_CPU_IO
Place within 100
mils of ICH
BC346
0.1uF * V7
W2
VCCSUS3_3
VCCSUS3_3
V_CPU_IO
V_CPU_IO
AD26
AB22
pin G10 Place near AB3
pin AG10 1D05V_S0

C0603
3D3V_S5
Y7 VCCSUS3_3
VCCSUS3_3 G16
BC347
0.1uF * BC348
0.1uF *
A17
B17
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
G15
F16
BC349
0.1uF * C0603 C0603
C17 F15 C0603

Place within 100 VCCSUS3_3 VCCSUS3_3 Layout Note:
1D5V_S0 mils of ICH
BC350
0.1uF * BC351
0.1uF * F18
G17
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
E16
D16 Place near AG23
pin A13 C0603 C0603 G18 C16
VCCSUS3_3 VCCSUS3_3
BC355 3D3V_ICH_S5 3D3V_S5
*
BC352 BC353
0.1uF 0.1uF * BC354
0.1uF * * 10uF
C0805 3D3V_S5 V3D3A_VCCPSUS
ICH6-M
R306 0
C0603 C0603 C0603 Dummy R307 0 R0603 +/-5%
A
Dummy Dummy Dummy R0603 +/-5%
Place within 100
BC356
0.1uF * BC357
0.1uF * BC358
0.1uF * BC359
0.1uF * A
mils of ICH Place within 100
BC360
0.1uF * pin V7
C0603 C0603 C0603
Dummy
C0603
Dummy mils of ICH
C0603 NO_STUFF NO_STUFF pin A17
TECHNOLOGY COPR.
Title
ICH6(3 of 4)
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
U7D
E27 VSS VSS F4

32K suspend clock output Y6 VSS VSS F22
Y27 VSS VSS F19
3D3V_S5 Y26 F17
VSS VSS
Y23 VSS VSS E25
20,30,36,37,38,40 S0_EN W7 VSS VSS E19
U8 W25 E18
VSS VSS
5
1
D R308 W24 VSS VSS E15 D
W23 VSS VSS E14
2 4 32KHZ W1 D7
15 PM_SUS_CLK CLK32_G768 18 VSS VSS
V4 VSS VSS D22
Dummy Dummy V27 D20
NC7SZ126 R309 10 VSS VSS
V26 D18
3
240K R0402 VSS VSS
V23 VSS VSS D14
+/-5% +/-5% U25 D13
R0603 VSS VSS
U24 VSS VSS D10
R514 0 Dummy U23 D1
R0603 +/-5% VSS VSS
U15 VSS VSS C4
U13 VSS VSS C22
T7 VSS VSS C20
T27 VSS VSS C18
T26 VSS VSS C14
T23 VSS VSS B25
T16 VSS VSS B24
T15 VSS VSS B23
T14 VSS VSS B21
5V_S0 T13 B19
VSS VSS
T12 VSS VSS B15
T1 VSS VSS B13
5
1
R310 R4 VSS VSS AG7
U37 R25 AG3
VSS VSS
7,15,30 PLT_RST1J 2 4 RSTDRVJ_5 19 R24 VSS VSS AG22
R23 VSS VSS AG20
74HCT1G125 Dummy R17 AG17
C 3 Dummy R311 33 R16
VSS VSS
AG14 C
10K R0402 VSS VSS
R15 VSS VSS AG12
+/-5% +/-5% R14 AG1
R0402 VSS VSS
R13 VSS VSS AF7
R515
R0603
0
+/-5%
Dummy R12
R11
VSS
VSS
VSS
VSS
AF3
AF26
VSS
P22 VSS VSS AF12
P16 VSS VSS AF10
P15 VSS VSS AF1
PLT_RSTJ 3V to 5V level shift for HDD & CDROM P14 VSS VSS AE7
P13 VSS VSS AE6
P12 VSS VSS AE25
N7 VSS VSS AE21
N17 VSS VSS AE2
N16 VSS VSS AE12
N15 VSS VSS AE11
N14 VSS VSS AE10
N13 VSS VSS AD6
N12 VSS VSS AD24
N11 VSS VSS AD2
N1 VSS VSS AD18
M4 AD15
SMBUS 3D3V_S0 M27
VSS
VSS
VSS
VSS AD10
M26 VSS VSS AD1
M23 VSS VSS AC6
3D3V_S5 M16 AC3
3D3V_S0 VSS VSS
M15 VSS VSS AC26
B M14 VSS VSS AC24 B
M13 VSS VSS AC23
R312 M12 AC22
R313 R314 2.2K VSS VSS
L25 VSS VSS AC12
10K 10K +/-5% R315 R316 L24 AC10
+/-5% +/-5% R0402 4.7K 4.7K VSS VSS
L23 VSS VSS AB9
R0402 R0402 +/-5% +/-5% L15 AB7
R0402 R0402 VSS VSS
L13 VSS VSS AB2
K7 VSS VSS AB19
Q5 K27 AB10
G
VSS VSS
K26 VSS VSS AB1
K23 VSS VSS AA4
D S K1 AA16
G
15 B_SMB_CLK Q6 SMBC_ICH 3,11 VSS VSS

J4 VSS VSS AA13
J25 VSS VSS AA11
2N7002EPT D S J24 A9
15 B_SMB_DATA B_SMBD_ICH 3,11 VSS VSS
J23 VSS VSS A7
H27 VSS VSS A4
2N7002EPT H26 A26
VSS VSS
H23 VSS VSS A23
G9 VSS VSS A21
G7 VSS VSS A19
G21 VSS VSS A15
G12 VSS VSS A12
G1 VSS VSS A1
A ICH6-M A
TECHNOLOGY COPR.
Title
ICH6(4 of 4)
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
Put thisCap near the thermal diode.

Put thisCap near the thermal diode.
THERMDP2_DDR
THERMDP2_VCORE BC702 Reserve for G768B
C
BC361 * 470pF
50V, X7R, +/-10% B
works at High
C
Speed
* 470pF
50V, X7R, +/-10% B
C0402
Q21
E
C0402 THERMDN_DDR MMBT3904
Q8 3D3V_S0 5V_S0
D
E
THERMDN_VCORE MMBT3904 SYSTEM SENSOR
D 5V_S0 5V_G768_S0 Q7 2N7002EPT D
SYSTEM SENSOR Dummy
R317
R318 G RUNPWROK
R319 R320 10K
Another Thermal Group BC362 BC363 10K 10K +/-5%
S
0 0.1uF
R0603 16V, Y5V, +80%/-20% * * 10uF
10V, Y5V, +80%/-20%
+/-5%
R0402
+/-5%
R0402
R0402
Dummy
+/-5% C0402 C0805
R321 0 +/-5% R0603
5
1
THERMDP1 U9 U36
BC364 VCC_FAN 1 16 G768_HW_SHDN 2 4 HW_SHUT

3D3V_S0 OUT1 OUT2 HW_SHUT 15
* 2.2nF
50V, X7R, +/-10%
4 THERMDP1
THERMDP1
2
3
VCC
DXP1
VCC
SMBCLK
15
14 B_KBC_SCL1 13,30
Dummy R322 R323
C0402 THERMDN 4 13 74HCT1G125 100 10K R0402
3
4 THERMDN DXN FG2
5
NC7SZ08 THERMDP2 5 12 R0402 +/-5%
DXP2 SMBDATA B_KBC_DAT1 13,30
THERMDN 1 RUNPWROK G768_RSTJ 6 11 +/-5% Dummy
RESET# ALERT# FAN_FB THRMJ 15
15 PWROK 4 7 GND FG1 10 Dummy
2 R326 R324 10K 8 9
GND CLK CLK32_G768 17
20K
Dummy +/-5% R0402
3
THERMDP1/DP2/THERMDN ON THE SAME LAYER U10 R0402 +/-5% G768D
W/S = 10/5 MIL, 12 MIL AWAY FROM OTHERS
CAPS CLOSE TO G768B
Put these two Caps near U9
HW thermal shut down tempature
setting 95 degree . Put Near CPU .
THERMDP2_VCORE R651 0 Dummy

C R0603 +/-5% THERMDP2 C
THERMDP2_DDR R652 0 BC365
5V_S0
R0603 +/-5%
* 2.2nF
50V, X7R, +/-10%
THERMDN_VCORE R655 0 Dummy C0402
R0603 +/-5% THERMDN R327
THERMDN_DDR R656 0 10K VCC_FAN
R0603 +/-5% +/-5%
R0402
J6 *Layout* 15 mil
5 NC 3 FAN_FB BC366 BC367 BC368
Thermal Group Option 4 NC

2
1 VCC_FAN
0.1uF
16V, Y5V, +80%/-20% * * 10uF
10V, Y5V, +80%/-20% * 2.2nF
50V, X7R, +/-10%
2
C0402 C0805 C0402
D29
Header_1X3
CH501H-40
1
B B
5V_AUX_S5
15 PURE_HW_SHUTDOWNJ
5V_AUX_S5
5V_AUX_S5 BC369
5V_AUX_S5 5V_AUX_S5
R328
R0402
18K CPU_THSET
+/-1%
0.1uF
*
16V, X7R, +/-10%
C0603 R329
R330 0
10K U11 R0603
+/-5%
R0402 +/-5%
1 SET VCC 6
5
U12 2 5
PURE_HW_SHUTDOWNJ GND OUTSET CPU_TH_HYST
5 VCC NC 1 1 3 OUT# HYST 4
2 SHUTDOWN_S5J 4
A
36 SHUTDOWN_S5 4 Y GND 3 2 S5_EN 30
U13 MAX6510HAUT-T
NC7SZ14 NC7SZ08 R331 R332
3
HW thermal shut down tempature 0 0

setting 95 degree . Put Near CPU . R0603 R0603
+/-5% +/-5%
Dummy Dummy
A A
TECHNOLOGY COPR.
Title
THERMAL G768
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
HDD Connector
HDDCON1
D D
PBRSTDRV1J_5 R333 33
2 1 RSTDRVJ_5 17
IDE_D7 R0402 +/-5%
14 IDE_D8 4 3 IDE_D7 14
IDE_D6
14 IDE_D9 6 5 IDE_D6 14
IDE_D5
14 IDE_D10 8 7 IDE_D5 14 5V_S0 3D3V_S0
IDE_D4
14 IDE_D11 10 9 IDE_D4 14
14
14
IDE_D12
IDE_D13
12
14
11
13
IDE_D3
IDE_D2
IDE_D3
IDE_D2
14
14
IDE_D1 R334 R335
14 IDE_D14 16 15 IDE_D1 14
IDE_D0 4.7K 4.7K
14 IDE_D15 18 17 IDE_D0 14
+/-5% +/-5%
20 19 R0402 R0402
22 21 IDE_DREQ 14
H: Slave 24 23 IDE_IOWJ 14
L: Master 26 25 IDE_IORJ 14
HDDCSEL1
28 27 PBIDDACKJ R336 33 IDE_IORDY 14
30 29 R0402 +/-5% IDE_DACKJ 14
R337 DIAG 32 31 IDE_IRQ14 14
34 33 IDE_A1 14
470
14 IDE_A2 36 35 IDE_A0 14
+/-5%
14 IDE_CSJ1 38 37 IDE_CSJ0 14
R0402
40 39 MEDIA_LEDJ 13
42 41
5V_S0
45
46
44
FG1
FG2
43
Master
HEADER_2X22 (HDD)
C C
5V_S0
CDROM
2
BC700 BC701 CN6

10V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
D41 BC699 0.1uF 0.1uF

SSM22LLPT
* 22uF * C0402 * C0402
52
C1206 49 50
26 CD_AUDR CD_GND CD_AUDL 26
47 48
1
IDE_D8 RSTDRVJ_5 CD_GND 26

45 46
IDE_D9 43 44 IDE_D7
IDE_D10 41 42 IDE_D6
IDE_D12
IDE_D13
IDE_D14
37
35
33
38
36
34
IDE_D4
IDE_D3
IDE_D2
SLAVE
IDE_DREQ 29 30 IDE_D0 3D3V_S0
IDE_IORJ 27 28
25 26 IDE_IOWJ
B IDE_DACKJ 23 24 IDE_IORDY B
TP80 1BAY_ID0 21 22 IDE_IRQ14 R338 8.2K
DIAG 19 20 IDE_A1 R0402 +/-5%
IDE_A2 17 18 IDE_A0 R10 0 MEDIA_LEDJ
5V_S0 IDE_CSJ1 15 16 IDE_CSJ0 R0402 +/-5%
R339 R340 13 14 ODD_LEDJ R343 10K Dummy
2.7K 10K 11 12 R0402 +/-5%
+/-5% +/-5% 9 10
R0402 R0402 R341 10K 5V_S0
7 8
Dummy 5 6 R0402 +/-5%
BC374 BC375 3 4 CSEL CDROM_CSEL R342 10K
0.1uF 0.1uF R0402 +/-5%
BC373 * * * 1 2 H: Slave Dummy
0.1uF C0402 C0402 L: Master
C0402 51
CD-ROM-50P
16V, Y5V, +80%/-20%
5V_S0
10V, Y5V, +80%/-20%
A A
BC376 BC378 BC377

0.1uF 10uF 10uF
25V, Y5V, +80%/-20% * * * 10V, Y5V, +80%/-20%
C0603 C0805 C0805 TECHNOLOGY COPR.
Title
HDD/CDROM
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
D D
CN7
R624 0 +/-5% 1 2
26 MDM_AUD_IN 1 2
Dummy 3 4
3 4 MDM_AUD_OUT 26
5 5 6 6
7 7 8 8
9 9 10 10 5V_S0
11 12 BC711
11 12 0.1uF
13
15
13
15
14
16
14
16
* 10V, X7R, +/-10%
3D3V_S5 17 18 C0402
17 18
C 19 19 20 20 C
3D3V_S0 21 21 22 22 ACZ_SYNC 14,28
23 24 R344 0 +/-5%
14,28 ACZ_SDATAOUT 23 24
25 26 R345 0 +/-5%
14,28 ACZ_RSTJ 25 26 Dummy ACZ_SDATAIN1 14
27 27 28 28
29 29 30 30 ACZ_BTCLK_MDC 26
31 H1 H2 32
R346
0.8P BTB_SMT 30P 10K
+/-5%
R0402
Dummy
G
Q9
17,30,36,37,38,40 S0_EN S D MDC_RINGJ 30
2N7002EPT
Dummy
B B
A A
TECHNOLOGY COPR.
Title
MDC
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
Dual Layout
USB2PWR
5V_S0
16V, Y5V, +80%/-20%

D U67 D
1 GND OUT 8
2 IN OUT 7
BC538 3 6
IN OUT
0.1uF
C0402 * 4 EN# OUTNC 5
MAX1930ESA Dummy
100 mil
5V_S0
USB2PWR
F2 100 mil
* BC534 BC535 BC536 TC13
*
16V, Y5V, +80%/-20%

F1210_1.1A
* 4.7uF
* 0.1uF
* 1nF 150uF R975
10V, Y5V, +80%/-20%

6.3V, +/-20% 47K
C0805 C0402 50V, X7R, +/-10% CTD +/-5%
C0402 R0402
BC537 USB_OCJ0 15
16V, Y5V, +80%/-20%

R976
56K * 0.1uF
+/-5% C0402
R0603
C C
USB1
5
USB2PWR 1 VCC
R494 0
B_USB_PN1 R0402 +/-5% USB_1- 2
USB-
15 B_USB_PN1
USB_1+ 3
Dummy L21
USB+
4 3 4 GND
6
1 2
USB
Common Choke 90 Ohm
R496 0
B_USB_PP1 R0402 +/-5%
15 B_USB_PP1
R498 0
B_USB_PN0 R0402 +/-5% USB2
15 B_USB_PN0
5
B USB2PWR B
1 VCC
Dummy L22
4 3 USB_0- 2
USB-
1 2 USB_0+ 3 USB+
Common Choke 90 Ohm 4 GND
6
R500 0
B_USB_PP0 R0402 +/-5% USB
15 B_USB_PP0
A A
TECHNOLOGY COPR.
Title
USB*2/POWERSWITCH
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
B_1394_TPA0P 23
B_1394_TPA0N 23
B_1394_TPB0P 23
B_1394_TPB0N 23
INT_PIRQEJ R958 R959 R960 R961
56.2 56.2 56.2 56.2
15,28,29,30 INT_SERIRQ +/-1% +/-1% +/-1% +/-1%
29 CBUS_PMEJ
R0603 R0603 R0603 R0603
26 PCI_SPKR +/-5% R0603 43K R926 1394_TPBIAS0
3D3V_S0
FW-RESETN FW-RESETN BC72 BC71
R962
47K 15 PCI_REQJ3
1uF
10V, X5R, +/-10% * * 220pF R947
4.99K
16V, Y5V, +80%/-20%
+/-5% 15 PCI_REQJ0 C0603 C0402 +/-1%

15 PCI_GNTJ3 3D3V_S0
BC704 R948 R0402 25V, NPO, +/-5% R0603
15 PCI_GNTJ0
* 0.1uF 510K
+/-5%
B_PCI_AD25
B_PCI_AD19
+/-5% R0402
+/-5% R0402
100 R347
100 R949
C0402 R0603 3D3V_S0 +/-5% R0402 10K R950
15,28,29 PCIRST1J VCCD1J 23
R953 R954 R955
3 PCLK_PCM VCCD0J 23
R979 0 10K 10K 10K
R0402 +/-5% VPPD1 23
15,29 B_PCI_FRAMEJ R0402 VPPD0 23
15,29 B_PCI_IRDYJ R956 B_CBB_D2 23
15,29 B_PCI_TRDYJ B_CBB_D14 23
2.49K
15,29 B_PCI_DEVSELJ B_CBB_A18 23
+/-1%
15,29 B_PCI_STOPJ B_CBB_CD1J 23
R0603
15,29 B_PCI_PERRJ CBB_CD2J 23
15,29 B_PCI_SERRJ B_CBB_VS1J 23
15 INT_PIRQEJ B_CBB_VS2J 23
W11
W13
W12
W14
M19
M16
G19
G18
G12
R13
R12
R14
N12
N11
N18
N19
H18
H19
R16
R15
H13
B12
P14
P11
P13
V12
V11
V13
V15
B11
A11
A12
B15
A15
P18
P19
K18
K19
P15
T14
T13
T12
F19
F18
T16
T15
J18
J19
M7
G1
G2
R4
N6
N4
D4
H1
H2
D5
D7
U63
P6
P5
P4
K1
K7
E4
A5
B6
B5
A6
B7
A7
F2
F9
L4
J2
J7
15,29 B_PCI_AD[31..0]
B_PCI_AD0 T11
FW-PCICLK
FW-PCIVIOS
PCICLK
FW-ROMCLK
FW-NANDTREE
FW-CNA
FW-SE
FW-TPB2P
FW-TPA2P
FW-TPA0P
FW-TPB0P
FW-TPA1P
FW-TPB1P
FW-TPB2M
FW-TPA2M
FW-TPA0M
FW-TPB0M
FW-TPA1M
FW-TPB1M
FW-RESET#
SPKROUT
G_RST#
RI_OUT#/PME#
FW-TEST0
FW-TEST1
FW-LPS
FW-CPS
FW-SM
FW-TPBIAS2
FW-TPBIAS0
FW-TPBIAS1
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
FW-INTA#
PCIRST#
FW-PCIRST#
FW-IDSEL
IDSEL
PCIGNT#
FW-PCIGNT#
PCIREQ#
FW-PCIREQ#
SUSPEND#
FW-PME#
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
FW-PC0
FW-PC1
FW-PC2
FW-PTEST
FW-CONTENDER
FW-R0
FW-R1
FW-LKON
VCCD1#
VCCD0#
VPPD1
VPPD0
RSVD/D2
RSVD/D14
RSVD/A18
CVS1/VS1
CVS2/VS2
CCD1#/CD1#
CCD2#/CD2#
FW-ROMAD
B_PCI_AD1 AD0
N10 AD1 CAD31/D10 E5 B_CBB_D10 23
B_PCI_AD2 P10 F6
AD2 CAD30/D9 B_CBB_D9 23
B_PCI_AD3 T10 E6
B_PCI_AD4 R10 D6
B_PCI_AD5 T9 F7
B_PCI_AD6 R9 D9
AD6 CAD26/A0 B_CBB_A0 23
PCLK_PCM B_PCI_AD7 N9 G10
B_PCI_AD8 R8 F10
R929 B_PCI_AD9 P8 D11
33 B_PCI_AD10 N8 G11
+/-5% B_PCI_AD11 R7 D12
R0402 B_PCI_AD12 N7 F12
Dummy B_PCI_AD13 T6 D13
C635
* B_PCI_AD14 R6 AD14 CAD18/A7 E13 B_CBB_A7 23
50V, NPO, +/-5%
33pF B_PCI_AD15 T5 G13

B_PCI_AD16 M5 H15
C0603 B_PCI_AD17 M4 J13 CBB_IOWRJ 23
Dummy B_PCI_AD18 AD17 CAD15/IOWR#
L7 AD18 CAD14/A9 H16 B_CBB_A9 23
B_PCI_AD19 L6 J16 CBB_IORDJ 23
B_PCI_AD20
B_PCI_AD21
K6
K5
AD19
AD20
AD21
www.hocnghetructuyen.vn CAD13/IORD#
CAD12/A11
CAD11/OE#
J14
K13
B_CBB_A11
B_CBB_OEJ
23
23
B_PCI_AD22 J4 K14 B_CBB_CE2J 23
B_PCI_AD23 AD22 CAD10/CE2#
J5 AD23 CAD9/A10 K15 B_CBB_A10 23
B_PCI_AD24 H5 L15 B_CBB_D15 23
B_PCI_AD25 AD24 CAD8/D15
H6 AD25 CAD7/D7 L13 B_CBB_D7 23
B_PCI_AD26 H7 M14 B_CBB_D13 23
G4 AD27 CAD5/D6 M15 B_CBB_D6 23
B_PCI_AD28 G5 N16 B_CBB_D12 23
G7 AD29 CAD3/D5 M13 B_CBB_D5 23
B_PCI_AD30 F4 N13 B_CBB_D11 23
F5 AD31 CAD1/D4 N15 B_CBB_D4 23
CSTSCHG/BVD1/STSCHG#
CAD0/D3 P16 B_CBB_D3 23
CCLKRUN#/WP/IOIS16#
15,28,29,30 B_PM_CLKRUNJ F1 FW-CLKRUN#
CAUDIO/BVD2/SPKR#
B13
CINT#/READY/IREQ#
FW-XI
15,29 B_PCI_C/BEJ0 T8 CBE0# FW-XO A13 X8
FW-VAUXPRSNT
CREQ#/INPACK#
T4
CSERR#/WAIT#
15,29 B_PCI_C/BEJ1 CBE1#
FW-CARDBUS#
CDEVSEL#/A21
FW-MPCIACT#
CRST#/RESET
CFRAME#/A23
CBLOCK#/A19
15,29 B_PCI_C/BEJ2 M6 CBE2# CCBE0#/CE1# L16 B_CBB_CE1J 23 2 1
CPERR#/A14
CTRDY#/A22
CSTOP#/A20
CGNT#/WE#
FW-PLLVDD
CIRDY#/A15
FW-PLLVSS
H4 H14 B_CBB_A8 23
FW-VDDA1
FW-VDDA2
FW-VDDA3
15,29 B_PCI_C/BEJ3 CBE3# CCBE1#/A8
FW-VDD10
FW-VDD11
FW-VSSA1
FW-VSSA2
FW-VSSA3
FW-VSSA4
FW-VSS10
FW-VSS11
FW-VSS12
FW-VSS13
FW-VSS14
X-24D576MHz
CCLK/A16
FW-VDD1
FW-VDD2
FW-VDD3
FW-VDD4
FW-VDD5
FW-VDD6
FW-VDD7
FW-VDD8
FW-VDD9
R5 D14
FW-VSS1
FW-VSS2
FW-VSS3
FW-VSS4
FW-VSS5
FW-VSS6
FW-VSS7
FW-VSS8
FW-VSS9
15,29 B_PCI_PAR PAR CCBE2#/A12 B_CBB_A12 23

E10
VCCA1
VCCA2
VCC10
CCBE3#/REG# CBB_REGJ 23
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
CPAR/A13 G16 B_CBB_A13 23 * BC705

10pF * BC706
10pF
C0402 C0402
G6
L5
P7
R11
N14
J15
F13
E9
B9
E2
K2
L2
M2
N2
P2
R2
V5
V6
V7
V8
V9
V10
A14
R18
M18
L18
E18
J6
K4
N5
T7
P9
P12
L14
G15
F11
E7
A9
E1
J1
L1
M1
N1
P1
R1
W7
W9
W15
B14
R19
L19
E19
A10
A8
V14
K16
D10
E8
F8
G9
G14
F14
E11
D8
F16
F15
E16
D16
D15
E14
G8
E12
E15
CB851
+/-5% R0402 10 R932 B_CBB_A16 23

3D3V_S0 3D3V_PLL_S0 VCC_ASKT_S0 CBB_RESET 23
3D3V_S0 3D3V_S0
3D3V_S0 CBB_WP 23
B_CBB_A23 23
B_CBB_A15 23
B_CBB_A22 23
R930 R931 C640
* C74
* C75
* C76
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
B_CBB_A21 23
10K 0.1uF 0.1uF 0.1uF 0.1uF C638
* C70
* C71
* C639
*
50V, X7R, +/-10%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
10K B_CBB_A20 23
+/-5% R0402 C0402 C0402 C0402 C0402 1nF 0.1uF 0.1uF 0.1uF
R0402 Dummy Dummy C0402 C0402 C0402 C0402 B_CBB_A14 23
Dummy +/-5%
CBB_WAITJ 23
G
Q10 CBB_INPACKJ 23
CBB_WEJ 23
D S CBUS_PMEJ
15,30 B_ICH_PMEJ
B_CBB_A19 23
Dummy CBB_RDY 23
2N7002EPT 3D3V_S0
CBB_BVD1J 23
R940 0 CBB_BVD2J 23
R0402 +/-5%
3D3V_S0 3D3V_PLL_S0
Dummy
C65
* C636
* C637
* C68
* R957 R0402
50V, X7R, +/-10%
50V, X7R, +/-10%

16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
1nF 0.1uF 0.1uF 1nF 0 TECHNOLOGY COPR.

C0402 C0402 C0402 C0402 +/-5%
Dummy
*
C668
10uF * C669
1nF * C670
1uF
Title
10V, Y5V, +80%/-20%

C0805
50V, X7R, +/-10%
C0402
10V, Y5V, +80%/-20%
C0603
ENE_CB851
Document Number Rev
S09 MAINBOARD A
PCMCIA Socket www.hocnghetructuyen.vn
CBUS1
Power switch
88
87
89
90
1 VPP_ASKT_S0 VCC_ASKT_S0
shield
shield
shield
shield
GND
34 GND
35 7 B_CBB_CE1J VPP_ASKT_S0 VCC_ASKT_S0
GND CC/BE0# (CE1*) B_CBB_A8 B_CBB_CE1J 22
68 GND CC/BE1# (A8) 12 B_CBB_A8 22
21 B_CBB_A12 C641 R353 C78 C642
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

CC/BE2# (A12) B_CBB_A12 22
22
22
B_CBB_D3
B_CBB_D4
B_CBB_D3
B_CBB_D4
2
3
(D3) CAD0
(D4) CAD1
CC/BE3# (REG*) 61 CBB_REGJ 22
0.1uF
C0402 * 100K
+/-5% * 0.1uF
C0402 * 4.7uF
C0805
B_CBB_D11 37 63 R0402 Dummy
22 B_CBB_D11 B_CBB_D5 (D11) CAD2 CSTSCHG (BVD1/RI*) CBB_BVD1J 22
22 B_CBB_D5 4 (D5) CAD3 CAUDIO (BVD2/SPKR*) 62 CBB_BVD2J 22
B_CBB_D12 38 67
22 B_CBB_D12 B_CBB_D6 (D12) CAD4 CCD2# (CD2*) B_CBB_CD1J CBB_CD2J 22
22 B_CBB_D6 5 (D6) CAD5 CCD1# (CD1*) 36 B_CBB_CD1J 22
B_CBB_D13 39 57
22 B_CBB_D13 B_CBB_D7 (D13) CAD6 CVS2 B_CBB_VS2J 22
22 B_CBB_D7 6 (D7) CAD7 CVS1 43 B_CBB_VS1J 22
B_CBB_D15 41 47 B_CBB_A18
22 B_CBB_D15 B_CBB_A10 (D15) CAD8 RFU (R2_A18) B_CBB_D14 B_CBB_A18 22
22 B_CBB_A10 8 (A10) CAD9 RFU (R2_D14) 40 B_CBB_D14 22
B_CBB_CE2J 42 32
22 B_CBB_CE2J B_CBB_OEJ (CE2*) CAD10 RFU (R2_D2) B_CBB_D2 22 3D3V_S0
22 B_CBB_OEJ 9 (OE*) CAD11 CRESET# (RESET) 58 CBB_RESET 22
B_CBB_A11 10 33
22 B_CBB_A11 CBB_IORDJ (A11) CAD12 CCLKRUN# (IO16*) B_CBB_A19 CBB_WP 22
22 CBB_IORDJ 44 (IORD*) CAD13 CBLOCK# (A19) 48 B_CBB_A19 22
B_CBB_A9 11 16 CBB_RDY
22 B_CBB_A9 CBB_IOWRJ (A9) CAD14 CINT# (IRQ*) CBB_WEJ CBB_RDY 22
22 CBB_IOWRJ 45 (IOWR*) CAD15 CGNT# (WE*) 15 CBB_WEJ 22
B_CBB_A17 46 60
22 B_CBB_A17 (A17) CAD16 CREQ# (INPACK*) CBB_INPACKJ 22 U18
B_CBB_A24 55 59 C85
* C86
*
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

22 B_CBB_A24 B_CBB_A7 (A24) CAD17 CSERR# (WAIT*) B_CBB_A14 CBB_WAITJ 22 0.1uF 4.7uF
22 B_CBB_A7 22 (A7) CAD18 CPERR# (A14) 14 B_CBB_A14 22 22 VCCD0J 1 VCCD0# SHTDN# 16
B_CBB_A25 56 13 B_CBB_A13 C0402 C0805 2 15
22 B_CBB_A25 (A25) CAD19 CPAR (A13) B_CBB_A13 22 22 VCCD1J VCCD1# VPPD0 VPPD0 22
B_CBB_A6 23 49 B_CBB_A20 Dummy 3 14
22 B_CBB_A6 (A6) CAD20 CSTOP# (A20) B_CBB_A20 22 3.3V VPPD1 VPPD1 22
24 50 B_CBB_A21 4 13 VCC_ASKT_S0
22 B_CBB_A5 (A5) CAD21 CDEVSEL# (A21) B_CBB_A22 B_CBB_A21 22 3.3V VCCOUT
22 B_CBB_A4 25 (A4) CAD22 CTRDY# (A22) 53 B_CBB_A22 22 5 5V VCCOUT 12
26 20 B_CBB_A15 6 11
22 B_CBB_A3 (A3) CAD23 CIRDY# (A15) B_CBB_A23 B_CBB_A15 22 5V VCCOUT VPP_ASKT_S0
22 B_CBB_A2 27 (A2) CAD24 CFRAME# (A23) 54 B_CBB_A23 22 7 GND VPPOUT 10
28 19 B_CBB_A16 8 9
22 B_CBB_A1 (A1) CAD25 CCLK (A16) B_CBB_A16 22 OC# 12V
22 B_CBB_A0 29 (A0) CAD26
30 18 CP2211
22 B_CBB_D0 (D0) CAD27 VPP
22
22
B_CBB_D8
B_CBB_D1
64
31
(D8) CAD28
(D1) CAD29
VPP 52
* C87
10pF
VCCD0J
65 17 VCCD1J
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
22 B_CBB_D9 (D9) CAD30 VCC C0402
66 51 5V_S0
10V, Y5V, +80%/-20%

22 B_CBB_D10 (D10) CAD31 VCC 50V, NPO, +/-5%
CardBus-68-SKT Place close to pin 19. R933 R934 C0805
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
43K 43K
+/-5% +/-5%
R0603 R0603 C88 C89
16V, Y5V, +80%/-20%

4.7uF
* * 0.1uF
C0402
VPP_ASKT_S0
Dummy
C664
16V, Y5V, +80%/-20%

VCC_ASKT_S0
* 0.1uF
C0402
Clock AC termination
33MHz clock for 32-bit
C80 C81 C82 C663
Cardbus card I/F
50V, X7R, +/-10%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
*10uF *10uF * 1nF

* 0.1uF
C0805
Dummy
C0805
Dummy
C0402 C0402
1394
R497 R0402 0 +/-5%
R495 R0402 0 +/-5%
Common Choke 90 Ohm SKT1

22 B_1394_TPA0P 3 4
TPA0+ 4 8
TPA0- TPA+ GND
22 B_1394_TPA0N 2 1 3 TPA- GND 7
TPB0+ 2 6
L36 Dummy TPB0- TPB+ GND
1 TPB- GND 5
VCC_ASKT_S0 Common Choke 90 Ohm
22 B_1394_TPB0P 3 4
1394 CONN
22 B_1394_TPB0N 2 1
R356 R357 R358 R359 L37 Dummy
47K 47K 47K 47K B_CBB_CD1J CBB_CD2J
+/-5% +/-5% +/-5% +/-5%
R0402 R0402 R0402 R0402 R501 R0402 0 +/-5%
Dummy Dummy Dummy Dummy R499 R0402 0 +/-5%
CBB_RESET
* C90
10pF
* C665
10pF
C0402 C0402
B_CBB_CE1J
50V, NPO, +/-5% 50V, NPO, +/-5%
B_CBB_OEJ
B_CBB_CE2J
TECHNOLOGY COPR.
Reserved Layout for Debug use
Title
Document Number
PCMCIA/1394 Rev
S09 MAINBOARD A
5 4 3 2 1
LAN_CLK R993 22R0402 +/-5%
14 LAN_CLK
D
C672 LAN PHY D
47pF
50V, NPO, +/-5% * TXOP
TXOP 25
C0402 U26 TXON
R998 TXON 25
TDP 10
39 110
LAN_RSTSYNC JCLK +/-5%
14 LAN_RSTSYNC 42 JRSTSYNC
LAN_TXD2 45 R0603
14 LAN_TXD2 JTXD2
LAN_TXD1 44 11
14 LAN_TXD1 JTXD1 TDN
LAN_TXD0 43
14 LAN_TXD0 JTXD0
R990 22R0402 +/-5%LAN_RXD2 37
14 R_LAN_RXD2 R991 22R0402 +/-5%LAN_RXD1 JRXD2 RXIP
14 R_LAN_RXD1 35 JRXD1 RDP 15 RXIP 25
R992 22R0402 +/-5%LAN_RXD0 34
14 R_LAN_RXD0 JRXD0
41 R997
ADV10 110
30 ISOL_TCK
28 +/-5%
ISOL_T1 R0603
29 ISOL_EX
26 16 RXIN
TOUT RDN RXIN 25 3D3V_LAN_S5
R999 200 21
R0402 +/-1% TESTEN R368 0
3D3V_S5
1 3D3V_LAN_S5 R0805 +/-5%
VCC_1 BC712 BC713 BC405 BC406 BC407 BC408
VCC_2 25
8 VSS_1
VCCP_1
VCCP_2
36
40
* 4.7uF
*
10V, X5R, +/-10%
4.7uF
*
10V, X5R, +/-10%
0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
13 2 C0805 C0805 C0402 C0402 C0402 C0402

VSS_2 VCCA
18 VSS_3 VCCA2 7
24 VSS_4 VCCT_1 9
48 VSS_5 VCCT_2 12
33 VSSP_1 VCCT_3 14
38 VSSP_2 VCCT_4 17
3 VSSA
6 VSSA2 VCCR_1 19 3D3V_LAN_S5
C C
20 VSSR_1 VCCR_2 23
22 VSSR_2
ACTLED 32 ACTIVE_LED 25
SPDLED 31 100M_LEDJ 25
4 RBIAS10 LILED 27 10M_LEDJ 25
5 RBIAS100
R995 R996
*
619 649 47 LAN_XTAL2 BC398 22pF
+/-1% +/-1% X2 C0402
X1 46
R0603 R0603 50V, NPO, +/-5%
X4
82562GT XTAL-25MHz
*
LAN_XTAL1 BC401 22pF
C0402
50V, NPO, +/-5%
3D3V_LAN_S5
U24
EEP_CS 1 8 BC404
14 EEP_CS CS VCC
EEP_SK
14
14
EEP_SK
EEP_DOUT
EEP_DOUT
2
3
SK
DI
NC
ORG
7
6
* 0.1uF
16V, Y5V, +80%/-20%
EEP_DIN 4 5 GND C0402
14 EEP_DIN DO GND
AT93C46-2.7V
B B
A A
TECHNOLOGY COPR.
Title
LAN_RTL8100C
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
3D3V_LAN_S5
For Modem Cable from MDC

R387
29.4
R388 0 +/-5% R0603 +/-1%
R0603
TIP_RJ11
J1
RJ45RJ11CN1
D 4
3
NC
NC
2
1
Maybe Use FB RING_RJ11 MX0+ 1 13 R389 330
D
TX+/0+ GREEN A3- 10M_LEDJ 24
MX0- 2 12 BC434 R0603 +/-5%
MX1+ TX-/0- A3- A2+ 1nF
Header_1X2 R390 0 +/-5%
3
4
RX+/1+
NC1/2+
A1-
A2+
AMBER
* 50V, X7R, +/-10%
R0603 5 C0402
MX1- NC2/2-
6 RX-/1-
7 NC/3+
Co-Layout with FB 8 11 R391 330
NC4/3- A1- 100M_LEDJ 24
BC435 R0603 +/-5%
1nF
* 50V, X7R, +/-10%
C0402
TIP_RJ11 9 14
RING_RJ11 TIP B1+
10 RING YELLOW B2 15
B3- B1+ 3D3V_LAN_S5_B R392 330 3D3V_LAN_S5
BC436 BC437 BC438 R0603 +/-5%
1.5nF 1.5nF 1nF
* 2kV, X7R, +/-10% * 2kV, X7R, +/-10% *50V, X7R, +/-10%
C1808 C1808 16 C0402
B3-
GND1 17 ACTIVE_LED 24
18 BC439
GND2 1nF
RJ45_RJ11
* 50V, X7R, +/-10%
C0402
C C
1.route on bottom as differential pairs.
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
BC440 6.36mil between pairs and any other trace.
*
0.1uF 7.Must not cross ground moat,except

C0402 L18
16V, X7R, +/-10% 3D3V_LAN_S5 RJ-45 moat. MX1+ 12 1
MX1- 11 RX+ RD+ RXIP 24
RX- RD- 2 RXIN 24
BC441 R395 R0402 75+/-5% 10 3 TF_V_DAC
*
10nF BC442 R396 R0402 75+/-5% RXCT RDCT

9 TXCT TDCT 4
C0402 MX0+ 8
25V, X7R, +/-10% * 0.1uF
C0402 MX0- 7
TX+
TX-
TD+
TD-
5
6
TXOP
TXON
24
24
BC443 16V, X7R, +/-10%
XFMR 350uH
*
1.5nF BC444
C1808 1.5nF BC680
2kV, X7R, +/-10% 2kV, X7R, +/-10% * 0.1uF
*
Dummy C1808 C0402
16V, X7R, +/-10%
B B
3D3V_LAN_S5 0 R373 TF_V_DAC

+/-5% R0402
A A
TECHNOLOGY COPR.
Title
RJ45/RJ11 & Transformer

Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
3D3V_S0
FAE suggest R502 47 ACZ_BTCLK_DJ 28
5
5VA_AUD_S0
Layout close to Pin6 AC97_BTCLK R491 22 AC97_BTCLK_1
U30 R0402 +/-5%
1
R0402 +/-5% 4 R503 47
*Layout* BC448 C671 ACZ_CRSTJ 2 R0402 +/-5%
ACZ_BITCLK 14
+/-5% * *
22pF R400 47pF
5V_S0 40 mil 50V, NPO, C0402 28.7K 50V, NPO, +/-5% NC7SZ08 R517 47 ACZ_BTCLK_MDC 20
3
D +/-1% C0402 Dummy R0402 +/-5% D
R0603 Dummy
U19 Low for external CLK
1 5
SHDN# SET NC for Crystal
BC450 2 5VA_AUD_S0 R970 0
GND
1
1uF
10V, Y5V, +80%/-20% * 3 IN OUT 4
R0402 +/-5%
BC451
BC452
C0402 R403
2
MAX8863 10K
FB8 2 1
** C0402
+/-1%
R0402
C0805
10uF
0.1uF
Dummy
FB L0603 180 Ohm 5VA_AUD_S0
10V, Y5V, +80%/-20% MDM_AUD_IN 20

AUD_AGND R405
3D3V_S0 0 Reserved,Dummy@Crystal
+/-5%
R0603
AUD_AGND
BC453 BC454 SOUND_R SOUND_R 27

10uF
** 0.1uF SOUND_L
48
47
46
45
44
43
42
41
40
39
38
37
SOUND_L 27
10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% BC455 BC456
C0805 C0402 U20 1nF
* * 1nF
SPDIFI/EAPD
SPDIFO
SURR-OUT-R/HP-OUT-R
NC
XTLSEL/ID1#
JD0/GPIO0
AVSS2
AVDD2
MONO-O
LFE-OUT
SURR-OUT-L/HP-OUT-L
CEN-OUT
ALC655 50V, X7R, +/-10% 50V, X7R, +/-10%
C0402 C0402
DUMMY 1 36
C
3 AC_CLK DVDD1 FRONT-OUT-R C
AUD_AGND AUD_AGND
R516 0 X1_AUDIO 2 35
XTL-IN FRONT-OUT-L
*
BC629 22pF R0603 +/-5%

C0402 X2_AUDIO 3 34
XTL-OUT FRONT-MIC1
1
50V, NPO, +/-5%

Dummy X7 4 33
DVSS1 VREFOUT2
X-24D576MHz 28 ACZ_CSDATAOUT 5 32
2
SDATA-OUT FRONT-MIC2/VRDA
*
BC630 22pF
C0402 AC97_BTCLK 6 31 VRDA BC462 1uF
***
50V, NPO, +/-5% Dummy BIT-CLK VRDA/VRAD C0603 10V, Y5V, +80%/-20%
Dummy 7 30 AFLT2 BC463 1nF
DVSS2 AFILT2 C0402 50V, X7R, +/-10%
R406 47 AC97_SDIN 8 29 AFLT1 BC464 1nF
14,28 ACZ_SDATAIN0 R0402 +/-5% SDATA-IN AFILT1 C0402 50V, X7R, +/-10%
9 28 AUD_REF AUD_AGND
DVDD2 VREFOUT
AUD_REF
22 PCI_SPKR BC689 0.47uF R618 47K 28 ACZ_CSYNC 10 27 ALC100_VREF
ALC100_VREF
*
C0603 R0402 +/-5% SYNC VREF

16V, Y5V, +80%/-20% C39 11 RESET# 26 5VA_AUD_S0
28 ACZ_CRSTJ AVSS1
R619 1uF
10V, Y5V, +80%/-20%

JD1/VIDEO-R
JD2/VIDEO-L
15 ICH_SPKR BC690 0.47uF 47K BEEP 1 210V, Y5V, +80%/-20%
12 PC-BEEP 25 BC472
*
AVDD1
C0603 R0402 +/-5% C0402 BC620 BC470
* 10uF
* BC678
LINE-IN-R
LINE-IN-L
CD-GND
16V, Y5V, +80%/-20%
* 10uF
* BC468
* 10uF
* BC471 C0805 0.1uF
PHONE
AUX-R
R620 R621 AUX-L 0.1uF 0.1uF C0402
CD-R
MIC1
MIC2
CD-L
BC691 0.47uF 47K 22K C0805 C0402 C0805 C0402
30 KBC_SPKR
*
C0603 R0402 +/-5% +/-1%

16V, Y5V, +80%/-20% R0402
13
14
15
16
17
18
19
20
21
22
23
24
BC475
20 MDM_AUD_OUT PHONE
*
AUD_AGND
B AUD_AGND 0.1uF C0402 B
16V, Y5V, +80%/-20%
*Layout* BC476
20 mil * 0.1uF
16V, Y5V, +80%/-20%
BC477
C0402 MIC2_1 1uF

MIC2 27
*
Dummy C0603
10V, Y5V, +80%/-20%
AUD_AGND
27 MIC_IN_A BC478 1uF MIC1_1

****
C0603 10V, Y5V, +80%/-20%

19 CD_AUDR CD_AUDR DummyR413
DummyR413 0 CSD_CD_R_2 BC479 1uF Dummy CSD_CD_R_1
R0603 +/-5% C0603 10V, Y5V, +80%/-20%
CD_GND Dummy
DummyR414
R414 0 CSD_GND_2 BC480 1uF Dummy CSD_GND_1
19 CD_GND
R0603 +/-5% C0603 10V, Y5V, +80%/-20%
19 CD_AUDL CD_AUDL Dummy
DummyR415
R415 0 CSD_CD_L_2 BC481 1uF Dummy CSD_CD_L_1
R0603 +/-5% C0603 10V, Y5V, +80%/-20%
If use this circuit,R621 change to 1K
Dummy
3D3V_S0 3D3V_S0
NORMAL:LOW NORMAL:LOW
5
A A
5
1 Dummy
www.hocnghetructuyen.vn 15 ICH_SPKR 1
22
4
PCI_SPKR
2
4 R537
R0402
10K
+/-5%
BEEP
30 KBC_SPKR 2
U28
* BC621
3
U29 Dummy NC7SZ86 0.1uF

3
Dummy NC7SZ86 C0402 TECHNOLOGY COPR.

Dummy
Title
AUD_AGND AUDIO_AC97_ALU655-U
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
5V_OP_S0
3D3V_S0
R422 100K+/-5% GAIN0 5V_S0 5V_OP_S0

R0402
R424
2
R423 100K+/-5% Dummy GAIN1 D31 D32 D33 D34
R0402 SPKR_L+ 3 BAV99 SPKR_L- 3 BAV99 SPKR_R- 3 BAV99 SPKR_R+ 3 BAV99
Dummy Dummy Dummy Dummy BC492
0
R425
1K
R426
1K R0805 * 4.7uF
10V, Y5V, +80%/-20%
1
+/-5% +/-5% +/-5% C0805
GAIN0 GAIN1 AV(inv) INPUT IMPEDANCE R0402 R0402
Dummy
0 0 6 dB 90k AUD_AGND
D D
0 1 10 dB 70k AUD_AGND AUD_AGND
1 0 15.6 dB 45k
1 1 21.6 dB 25k
SOUND_L TC10 1 2100uF SPKR_L+2 R439 22 SPKR_L_2
**
16V, +/-20% cesdh55 R0402 +/-5%
SOUND_L BC622 0.47uF LIN- SOUND_R TC11 1 2100uF SPKR_R+2 R443 22 SPKR_R_2
26 SOUND_L *
C0603 16V, Y5V, +80%/-20% 16V, +/-20% cesdh55 R0402 +/-5%
50V, X7R, +/-10%
50V, X7R, +/-10%

BC508 BC509
R447
22K
R448
22K * 680pF
*
680pF
+/-1% +/-1% C0402 C0402

SOUND_R BC623 0.47uF RIN- R0402 R0402
26 SOUND_R
*
C0603 16V, Y5V, +80%/-20%
AUD_AGND AUD_AGND AUD_AGND AUD_AGND

AUD_REF MIC-In
AUD_AGND MIC_JK1
R429
4.7K
+/-5%
10V, Y5V, +80%/-20%
5
R0402
5V_OP_S0 4
R430
+/-5%
BC499 Place it as close as AMP 3
26 MIC2
* 10uF
* BC500
0.1uF 0 R0603 6
C C0805 C0402 SPKR_L+ BC494 1nF C0402 50V, X7R, +/-10% C
****
R432 MIC1 2
U21 SPKR_L- BC495 1nF C0402 50V, X7R, +/-10% 22K BC502
50V, X7R, +/-10%
50V, X7R, +/-10%

AUD_AGND AUD_AGND 6
15
PVDD
PVDD
ROUT+
ROUT-
18
14
SPKR_R+
SPKR_R- SPKR_R- BC496 1nF C0402 50V, X7R, +/-10%
+/-1%
R0402 * 680pF
C0402 * 1
16 BC503 MIC-IN
5V_OP_S0 VDD SPKR_L+ SPKR_R+ BC498 1nF C0402 50V, X7R, +/-10% 680pF
LOUT+ 4
12 8 SPKR_L- C0402
R433 100K NC LOUT-
R0402 +/-5% BYPASS 10 7 RIN+ BC504 0.47uF
* *
BYPASS RIN+ RIN- C0603 16V, Y5V, +80%/-20% AUD_AGND AUD_AGND AUD_AGND AUD_AGND
RIN- 17
SHUTDOWNJ 19 J7
SHUTDOWN LIN+ BC505 0.47uF SPKR_L+
LIN+ 9 1 NC 3
3
20 5 LIN- C0603 16V, Y5V, +80%/-20% SPKR_L- 2 NC 4

thermal_pad
GND LIN-
13 GND
30 MUTE_EN 2 11 2 GAIN0 Header_1X2
DTC144EUA GND GAIN0 GAIN1
1 GND GAIN1 3
Q15 AUD_AGND
AUD_AGND
1
AUD_AGND TPA6017A2 J4
21
SPKR_R- 1 NC 3
SPKR_R+ 2 NC 4
BYPASS
AUD_AGND Header_1X2
BC491
* 0.47uF
C0603 AUD_AGND
16V, Y5V, +80%/-20%
AUD_AGND
B B
www.hocnghetructuyen.vn 3D3V_S0
5V_OP_S0
SHORT2 R435
1
SHORT
2 100K
+/-5%
R0402 R436
Line-Out
100K
R437 0 AJ_IN +/-5%
R0603 +/-5% 30 AJ_IN R0402 LINEOUT_JK1
Dummy 5
D
4
R438 0 Q17 SPKR_L_2 3
R0603 +/-5%
16V, Y5V, +80%/-20%

Dummy G
2N7002EPT
R440 0 BC507 6
S
R0603
Dummy
+/-5%
* 0.1uF
C0402
SPKR_R_2 2
1
D
R530 AUD_AGND AUD_AGND AUD_AGND JACK_AUDX1 Reverse
AUD_REF
Q23 Q24
+/-5%
4.7K R0402 30 HP_MUTE_EN HP_MUTE_EN G G
AUD_AGND
2N7002EPT 2N7002EPT
S
A A
R431 +/-5% MIC1 AUD_AGND AUD_AGND

26 MIC_IN_A
R531 0 R0603
+/-1%
22K R0402 TECHNOLOGY COPR.
Title
AUD_AGND
AUDIO_AMP
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
3D3V_S0
VOLUME DOWN AND UP BUTTON

VOL_UP_BTN1 R977
100K
1 2 VOL_UPJ_CN R0402
3 4 +/-5%
MP3_BCK_LEDJ
www.hocnghetructuyen.vn 1BT008
D
CN19
TO EC Q14 27
VOL_DN_BTN1 2N7002EPT
30 MP3_BCK_LED MP3_BCK_LEDG 1
1 2 VOL_DOWNJ_CN 2
3 4 REW/SCAN_REWJ_CN 3
S
FW/SCAN_FWJ_CN 4
1BT008 PLAY/PAUSEJ_CN 5
STOP/EJECTJ_CN 6
MP3_PWRBTNJ_CN 7
DJ_SEG0 8
DJ_SEG1 9
DJ_SEG2 10
DJ_SEG3 11
DJ_SEG4 12
DJ_SEG5 13
3D3V_S0 DJ_SEG6 14
15,22,29,30 B_PM_CLKRUNJ
15,22,29,30 INT_SERIRQ DJ_SEG7 15
14 LPC_LDRQ1J DJ_SEG8 16
3D3V_S0 C40 C41 C42 C43 DJ_SEG9 17
14,30 B_LPC_LFRAMEJ
RN80
3 CLK33_AUDIODJ
R637 15,22,29 PCIRST1J
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
COM0
18
19
*
1
3
2
4 VOL_UPJ
33
+/-5%
C0402 C0402 C0402 C0402 COM1 20
21
5 6 VOL_DOWNJ R0402 3D3V_S0 R228 330
R0603 +/-5% 22
7 8 MP3_MEDIASEL Dummy EMI MP3_BCK_LEDJ 23
C44
10
11
12
17
29
41
24
2
9
5
10K 8P4R0603 +/-5%
RN82 * 33pF
50V, NPO, +/-5%
U40
SEG0
*
1
RN81
2 DJ_SEG0
25
26
LCLK
LRESET#
LFRAME#
LDRQ#
IRQ
CLKRUN#
VCC
VCC
VCC
VCC
*1
3
2
4
FW/SCAN_FWJ
REW/SCAN_REWJ
C0603
Dummy
SEG3
SEG2
3
5
4
6
DJ_SEG3
DJ_SEG2 28
5 6 STOP/EJECTJ SEG1 7 8 DJ_SEG1
7 8 PLAY/PAUSEJ B_LPC_LAD0 7 43 SEG0
14,30 B_LPC_LAD0 B_LPC_LAD1 LAD0 SEG0 SEG1 100 +/-5%
14,30 B_LPC_LAD1 6 LAD1 SEG1 39 AUDIO-CONN26
10K 8P4R0603 +/-5% B_LPC_LAD2 4 40 SEG2 8P4R0603
14,30 B_LPC_LAD2 B_LPC_LAD3 LAD2 SEG2 SEG3 RN83
14,30 B_LPC_LAD3 3 LAD3 SEG3 42
38 SEG4 SEG4
*
1 2 DJ_SEG4
14,20 ACZ_RSTJ
26 ACZ_CRSTJ
13
14
HRST#
CRST#
SEG4
SEG5
SEG6
35
36
37
SEG5
SEG6
SEG7
SEG7
SEG6
SEG5
3
5
7
4
6
8
DJ_SEG7
DJ_SEG6
DJ_SEG5
AudioDJ Connector
SEG7 SEG8
14,20 ACZ_SYNC 15 HSYNC SEG8 48
16 45 SEG9 100 +/-5%
26 ACZ_CSYNC CSYNC SEG9 8P4R0603
SEG10 46
14,26 ACZ_SDATAIN0 18 CSDATA_IN SEG11 47
22 SEG8 R973 100 DJ_SEG8
26 ACZ_CSDATAOUT CSDATA_OUT COM0 R0402 +/-5%
33
REW/SCAN_REW#
COM0 COM1
14,20 ACZ_SDATAOUT 21 HSDATA_OUT COM1 34
FW/SCAN_FW#
19 SEG9 R974 100 DJ_SEG9
STOP/EJECT#
PLAT/PAUSE#
26 ACZ_BTCLK_DJ
VOL_DOWN#
CBIT_CLK R0402 +/-5% ESD
MEDIA_SEL
VOL_UP#
CLK32K
GND
GND
GND
GND
RN85 VOL_UPJ_CN C45 470pF
* * * * * * *
VOL_UPJ
VOL_DOWNJ
*
1
3
2
4
VOL_UPJ_CN
VOL_DOWNJ_CN OZ263T
C0402 Dummy
8
20
32
44
30
28
27
26
23
24
25
31
STOP/EJECTJ 5 6 STOP/EJECTJ_CN VOL_DOWNJ_CN C46 470pF
PLAY/PAUSEJ 7 8 PLAY/PAUSEJ_CN C0402 Dummy
R638
FW/SCAN_FWJ_CN 10K
8P4R0603 470 +/-5% REW/SCAN_REWJ_CN NOTUS_CLK R0402 NOTUS_CLK_RC STOP/EJECTJ_CN C47 470pF
470 R0402 MP3_MEDIASEL C0402 Dummy
FW/SCAN_FWJ R639 +/-5%
REW/SCAN_REWJ 3D3V_S0 PLAY/PAUSEJ_CN C48 470pF
VOL_DOWNJ C0402 Dummy
R640 470 R0402 VOL_UPJ U41
STOP/EJECTJ 5 1 FW/SCAN_FWJ_CN C49 470pF
PLAY/PAUSEJ C50 VCC NC C0402 Dummy
A 2
FW/SCAN_FWJ
REW/SCAN_REWJ * 0.1uF 4 Y GND 3
*
C52
4.7nF REW/SCAN_REWJ_CN C51 470pF
C0402 NC7SZ14 50V, X7R, +/-10% C0402 Dummy
C0603
MP3_PWRBTNJ_CN C53 470pF
To EC (Check) C0402 Dummy
VOL_DOWNJ
VOL_UPJ VOL_DOWNJ 30
STOP/EJECTJ VOL_UPJ 30
PLAY/PAUSEJ STOP/EJECTJ 30
FW/SCAN_FWJ PLAY/PAUSEJ 30
REW/SCAN_REWJ FW/SCAN_FWJ 30
REW/SCAN_REWJ 30
MP3 POWER BUTTON
3D3V_S0 3D3V_S0
For Non-MP3 Model 3D3V_AUX_S5
PUT INSIDE OZ263
R641 R642
10K 10K R643
R644 0 R0402 +/-5% +/-5% +/-5% 10K
ACZ_SDATAOUT ACZ_CSDATAOUT R0402 R0402 +/-5%
Dummy R0402
R645 0 R0402 +/-5% COM1 COM0 R646 470
ACZ_SYNC ACZ_CSYNC MP3_PWRBTNJ_CN MP3_PWRBTNJ 30
Dummy R647 R648 C54
ACZ_RSTJ
R649 0 R0402 +/-5%
ACZ_CRSTJ
10K
+/-5%
10K
+/-5%
+/-5% R0402
* 0.1uF
Dummy R0402 R0402 C0402

TECHNOLOGY COPR.
Title
Document Number
OZ263T Rev
S09 MAINBOARD A
5 4 3 2 1
15,22 B_PCI_AD[31..0]
127
MINI1
D 125 D
1 2
3 4
5 6
7 8
9 10 PIN 3-16 : LAN RESERVE
13 802.11_ACT 11 12 802.11_LINK 13
30 RF_KILLJ 13 14
15 16
R419 INT_PIRQCJ 17 18 5V_S0
10K 19 20 INT_PIRQCJ 15
3D3V_S0
+/-5% 1 21 22
R0402 TP83 23 24
3 PCLK_MINI 25 26 PCIRST1J 15,22,28
27 28 3D3V_S0
15 PCI_REQJ1 29 30 PCI_GNTJ1 15
31 32
R420 B_PCI_AD31 33 34 CBUS_PMEJ 22
33 B_PCI_AD29 35 36
+/-5% 37 38 B_PCI_AD30
R0402 B_PCI_AD27 39 40
Dummy B_PCI_AD25 41 42 B_PCI_AD28
43 44 B_PCI_AD26
15,22 B_PCI_C/BEJ3 B_PCI_C/BEJ3 45 46 B_PCI_AD24
BC482 B_PCI_AD23 47 48 MOD_IDSEL R421 10 B_PCI_AD21
33pF R0402 +/-5%
C
* 50V, NPO, +/-5% B_PCI_AD21
49
51
50
52 B_PCI_AD22 C
C0603 B_PCI_AD19 53 54 B_PCI_AD20
Dummy 55 56 B_PCI_PAR 15,22
B_PCI_AD17 57 58 B_PCI_AD18
15,22 B_PCI_C/BEJ2 B_PCI_C/BEJ2 59 60 B_PCI_AD16
15,22 B_PCI_IRDYJ 61 62
63 64 B_PCI_FRAMEJ 15,22
B_PM_CLKRUNJ 65 66 B_PCI_TRDYJ 15,22
www.hocnghetructuyen.vn 15,22,28,30 B_PM_CLKRUNJ
15,22 B_PCI_SERRJ 67
69
68
70
B_PCI_STOPJ 15,22
15,22 B_PCI_PERRJ 71 72 B_PCI_DEVSELJ 15,22

15,22 B_PCI_C/BEJ1 B_PCI_C/BEJ1 73 74
77 78 B_PCI_AD13
B_PCI_AD10 81 82
83 84 B_PCI_AD9
B_PCI_AD8 85 86 B_PCI_C/BEJ0 B_PCI_C/BEJ0 15,22
B_PCI_AD7 87 88
89 90 B_PCI_AD6
93 94 B_PCI_AD2
5V_S0 97 98
B_PCI_AD1 99 100 INT_SERIRQ 15,22,28,30
101 102
103 104
B 105 106 B
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
3D3V_S0
123 124
126
BC483 BC484 BC485 BC486 BC487 BC488 BC489
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 4.7uF
* * * * * * * Mini-PCI
128
C0402 C0402 C0402 C0402 C0402 C0402 10V, Y5V, +80%/-20%

Dummy Dummy Dummy Dummy Dummy Dummy C0805
Dummy
5V_S0
A BC490 A
4.7uF
* 10V, Y5V, +80%/-20%
C0805
Dummy
TECHNOLOGY COPR.
Title
MINI-PCI
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
HW STRAP OPTION
3D3V_AUX_S5
3D3V_AUX_S5
R454 R455 R456

3D3V_AUX_S5 47K 47K 47K
+/-5% +/-5% +/-5%
U23 R0402 R0402 R0402
www.hocnghetructuyen.vn L19 A4/TRIS A5/SHBM GPIO20
Power
161 VCCBAT VCC 16
BC513 17
VCC 34
45
1 2
FB L0805 100 Ohm
A4 A5 GPIO20
GND VCC
D
0.1uF
16V, Y5V, +80%/-20% * 35
46
GND
GND
VCC
VCC
123
136 BC514 BC515 TC12 S0_EN S3_EN A1/ENV1 D
C0402 122 GND VCC 157
*1uF
*
0.1uF
10V, Y5V, +80%/-20% 10V, X7R, +/-10%
10uF
*
10V, Y5V, +80%/-20%
Power
137 GND VCC 166
167 C0603 C0402 C0805 R459 R460 R461
GND 4.7K 4.7K 4.7K
159 95 G9
BATGND VCCA +/-5% +/-5% +/-5%
AGND 96 1 2
Close-Power-Gap-3050 R0402 R0402 R0402
Expanded I/O
7 85 REW/SCAN_REWJ REW/SCAN_REWJ 28
15,22,28,29 INT_SERIRQ SERIRQ XIO8CS#/GPIO18
LPC Interface
14,28 B_LPC_LFRAMEJ 9 LFRAME# XIO9CS#/GPIO19 86 CHG_LEDJ 13
15 91 CHG_LED2J
14,28 B_LPC_LAD0 LAD0 XIOACS#/GPIO1A STOP/EJECTJ CHG_LED2J 13
14,28 B_LPC_LAD1 14
13
LAD1 XIOBCS#/GPIO1B 92
93 PWR_LED
STOP/EJECTJ 28 GPIO05 GPIO06 A1
14,28 B_LPC_LAD2 LAD2 XIOCCS#/GPIO1C VOL_UPJ PWR_LED 13 3D3V_AUX_S5
14,28 B_LPC_LAD3 10 LAD3 XIODCS#/GPIO1D 94 VOL_UPJ 28
18 97 VOL_DOWNJ VOL_DOWNJ 28
3 PCLK_KBC LCLK XIOECS#/GPIO1E
15,22,28,29 B_PM_CLKRUNJ 25 CLKRUN#/GPIO0C XIOFCS#/GPIO1F 98 ANTI_THEFT_LED 13 RN61 4.7K
PCLK_KBC 24
15 PM_SUS_STATJ GPIO0B
7,15,17 PLT_RST1J 165

A0 124
125
A0/ENV0
A1/ENV1
KBC_D3 1
KBC_D2 3
* 2
4
R457 R458 LRST#/GPIO2C A1 A2/BADDR0 KBC_D1 5
14H_RCINJ 6 KBRST#/GPIO03 A2 126 6
33 10K 5 127 A3/BADDR1 KBC_D0 7 8
+/-5% Pull-Down resistor required +/-5% 14 H_A20GATE
31
GA20/GPIO02 A3
128 A4/TRIS Dummy
R0402 to avoid leakage current R0402 15 SMC_RUNTIME_SCIJ ECSCI# A4 A5/SHBM +/-5% 8P4R0603
19 ECRST# A5 131
BC516 Dummy 132 A6 RN62 4.7K
A6
*
50V, NPO, +/-5%
* 33pF
C0603 3D3V_AUX_S5
31 KROW1
KROW1 71 KSI0/GPIK0
A7
A8
133
143
A7
A8
KBC_D7 1
KBC_D6 3
2
4
Dummy R462 47K ECRSTJ KROW2 72 142 A9 KBC_D5 5 6
31 KROW2 KROW3 73
KSI1/GPIK1 A9
135 A10 KBC_D4 7 8
DUAL LAYOUT 3D3V_AUX_S5
R0402 +/-5% BC517 31 KROW3 KROW4 KSI2/GPIK2 A10 A11
31 KROW4 74 KSI3/GPIK3 A11 134
* 0.1uF
25V, Y5V, +80%/-20%31 KROW5
KROW5 77 KSI4/GPIK4 A12 130 A12 Dummy +/-5% 8P4R0603
1MB Flash
Internal KeyBoard
KROW6 78 129 A13
X-BUS Interface
C0603 31 KROW6 KROW7 KSI5/GPIK5 A13 A14 U66
31 KROW7 79 KSI6/GPIK6 A14 121
KROW8 80 120 A15 A16 1 40 A17
C 31 KROW8 KSI7/GPIK7 A15 A16 A15 A16 A17 GND C
POWER-ON RESET A16 113
A17 A14
2 A15 VSS2 39
31 KCOL1 49 KSO0/GPOK0 A17 112 3 A14 NC5 38
Example Only 50 104 A18 A13 4 37 A19
31 KCOL2 KSO1/GPOK1 A18 A19 A12 A13 A19 A10
31 KCOL3 51 KSO2/GPOK2 A19 103 5 A12 A10 36
52 108 A11 6 35 KBC_D7
3D3V_S5 31 KCOL4 KSO3/GPOK3 A20/GPIO23 A9 A11 DQ7 KBC_D6
31 KCOL5 53 KSO4/GPOK4 7 A9 DQ6 34
56 138 KBC_D0 A8 8 33 KBC_D5
31 KCOL6 KSO5/GPOK5 D0 KBC_D1 KBCBIOS_FWRJ A8 DQ5 KBC_D4
31 KCOL7 57 KSO6/GPOK6 D1 139 9 WE# DQ4 32
R463 58 140 KBC_D2 10 31
10K 31 KCOL8 KSO7/GPOK7 D2 KBC_D3 NC1 VDD2
31 KCOL9 59 KSO8/GPOK8 D3 141 11 NC2 VDD1 30
+/-5% 60 144 KBC_D4 12 29 C32
31 KCOL10 KSO9/GPOK9 D4 NC3 NC4
R0402
3D3V_AUX_S5 31
31
KCOL11
KCOL12
61
64
KSO10/GPOK10
KSO11/GPOK11
D5
D6
145
146
KBC_D5
KBC_D6
A18
A7
13
14
A18
A7
DQ3
DQ2
28
27
KBC_D3
KBC_D2 * 0.1uF
16V, Y5V, +80%/-20%
COVERUP 65 147 KBC_D7 A6 15 26 KBC_D1 C0402
31 KCOL13 KSO12/GPOK12 D7 KBCBIOS_FRDJ A5/SHBM A6 DQ1 KBC_D0 Dummy
31 KCOL14 66 KSO13/GPOK13 RD# 150 16 A5 DQ0 25
R464 67 151 KBCBIOS_FWRJ A4/TRIS 17 24 KBCBIOS_FRDJ
10K 31 KCOL15 KSO14/GPOK14 WR# KBCBIOS_IOCSJ 1 A3/BADDR1 A4 OE# GND
31 KCOL16 68 KSO15/GPOK15 IOCS# 152 18 A3 VSS1 23
+/-5% KCOL17 153 173 KBCBIOS_MEMCSJ TP88 A2/BADDR0 19 22 KBCBIOS_MEMCSJ
R0402 31 KCOL17 KCOL18 KSO16/GPOK16 MEMCS# A1/ENV1 A2 CE# A0/ENV0
R465 1 154 KSO17/GPOK17 20 A1 A0 21
TP90 163
SCL1 B_KBC_SCL1 13,18
SMbus
15,22 B_ICH_PMEJ 2 GPWU0 SDA1 164 B_KBC_DAT1 13,18 SST39LF080
28 MP3_PWRBTNJ 26 GPWU1 SCL2 169 BAT_KBC_SCL1 32,35
0 29 170
13 ANTI_THEFT_ARMJ GPWU2 SDA2 BAT_KBC_DAT1 32,35
5V_S0 R0603 30
GPW
35 AC_IN GPWU3
+/-5% 44 32
13 COVERUP GPWU4 PWM0/GPOW0 BRIGHTNESS_PWM 13
R466 R467 R468 R469 Dummy 76 33
41 EC_PWRBTNJ GPWU5 PWM1/GPOW1 KBC_SPKR 26
10K 10K 10K 10K 172 36
+/-5% +/-5% +/-5% +/-5% GPWU6/TIN1 PWM2/GPOW2/FAN1PWM ALARM_ENABLE 32 3D3V_AUX_S5
176 GPWU7/TIN2/FANFB2 PWM3/GPOW3 37
R0402 R0402 R0402 R0402 38
PWD
TP92 PSCLK1 PWM4/GPOW4
1 110 PSCLK1 PWM5/GPOW5 39
TP93 1 PSDAT1 111 40 R470 C30
PSDAT1 PWM6/GPOW6
*
PS2
TP94 1 PSCLK2 114 43 100K 0.1uF
B TP95 1 PSDAT2 115
PSCLK2 PWM7/GPOW7/FAN2PWM +/-5% 16V, Y5V, +80%/-20% 512KB Flash B
PSDAT2 R0402 C0402
31 TCLK 116 PSCLK3
31 TDATA 117 PSDAT3 FANFB1/TOUT1/GPIO2E 171
35 BTSENSE 81 U25
BAT_TYPE AD0/GPIAD0 KBC_D0
35 BAT_TYPE 82 AD1/GPIAD1 32 VCC O0 13
1 BT_INJ 83
A to D A0/ENV0 12 14 KBC_D1
TP96 AD2/GPIAD2 A1/ENV1 A0 O1 KBC_D2
84 54 11 15
Restore Button 35 IOUT
87
AD3/GPIAD3
AD4/GPIAD4
CAPLOCK#/GPIO11
FNLOCK#/GPIO12 55
CAPSJ 13 A2/BADDR0 10
A1
A2
O2
O3 17 KBC_D3
88 41 A3/BADDR1 9 18 KBC_D4
AD5/GPIAD5 SCROLLLOCK#/GPIO0F A4/TRIS A3 O4 KBC_D5
32 ANTI_THEFT_XOUT 89 AD6/GPIAD6 NUMLOCK#/GPIO0A 23 NUMJ 13 8 A4 O5 19
BC523 KROW2 90 A5/SHBM 7 20 KBC_D6
32 ANTI_THEFT_YOUT AD7/GPIAD7 A5 O6
* 10nF BC521 10nF C0402 Dummy 28 99 A6 6 21 KBC_D7
**
BTN2 Dummy 25V, X7R, +/-10% 25V, X7R, +/-10% BC522 10nF C0402 Dummy GPIO0E DA0/GPODA0 A7 A6 O7
27 GPIO0D DA1/GPODA1 100 5 A7
C0402 175 101 A8 27
BC524 KCOL17 27 HP_MUTE_EN TOUT2/GPIO2F DA2/GPODA2 A9 A8
D to A
2 1 27 AJ_IN 8 GPIO04 DA3/GPODA3 102 26 A9

4
5 GND
3
* 10nF
25V, X7R, +/-10% 17,20,36,37,38,40 S0_EN
38 S3_EN
11
12
GPIO05/FAN3PWM
GPIO06/FANFB3
DA4/GPODA4
DA5/GPODA5
1
42
VSET
ISET
35
35
A10
A11
23
25
A10
A11
Dummy C0402 20 47 A12 4
15 PM_SLP_S3J_ICH GPIO07 DA6/GPODA6 CELLS 35 A12
Tactile Switch 21 174 A13 28
15 PM_SLP_S4J_ICH GPIO08 DA7/GPODA7 A13
22 A14 29
37 S0_EN_D GPIO09 A15 A14
Debug
GPIO
18 S5_EN 48 GPIO10 E51IT0/GPIO00 3 PWRBTNJ_ICH 15 3 A15

62 4 A16 2
29 RF_KILLJ GPIO13 E51IT1/GPIO01 MUTE_EN 27 A17 A16
13 EC_BLON 63 GPIO14 E51RXD/GPIO21/ISPCLK 106 1 30 A17
R472 0 BL_ONF_NB_VGA 69 107 1 TP98 For External Debug KBCBIOS_MEMCSJ 22
7 GMCH_BL_ON GPIO15 E51TXD/GPIO22/ISPDAT CE
R0402 +/-5% 28 PLAY/PAUSEJ PLAY/PAUSEJ 70 105 GPIO20 1 TP99 KBCBIOS_FRDJ 24 U34
FW/SCAN_FWJ GPIO16 E51CS#/GPIO20/ISPEN_TP TP101 A18 OE
28 FW/SCAN_FWJ 75 GPIO17 1 VPP
109 KBCBIOS_FWRJ 31
28 MP3_BCK_LED GPIO24 X1_KBC PGM
14 RTC_SENSEJ 118 GPIO25 XCLKO 160 16 GND
119
User Programing Button 15 SMC_WAKE_SCIJ_R GPIO26 X6 SST39VF040
Clock
148 PLCC-32-SKT
15 SMC_EXTSMIJ_R GPIO27
32 M_ENABLEJ 149 GPIO28
155 158 X2_KBC 1 4
A 20 MDC_RINGJ GPIO29 XCLKI A
BC525 KROW1 156
33 AD_OFF GPIO2A
BTN1 Dummy * 10nF
25V, X7R, +/-10% 35 CHARONJ/OFF 162
168
GPIO2B
GPIO2D
BC519
10pF
* * BC520
10pF
C0402 C0402 2 3 C0402
2 1 BC526 KCOL17 R476
50V, NPO, +/-5% 50V, NPO, +/-5%
4
5 GND
3
* 10nF
25V, X7R, +/-10%
10K
+/-5%
KB3910
XTAL-32.768kHz
Dummy C0402 R0402 TECHNOLOGY COPR.
Tactile Switch
Title
KBC_ENE3910
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
Internal KeyBoard Connector

ENABLE/DISABLE TOUCH PAD BUTTON
KB1
D 27 27 D
KROW3 26
KROW3 30 KCOL1 26
30 KCOL1 25 25
BTN3 KCOL2 24
30 KCOL2 KCOL3 24
30 KCOL3 23 23
2 1 KCOL17 KROW8 22
KCOL17 30 30 KROW8 KROW7 22
4 3 30 KROW7 21 21
5 KROW6 20
GND 30 KROW6 KROW5 20
30 KROW5 19 19
Tactile Switch KCOL4 18
30 KCOL4 KCOL5 18
30 KCOL5 17 17
KROW4 16
30 KROW4 KROW3 16
30 KROW3 15 15
KROW2 14
30 KROW2 KROW1 14
30 KROW1 13 13
KCOL6 12
30 KCOL6 KCOL7 12
30 KCOL7 11 11
KCOL8 10
30 KCOL8 KCOL9 10
30 KCOL9 9 9
KCOL10 8
30 KCOL10 KCOL11 8
30 KCOL11 7 7
KCOL12 6
30
30
KCOL12
KCOL13
KCOL13
KCOL14
5
4
6
5 www.hocnghetructuyen.vn
TouchPad Connector For Module TM42PU-351 (UP Orientation) 30
30
KCOL14
KCOL15
KCOL15
KCOL16
3
4
3
10V, Y5V, +80%/-20%

30 KCOL16 2 2
1 1
5V_S0 5V_S0
C C
16V, Y5V, +80%/-20% FPC CONN_25P_R/A
C26 C27
R485 R486 0.1uF 1uF
10K 10K
* * TP_CN1
R0402 R0402 C0402 C0603 1
+/-5% +/-5% 2
TDATA 3
30 TDATA
4
TCLK 5
30 TCLK
6 13
7 14
8
LEFT 9
C28 C29 10
33pF 33pF
50V, NPO, +/-5% * * 50V, NPO, +/-5% RIGHT
11
12
C0603 C0603
TOUCH-PAD-12Pin-LF
B B
SW_Right1 SW_Left1
2 1 RIGHT 2 1 LEFT
4 3 4 3
5 5 Dummy
TouchPad Connector For Module TM51-389(Up Orientation) GND GND
3
Dummy
3
Tactile Switch Tactile Switch 1 2
1 2
D39
5V_S0 D40 BAV99
DUAL LAYOUT WITH ABOVE BAV99 5V_S0
BC676
0.1uF
C31 TP_CN2 * 16V, Y5V, +80%/-20%
0.1uF C0402
16V, Y5V, +80%/-20% * 12 Dummy
Dummy C0402 11
TDATA 10
TCLK 9
8
7 14
6 13
5
4
A LEFT 3 A
RIGHT 2
1
TOUCH-PAD-12Pin-LF
TECHNOLOGY COPR.
Title
KBC CONN
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
D D
3D3V_S5 3D3V_S5
From GPIO, This GPIO

must be tied to stand by BC707
R434 0.1uF
3.3V power supply!
100K
* 16V, Y5V, +80%/-20%
R0402 U64 C0402
8
D25 +/-5% To EC ADC input
Vcc
30 M_ENABLEJ 2 1 1 7 R963 10K +/-5% R0402 ANTI_THEFT_XOUT 30 or to
PD Xout R964 10K +/-5% R0402
2 6 ANTI_THEFT_YOUT 30 microcontroller
CH501H-40 TP Yout
3 5 ADC input!
NC1
COM NC2
Low for enable MXA6999MP BC708 BC709
4
1uF 1uF
10V, X5R, +/-10% ** 10V, X5R, +/-10%
C0603 C0603
C C
5V_S5
R17
0
+/-5%
R0603 BUZZER1
2
1
D30
CH501H-40
2 EEPROM 3D3V_S5
Dummy
Buzzer U65
1
R3 0 R0402 +/-5%
1 A0 8 16V, Y5V, +80%/-20%
R4 0 R0402 +/-5% VCC BC710 0.1uF
2 A1 7
D
*
R5 0 R0402 +/-5% WP C0402
3 A2 SCL 6 BAT_KBC_SCL1 30,35
Q22 4 VSS 5
SDA BAT_KBC_DAT1 30,35
30 ALARM_ENABLE ALARM_ENABLE G AT24C02N

2N7002EPT
S
B B
Reserved for debug
A A
TECHNOLOGY COPR.
Title
ANTITHEFT
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
D Board To Board CONN D
BTBCN2
1 1 2 2
B_USB_PN7 3 4
15 B_USB_PN7 3 4 GMCH_TV_LUMA 7
B_USB_PP7 5 6
15 B_USB_PP7 5 6
7 7 8 8 GMCH_TV_COM 7
5V_S0 9 9 10 10
11 11 12 12 GMCH_TV_CRMA 7
13 13 14 14
15 USB_OCJ7 15 16 ADIN
15 16
30 AD_OFF 17 17 18 18
19 19 20 20
C ADIN 21 22 C
21 22
23 23 24 24
25 25 26 26
27 27 28 28
29 29 30 30
31 H1 H2 32
0.6P BTB_High Speed 30P
B B
A TECHNOLOGY COPR. A
Title
Board To Board CONN

Document Number Rev
S09 MAINBOARD A
Date: Wednesday, March 16, 2005 Sheet 33 of 45
5 4 3 2 1
5 4 3 2 1
Power design diagram

5V_S0 5V_S0
S0_EN 6365
AD+ 6425 5V_S5 5V_S5
D D
SHUTDOWN_S5 60
CHARGER 1D5V_S5 1D5V_S5
1D5V_S5PGD 270
4308.15 3D3V_S5 3D3V_S5
BAT+ DCBATOUT SHUTDOWN_S5 780
3D3V_S0 3D3V_S0
S0_EN 2716 LDO 2D5V_S0 2D5V_S0
C
5V_AUX_S5 152.15 C
LDO 20 3D3V_LAN_S5 3D3V_LAN_S5
3D3V_AUX_S5 390
LDO 34
6854 1D05V_S0 1D05V_S0

S0_EN 6854
S0_EN_D
B 8974 1D5V_S0 1D5V_S0 B
S0_EN 8974
S0_EN_D
12310 1D8V_S3 1D8V_S3
S3_EN 8310
0D9V_S0 0D9V_S0
S0_EN 4000
A
27000 VCC_CORE_S0 VCC_CORE_S0 A
VCC_PWRGD 27000
TECHNOLOGY COPR.
Title
Power design diagram

Document Number Rev
S09 MAINBOARD A
Date: Saturday, March 05, 2005 Sheet 34 of 45
5 4 3 2 1
A B C D E
MBATA+
PR1 0 could change it to FB
R0805 +/-5% (FB L0805 30 Ohm, 4A) BAT1
1 Pack+
PR2 0 BATCN_MBATA+ 2
R0805 +/-5% Pack+
PR6 0 3
R0805 +/-5% CNT1
4 CNT2
PC1 PC2 PR5 0 R0402 +/-5% BATCN_SMB_CLK
0.1uF * * 47pF * PC3 30,32 BAT_KBC_SCL1
30,32 BAT_KBC_DAT1
PR4 0 R0402 +/-5% BATCN_SMB_DAT
5
6
CLK
DATA
50V, Y5V, +80%/-20% 50V, NPO, +/-5% 1nF PR3 0 R0402 +/-5% BATCN_SMB_PRESJ 7
4 C0603 C0402 50V, NPO, +/-5% 30 BAT_TYPE THRM 4
C0603 PR14 8
PR13 47K PBC1 Pack-
10K +/-5% * 0.1uF
9 Pack-
+/-5% R0402 C0402 C14454-109A1
R0402 16V, Y5V, +80%/-20% BATTERY CONNECTOR
Dummy
PR157 PR9 Pack+ Battery Pack positive terminal
3
0 10K PR10 Pack+ Battery Pack positive terminal
R0402 2 1 +/-5% 2 1 PR16 2 1 10K
+/-5% R0402 10K +/-5% CNT1 NC
BT+BAT PD1 PD2 +/-5% PD3 R0402 CNT2 NC
BTSENSE 30 BAV99 BAV99 R0402 BAV99 CLK Clock signal
PR20 Dummy Dummy Dummy
www.hocnghetructuyen.vn PR19 10K PC4 DATA
THRM
Data Signal
Thermal indicator
10K
+/-5%
+/-5%
R0402 * 0.1uF
16V, Y5V, +80%/-20%
3D3V_S5 3D3V_S5 3D3V_S5 3D3V_S5 3D3V_S5 3D3V_S5
Pack- Battery Pack negative terminal
R0402 C0402 Pack- Battery Pack negative terminal
Dummy
DCBATOUT DCBATOUT
3 3
PC5
ADIN ADIN2
* 10uF
4
3
2
1
PR21 25V, Y5V, +80%/-20%
10K S PQ1 C1210
PD4 R0402 G SI4435BDY
SSM54PT +/-5%
D
1 2
PQ2
5
6
7
8
PR22 SI4435BDY
ADIN 33m PD5
r2512h9 SSM54PT 1 8
D
+/-1% 2 7 PL1 6.8uH
*
ADIN ADIN1 1 2 DCBATOUT 3 6 CHARGEBAT1 CHARGEBAT2 MBATA+
G
4 5
2
OZ860_HDR1
PR23 PC8
25V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%
PR24 PR25 33m 0.1uF

* * *
25V, Y5V, +80%/-20%
PC10
PC11
10uF
C0805
C1206
C1210
4.7uF
10 10
* * * PD6 PC6 r2512h9 25V, Y5V, +80%/-20%
PC9
1uF
PR27 +/-5% +/-5% SSM54PT 10uF PC7 OZ860_ICHP PR26 10 +/-1% C0603
PC12
C0603
0.1uF
22K R0402 R0402 25V, Y5V, +80%/-20% 10uF R0402 +/-5%

*
1
+/-5% C1210 25V, Y5V, +80%/-20% PC14
r0402h4 PR28 C1210 2.2uF
0 *C1206
16V, Y5V, +80%/-20%
*
R0603 25V, Y5V, +80%/-20%

2
PC13 +/-5% MBATA+
Note: 2
PC15
C0402
2.2uF CELLS=Hi-Z for 2 cells

0.1uF
C1206 OZ860_IACM PR30 PR158

CELLS= Low for 3 cells
25V, Y5V, +80%/-20%
OZ860_IACP AGND_OZ860 * 10K
+/-5%
0
R0402 CELLS= High for 4 cells
PU1 R0402 +/-5%
PR29 10K OZ860_CELLS 1 OZ860_ISET0 ISET1
30 CELLS +/-5% R0402 CELLS ISET 16 ISET All30 the decupling close to the
PR31 10K +/-5% R0402 OZ860_IOUT 2 15 OZ860_IACP PQ3 PR159 active pins and ground: ref, lv,
D
IOUT Dummy IOUT IACP PC16 0
PR32 10K OZ860_VSET 3 VSET IACM 14 OZ860_IACM * 0.1uF 2N7002EPT R0402 vset, iset, comp and gnd
30 VSET +/-5% R0402 16V, Y5V, +80%/-20% PR226 +/-5%
*
PC17 0.22uF OZ860_COMP1 PR33 150 OZ860_COMP 4 13 MBATA+ C0402 10K G CHARG CHARONJ/OFF 30
C0603 16V, Y5V, +80%/-20% +/-5% R0402 COMP VBATT +/-5%
16V, Y5V, +80%/-20%
OZ860_ICHP AGND_OZ860 R0603

* 5 12
S
GND ICHP
PC18
C0402
0.1uF
Dummy
*
PR34 PC19 10uF OZ860_LV 6 11 OZ860_ACAV PR36

10V, Y5V, +80%/-20% C0805 LV ACAV AC_IN 30 200K
10K
16V, Y5V, +80%/-20%
7 10 OZ860_CHIGH PR35 AD in use R0402

+/-5% REF3D3V REF CHIGH
GNDP
10K +/-5%
R0402 OZ860_HDR +/-5%
* 8 VAC HDR 9
R0402
PC20
C0402
0.1uF
AGND_OZ860 AGND_OZ860 AGND_OZ860

Dummy
25V, Y5V, +80%/-20%
17
OZ8604LN
1 PC21
* 1
10uF
PC22
C1210
2.2uF
10V, Y5V, +80%/-20% *
*
C0603 PJ1
TECHNOLOGY COPR.
PC23 1 2
0.47uF Title
25V, Y5V, +80%/-20% JUMPER1 Charger
AGND_OZ860 AGND_OZ860 AGND_OZ860 AGND_OZ860 AGND_OZ860 AGND_OZ860 AGND_OZ860 C0805
AGND_OZ860 Document Number Rev
S09 MAINBOARD A
A B C D E
5V_AUX_S5 DCBATOUT
www.hocnghetructuyen.vn PR37
0
+/-5%
PR38 PR39
R0402
MAX1999_LDO5
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
M1999_CTLTON PR40
OPEN-POWER-GAP-3050
PR41 10 100K 0
R0402
PG28
PG17
PG18
PG19
PG20
10uF
PC24
PR42 150K +/-5% +/-5%
2
47K +/-5% DCBATOUT R0805 +/-5% R0402 MAX1999AGND
+/-5% PD7 R0402
* PD10 Dummy
CH501H-40
PQ4
PD9
R0402
10V, Y5V, +80%/-20%

CH501H-40 CH501H-40
TP0610K
C0805
1
PR45 PC25
2
MAX1999_SLP_VEST S D MAX1999_SKIPJ 100K
+/-5% * 1uF
10V, Y5V, +80%/-20%
DRV_BST3
MAX1999_LDO5
DCBATOUT R0402 PR46 C0603 M1999V+P5
PR47 4.7
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
25V, Y5V, +80%/-20%

G
47K +/-5%
*
25V, X5R, +/-10%
25V, X5R, +/-10%
PC26
C0603
0.1uF
+/-5% R0805 MAX1999AGND
* *
10uF
PC27
PC28
C1210
C1210
R0402 MAX1999AGND
PG21
PG22
10uF
DRV_BST5
2
PWRPM_SLP_S3 6.2A/5V
5
6
7
8
25V, X7R, +/-10%
25V, Y5V, +80%/-20%
D
D
D
D
PQ5
MAX1999_SKIPJ 5V_S5
SI4892DY
PC29
PC30
C1206
C0603
4.7uF
0.1uF
PR163
* *
D
1
0 2N7002EPT
R0402 PQ6
12
+/-5% M1999V+P3 PU2
25V, X5R, +/-10% 10uF
S0_EN1 G
G
S
S
S
SKIP
17,20,30,37,38,40 S0_EN
C1210 PC31
25V, X7R, +/-10%
4
3
2
1
8
7
6
5
* * 18 13 MAX1999_TON
S
LDO5 TON
PQ7
PC32
C0603
PSHORT7
PSHORT1
D
D
D
D
0.1uF
4.3A/3D3V MAX1999_V+ MAX1999_VCC
Si4800BDY
20 V+ VCC 17
3D3V_S5 MAX1999_BST3 28 14 MAX1999_BST5
PR49 BST3 BST5
PC33 0 PR50
0
MAX1999AGND * 0.1uF
C0603
R0603
+/-5% R0603
PC34
0.1uF
*
S
S
S
G
25V, Y5V, +80%/-20% +/-5% C0603
1
2
3
4
PSHORT2
25V, Y5V, +80%/-20%

MAX1999_DH3 26 16 MAX1999_DH5
DH3 DH5 PL2 4.7uH
*
PL3
4.7uH MAX1999_LX3 27 15 MAX1999_LX5 VCC5V
*
VCC3D3V LX3 LX5

MAX1999_DL3 24 19 MAX1999_DL5
DL3 DL5
8
7
6
5
16V, Y5V, +80%/-20%
MAX1999
2
5
6
7
8
2
SSM24PT
PQ8
D
D
D
D
PTC1 PTC2 PTC3

SI4892DY
Dummy
1
* * *
D
D
D
D
SSM24PT
PQ9
PC35
PD11
PD12
C0402
0.1uF
* 220uF PD13 150uF 150uF

* PC36
SI4892DY
Dummy
4V, +/-20% SSM24PT 6.3V, +/-20% 6.3V, +/-20% 0.1uF

ctdh19 Dummy CTD CTD 16V, Y5V, +80%/-20%
2
Dummy C0402
1
1
S
S
S
G
G
S
S
S
1
2
3
4
22 21
4
3
2
1
MAX1999_FB3 OUT3 OUT5 MAX1999_FB5
7 FB3 FB5 9
MAX1999_SHDNJ 6 SHDN MAX1999_PGOOD
PGOOD 2
MAX1999_ON3 3 ON3 M1999_VREF

REF 8
MAX1999_ON5 4 ON5
LDO3
MAX1999_ILIM3 5 10
GND
N.C.
ILIM3 PRO
11 ILIM5 1
PC37 PR51 PR52 PC38
100pF
* 6.8K 15K
* 100pF
23
1
25
50V, NPO, +/-5% +/-1% MAX1999AGND 5V_AUX_S5 +/-1% C0402
C0402 R0402 PC39 r0402h4 50V, NPO, +/-5%
2
0.22uF
*
MAX1999_LDO3
10V, X7R, +/-10%
PR53 PR54
5V_AUX_S5 PR55 0 C0603 100K
10K DCBATOUT +/-5% +/-5% PR56
+/-1% R0402 9.76K
R0402 PC40 3D3V_AUX_S5 +/-1%
PR58
4.7K * 10uF
C0805
R0402 r0402h4
PJ2
+/-5% MAX1999AGND
PR59 MAX1999AGND PR60 R0603 10V, Y5V, +80%/-20%
2 1
47K 0 MAX1999AGND
+/-5% R0402
R0402 +/-5% JUMPER1
MAX1999_ON3 DCBATOUT
MAX1999_SHUTDOWN_S5J MAX1999_ON5
PR61 MAX1999AGND
PD14
0
MAX985_SHDNJ 2 1 +/-5% M1999_VREF M1999_VREF MAX985_SHDNJ MAX985_SHDNJ 39
R0402
D
CH501H-40 PQ10 PR65 PR64

PR172 PR173 300K 1M
100K 100K +/-5% R0402 PU3
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
18 SHUTDOWN_S5 SHUTDOWN_S5_A G PR227 PR229 +/-5% +/-5% R0402 +/-5%

0 0 R0402 R0402 1 5
OUT VEE
PC41
PC42
C0402
C0402
0.1uF
0.1uF
PR164 2N7002EPT +/-5%

* * +/-5% MAX1999_ILIM3
S
0 R0603 5V_AUX_S5 2
R0402 PR228 R0603 MAX1999_ILIM5 VCC
+/-5% 10K Dummy Dummy MAX985_IN 3 4 M1999_VREF
+/-5% PR174 PR175 IN+ IN-
TECHNOLOGY COPR.
For Debug R0603 100K 249K
Dummy +/-5% +/-1% MAX985 Title
R0402 R0603 PR69 MAX1999+ 5V/3D3V
MAX1999AGND 100K
MAX1999AGND +/-5% Document Number Rev
MAX1999AGND MAX1999AGND MAX1999AGND R0402 S09 MAINBOARD A
MAX1999AGND MAX1999AGND MAX1999AGND
Low4 Protect CKT Date: Tuesday, March 15, 2005 Sheet 36 of 45
5 4 3 2 1
www.hocnghetructuyen.vn DCBATOUT
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
PG5
PG6
2
2
Dummy
D PR109 10K D
3D3V_S0
3D3V_S5 R0402 +/-5%
1
3D3V_S0 3D3V_S5
7A/1.05V
PR70 1D05V_S0
OZ824_SKIP2
PR71 10K
PR166 10K PR108 +/-5%
0 R0402 10K R0402 OZ824_VIN1
+/-5% +/-5% +/-5% PSHORT8 PSHORT3
R0402 R0402 PC43
Dummy 10uF
39 VCC_PWRGD
OZ824_PGDP2
25V, Y5V, +80%/-20% *
OZ824_VIN1 PC44 47nF OZ824_SLEW2 C1210
*
C0402 OZ824_CS2NF PL4
5V_S5 16V. Y5V, +80/-20% OZ824_CS2PF 2.2uH
OZ824_SET2 OZ824_HDR2
*
PR72 PR73 OZ824_LX2 OZ824_1D05V_S0
1K 22 For Debug PC45
+/-5% +/-5% 0.22uF PR74
5
6
7
8
2.5V, +/-20% PTC4
2.5V, +/-20% PTC5

ctbh20 220uF
220uF
R0603 R0603 PR230 PR231 25V, X7R, +/-10% PR77 PR78 51
*
33
32
31
30
29
28
27
26
25
2
D
D
D
D
0 0 PU4 C0805 120K 45.3K +/-1% PR75
1
* *
SSM24PT
C0402 PC155
16V, Y5V, +80%/-20% 0.1uF
+/-5% +/-5% OZ824_LDR2 +/-1% +/-1% R0603
* 15K
Si4800BDY
Dummy
GNDA
VSET2
SKIP2
SLEW2
CS2P
PGD2
LX2
HDR2
CS2N
PQ11
PD15
PR76 0 +/-5% R0805 R0805 OZ824_BST2 R0603 R0603 +/-5%
30 S0_EN_D
ctbh20
Dummy R0402 Dummy Dummy R0402
2
C C
PD16
1
PR79 0 +/-5% OZ824_ON2 5V_S5
G
S
S
S
17,20,30,36,38,40 S0_EN 1 ON2 BST2 24
R0402 2 23 1 2
4
3
2
1
NC GNDP2
*
OZ824_VIN 3 22 OZ824_CS2PF PC46 3.3nF
OZ824_VREF VIN LDR2 CH501H-40 DCBATOUT C0603
4 VREF VDDP2 21
50V, X7R, +/-10%
OPEN-POWER-GAP-3050
5 GNDA OZ824LN VDDP1 20
5
6
7
8
2
1uF
OZ824_VDDA 6 19 OZ824_LDR1 OZ824_CS2NF 9A/1.5V
VDDA LDR1
D
D
D
D
SSM24PT
7 CE GNDP1 18
* PD18 1D5V_S0
C0603
PD17
OZ824_ON1 PC48 PC49
* *
SI4892DY
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
17,20,30,36,38,40 S0_EN 8 ON1 BST1 17 1 2
PG7
PG8
PQ12
PG29
PC47
22pF 1nF
2
PR80 PC52 CH501H-40 50V, NPO, +/-5% 50V, X7R, +/-10%
*
SLEW1
VSET1
1
SKIP1
HDR1
PGD1
CS1N
0 1uF C0402 C0402
CS1P
Dummy
LX1
+/-5% C0603 OZ824_BST1
G
S
S
S
PSHORT4
R0402 PR81 PC53
4
3
2
1
PSHORT5
102K 0.22uF
*
9
10
11
12
13
14
15
16
+/-1% 25V, X7R, +/-10% OZ824AGND OZ824AGND
R0402 C0805
C0603 0.1uF PC87
C0603 0.1uF PC88
OZ824_SKIP1
OZ824_PGD1
OZ824_SET1 PL5
50V, Y5V, +80%/-20%
50V, Y5V, +80%/-20%
OZ824AGND 2.2uH
* *
Dummy
*
OZ824_LX1 OZ824_1D5V_S0
Dummy
OZ824_SET1
16V, Y5V, +80%/-20%
OZ824_HDR1 PR82
50V, X7R, +/-10%
50V, X7R, +/-10%
5
6
7
8
B PR85 PR86 51 B
OZ824_VIN2
2
D
D
D
D
PC51
C0603
2.5V, +/-20% 220uF
220uF
0.22uF
PR84 158K 48.7K +/-1%

* * *
1
*
SSM24PT
PTC6
PTC7
PC50
C0603
PC54
C0402
10nF
45.3K OZ824_CS1PF R0603 R0603 R0603
SI4392DY
Dummy
1
*
PQ13
1nF
PD19
+/-1% OZ824_CS1NF +/-1% +/-1% PR83
C0402 PC156
16V, Y5V, +80%/-20% 0.1uF
R0402
* 15K
2
+/-5%
2.5V, +/-20%
1
2
ctbh20
R0402
G
S
S
S
ctbh20
OZ824AGND
4
3
2
1
*
OZ824_SET2 OZ824_CS1PF PC55 3.3nF
OZ824AGND OZ824AGND PC56 C0603
50V, X7R, +/-10%
47nF 50V, X7R, +/-10%
5
6
7
8
2
16V. Y5V, +80/-20% OZ824_CS1NF
D
D
D
D
SSM24PT
C0402
PC57
PD20
C0402
PR87 PC58 PC59

* OZ824_SLEW1
Si4856DY
*
PQ14
1nF
105K
+/-1%
OZ824AGND
* 22pF
50V, NPO, +/-5% * 1nF
50V, X7R, +/-10%
1
r0402h4 C0402 C0402
Dummy
G
S
S
S
4
3
2
1
OZ824AGND OZ824AGND
PR107 PR88 PR89 PR106
OZ824AGND OZ824AGND 10K 10K 10K 10K
+/-5% +/-5% +/-5% +/-5%
A R0402 R0402 R0402 R0402 PC60 PC61 A
Dummy Dummy PJ3 10uF 10uF
1 2 25V, Y5V, +80%/-20% ** 25V, Y5V, +80%/-20%
C1210 C1210 TECHNOLOGY COPR.
3D3V_S0 3D3V_S5 3D3V_S5 3D3V_S0 JUMPER1
Title
OZ824AGND OZ824
Document Number Rev
S09MAINBOARD A
5 4 3 2 1
5 4 3 2 1
DCBATOUT
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
OPEN-POWER-GAP-3050
PG9
PG10
2A 2A
2
PG23
PG24
2
2
SC486DCBATOUT
1
1
1
5V_S5
SC486_1D8V
PR91
D PR90 820K PR232 PR92 D
10 +/-1% 0 For Debug 0
25V, Y5V, +80%/-20%
25V, Y5V, +80%/-20%

R0402 r0402h4 +/-5% R0402
25V, X7R, +/-10%

50V, NPO, +/-5%
10V, Y5V, +80%/-20%

1 +/-5% R0805 +/-5%
PR93 Dummy
PC63
C0402
2.26K
*
PC66
PC64
PC65
10pF
1uF
10uF
10uF
C0402
C1210
C1210
* +/-1%
* * *
25V, NPO, +/-5%

1
PC62
C0603
0.1uF
r0402h4 PR233 PR94
2
1nF
PR95 For Debug 0 470K PR96
2
DDR_VREF 10 +/-5% +/-5% 0
*
C0603
+/-5% R0805 R0402H4 R0402
PU5 2
PC67
R0402 Dummy +/-5%
3mA SC486_VTTEN11 7SC486_PG SC486_PGD 1 PTP1
VTTEN PGD
SC486_VDDQS 3
VDDQS
1
PR97 1SC486_EN Dummy
SC486_TON 2 EN/PSV
CH501H-40
TON 1D8V_S3 13A
PD21
0D9V_S0 3A 10
+/-5% SC486_FB 6 PR99 VDIMM
25V, Y5V, +80%/-20%

FB
5
6
7
8
VTT_MEM R0402 PR98 0
D
D
D
D
R0402 PQ15
DRV_BST
8
10V, Y5V, +80%/-20%
1SC486_DDR
10 REF
R0402 * PC68
0.1uF SC486_COMP 9 24 SC486_BST
+/-5% SI4892DY
C
+/-5% 10V, Y5V, +80%/-20% C0402 COMP BST
C
PC69
C0603
0.1uF
16V, Y5V, +80%/-20% SC486_VTTS PSHORT10 PSHORT9 PSHORT6
*
16V, X7R, +/-10%

PR100
G
S
S
S
1
1uF PC72
PC70
1uF
PC71 68nF
C0402
C0402
PSHORT11
* 10K
* SC486_VCCA 10
4
3
2
1
+/-1% PR101 PC73 VTTS
23 SC486_DH
* DH
1
R0402 10 1uF PR102
* 5
2
VCCA
C0603
+/-5% 10V, Y5V, +80%/-20% 21 SC486_ILIM
ILIM PL6
R0402 C0402 1uH
*
2
4 VSSA LX 22 SC486_LX 14K SC486_1D8V
R0603
SC486AGND 14 +/-1%
SC486_VTT VTT_1
15 VTT_2
5
6
7
8
19 SC486_DL PC74
THERMALPAD
DL
D
D
D
D
12 VDDP2_1 * 0.1uF PTC8 PTC9
1
SC486_VDDP1 10V, X7R, +/-10% * 330uF * 330uF
Si4856DY
13 VDDP2_2 VDDP1 20
PQ16
C0402 2.5V, +/-20% 2.5V, +/-20%
16 ctdh19 ctdh19
2
PGND2_1
17 PGND2_2 PGND1 18
G
S
S
S
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

SC486IM
25
4
3
2
1
6.3V, X5R, +/-10%
25V, Y5V, +80%/-20%
1
PC78
C1206
22uF
* * * *
6.3V, X5R, +/-10%
6.3V, X5R, +/-10%
1uF
PC76
PC77
PC79
10uF
C0603
C0805
C0402
0.1uF
* *
PC80
PC81
10uF
10uF
C0805
C0805
PC75
2
1
1uF
B PR103 * 10V, Y5V, +80%/-20%
B
C0402
2
0
R0402
+/-5%
PR104
17,20,30,36,37,40 S0_EN SC486_VTTEN

SC486AGND
16V, Y5V, +80%/-20%

0
PC82 0.1uF
VDIMM/EN VTT_MEM/EN VDIMM VTT_MEM VREF R0402 *
C0402
+/-5%
0 0 X X X
0 1 X X X
SC486AGND
PR105
1 0 1.8 X 0.9
A
30 S3_EN SC486_EN A
16V, Y5V, +80%/-20%

1 1 1.8 0.9 0.9
0
PC83 0.1uF
R0402 * TECHNOLOGY COPR.
C0402
+/-5% Title
SC486(1D8V-S3&0D9V-S0)
Document Number Rev
SC486AGND
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
3D3V_S0 PR206 0 5V_S0

PC126 DCBATOUT
PD30
1
CH501H-40 PR224
* 1uF R0402
CH501H-40
0 10V, X5R, +/-10% +/-5%
36 MAX985_SHDNJ 2 1
PD31
PSHORT12
R0402 C0603
PR178 +/-5%
3.3K Dummy 5V_AUX_S5
2
+/-5% PR179 0
R0603 R0402 +/-5%
37 VCC_PWRGD PR215 0
R0402 +/-5% PR234
BSTRCD1
D 0 D
PR195
For Debug +/-5% DCBATOUT_450
25V, X5R, +/-10%

10uF PC148
PR216 0 SC450_DPRSL 100K DS2 PR180 261K R0805
25V, X5R, +/-10%
25V, X5R, +/-10%

5 PM_DPRSLPVR
10uF PC128
R0402 +/-5% +/-5% R0603 +/-1% Dummy
5
6
7
8
C1210
10uF PC129
R0402 PC127 VCC_CORE_S0
*
Dummy
D
D
D
D
C1210
PQ36 1uF PQ37
* *
C1210
PR217 DS1
SC450AGND
G
3D3V_S0 10V, X5R, +/-10%
C0603 * Si4800BDY
0
D
D
PG1
R0402 2N7002EPT
S
+/-5% PQ39 PQ38
G
S
S
S
3,15 PM_STPCPUJ PL12
4
3
2
1
G G TG1 PR181 1.5V @ 27A
*
DRN1 L-R1
2N7002EPT 2N7002EPT
S
S
0.56uH 2m
25V, X7R, +/-10%
5
6
7
8
5
6
7
8
PT10
PT11
C0603
2.5V, +/-20% 330uF
2.5V, +/-20% 330uF
25V, X7R, +/-10% 0.1uF
25V, X7R, +/-10% 0.1uF

PR182 44.2K 3D3V_S0 R2512
SC450_V5_1
D
D
D
D
D
D
D
D
C0603 PC152
C0603 PC151
R0603 +/-1% PR183 PR184 10K +/-5%
SC450AGND 10 R0603 +/-1% PD32
Si4856DY
Si4856DY
1
* *
*
PQ41
PQ40
PC130
PC131 1nF +/-1% SSM54PT
* * *
Dummy
0.1uF
ctdh19
ctdh19
PC132 1nF C0603 PU13 R0603 Dummy
1
*
C0603 25V, NPO, +/-5% PR187 332
2
PR185 PC134
G
S
S
S
G
S
S
S
1 DRN1 V5_1 38
25V, NPO, +/-5% 10K SC450_BG1 1uF R0603 +/-1% PD35
2 37
*
4
3
2
1
4
3
2
1
1
C TG1 BG1 C
+/-5% BST13 36 C0603 PR188 750 SSM54PT
R0603 BST1 PGND1 SC450_EN 16V, Y5V, +80%/-20% R0603 +/-1% Dummy
4 DPRSL EN 35
220pF PC133
SC450AGND SC450AGND PR223 0 SC450_VDPR 5 SC450_ISH1
50V, NPO, +/-5%
50V, NPO, +/-5%

VDPR ISH1 34
180pF PC135
R0402 +/-5% SC450_PBOOT 6 33 SC450_CL1
PBOOT CL1
C0603
SC450_CLSET CMP1
3 VTT_PWRGDJ
PR186 36.5K PR189 19.6K SC450_HYS 8
7 CLK_ENABLE# CMP1
HYS CLRF
32
31 SC450_CLRF
* * PR190
C0805
H_VID5 R0603 +/-1% R0603 +/-1% SC450_VID5 9 30 SC450_VCCA 750
SC450_VID410 VID5 VCCA SC450_CMPRF R0603
H_VID4 VID4 CMPRF 29 Note: Route CS1P, CS2P, and CLREF
H_VID3 PR208 0 SC450_VID311 28 SC450_CMP2 SC450AGND +/-1%
R0402 +/-5% SC450_VID212 VID3 CMP2
27 SC450_CL2 together as differential triple, or two
H_VID2 VID2 CL2
H_VID1 PR209 0 SC450_VID113
VID1 ISH2 26 SC450_ISH2 differential pairs.
C0603 330pF PC136

H_VID0 R0402 +/-5% SC450_VID014 25 PR191 1.33K
VID0 GND
PC140
220pF PC137
0.1uF PC138
SC450_SS15 SC450_DAC R0603 +/-1%
25V, X7R, +/-10%

50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%

SS DAC 24
330pF PC139
PR207 0 SC450_PWRGD 16 23
VRMPWRGD IMVP4_PWRGD CORE
C0603
C0603
C0603
R0402 +/-5% PR192 +/-1%
17 BST2 PGND2 22
* * * *
180pF
BG2 2.49K R0603 DCBATOUT_450
PR210 0
18
19
TG2
DRN2
BG2
V5_2
21
20
*
5
6
7
8
C0805
PC143
3D3V_S0 R0402 +/-5% PC141
Si4800BDY
25V, X5R, +/-10%
25V, X5R, +/-10%

D
D
D
D
10uF PC144
1nF
*
25V, X5R, +/-10%

PQ42
10uF PC149
PR211 0 SC450IT C0603 PR193 750
C1210
C1210
C1210
C0603 4.7nF PC142
PR218 R0402 +/-5% 25V, NPO, +/-5% R0603 +/-1%

* *
Dummy
100K PR194 332
*
50V, X7R, +/-10%
10uF
+/-5% PR212 0 PR219 R0603 +/-1%
R0402 R0402 +/-5% VCC_CORE_S0 PR196 10K
*
G
S
S
S
B B
R0603 +/-5% PR199
4
3
2
1
PR213 0 200K 2m
R0402 +/-5% +/-5% PR197 332 SC450_CORE R2512
R0402 R0603 +/-1% PL14 +/-5%
16V, Y5V, +80%/-20%
*
L-R2
0.1uF PC150
SC450_TG2
Dummy
2
0.56uH
*
5
6
7
8
5
6
7
8
PT12
2.5V, +/-20% 330uF
2.5V, +/-20% 330uF
25V, X7R, +/-10% 0.1uF
25V, X7R, +/-10% 0.1uF

5V_S0
D
D
D
D
D
D
D
D
ctdh19 PT13
C0402
C0603 PC153
C0603 PC154
SC450AGND PD33
SSM54PT
Si4856DY
Si4856DY
1
* *
PQ44
PQ43
SC450_DRN2
PR220 PR221 PR222 PC145 Dummy

* *
Dummy
1
ctdh19
0 0 0 PR198 330pF PR214 SC450AGND
SC450AGND R0402 R0402 R0402 64.9K * 50V, X7R, +/-10% 0 PD36
SC450_BST2
2
+/-5% +/-5% +/-5% +/-1% C0603 SSM54PT
G
S
S
S
G
S
S
S
R0402
Dummy Dummy Dummy R0603 Dummy
4
3
2
1
4
3
2
1
1
SC450_V5_2 +/-5%
PC146
* 1uF
1
SC450AGND 10V, X5R, +/-10% PJ4

CH501H-40
C0603 1 2
PD34
Design to IMVP-IV Revision 1.0. JUMPER1

A SC450AGND A
2
Vboot = 1.20V SC450AGND

BSTRCD2
Vdprslp = .748V PR200 0

R0402 +/-5% TECHNOLOGY COPR.
PC147 Note: All Grounds Tied together at output Caps.
Notes: * 1uF
10V, X5R, +/-10%
Title
Vcore
C0603
1) This schematic is set up for 27A output. Document Number Rev
S09 Vcore A
5 4 3 2 1
5 4 3 2 1
暂时使用此零件
待申请完后再用
3D3V_S0
SI3447BDV 3D3V_S5
PQ45
SI3456BDV
6
5 4
D
www.hocnghetructuyen.vn 2
1
D
PC85
3
4.7uF
* C0805 PR225
10V, Y5V, +80%/-20% 100K
Dummy +/-5%
R0402
5V_S5
5V_S0
PU8
S
8 1
7 2
6 3
G
5 4
C C
PC86
4.7uF SI4435BDY
* C0805 PR136
10V, Y5V, +80%/-20% 100K
Dummy +/-5%
R0402
S02NJ
D
PQ26
PR176
153mA
17,20,30,36,37,38 S0_EN S0_EN_A G
2N7002EPT
2D5V_S0
S
0
R0402
+/-5%
50V, NPO, +/-5%

22pF
PC109
C0402
B
* PR135
10K B
+/-1%
R0402
I max = 300 mA
PU9
1 5 2D5V_S0_SET
3D3V_S0 SHDN# SET
2 GND
3 IN OUT 4
PC110
1uF
* G913C
10V, Y5V, +80%/-20% PC111
C0603
* 1uF
10V, Y5V, +80%/-20%
PR137
10K
C0603 +/-1%
R0402
A A
TECHNOLOGY COPR.
Title
Other power
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
D D
3D3V_AUX_S5
C C
1D5V_S5
1D5V_S5 3D3V_S5 5V_S5
PR154
100K
R0402
6.3V, X5R, +/-10%
10V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
PR146 PSW1 +/-5%

* *
PC120
C0805
C0603
PC118
PC119
C0805
10uF
1uF
10uF
10K
+/-5% * 2 1 EC_PWRBTNJ 30
R0402 4 3
5 GND
PR147
21K Tactile Switch
16V, Y5V, +80%/-20%

PU11 +/-1%
4 R0402
VPP
PC84
C0402
0.1uF
1D5V_S5POK 1 POK
VO 6
*
2 7 1D5V_S5_FB
VEN ADJ
1
GND
GND
PR149
10V, Y5V, +80%/-20%
3 VIN NC 5
24K
*
PC123
C0603
1uF
+/-1%
Dummy
1D5V_S5 G966
8
9
r0402h4
2
B Io = 540mA B
Vo=1.5V
=0.8*(21+24)/24
A A
TECHNOLOGY COPR.
Title
Save Power circuit
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
D D
H4 H5 H6 H7 H8 H9
MH27X80 MH27X80 MH27X80 MH27X80 MH27X80 MH27X80
1
AUD_AGND
H11 H12 H13 H14

MH27X34 MH27X34 MH27X34 MH27X34
1
1
C C
H15 H16 H18 H3

MH41X70 MH41X70 MH41X70 MH41X70
1
H17 H2
MH41X65 MH41X65
1
H19
B MH20X30 B
1
H20
MH30X100
1
H21
MH27X60
A A
1
TECHNOLOGY COPR.
Title
HOLE/UNUSED PARTS
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
D D
MDC
ACZ_RST# ACZ_RSTJ H_RST# C_RST# ACZ_CRSTJ RESET#
OZ263 ALC650
RTCRST#
RTC
MINI_PCI
PCIRST#
3D3V_S5 CB851
ICH-6 LAN_RSTSYNC
LAN82562
CH501H-40 4.7K LAN_RST#
KB3910
C RSMRST# C
PLT_RST#
100K
HDD/ODD
4.7uF
Alviso
www.hocnghetructuyen.vn RSTIN#
H_CPURST#
B B
RESET#
Dothan
A A
TECHNOLOGY COPR.
Title
RESET MAP
Document Number Rev
S09 MAINBOARD A
5 4 3 2 1
5 4 3 2 1
Device CLK
CPU GMCH ICH6-MENE3910 DDRII Audio HDD ODD LCD INV USB2.0 LAN CB851 Oz263 ANTITHEFT
D
Rails GEN D
3D3V_AUX_S5
5V_AUX_S5
3D3V_S5
5V_S5
1D5V_S5
VDIMM
(1D8V_S3)
C
VTT_MEM C
(0D9V_S0)
3D3V_S0
5V_S0
2D5V_S0
1D5V_S0
1D05V_S0
VCC_CORE_S0
B B
1D8V_S0
DCBATOUT
A A
TECHNOLOGY COPR.
Title
POWER_PLANE
Document Number Rev
S09 MAINBOARD A
Date: Sunday, March 13, 2005 Sheet 44 of 45
5 4 3 2 1
5 4 3 2 1
0218. P39, change Vcore to two phase

0222. P14,add SATA diable circuit when use PATA
0224. P24,change Lan to 82625GT
0225. P14,P19,Del SATA
0303. ADD RESET MAP
D 0312. del AUD_AGND_S D
C C
B B
A A
TECHNOLOGY COPR.
Title
HISTORY
Document Number Rev
S09 MAINBOARD A
Date: Saturday, March 12, 2005 Sheet 45 of 45
5 4 3 2 1

Laptop Lenovo Foxcon-S09

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Laptop Lenovo Foxcon-S09

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S09 Block Diagram

CLK GEN Dothan T8 SYSTEM DC/DC

400/533 13 MAXIM CHARGER

DMI I/F 100MHz BT+

Intel LAN PCB LAYER

USB LPC BUS L3: Signal 2

CB851 25 E 0 LAN_CLK ICH6 internal 100K pull-downs

12 GPIO06 High:Test Mode(KSOUT0~15 become DPLL internal data outputs,

105 GPIO20 High:Normal operation(Recommended)

Dummy BC13 50V, NPO, +/-5% X2_ICS 49 51

R0402 BC14 R19 R0402 39

14 H_STPCLKJ C6 A15 1 TP17 B_H_DJ16 H23 AB25 B_H_DJ48

10V, Y5V, +80%/-20%

Layout Note: BC628

C4 VSS84 VSS181 V21

D11 VSS96 TECHNOLOGY COPR.

Place them near to the chip TECHNOLOGY COPR.

Alviso will provide SDVO_CTRLCLK

11 M_CKE1_RJ AM21 LCTLB_DATA C22 E32

11 M_CS0_RJ SM_CS0# THRMTRIP# PM_THRMTRIPJ 4,14 LIBG EXP_TXN4

11 M_CS2_RJ AH15 AE29 R94 100 TP34 1 L_VREFH F28 L32

SM_OCDCOMP0 DREF_CLKP DREFCLK 3 13 GMCH_TXACLK- LACLKN EXP_TXN9

DDR_VREF SMVREF0 NC7 13 GMCH_TXAOUT0+ LADATAP0 EXP_TXP2

SMXSLEW AE27 B37 13 GMCH_TXAOUT2+ GMCH_TXAOUT2+ B31 H32

CFG18 R632 2.2K +/-5% R0402 @GM

R98 10K PM_EXTTSJ0 CFG6 R103 2.2K +/-5% R0402

R101 10K PM_EXTTSJ1 CFG8 R108 2.2K +/-5% R0402 Dummy

A R113 R114 R115 LCTLB_DATA R112 2.2K R0402 +/-5% A

GMCH_BL_ON R117 100KR0402 +/-5%

M_A_DQ24 AP27 AN30 M_A_DQSJ2 M_B_DQ23 AG28 AK33 M_B_DQSJ1

DDR SYSTEM MEMORY B

10V, Y5V, +80%/-20%

then connect to the gnd plane

Route ASSATVBG gnd from GMCH to

10V, X5R, +/-10%

T29 VCC0 VCCA_TVDACA0 F17

K28 VCC14 VCCD_LVDS1 B25

VCC23 VCCSM0 V1.8_DDR_CAP2

L27 AP29 V1.8_DDR_CAP5

K25 VCC31 VCCSM8 AM26

K24 VCC33 VCCSM10 AK26

K22 VCC35 VCCSM12 AH26

K21 VCC36 VCCSM13 AG26

BC155 BC154 BC150 BC148

10V, Y5V, +80%/-20%

V18 VCC45 VCCSM22 AH25

VCCA_DPLLB VCCSM30 10V, Y5V, +80%/-20%

VSSA_CRTDAC VCCSM36 10V, Y5V, +80%/-20%

K12 VTT2 VCCSM43 AH13

within 3" of Alviso.

Route caps within 250mil VTT7 VCCSM48

N11 VTT9 VCCSM50 AL12

T10 VTT16 VCCSM57 AD11 *

P10 VTT18 VCCSM59 AB11

N10 VTT19 VCCSM60 AB10

K10 VTT21 VCCSM62 AP8 V1.8_DDR_CAP6

VTT22 VCCSM63 V1.8_DDR_CAP3

decoupling cap ground lead and then

P9 VTT27 VCCTX_LVDS2 A27

M9 VTT29 VCCA_SM0 AF20

J9 VTT31 VCCA_SM2 AF19

16V, Y5V, +80%/-20%

VCCP_GMCH_CAP1 VTT37 VCC3G3

N5 VTT39 VCC3G5 L37