Instructor: U.

Ganguly

udayan@ee.iitb.ac.in; Room 605 Nanoelectronics Bldg

Source (EE; Website: https://www.ee.iitb.ac.in/web/academics/courses#EE669 )

EE669 VLSI TECHNOLOGY

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Environment for VLSI Technology: Clean room and safety requirements. Wafer cleaning processes and wet chemical
etching techniques.Impurity incorporation: Solid State diffusion modeling and technology, Ion Implantation modeling,
technology and damage annealing, characterization of Impurity profiles.Oxidation: Kinetics of Silicon dioxide growth
both for thick, thin and ultrathin films. Oxidation technologies in VLSI and ULSI, Characterization of oxide films, High k
and low k dielectrics for ULSI. Lithography: Photolithography, E-beam lithography and newer lithography techniques
for VLSI/ULSI; Mask generation.Chemical Vapour Deposition techniques: CVD techniques for deposition of
polysilicon, silicon dioxide, silicon nitride and metal films, Epitaxial growth of silicon, modelling and technology.Metal
film deposition: Evaporation and sputtering techniques. Failure mechanisms in metal interconnects, Multi-level
metallisation schemes. Plasma and Rapid Thermal Processing: PECVD, Plasma etching and RIE techniques, RTP
techniques for annealing, growth and deposition of various films for use in ULSI.Process integration for NMOS,
CMOS and Bipolar circuits, Advanced MOS technologies.
Text/References
 C.Y. Chang and S.M.Sze (Ed),ULSI Technology, McGraw Hill Companies Inc, 1996.
 S.K. Ghandhi, VLSI Fabrication Principles, John Wiley Inc., New York, 1983.
 S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 1988

Text and Reference Changed to following

Main Reference Books:

1. Stephen Campbell Science and Engineering of Microelectronics Fabrication; Oxford 1996

2. J. D. Plummer, M. Deal and P. D. Griffin, Silicon VLSI Technology: Fundamentals, Practice and
Modeling, 2000, Prentice Hall, ISBN: 978-0130850379, 2nd Ed., 2008.

3. S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 1988

4. Marc J. Madou Fundamentals of Microfabrication: The Science of Miniaturization CRC Press 2002

Approximate Lesson Plan

This follows Stephen Cambell’s book in content – additional problem solving in classwork and homework

1. Overview and Motivation: What do we fabricate? What is the benefit?

2. Modules with examples/applications
a. Basic Materials Types: Crystal, organics etc.
b. Hot Processing and Ion Implantation; How to change film properties
c. Pattern Transfer
d. Deposition of thin film- Physical / Chemical Vapor
 3. Process integration of advanced devices and circuits e.g. FinFETs, nanowire FET, MEMS Digital
Micro-mirror Device (display), Nanocrystal memories, Optical Clocks etc.

Attendance

Biometric attendance will be used. Please ensure that your cards work.

You will get an XX grade for less than 80% attendance.

Pre-requisites

There are no specific pre-requisites except working knowledge of devices, optics, chemical reactions at
par with 1st year undergrad physics/chemistry, basic electronic devices EE207 or 733.

We will use MATLAB for exercises.

Evaluation Structure

Topic Quantity Preparation Grading Weight

Home-works 8 Instructor TAs 15%
Quiz 4 Quizes (approx Instructor TAs 4x15%=60%
dates)
Aug 15
Week of Sept 18
(Midsem)
Oct 19
Week of Nov 19
(Endsem)
Project 1 project Instructor Instructor with TAs 20%
Week of April 15 help
Class Class Work; Instructor Instructor with TAs 5%
participation/ Recitations; help
Attendance

Grading methodology

a) Grading will be relative i.e. score = (marks-median)/std dev

b) Final score is weighted average of individual scores. Absolute mark ranking is not considered.
c) Absentees will not be given a retest but marks will be scaled up if reason of absence is formally
accepted (pink slip etc). Pink slips need to mailed by absentee on moodle after each quiz.
d) Class participation grade is based on attendance and engagement in discussion. It is
discretionary for the instructor.
Policy in Cheating during Exams

It’s best not to test this. The institute policy is as tough as expulsion.

Homework submission

Box in EE Office or by moodle.