DSX Electronics Hardware

DSX Circuit Board Diagrams
1. OVERVIEW
2. BACK PLANE
2.1.1. Schematic
2.1.2. PCB Layout
3. COMMUNICATIONS MODULE
3.1.1. Schematic
3.1.2. PCB Layout
4. XY MOTION
4.1. CONTROL BOARD
4.1.1. Schematic
4.1.2. PCB Layout
4.2. X TRANSITION
4.2.1. Schematic
4.2.2. PCB Layout
4.3. Y TRANSITION
4.3.1. Schematic
4.3.2. PCB Layout
5. Z & PIPETTE
5.1. CONTROL BOARD
5.1.1. Schematic
5.1.2. PCB Layout
5.2. PIPETTE & EJECT DRIVES
5.2.1. Schematic
5.2.2. PCB Layout
5.3. Z TRANSITION BOARD
5.3.1. Schematic
5.3.2. PCB Layout
6. WASHER
6.1. CONTROL BOARD
6.1.1. Schematic
6.1.2. PCB Layout
6.2. DAUGHTER BOARD
6.2.1. Schematic
6.2.2. PCB Layout
1. Overview
1 2 3 4 5 6 7 8
REV. ECO No. CHANGE DESCRIPTION INI. DATE

Comms Module
IM Washer Module
Back Plane
J1
J5
J2 J17
J1
J3 J2
J2 J1
IM IM
J4
D Pinch Vale D Pump 1 D
J3
Pinch Vale D Pump 2
J5 J5 J5
Pinch Vale D Pump 3
J4
Pinch Vale D Pump 4
Wash Level Switch 1
J5
Wash Level Switch 2
AM Bar Code Reader Wash Level Switch 3
J6
Wash Level Switch 4
Waste Level Switch
J7 J6 J4
Aspirate Pump drive
PSU Vacuum switch
J8
J9
IM Drawer
JXXX J18 J10
J5 J4
J11
J12
J13
J14
Guard Switch
Terminals J15
C C
J29
XY Board
J2 J16
J24
J25
J26
J27
B B
Z Transition And drive Z & Pipette Module

X Transition And Drive Y Transition And drive 1 12
FlexiCct 12 way
J2 J8a J7b
Y Motor FlexiCct 12 way
J3 J1 J8b J7a
1 1 12 1
FlexiCct 12 way FlexiCct 12 way Z Encoder
J8a J3b J2 J3 J6
FlexiCct 12 way Z Home
J8b J3a J5
Z Motor
J15 J1
Y Home
J5
Y Encoder
J6
J7
Solenoid 1
J4
Solenoid 2
J9 DYNEX TECHNOLOGIES (Guernsey) Ltd
X Encoder
J6 Rue Du Commerce
X Home Switch
Interconnect Key J5 St Peter Port
X Motor
J1 Guernsey, GY1 2HX
Mating Plug/Socket
A DSX Overall Schematic A
FlexiCct
Cable harness
Sensors/ Motors etc
Size FCSM No. DWG No. Rev
Ribbon Cable A3
Scale Sheet
1 of 6
1 2 3 4 5 6 7 8
2. Back Plane
2.1.1. Schematic
2.1.2. PCB Layout

1 2 3 4 5 6 7 8

J1 J7 J13
RSSR1 RSSR2 RSSR3
1 1 1 1 N/A NEW DESIGN PAH 28/9/98
2 2 2
3
+12v
3
+12v
3
+12v 2 N/A Specification Change KDU Sept 28 98
4 4 4
5
6
TX1
5
6
TX7
5
6
TX13 3 N/A Development Mods KDU 29 Sep 99
RX1 RX7 RX13
7
8
DSX1
7
8
DSX7
7
8
DSX13 4 3972 Connectors to take port Nos. KDU 17 Jan 00
FS1 FS7 FS13
9 9 9
D FSR1 FSR7 FSR13 D
10 10 10
Connections to Comms Board
J17A J17C J17B
J2 J8 J14
FS1 FS2 FS3
1A 1C 1B RSSR1 RSSR2 RSSR3
FSR1 FSR2 FSR3 1 1 1
2A 2C 2B
FS4 FS5 FS6 2 2 2
3A 3C 3B
4A 4C 4B +12v +12v +12v
FS7 FS8 FS9 4 4 4
5A 5C 5B
6A 6C 6B TX2 TX8 TX14
FS10 FS11 FS12 6 6 6
7A 7C 7B RX2 RX8 RX14
FSR10 FSR11 FSR12 7 7 7
8A 8C 8B DSX2 DSX8 DSX14
FS13 FS14 FLOATSW1 8 8 8
9A 9C 9B FS2 FS8 FS14
FSR13 FSR14 FLOATSW2 9 9 9
10A 10C 10B FSR2 FSR8 FSR14
FLOATSW3 FLOATSW4 FLOATSW5 10 10 10
11A 11C 11B
RX1 RX2 FSWRet
12A 12C 12B
TX1 TX2 RX3
13A 13C 13B J28
RX4 RX5 TX3
14A 14C 14B J3 J9 J18 FLOATSW1
TX4 TX5 RX6 1
15A 15C 15B RSSR1 RSSR2 FSWRet
RX7 RX8 TX6 1 1 1 +12V 2
16A 16C 16B FLOATSW2
TX7 TX8 RX9 2 2 2 +12V 3
17A 17C 17B FSWRet
RX10 RX11 TX9 3 3 3 +12V 4
18A 18C 18B +12v +12v FLOATSW3
TX10 TX11 RX12 4 4 4 +12V 5
19A 19C 19B FSWRet
RX13 RX14 TX12 5 5 5 C+24V 6
20A 20C 20B TX3 TX9 FLOATSW4
TX13 TX14 RSSR1 6 6 6 7
21A 21C 21B RX3 RX9 PowerFail FSWRet
RSSR3 RSSR2 Chassis 7 7 7 8
22A 22C 22B DSX3 DSX9 FLOATSW5
Mon48v Chassis Mon24v 8 8 8 9
23A 23C 23B FS3 FS9 FSWRet
C Mon12v MonRet +12v Chassis 9 9 9 10 C
24A 24C 24B FSR3 FSR9
Chassis 10 10 10 11
25A 25C 25B
PowerFail Chassis Chassis 11 12
26A 26C 26B
RSSR1 DSX1 DSX2 12 13
27A 27C 27B
DSX3 DSX4 RSSR2 13 M1_+24v_1 14
28A 28C 28B J4 J10
DSX5 DSX6 DSX7 14 M1_+24v_2
29A 29C 29B RSSR1 RSSR3 5566-14
RSSR3 DSX8 DSX9 1 1 15 M1_0v_1
30A 30C 30B
DSX10 DSX11 DSX14 2 2 16 M1_0v_2
31A 31C 31B
DSX12 DSX13 Chassis 3 3 17 M2_+24v_1
32A 32C 32B +12v +12v
4 4 18 M2_+24v_2 To X Drive and transition
DIN41612C96 DIN41612C96 DIN41612C96 5 5
TX4 TX10 J29
6 6
RX4 RX10
Connection To XY Board 7 7 C+24V 1
DSX4 DSX10 To Interlock Switches
8 8 2
J16A J16B FS4 FS10 XYGND
9 9 3
XYVCC XYVCC FSR4 FSR10 J15 XHOME
1A 1B 10 10 4
XYGND XYGND XBOOST
2A 2B M2_+24v_2 1 5
XHOME YHOME XBRAKE
3A 3B M2_+24v_1 2 6
XYGND XYGND XCLK
4A 4B 3 7
ENCXA ENCYA J5 J11 XDIRN
5A 5B 4 8
ENCXB ENCYB RSSR2 RSSR3 XRESET
6A 6B 1 1 5 9
XYGND XYGND YHOME
7A 7B 2 2 6 10
XDIRN YDIRN YBOOST
8A 8B 3 3 M1_+24v_1 7 11
XRESET YRESET +12v +12v YBRAKE
9A 9B 4 4 M1_+24v_2 8 12
XYGND XYGND YCLK
10A 10B 5 5 M1_0v_1 9 13
XCLK YCLK TX5 TX11 YDIRN
11A 11B 6 6 M1_0v_2 10 14
XYGND XYGND RX5 RX11 YRESET
12A 12B 7 7 11 15
XBOOST YBOOST DSX5 DSX11 ENCXA
13A 13B 8 8 12 16
B XBRAKE YBRAKE FS5 FS11 ENCXB B
14A 14B 9 9 17
XYGND XYGND FSR5 FSR11 ENCYA
15A 15B 10 10 18
XYRX XYDSR ENCYB
16A 16B 19
XYTX XYFS XYGND
17A 17B 20
XYGND XYRSSR XYTX
18A 18B 21
XYGND XYGND J6 J12 XYRSSR
19A 19B 22
XYFSR RSSR2 RSSR3 XYRX
20A 20B 1 1 23
XYDSR
21A 21B 2 2 24
XYFS
22A 22B 3 3 25
+12v +12v XYFSR
23A 23B 4 4 26
XYVCC
24A 24B 5 5 27
+12v +12v TX6 TX12 XYGND
25A 25B 6 6 28
+12v +12v RX6 RX12 Mon48v
26A 26B 7 7 29
DSX6 DSX12 Mon24v
27A 27B 8 8 30
FS6 FS12 MonRet
28A 28B 9 9 31
+12v +12v FSR6 FSR12 Mon12v
29A 29B 10 10 32
+12v +12v XYGND
30A 30B 33
XYVCC
31A 31B 34
XYVCC XYVCC
32A 32B
DIN41612B64AB DIN41612B64AB
FANS DYNEX TECHNOLOGIES (Guernsey) Ltd

Rue Du Commerce
St Peter Port
M2_+24v_2 M2_+24v_2 Guernsey, GY1 2HX
1 1
A J27 J26 DSX Backplane A
0507001 2 2 1 1
M2_+24v_2 M2_+24v_2
1 1 Size FCSM No. DWG No. Rev
J25 J24
2 2
A3 0507-04 4
Scale Sheet
1 of 1
1 2 3 4 5 6 7 8
3. Communications Module
3.1.1. Schematic
3.1.2. PCB Layout

Dynex Technologies (Guernsey) Ltd. Comms Module Hardware Description
1. Scope of This Document

This document is intended to describe the interaction of the Communications Module
electronics to control all of the various internal functions and the results of the operation
of various sensors.
2. References
1 Comms Module Requirements
2 Hitachi H8/3397 Series, H8/3337, H8/3334Y F-ZTAT Hardware Manual
3 Maxim MAX705-MAX708/MAX813L Data Sheet
3. Circuit Block Diagram
Non Vol Storage
Power and
Float switch
monitoring
Flash Upgrade
Controlt
Controller Address Bus A(15..0) A(15..4) Address Decoding
Interrupt Decoding
S(4..0)
Data Bus Data Bus Data Bus
A( 4..0) A( 9..0)
UARTS & RS232

SRAM Flash Selection DSR Test
Level Converters
__________________________________________________________________________________
Comms Module.doc 1 Revision 1
CONFIDENTIAL for Internal use ONLY
4. Circuit Functions
4.1. Flash upgrade Control

Switches the 12v Power supply through to the Microcontroller to force it into the
flash programming mode.
4.2. Address Decoding

Using a Vantis/Amd MACH111 device the various Memory mapped device
addresses are decoded. The maximum delay on signals is 15nS. To ensure the
maintenance of relative timings the Read and Write Signals from the micro-
controller have also been routed through this chip and subjected to the same delay.
Addresses have been chosen to reduce the decoding requirement as much as

possible.
4.2.1. UART Base Addresses
Port Address
Number
0 F400
1 F410
2 F420
3 F430
4 F440
5 F450
6 F460
7 F470
8 F480
9 F490
10 F4A0
11 F4B0
12 F4C0
__________________________________________________________________________________
13 F4D0
14 F4E0
15 F4F0
4.2.2. SRAM Addressing

Addresses from F000 to F3FF are all valid SRAM addresses
4.2.3. Flash Control Ports Addresses

• Flash ports 0 to 7 F500
• Flash ports 8 to 15 F540
4.2.4. Power Monitor Address

• Power Monitors F581 (bottom three bits)
4.2.5. DSR/DTR Addresses

• DSR/DTR Ports 0-7 F582
Ports 8-15 F583
4.2.6. Float Switches State Address

• Float switches F5C0
4.3. Interrupt Decoding
4.3.1. UARTS
Each UART produces an interrput signal for each channel. These Interrupt
signals are grouoped in fours to produce an interrupt signal for each UART.
• Comms Port • IRQ
• 0-3 • 0
• 4-7 • 1
• 8-11 • 2
__________________________________________________________________________________
• 12-15 • 3
4.3.2. System Monitoring

A change in the motor supply voltages, or in the DSR/DTR states will
produce an interrupt
Any change in the state of the 12, 24 or 48 volt supplies, or DSR/DTR states
will generate IRQ6. The service routine should read the state of the inputs to
determine the action to be taken.
Should the Mains supply to the system fail then the PSU will generate a NMI
giving at least 20mS warning of loss of dc supplies.
4.4. DSR/DTR Test

The DSR/DTR input from each module is around +/- 12v, this has to be changed to
logic levels for monitoting by he micro-controller. A low current Opto-isolator was
chosen which requires only 0.5mA to drive the LED, however the –12v reverse
voltage from the RS232 level changer is excessive. A low current LED has been
introduced to limit the reverse voltage.
The signals are passed to a programmable logic device which also acts as a three
state bus driver. The device produces an interrupt if any change of state takes place.
4.5. Power Monitoring.

Three identical channels with the exception of the Opto-Coupler LED dropping
resistor value. The rersistor value is such as to limit the LED current to 5mA in each
channel
4.6. Float Switches

The float switches should be made for valid results. If the circuit is broken an non
valid return will be made. This could be due to the absence of the switch an open
circuit lead, or the correct breaking of the switch when the washer bottle is empty
(full in the case of waste).
In order to limit switch bounce and noise interference each switch input is filtered
such that a 1mS pulse is required before a change in switch state is detected.
The switches are interfaced to the data bus via a three state bus driver at the address
above.
__________________________________________________________________________________
4.7. Flash Selection.

Updating other module programs via flash upgrade will be supervised by this
module. An isolated signal FS*/FSR* is produced by opto-couplers. Two off 74574
D type latches are used to set opto-coupler LED cathodes low to switch on the
output transistor. Ports 0-7 are controlled by the 74574 ast address F500 and Ports
8-15 by that at F540. Normally only one bit from the 16 will be set low.
4.8. SRAM
The SRAM is addressable at the range of addresses given above. The direct
addressing gives access to only 1kbyte of storage. This memory is extended by using
the page principal, by connecting the upper 5 address pins to I/O bits on the
controller 32 1kbyte pages can be accessed.
4.9. UARTS
The addresses given above are only the base addresses, address lines A(2..0) are also
routed to each UART allowing each channel to be accessed and also the control
regusters. Refer to the data sheet for details
5. Voltage generation and regulation

DC voltage of +12 volts +/- 5% is provided to the Comms Module from an external
power supply.A linear regulator converts the 12v to 5 volts to drive the logic devices.
6. H8 microcomputer
The Comms Module hardware is based around the Hitachi H8/3337F single-chip
microcomputer. This microcomputer provides 60Kbytes of Flash ROM and 2Kbytes of
RAM. The H8/3337F has the following internal peripheral capabilities:[2]
9 ports, providing 58 I/O and 8 Input lines
two 8-bit timers (TMR0, TMR1)
one 16-bit free-running counter (FRC)
two digital to analog channels (DA0, DA1), with 8-bit resolution
eight analog to digital channels (AN0 through AN7), with 10-bit resolution
two serial communications channels (COM0, COM1)
two pulse width modulation channels (PWM0, PWM1)
__________________________________________________________________________________
6.1. Port Configurations and Operating Mode [2]

The memory and port requirements force the use of Mode 1. In this mode the
controller is able to access external memory and peripherals which are memory
mapped
An external ST93C46CB1 serial EEPROM connected to port P4 is used to store

setup and calibration information for the Comms Module.
An MAX705[3] µprocessor supervisor IC is connected to the Reset input on the H8

to provide reset on power up.
The port I/O pin assignments are detailed in the “I/O Pin Assignments” section of
this document.
6.2. H8 Operating Frequency

The H8/3337Y XTAL operating frequency is 16 MHz.
6.3. Packaging
The Comms Module shall use the 84-pin, PLCC (Plastic Leadless Chip Carrier),
Flash Memory with 2kbytes RAM
Hitachi part number HD64F3337YCP16.
6.4. 8-bit Timer, TMR0

Supplies the serial Clock for the Non-Vol Storage

Not Used.
6.6. 16-bit Free Running Counter (FRC)

Not Used.
6.7. Digital to Analog
6.7.1. Channel 0 (DA0)

Not Used.

Not Used.
__________________________________________________________________________________
6.8. A/D converter
6.8.1. Channel AN0

Not used.
6.8.2. Channel AN1

Not used.
6.8.3. Channel AN2

Not used.
6.8.4. Channel AN3

Not used.
6.8.5. Channel AN4

Not used.
6.8.6. Channel AN5

Not used.
6.8.7. Channel AN6

Not used.
6.8.8. Channel AN7

Not used.
6.9. Serial Communications
6.9.1. Channel 0 (COM0)

Not Used

Communications with Controlling Computer System
__________________________________________________________________________________
6.10. Pulse Width Modulation
6.10.1. Channel PWM0

Not used.

Not used.
7. Module Functions
8. Serial Communications with Controller

Commands and test data are transferred between the H8 and the external PC controller
via a serial RS-232 interface. Interface drivers and receivers are used between the COM1
serial communications channel on the H8 and the interface connector to provide proper
RS-232 signal levels to the controller.
DTR is signalled via Port 6-7
DSR is received on Port 6-5
9. I/O Pin Assignments

The table below lists the I/O pin assignments for the H8/338 microcomputer. Column 1 is
the port pin assignment and functional name assigned to the pin by the manufacturer.
Column 2 is the logical name used within the LM. Column 3 is a brief description of the
logical function as applied to the LM.
Port pins can generally be used as Input or Output or may have alternate functions. The
predominant utilization of the port pin is shown in boldface type.
Port P1 is output only
P1-0/A0 A0 78 Address Bus
__________________________________________________________________________________
Port P2 is bi-directional only
P3-0/D0 D0 79 Data Bus
Port P4 is mixed
__________________________________________________________________________________
P4-0/TMCI-0 E_DO 52
P4-1/TMO-0 E_SCLK 53 Output
P4-2/TMRI-0 E_CS 54 Output
P4-3/TMCI-1 E_DI 55
P4-4/TMO-1 URESET 56 Output
P4-5/TMRI-1 STATUS 57 Output
P4-6/PW0 ResetSys 58 Output
P4-7/PW1 Not used 59
Port P5 is not Used
P5-0/TxD-0 TXD 22 Not Used
P5-1/RxD-0 RXD 21 Not Used
P5-2/SCK-0 DSR 20 Not Used
Port P6 is mixed
P6-0/FTCI S0 33 Output SRAM Page Select Bus
P6-1/FTOA S1 34 Output SRAM Page Select Bus
P6-2/FTIA S2 35 Output SRAM Page Select Bus
P6-3/FTIB S3 36 Output SRAM Page Select Bus
P6-4/FTIC S4 37 Output SRAM Page Select Bus
P6-5/FTID DSR0 38 Input
P6-6/FTOB/IRQ6 IRQ6 39 Input
P6-7/IRQ7 DTR0 40 Output
Port P7 is input only
P7-0/AN0 VCCMon 43 Analogue Input
__________________________________________________________________________________
P7-1/AN1 12vMon 44 Analogue Input
P7-2/AN2 Not Used 45 Not Used
P7-6/AN6/DA0 Not Used 49 Not Used
Port P8 is mixed
P8-0 FCLK0 5 Output
P8-1 FD0 6 Output
P8-2 FMR0 7 Output
P8-3 FDET0 8 Input
P8-4/TxD1/IRQ3 T0 9 Output
P8-5/RxD1/IRQ4 R0 10 Input
P8-6/SCK1/IRQ5 IRQ5 11 Input
P9-0/ADTRG/IRQ2 IRQ2 32 Input
P9-1/IRQ1 IRQ1 31 Input
P9-2/IRQ0 IRQ0 30 Input
P9-3/RD IOR 29 Output
P9-4/WR IOW 28 Output
P9-5/AS AS 27 Output
P9-6/Φ Not used 26 Not used
__________________________________________________________________________________
P9-7 Not used 25 Not used
NMI NMI 17 Input
__________________________________________________________________________________
1 2 3
COMMS FLASH UPGRADE
4 5 6 7 8
AND STATUS LED
J1 REV. ECO No. CHANGE DESCRIPTION INI. DATE
1
2 1 N/A NEW DESIGN PAH
3
MICROCONTROLLER RS232 CONVERTORS 4 2-4 N/A Development Mods KDU 28/05/99
0501052.asc 0501054.asc
GND MOLEX 4
CONNECTIONS TO BACKPLANE 5 3971/xxxx Move Heat Sink,Disable NMI,change EEPROM KDU 13 Jan 00
A[0..15]
FS0 A[0..15]
D[0..7]
EXLED D[0..7]
ResetSys
ResetSys
D IRQ[0..6] J2A J2C J2B D
IRQ[0..6] AS
FS1 FS2 FS3
IOW 1A 1C 1B
IRQ6 IOR FSR1 FSR2 FSR3
IRQ6 IOR 2A 2C 2B
FS4 FS5 FS6
URESET 3A 3C 3B
NMI FSR4 FSR5 FSR6
NMI S[0..4] 4A 4C 4B
FS7 FS8 FS9
5A 5C 5B
T[0..16] TX[0..16] FSR7 FSR8 FSR9
T[0..16] T[0..16] TX[0..16] 6A 6C 6B
R[0..16] RX[0..16] FS10 FS11 FS12
R[0..16] R[0..16] RX[0..16] 7A 7C 7B
FSR10 FSR11 FSR12
DTR0 DTR0 8A 8C 8B
VCC DTRX0 FS13 FS14 FLOATSW1
DSR0 DSR0 DTRX0 9A 9C 9B
VCC DSRX0 FSR13 FSR14 FLOATSW2
VCC DSRX0 10A 10C 10B
FLOATSW3 FLOATSW4 FLOATSW5
GND VCC 11A 11C 11B
RX1 RX2 GND
GND 12A 12C 12B
GND TX1 TX2 RX3
13A 13C 13B
GND RX4 RX5 TX3
14A 14C 14B
SRAM, UARTS, DECODE MODULE FLASH UPGRADE TX4 TX5 RX6
15A 15C 15B
0501053.asc 0501055.asc RX7 RX8 TX6
16A 16C 16B
TX7 TX8 RX9
17A 17C 17B
RX10 RX11 TX9
A[0..15] A[0..15] 18A 18C 18B
D[0..7] D[0..7] TX10 TX11 RX12
D[0..7] D[0..7] 19A 19C 19B
RX13 RX14 TX12
20A 20C 20B
TX13 TX14 GND
AS 21A 21C 21B
GND GND M_GND
IOW IOW 22A 22C 22B
Mon48v M_GND Mon24v
IOR 23A 23C 23B
Mon12v C_GND C_GND
IRQ[0..5] URESET 24A 24C 24B
SysCS C_GND
SysCS S[0..4] 25A 25C 25B
SCLK FS[1..16] PowerFail C_GND C_GND
SCLK Flash0 Flash0 FS[1..16] 26A 26C F1 26B
Float GND DSX1 DSX2
C Float Flash1 Flash1 27A 27C MF-R500 27B C
DSX3 DSX4 C_GND GND EXTERNAL RS232
T[0..16] 28A 28C 28B
FSR[1..16] DSX5 DSX6 +12v DSX7
R[0..16] FSR[1..16] 29A 29C 29B
VCC VCC GND DSX8 DSX9
30A 30C 30B
DSX10 DSX11 DSX14 J5
VCC VCC 31A 31C 31B
DSX12 DSX13 GND
GND GND 32A 32C 32B 1
DSX15
2
GND GND DIN41612C96-RA DIN41612C96-RA DIN41612C96-RA RX15
3
FSR15
4
TX15
5
FS15
6
0501056.asc
7
System Monitoring
8
SysCS IRQ6
SysCS IRQ6 9
IOR D[0..7]
IOR D[0..7] 10
ResetSys Mon48v GND
ResetSys Mon48v
M_GND VCC VCC VCC VCC VCC
M_GND
DSX[1..16] Mon24v J4
DSX[1..16] Mon24v
Mon12v
Mon12v 1
SCLK C_GND R18 R21 R27 R25 R20 DSX16
SCLK C_GND 2
A[0..15] GND 100K 100K 100K 100K 100K RX16
A[0..15] GND 3
Float FSR16
Float 4
IOR FLOATSW1 FLOATSW2 FLOATSW3 FLOATSW4 FLOATSW5 TX16
IOR 5
NMI FS16
NMI 6
+ C11 + C16 + C18 + C17 + C13
0.068 100v 0.068 100v 0.068 100v 0.068 100v 0.068 100v 7
PowerFail FLOATSW[1..5]
PowerFail FLOATSW[1..5] 8
9
10
B GND GND GND GND GND GND B
U10
1mS Filter +12V LM7805 VCC
1 3
Vin Vout
HOST RS232
GND
+ C23 +
C15 C34 C14
220uF J3
0.1 22 25v 0.1
2
1
DSRX0
R23 2
RX0
3
LINK 4
C_GND GND TX0
5
6
DTRX0
7
VCC
8
9
10
C35 C81 C1 C22 GND
+ + + +
22 25v 22 25v 22 25v 22 25v
GND DYNEX TECHNOLOGIES (Guernsey) Ltd

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Communications A
1 off Heat Sink 17 C/W U10

1 off DIP 24 (0.3) Skt 24 Way U23
1 off PLCC Socket 84 Way U4 A3 0501-05 5
1 off PLCC Socket 44 Way U3 Scale Sheet

1 off PLCC Socket 44 Way U2 1 of 6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

VCC
R26
10K
FLASH UPGRADE CONTROL

D D1 D
VCC 1N4148
+12V Q3
R36 1 BSS110 3 R24
10K 82R
1
R35 R22
2 10K 22K
FS0 Q4
2
FS0 BSS110D4
3
C25 R32 1N4148 U11A
1
0.1 10K
VCC VCC
Q2 1 2
R33 2 2N4401
10K R19 C6 C8
GND D5 R34 10K 74HC14 0.1 0.1
VCC 1N4148 10K
3
GND GND
VCC U1A D[0..7]
D3 D[0..7]
R28 4
1N4148 PRE
10K 3 5 GND
CLK Q VCC
2 6 U4
D Q
1
CLR
+ C5 D6 1 84 D5
C21 74HC74A P3_6/HDB_6/D_6 P3_5/HDB5/D5
0.1 2 83 D4
10 10v Vss P3_4/HDB4/D4
D7 3 82 D3
C P3_7/HDB_7/D_7 P3_3/HDB3/D3 C
GND 4 81 D2
GND Vss P3_2/HDB2/D2
GND FCLK0 5 80 D1
P8_0/HA_0 P3_1/HDB1/D1
FD0 6 79 D0 A[0..15]
P8_1/GA20 P3_0/HDB0/D0 A[0..15]
FMR0 7 78 A0
P8_2/CS1 P1_0/A0
FDET0 8 77 A1 VCC
P8_3/IOR P1_1/A1
T0 9 76 A2
RESET CONTROL T0 P8_4/IOW/IRQ3/TxD1 P1_2/A2
1
R0 10 75 A3
R0 P8_5/CS2/IRQ4/RxD1 P1_3/A3 Q1
VCC IRQ5 11 74 A4 2
P8_6/IRQ5/SCK1/SCL P1_4/A4
RESET0 12 73 A5 BSS110
RES P1_5/A5
13 72 A6
XTAL P1_6/A6
R31 14 71 A7 EXLED
EXTAL P1_7/A7 EXLED
10K X1 15 70
3
MD_1 Vss
D2 16 69 A8 R3
MD_0 P2_0/A8
FMR0 U8 17 68 A9 GND 620R
NMI NMI P2_1/A9
1 8 GND FVPP0 18 67 A10
1N4148 MR WDO 16MHz STBY P2_2/A10
+ 6 19 66 A11
WDI Vcc P2_3/A11
1
C20 5 C4 C3 VCC 20 65 A12
10 10v PFO 22pF 22pF R29 P5_2/SCK0 P2_4/A12
4 7 RESET0 21 64
PFI RESET P5_1/RxD0 Vss LED1
4K7 22 63 A13
P5_0/TxD0 P2_5/A13 LED GREEN
GND MAX705CPA GND 23 62 A14 GND
Vss P2_6/A14
VCC 24 61 A15 VCC
GND Vss P2_7/A15
25 60
R304K7 P9_7/WAIT/SDA Vcc
26 59 R164k7
2
C12 VCC P9_6/CLK P4_7/PW1
AS 27 58
0.1 AS P9_5/AS P4_6/PW0 ResetSys
IOW 28 57 STATUS GND
IOW P9_4/WR P4_5/TMRI1/HIRQ12
IOR 29 56 URESET
IOR P9_3/RD P4_4/TMO1/HIRQ1 URESET
GND IRQ0 30 55 E_DI
P9_2/IRQ0 P4_3/TMCI1/HIRQ11
B IRQ1 31 54 E_CS B
P9_1/IRQ1/EIOW P4_2/TMRI0
IRQ2 32 53 E_SCLK
P9_0/IRQ2/ADTRG/ECS2 P4_1/TMCO0
S0 33 52 E_DO NON VOLATILE STORAGE
P6_0/KEYIN0/FTCI P4_0/TMCI0
IRQ[0..5] S1 34 51 VCC +12V
IRQ[0..5] P6_1/KEYN1/FTOA AVss
S2 35 50
P6_2/KEYN2/FTIA P7_7/AN7/DA1 R124k7 VCC
S3 36 49 GND U7
P6_3/KEYN3/FTIB P7_6/AN6/DA0
S4 37 48 R9 R13 E_CS 1
P6_4/KEYN4/FTIC P7_5/AN5 CS
S[0..4] 38 47 10K 22K E_SCLK 2 C9
S[0..4] P6_5/KEYN5/FTID P7_4/AN4 SCLK
39 46 E_DI 3 0.1
DSR0 P6_6/KEYN6/FTOB/IRQ6 P7_3/AN3 DI
40 45 E_DO 4
DTR0 P6_7/KEYN8/IRQ7 P7_2/AN2 DO
VCC 41 44 6
Vss P7_1/AN1 VCC PE GND
42 43 7
AVcc P7_0/AN0 PRE
IRQ6
R10 R14 GND NM93CS66N
GND H8/3337YF/16 10K 10K
VCC
VCC
GND
GND
GND
DYNEX TECHNOLOGIES (Guernsey) Ltd

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Communications (Control) A

A3 0501-05
Scale Sheet
2 of 6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
D[0..7]
D[0..7]
U18 U19 U22 U21

D D0 66 17 T1 D0 66 17 T5 D0 66 17 T9 D0 66 17 T13 D
D0 TXA D0 TXA D0 TXA D0 TXA
D1 67 7 R1 VCC D1 67 7 R5 VCC D1 67 7 R9 VCC D1 67 7 R13 VCC
D1 RXA D1 RXA D1 RXA D1 RXA
D2 68 11 D2 68 11 D2 68 11 D2 68 11
D2 CTSA D2 CTSA D2 CTSA D2 CTSA
D3 1 14 D3 1 14 D3 1 14 D3 1 14
D3 RTSA D3 RTSA D3 RTSA D3 RTSA
D4 2 10 R37 D4 2 10 R38 D4 2 10 R41 D4 2 10 R40
D4 DSRA D4 DSRA D4 DSRA D4 DSRA
D5 3 12 4K7 D5 3 12 4K7 D5 3 12 4K7 D5 3 12 4K7
D5 DTRA D5 DTRA D5 DTRA D5 DTRA
D6 4 9 D6 4 9 D6 4 9 D6 4 9
D6 CDA D6 CDA D6 CDA D6 CDA
D7 5 8 D7 5 8 D7 5 8 D7 5 8
D7 RIA D7 RIA D7 RIA D7 RIA
DIOW 18 19 T2 DIOW 18 19 T6 DIOW 18 19 T10 DIOW 18 19 T14
IOW TXB IOW TXB IOW TXB IOW TXB
DIOR 52 29 R2 DIOR 52 29 R6 DIOR 52 29 R10 DIOR 52 29 R14
IOR RXB IOR RXB IOR RXB IOR RXB
A[0..15] 25 25 25 25
A[0..15] CTSB CTSB CTSB CTSB
A0 34 22 A0 34 22 A0 34 22 A0 34 22
A0 RTSB A0 RTSB A0 RTSB A0 RTSB
A1 33 26 A1 33 26 A1 33 26 A1 33 26
A1 DSRB A1 DSRB A1 DSRB A1 DSRB
A2 32 24 A2 32 24 A2 32 24 A2 32 24
A2 DTRB A2 DTRB A2 DTRB A2 DTRB
27 27 27 27
CDB CDB CDB CDB
CS1 16 28 CS5 16 28 CS9 16 28 CS13 16 28
CSA RIB CSA RIB CSA RIB CSA RIB
CS2 20 CS6 20 CS10 20 CS14 20
CSB CSB CSB CSB
CS3 50 51 T3 CS7 50 51 T7 CS11 50 51 T11 CS15 50 51 T15
CSC TXC CSC TXC CSC TXC CSC TXC
CS4 54 41 R3 CS8 54 41 R7 CS12 54 41 R11 CS16 54 41 R15
CSD RXC CSD RXC CSD RXC CSD RXC
45 45 45 45
CTSC CTSC CTSC CTSC
I1 15 48 I5 15 48 I9 15 48 I13 15 48
INTA RTSC INTA RTSC INTA RTSC INTA RTSC
I2 21 44 I6 21 44 I10 21 44 I14 21 44
INTB DSRC INTB DSRC INTB DSRC INTB DSRC
I3 49 46 I7 49 46 I11 49 46 I15 49 46
INTC DTRC INTC DTRC INTC DTRC INTC DTRC
VCC I4 55 43 VCC I8 55 43 VCC I12 55 43 VCC I16 55 43
INTD CDC INTD CDC INTD CDC INTD CDC
65 42 65 42 65 42 65 42
INTSEL RIC INTSEL RIC INTSEL RIC INTSEL RIC
URESET 37 53 T4 URESET 37 53 T8 URESET 37 53 T12 URESET 37 53 T16
C URESET RESET TXD RESET TXD RESET TXD RESET TXD C
63 R4 63 R8 63 R12 63 R16
RXD RXD RXD RXD
35 59 SCLK 35 59 SCLK 35 59 SCLK 35 59
XTAL1 CTSD XTAL1 CTSD XTAL1 CTSD XTAL1 CTSD
X2 SCLK 36 56 36 56 36 56 36 56
XTAL2 RTSD XTAL2 RTSD XTAL2 RTSD XTAL2 RTSD
60 60 60 60
DSRD DSRD DSRD DSRD
13 58 13 58 13 58 13 58
VCC DTRD VCC DTRD VCC DTRD VCC DTRD
1.8432MHz 30 61 30 61 30 61 30 61
VCC CDD VCC CDD VCC CDD VCC CDD
C27 C26 VCC 47
VCC RID
62 VCC 47
VCC RID
62 VCC 47
VCC RID
62 VCC 47
VCC RID
62
22pF 22pF 64 64 64 64
VCC VCC VCC VCC
38 38 38 38
RXRDY RXRDY RXRDY RXRDY
6 39 6 39 6 39 6 39
GND GND TXRDY GND TXRDY GND TXRDY GND TXRDY
23 23 23 23
GND GND GND GND
GND 40 GND 40 GND 40 GND 40
GND GND GND GND
57 57 57 57
GND GND GND GND
T[1..16]
T[1..16]
ST16C554D ST16C554D ST16C554D ST16C554D
VCC VCC VCC
VCC
R[1..16]
R[1..16] VCC
C29 C30 C33
C2
0.1 0.1 0.1
AS 0.1
AS C32
GND GND GND 0.1
SRAM 0xF000 - 0xF3FF
SCLK IRQ[0..5] GND
SCLK IRQ[0..5]
U23 U3 U20
GND
I16 1 A13 10 43 SysCS A0 10 11 D0
IN CLK IN 0 IO 31 SysCS A0 O0
I15 2 14 IRQ0 A9 11 42 A4 A1 9 12 D1
IN IO IN 1/CLK0 IO 30 A1 O1
I14 3 15 IRQ2 A11 13 41 SCS A2 8 13 D2
IN IO R39 IN 2/CLK1 IO 29 A2 O2
I13 4 16 A15 32 40 A8 A3 7 15 D3
IN IO VCC IN 3 IO 28 A3 O3
B I12 5 17 4K7 A14 33 39 CS16 A4 6 16 D4 B
IN IO IN 4/CLK2 IO 27 A4 O4
I11 6 18 I1 A5 35 38 Flash0 A5 5 17 D5
IN IO IN 5/CLK3 IO 26 Flash0 A5 O5
I10 7 19 I2 CS1 2 37 AS A6 4 18 D6
IN IO IO 0 IO 25 A6 O6
I9 8 20 I3 CS3 3 36 DIOR A7 3 19 D7
IN IO IO 1 IO 24 A7 O7 VCC
I8 9 21 I4 A10 4 31 A7 A8 25
IN IO IO 2 IO 23 A8
I7 10 22 IRQ1 CS11 5 30 CS15 S[0..4] A9 24
IN IO IO 3 IO 22 S[0..4] A9
I6 11 23 IRQ5 6 29 CS14 S0 21 C28
IN IO Flash1 IO 4 IO 21 A10
I5 13 7 28 A12 S1 23 0.1
IN Float IO 5 IO 20 A11
8 27 CS13 S2 2
IOW IO 6 IO 19 A12
PALCE22V10Q25PC4 DIOW 9 26 CS7 S3 26
IO 7 IO 18 A13 GND
VCC CS12 14 25 CS5 S4 1
IO 8 IO 17 A14
CS10 15 24 CS2 VCC
IO 9 IO 16
CS9 16 21 CS4 SCS 20 28
C31 IO 10 IO 15 CE VCC
CS8 17 20 A6 DIOR 22
0.1 IO 11 IO 14 OE
CS6 18 19 IOR DIOW 27 14
IO 12 IO 13 IOR WE GND
GND MACH211 32Kx8 SRAM GND
VCC
VCC
GND DYNEX TECHNOLOGIES (Guernsey) Ltd

GND Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Communications (UARTS A

A3 0501-05 5
Scale Sheet
3 of 6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
RS232 LEVEL CONVERTERS

D D
VCC
VCC
VCC VCC VCC VCC
C36
0.1 C42 C47 C45
22 25v 22 25v C39 22 25v
C40
0.1
0.1
+ + +
GND U24 U27 U26
6 2 6 2 6 2
V- V+ V- V+ GND V- V+
GND
C52 1 4 C55 1 4 C60 1 4
+
22 25v C1+ C2+ +
22 25v C1+ C2+ +
22 25v C1+ C2+
+ C37 + C51 + C48 + C54 + C46 + C53
22 25v 22 25v 22 25v 22 25v 22 25v 22 25v
GND 3 5 GND 3 5 GND 3 5
C1- C2- C1- C2- C1- C2-
R0 9 8 RX0 R5 9 8 RX5 R11 9 8 RX11
R2OUT R2IN R2OUT R2IN R2OUT R2IN
12 13 DSRX0 R6 12 13 RX6 R12 12 13 RX12
T0 10 7 TX0 T5 10 7 TX5 T11 10 7 TX11
T2IN T2OUT T2IN T2OUT T2IN T2OUT
DTR0 11 14 DTRX0 T6 11 14 TX6 T12 11 14 TX12
MAX232 MAX232 MAX232
DSR0 VCC VCC

VCC VCC VCC
VCC
C49 C67 C43
22 25v C63 22 25v C38 22 25v
C 0.1 0.1 C
C41
+ + +
U28 U31 U25
0.1 6 2 6 2 6 2
V- V+ GND V- V+ GND V- V+
GND C57 1 4 C75 1 4 C59 1 4
R[0..16] +
22 25v C1+ C2+ +
22 25v C1+ C2+ +
22 25v C1+ C2+
R[0..16]
+ C50 + C56 + C68 + C74 + C44 + C58
22 25v 22 25v 22 25v 22 25v 22 25v 22 25v
T[0..16]
T[0..16] GND 3 5 GND 3 5 GND 3 5
C1- C2- C1- C2- C1- C2-
R1 9 8 RX1 R7 9 8 RX7 R13 9 8 RX13
RX[0..16] R2OUT R2IN R2OUT R2IN R2OUT R2IN
RX[0..16] R2 12 13 RX2 R8 12 13 RX8 R14 12 13 RX14
T1 10 7 TX1 T7 10 7 TX7 T13 10 7 TX13
T2 11 14 TX2 T8 11 14 TX8 T14 11 14 TX14
TX[0..16] T1IN T1OUT T1IN T1OUT T1IN T1OUT
TX[0..16]
DTR0
DTR0
VCC VCC
VCC VCC VCC VCC
DTRX0 C69 C66 C65

DTRX0 C64 22 25v C62 22 25v 22 25v
C61
0.1 + 0.1 + +
DSRX0 U32 U30 0.1 U29
DSRX0
6 2 6 2 6 2
GND V- V+ GND V- V+ V- V+
GND
C77 1 4 C80 1 4 C79 1 4
+
22 25v C1+ C2+ +
22 25v C1+ C2+ +
22 25v C1+ C2+
+ C70 + C76 + C72 + C73 + C71 + C78
B B
22 25v 22 25v 22 25v 22 25v 22 25v 22 25v
GND 3 5 GND 3 5 GND 3 5
C1- C2- C1- C2- C1- C2-
R3 9 8 RX3 R9 9 8 RX9 R15 9 8 RX15
R4 12 13 RX4 R10 12 13 RX10 R16 12 13 RX16
T3 10 7 TX3 T9 10 7 TX9 T15 10 7 TX15
VCC T4 11 14 TX4 T10 11 14 TX10 T16 11 14 TX16
VCC
GND
GND

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Communications (RS232) A

A3 0501-05 5
Scale Sheet
4 of 6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
F[1..16]
D U14A U17C D
VCC RN3A RN4C
1 2 1 15 FS1 1 4 5 11 FS11
VCC VCC
470R 470R
C19 F1 2 16 FSR1 F11 6 12 FSR11
0.1 CNY74-4 CNY74-4
U12 U14B U17D
GND RN3B RN4D
1 1 3 4 14 FS2 1 5 8 10 FS12
OC VCC VCC
GND 11 19 F1 470R 470R
CLK 1Q
18 F2 F2 3 13 FSR2 F12 7 9 FSR12
2Q
D0 2 17 F3
1D 3Q CNY74-4 CNY74-4
D1 3 16 F4
2D 4Q
D2 4 15 F5 U14C U16A
3D 5Q RN3C RN4E
D3 5 14 F6 1 4 5 11 FS3 1 6 1 15 FS13
4D 6Q VCC VCC
D4 6 13 F7 470R 470R
5D 7Q
D5 7 12 F8 F3 6 12 FSR3 F13 2 16 FSR13
6D 8Q
D6 8
7D CNY74-4 CNY74-4
D7 9
8D
VCC RN3D U14D RN4F U16B
MC74HC574 1 5 8 10 FS4 1 7 4 14 FS14
VCC VCC
470R 470R
U15 C24 F4 7 9 FSR4 F14 3 13 FSR14
1 0.1
Flash0 OC CNY74-4 CNY74-4
GND 11 19 F9
CLK 1Q
18 F10 U13A U16C
2Q GND RN3E RN4G
D0 2 17 F11 1 6 1 15 FS5 1 8 5 11 FS15
1D 3Q VCC VCC
D1 3 16 F12 470R 470R
Flash1 2D 4Q
D2 4 15 F13 F5 2 16 FSR5 F15 6 12 FSR15
C 3D 5Q C
D3 5 14 F14
4D 6Q CNY74-4 CNY74-4
D4 6 13 F15
5D 7Q
D5 7 12 F16 U13B U16D
6D 8Q RN3F RN4H
D6 8 1 7 4 14 FS6 1 9 8 10 FS16
7D VCC VCC
D7 9 470R 470R
8D
F6 3 13 FSR6 F16 7 9 FSR16
MC74HC574
CNY74-4 CNY74-4
RN3G U13C
1 8 5 11 FS7
VCC
470R
F7 6 12 FSR7
CNY74-4
RN3H U13D
1 9 8 10 FS8
VCC
470R
F8 7 9 FSR8
CNY74-4
RN4A U17A
D[0..7] 1 2 1 15 FS9
D[0..7] VCC
470R
F9 2 16 FSR9
CNY74-4
RN4B U17B
B 1 3 4 14 FS10 B
VCC
470R
F10 3 13 FSR10
CNY74-4
FSR[1..16]
FSR[1..16]
FS[1..16]
FS[1..16]
VCC
VCC
GND
GND

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Communications (Flash) A

A3 0501-05 5
Scale Sheet
5 of 6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VCC
VCC
VCC
C7
0.1
R1 C10
4K7 0.1
U2 GND
U9
SysCS 10 43 DS2
SysCS IN 0 IO 31 PullUpA 1
DS4 11 42 MON1 Float G1 GND
IN 1/CLK0 IO 30 IOR 15 3 D0
DS3 13 41 DS12 G2 Y1
IN 2/CLK1 IO 29 5 D1
DS0 32 40 PullUpA Y2
IN 3 IO 28 FLOATSW1 2 7 D2
SCLK 33 39 DS15 A1 Y3
D SCLK IN 4/CLK2 IO 27 FLOATSW2 4 9 D3 D
PullUpA 35 38 DS1 A2 Y4
IN 5/CLK3 IO 26 FLOATSW3 6 11 D4
A0 2 37 MON0 A3 Y5
IO 0 IO 25 FLOATSW4 10 13 D5
D2 3 36 DS9 A4 Y6 VCC RN1A RN1B
IO 1 IO 24 FLOATSW5 12
1
D4 4 31 D7 A5
IO 2 IO 23 14
D0 5 30 PullUpA A6
IO 3 IO 22 U34
IOR 6 29 FLOATSW[1..5]
IO 4 IO 21 FLOATSW[1..5] GND 74HC365
D5 7 28 D3 8 2k7 2k7
IO 5 IO 20 R4320K
8 27 D6 DSX9 1
ResetSys IO 6 IO 19
9 26 A1 7 DS8
IRQ6 IO 7 IO 18
DS10 14 25 DS8 GND 2
3
IO 8 IO 17
DS14 15 24 D1 LED4
IO 9 IO 16
DS13 16 21 MON2 DSX10 4
D[0..7]
IO 10 IO 15
DS5 17 20 DS6 R4720K 6 DS9
IO 11 IO 14 D[0..7]
DS11 18 19 DS7 GND 3
IO 12 IO 13
LED5 5
MACH211
D[0..7]
DS[15..0] HCPL2731 GND
VCC RN1C RN1D
1
A[0..15]
A[0..15]
U38
IOR
IOR VCC 8 2k7 2k7
R5120K
DSX11 1
7 DS10
C U6 VCC R15 R11 U5 R4 C
R7 GND 2
5
8 2K7 2K7 8 620R 2K7 LED12
Mon12v R8 1 Mon24v R2 1 DSX12 4
Mon12v Mon24v
2K0 7 MON0 4K7 7 MON2 R5420K 6 DS11
C_GND 2 M_GND 2 GND 3
C_GND
LED13 5
R6
Mon48v R17 4 4
Mon48v
9K1 6 MON1 6 HCPL2731 GND
150R NMI
M_GND 3 3
M_GND PowerFail
5 5
GND
HCPL2731 GND If Power Fail Required fit 1k5 (R5) HCPL2731 GND
resistor between Power Fail net
and Vcc
DSX[1..16]
DSX[1..16]
VCC RN2A RN2B VCC RN2E RN2F
VCC RN1E RN1F
1
1
U36 U35
U33
8 2k7 2k7 8 2k7 2k7
R4520K R4420K 8 2k7 2k7
DSX1 1 DSX5 1 R4220K
DSX13 1
7 DS0 7 DS4
7 DS12
GND 2 GND 2
2
7
GND 2
7
LED8 LED6
DSX2 4 DSX6 4 LED2
DSX14 4
R4920K 6 DS1 R4820K 6 DS5
R4620K 6 DS13
GND 3 GND 3
GND 3
LED9 5 LED7 5
B LED3 5 B
HCPL2731 GND HCPL2731 GND
HCPL2731 GND
VCC RN2C RN2D VCC RN2G RN2H

VCC RN1G RN1H
1
1
U40 U39
U37
8 2k7 2k7 8 2k7 2k7
R5320K R5220K 8 2k7 2k7
DSX3 1 DSX7 1 R5020K
DSX15 1
7 DS2 7 DS6
7 DS14
GND 2 GND 2
4
GND 2
9
LED16 LED14
DSX4 4 DSX8 4 LED10
DSX16 4
R5620K 6 DS3 R5520K 6 DS7
R5720K 6 DS15
GND 3 GND 3
GND 3
LED17 5 LED15 5
LED11 5
HCPL2731 GND HCPL2731 GND

HCPL2731 GND

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Communications (System Monitoring) A

A3 0501-05 5
Scale Sheet
6 of 6
1 2 3 4 5 6 7 8
4. XY Motion
4.1. Control Board
4.1.1. Schematic
4.1.2. PCB Layout
4.2. X Transition
4.2.1. Schematic
4.2.2. PCB Layout
4.3. Y Transition
4.3.1. Schematic
4.3.2. PCB Layout

Dynex Technologies (Guernsey) Ltd. XY Module Hardware Description

This document is intended to describe the interaction of the XY Module electronics to
control all of the various internal functions and the results of the operation of various
sensors. It also describes the hardware configuration of the module.
2. References
1 XY Module Requirements
4 Maxim MAX220-MAX249 Data Sheet
3.1. Board Breakdown
X Motor
XY Transition Board
FlexiCct
Module Interface Y Transition Board
34 Way ribbon
Back Plane Y Motor
FlexiCct
XY Board
XY Module Hardware Description.doc 1

Revision 1
3.2. XY Control Diagram
Encoder Counter
Connection
Flash Upgrade and
Controller To
Reset Control
Back plane
Non Vol Storage
3.3. X Motor Drive (Transition)
Sensors
Motor Driver A
To
Back To X
Plane Bit Pattern Generator
Motor
Motor Driver B
To Y Transition To Interlocks

Revision 1
3.4. Y Motor drive (Transition)
Sensors
Motor Driver A
To X Bit Pattern Generator Interlocked To Y

Transition Motor
Supply
Motor Driver B
To Z Transition
The module drives and controls two stepping motors singly and together. The position of
the two axes can be checked using encoders.
There are no limit switches but there is a slotted-opto switch for use as a reference.
The Module communicates via a standard Trilogy module interface which is routed from
the back Plane via the X transition and drive board.
The motor drive supply is 48v in order that the motors can develop the torque and speed
requirements.
The motor circuits are identical for both motors.:
The Bit Pattern generator is a MACH111 device which with Direction and Step
produces the bit patterns required to drive the motors in quarter step mode.
Additional current control is supplied by the boost signal which when held low

Revision 1
reduces Vref and thus the current at which the current chopper cuts in. This is to
allow the motor current to be reduced when the motor is stationary. This reduces
the heat dissipation of the motor and driver chips.
The brake signal momentarily short circuits the motor drives causing the motor
current to be reduced rapidly to bring the motor to a halt.
5.1. Motor Supplies

The motor supply (48v) is supplied from the Interlock switches directly to the X
transition board. It arrives on the board as two separate 24v supplies. One supply is
tied to ground, via the 0v line, at the Back Plane. On the Transition board the
second 0v line is tied to the first 24v volts. This produces 24v and 48v supplies for
the stepper motors. The 24v motor supply is not used on the X, Y axes but is routed
through for the Z axis.
5.2. Logic and Control supplies

The +12v from the module interface is used directly for the flash programming
voltage (FVPP), it is also the input to a dc\dc converter which provides the 5v logic
supply. The logic GND is star connected to chassis on the Back Plane.
6. H8 microcomputer
The XY Module hardware is based around the Hitachi H8/3337F single-chip
Two 8-bit timers (TMR0, TMR1)
One 16-bit free-running counter (FRC)
Two digital to analog channels (DA0, DA1), with 8-bit resolution
Eight analog to digital channels (AN0 through AN7), with 10-bit resolution
Two serial communications channels (COM0, COM1)
Two pulse width modulation channels (PWM0, PWM1)

Revision 1

The I/O ports are configured to allow maximum software control of all XY
functions within the limitations of timing and functionality of the H8/3337 and to
minimize external hardware
To maximize this capability, the H8/3337 shall be configured in the single-chip mode
to allow all port pins to be available. The “single-chip” mode of operation implies
that there are no external program memory resources available to the software. The
entire program must fit within the confines of the 60Kbyte internal ROM space, and
all variables, stack, and heap space must be restricted to the 2Kbytes of internal
RAM.
An external ST93C46CB1 serial EEPROM connected to port P1 is used to store

setup and calibration information for the XY Module.
An MAX705[3] µprocessor supervisor IC is connected to the Reset input on the H8

to provide reset on power up.
The port I/O pin assignments are detailed in the “I/O Pin Assignments” section of
this document.

6.3. Packaging
The XY Module shall use the 84-pin, PLCC (Plastic Leadless Chip Carrier), Flash
Memory with 2kbytes RAM

Provides the Y motor clock. The settings for this timer will be dependant on
required motor velocity profiles.

Provides the X motor clock. The settings for this timer will be dependant on
required motor velocity profiles.

Not Hardware dedicated.

Revision 1
6.7. Digital to Analog

Not Used.

Not Used.
6.8. A/D converter
6.8.1. Channel AN0

Not used.
6.8.2. Channel AN1

Not used.
6.8.3. Channel AN2

Not used.
6.8.4. Channel AN3

Not used.
6.8.5. Channel AN4

Not used.
6.8.6. Channel AN5

Not used.
6.8.7. Channel AN6

Not used.
6.8.8. Channel AN7

Not used.

Revision 1

Not Used


Not used.

Not used.
7. Module Functions

Commands and test data are transferred between the H8 and the Comms controller via a
serial RS-232 interface. Interface drivers and receivers are used between the COM1 serial
communications channel on the H8 and the interface connector to provide proper RS-232
signal levels to the controller.
DSR is signalled via Port 8-6

The table below lists the I/O pin assignments for the H8/3337 microcomputer. Column 1
is the port pin assignment and functional name assigned to the pin by the manufacturer.
Column 2 is the logical name used within the XY. Column 4 is the pin number in the XY
while column 4 is the signal direction with respect to the controller.

Revision 1
Port P1 is mixed
P1-0/A0 Not Used 78 Not Used
P1-4/A4 E_DO 74 Input
P1-5/A5 E_DI 73 Output
P1-6/A6 E_SCLK 72 Output
P1-7/A7 E_CS 71 Output
Port P2 is mixed
P2-0/A8 XHOME 69 Input
P2-1/A9 YHOME 68 Input
P2-7/A15 Status LED 61 Output
P3-0/D0 XDIRN 79 Output
P3-1/D1 XRESET 80 Output
P3-2/D2 XBRAKE 81 Output
P3-3/D3 XBOOST 82 Output

Revision 1
P3-4/D4 YDIRN 83 Output
P3-5/D5 YRESET 84 Output
P3-6/D6 YBRAKE 1 Output
P3-7/D7 YBOOST 3 Output
P4-0/TMCI-0 Not Used 52 Not Used
P4-1/TMO-0 YCLK 53 Output
P4-2/TMRI-0 Not Used 54 Not Used
P4-3/TMCI-1 Not Used 55 Not Used
P4-4/TMO-1 XCLK 56 Output
P4-5/TMRI-1 Not Used 57 Not Used
P4-6/PW0 Not Used 58 Not Used
P4-7/PW1 Not Used 59 Not Used
Port P5 is not used
P5-0/TxD-0 Not Used 22 Not Used
P5-1/RxD-0 Not Used 21 Not Used
P5-2/SCK-0 Not Used 20 Not Used
P6-0/FTCI ED0 33 Input
P6-1/FTOA ED1 34 Input
P6-2/FTIA ED2 35 Input
P6-3/FTIB ED3 36 Input
P6-4/FTIC ED4 37 Input

Revision 1
P6-5/FTID ED5 38 Input
P6-6/FTOB/IRQ6 ED6 39 Input
P6-7/IRQ7 ED7 40 Input
Port P7 is not used
Port P8 is mixed
P8-0 Not Used 5 Not Used
P8-4/TxD1/IRQ3 TX1 9 Output
P8-5/RxD1/IRQ4 RX1 10 Input
P8-6/SCK1/IRQ5 DSR 11 Output
P9-0/ADTRG/IRQ2 EA0 32 Output
P9-1/IRQ1 EA1 31 Output

Revision 1
P9-2/IRQ0 Not Used 30 Not Used
P9-3/RD ERD 29 Output
P9-4/WR EWR 28 Output
P9-5/AS ECS 27 Output
P9-6/Φ ECLK 26 Output
P9-7 Not used 25 Not Used
NMI Not Used 17 Not Used

Revision 1
U5 U4
1 2 3 4 5 6 7 8
1 off PLCC Socket 84 Way U2 1N4148 VCC REV. ECO No. CHANGE DESCRIPTION INI. DATE
D5
R13
D1 VCC
1N4148 FLASH UPGRADE & RESET CONTROL 10k X XXXX Xxxx Xxxxxxxxx Xxxx W.T XX-XX-XX
+12V Q2
R15 1 BSS110 3 R14
1
R9 FVPP1
10k U5D Q1 10k 82R
9 8 R16 2
XYFS R8 VCC
2
10k
100R U7A
C9 R17
D 74HC14 1 2N4401 D
100nF A D3 10k
VCC C16 2 13
3
R10 B Q
3 4
CLR Q 1N4148 RS232 SERIAL DRIVER
GND 10k 14 VCC
Cext
100nF 15 VCC
Rext/Cext GND
MM74HC123A C15 C10
100nF 22uF
+
GND U7B
9 D4 GND U4
A
10 5 U6 6 2 VCC
B Q V- V+
VCC C18 11 12 1 8 PS1
R12 CLR Q 1N4148 MR WDO
6 6 1 4 +12v
U5F Cext WDI C13 C1+ C2+ C5
10k 7 5 1 6 +
Rext/Cext PFO +
22uF C11 C12 +Input +5v 22uF 35V
100nF 4 7 RESET1 + +
C17 PFI RESET 22uF 22uF C7
13 12 VCC MM74HC123A + 5
R11 22uF 35v 0V
MAX705CPA 3 5
+
VCC C1- C2-
10k GND 2 4 GND
-Input -5v
74HC14 10UF 10V GND RX1 9
R2OUT R2IN
8 XYRX
C19 12 13 Chassis
U5E 1N4148 R1OUT R1IN
100nF TX1 10 7 XYTX NMH1205S
T2IN T2OUT
D2 DSR 11 14 DSRX
T1IN T1OUT
11 10
GND
MAX232
74HC14
U5C
C NON VOLATILE STORAGE C
5 6
VCC VCC VCC
U3
E_CS 1
74HC14 C6 C4 CS C8
E_SCLK 2
100nF 100nF SCLK 100nF
U5B E_DI 3
DI
E_DO 4
DO
GND GND 6 GND
3 4 VCC PE
R6 7
PRE
U2 4k7 GND
74HC14
GND YBRAKE1 84 YRESET CONNECTION TO BACK PLANE
P3_6/HDB_6/D_6 P3_5/HDB5/D5 VCC NM93CS46 VCC
2 83 YDIRN J1A J1B
YBOOST 3 82 XBOOST FVCC FVCC
P3_7/HDB_7/D_7 P3_3/HDB3/D3 ENCODER COUNTERS 1A 1B
4 81 C1 GND GND
GND Vss P3_2/HDB2/D2 2A 2B
5 80 XRESET + C14 100nF XHOME YHOME
VCC P8_0/HA_0 P3_1/HDB1/D1 3A 3B
R1 4k7 6 79 XDIRN 22uF GND GND
P8_1/GA20 P3_0/HDB0/D0 4A 4B
7 78 SOL_DRIVER ENCXA ENCYA
P8_2/CS1 P1_0/A0 GND 5A 5B
8 77 VCC U1 ENCXB ENCYB
P8_3/IOR P1_1/A1 6A 6B
TX1 9 76 3 20 ENCXA GND GND
P8_4/IOW/IRQ3/TxD1 P1_2/A2 GND VCC XA 7A 7B
RX1 10 75 12 21 ENCXB XDIRN YDIRN
P8_5/CS2/IRQ4/RxD1 P1_3/A3 GND XB 8A 8B
VCC DSR 11 74 E_DO XRESET YRESET
P8_6/IRQ5/SCK1/SCL P1_4/A4 9A 9B
RESET1 12 73 E_DI ED0 GND 4 25 ENCYA GND GND
RES P1_5/A5 D0 YA 10A 10B
13 72 E_SCLK ED1 5 24 ENCYB XCLK YCLK
XTAL P1_6/A6 D1 YB 11A 11B
14 71 E_CS ED2 6 GND GND
EXTAL P1_7/A7 D2 12A 12B
X1 15 70 ED3 7 22 XBOOST YBOOST
MD_1 Vss GND D3 XFLG1 13A 13B
B 16 69 XHOME ED4 8 23 SOL_DRIVER YBRAKE B
MD_0 P2_0/A8 D4 XFLG2 14A 14B
17 68 YHOME ED5 9 27 VCC GND GND
NMI P2_1/A9 D5 YFLG1 15A 15B
FVPP1 18 67 ED6 10 26 XYRX DSRX
16MHz STBY P2_2/A10 D6 YFLG2 16A 16B
19 66 ED7 11 XYTX XYFS
C3 C2 Vcc P2_3/A11 D7 17A 17B
VCC 20 65 19 R4 GND GND
22pF 22pF R2 P5_2/SCK0 P2_4/A12 STATUS INDICATOR XLCNT/XLOL 18A 18B
21 64 EWR 14 1 10k GND GND
P5_1/RxD0 Vss GND WR YLCNT/YLOL 19A 19B
4k7 22 63 ERD 16 18 GND GND
P5_0/TxD0 P2_5/A13 VCC RD XRCNT/XABG 20A 20B
23 62 LED1 VCC ECS 15 28 GND GND
Vss P2_6/A14 R3 CS YRCNT/YABG 21A 21B
GND GND 24 61 2 1 EA1 17 GND GND
Vss P2_7/A15 Y/X 22A 22B
GND 25 60 620R EA0 13 GND GND
P9_7/WAIT/SDA Vcc C/D 23A 23B
ECLK 26 59 ECLK 2 Chassis Chassis
P9_6/CLK P4_7/PW1 LED Green 5mm FCLK 24A 24B
ECS 27 58 PWR 12v
P9_5/AS P4_6/PW0 25A 25B
EWR 28 57 LS7266R1 PWR 12v
P9_4/WR P4_5/TMRI1/HIRQ12 +12v 26A 26B
ERD 29 56 XCLK F1 Chassis Chassis
P9_3/RD P4_4/TMO1/HIRQ1 PWR 12v 27A 27B
30 55 Chassis Chassis
P9_2/IRQ0 P4_3/TMCI1/HIRQ11 28A 28B
EA1 31 54 PWR 12v
P9_1/IRQ1/EIOW P4_2/TMRI0 MF-R500 29A 29B
EA0 32 53 YCLK PWR 12v
P9_0/IRQ2/ADTRG/ECS2 P4_1/TMCO0 30A 30B
ED0 33 52 Chassis Chassis VCC
P6_0/KEYIN0/FTCI P4_0/TMCI0 31A 31B
ED1 34 51 VCC FVCC FVCC
P6_1/KEYN1/FTOA AVss GND R5 32A 32B
ED2 35 50
P6_2/KEYN2/FTIA P7_7/AN7/DA1 MF-R110 F2
ED3 36 49 4K7
P6_3/KEYN3/FTIB P7_6/AN6/DA0
ED4 37 48
P6_4/KEYN4/FTIC P7_5/AN5
ED5 38 47
ED6 39
P6_5/KEYN5/FTID P7_4/AN4
46
NOTES DYNEX TECHNOLOGIES (Guernsey) Ltd
P6_6/KEYN6/FTOB/IRQ6 P7_3/AN3 Rue Du Commerce
ED7 40 45
P6_7/KEYN8/IRQ7 P7_2/AN2 1. UNLESS OTHERWISE SPECIFIED: St Peter Port
41 44
Vss P7_1/AN1 A. ALL CAPACITORS ARE IN MICROFARADS (uF) Guernsey, GY1 2HX
42 43
VCC AVcc P7_0/AN0 B. ALL RESISTORS ARE IN OHMS, 1/4W, 1.%
A DSX XY Controller Board A
GND H8/3337YF/16
GND

A3 0500 4
Scale Sheet
1 of 1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
To Y Transition
J8
Z_+24v
1a
1b
M_+48v
Z_0v
1 N/A New Design KDU 9 Oct 98
2a From Interlock Switches
2b
Y M_GND
Z TX M_+48v
2 N/A Development changes KDU 27 Oct 98
3a J15 M_+48v
3b
Y Direction
Z RX 1
IM1+48v
F3
Brake 10
U1
9
3 3971 Layout Changes KDU 12 Jan 00
4a BRAKE VM+ C1
4b
Y Reset
Z RS232 SigGnd
2
3
MF-R500
F1 MF-R500
M_+24v
PhaseA 11
DIRN +
470u 63v
C11 4
5a IM2+24v TP1 1u
D 5b
Y Brake
Z DSR
4
5 Z M_GND1
R5 10k TESTPOINT
MA1
MA2
8
7
M1 VM-
5 1 off PLCC Socket 44 Way U3 D
6a M2
Y Clock 6 Z M_GND2 MA3 6 X M_GND
6b M3
Z FS 7 MA4 4
7a VCC M4
Y Boost 8 Y M_GND GND Vref 14
7b DAC REF
1
Z FSR 9 1 MOTORA1
8a OUT1
Y VCC 10 C8 3
8b RC
M_+24v 11 X M_GND 100n
9a
Y GND 12 2
9b COMPOUT
Z M_GND1 13 15 MOTORA2
10a GND CS OUT OUT2
Y ENCA
10b R15 R1
M_+24v C2 R3 C4 12
11a 10R 20K GND J1
Y ENCB 1nF 5k1 100p
11b LMD18245
Z M_GND2 1
12a
Y HOME 2
12b
3
GND M_+48v
GND 4
U2
From Controller Brake 10 9
BRAKE VM+ C6
PhaseB 11 + C12
J7 DIRN 470u 63v
Z_+24v TP5 TP2 1u
1 TP6 MB1 8 5
Z_0v TESTPOINT M1 VM-
2 MB2 7
GND M2
3 MB3 6 X M_GND
HOME M3
4 MB4 4
Boost VCC M4
5 Vref 14
Solenoid DAC REF
1
1
6 1 MOTORB1
1
Clock_IN OUT1
7 VCC 3
Direction_IN GND RC
8
C Reset_IN C
9 2
Y HOME C9 COMPOUT
10 13 15 MOTORB2
Y Boost 100n CS OUT OUT2
11
Y Brake R2
12 C3 R4 C5 12
Y Clock 20K GND
13 GND 1nF 5k1 100p
Y Direction
14 LMD18245
Y Reset
15
ENCA
16
ENCB
17 GND VCC
Y ENCA
18
Y ENCB
19
Y GND VCC
20
XYTX
21
XYRSSR R6
22 C13 C10
XYRX + 33K
23 22u 25v 100n
XYDSR
24
XYFS
25 Solenoid Driver U5A
XYFSR GND
26
Y VCC GND
27 M_+24v
Y GND Direction_IN R12 1 2 Direction
28 R7 VCC U3
M_+48v Boost Vref 10K R16
29 C19 C16 10 43 PhaseA
M_+24v C18 33k 1N 63V IN 0 IO 31
30 + R14 U5B 4K7 Clock 11 42
X M_GND 1U 63V 220U 35V IN 1/CLK0 IO 30
31 1R 2W 13 41
C_PWR C7 IN 2/CLK1 IO 29
32 Sol_Hi R9 32 40
GND J4 100n Reset_IN R11 GND 3 4 Reset IN 3 IO 28
33 33K 33 39
VCC D1 10K IN 4/CLK2 IO 27
34 X M_GND 1 C15 35 38
1N4935 IN 5/CLK3 IO 26
5
U4 2 1N 63V 2 37
U5D IO 0 IO 25
B DRV101 3 36 B
Solenoid 1 IO 1 IO 24
6 Sol_Lo 4 31 Reset
PWM Vs
Out R10 GND IO 2 IO 23

Solenoid 1 Clock_IN 9 8 Clock 5 30 MA3
In J9 IO 3 IO 22
GND 6 29
Delay
GND
10K IO 4 IO 21
7 1 MA2 7 28
/Flag IO 5 IO 20
2 MB4 8 27 Direction
IO 6 IO 19
9 26 MA4
Solenoid 2 IO 7 IO 18
MA1 14 25
2
IO 8 IO 17
MB3 15 24
X M_GND IO 9 IO 16
MB2 16 21 MB1
C17 IO 10 IO 15
R13 17 20 PhaseB
IO 11 IO 14
220N 63V 100K 18 19
IO 12 IO 13
J2
Z RS232 SigGnd MACH211-15JC
1
Z C_GND
2
X M_GND
From Back Plane 3
Z C_PWR
4
Z Module Interface 5
Z RX
6
Z TX U5E
7 J6 VCC
Z DSR
8
Z FS 1 GND
9 11 10
Z FSR 2
10 ENCA DYNEX TECHNOLOGIES (Guernsey) Ltd
Encoder 3
4 Rue Du Commerce
ENCB MM74HC14 St Peter Port
5 U5F
J3 Guernsey, GY1 2HX
6
XYRSSR
1
M_+24v 13 12
A 2 X C_GND DSX X Transition and Drive A
J5 VCC GND
3 R8
C_PWR
4 1 X M_GND 2k2
XY Module Interface MM74HC14
5 2 U5C
XYRX Home
6 3
XYTX HOME
7 4
XYDSR 5 6 Size FCSM No. DWG No. Rev
8 5
XYFS
9 A3 0509-03 3
XYFSR
10
GND
Scale Sheet
1 of 1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 off PLCC Socket 44 Way U3 REV. ECO No. CHANGE DESCRIPTION INI. DATE

2 N/A Development Mods KDU 27 Oct 98
3 3971 Layout Changes KDU 12 Jan 00
D D
M+ve
U1
From Controller Brake 10
BRAKE VM+
9
PhaseA 11 + C1
DIRN C11
470 63v
R5 10k MA1 8 5 1
M1 VM-
MA2 7
M2
MA3 6 M_GND
M3
MA4 4
M4
GND VCC Vref 14
DAC REF
1 MOTORA1
OUT1
J6 VCC VCC U3 3
R16 C8 RC
10 43 PhaseA
1 GND IN 0 IO 31 0.1
4K7 Clock 11 42 2
2 IN 1/CLK0 IO 30 COMPOUT
ENCA 13 41 13 15 MOTORA2 J1
Encoder 3 IN 2/CLK1 IO 29 CS OUT OUT2
32 40 GND
4 IN 3 IO 28 R1 1
ENCB 33 39 C3 R3 C5 12
5 IN 4/CLK2 IO 27 20k GND 2
35 38 0.001 5k1 100p
6 IN 5/CLK3 IO 26 LMD18245 3
2 37
IO 0 IO 25 4
M+ve 3 36
IO 1 IO 24 5
J5 VCC 4 31 Reset
R8 IO 2 IO 23 6
5 30 MA3 GND M+ve
1 M_GND 2k2 IO 3 IO 22
6 29 U2 JST6
2 IO 4 IO 21
Home MA2 7 28 Brake 10 9
3 IO 5 IO 20 BRAKE VM+ C2
HOME MB4 8 27 Direction PhaseB 11 + C12
C 4 IO 6 IO 19 DIRN 470 63v C
9 26 MA4
5 IO 7 IO 18 VCC 1
MA1 14 25 MB1 8 5
IO 8 IO 17 M1 VM-
MB3 15 24 MB2 7
IO 9 IO 16 M2
GND MB2 16 21 MB1 C9 MB3 6 M_GND
IO 10 IO 15 M3
17 20 PhaseB 0.1 MB4 4
IO 11 IO 14 M4
18 19 Vref 14
IO 12 IO 13 DAC REF
1 MOTORB1
GND OUT1
MACH211-15JC 3
RC
2 VCC
COMPOUT
13 15 MOTORB2
CS OUT OUT2
R2 C10
C4 R4 C6 12
20k GND 0.1
0.001 5k1 100p
LMD18245
U5A GND
J3
GND Direction_IN 1 2 Direction
1a M+ve
1b
2a M_GND U5B
2b
Direction_IN
3a
J2 Reset_IN 3 4 Reset
3b
Reset_IN IntCon1
4a 12
IntCon2
4b 11
Brake IntCon3 U5D
5a 10
IntCon4
From X Transition Board 5b 9
B Clock_IN IntCon5 VCC B
6a 8 Clock_IN 9 8 Clock
IntCon6
6b 7
Boost IntCon7
7a 6
IntCon8
7b 5
IntCon9 R6
8a VCC 4
IntCon10 C13 22k
8b 3 +
IntCon11 22u 25v
9a GND 2
IntCon12
9b 1
ENCA
10a
10b GND
ENCB
11a To Z Transition Board
11b Vref
HOME
12a
12b
R7
R9 C7
33k
8k2 0.1
U5E
11 10 Boost
MM74HC14 GND
U5F DYNEX TECHNOLOGIES (Guernsey) Ltd
Rue Du Commerce
13 12 St Peter Port
GND Guernsey, GY1 2HX
MM74HC14 DSX Y Drive and Transition

A U5C A
5 6

A3 050503 3
Scale Sheet
1 of 1
1 2 3 4 5 6 7 8
5. Z & Pipette
5.1. Control Board
5.1.1. Schematic
5.1.2. PCB Layout
5.2. Pipette & Eject Drives
5.2.1. Schematic
5.2.2. PCB Layout
5.3. Z Transition Board
5.3.1. Schematic
5.3.2. PCB Layout

Dynex Technologies (Guernsey) Ltd. Document Title

This document is intended to describe the interaction of the Z & Pipette Module
electronics to control all of the various internal functions and the results of the operation
of various sensors.
2. References
1 Z & Pipette Module Requirements
3. Module Functions
The module is required to carry out Plate washing functions, in order to achieve this it is
necessary to:
• Be able to control 3 motors in the X, Y and Z modes.
• Deliver one of four wash liquids to the wells in controlled quantities and at controlled
delivery rates.
• Remove as much as possible of the fluid from the wells.
• Sense when wash buffer bottles are empty and the waste bottle is full, and prevent
further use of those bottles until situation remedied.
• Communicate with the host, via RS232 and, in the stand alone mode, with the
opereator via keypad and LCD display
• Store wash protocols.
• Carry out macro functions when in stand alone mode.
__________________________________________________________________________________
FileName.doc 1 Revision 1
P Motor
Motor Drives
E Motor
Z Motor
Z transition
Pressure
Analogue Circuits
Sensors
Z & Pipette Control
From Back Plane
__________________________________________________________________________________
4.2. Z & Pipette Control
Z transition Board
Pipette and
Mach 211 Eject Drive
Board
FVPP
H8 Controller
RS232 Level
To Back Plane
Changer
Variable Gain Pressure Sensor

Amplifier + Preamp
Digital Pot Digital Pot

(Gain) (Offset)
__________________________________________________________________________________
5.1. Motor Drivers Pipette and Eject

The Pipette and Eject motor drivers are similar, using the A2919, and set for 0.5
amps. The pipette actuator is only rated for 350 mA with a software boost, and
driven in quarter steps. The Eject motor runs in half steps.
5.2. Motor Driver Z Motor

The Z Motor is driven via two National Semi Conductor H drivers ICs. These are
mounted on the Z Transition board on the Z axis arm. The motor voltage is 24v and
the H drivers use current limiting to produce a driving current of 1.5A with boost
and 0.9 Amps without boost.
5.3. Pressure sensing

The SDX-A family of sensors produces a voltage directly proportional to the
pressure applied. This voltage for a 12 volt supply is +/- 11mv full scale span. This
equates to +/- 1 psi.
An AD 620 instrumentation amplifier is used for the first stage of amplification. This
is followed by an op-amp with a gain which can be adjusted from1 to 50 in 512
steps, by use of a Digital potentiometer. At zero voltage there may be an offset of
+/- 0.3 mV, there may also be an offset of +/- 0.5mV due to temperature
fluctuations. These are removed by the use of a second digital potentiometer.
The amplified signal is level shifted by 2.5 volts to ensure that negative pressures can
be measured.

The Vcc is for the Control and driver board utilise a Newport Power NMA 2405S which
provides +/5v for a total of 2 Watts.
The Vcc for the Transition board is derived from a Newport Power NME 2405S which
provides 1 Watt @ +5v.
7. H8 microcomputer
The Z & Pipette Module hardware is based around the Hitachi H8/3337F single-chip

__________________________________________________________________________________

7.3. PLCC, 84-pin Packaging

The Z & Pipette Module shall use the 84-pin, PLCC (Plastic Leadless Chip Carrier),

Provides the Z clock.

Provides the clock for the Pipette and eject Motors.

Provides timing for delays.
7.7. Digital to Analogue

Not Used.

Not Used.
__________________________________________________________________________________
7.8. A/D converter
7.8.1. Channel AN0

Used to read the output from the pressure sensor.
7.8.2. Channel AN1

Not Used
7.8.3. Channel AN2

Not Used
7.8.4. Channel AN3

Not Used
7.8.5. Channel AN4

Not Used
7.8.6. Channel AN5

Not Used
7.8.7. Channel AN6

Not used.
7.8.8. Channel AN7

Not used.

Not Used

__________________________________________________________________________________

Not used.

Not Used

Commands and test data are transferred between the H8 and the external PC controller via
a serial RS-232 interface. Interface drivers and receivers are used between the COM1
DTR is signaled via Port 8-7

Column 2 is the logical name used within the Z & Pipette. Column 3 is a brief description
of the logical function as applied to the Z & Pipette.
Port Pin Special Signal Name I/O Use
P1-0 A0 DATA0 78 O Not Used
__________________________________________________________________________________
P2-0 A8 E_DO 69 I EEPROM data out
P2-1 A9 E_DI 68 O EEPROM data in
P2-2 A10 E_SCLK 67 O EEPROM clock
P2-3 A11 E_CS 66 O EEPROM Chip select
P2-4 A12 RSTPOT 65 O Enable Pot data change
P2-5 A13 DQ 63 IO Data to from Pots
P2-6 A14 Z Boost 62 O Boost to Z motor
P2-7 A15 LED 61 O Status LED
P3-0 D0 P_Select 79 O Select P Motor
P3-1 D1 P_Direction 80 O Set P Direction
P3-2 D2 P_Reset 81 O Set P Reset
P3-3 D3 P_Home 82 I From P Home switch
P3-4 D4 E_Select 83 O Select E Motor
P3-5 D5 E_Direction 84 O Set E Direction
P3-6 D6 E_Reset 1 O Set E Reset
P3-7 D7 E_Home 3 O From E Home switch
P4-0 TMCI-0 Z_Direction 52 O Set Z Motor Direction
P4-1 TMO-0 Z_Clock 53 O Z Motor Clock
P4-2 TMRI-0 Z_MRes 54 O Reset Z Motor Pattern

Generator
__________________________________________________________________________________
P4-3 TMCI-1 Z_Brake 55 O Not Used
P4-4 TMO-1 Peclock 56 O Shared Clock for P and

E Motors
P4-5 TMRI-1 PLATEDET 57 I Plate detect Switch
P4-6 PW0 TIPDET 58 I Tip Detect Switch
P4-7 PW1 Z_Home 59 I From Z Home switch
P5-0 TxD-0 SINT1 22 O Not Used
P5-1 RxD-0 SINT2 21 O Not Used
P5-2 SCK-0 DTR 20 O DTR Signal to Comms

Board
P6-0 FTCI ED0 33 I Encoder Data Bit 0
P6-1 FTOA ED1 34 I Encoder Data Bit 1
P6-2 FTIA ED2 35 I Encoder Data Bit 2
P6-3 FTIB ED3 36 I Encoder Data Bit 3
P6-4 FTIC ED4 37 I Encoder Data Bit 4
P6-5 FTID ED5 38 I Encoder Data Bit 5
P6-6 FTOB ED6 39 I Encoder Data Bit 6
P6-7 IRQ7 ED7 40 I Encoder Data Bit 7
P7-0 AN0 PRESS 43 I Pressure Input
P7-1 AN1 44 I Not Used
__________________________________________________________________________________
P7-6 AN6/D 49 I Not Used

A0
P7-7 AN7/D 50 I Not Used

A1
P8-0 5 Not Used
P8-1 6 Not Used
P8-2 7 Not Used
P8-3 8 Not Used
P8-4 TxD1/ T0 9 O Host Communications
IRQ3 Transmit
P8-5 RxD1/ R0 10 I Host Communications
IRQ4 Receive
P8-6 SCK1/ Laser 11 I Laser Plate Detector
IRQ5
P9-0 ADTRG ED0 32 O Encoder Reg Address

/IRQ2 Bit 0
P9-1 IRQ1 ED1 31 O Encoder Reg Address

Bit 1
P9-2 IRQ0 Torque 30 O Not Used
P9-3 RD ERD 29 O Encoder Read
__________________________________________________________________________________
P9-4 WR EWR 28 O Encoder Write
P9-5 AS ECS 27 O Encoder Chip Select
P9-6 Φ ECLK 26 O Encoder Clock
P9-7 Not used 25 Not Used
NMI NMI Not Used 17 Not Used
__________________________________________________________________________________
1 2 3 4 5 6 7 8
1 off PLCC Socket 84 Way U3
1 N/A NEW DESIGN PAH
2-6 N/A Development Mods KDU 4th Nov 99

VCC +5V 7 3971/xxxx Layout Modifications, Change EEPROM KDU 17 Jan 00
FAN PS1 R21
J1 M+ve C_PWR LINK
1 6 C5 +
1 +Input +5v 22uF 25v
D D
2 C30 R22
+ 5
22uF 35v 0V
M_GND LINK
TP1 External LED (Power) 2 4 GND C27 + A_GND
-Input -5v 22uF 25v
J2
M+ve C_GND
1 R8 NMH2405S
2
J7 2K2 -5V
3
1
12b GND
M_GND
12a GND
Z MRes
11b
Z Direction
11a
Z Brake
10b
torque
10a
9b
Z Clock
9a
Z Home
8b
Z Boost
8a
Z ENCB
7b
Z ENCA TP2
7a
6b GND
6a M+ve
5b M_GND
1
5a VCC
FS
4b
DSRZ
4a
3b
C 3a GND C
2b C_GND
Z_TX Control Analogue
2a
0503061.asc 0503062.asc
1b C_PWR
Z_RX
1a
Z Home
Z Home DigiClk DigiClk
M+ve Z_RX
Z_RX RSTPOT RSTPOT
Z_TX
Z_TX DQ DQ
Laser Sensor Z Direction
Z Direction PRESS PRESS
Z Brake
Z Brake
J9 Z Boost
Z Boost
Z Clock
1 Z Clock C_PWR C_PWR
LaserSense FS
2 FS C_GND C_GND
Z MRes
3 Z MRes
Z ENCA
Z ENCA
M_GND Z ENCB
Z ENCB
torque
torque +5V +5V
DSRZ
DSRZ A_GND A_GND
-5V -5V
LaserSense
LaserSense
M+ve M+ve VCC VCC

M_GND M_GND GND GND
C_PWR C_PWR
C_GND C_GND
B VCC VCC B
GND GND
+5V +5V
A_GND A_GND
C_PWR
+ C17
22uF 35v
C_GND

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Z & Pipette Control A

A3 0503-06 06
Scale Sheet
1 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
REV. ECO No. CHANGE DESCRIPTION

J3 INI. DATE
VCC RS232 SERIAL DRIVER 1
VCC
VCC VCC GND
2
1
P1_E
C36 C24 3
I01_E
100n 22uF 25v RN1A 4
DSRZ VCC I11_E
DSRZ + 5
1
M+ve VCC 10k GND
Z Boost 6
1
Z Boost GND U10 P2_E
RN1D 7
Z Brake VCC 6 2 VCC U8 I02_E
Z Brake V- V+ RN1B 10k 8
1
R14 VCC 10 43 I11_P I12_E
2
Z MRes U5 C22 10k Z Clock IN 0 IO 31 9
Z MRes 10K 1 4 11 42 P2_P VCC
R20 C37 C1+ C2+ RN1C IN 1/CLK0 IO 30 10
D Z Direction 8 + PEclock 13 41 GND D
Z Direction 22u
+
C29 10k IN 2/CLK1 IO 29 11
1 + P_Select 32 40 P_Direction P1_P
5
Z Home 10K IN 3 IO 28 12
Z Home 7 Laser 22u 22uF 25v R23 4k7 33 39 P1_P I01_P
3
IN 4/CLK2 IO 27 13
LaserSense 2 GND 3 5 35 38 I02_P I11_P
LaserSense C1- C2- IN 5/CLK3 IO 26 14
Z Clock DATA3 2 37 I12_P GND
4
Z Clock IO 0 IO 25 15
4 9 8 3 36 DATA1 P2_P
Z ENCA R2OUT R2IN DigiClk IO 1 IO 24 16
Z ENCA 6 R1 12 13 Z_RX E_Direction 4 31 DATA6 I02_P
R1OUT R1IN IO 2 IO 23 17
3 DTR1 10 7 DSRZ DATA2 5 30 I11_E I12_P
Z ENCB T2IN T2OUT IO 3 IO 22 18
Z ENCB 5 T1 11 14 Z_TX SINT2 6 29 P_Reset M+ve
T1IN T1OUT IO 4 IO 21 19
DATA0 7 28 DATA4 M_GND
M+ve IO 5 IO 20 20
HCPL2730 GND MAX232 RSTPOT 8 27 SINT1 FS
IO 6 IO 19 21 FS
M+ve 9 26 GND
IO 7 IO 18 22
I01_E 14 25 P1_E FVPP1
IO 8 IO 17 23
M_GND DATA5 15 24 E_Reset RESET
IO 9 IO 16 24
NON VOLATILE STORAGE P2_E 16 21 I02_E C_GND
M_GND IO 10 IO 15 25
I01_P 17 20 E_Select C_PWR
Z_RX IO 11 IO 14 26
Z_RX U7 VCC DATA7 18 19 I12_E M+ve
IO 12 IO 13 27
E_CS 1 M_GND
Z_TX CS 28
Z_TX E_SCLK 2 MACH211-15JC C_PWR
SCLK C21 29
E_DI 3 C_GND
DI 100n 30
E_DO 4 P_Boost
R27 DO 31
6
VCC PE 32
VCC VCC 4k7 7 GND
torque PRE 33
torque
34
GND
C20 C2
C_PWR 100n 100n NM93C66N
C_PWR GND
C GND GND C
C_GND U3
C_GND
E_Reset
1 84 E_Direction
VCC P3_6/HDB_6/D_6 P3_5/HDB5/D5
2 83 E_Select
VCC EHOME 3 82 PHOME
P3_7/HDB_7/D_7 P3_3/HDB3/D3
4 81 P_Reset VCC
GND VCC P_Boost 5 80 P_Direction VCC C_PWR
R18 P8_0/HA_0 P3_1/HDB1/D1
6 79 P_Select J6
GND P8_1/GA20 P3_0/HDB0/D0 R29
4K7 7 78 DATA0
P8_2/CS1 P1_0/A0 C28 2k2 1
8 77 DATA1 +
+5V P8_3/IOR P1_1/A1 22uF 25v 2
T1 9 76 DATA2
P8_4/IOW/IRQ3/TxD1 P1_2/A2 3
+5V R1 10 75 DATA3 TIPDET
P8_5/CS2/IRQ4/RxD1 P1_3/A3 4
Laser 11 74 DATA4
P8_6/IRQ5/SCK1/SCL P1_4/A4 5
A_GND RESET 12 73 DATA5 GND
RES P1_5/A5
13 72 DATA6
A_GND XTAL P1_6/A6
14 71 DATA7
EXTAL P1_7/A7
X1 FVPP1 15 70 STATUS INDICATOR J5
R17 MD_1 Vss GND R28
16 69 E_DO
VCC MD_0 P2_0/A8 2k2 1
4k7 17 68 E_DI VCC
NMI P2_1/A9 2
FVPP1 18 67 E_SCLK VCC
16MHz STBY P2_2/A10 3
19 66 E_CS RSTPOT PLATEDET
VCC Vcc P2_3/A11 + C8 4
C10 C9 DTR1 20 65 R9
P5_2/SCK0 P2_4/A12 RSTPOT 220UF 16V 5
22pF 22pF SINT2 21
P5_1/RxD0 Vss
64
GND DQ
620R C6 Encoder
SINT1 22 63 100n
P5_0/TxD0 P2_5/A13
GND
23
Vss P2_6/A14
62 Z Boost
GND
ENCODER COUNTERS
GND GND 24 61 2 1 GND J4
R12 4k7 Vss P2_7/A15 R25
B 25 60 VCC U1 B
VCC P9_7/WAIT/SDA Vcc VCC 2k2 1
ECLK 26 59 Z Home LED1 3 20 VCC
P9_6/CLK P4_7/PW1 VCC XA R16 2
ECS 27 58 TIPDET 12 21
P9_5/AS P4_6/PW0 GND XB 3
EWR 28 57 PLATEDET 10K EHOME
P9_4/WR P4_5/TMRI1/HIRQ12 4
ERD 29 56 PEclock ED0 GND 4 25 Z ENCA
P9_3/RD P4_4/TMO1/HIRQ1 D0 YA 5
torque 30 55 Z Brake ED1 5 24 Z ENCB
P9_2/IRQ0 P4_3/TMCI1/HIRQ11 D1 YB
EA1 31 54 Z MRes ED2 6
P9_1/IRQ1/EIOW P4_2/TMRI0 D2
EA0 32 53 Z Clock ED3 7 22
P9_0/IRQ2/ADTRG/ECS2 P4_1/TMCO0 D3 XFLG1 VCC
ED0 33 52 Z Direction ED4 8 23 J8
P6_0/KEYIN0/FTCI P4_0/TMCI0 D4 XFLG2 R26
ED1 34 51 ED5 9 27
P6_1/KEYN1/FTOA AVss A_GND D5 YFLG1 2k2 1
ED2 35 50 ED6 10 26
P6_2/KEYN2/FTIA P7_7/AN7/DA1 D6 YFLG2 R15 2
ED3 36 49 ED7 11
P6_3/KEYN3/FTIB P7_6/AN6/DA0 R30 D7 3
ED4 37 48 19 4K7 PHOME
P6_4/KEYN4/FTIC P7_5/AN5 XLCNT/XLOL 4
ED5 38 47 4k7 EWR 14 1
P6_5/KEYN5/FTID P7_4/AN4 WR YLCNT/YLOL 5
ED6 39 46 ERD 16 18
P6_6/KEYN6/FTOB/IRQ6 P7_3/AN3 RD XRCNT/XABG
ED7 40 45 ECS 15 28
P6_7/KEYN8/IRQ7 P7_2/AN2 CS YRCNT/YABG
+5V 41 44 EA1 17
Vss P7_1/AN1 Y/X
42 43 EA0 13 GND
AVcc P7_0/AN0 PRESS C/D
ECLK 2 C_GND
FCLK
GND
H8/3337YF/16 LS7266R1

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A A

A3
Scale Sheet
2 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

+5V
+5V Low Pass Filter 200Hz
A_GND
A_GND Gain 1
-5V GAIN +128 V/V
A_GND +5V C4
-5V 220n
C32 C33 R31 GAIN -(1 to 50) V/V
D C_PWR C_PWR 1K5 C7 D
100n 100n
C_PWR
R34 -5V A_GND U9 100P +5V
C_GND R6
1K5
C_GND S1 1 8 33K
Rg Rg1
4
5 1 +5V U4D LM6134BIN
Vs OUT+
2 7 13
-IN +Vs R7 U4A
14 3
D3 2 3 3 6 R4 R3 R1 12 1 Clean_Press
GND OUT- +IN O/P 2k
C31 R10 2
10K 10K 10K
BZX79C9V1 100n SDX01G2-A C25 C23 4 5 LM6134BIN 2K0
10N 50V 10N 50V -Vs REF
-5V A_GND C3 C1 R13
11
C_GND AD620 100N 15n 2K0
A_GND
A_GND A_GND -5V
A_GND +5V
A_GND
A_GND C13
100N C16 10N 50V
VCC U6 +5V
C11 GAIN CONTROL C14 C15
14 2 R24 OFFSET ADJUST 100N VCC U11 100n 100n
VCC H1 14 2 R11
270K U4C VCC H1
A_GND 2K -5V A_GND
7 3
GND L1 LM6134BIN 7 3
GND L1
GND 1 4
VB W1 10 GND 1 4
VB W1
8
C R33 10K -5V 11 C
H0 9 -5V 11
DQ 9 H0
Cout R32 9
5 10 Cout
RSTPOT RST L0 5 10
8 270K RST L0
DQ DQ 8
6 12 -5V DQ DQ
DigiClk CLK W0 6 12
CLK W0
13
Sout 13
Sout
DS1267-10
DS1267-50
A_GND VCC
A_GND VCC C34 C35

C26 100n 100n
C18 C19
100N GAIN +2 V/V
100n 100n -5V GND
A_GND +5V
-5V GND
U4B D2
LM6134BIN BAT47
Clean_Press 5
7
PRESS
6
R19 D1
10K C12
100n BAT47
B B
A_GND
-5V R5
10K
R2
10K
-2.5V
U2
GND
ZRA250A03
Vr
A_GND

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Z & Pipette Control A

A3 0503-06 6
Scale Sheet
3 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 off IDC Female Connector 34 way REV. ECO No. CHANGE DESCRIPTION INI. DATE
47.5mm Ribbon Cable 34 way
2 N/A Development Mods KDU 28 Sept 99
3 3971 New Hole in PCB for Set up KDU 14 Jan 00
4 3999 Reservoir Cap in Flash Voltage Cct KDU 22 Feb 2000
VCC
D D
P AXIS DRIVE VCC M+ve

C14
VCC 0.1
U3
13
Vcc GND
P1_P 16 24
R14 Phase 1 Vbb
I01_P 20
10k I01
I11_P 17 1 PMOTORA1
I11 OUT 1A
15 21 PMOTORA2 J3
Vref 1 OUT 1B
14
RC1 1
R12
2
22k 23
E1 3
P2_P 10 R5
Phase 2 4
P_Boost I02_P 8 22 1
C21 I02 SENSE 1
FLASH UPGRADE & RESET CONTROL R7 I12_P 9
I12
47K
470pF
11
Vref 2
12 2 M_GND PMOTORB1
RC2 OUT 2A
D5 VCC
R47 C22 5 PMOTORB2
GND OUT 2B
10K R8
+12V Q2 1N4148 M+ve 47K 470pF 6
R46 BSS110 3 R52 GND
1 FVPP1 7 3
1
GND E2
10K 82 18
Q1 GND
+ C4 + C25 19 4
GND SENSE 2
R45 2 22 35v
C 22U 25V C1 0.1 C
2
10K GND A2919SB R3
R48 GND M_GND 1
2N4401
10K M_GND
3
GND
VCC M_GND
GND
D4 VCC
R44
10K U17A
1N4148 E AXIS DRIVE C15
1 2 VCC M+ve 0.1
R51 VCC VCC
FS U2
U16A
100 13
C49 1 Vcc GND
74HC14 A P1_E 16 24
0.1 VCC C48 2 13 D6 R13 Phase 1 Vbb
J1 R43 B Q I01_E 20
3 4 1K8 I01
VCC CLR Q I11_E 17 1 EMOTORA1
1 10K 14 I11 OUT 1A
GND GND Cext 1N4148 J9
2 0.1 15
P1_E Rext/Cext 15 21 EMOTORA2
3 Vref 1 OUT 1B 1
I01_E 14
4 MM74HC123A RC1 2
I11_E R11
5 3
GND 22k 23
6 GND U16B C23 E1 R6 4
P2_E R9 P2_E 10
7 9 Phase 2 1
I02_E A 47K I02_E 8 22
8 10 5 D7 U15 470pF I02 SENSE 1
I12_E B Q I12_E 9
9 VCC C50 11 12 1 8 I12
VCC R49 CLR Q MR WDO GND
10 6 6
B GND Cext 1N4148 WDI 11 B
11 10K 7 5 Vref 2 M_GND
P1_P Rext/Cext PFO 12 2 EMOTORB1
12 0.1 4 7 RESET RC2 OUT 2A
I01_P C51 PFI RESET
13 VCC MM74HC123A GND
I11_P R50 5 EMOTORB2
14 MAX705CPA OUT 2B
+
GND
15 10K C_PWR R10 C24
P2_P M+ve 6
16 D8 10 10v GND 47K 470pF GND
I02_P 7 3
17 GND E2
I12_P R54 18
18 C5 C26 GND
M+ve 1N4148 + 19 4
19 1k2 22 35v 0.1 GND SENSE 2
M_GND
20 +12v
FS
21 A2919SB
GND GND M_GND R4
22 D9
FVPP1 BZX79C12 1
23
RESET M_GND
24
C_GND
25
C_PWR
26
M+ve M_GND
27
M_GND
28 C_GND
C_PWR
29
C_GND
30
P_Boost
31
32
33 DYNEX TECHNOLOGIES (Guernsey) Ltd
34 Rue Du Commerce
GND
TRANSITION IDC 34 WAY St Peter Port
Guernsey, GY1 2HX
A DSX Pipette and Eject Drives A

A3 0508-03 3
Scale Sheet
1 of 1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 off Clinched Stand Off 20mm 3.2mm dia hole

PS1
1 off Clinched Stand Off 20mm 3.2mm dia hole VCC
C_PWR 2 4
Vin+ve +5v
C_GND 1 3
Vin-ve 0v
GND
NME2405S
D D
M+ve
U1
From Controller Brake_In 10 9
BRAKE VM+ C1
PhaseA 11 +
C11
DIRN 220u 35v
VCC 1u
R5 10k TP4 MA1 8 5
M1 VM-
MA2 7
M2
C8 MA3 6 M_GND
M3
J6 VCC 100n MA4 4
M4
GND Vref 14
1 GND DAC REF
1 MOTORA1
1
2 GND OUT1
Encoder ENCA 3
3 RC
4
ENCB 2
5 COMPOUT
VCC U3 13 15 MOTORA2
6 R16 CS OUT OUT2
10 43 PhaseA
IN 0 IO 31 R1
M+ve 4K7 Clock 11 42 C3 R3 C5 12
IN 1/CLK0 IO 30 20K GND
J5 VCC 13 41 torque 1nF 5k1 100p J1
IN 2/CLK1 IO 29 LMD18245
32 40
1 M_GND R8 2k2 IN 3 IO 28 1
33 39
2 IN 4/CLK2 IO 27 2
Home 35 38
3 IN 5/CLK3 IO 26 3
HOME 2 37 GND M+ve
4 IO 0 IO 25 4
3 36 U2
5 IO 1 IO 24 5
4 31 Reset Brake_In 10 9
VCC IO 2 IO 23 BRAKE VM+ C2 6
5 30 MA3 PhaseB 11 +
C12
IO 3 IO 22 DIRN 220u 35v JST6
GND 6 29
IO 4 IO 21 1u
C10 MA2 7 28 MB1 8 5
C IO 5 IO 20 M1 VM- C
100n MB4 8 27 Direction MB2 7
IO 6 IO 19 M2
U5A 9 26 MA4 VCC TP3 MB3 6 M_GND
IO 7 IO 18 M3
MA1 14 25 MB4 4
GND IO 8 IO 17 M4
MB3 15 24 Vref 14
1
Direction_IN 2 Direction IO 9 IO 16 DAC REF
1
MB2 16 21 MB1 C9 1 MOTORB1
IO 10 IO 15 100n OUT1
17 20 PhaseB 3
IO 11 IO 14 RC
18 19
U5B IO 12 IO 13
GND 2
COMPOUT
MACH211-15JC 13 15 MOTORB2
CS OUT OUT2
Reset_IN 3 4 Reset
R2 U5E
20K C4 R4 C6 12
GND
VCC 1nF 5k1 100p
LMD18245 11 10
U5D
Clock_IN 9 8 Clock GND MM74HC14

R6 U5F
+ C13
22u 25v 22k
TP1 13 12
GND
Vref
GND
J8 MM74HC14
U5C
1
1a GND
1b GND R9 C7
Direction_IN R7 5 6
2a 8k2 100n
Reset_IN 33k
2b
torque
3a
B Brake_In MM74HC14 B
3b
Clock_IN
4a
Boost
4b
Boost
5a GND J3
HOME
5b C_PWR
ENCA 1
6a C_GND
ENCB TP2 2
6b TX
C_PWR 3
7a RX
4
7b GND RSSR
5
8a DSR
C_GND 6
1
8b VCC FS
DSR 7
9a FSR
FS 8
9b
RSSR 9 M+ve
10a
FSR 10 M_GND
10b
TX 11 M+ve
11a
C_GND 12 M_GND
11b
RX
12a
C_PWR
12b
To Y Transition
To Z & Pipette Board
REV ECO DESCRIPTION DRN DATE CHK UNLESS STATED TITLE DSX Z transition & Drive
A A
050400 Printed 11:25:36 10-Mar-2000 RESISTORS 1/4W +/-1% PCB PART NO. SHEET 1 OF 1
File Name F:\DSXPCB\ztrans\Rev3\Sch\050403.asc CAPS NON-POL +/-10% ECB PART NO.
CAPS POL +/-20% ORIGINATOR DATE
APPROVED ECO
TEL +44 1481 723777 DYNEX TECHNOLOGIES (GUERNSEY) LTD FAX +44 1481 711485
THIS DRAWING AND THE CONTENTS HEREIN CANNOT BE USED, COPIED OR DISCLOSED WITHOUT THE PRIOR WRITTEN PERMISSION OF DYNEX TECHNOLOGIES (GUERNSEY) LTD A3
1 2 3 4 5 6 7 8
6. Washer
6.1. Control Board
6.1.1. Schematic
6.1.2. PCB Layout
6.2. Daughter Board
6.2.1. Schematic
6.2.2. PCB Layout


This document is intended to describe the interaction of the Washer Module electronics to
control all of the various internal functions and the results of the operation of various
sensors.
2. References
1 Washer Module Requirements
3. Module Functions
The module is required to carry out Plate washing functions, in order to achieve this it is
necessary to:
• Be able to control 3 motors in the X, Y and Z modes.
• Deliver one of four wash liquids to the wells in controlled quantities and at controlled
delivery rates.
• Remove as much as possible of the fluid from the wells.
• Sense when wash buffer bottles are empty and the waste bottle is full, and prevent
further use of those bottles until situation remedied.
• Communicate with the host, via RS232 and, in the stand alone mode, with the
opereator via keypad and LCD display
• Store wash protocols.
• Carry out macro functions when in stand alone mode.
__________________________________________________________________________________
X Motor
Sensors Motor Drives Y Motor
Z Motor
Key Pad
LCD Display
From Back Plane Washer Control Pinch Valve
Pump Drives
Float Switches
__________________________________________________________________________________
4.2. Washer Control
Oscillator
Flash Display LCD Display

FVPP
Upgrade Interface Connector
Key Pad
Pattern Key Pad
Generator & Connector
Decoder
FlashUG1&2
H8 Controller
Auto Clean Motor Drives
NMI
Clock Connector
RS232 Level
Changer
Reset
Pump
Selection
Pump
Drivers & Pinch Valve
Current Drive
Sensing
Pinch Valve
Connector
Pump and switch Connector
__________________________________________________________________________________
4.3. Motor Drives
X Motor
X Drive
Connector
Bit Patter
Y Motor
Generator And Y Drive
Connector
Motor Selector
Z Motor
Z Drive
Connector
Motor Control
Sensors
Connector
__________________________________________________________________________________
5.1. Bit Pattern Generator and Motor Selector

This is a MACH211 device, which is programmed to:
• Produce the bit patterns required for quarter stepping for each of the three
motors.
• Enable the Y or the Z motor to be driven independently or simultaneously with

the X motor.
• Enable Y and Z motors to be driven simultaneously but independently only in

direction
• Enable the X motor to be driven independently of the other two
Each motor requires Direction and Reset. The X motor has its own dedicated clock
while the Y and Z each share the SHARED CLOCK
Using YZ CLK the SHARED CLOCK can be switched from Y (Logic 0) to Z

(Logic 1)
If TWO CLK is set to a logic 1 then both Y and Z motors are pulsed with the
SHARED CLOCK this condition over-rides the SHARED CLOCK.
5.2. Motor Drivers

The three motor drivers are identical, using the A2919, and are all set for 0.5 Amps
peak current. Using the above Bit pattern generator the motors are driven in quarter
steps (1/4)
5.3. Pump selection, Drives and Current monitoring

Pump speed is controlled by regulation of the mean dc current to the motor. That
regulation is via the PWM outputs of the H8 controller. The frequency of the PWM
is set and the on period of the cycle is adjusted to produce the duty cycle required
for the pump output necessary. This frequency is determined by test and is preset for
each motor.
The PWM output for the dispense pumps is gated to one of four pumps, using DP1-
DP4 to enable the required dispense pump. These signals also enable the required
pinch valve.to be opened.
All four dispense pump drives are identical. The current is switched via a FET
employing low side switching. The return current passes through a one-ohm resistor;
the resulting voltage drop is integrated, amplified and passed to the analogue inputs
__________________________________________________________________________________
of the H8 controller. The voltage read is proportional to the actual current drawn by
the motor.
The actual current drawn is proportional to the PWM duty cycle, frequency (fixed)
and the load on the motor. The current will increase if the motor is stalled and it will
decrease from the norm if the motor is running with a light load (i.e. not pumping
fluid). Any large difference from the norm can be detected, by the controller, and
corrective action taken.
CAUTION At low nominal currents (low PWM period) there may be no, or
undetectably low differences between the current levels in the different states.
5.4. Key Pad Pattern generator and decoder

This is a MACH111 device which generates a five bit ‘walking zero’sequence which
is applied to one side of the keyboard matrix. This sequence is produced
automatically at the frequency determined by the Oscillator.
When a key is pressed the sequence freezes until the key is released. A five-bit
number which, is dependent upon the key pressed, is passed to the controller. With
no key depressed the value returned is zero.
It is expected that when the key press is sensed the controller will sound the beeper
and the operator will release the key. This will allow the sequence to proceed, in
readiness for the next key push.
5.5. LCD Display interface

Eight data lines are latched via a 74374 octal D type latch with tri-state output
through to the LCD Display connector. DISPR/W enables the output while
DISPCLK latches the data.

The Vcc is derived from +12volts via a linear regulator LM7085CT fitted with a
17Co/Watt heatsink.
7. H8 microcomputer
The Washer Module hardware is based around the Hitachi H8/3337F single-chip
__________________________________________________________________________________

7.3. PLCC, 84-pin Packaging

The Washer Module shall use the 84-pin, PLCC (Plastic Leadless Chip Carrier),

Provides the YZ clock.

Provides the colck for the X motor.

Provides internal timing information.
7.7. Digital to Analogue

Not Used.

Not Used.
__________________________________________________________________________________
7.8. A/D converter
7.8.1. Channel AN0

Used to check the state of the waste switch. This is basically a digital signal.
7.8.2. Channel AN1

To sense the current through the dsipense pump 1.
7.8.3. Channel AN2

7.8.4. Channel AN3

7.8.5. Channel AN4

7.8.6. Channel AN5

Used to check the state of the Vacuum switch, a digital signal.
7.8.7. Channel AN6

Not used.
7.8.8. Channel AN7

Not used.

Not Used

__________________________________________________________________________________

Not used.

The drive frequency for the dispense pumps.

Commands and test data are transferred between the H8 and the external PC controller via
a serial RS-232 interface. Interface drivers and receivers are used between the COM1
DTR is signaled via Port 8-7

Column 2 is the logical name used within the Washer. Column 3 is a brief description of
the logical function as applied to the Washer.
Port Pin Special Signal Name I/O Use
P1-0 A0 XRST 78 O Reset X motor Pattern
P1-1 A1 XDIR 77 O X Motor Direction
P1-2 A2 YRST 76 O Reset Y motor Pattern
P1-3 A3 YDIR 75 O Y Motor Direction
P1-4 A4 YCLK 74 O Y Motor Clock
P1-5 A5 ZRST 73 O Reset Z motor Pattern
P1-6 A6 ZDIR 72 O Z Motor Direction
__________________________________________________________________________________
P1-7 A7 ZCLK 71 O Z Motor Clock
P2-0 A8 ASP 69 O Enable Aspirate Pump
P2-1 A9 DP1 68 O Enable Disp. Pump 1
P2-5 A13 63
P2-6 A14 OUT_Y 62 I Y Eject Pos. Sensor
P2-7 A15 LED 61 O Status LED
P3-0 D0 D0 79 O D0 to LCD Display
P4-0 TMCI-0 SHAREDCLO 52 O Y Z Clock

CK
P4-1 TMO-0 X_CLOCK 53 O X Clock Output
P4-2 TMRI-0 Y Z_CLK 54 O Directs YZ Clock to
__________________________________________________________________________________
requred Motor
P4-3 TMCI-1 TWO_CLK 55 O Enables both Y & Z

Motors
P4-4 TMO-1 56
P4-5 TMRI-1 VALVE 57 O Drive to Pinch valve
P4-6 PW0 APWM 58 O
P4-7 PW1 DPWM 59 O Dispense Pump PWM
P5-0 TxD-0 DISPR/W 22 O Display Read/Write
P5-1 RxD-0 DISPSTROB 21 O Display Strobe

E
P5-2 SCK-0 DISPREGSEL 20 O Select Display register
P6-0 FTCI KEY1 33 I Bit 0 for key pressed
P6-1 FTOA KEY2 34 I Bit 1 for key pressed
P6-2 FTIA KEY3 35 I Bit 2 for key pressed
P6-3 FTIB KEY4 36 I Bit 3 for key pressed
P6-4 FTIC KEY5 37 I Bit 4 for key pressed
P6-5 FTID HOME_X 38 I Ref For X Motor
P6-6 FTOB HOME_Y 39 I Ref For YMotor
P6-7 IRQ7 HOME_Z 40 I Ref For Z Motor
P7-0 AN0 Waste 43 I Waste Level Switch
P7-1 AN1 DSENS1 44 I Current Sense
__________________________________________________________________________________
P7-5 AN5 Vacuum 48 I Current Sense
P7-6 AN6/D 49 I
A0
P7-7 AN7/D 50 I
A1
P8-0 5
P8-1 6
P8-2 7
P8-3 8
P8-4 TxD1/ T0 9
IRQ3
P8-5 RxD1/ R0 10
IRQ4
P8-6 SCK1/ IRQ5 11
IRQ5
P9-0 ADTRG IRQ2 32

/IRQ2
P9-1 IRQ1 IRQ1 31
P9-2 IRQ0 IRQ0 30
P9-3 RD 29
P9-4 WR 28
__________________________________________________________________________________
P9-5 AS 27
P9-6 Φ Not used 26
P9-7 Not used 25
NMI NMI 17
__________________________________________________________________________________
1 2 3 4 5 6 7 8
1 off Clinched Nut M3 SS 4.2mm dia hole REV. ECO No. CHANGE DESCRIPTION INI. DATE
1 off Clinched Nut M3 SS 4.2mm dia hole
1 N/A New R&D design PAH 01.12.97
1 off Heat Sink 17 C/W U1 POWER INPUT AND FILTER
2 N/A Specification Change APH 08.10.98
1 off PLCC Socket 44 Way U8 Socket
3-5 N/A Development Changes KDU 30.06.99
1 off PLCC Socket 84 Way U5 Socket
6 N/A Specification change KDU 1 Jul 99
1 off PLCC Skt 28 Way U10 Socket HEAT SINK AT 17C/W
D 7 3971 Remove NMI and ass. parts KDU 17 Jan 00 D
U1
PWR +12V LM7805 VCC
VCC
1 3
Vin Vout
GND
F1
+ +
RGE1200 C10
C1 C11 C37
0.1 220 C36 C35 C38 C21 C29 C27 C34
22 0.1
0.1 0.1 0.1 0.1 0.1 0.1 0.1
2
R1
LINK GND
M_GND GND
C J2 GND PWR C
MICROCONTROLLER PUMP DRIVES
1
0502072.asc 0502073.asc
2
Vacuum
3 Vacuum
M_GND ASP_OUT
4 DPWM DPWM ASP_OUT
DP[1..4]
5 DP[1..4] DP[1..4]
RX DSEN[1..4]
6 RX DSEN[1..4] DSEN[1..4]
TX
7 TX APWM APWM
DTR
8 DTR ASP ASP
FL+
9 FL+ ASEN ASEN
10 VALVE VALVE
Lamp Lamp
GND +12V WASTE +12V
WASTE
+12V L[1..4] +12V
M_GND M_GND
M_GND M_GND
VCC VCC DPPV[1..4]
DPPV[1..4]
VCC VCC
GND GND DISP[1..4]
GND GND
J1
L[1..4]
1 M_GND
2
3
4
B DPPV[1..4] B
5
6 +12V
7
DPPV1
8
DPPV2
9
DPPV3
10
DPPV4 DISP[1..4]
11
12 M_GND
L4
13
L3
14
L2
15
L1
16
WASTE
17
DISP4
18
DISP3
19
DISP2
20
DISP1
21
ASP_OUT
22
23 +12V
Vacuum
24

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Washer Module A

A3 030-0502-07 7
Scale Sheet
1 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+12V REV. ECO No. CHANGE DESCRIPTION INI. DATE

D6
VCC 1N4934
1
+12v +12v +12V
D10 D16 C23
VCC 1N4934 VCC 1N4934 RN4A 1k Q2 0.1 DISP1
4
VCC
C28 C42 D3
RN6A Q1 0.1 RN6E Q11 0.1 FBDP1 DSPR1 R19 3 BAT47
1k DPPV1 1k PVALVE 1 DSEN1
2
1M
IRF2807 R5 2
D FBDPPV1 FBValve 1R 2W C30 R14 D
0.1 U6A 47k
2
6
ZVN4306A M_GND ZVN4306A M_GND LM324
11
3
M_GND GND
GND RN2B
+12V 10K
VCC D7
1N4934
1
+12v VCC
D13
1
VCC 1N4934 RN6F Q13 GND
1
1k LampOut RN4B Q3 C24 DISP2

C39 1k 0.1 VCC
RN6B 0.1 D2
Q9
1k Lamp R20
DPPV2 FBDP2 DSPR2 5 BAT47
7
ZVN4306A M_GND 1M 7 DSEN2
3
FBDPPV2 IRF2807 6
R6 R9
3
ZVN4306A M_GND 1R C31 U6B 47k

0.1 LM324
4
GND
M_GND
+12v RN2C
D14 +12V 10K
VCC 1N4934 D8
1N4934
1
VCC
1
C40
1
GND
C RN6C Q10 0.1 C25 C
1k DPPV3 RN4C Q4 0.1 DISP3
1k VCC
FBDPPV3 D4
FBDP3 DSPR3 R21 12 BAT47
4
ZVN4306A M_GND 1M 14 DSEN3
4
IRF2807 R7 13
1R C32 R17
0.1 U6D 47k
LM324
6
+12v
D15 M_GND GND
VCC 1N4934 RN2E
10K
1
+12V
C41 D9
RN6D Q12 0.1 VCC 1N4934
1
1k DPPV4
1
GND
FBDPPV4 RN4D Q5 C26 DISP4
1k 0.1 VCC
5
BAT47
ZVN4306A M_GND R22
FBDP4 DSPR4 10 D11 DISP[1..4]
DISP[1..4]
8 DSEN4
5
1M
+12v IRF2807 9
J8 R8 R25
DPPV[1..4] 1R C33 U6C 47k
DPPV[1..4] 1 0.1
LampOut LM324 DSEN[1..4]
2 DSEN[1..4]
2
B 3 B
GND
4
M_GND
VALVE 5 RN2A
U10 +12V
6
DP[1..4] 2 D5 10K
DP[1..4] CLK/IN 7
DP1 3 17 FBValve VCC
IN IO 8 1N4934
DP2 4 18 FBDPPV4 1
1
IN IO
DP3 5 19 FBDPPV3 GND
IN IO RN4E C22
DP4 6 20 FBDPPV2 Q6
IN IO 1k 0.1
7 21 FBDPPV1 ASP_OUT
DPWM IN IO ASP_OUT
9 23 FBDP4
ASP IN IO
10 24 FBDP3 FBASP
IN IO
11 25 FBDP2
6
IN IO
12 26 FBDP1 +12V J3 IRF2807 M_GND
IN IO
13 27 FBASP
IN IO 1
16 PVALVE
IN 2
3
PALCEV10H25JC(28) 4
5
ASP_OUT
6

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX
A DSX Washer Module A

A3 050207 7
Scale Sheet
2 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
D1 VCC
1N4148
R3
U9A D12 VCC
10K R30
1 1N4148
3 FLASHUG1 10K
R2 2 +12V Q8 VCC
FL+ R28 R29 KEYPAD CONNECTION
1
1
1
1
1
1
1
1
100R 1 BSS110 3 FVPP
D C19 74HC00 D
R26 10K 82R
0.1 RN5H
10K 2 10K SIL8+1
GND
2
Q7 U8
R27
2N4401 10 43 I3
2
3
4
5
6
7
8
9
10K IN 0 IO 31
11 42
3
IN 1/CLK0 IO 30
13 41 J6
U9B IN 2/CLK1 IO 29
KEY_RST 32 40 I5
IN 3 IO 28 1
4 33 39 I1 P5
GND IN 4/CLK2 IO 27 2
6 FLASHUG2 35 38 P1 I4
IN 5/CLK3 IO 26 3
5 2 37 P4
IO 0 IO 25 4
3 36 P4 I3
IO 1 IO 24 5
74HC00 4 31 KEY3 P3
IO 2 IO 23 6
5 30 I2
IO 3 IO 22 7
6 29 P5 P2
IO 4 IO 21 8
KEY1 7 28 I4 I1
IO 5 IO 20 9
8 27 P1
IO 6 IO 19 10
KEY4 9 26 KEY2
IO 7 IO 18
KEY5 14 25
IO 8 IO 17
I5 15 24
IO 9 IO 16
P3 16 21
50Hz OSCILLATOR IO 10 IO 15
I2 17 20
IO 11 IO 14
18 19 P2
NON VOLATILE STORAGE VCC
IO 12 IO 13
MACH211-15JC
U4 R11
10
E_CS1 1 43k
/CS
E_SO 2 U2B
SO
E_WP 3
R
/WP
E_SI 5 TrigB 8 9
SI TRIG Q
E_SCK 6
SCK LCD BACKLIGHT
R24 VCC 7 13
/HOLD DIS
10K
X25640 11 12 +12V R31 J5
CVolt THR
1
R10
2
C GND NE556 22K 33r 2.5W C
TrigB GND
C16 LCD DISPLAY PORT

0.01 C13
0.33
GND GND
VCC
1
VCC
10K 10K 10K 10K VCC J7
RV1 1
L1 L2 L3 L4 GND
2
10K TRIMPOT DISPREGSEL
6
C9 C8 C6 C5 3
0.1 0.1 0.1 0.1 4
DISPSTROBE
5
DISPR/W
6
D1
7
D0
8
GND GND D3
9
D2
10
6
L[1..4] DP1 DP2 DP3 DP4 D5
L[1..4] 11
D4
12
U5 D7
10K 10K 10K 10K 13
D6
14
D6 1 84 D5
P3_6/HDB_6/D_6 P3_5/HDB5/D5
2 83 D4 IDC 14 way Box
Vss P3_4/HDB4/D4
D7 3 82 D3
1
P3_7/HDB_7/D_7 P3_3/HDB3/D3
4 81 D2 GND
Vss P3_2/HDB2/D2
+12V GND L1 5 80 D1
P8_0/HA_0 P3_1/HDB1/D1
L2 6 79 D0
+12V P8_1/GA20 P3_0/HDB0/D0
L3 7 78 X_RST
P8_2/CS1 P1_0/A0
L4 8 77 X_DIR
M_GND P8_3/IOR P1_1/A1
T1 9 76 Y_RST
P8_4/IOW/IRQ3/TxD1 P1_2/A2
M_GND R1 10 75 Y_DIR
P8_5/CS2/IRQ4/RxD1 P1_3/A3
DTR1 11 74 Y_CLK
P8_6/IRQ5/SCK1/SCL P1_4/A4
VCC RESET 12 73 Z_RST
RES P1_5/A5
B 13 72 Z_DIR DP[1..4] VCC B
VCC XTAL P1_6/A6 DP[1..4]
14 71 Z_CLK
EXTAL P1_7/A7
X1 VCC FVPP 15 70
GND MD_1 Vss
2
16 69 ASP R32
MD_0 P2_0/A8 ASP
GND 17 68 DP1 620R
NMI P2_1/A9
VCC FVPP 18 67 DP2
16MHz STBY P2_2/A10 10K
19 66 DP3
C17 C14 Vcc P2_3/A11
DISPR/W 20 65 DP4
22pF 22pF P5_2/SCK0 P2_4/A12 LED1
DISPSTROBE 21 64
P5_1/RxD0 Vss
DISPREGSEL 22 63
1
P5_0/TxD0 P2_5/A13
23 62 OUT_Y GND
Vss P2_6/A14
GND 24 61 GND Lamp
GND Vss P2_7/A15 Lamp
VCC 25 60
VCC P9_7/WAIT/SDA Vcc VCC
RS232 SERIAL DRIVER R15 10K E_SO
E_SI
26
27
P9_6/CLK P4_7/PW1
59
58
DPWM
DPWM
C2 P9_5/AS P4_6/PW0
E_WP 28 57 VALVE
22 P9_4/WR P4_5/TMRI1/HIRQ12 VALVE
E_CS1 29 56
P9_3/RD P4_4/TMO1/HIRQ1
U3 E_SCK 30 55 TWO_CLK J4
+ P9_2/IRQ0 P4_3/TMCI1/HIRQ11
6 2 BEEPER 31 54 XY_CLK TWO_CLK 1A 1B X_RST
V- V+ P9_1/IRQ1/EIOW P4_2/TMRI0 1A 1B
KEY_RST 32 53 X_CLK XY_CLK 2A 2B X_DIR
C7 P9_0/IRQ2/ADTRG/ECS2 P4_1/TMCO0 2A 2B
1 4 KEY1 33 52 SHAREDCLOCK X_CLK 3A 3B Y_RST
22 C1+ C2+ P6_0/KEYIN0/FTCI P4_0/TMCI0 3A 3B
+ + KEY2 34 51 VCC SHAREDCLOCK 4A 4B Y_DIR
+
C4 C12 P6_1/KEYN1/FTOA AVss R12 4A 4B
KEY3 35 50 5A 5B Y_CLK
22 22 P6_2/KEYN2/FTIA P7_7/AN7/DA1 5A 5B
KEY4 36 49 GND 10K HOME_X 6A 6B Z_RST
P6_3/KEYN3/FTIB P7_6/AN6/DA0 6A 6B
GND 3 5 KEY5 37 48 HOME_Z 7A 7B Z_DIR
C1- C2- P6_4/KEYN4/FTIC P7_5/AN5 Vacuum 7A 7B
HOME_X 38 47 DSEN4 HOME_Y 8A 8B Z_CLK
P6_5/KEYN5/FTID P7_4/AN4 C20 8A 8B
9 8 HOME_Y 39 46 DSEN3 VCC OUT_Y 9A 9B FLASHUG1
R2OUT R2IN P6_6/KEYN6/FTOB/IRQ6 P7_3/AN3 RN1A 0.1 9A 9B
R1 12 13 RX HOME_Z 40 45 DSEN2 2 1 BEEPER 10A 10B FLASHUG2
R1OUT R1IN RX P6_7/KEYN8/IRQ7 P7_2/AN2 10A 10B
DTR1 10 7 DTR VCC 41 44 DSEN1 10K 11A 11B
T2IN T2OUT DTR Vss P7_1/AN1 11A 11B
T1 11 14 TX 42 43 WASTE GND 12A 12B RESET
T1IN T1OUT TX AVcc P7_0/AN0 WASTE 12A 12B
GND M_GND 13A 13B
C3 13A 13B
MAX232CPA 14A 14B
0.1 14A 14B
HD64F3337CP16 +12V 15A 15B VCC GND
15A 15B
16A 16B
16A 16B
GND
DIN41612B32
A DSEN[1..4] A
DSEN[1..4]
REV ECO DESCRIPTION DRN DATE CHK UNLESS STATED TITLE DSX WASHER MODULE
1 N/A New R&D design PAH 01.12.97 05020012 RESISTORS 1/4W +/-1% PCB PART NO. 030-0502-06 SHEET 2 OF 3
2 N/A Specification Change APH 08.10.98 05020022 CAPS NON-POL +/-10% ECB PART NO. 580-0502-06 REV 6
3-5 N/A Development Changes KDU 30.06.99 CAPS POL +/-20% ORIGINATOR PAUL HIGGS DATE 01.12.97
6 N/A Specification change KDU 1 Jul 99 APPROVED ECO
7 Remove Unused Components and NMI TEL +44 1481 723777 KDU 1 Jan 00 DYNEX TECHNOLOGIES (GUERNSEY) LTD FAX +44 1481 711485
THIS DRAWING AND THE CONTENTS HEREIN CANNOT BE USED, COPIED OR DISCLOSED WITHOUT THE PRIOR WRITTEN PERMISSION OF DYNEX TECHNOLOGIES (GUERNSEY) LTD A2
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 N/A New Design APH 07.OCT98

2 N/A Development Mods KDU 19:MAY99
3 3971 Change Y Driver IC KDU 10 Jan 00
D D
VCC
C5 C7 C14
100N 100N 100N
XZ Drivers Y Drivers
GND 0510042.asc 0510041.asc
X_CLK D0b_Y D0b_Y
J2
D1b_Y D1b_Y
1A 1B X_RST
1A 1B X_RST D2b_Y D2b_Y
2A 2B X_DIR
2A 2B X_DIR D0a_Y D0a_Y
X_CLK 3A 3B Y_RST
3A 3B Y_RST D1a_Y D1a_Y
4A 4B Y_DIR
4A 4B Y_DIR D2a_Y D2a_Y
5A 5B Y_CLK
5A 5B Y_CLK Phb_Y Phb_Y
HOME_X 6A 6B Z_RST
6A 6B Z_RST Pha_Y Pha_Y
HOME_Z 7A 7B Z_DIR
C 7A 7B Z_DIR C
HOME_Y 8A 8B Z_CLK
8A 8B Z_CLK
OUT_Y 9A 9B FLASHUG1
9A 9B FLASH
BEEPER 10A 10B
10A 10B BEEPER
11A 11B
11A 11B
12A 12B RESET
12A 12B RESET
M_GND 13A 13B
13A 13B
14A 14B
14A 14B
+12V 15A 15B VCC GND
15A 15B
16A 16B
16A 16B
DIN41612/16X2AB
J1
1
HOME_X
2
3
HOME_Z
4
5
C10 C11
100N 100N
B B
GND
VCC +12v
R6
620R J4
1
2
3
HOME_Y
4
5
C12
100N
GND GND
VCC +12v DYNEX TECHNOLOGIES (Guernsey) Ltd

Rue Du Commerce
St Peter Port
R7 Guernsey, GY1 2HX
620R J3
A Washer Daughter Board A
1
2
3
OUT_Y
4
5
C13 Size FCSM No. DWG No. Rev
100N
A3 0510 3
GND GND
Scale Sheet
1 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

Flash Upgrade
FLASH
VCC
U1A +12V
1 X DRIVE
A
VCC C1 2 13 U5 VCC +12V
R1 B Q
3 4 + 13
CLR Q C16 Vcc
10k 14 C17 Phase1_X 16 24
Cext 100N Phase 1 Vbb
100N 15 D2 22uF I01_X 20
Rext/Cext I01
D I11_X 17 1 Z_MOTA1 D
I11 OUT 1A
MC74HC123A VCC
1N4148 M_GND 15 21 Z_MOTA2 J6
Vref 1 OUT 1B
GND U1B 14 1 Blue
RC1
9 D3 2 Yellow
A
10 5 U4 23 3 White
B Q E1
VCC C2 11 12 1 8 Phase2_X 10 4 Black
R2 CLR Q 1N4148 MR WDO Phase 2 R12
6 6 I02_X 8 22 5
Cext WDI C20 I02 SENSE 1
10k 7 5 R16 I12_X 9 1R 6
Rext/Cext PFO 220P I12
100N 4 7 RESET 47k M_GND
PFI RESET RESET
VCC MC74HC123A 11
R5 Vref 2
MAX705CPA 12 2 Z_MOTB1
RC2 OUT 2A
10k + C8
10UF 10V M_GND 5 Z_MOTB2
C21 OUT 2B
R17
D1 47k 220P 6
1N4148 GND
GND 7 3
GND E2
18
GND
19 4 R13
GND SENSE 2
1R
M_GND A2919SB
M_GND
M_GND
+12V
+ U6
Z DRIVE VCC +12V
C15 13
Vcc
C BEEPER +12V 22uF
C19 Phase1_Z 16
Phase 1 Vbb
24 C
100N I01_Z 20
I01
B1 I11_Z 17 1 X_MOTA1
I11 OUT 1A
VCC
BUZZER M_GND 15 21 X_MOTA2
Vref 1 OUT 1B
14 J7
RC1
1
1 Blue
23 Yellow
Q1 E1 2
Phase2_Z 10 White
R11 2N4401 Phase 2 R14 3
BEEPER 2 I02_Z 8 22 Black
BEEPER C18 I02 SENSE 1 4
10k R18 I12_Z 9 1R
220P I12 5
X_DIR R10 47k M_GND
X_DIR 6
X_CLK 10k 11
X_CLK Vref 2
X_RST 12 2 X_MOTB1
3
X_RST RC2 OUT 2A

Z_DIR
Z_DIR
Z_CLK M_GND 5 X_MOTB2
Z_CLK C22 OUT 2B
Z_RST R19
Z_RST 220P
Y_DIR 47k 6
Y_DIR GND
Y_CLK GND 7 3
Y_CLK GND E2
Y_RST 18
Y_RST GND
19 4 R15
GND SENSE 2
1R
M_GND A2919SB
U3
X_DIR 10 43 M_GND M_GND
IN 0 IO 31
11 42
IN 1/CLK0 IO 30
B X_CLK 13 41 B
IN 2/CLK1 IO 29
32 40
IN 3 IO 28
Z_CLK 33 39
IN 4/CLK2 IO 27
Y_CLK 35 38
IN 5/CLK3 IO 26
PHASE1_Z 2 37
IO 0 IO 25
I01_Z 3 36 X_RST
IO 1 IO 24
I11_Z 4 31 Z_DIR
IO 2 IO 23
PHASE2_Z 5 30 Z_RST
IO 3 IO 22
I02_Z 6 29 Y_DIR
IO 4 IO 21
I12_Z 7 28 Y_RST
IO 5 IO 20
PHASE1_X 8 27 D0b_Y
IO 6 IO 19 D0b_Y
I01_X 9 26 D1b_Y
IO 7 IO 18 D1b_Y
I11_X 14 25 D2b_Y
IO 8 IO 17 D2b_Y
PHASE2_X 15 24 Phb_Y
IO 9 IO 16 Phb_Y
I02_X 16 21 D0a_Y
IO 10 IO 15 D0a_Y
I12_X 17 20 D1a_Y
IO 11 IO 14 D1a_Y
Pha_Y 18 19 D2a_Y
Pha_Y IO 12 IO 13 D2a_Y
MACH211-15JC

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX

A3 0510 3
Scale Sheet
2 of 3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VCC
R3 U2 VCC
D 33K VRefY 2 6 +12v D
Vref Vcc
16
Load Supply
VRefY Pha_Y 7
Pha_Y Phase C6
D0a_Y 14 10 +
D0a_Y D0 OUT A
R25 D1a_Y 9 220U 25V
D1a_Y D1
22K D2a_Y 8 15
D2a_Y D2 OUT B
GND
3 Y_MOTA1
RC
GND PFDY 1
PFD
11 Y_MOTB1
C3 SENSE
VCC R23 4
220P GND
47K 5
GND
12 R9 R20
GND
R4 13 1R 1R
GND
10K J5
GND A3955SB Blue
1
PFDY GND
2
GND White
3
R8 Black
4
10K
5
6
GND
U7 VCC
VRefY 2 6 +12v
C Vref Vcc C
16
Load Supply C9
Phb_Y 7
Phb_Y Phase
D0b_Y 14 10 + 220U 25V
D0b_Y D0 OUT A
D1b_Y 9
D1b_Y D1
D2b_Y 8 15
D2b_Y D2 OUT B
GND
3 Y_MOTA2
RC
PFDY 1
PFD
11
C4 SENSE
R24 4 Y_MOTB2
220P GND
47K 5
GND
12 R21 R22
GND
13 1R 1R
GND
GND A3955SB
GND
GND
B B

Rue Du Commerce
St Peter Port
Guernsey, GY1 2HX

A3 0510 3
Scale Sheet
3 of 3
1 2 3 4 5 6 7 8

DSX Electronics Hardware

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DSX Circuit Board Diagrams

REV. ECO No. CHANGE DESCRIPTION INI. DATE

Z Transition And drive Z & Pipette Module

2.1.2. PCB Layout

REV. ECO No. CHANGE DESCRIPTION INI. DATE

FANS DYNEX TECHNOLOGIES (Guernsey) Ltd

3.1.2. PCB Layout

1. Scope of This Document

2 Hitachi H8/3397 Series, H8/3337, H8/3334Y F-ZTAT Hardware Manual

3 Maxim MAX705-MAX708/MAX813L Data Sheet

3. Circuit Block Diagram

Non Vol Storage

Controller Address Bus A(15..0) A(15..4) Address Decoding

Data Bus Data Bus Data Bus

UARTS & RS232

4.1. Flash upgrade Control

4.2. Address Decoding

Addresses have been chosen to reduce the decoding requirement as much as

4.2.1. UART Base Addresses

4.2.2. SRAM Addressing

4.2.3. Flash Control Ports Addresses

• Flash ports 8 to 15 F540

4.2.4. Power Monitor Address

4.2.5. DSR/DTR Addresses

Ports 8-15 F583

4.2.6. Float Switches State Address

4.3. Interrupt Decoding

• Comms Port • IRQ

4.3.2. System Monitoring

4.4. DSR/DTR Test

4.5. Power Monitoring.

4.6. Float Switches

4.7. Flash Selection.

5. Voltage generation and regulation

9 ports, providing 58 I/O and 8 Input lines

two 8-bit timers (TMR0, TMR1)

one 16-bit free-running counter (FRC)

two digital to analog channels (DA0, DA1), with 8-bit resolution

two serial communications channels (COM0, COM1)

two pulse width modulation channels (PWM0, PWM1)

6.1. Port Configurations and Operating Mode [2]

An external ST93C46CB1 serial EEPROM connected to port P4 is used to store

An MAX705[3] µprocessor supervisor IC is connected to the Reset input on the H8

6.2. H8 Operating Frequency

Hitachi part number HD64F3337YCP16.

6.4. 8-bit Timer, TMR0

6.5. 8-bit Timer, TMR1

6.6. 16-bit Free Running Counter (FRC)

6.7. Digital to Analog

6.7.1. Channel 0 (DA0)

6.7.2. Channel 1 (DA1)

6.8. A/D converter

6.8.1. Channel AN0

6.8.2. Channel AN1

6.8.3. Channel AN2

6.8.4. Channel AN3

6.8.5. Channel AN4

6.8.6. Channel AN5

6.8.7. Channel AN6

6.8.8. Channel AN7

6.9. Serial Communications

6.9.1. Channel 0 (COM0)

6.9.2. Channel 1 (COM1)

6.10. Pulse Width Modulation