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LAB NO 8
CMOS INVERTER OPTIMIZATION, POWER ANALYSIS
1. Objective
Performing power analysis and optimizing CMOS inverter.
2. Tools
NG spice software
MATLAB software
Capacitors
Resistors
VCC
Ground
3. Theory
Reduction in Power dissipation is an essential design issue in VLSI circuit. The
design parameters have conflicting effect on overall performance of the system. Depending
upon the component and function, different optimization approaches can be adopted. For
instance, power consumption in multiplier is data dependent as gate switching activity
contribute to more power consumption.
4. Procedure
circuit diagram:
1
Name Abdul Wahab Khan DIE LAB MANUAL CMS ID 43042
2
Name Abdul Wahab Khan DIE LAB MANUAL CMS ID 43042
Calculations of 10KHz.
2
𝑃𝐷𝑌𝑁𝐴𝑀𝐼𝐶 = 𝐶𝐿 𝑉𝐷𝐷 = 50𝑝 × 1.32 × 10𝐾
𝑃𝐷𝑌𝑁𝐴𝑀𝐼𝐶 = 8.47 × 10−7 𝑊.
Calculation of 0.1MHz.
2
𝑃𝐷𝑌𝑁𝐴𝑀𝐼𝐶 = 𝐶𝐿 𝑉𝐷𝐷 𝑓 = 50𝑝 × 1.32 × 10𝑀
𝑃𝐷𝑌𝑁𝐴𝑀𝐼𝐶 = 8.45 𝑢𝑊.
6. Conclusion
In this lab, we had performed the power analysis of CMOS inverter. We measured the
Dynamic-power of CMOS inverter at 10 KHz and 0.1 MHz and then compared both
manual and MATLAB results. We observed that both results are same.