Instruction Cycle

● The timing and control unit generates timing signals for the execution of the instructions
and control of peripheral devices
● The timing used for the execution of instruction and control of peripherals are different
from different microprocessors
● For the execution of an instruction a microprocessor fetches the instruction and executes
it
● The time taken for the execution of an instruction is called instruction cycle (IC) ..
● The instruction cycle of an instruction can be divided into two sub cycles
(1) Fetch cycle
(2) Execute cycle

Fetch operation
● The first byte an instruction is opcode
● An instruction may be more than one byte long. The other bytes are operand or operand
address
● The PC keeps the address of the next instruction to be executed
● In the begining of FC the content of PC, which is the address of the memory location
where the opcode is available is sent to the memory
● The memory places the opcode on the data bus so as to transfer it to the CPU
● In case os slow memory the processor has to wait till memory send the opcode.
● The clock cycle for which CPU wait is called wait cycle.
 Execute Operation
● the opcode fetched from the memory goes to instruction register , from there it goes to
decoder circuitry which decodes the instruction
● After decoding the instruction, execution begins.
● If the operand is in general purpose register execution is immediately performed.
● If an instruction contains operand address which are still in the memory, the CPU has
to perform some read operations to get the desired data.

Machine Cycle
● An instruction cycle consists of several machine cycles.
● Machine cycle of a processor are also called processor cycle.
●
To execute an instruction , the processor executes one or more machine cycles in a
particular sequence.
● The necessary steps carried out to perform a fetch or a read or a write operation
constitute a machine cycle
● In a machine cycle basic operations such as opcode fetch , memory read,memory write,
I/O read or I/O write performed
● The opcode of an instruction is fetched in the first machine cycle of an instruction
cycle.
● Most of the single byte instruction require only one machine cycle to fetch the opcode
and execute the instruction.
● Two byte and three byte instruction instructions requires more than one
machine cycle.
● The processor takes definite time to execute the machine cycle
● Time taken by the processor to execute the machine cycle is expressed in T
states.
● One T states equal to the time period of the internal clock of the processor
● Opcode fetch- 4T or 6T
Memory read (data)- 3T
Memory Write (data)-3T
IO read (data)-3T
IO write (data)- 3T
●
 Timing Diagram
● The necessary steps to which are carried out in a machine cycle can be
represented graphically. Such a graphical representation is called timing
diagram.
● It will give information about various condition of the signals while a
machine cycle is executed
● Only from the knowlwdge of timing diagram the matched peripheral devices
like memory,ports etc can be selected to form a system
Opcode fetch
● In a fetch cycle the microprocessor fetches the opcode of an instructin from the
memory
● The microprocessor issues a low IO/M signal to indicate that it wants to make
communication with the memory.
● Again microprocessor sends out high S0 and S1 signal to indicate that it is
going to perform fetch operation.
● During the first clock cycle, T1, microprocessor sends out the address of the
memory location where opcode is available. The 16 bit memory address is send
through the address bus A and address/date bus AD. Since AD bus is needed to
transfer data during subsequent clock cycle it is used in time multiplexed mode.
● To accomplish this the microprocessor sends an address latch enable signal ALE
to latch 8 LSB s of the memory address so that 16 bit may be available
● During T2 AD bus is ready to to carry data. In T2 the microprocessor makes
RD(bar) low. Now the memory gets the opcode from the specified memory
location and places it on the data bus.
● During T3 opcode is placed in the instruction register
● The fetch cycle is completed by T3. The opcode is decoded in T4
● If an instruction is one byte long only one machine cycle is is required to fetch
and execute the instruction eg:0 MOV, SUB, ADD, RAL
● As the operands are in the general purpose registers the decoding of the
operation code and its execution also takes place in T4
Memory Read
● In this cycle processor reads the content of a memory location. The content
is then placed either in the accumulator or any other register
● MVI A,05
Machine code of it is 3E,05
3E is the opcode for MVI A instruction and 05 is data
● This intruction requuires 2 machine cycle M1 and M2. First m/c is to fetch
the opcode from the memory and the second machine cycle is to read the
data ie 05 from the memory (memory read cycle)
● IO/M(bar) goes low indicating that the address is for memory
● S1 and S0 are set to 1 and 0 respectively for read operation
● During T1, 8 LSBs of the memory address of the data are sent on AD0-AD7.
During T2, AD0-AD7 are made free for data transmission.
● RD(bar) goes low during T2 to enable the memory for read operation. Now
data is placed on data bus.
● During T3 the data enters into accumulator
● Now consider a three byte instruction eg: LXI rp, data16
● This instruction requires 3 m/c one fetch and two consecutive memory read
cycles (2nd m/c to read 8 LSB of 16 bit data and 3rd for 8 MSBs of 16 bit
data)
● Eg 2: LDA 2400 H

● This instruction requires 4 m/c one fetch and two consecutive memory
read cycles (2nd m/c to read 8 LSB of 16 bit data and 3rd for 8 MSBs of
16 bit data) In the 4th m/c the microprocesoor reads the data from 2400
and get it to the accumulator.
●
Memory Write
● The status signal S0 and S1 are 1 and zero respectively for write operation
● WR(bar) goes low in T2 indicating that write operation is to be performed
● During T2 data is send out of the memory and placed on AD bus
● MOV M,A; STA 2500H etc use memory write cycle.

I/O Read

● In this cycle the microprocessor read the data available at an input port or
input device
● It is similar to memory read. The only difference is IO/M(bar) is high for IO
read
● It indicates that the address on the address bus is for an input device.
● IN instruction is used for I/O read, It is two byte long.
● It requires 3 m/c. One for opcode fetch, 2nd for memory read to read input
device address and third for I/O read cycle to read the data from the device
or port.
 I/O Write
● Similar to memory write
● Here also IO/M (bar) is high indicating that the address sent out by the CPU is
for IO device
● The OUT instruction is used for I/O write
● It requires 3 machine cycle. First machine cycle is opcode fetch operation, the
second is a memory read cycle for reading the I/O device address from memory
and the third machine cycle is an I/O write cycle sending data to the I/O
device