// Latency: 8

// Gap: 1
module codeBlock9103(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);

output next_out;
input clk, reset, next_in;

reg next;
input [1:0] i4_in;
reg [1:0] i4;

input [15:0] X0_in,

X1_in,
X2_in,
X3_in;

reg [15:0] X0,

X1,
X2,
X3;

output [15:0] Y0,

Y1,
Y2,
Y3;

shiftRegFIFO #(7, 1) shiftFIFO_11251(.X(next), .Y(next_out), .clk(clk));

wire signed [15:0] a233;

wire signed [15:0] a222;
wire signed [15:0] a236;
wire signed [15:0] a226;
wire signed [15:0] a237;
wire signed [15:0] a238;
reg signed [15:0] tm160;
reg signed [15:0] tm164;
reg signed [15:0] tm176;
reg signed [15:0] tm183;
reg signed [15:0] tm161;
reg signed [15:0] tm165;
reg signed [15:0] tm177;
reg signed [15:0] tm184;
wire signed [15:0] tm6;
wire signed [15:0] a227;
wire signed [15:0] tm7;
wire signed [15:0] a229;
reg signed [15:0] tm162;
reg signed [15:0] tm166;
reg signed [15:0] tm178;
reg signed [15:0] tm185;
reg signed [15:0] tm32;
reg signed [15:0] tm33;
 reg signed [15:0] tm163;
reg signed [15:0] tm167;
reg signed [15:0] tm179;
reg signed [15:0] tm186;
reg signed [15:0] tm180;
reg signed [15:0] tm187;
wire signed [15:0] a228;
wire signed [15:0] a230;
wire signed [15:0] a231;
wire signed [15:0] a232;
reg signed [15:0] tm181;
reg signed [15:0] tm188;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm182;
reg signed [15:0] tm189;

assign a233 = X0;

assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm6;
assign a229 = tm7;
assign Y0 = tm182;
assign Y1 = tm189;

D14_9275 instD14inst0_9275(.addr(i4[1:0]), .out(tm6), .clk(clk));

D16_9287 instD16inst0_9287(.addr(i4[1:0]), .out(tm7), .clk(clk));

multfix #(16, 2) m9202(.a(tm32), .b(tm163), .clk(clk), .q_sc(a228),

.q_unsc(), .rst(reset));
multfix #(16, 2) m9224(.a(tm33), .b(tm167), .clk(clk), .q_sc(a230),
.q_unsc(), .rst(reset));
multfix #(16, 2) m9242(.a(tm33), .b(tm163), .clk(clk), .q_sc(a231),
.q_unsc(), .rst(reset));
multfix #(16, 2) m9253(.a(tm32), .b(tm167), .clk(clk), .q_sc(a232),
.q_unsc(), .rst(reset));
subfxp #(16, 1) sub9231(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add9260(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6

always @(posedge clk) begin

if (reset == 1) begin
tm32 <= 0;
tm163 <= 0;
tm33 <= 0;
tm167 <= 0;
tm33 <= 0;
tm163 <= 0;
tm32 <= 0;
tm167 <= 0;
end
else begin
 i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm160 <= a237;
tm164 <= a238;
tm176 <= a222;
tm183 <= a226;
tm161 <= tm160;
tm165 <= tm164;
tm177 <= tm176;
tm184 <= tm183;
tm162 <= tm161;
tm166 <= tm165;
tm178 <= tm177;
tm185 <= tm184;
tm32 <= a227;
tm33 <= a229;
tm163 <= tm162;
tm167 <= tm166;
tm179 <= tm178;
tm186 <= tm185;
tm180 <= tm179;
tm187 <= tm186;
tm181 <= tm180;
tm188 <= tm187;
tm182 <= tm181;
tm189 <= tm188;
end
end
endmodule