ACS714 Datasheet PDF

ACS714
Automotive Grade, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC

with 2.1 kVRMS Voltage Isolation and Low-Resistance Current Conductor
Not for New Design

These parts are in production but have been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications.
The device should not be purchased for new design applications
because obsolescence in the near future is probable. Samples are no
longer available.
Date of status change: June 5, 2017
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, use ACS724.
NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.
Allegro MicroSystems reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The infor-
mation included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for
its use; nor for any infringements of patents or other rights of third parties which may result from its use.
ACS714
Automotive Grade, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC
Features and Benefits Description

▪ Low-noise analog signal path The Allegro™ ACS714 provides economical and precise
▪ Device bandwidth is set via the FILTER pin solutions for AC or DC current sensing in automotive systems.
▪ 5 µs output rise time in response to step input current The device package allows for easy implementation by the
▪ 80 kHz bandwidth
customer. Typical applications include motor control, load
▪ Total output error 1.5% typical, at TA = 25°C
▪ Small footprint, low-profile SOIC8 package
detection and management, switch-mode power supplies, and
▪ 1.2 mΩ internal conductor resistance overcurrent fault protection.
▪ 2.1 kVRMS minimum isolation voltage from pins 1-4 to pins 5-8 The device consists of a precise, low-offset, linear Hall circuit
▪ 5.0 V, single supply operation
with a copper conduction path located near the surface of the
▪ 66 to 185 mV/A output sensitivity
▪ Output voltage proportional to AC or DC currents
die. Applied current flowing through this copper conduction
▪ Factory-trimmed for accuracy path generates a magnetic field which the Hall IC converts into a
▪ Extremely stable output offset voltage proportional voltage. Device accuracy is optimized through the
▪ Nearly zero magnetic hysteresis close proximity of the magnetic signal to the Hall transducer.
▪ Ratiometric output from supply voltage A precise, proportional voltage is provided by the low-offset,
▪ Operating temperature range, –40°C to 150°C chopper-stabilized BiCMOS Hall IC, which is programmed
for accuracy after packaging.
TÜV America
Certificate Number:
U8V 15 05 54214 038
The output of the device has a positive slope (>VIOUT(Q))
CB 13 06 54214 026 when an increasing current flows through the primary copper
conduction path (from pins 1 and 2, to pins 3 and 4), which is
the path used for current sampling. The internal resistance of
Package: 8-pin SOIC (suffix LC) this conductive path is 1.2 mΩ typical, providing low power
loss. The thickness of the copper conductor allows survival of
the device at up to 5× overcurrent conditions. The terminals of
Continued on the next page…
Not to scale
Typical Application
+5 V
8
1 VCC
IP+
7 VOUT
2 CBYP
IP+ VIOUT
0.1 µF
IP ACS714
3 6
IP– FILTER CF
4
IP– 5 1 nF
GND
Application 1. The ACS714 outputs an analog signal, VOUT .

that varies linearly with the uni- or bi-directional AC or DC
primary sampled current, IP , within the range specified. CF
is recommended for noise management, with values that
depend on the application.
ACS714-DS, Rev. 12 May 17, 2019

MCO-0000199
ACS714 Automotive Grade, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC
Description (continued)
the conductive path are electrically isolated from the signal leads The leadframe is plated with 100% matte tin, which is compatible
(pins 5 through 8). This allows the ACS714 to be used in applications with standard lead (Pb) free printed circuit board assembly processes.
requiring electrical isolation without the use of opto-isolators or Internally, the device is Pb-free, except for flip-chip high-temperature
other costly isolation techniques. Pb‑based solder balls, currently exempt from RoHS. The device is
The ACS714 is provided in a small, surface mount SOIC8 package. fully calibrated prior to shipment from the factory.
Selection Guide
Optimized Range, IP Sensitivity, Sens TA
Part Number Packing*
(A) (Typ) (mV/A) (°C)
ACS714ELCTR-05B-T ±5 185
ACS714ELCTR-20A-T ±20 100 –40 to 85
ACS714ELCTR-30A-T ±30 66
ACS714LLCTR-05B-T ±5 185 Tape and reel, 3000 pieces/reel
ACS714LLCTR-20A-T ±20 100
–40 to 150
*Contact Allegro for additional packing options.
Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
Supply Voltage VCC 8 V
Reverse Supply Voltage VRCC –0.1 V
Output Voltage VIOUT 8 V
Reverse Output Voltage VRIOUT –0.1 V
Output Current Source IIOUT(Source) 3 mA
Output Current Sink IIOUT(Sink) 10 mA
Overcurrent Transient Tolerance IP 1 pulse, 100 ms 100 A
Range E –40 to 85 ºC
Nominal Operating Ambient Temperature TA
Range L –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC
Isolation Characteristics
Characteristic Symbol Notes Rating Unit
Agency type-tested for 60 seconds per
Dielectric Strength Test Voltage* VISO 2100 VAC
UL standard 60950-1, 1st Edition
For basic (single) isolation per UL standard
Working Voltage for Basic Isolation VWFSI 354 VDC or Vpk
60950-1, 1st Edition
For reinforced (double) isolation per UL standard
Working Voltage for Reinforced Isolation VWFRI 184 VDC or Vpk
60950-1, 1st Edition
* Allegro does not conduct 60-second testing. It is done only during the UL certification process.
Parameter Specification
CAN/CSA-C22.2 No. 60950-1-03
Fire and Electric Shock UL 60950-1:2003
EN 60950-1:2001
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Block Diagram

+5 V
VCC
(Pin 8)
Hall Current
Drive
IP+ Sense Temperature

(Pin 1)
Coefficient Trim
IP+
(Pin 2)
Dynamic Offset
Cancellation
Signal VIOUT
Recovery (Pin 7)
RF(INT)
IP−
(Pin 3)
Sense
Trim
IP−
(Pin 4) 0 Ampere
Offset Adjust
GND FILTER
(Pin 5) (Pin 6)
Pin-out Diagram
IP+ 1 8 VCC
IP+ 2 7 VIOUT
IP– 3 6 FILTER
IP– 4 5 GND
Terminal List Table

Number Name Description
1 and 2 IP+ Terminals for current being sampled; fused internally
3 and 4 IP– Terminals for current being sampled; fused internally
5 GND Signal ground terminal
6 FILTER Terminal for external capacitor that sets bandwidth
7 VIOUT Analog output signal
8 VCC Device power supply terminal
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COMMON OPERATING CHARACTERISTICS1 over full range of TA , CF = 1 nF, and VCC = 5 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Current ICC VCC = 5.0 V, output open – 10 13 mA
Output Capacitance Load CLOAD VIOUT to GND – – 10 nF
Output Resistive Load RLOAD VIOUT to GND 4.7 – – kΩ
Primary Conductor Resistance RPRIMARY TA = 25°C – 1.2 – mΩ
Rise Time tr IP = IP(max), TA = 25°C, COUT = open – 3.5 – μs
Frequency Bandwidth f –3 dB, TA = 25°C; IP is 10 A peak-to-peak – 80 – kHz
Nonlinearity ELIN Over full range of IP – 1.5 – %
Symmetry ESYM Over full range of IP 98 100 102 %
VCC ×
Zero Current Output Voltage VIOUT(Q) Bidirectional; IP = 0 A, TA = 25°C – – V
0.5
Output reaches 90% of steady-state level, TJ = 25°C, 20 A  present
Power-On Time tPO – 35 – µs
on leadframe
Magnetic Coupling2 – 12 – G/A
Internal Filter Resistance3 RF(INT) 1.7 kΩ
1Device may be operated at higher primary current levels, IP, and ambient, TA , and internal leadframe temperatures, TA , provided that the Maximum
Junction Temperature, TJ(max), is not exceeded.
21G = 0.1 mT.
3R
F(INT) forms an RC circuit via the FILTER pin.
COMMON THERMAL CHARACTERISTICS1

Min. Typ. Max. Units
E range –40 – 85 °C
Operating Internal Leadframe Temperature TA
L range –40 – 150 °C
Value Units
Junction-to-Lead Thermal Resistance2 RθJL Mounted on the Allegro ASEK 714 evaluation board 5 °C/W
Mounted on the Allegro 85-0322 evaluation board, includes the power con-
Junction-to-Ambient Thermal Resistance RθJA 23 °C/W
sumed by the board
1Additional thermal information is available on the Allegro website.
2The Allegro evaluation board has 1500 mm2 of 2 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connect-
ing the layers. Performance values include the power consumed by the PCB. Further details on the board are available from the Frequently Asked
Questions document on our website. Further information about board design and thermal performance also can be found in the Applications Informa-
tion section of this datasheet.
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x05B PERFORMANCE CHARACTERISTICS1 over Range E: TA = –40°C to 85°C, CF = 1 nF, and VCC = 5 V, unless otherwise specified
Optimized Accuracy Range IP –5 – 5 A
Sensitivity Sens Over full range of IP, TA = 25°C 180 185 190 mV/A
Peak-to-peak, TA = 25°C, 185 mV/A programmed Sensitivity,
Noise VNOISE(PP) – 21 – mV
CF = 47 nF, COUT = open, 2 kHz bandwidth
TA = –40°C to 25°C – –0.26 – mV/°C
Zero Current Output Slope ∆VOUT(Q)
TA = 25°C to 150°C – –0.08 – mV/°C
TA = –40°C to 25°C – 0.054 – mV/A/°C
Sensitivity Slope ∆Sens
TA = 25°C to 150°C – –0.008 – mV/A/°C
Electrical Output Voltage VOE IP = 0 A –40 – 40 mV
Total Output Error2 ETOT IP =±5 A, TA = 25°C – ±1.5 – %
1Device may be operated at higher primary current levels, IP, and ambient temperatures, TA, provided that the Maximum Junction Temperature, TJ(max),
is not exceeded.
2Percentage of I , with I = 5 A. Output filtered.
P P
x05B PERFORMANCE CHARACTERISTICS1 over Range L: TA = –40°C to 150°C, CF = 1 nF, and VCC = 5 V, unless otherwise specified
Sensitivity Sens Over full range of IP, TA = 25°C – 185 – mV/A
TA = –40°C to 25°C – –0.26 – mV/°C
TA = 25°C to 150°C – –0.08 – mV/°C
TA = –40°C to 25°C – 0.054 – mV/A/°C
TA = 25°C to 150°C – –0.008 – mV/A/°C
IP =±5 A, TA = 25°C – ±1.5 – %
Total Output Error2 ETOT
IP =±5 A, TA = –40°C to 150°C –7 – 7 %
1Device may be operated at higher primary current levels, IP, and ambient temperatures, TA, provided that the Maximum Junction Temperature, TJ(max),
is not exceeded.
P P
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x20A PERFORMANCE CHARACTERISTICS over Range E: TA = –40°C to 85°C1, CF = 1 nF, and VCC = 5 V, unless otherwise specified
TA = –40°C to 25°C – –0.34 – mV/°C
TA = 25°C to 150°C – –0.07 – mV/°C
TA = –40°C to 25°C – 0.017 – mV/A/°C
TA = 25°C to 150°C – –0.004 – mV/A/°C
Total Output Error2 ETOT IP = ±20 A, TA = 25°C – ±1.5 – %
1Device may be operated at higher primary current levels, IP, and ambient temperatures, TA, provided that the Maximum Junction Temperature,
TJ(max), is not exceeded.
P P
x20A PERFORMANCE CHARACTERISTICS over Range L: TA = –40°C to 150°C1, CF = 1 nF, and VCC = 5 V, unless otherwise specified
Over full range of IP, TA = 25°C – 100 – mV/A
Sensitivity Sens
Over full range of IP, TA = –40°C to 150°C 94 – 104 mV/A
CF = 47 nF, COUT = out, 2 kHz bandwidth
TA = –40°C to 25°C – –0.34 – mV/°C
TA = 25°C to 150°C – –0.07 – mV/°C
TA = –40°C to 25°C – 0.017 – mV/A/°C
TA = 25°C to 150°C – –0.004 – mV/A/°C
IP = ±20 A, TA = 25°C – ±1.5 – %
IP = ±20 A, TA = –40°C to 150°C –5 – 5 %
P P
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x30A PERFORMANCE CHARACTERISTICS over Range E: TA = –40°C to 85°C1, CF = 1 nF, and VCC = 5 V, unless otherwise specified
TA = –40°C to 25°C – –0.35 – mV/°C
TA = 25°C to 150°C – –0.08 – mV/°C
TA = –40°C to 25°C – 0.007 – mV/A/°C
TA = 25°C to 150°C – –0.002 – mV/A/°C
Total Output Error2 ETOT IP = ±30 A , TA = 25°C – ±1.5 – %
P P
Sensitivity Sens
Over full range of IP, TA = –40°C to 150°C 63 – 69 mV/A
TA = –40°C to 25°C – –0.35 – mV/°C
TA = 25°C to 150°C – –0.08 – mV/°C
TA = –40°C to 25°C – 0.007 – mV/A/°C
TA = 25°C to 150°C – –0.002 – mV/A/°C
IP = ±30 A , TA = 25°C – ±1.5 – %
IP = ±30 A , TA = –40°C to 150°C –5 – 5 %
P P
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Sensitivity Sens
Over full range of IP, TA = –40°C to 150°C 37.5 – 42.5 mV/A
Noise VNOISE(PP) – 4.5 – mV
TA = –40°C to 25°C – –0.35 – mV/°C
TA = 25°C to 150°C – –0.08 – mV/°C
TA = –40°C to 25°C – 0.007 – mV/A/°C
TA = 25°C to 150°C – –0.002 – mV/A/°C
Electrical Output Voltage VOE IP = 0 A, TA = 25°C –40 – 40 mV
IP = ±40 A , TA = 25°C – ±1.5 – %
IP = ±40 A , TA = –40°C to 150°C – ±6 – %
P P
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Characteristic Performance
IP = 5 A, unless otherwise specified
Mean Supply Current versus Ambient Temperature Supply Current versus Supply Voltage
10.30 10.9
10.25 10.8
10.20
10.7
10.15
ICC (mA)
10.10 10.6
Mean ICC (mA)
10.05 VCC = 5 V 10.5

10.00 10.4
9.95
10.3
9.90
10.2
9.85
9.80 10.1
9.75 10.0
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (°C) VCC (V)
Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

0 0.6
–0.5
–1.0 0.5
–1.5 VCC = 5 V
0.4
ELIN (%)
IOM (mA)
–2.0
VCC = 5 V; IP = 0 A,
–2.5 0.3
After excursion to 20 A
–3.0
–3.5 0.2
–4.0
0.1
–4.5
–5.0 0
-50 -25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Mean Total Output Error versus Ambient Temperature Sensitivity versus Ambient Temperature
8 186.5
6 186.0
185.5
Sens (mV/A)
4 185.0
ETOT (%)
2 184.5
184.0
0
183.5
–2 183.0
–4 182.5
182.0
–6 181.5
–8 181.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Output Voltage versus Sensed Current Sensitivity versus Sensed Current

4.0 200.00
3.5 190.00
180.00
3.0 VCC = 5 V
Sens (mV/A)
170.00
VIOUT (V)
2.5 160.00 TA (°C)

2.0 TA (°C) 150.00 –40
–40 140.00 25
1.5 25 85
85 130.00 150
1.0
150 120.00
0.5 110.00
0 100.00
–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 -6 -4 -2 0 2 4 6
Ip (A)
IP (A)
0 A Output Voltage versus Ambient Temperature 0 A Output Voltage Current versus Ambient Temperature
2520 0.20
2515 0.15
2510 IP = 0 A 0.10 IP = 0 A
VIOUT(Q) (mV)
IOUT(Q) (A)
2505 0.05
2500 0
2495 –0.05
2490 –0.10
2485 –0.15
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
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9.7 10.4
9.6 10.2
10.0
9.5
Mean ICC (mA)
ICC (mA)
9.8
9.4 VCC = 5 V
9.6
9.3
9.4
9.2 9.2
9.1 9.0
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (°C) VCC (V)

0 0.35
–0.5
0.30
–1.0
–1.5 0.25
ELIN (%)
–2.0 0.20
IOM (mA)
–2.5 VCC = 5 V; IP = 0 A,
After excursion to 20 A 0.15
–3.0
–3.5 0.10
–4.0
0.05
–4.5
–5.0 0
-50 -25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)
8 100.8
6 100.6
4 100.4
100.2
Sens (mV/A)
2
ETOT (%)
100.0
0
99.8
–2
99.6
–4 99.4
–6 99.2
–8 99.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)
5.0 110.00
4.5 108.00 TA (°C)
–40
4.0 106.00
25
3.5 VCC = 5 V 104.00 85
Sens (mV/A)
3.0 102.00 150

VIOUT (V)
2.5 TA (°C) 100.00

–40 98.00
2.0
–20
1.5 25 96.00
1.0 85 94.00
0.5 125 92.00
0 90.00
–25 –20 –15 –10 –5 0 5 10 15 20 25 –25 –20 –15 –10 –5 0 5 10 15 20 25
Ip (A)
IP (A)
2525 0.25
2520 0.20
2515 0.15
VIOUT(Q) (mV)
IP = 0 A
IOUT(Q) (A)
2510 IP = 0 A 0.10
2505 0.05
2500 0
2495 –0.05
2490 –0.10
2485 –0.15
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
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9.6 10.2
9.5 10.0
9.4
9.8
ICC (mA)
Mean ICC (mA)
9.3 VCC = 5 V
9.6
9.2
9.4
9.1
9.0 9.2
8.9 9.0
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (°C) VCC (V)

0 0.45
–0.5 0.40
–1.0 0.35
–1.5 0.30 VCC = 5 V
ELIN (%)
IOM (mA)
–2.0
0.25
–2.5 VCC = 5 V; IP = 0 A,
0.20
–3.0 After excursion to 20 A
0.15
–3.5
–4.0 0.10
–4.5 0.05
–5.0 0
-50 -25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)
8 66.6
6 66.5
66.4
Sens (mV/A)
4
66.3
ETOT (%)
2
66.2
0
66.1
–2
66.0
–4 65.9
–6 65.8
–8 65.7
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)

5.0 70.00
4.5 69.00
4.0 68.00
Sens (mV/A)
3.5 VCC = 5 V 67.00

VIOUT (V)
3.0 66.00
2.5 TA (°C) 65.00
–40 64.00 TA (°C)
2.0
–20 –40
1.5 25 63.00
25
1.0 85 62.00 85
0.5 125 61.00 150
0 60.00
–30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30
Ip (A)
IP (A)
2535 0.35
2530 0.30
2525 0.25
2520 0.20
VIOUT(Q) (mV)
2515 IP = 0 A 0.15 IP = 0 A
IOUT(Q) (A)
2510 0.10
2505 0.05
2500 0
2495 –0.05
2490 –0.10
2485 –0.15
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
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9.8 10.2
9.7
10.0
9.6
9.5 9.8
ICC (mA)
Mean ICC (mA)
9.4 VCC = 5 V
9.6
9.3
9.2 9.4
9.1
9.2
9.0
8.9 9.0
-50 -25 0 25 50 75 100 125 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
TA (°C) VCC (V)

0 0.50
–0.5 0.45
–1.0 0.40
–1.5 0.35
ELIN (%)
0.30 VCC = 5 V
IOM (mA)
–2.0
–2.5 VCC = 5 V; IP = 0 A, 0.25
–3.0 After excursion to 20 A 0.20
–3.5 0.15
–4.0 0.10
–4.5 0.05
–5.0 0
-50 -25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)
8 39.10
6
39.05
Sens (mV/A)
4
39.00
ETOT (%)
2
0 38.95
–2 38.90
–4
38.85
–6
–8 38.80
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TA (°C) TA (°C)

5.0 45.00
4.5 44.00
4.0 43.00 TA (°C)
Sens (mV/A)
3.5 VCC = 5 V 42.00 –40

VIOUT (V)
25
3.0 41.00 150
2.5 40.00
2.0 TA (°C) 39.00
1.5 –40 38.00
1.0 25 37.00
0.5 125 36.00
0 35.00
-40 -30 -20 -10 0 10 20 30 40 -40 -30 -20 -10 0 10 20 30 40
Ip (A)
IP (A)
2526 0.70
2523 0.60
2520
2517 0.50
2514 0.40
VIOUT(Q) (mV)
2511 IP = 0 A 0.30 IP = 0 A
IOUT(Q) (A)
2508
2505 0.20
2502 0.10
2499 0
2496
–0.10
2493
2490 –0.20
2487 –0.30
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
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Definitions of Accuracy Characteristics

Sensitivity (Sens). The change in device output in response to a Accuracy is divided into four areas:
1 A change through the primary conductor. The sensitivity is the
• 0 A at 25°C. Accuracy at the zero current flow at 25°C, with-
product of the magnetic circuit sensitivity (G / A) and the linear
out the effects of temperature.
IC amplifier gain (mV/G). The linear IC amplifier gain is pro-
grammed at the factory to optimize the sensitivity (mV/A) for the • 0 A over Δ temperature. Accuracy at the zero current flow
full-scale current of the device. including temperature effects.
Noise (VNOISE). The product of the linear IC amplifier gain • Full-scale current at 25°C. Accuracy at the the full-scale current
(mV/G) and the noise floor for the Allegro Hall effect linear IC at 25°C, without the effects of temperature.
(≈1 G). The noise floor is derived from the thermal and shot • Full-scale current over Δ temperature. Accuracy at the full-
noise observed in Hall elements. Dividing the noise (mV) by the scale current flow including temperature effects.
sensitivity (mV/A) provides the smallest current that the device is
Ratiometry. The ratiometric feature means that its 0 A output,
able to resolve.
VIOUT(Q), (nominally equal to VCC/2) and sensitivity, Sens, are
Linearity (ELIN). The degree to which the voltage output from proportional to its supply voltage, VCC . The following formula is
the IC varies in direct proportion to the primary current through
used to derive the ratiometric change in 0 A output voltage,
its full-scale amplitude. Nonlinearity in the output can be attrib-
uted to the saturation of the flux concentrator approaching the ΔVIOUT(Q)RAT (%).
full-scale current. The following equation is used to derive the

VIOUT(Q)VCC / VIOUT(Q)5V

linearity: 100
VCC / 5 V
{ [
100 1–
∆ gain × % sat ( VIOUT_full-scale amperes – VIOUT(Q) )
2 (VIOUT_half-scale amperes – VIOUT(Q) ) [{ The ratiometric change in sensitivity, ΔSensRAT (%), is defined as:
SensVCC / Sens5V
where VIOUT_full-scale amperes = the output voltage (V) when the 100
sampled current approximates full-scale ±IP . ‰ VCC / 5 V
Symmetry (ESYM). The degree to which the absolute voltage
output from the IC varies in proportion to either a positive or Output Voltage versus Sampled Current
Accuracy at 0 A and at Full-Scale Current
negative full-scale primary current. The following formula is
used to derive symmetry: Increasing VIOUT(V)
Accuracy
VIOUT_+ full-scale amperes – VIOUT(Q)
 VIOUT(Q) – VIOUT_–full-scale amperes 

Over ∆Temp erature
100
Accuracy
25°C Only
Quiescent output voltage (VIOUT(Q)). The output of the device

Average
when the primary current is zero. For a unipolar supply voltage, VIOUT
it nominally remains at VCC ⁄ 2. Thus, VCC = 5 V translates into Accuracy
VIOUT(Q) = 2.5 V. Variation in VIOUT(Q) can be attributed to the Over ∆Temp erature
resolution of the Allegro linear IC quiescent voltage trim and Accuracy

thermal drift. IP(min)
25°C Only
Electrical offset voltage (VOE). The deviation of the device out- –IP (A) +IP (A)
put from its ideal quiescent value of VCC / 2 due to nonmagnetic Full Scale
IP(max)
causes. To convert this voltage to amperes, divide by the device
sensitivity, Sens. 0A
Accuracy (ETOT). The accuracy represents the maximum devia-

tion of the actual output from its ideal value. This is also known
as the total output error. The accuracy is illustrated graphically in Accuracy
25°C Only
the output voltage versus current chart at right. Accuracy

Over ∆Temp erature
Decreasing VIOUT(V)
13
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Definitions of Dynamic Response Characteristics
Power-On Time (tPO). When the supply is ramped to its operat-

ing voltage, the device requires a finite time to power its internal
components before responding to an input magnetic field.
Power-On Time, tPO , is defined as the time it takes for the output
voltage to settle within ±10% of its steady state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
Rise time (tr). The time interval between a) when the device I (%) Primary Current
reaches 10% of its full scale value, and b) when it reaches 90% 90
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the device, in which ƒ(–3 dB) = 0.35 / tr.
Both tr and tRESPONSE are detrimentally affected by eddy current 10
Transducer Output
losses observed in the conductive IC ground plane. 0

t
Rise Time, tr
Power on Time versus External Filter Capacitance Step Response

200
TA=25°C
180
160 IP = 5 A
140
120
tPO (µs)
IP = 0 A
100
80
60
40
20
0 Output (mV)
0 10 20 30 40 50
CF (nF)
Noise vs. Filter Cap
Noise versus External Filter Capacitance 15 A
10000
Excitation Signal
1000
Noise(p-p) (mA)
100
10
1
0.01 0.1 1 10 100 1000
CF (nF)
Rise Time versus External Filter Capacitance Rise Time versus External Filter Capacitance
1200 180
CF (nF) tr (µs) 160
1000
Open 3.5 140
800 1 5.8 120
tr(µs)
tr(µs)
Expanded in chart at right 4.7 17.5 100

600
22 73.5 80
}
400 47 88.2 60
100 291.3 40
200 220 623 20
0 470 1120 0
0.1 1 10 100 1000 0.1 1 10 100
CF (nF) CF (nF)
14
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Chopper Stabilization Technique
Chopper Stabilization is an innovative circuit technique that is This technique is made possible through the use of a BiCMOS
used to minimize the offset voltage of a Hall element and an process that allows the use of low-offset and low-noise amplifiers
associated on-chip amplifier. Allegro has a Chopper Stabiliza- in combination with high-density logic integration and sample
tion technique that nearly eliminates Hall IC output drift induced and hold circuits.
by temperature or package stress effects. This offset reduction
technique is based on a signal modulation-demodulation process. Regulator
Modulation is used to separate the undesired DC offset signal

from the magnetically induced signal in the frequency domain. Clock/Logic
Then, using a low-pass filter, the modulated DC offset is sup- Hall Element
Low-Pass
Filter
pressed while the magnetically induced signal passes through
Sample and
the filter. As a result of this chopper stabilization approach, the
Hold
Amp
output voltage from the Hall IC is desensitized to the effects
of temperature and mechanical stress. This technique produces
devices that have an extremely stable Electrical Offset Voltage,
are immune to thermal stress, and have precise recoverability
after temperature cycling.
Concept of Chopper Stabilization Technique
Typical Applications
+5 V
+5 V
VPEAK
CBYP
CBYP R1
C2 0.1 µF 100 kΩ
0.1 µF 0.1 µF VRESET
R4 Q1
10 kΩ 2N7002 R2
8 COUT 100 kΩ LM321
1 VCC 0.1 µF 8 1 + 5
IP+ 1 4 VOUT
7 VOUT + IP+ VCC
2
IP+ VIOUT 2 7 3 –
RF IP+ VIOUT 2
IP ACS714 10 kΩ
– RF
R1 U1 D1 C1
6 LT1178 1N914 IP ACS714 1 kΩ
3 1 MΩ 1000 pF
IP– FILTER CF 3 6 R3
4 1 nF IP– FILTER CF
3.3 kΩ
IP– 5 4
GND IP– 5 0.01 µF
R3 C1 GND
R2 0.1 µF
33 kΩ 330 kΩ
Application 3. This configuration increases gain to 610 mV/A

(tested using the ACS714ELC-05A).
Application 2. Peak Detecting Circuit
+5 V
+5 V
CBYP
R1
0.1 µF 33 kΩ
CBYP
0.1 µF RPU
R2 100 kΩ
100 kΩ
8 8
1 1 VCC
VCC D1 IP+
IP+ 1N4448W 7 VOUT 4
2 7 VOUT 2 5
IP+ VIOUT
A-to-D IP+ VIOUT – 1 Fault
Converter
RF 3
IP ACS714 IP ACS714 +
2 kΩ R1 2 U1
6 C1 3 6
LMV7235
3
IP– FILTER
10 kΩ IP– FILTER CF
CF 4 1 nF
4 1 nF IP– 5
IP– 5 GND
GND
D1
1N914
Application 4. Rectified Output. 3.3 V scaling and rectification application Application 5. 10 A Overcurrent Fault Latch. Fault threshold set by R1 and
for A-to-D converters. Replaces current transformer solutions with simpler R2. This circuit latches an overcurrent fault and holds it until the 5 V rail is
ACS circuit. C1 is a function of the load resistance and filtering desired. powered down.
R1 can be omitted if the full range is desired.
15
955 Perimeter Road
Improving Sensing System Accuracy Using the FILTER Pin
In low-frequency sensing applications, it is often advantageous temperature. Therefore, signal attenuation will vary as a function
to add a simple RC filter to the output of the device. Such a low- of temperature. Note that, in many cases, the input impedance,
pass filter improves the signal-to-noise ratio, and therefore the RINTFC , of a typical analog-to-digital converter (ADC) can be as
resolution, of the device output signal. However, the addition of low as 10 kΩ.
an RC filter to the output of a sensor IC can result in undesirable
device output attenuation — even for DC signals. The ACS714 contains an internal resistor, a FILTER pin connec-
tion to the printed circuit board, and an internal buffer amplifier.
Signal attenuation, ∆VATT , is a result of the resistive divider
With this circuit architecture, users can implement a simple
effect between the resistance of the external filter, RF (see
Application 6), and the input impedance and resistance of the RC filter via the addition of a capacitor, CF (see Application 7)
customer interface circuit, RINTFC. The transfer function of this from the FILTER pin to ground. The buffer amplifier inside of
resistive divider is given by: the ACS714 (located after the internal resistor and FILTER pin
 RINTFC  connection) eliminates the attenuation caused by the resistive
∆VATT = VIOUT  . divider effect described in the equation for ∆VATT. Therefore, the
 RF + RINTFC 
  ACS714 device is ideal for use in high-accuracy applications
Even if RF and RINTFC are designed to match, the two individual that cannot afford the signal attenuation associated with the use
resistance values will most likely drift by different amounts over of an external RC low-pass filter.
+5 V
Pin 3 Pin 4 VCC

IP– IP– Pin 8
Allegro ACS706
Application 6. When a low pass filter is constructed
externally to a standard Hall effect device, a resistive Voltage
Regulator
divider may exist between the filter resistor, RF, and To all subcircuits
the resistance of the customer interface circuit, RINTFC.
VIOUT Resistive Divider
This resistive divider will cause excessive attenuation, Pin 7
Dynamic Offset
Input
Cancellation
as given by the transfer function for ∆VATT. RF

Filter
Amp Out N.C. Application

0.1 µF Pin 6 Interface
Circuit
Low Pass Filter
Temperature
Gain Offset CF
Coefficient
1 nF RINTFC
Trim Control
IP+ IP+ GND

Pin 1 Pin 2 Pin 5
+5 V
VCC
Pin 8
Allegro ACS714
Application 7. Using the FILTER pin
provided on the ACS714 eliminates the Hall Current
Drive
attenuation effects of the resistor divider
between RF and RINTFC, shown in Appli- IP+
Pin 1 Sense Temperature
Coefficient Trim
cation 6. IP+ Buffer Amplifier
Pin 2
Dynamic Offset
and Resistor
Cancellation
Signal VIOUT
Recovery Pin 7
Input
IP– Application
Pin 3 Interface
Sense
Trim Circuit
IP–
Pin 4 0 Ampere
Offset Adjust
RINTFC
GND FILTER
Pin 5 Pin 6 CF
1 nF
16
955 Perimeter Road
Package LC, 8-pin SOIC
4.90 ±0.10
8°
0° 8 1.27
0.65
8
1.75
0.25
0.17
3.90 ±0.10 6.00 ±0.20 5.60

A
1.04 REF
1 2 1 2
1.27
0.40
0.25 BSC C PCB Layout Reference View

SEATING PLANE
Branded Face
GAUGE PLANE
8X C
SEATING NNNNNNN
0.10 C PLANE
TPP-AAA
LLLLL
1.75 MAX
0.51
0.31 0.25 1
0.10
1.27 BSC
B Standard Branding Reference View
For Reference Only; not for tooling use (reference MS-012AA) N = Device part number
Dimensions in millimeters T = Device temperature range
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions P = Package Designator
Exact case and lead configuration at supplier discretion within limits shown A = Amperage
L = Lot number
A Terminal #1 mark area Belly Brand = Country of Origin
B Branding scale and appearance at supplier discretion
C Reference land pattern layout (reference IPC7351
D SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances
17
955 Perimeter Road
Revision History
Number Date Description
9 November 16, 2012 Update product selection, rise time, isolation, patents
10 June 5, 2017 Updated product status
11 December 10, 2018 Updated certificate numbers
12 May 17, 2019 Updated TUV certificate mark and minor editorial updates
The products described herein are protected by U.S. patents: 5,621,319; 7,598,601; and 7,709,754.
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

18
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ACS714 Datasheet PDF

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ACS714

Automotive Grade, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC

Not for New Design

Date of status change: June 5, 2017

NOTE: For detailed information on purchasing options, contact your

Features and Benefits Description

Continued on the next page…

Application 1. The ACS714 outputs an analog signal, VOUT .

ACS714-DS, Rev. 12 May 17, 2019

Absolute Maximum Ratings

Functional Block Diagram

IP+ Sense Temperature

Terminal List Table

COMMON THERMAL CHARACTERISTICS1

10.05 VCC = 5 V 10.5

Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

Output Voltage versus Sensed Current Sensitivity versus Sensed Current

2.5 160.00 TA (°C)

Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

3.0 102.00 150

2.5 TA (°C) 100.00

Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

Output Voltage versus Sensed Current Sensitivity versus Sensed Current

3.5 VCC = 5 V 67.00

Magnetic Offset versus Ambient Temperature Nonlinearity versus Ambient Temperature

Output Voltage versus Sensed Current Sensitivity versus Sensed Current

3.5 VCC = 5 V 42.00 –40

Definitions of Accuracy Characteristics

 VIOUT(Q) – VIOUT_–full-scale amperes 

Quiescent output voltage (VIOUT(Q)). The output of the device

it nominally remains at VCC ⁄ 2. Thus, VCC = 5 V translates into Accuracy

resolution of the Allegro linear IC quiescent voltage trim and Accuracy

Accuracy (ETOT). The accuracy represents the maximum devia-

the output voltage versus current chart at right. Accuracy

Definitions of Dynamic Response Characteristics

Power-On Time (tPO). When the supply is ramped to its operat-

losses observed in the conductive IC ground plane. 0

Power on Time versus External Filter Capacitance Step Response

Expanded in chart at right 4.7 17.5 100

Chopper Stabilization Technique

Modulation is used to separate the undesired DC offset signal

Application 3. This configuration increases gain to 610 mV/A

Improving Sensing System Accuracy Using the FILTER Pin

Pin 3 Pin 4 VCC

as given by the transfer function for ∆VATT. RF

Amp Out N.C. Application

Low Pass Filter

IP+ IP+ GND

Package LC, 8-pin SOIC

3.90 ±0.10 6.00 ±0.20 5.60

0.25 BSC C PCB Layout Reference View

B Standard Branding Reference View

For the latest version of this document, visit our website:

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