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Microprocessor 8085

Features, Architecture, Instruction set and Basic Programs


Features
 Intel Second generation, 40 pin, Dual inline package, Single power supply +5V
 Clock frequency 2-5 MHz with 50% duty cycle, comes with Internal oscillator
 8 bit microprocessor: Thus can handle unsigned data of 0-255D, or a signed
data of -128D to +127D
 16 bit address bus: Thus can handle a memory capacity of 64 MB
 Arithmetic and logical unit:
 Performs arithmetic and logical operations
 Operands are obtained from TR and A
 Affects the status flags according to the result and instruction executed
ALU
 Arithmetic operations supported:
 Addition and subtraction of Binary numbers
 Special addition of 16 bit numbers
 Only addition of BCD numbers via adjuster instructions
 Increment and decrement of 8/16 bit binary numbers
 Comparison of two 8 bit binary numbers
 Logical operations supported:
 AND, OR, NOT (Complementing), EXOR, Clear
 Shift operations: rotate 8 bit numbers left/right with/without carry
ARCHITECTURE BLOCK DIAGRAM
Registers of 8085
 Accumulator (A): For Arithmetic and Logical operations one operand comes from A
and result of operation is stored in A again. Most of the 8085 instructions access
Accumulator
 Temporary registers (TR, W, Z): Not accessible by the programmer. Read or written
by microprocessor for internal operations for holding temporary operands or data,
for example immediate data or direct addresses.
 General purpose registers (B, C, D, E, H, L): 8 bits individual and 16 bit when in
pairs (BC, DE, HL register pairs). HL pair acts like a 16 bit accumulator.
 Flag register: 8 bit register of which 5 flip-flops are affected after arithmetic and
logical operations carried out by ALU.

 Special purpose registers: SP and PC


Flag register
 This is an 8 bit register. Thus it can store 8 bit data. However 5 out of 8 bits are
used as status flags. The status flags are updated as per the status of the results
obtained after arithmetic or logical operation.
 The status of result reflected in the form of status flags are checked by the
decision codes (Branching instructions) during their execution.
 Flags:
 CY (Carry flag):
 When microprocessor performs addition of 8/16 bit numbers, the result obtained will be 9/17
bits wide. The most significant bit of the result; the carry bit is directly copied into the carry
flag
 When microprocessor performs subtraction of 8 bit numbers, the result obtained will be 9 bits
wide. The most significant bit of the result; the borrow bit is directly copied into the carry
flag. Example: X-Y  CF=1 if X < Y and CF=0 if X > Y
 AC (Auxiliary Carry flag):
 In case of addition (or subtraction) of two 8 bit numbers, the carry-to (or borrow-from) bit D4
from (to) D3 of the result is copied into AC
 Internally checked by the microprocessor during the execution of decimal adjust after
addition (DAA) instruction
Flag register
 Flags:
 P (Parity flag):
 If count of number if 1’s in 8 LSB of result is EVEN, then PF is made 1 by the processor. Thus 8085
follows even parity scheme.
 If count of number if 1’s in 8 LSB of result is odd, then PF is made 0 by the processor.
 This flag is used to check the parity of result.
 Useful during serial transmission applications.
 Z (Zero flag):
 If the ALU in microprocessor performs arithmetic and logical operation and all the bits of result is
ZERO, then Z flag is set to 1, else it is set to 0
 S (Sign Flag)
 This flag indicates the sign of the result after arithmetic and logical operations using signed
operands.
 The MSB of the result is directly copied into S flag.
 Microprocessor will not know whether the data is signed or unsigned it will blindly copy the status of
MSB of the result into sign flag
 The real concept of sign and sign flag will be valid only when signed numbers are used.
 For signed numbers, status of CY flag bit is ignored and only the status of S flag bit is considered for
correct interpretation of result
 For unsigned numbers, status of S flag bit is ignored and only the status of CY flag bit is considered
for correct interpretation of result.
Example:
 75H+8CH (unsigned operands) (117D and 140D)
 0111 0101
 1000 1100
 Result: 01H
 AC=1, CY=1, Z=0, P=0, S=0
 75H+8CH (signed operands) (+117D and -116D)
 0111 0101
 1000 1100
 Result: 01H (+1D)
 AC=1, CY=1, Z=0, P=0, S=0
 Add -127D and -3D
 Cin not equal to Cout -> Overflow in 8085
PIN CONFIGURATION
Pins of 8085
1. Address Data Pins (AD7-AD0)
2. Higher Order Address pins (A15-A8)
3. Memory Control signal Pins (𝑅𝐷, 𝑊𝑅, 𝐴𝐿𝐸, 𝐼𝑂/𝑀, READY)
4. Interrupt Signal Pins (TRAP, RST5.5, RST6.5, RST7.5, INTR, 𝐼𝑁𝑇𝐴)
5. Reset Control Signal Pins (𝑅𝐸𝑆𝐸𝑇𝐼𝑁, 𝑅𝐸𝑆𝑇𝑂𝑈𝑇)
6. DMA control signal pins (HOLD, HLDA)
7. Status Signals (S1, S0)
8. Serial Data Pins (SID, SOD)
9. Crystal Connection and Clock (X1, X2, CLK)
10. Power Pins (Vcc, Vss/Ground)
Timing of data flow when instruction code 4FH (MOV C,A)
stored in memory location 2005H is being fetched
ALE: ADDRESS LATCH ENABLE
Address/Data de-multiplexing
Instruction set of 8085
Data Flow

Instructions
 Binary Codes Microprocessor Processed
 Hexadecimal Programs
(Data Processor) Data
Codes
 Mneumonics
 Low Level
Language/Machine
Language
 Hexadecimal Code
language
 Assembly Language Input Data
 High Level Language • Memory
• IO Device
Assembler

Assembly Language
Machine Language
program ASSEMBLER
Program (memory)
Instructions
LABEL: OPERANDS (If ; Comments
MNEUMONIC
required) (Optional)

Examples:

MVI C, 05H
LXI D, 2005H
Continue: LDAX D
ADD B; Adds eight bit data of accumulator A and register B and stores result in register A
JC BypInstr
INR B
BypInstr: INX D
DCR C
JNZ Continue
OUT 80H (STA 8000H)
MOV A, B
OUT 81H (STA 8001H)
RST1/HLT
PROGRAM MEMORY
Instruction codes CONTENTS
Address Codes
8000 21
PROGRAM
ASSEMBLED 8001 00
MEMORY MENUMONICS
CODES 8002 40
ADDRESS
8003 0E
8000 LXI H 4000h 21,00,40 8004 04
8003 MVI C 04 0E, 04 8005 06
8005 MVI B 00 06, 00 8006 00
8007 3E
8007 MVI A 00 3E, 00 8008 00
8009 VERTADD: ADD M 86 8009 86
800A JNC SKIPCARRYACCUM D2, 0E, 80
ASSEMBLY 800A D2
800B 0E
800B INR B 04
800C 80
SKIPCARRYACCUM: INX 800D 04
800E 23
H 800E 23
800F DCR C 0D 800F 0D
8010 JNZ VERTADD C2, 09, 80 8010 C2
8011 09
8013 MOV M A 77
8012 80
8014 INX H 23 8013 77
8015 MOV M B 70 8014 23
8016 RST 1 CF 8015 70
8016 CF
Instructions

Function Size Addressing modes

1. Data Transfer 1. One Byte (MOV A, B; MOV 1. Register Direct (MOV A, B)


2. Arithmetic A, M; LDAX H) 2. Immediate (MVI A, 05H; LXI H,
0C78H)
3. Logical 2. Two Byte (MVI A, 05H) 3. Direct (LDA 0905H, STA 0502H)
4. Branching 3. Three Byte (LXI H, 0C78H; 4. Register Indirect (MOV A, M; LDAX
LDA 0905H, STA 0502H) H)
5. Stack 5. Implicit (CMA, RAL, ROR)
6. Machine Control
7. Input Output
Instruction set of 8085
 246 total opcodes and 74 basic instructions
 Data transfer type (Does Not affect flags)
 MOV Dest, Source (MOV A, C; MOV M,C) Dest Source
 MVI Dest, data8 (MVI C, 0C5H, MVI M, 95H)
Register8 Register8
 LXI RP, data16 (LXI H, 0C205H)
Register8 M
 LDA addr16/STA addr16 (LDA 0C205H)
 LDAX RP/STAX RP (LDAX B) M Register8
 XCHG (Interchange HL and DE register pair)
 LHLD addr16 (L<-[addr16], H<-[addr16+1])
 SHLD addr16 (L->[addr16], H->[addr16+1])
Examples
 Exchange 8 bit nos of register pair HL and BC by two different methods
 Transfer 8 bit data in memory address 9000H in Accumulator (by two different
methods)
 Transfer 8 bit data in register C
 Transfer 16 bit data in register pair BC by two different methods
 Transfer 8 bit data of memory location 2500H into register C by 4 different
methods
 Register Indirect Addressing methods (3 nos)
 Direct Addressing mode (1 nos)
Data Exchange Programs
3. INTERCHANGE MEMORY CONTENTS OF 1000H
1. INTERCHANGE REGISTER 2. INTERCHANGE REGISTER CONTENT AND REGISTER PAIR BC
SOLUTION 1:
CONTENT D AND C OF PAIRS BC AND DE LXI B 3035h
LXI H 1000h
MVI A 50h
MVI C 05h SOLUTION 1: MOV M A

MVI D 50h LXI B 0050h INX H


MVI A 05h
MOV A C LXI D 5000h MOV M A

MOV C D MOV A C
LDA 1000h
LXI H 1000h
MOV M C
MOV D A MOV C E MOV C A
MOV E A
RST 1 LDA 1001h
LXI H 1001h
MOV A B MOV M B
MOV B A
MOV B D
MOV D A SOLUTION 2:
RST 1 //USE HL PAIR INTERFACE
1. READ MEMLOCATION DATA IN HL.
2. EXCHANGE HL AND DE
SOLUTION 2: 3. COPY BC RP TO HL
4. COPY DE RP TO BC
5. COPY HL PAIR DATA TO MEMLOC
LXI B 0050h LXI B 1234h
LXI D 5000h
XCHG LXI H 1000h
MVI A 50h
MOV M A
MOV A C
MOV C L INX H
MOV L A MVI A 05h
MOV M A
LHLD 1000
MOV A B XCHG
MOV B H MOV L C
MOV H B
MOV H A
MOV C D
MOV B E
XCHG
SHLD 1000
RST 1
RST 1
Data Exchange Programs
4. Exchange memory contents of 1000H and 1001H 5. INTERCHANGE 16 BIT MEMORY
SOLUTION 1: LOCATIONS AT 1000H AND 2000H
//USE Accumulator to read individual bytes from memory and //USE HL PAIR INTERFACE
write in reverse manner
LXI H 1000h
MVI A 50h //Init values in MLocs
MOV M A LXI H 1000h
INX H MVI A 50h
MVI A 05h MOV M A
MOV M A
MOV A M INX H
MOV C A MVI A 05h
DCX H
MOV A M MOV M A
STA 1001h
MOV A C LXI H 2000h
STA 1000h
RST 1 MVI A 20h
MOV M A
Solution 2:
1. Read 1000H and 1001H in HL Pair INX H
2. Interchange HL pair data MVI A 02h
3. Store the data back
MOV M A
LXI H 1000h
MVI A 50h
MOV M A
LHLD 2000h
INX H XCHG
MVI A 05h LHLD 1000h
MOV M A
SHLD 2000h
LHLD 1000h XCHG
MOV A L SHLD 1000h
MOV L H
MOV H A RST 1
SHLD 1000h
RST 1
Arithmetic Instructions
 Addition (with/without carry), Subtraction (with/without Borrow) (AFAC)
 A=A±S (addition or subtraction without carry/borrow), where S=R8/M8
 A=A±S±CY (addition or subtraction with carry/borrow), where S=R8/M8
 ADD S, ADC S, ADI data8, ACI data8
 SUB S, SBB S, SUI data8, SBI data8
 Double addition (16 bit addition): DAD RP (HL=HL+RP) Only CY is changed
 Increment (8/16 bit), decrement (8/16 bit)
 S=S±1, where S=R8/M8
 INR S, DCR S (AFAC except CY)
 INX RP, DCX RP [NFAC]
 Decimal adjust after addition (only 8 bits): DAA (AFAC)
 Comparison (only 8 bits): CMP S, CPI data8
Logical Instructions
 For logical operations like AND, OR, XOR: CY=0 and ZF, PF, SF will vary according
to result
 AND OPERATION (AC=1)
 ANA S (A=A.S)
 ANI data8 (A=A.data8)
 OR OPERATION (AC=0)
 ORA S
 ORI data8
 XOR OPERATION (AC=0)
 XRA S
 XRI data8
 Other Logical Operations
 CMA, CMC, STC
 RLC, RRC, (Rotate left/right accumulator without carry)
 RAL, RAR (Rotate left/right accumulator with carry)
Stack Instructions FFFB
 Stack is a memory area of 8085 memory model where data is arranged in FFFC
the form of Stack data structure for frequent access.
 Only one entry/exit point FFFD CFH TOS
 LIFO FFFE 84H TOS+1
 TOS: Top of the stack
FFFF 55H TOS+2
 STACK POINTER (SP) Holds the address of the TOP of the Stack (TOS)
 Instructions:
 PUSH RP (SP=SP-1, RPH->[SP], SP=SP-1, RPL->[SP])
FFFD
 POP RP (RPL<-[SP], SP=SP+1, RPH=[SP+1], SP=SP+1)
 SPHL (SP<- HL) SP
 XTHL (Exchange TOS and TOS+1 data with HL Pair)
 LXI SP, data16 (SP<- data16)
 INX SP (SP=SP+1)
 DCX SP (SP=SP-1)
 DAD SP (HL=HL+SP)
Branching Instructions
 Also known as Decision codes
 Updates PC with new address
 Alters the sequential execution pattern and transfers program control to another
address
 Branching can be Conditional or Unconditional
 Instructions:
 JMP addr16
 JZ addr16, JNZ addr16
 JC addr16, JNC addr16
 JPE addr16, JPO addr16
 JM addr16, JP addr16
 CALL addr16
 RET
 RSTn
 PCHL
Machine control Instructions

 Machine control Instructions


 No Addressing modes
 SIM, RIM
 NOP
 HLT
 Input output Instructions
 IN IOaddr8
 OUT IOaddr8
Exercises
 Exchange/Interchange the 16 bit data of two memory locations
 Add two 32 bit numbers in memory from 6000H and 7000H. Store the result
from 8000H
 Add 10 bytes present from memory location; 1000H and store the result in
7000H and 7001H.
Solutions 1: Exchange/Interchange the
16 bit data of two memory locations
LHLD 3000H
XCHG
LHLD 4000H
SHLD 3000H
XCHG
SHLD 4000H
Solution- 2: Add two 32 bit numbers in memory from 6000H
and 7000H. Store the result from 8000H
LXI H, 6000H LDAX D
LXI D, 7000H ADC M
LXI B, 8000H STAX D
INX H
LDAX D INX D
ADDM INX B
STAX D
INX H LDAX D
INX D ADC M
INX B STAX D
INX H
LDAX D INX D
ADC M INX B
STAX D
INX H INX B
INX D MVI A, 00H
INX B ADC A
STAX B; Stored final carry into memory location 8004H
RST1/HLT
Solution-3: Add 5 bytes present from memory
location; 1000H and store the result in 7000H and
7001H. LXI H, 1000h

MVI C, 05h

MVI B, 00H

MVI A, 00H
VERTADD: ADD M

JNC SKIPCARRYACCUM

INR B
SKIPCARRYACCUM: INX H
DCR C

JNZ VERTADD

STA 7000H

MOV A, B

STA 7001H

RST1/HLT

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