Interface states state_idle state_rewe state_ack state_idle

WB clock
Bus Master Cycles and Timing to/
from WB Master Interface

cycle

strobe

address

write data

Acknowledge (Bus)

read data (Bus)

state_idle state_0 state_1 state_2 state_3 state_end state_0 state_1 state_2 state_3 state_end state_idle

WB clock

ADV#

CE#

LB#/UB#

WE#

OE#

Data_O

Data_I

Data_dir
 Interface states state_idle state_rewe state_ack state_idle

WB clock
Bus Master Cycles and Timing to/
from WB Master Interface

cycle

strobe

address
Clocked write times
(red preferred)
write data

Acknowledge (Bus)

state_idle state_0 state_1 state_2 state_3 state_end state_0 state_1 state_2 state_3 State_end state_idle

WB clock

ADV#

CE#

LB#/UB#

WE#

OE#

Data_O

Data_I

Data_dir