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Eee Exp 6
Eee Exp 6
: 4 Date:9/09/2019
Design of Half Adder and Full Adder circuits
Aim:
To design the Half adder circuit and Full adder circuit
Apparatus/Tool required:
ORCAD / PSpice simulator - > 7400 Library – 7408, 7432 & 7486
Source Library - Digclock
Simulation Settings: Analysis Type - Time Domain
Run to time: 4ms (for Half Adder)
Run to time: 8ms (for Full Adder)
Circuit Diagram:
7408
7408
A half adder is a type of adder, an electronic circuit that performs the addition of
numbers. The half adder is able to add two single binary digits and provide the
output plus a carry value.
TRUTH
A BTABLE
C S=ABB C= (AB).C+A.B
0 A 0 B 0S=AB 0C=A.B 0
0 00 0 1 0 0 0 1
0 01 1 0 1 0 0 1
0 1 1 0 1 1 1 0 0
1 10 1 0 0 0 1 1
1 0 1 1 0
1 1 0 1 0
Model Timing Diagram:
1 – Adder:
Half 1 1 1 1
Full – Adder
RESULT:
Hence the half adder circuit and full adder circuit is drawn and its graph is shown
above.
Reg. No: 19BCE2145 Name: NUPOOR RAJ Date: 9/09/19