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    Diego Bersabal
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    This document describes Laboratory Activity No. 3 on implementing a CMOS NAND gate. It includes the equation, truth table, schematic, netlist, and output graph of a CMOS NAND gate. The equation is F = AB. The truth table shows the output is 1 when inputs A and B are both 0 or when one input is 1 and the other is 0, and the output is 0 when both inputs are 1. The schematic shows the layout of the NAND gate with NMOS and PMOS transistors. The netlist provides further details of the transistor nodes and voltages. The output graph plots the output voltage over time during a transient analysis simulation.

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    VLSI

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    Laboratory 3 Nand

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    This document describes Laboratory Activity No. 3 on implementing a CMOS NAND gate. It includes the equation, truth table, schematic, netlist, and output graph of a CMOS NAND gate. The equation is F = AB. The truth table shows the output is 1 when inputs A and B are both 0 or when one input is 1 and the other is 0, and the output is 0 when both inputs are 1. The schematic shows the layout of the NAND gate with NMOS and PMOS transistors. The netlist provides further details of the transistor nodes and voltages. The output graph plots the output voltage over time during a transient analysis simulation.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    1 views2 pages

    Cavite State University: Republic of The Philippines

    Uploaded by

    Diego Bersabal
    This document describes Laboratory Activity No. 3 on implementing a CMOS NAND gate. It includes the equation, truth table, schematic, netlist, and output graph of a CMOS NAND gate. The equation is F = AB. The truth table shows the output is 1 when inputs A and B are both 0 or when one input is 1 and the other is 0, and the output is 0 when both inputs are 1. The schematic shows the layout of the NAND gate with NMOS and PMOS transistors. The netlist provides further details of the transistor nodes and voltages. The output graph plots the output voltage over time during a transient analysis simulation.

    Copyright:

    © All Rights Reserved
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    of 2

    Republic of the Philippines

    CAVITE STATE UNIVERSITY


    Don Severino de las Alas Campus
    Indang, Cavite
     (046) 415-0010 / (046) 415-0021
    www.cvsu.edu.ph

    Laboratory Activity No. 3


    CMOS NAND Implementation

    EQUATION

    F = AB

    TRUTH TABLE

    A B F
    0 0 1
    0 1 1
    1 0 1
    1 1 0

    SCHEMATIC

    Engr. Rose Ann E.


    Bersabal, Diego Rafael Laboratory Activity No. 3 1
    Sumadsad
    L. 00 00
    CMOS NAND
    201411305 / BSECE 5-2 September 17, 2019 2
    Implementation
    NETLIST

    *** TOP LEVEL FACET: nand{sch}


    ** GROUND NET: 0 (net1)
    Cnode3 0 4 100F
    Mnode10 7 5 0 0 N L=2.00U W=2.00U
    Mnode11 4 6 7 0 N L=2.00U W=2.00U
    Mnode12 3 5 4 3 P L=2.00U W=2.00U
    Mnode13 3 6 4 3 P L=2.00U W=2.00U
    ** Sources and special nodes:
    Vnode6 5 0 pulse 0 3 0 1n 1n 100n 200n
    Vnode7 6 0 pulse 0 3 0 1n 1n 50n 100n
    Vnode9 3 0 3
    .PRINT TRAN V(4)-5 V(5)+5 V(6)
    .TRAN 1p 200n 1n 1n
    .END

    OUTPUT GRAPH

    Engr. Rose Ann E.


    Bersabal, Diego Rafael Laboratory Activity No. 2
    3 Sumadsad
    L. 00 00
    CMOS NAND
    201411305 / BSECE 5-2 September 17, 2019 2
    Implementation

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