Nnew - DC Lab Manual

TIME DIVISION MULTIPLEXING EXPT.
NO : 1
DATE :
1. AIM:
To perform 4-Channel analog multiplexing and De-multiplexing
2. COMPONENTS & TOOLS REQUIRED:
 TDM Trainer kit

 30 KHz dual channel oscilloscope
 CRO probes and patch chords.
3. THEORY:
TDM is used for transmitting several analog message signals over a

communication channel by dividing time frame in to number of slots. Each slot is
assigned for different signal channel where each message signal must be band
limited signal, N no of message signals are applied to Multiplexer through a pre-
aliasing filter, then all signals are sampled sequentially. The output will be a PAM
wave form containing samples of the input signals periodically interlaced in time the
sample from adjacent input channel are separated by t s/N where ts is a sampling
time and N is number of channel applied to Multiplexer. A set of N samples from
each of N input samples is called Frame. The transmitter and receiver must be
synchronized. The receiver distributes the all samples over n- root output channels
and filter to produce the original channel information. A two level synchronization is
used in TDM. Frame synchronization is necessary to establish when group of
sample begin and word synchronization necessary to separate the sample with in a
frame. TDM is immune to amplitude non-linearities in channel as source of cross talk
for all the different message signals are not simultaneously impressed in the
channel.
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4. BLOCK DIAGRAM:
Function Transmitter Receiver TDM

L.P.F Out
Timing Logic Timing Logic Put
Generator
5. EXPERIMENTAL PROCEDURE:
1. Switch on the power supply.
2. Set the duty cycle switch in position 5 in transmitter timing logic block.
3. Set the amplitudes of each modulating signal to convenient value.
4. Make the following connections from function block to transmitter block with 4 mm
banana connectors
i. 250Hz to channel 0 (TP11)
ii. 500Hz to channel 1 (TP13)
iii. 1 kHz to channel 3 (TP15)
iv. 2 kHz to channel 4 (TP17).
5. Varying the amplitude of the input signals corresponding each channel by using
amplitude potentiometers and observe the TDM output (TP20)
6. Connect output (TP20) to Rx input (TP39).
7. Connect TX clock to RX clock and Tx ch0 to Rx ch-0, then observe the
extracted modulating (De-multiplexed signals) signals before and after low pass
filters (TP 42, 44, 46, 48)
8. Observe by varying the duty cycle pot and see the effect on the outputs
6. PRECAUTIONS:
1. Check for loose contacts of wires and components.
2. Keep all the control knobs in the minimum position.
3. Before switch on the power supply get the circuit connections verified by the
teacher.
4. Adjust the control knobs smoothly.
5. After taking the readings bring back all the control knobs to minimum position.
6. Switch off the power supply before leaving the experimental table.
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7. OBSERVATIONS:
1. CH0 Modulating frequency : ----------------

4. Modulating frequency : ----------------
5. CH0 De-Modulating frequency : ----------------
9. Time interval between any two successive samples----------------
8. RESULT:
The 4-channel analog multiplexing and de-multiplexing techniques is done

and verified, the effect of sampling frequency variation and the amplitude variation
on the output is observed.
9. VIVA -VOCE QUESTIONS:
1. What is the working principle of TDM?

2. What is the purpose of commutator in TDM?
3. In TDM how does the synchronization can be achieved?
4. What are the applications of TDM?
5. What is aperture effect?
LBRCE, ECE 3
PULSE CODE MODULATION EXPT. NO : 2
DATE :
1. AIM:
To perform Pulse Code modulation and Demodulation
.
 PCM modulator and De-modulator kit

 Dual channel CRO (30 MHz),
 Patch chords.
3. THEORY:
In PCM a message signal is represented by a sequence of coded pulse which is

accomplished by representing in both time and amplitude. Mainly it consists of sampling
quantization and encoder.
Sampling: For perfect reconstruction of message signal at receiver, the sampling
rate must be greater than twice the highest frequency component 'w' as per sampling
theorem. The pre- aliasing filter is used at the front of the sampler to excuse the frequency
greater than 'w'.
Quantization: By quantization signal is discrete both time and amplitude. In uniform
quantization the represented levels are uniformly spaced and non uniform quantization step
size increases as separation from origin of i/p amplitude characteristics is increased. The
non uniform quantizer is equivalent to pass base band signal through a compressor and
then uniform quantizer.
Encoder: The discrete set of sampler values are represented in to a set of single values of
discrete set is called code word.
Decoder: The clear pulses are regenerated to code word and decoded in to a quantized
PAM in decoding process a pulse generator whose amplitude is linear sum of all pulses.
Filter : The message signal can be reconstructed by passing the decoder output through
a constructed filter LPF having the cut off frequency equal to twice message band width.
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4. BLOCK DIAGRAM:
Quantized PCM
Sampled Signal Output
Modulator Signal
S
A
M
Modulating Quantizer Encoder
L.P.F. P
Signal
L
E
R
De - Modulator
L
PCM P Demodulated
Input Decoder D/A Converter F Signal
Decoded Analog
Signal
Equivalen
t Signal
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1. Keep mode switch in fast position.

2. Rotate DC1 & DC2 Controls in function generator block set to convenient value.
3. Set 1 KHz & 2 KHz controls to 10V, and pseudo random sync code generator
switched to OFF position.
4. Error check code generator switch A & B must be in OFF mode.
5. All switched faults OFF and turn on power. Check that PAM O/P of 1 KHz sine
wave available at TP 15.
6. Make the following connections with help of patch chords
(i) PCM output tp1 (PCM TX kit) to data input (PCM Demodulator kit) and
Tx clock output (PCM TX kit) to RX clock input (PCM Demodulator kit).
(ii) Connect DC2 to transmitter input Ch-I as well as Ch-II.
7. Observe the outputs at encoded signal (PCM) by varying input signal amplitude
and demodulated output which is exact replica of applied input signal.
8. Repeat the above procedure for 1KHz signal also
9. Note the observations
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6. PRECAUTIONS:
teacher.
7. OBSERVATIONS:
1. Amplitude of modulating signal :_______________

2. Frequency of modulating signal :_______________
3. PCM output data :________________
4. Amplitude of demodulating signal :_____________
5. Frequency of demodulating signal :______________
8. RESULT:
The pulse code modulation and demodulation is performed
1. Define PCM?
2. Give the expression for figure of merit a PCM system?
3. What are the applications of PCM?
4. What is quantization?
5. What is the use of Decoder?
LBRCE, ECE 7
DIFFERENTIAL PULSE CODE MODULATION EXPT. NO : 3
AND DEMODULATION DATE :
1. AIM:
To study the differential pulse code modulation and demodulation by sending
variable frequency sine and variable D.C signal.

 Differential pulse code modulation &demodulation trainer kit.
 30 MHz Dual channel C.R.O.
 4 mm patch cords.
3. THEORY:
In a typical PCM- encoded speech waveform, there are often successive samples
taken in which there is little difference between the amplitude of the two samples. This
necessitates transmitting several identical PCM codes, which is redundant. Differential
pulse code modulation (DPCM) is designed specifically to take advantage of sample to
sample redundancy in typical speech waveforms. With DPCM, the difference in amplitude
of two successive samples is transmitted rather than the actual sample. Since the range of
sample differences is typically less than the range of individual samples, fewer bits are
required for DPCM than conventional PCM.
Shown below is a block diagram of transmitter.
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4. CIRCUIT DIAGRAM:
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5. EXPERIMENT PROCEDURE:
1. Switch on the power supply of experimental kit.
2. Apply the variable D.C. signal to the input terminals of DPCM demodulator.
3. Observe the sampling signal output on the channel of a CRO.
4. Observe the output of DPCM on the second channel of CRO.
5. By adjusting the D.C. voltage potentiometer, we can get the DPCM output from
00000000 to 11111111.
6. Now, disconnect the D.C. voltage and apply AF oscillator output to the input of DPCM
modulator.
7. Observe the output of conditioning amplifier (differential output) and DPCM outputs in
synchronizing with the sampling signal.
8. During the demodulation, connect DPCM output the input of the demodulation and
observe the output of the DPCM demodulator.
6. MODEL WAVEFORMS:
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7. OBSERVATIONS:
1. Amplitude of modulating signal : _______________

2. Frequency of modulating signal : _______________
3. PCM output data : ________________
4. Amplitude of demodulating signal : _____________
5. Frequency of demodulating signal : ______________
8. RESULT:
The differential pulse code modulation and demodulation is performed
1. Define DPCM?
2. What are the advantages of DPCM compared to PCM?
3. What is the transmission bandwidth of DPCM?
4. What is the use of predictor in DPCM?
LBRCE, ECE 11
DELTA MODULATION EXPT. NO : 4(A)
DATE :
1. AIM: To perform Delta modulation and observe the waveforms
2. COMPONENTS AND TOOLS REQUIRED:

 Delta modulation and demodulation trainer kit – Scientech2803
 Power Supply
 Oscilloscope/DSO
 Test probe
3. Theory:
Delta modulator technique has evolved a simple, efficient method for digitizing input
signal for secure, reliable communications and for voice input- output in data processing.
Delta modulator (DM or Δ-modulation) is an analog-to-digital and digital-to- analog signal
conversion technique used for transmission of voice information where quality is not of
primary importance. DM is the simplest form of differential pulse-code modulation (DPCM)
where the difference between successive samples is encoded into n-bit data streams. In
delta modulation, the transmitted data is reduced to a 1-bit data stream.
Working of Delta Modulator:
The modulator is a sampled data system employing a feedback loop. A comparator senses
whether or not the instantaneous level of the analog input is greater or less than the
feedback signal. The comparator output is clocked by a flip-flop to form a continuous NRZ
digital data stream. This digital data is also integrated and feed back to the comparator. The
feedback system is such that the integrator ramps up and down to produce a rough
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approximation of the input waveform. An identical integrator in the demodulator produces
the same waveform. One can see that the digital data 0’s and 1’s are command to the
integrators to “go up” or “go down” respectively.
Delta Modulation is strange in the fact that it attempts to represent an analog signal with a
resolution of 1 bit. This is accomplished by successive steps, either up or down, by a preset
step size. In delta modulation, we have the step size (Δ) that is defined for each sampler,
and we have the following rules for output:
If the input signal is higher then the current reference signal, increase the reference by
Δ, and output a 1.
If the input signal is lower then the current reference signal, decrease the reference by
Δ, and output a 0.
4. CONNECTION DIAGRAM:
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4. PROCEDURE:
Step1 : Connect and switch on the Power Supply of Scientech2803.

Step2 : Select either internal mode or external mode for source signal using switch at
Signal Generator.
Step 2.1: Select input signal type using push button i.e. Sine, square, Triangle, Arbitrary1
and Arbitrary2. And respective LED will glow. Observe the input signal on test
point (TP1).
Step 2.2: Select input signal frequency using push button i.e. 500Hz, 1 KHz, 1.5 KHz, 2
KHz and 3KHz. Observe the change in frequency on test point (TP1).
Step3 : Delta Modulator is by default condition when switch on the Power Supply of ST
2803 and LED of TP2 will glow.
Step4 : Select Sampling Frequency to observe effects of different sampling frequency
on output.
Step5: Select Gain Control to observe effects of different step size on integrator output.
* Note: Press reset button when make any change
5. OBSERVATIONS:
 Observe the input signal at TP1 by varying input signal type and frequency on the
oscilloscope screen.
 Observe the same input signal atTP2.
 Observe the sampled clock at TP3 and sampled signal at TP4 by varying sampling
frequency through pushbutton.
 Observe the integrator output at TP5 by varying step size using gain control
pushbutton.
 Observe the PCM output at TP6, Which will vary with respect to Signal Frequency
and Sampling Frequency.
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6. PRECAUTIONS:
 Check for loose contacts of wires and components.
 Keep all the control knobs in the minimum position.
 Before switch on the power supply get the circuit connections verified by the teacher.
 Adjust the control knobs smoothly.
 After taking the readings bring back all the control knobs to minimum position.
 Switch off the power supply before leaving the experimental table.
7. RESULT:
Thus the Delta modulation is performed and graphs were plotted.
8. VIVA QUESTIONS:
1. Compare DPCM, PCM & Delta modulation.
2. How to reduce the quantization noise that occurs in DM?
3. Mention the applications of DM.
4. What are the drawbacks of the delta modulation?
LBRCE, ECE 16
DELTA DEMODULATION EXPT. NO : 4(B)
DATE :
1. AIM: To perform Delta Demodulation and observe the waveforms.

 Delta modulation and demodulation trainer kit – Scientech2803
 Power Supply
 Test probe
3. THEORY:
Delta Demodulator:
Delta demodulator is a simple integrator and as the logic 1s and 0s are received, the up-
down counter is incremented or decremented accordingly.
Advantages:
Some benefits of delta modulation are as follows:
Delta modulator transmits single bit data (i.e.PCM).
No preset upper or lower bounds, So Delta modulation can (theoretically) be used to
modulate unbounded signals.
These benefits are countered by the problems of Slope Overload, and Granular Noise,
which play an important role when designing a Delta Modulated system.
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4. PROCEDURE:
Step2 : Select either internal mode or external mode for source signal using switch
at Signal Generator.
Step 2.1: Select input signal type using push button i.e. Sine, square, Triangle,
Arbitrary1 and Arbitrary2. And respective LED will glow. Observe the input
signal on test point (TP1).
Step 2.2: Select input signal frequency using push button i.e. 500Hz, 1 KHz, 1.5
KHz, 2KHz and 3 KHz. Observe the change in frequency on test
point(TP1).
Step3 : Delta Modulator is by default condition when switch on the Power Supply of
ST 2803 and LED of TP2 will glow.
Step4 : Select Sampling Frequency to observe effects of different sampling
frequency on output.
Step5 : Select Gain Control to observe effects of different step size on integrator
output.
Step6 : Select Channel using pushbutton.
5. OBSERVATION:
oscilloscope screen.
 Observe the sampled clock at TP3 and sampled signal at TP4 by varying sampling
frequency through pushbutton.
 Observe the integrator output at TP5 by varying step size using gain control
pushbutton.
 Observe the PCM output at TP6, That will vary with respect to signal Frequency and
Sampling Frequency.
 Observe the slope overloading and granular noise by comparing the signal of TP2
andTP5.
 Observe the output of different channel output with respective Test Points.
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6. PRECAUTIONS:
7. RESULT:
Thus the Delta demodulation is performed and graphs were plotted.
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ADAPTIVE DELTA MODULATION EXPT. NO : 5(A)
DATE :
1. AIM: To perform Adaptive Delta modulation and observe output waveforms.

 Adaptive delta modulation and demodulation trainer kit – Scientech2803

 Power Supply
 Test probe
3. THEORY:
Introduction:
Adaptive delta modulator technique has evolved a simple, efficient method for digitizing
input signal for secure, reliable communications and for voice input- output in data
processing. Delta modulation is an important modulation technique employed for data
communication. Since slope overload error is a big problem in delta modulation, adaptive
delta modulation became more important.
Adaptive Delta Modulator:
A simple block diagram of the ADM is shown in Fig. The accumulator generates a data
based on the past ADM pulses transmitted, which would always try to approach the given
analog signal. The sampled form of the analog signal and the analog equivalent of the
LBRCE, ECE 23
accumulator are compared in an analog comparator C and the present ADM pulses are
produced. The step generator produces the new step at every clock. The proposed
algorithm for generating the step size can be stated as follows. When the accumulated
signal doesn’t cross the analog signal in the comparator, the step size is doubled so that it
would catch the input analog signal quickly and when once it crosses it, the step size is
made as half the previous step and not made unity step. If there is another crossover by the
next clock the step again reduces to half of the previous value. Nevertheless, the minimum
step size that can be reached is kept as unity. If the accumulated signal is continuously
above( or below) the given analog input signal the step size doubles every time and it is
made as half of the previous step after reaching three consecutive increase in step size and
thereafter the step doubling process would continue.
LBRCE, ECE 24
5. PROCEDURE:
Step2 : Select either internal mode or external mode for source signal using switch at
Signal Generator.
point (TP1).
KHz and 3 KHz. observe the change in frequency on test point (TP1).
Step3 : Select Adaptive Delta Modulation using push button and LED of TP19 will glow
Step4 : Select Sampling Frequency to observe effects of different sampling frequency on
output.
Note: Press reset button when make any change
6. OBSERVATIONS:
Oscilloscope screen.
 Observe the sampled clock at TP20 and sampled signal at TP21 by varying
sampling frequency through pushbutton.
 Observe the step register output at TP23 andTP26.
 Observe the accumulator output at TP22 and TP27.
 Observe the PCM output at TP24 that will transmit one bit for any type of signal.
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7. PRECAUTIONS:
8. RESULT
Thus the Adaptive Delta modulation is performed and waveforms are observed.
VIVA QUESTIONS:
1. What is Adaptive Delta modulation and what are the advantages?
2. Distinguish between DM and ADM.
3. How slope overload distortion is reduced in ADM?
LBRCE, ECE 27
ADAPTIVE DELTA DEMODULATION EXPT. NO : 5(B)
DATE :
1. AIM:
Study and analysis of the Adaptive Delta Demodulator output
 Adaptive delta modulation and demodulation trainer kit – Scientech2803

 Power Supply
 Test probe
3. THEORY:
Adaptive Delta Demodulator:
The ADM demodulator has somewhat similar function as modulator. The receiver also
follows the same algorithm as that of the transmitter and the accumulator at the receiver at
any time would build the same pattern of signal generated by the accumulator of the
transmitter. The received ADM pulses are given to the SP register and used as the
instantaneous command for the ADD/SUB input of the 8AS. If this is of logic ‘1’ it adds up
the STR register to the accumulator (AC) otherwise it would subtract it from the AC.
Advantages:
Some benefits of Adaptive delta modulation are as follows:
Adaptive delta modulator transmits single bit data (i.e.PCM).
It overcomes the problem of slope overload distortion occurred in delta modulation by
generating variable step size.
LBRCE, ECE 28
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5. PROCEDURE:
Step 1: Connect and switch on the Power Supply of Scientech 2803.
Step 2: Select either internal mode or external mode for source signal using switch at
Signal Generator.
If External Mode is selected: Onboard signal type and signal frequency will be
Deactivated
If Internal Mode is selected:
point (TP1).
KHz and 3 KHz. Observe the change in frequency on test point(TP1).
Step 3: Select Adaptive Delta Modulation using push button and LED of TP19 will glow
Step 4: Select Sampling Frequency to observe effects of different sampling frequency
On output.
Step 5: Channel selection through push button.
6. OBSERVATIONS:
Oscilloscope screen.
 Observe the sampled clock at TP20 and sampled signal at TP21 by varying
sampling frequency through pushbutton.
 Observe the step register output at TP23 andTP26.
 Observe the accumulator output at TP22 and TP27.
LBRCE, ECE 30
 Observe the PCM output at TP24 that will transmit one bit for any type of signal.
 Observe the output of different channel output with respective Test Points.
 Observe the output of Adaptive Delta Demodulator at TP27 changing different

parameters using push button
Input Signal Input Signal Sampling Demodulated output

Frequency type Frequency
500 Hz Sine 16 KHz
CH1: CDR Output (TP16),

CH2: Demodulated Output (TP27)
500 Hz Sine 64 KHz
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7. PRECAUTIONS:
 Before switch on the power supply get the circuit connections verified by the
teacher.
8. RESULT
Thus the Adaptive Delta demodulation is performed and graphs were plotted.
VIVA QUESTIONS:
1. What is Adaptive Delta modulation and what are the advantages?
2. Distinguish between DM and ADM in terms of demodulation process.
LBRCE, ECE 33
AMPLITUDE SHIFT KEYING MODULATION EXPT. NO : 6(A)
DATE :
1. AIM: Study and analysis of ASK modulator.

 ASK modulation and demodulation trainer kit- Scientech2807
 Power Supply
 Test probe
3. THEORY:
Introduction:
Amplitude-Shift Keying (ASK) or On-Off Keying (OOK) is a form of modulation that
represents digital data as variations in the amplitude of a carrier wave. The amplitude of
an analog carrier signal varies in accordance with the bit stream (modulating signal),
keeping frequency and phase constant.
ASK Modulator:
In ASK Modulator level of amplitude can be used to represent binary logic 0s and 1s. We
can think of a carrier signal as an ON or OFF switch. In the modulated signal, logic 0 is
represented by the absence of a carrier, thus giving OFF/ON keying operation and
hence the name given. Mathematically ASK is given by
LBRCE, ECE 34
In the above equation, the modulating signal ( m(t)) is a normalized binary waveform,
where
+1V = logic 1 and -1V = logic 0. Therefore , for logic 1 equation reduces to
for logic0 equation reduces to
Thus the modulated wave vask(t) is either
[A cos (wct)] or 0. As shown in the waveform diagram below down,
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4. PROCEDURE:
Step 2 : Select input Data pattern using push button i.e. 8-Bit, 16-Bit, 32-Bit, 64- Bit.
And respective LED will glow. Observe the input Data on test point (TP2).
Step3 : Select input data clock using push button i.e. 2 KHz, 4 KHz, 8 KHz, 16 KHz.
Observe the change in frequency on test point (TP1).
Step4 : Observe the change in frequency of carrier signal at (TP4).
Step5 : ASK Modulator is by default selection when switch on the Power Supply of
Scientech 2807 and LED of (TP3) will glow.
Step6 : Observe the ASK modulator output on (TP5).
5. OBSERVATIONS:
 Observe the Input Data at TP2.
 Observe the Input data clock atTP1
 Observe the encoded data input atTP3.
 Observe the Carrier signal at TP4.
 Observe the Modulated output atTP5.
 Observe the following data Patterns on TP2

8-Bit: “10110010”
16-Bit: “0100110110110010 ”
32-Bit: “00000101000101111100101000111111 ”
64-Bit:
1010110011100011110000111110000011110000111000110010101000111010”
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6. PRECAUTIONS:
teacher.
7. RESULT
Thus the ASK Modulation is performed and graphs were plotted.
VIVA QUESTIONS:
1. Write the mathematical expression for ASK
2. What is meant by coherent ASK?
3. Draw the constellation diagram for ASK and mention its bandwidth?
LBRCE, ECE 39
AMPLITUDE SHIFT KEYING EXPT. NO : 6(B)
DEMODULATION DATE :
1. AIM: Study and analysis of ASK Demodulator

 ASK modulation and demodulation trainer kit- Scientech2807
 Power Supply
 Test probe
3. THEORY:
ASK Demodulator:
At receiver side ASK modulated signal is multiplied by the carrier signal which is
generated from the carrier generator the output of multiplier consist of higher frequency
and lower frequency components this output then integrated by Integrator block and
passed by comparator block . Comparator block recovers digital data by comparing
threshold value with integrated signal.
Advantages:
Amplitude-shift keying is used extensively for commercial terrestrial
It’s usefulness for satellite applications are limited.
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5. PROCEDURE:
Step 2 :Select input Data pattern using push button i.e. 8-Bit, 16-Bit, 32-Bit, 64- Bit. And
respective LED will glow. Observe the input Data on test point (TP2).
Step4 : Observe the change in frequency of carrier signal at (TP4).
Step5 : ASK Modulator is by default selection when switch on the Power Supply of
Scientech 2807 and LED of (TP3) will glow
6. OBSERVATIONS:
 Observe the Input Data at TP2.
 Observe the Input data clock atTP1.
 Observe the 1-bit encoded input data atTP3.
 Observe the Carrier signal at TP4 andTP6.
 Observe the Modulated output atTP5.
 Observe the multiplier output atTP7
 Observe the Integrator output atTP8
 Observe the output atTP9
 Observe the following data Patterns on TP2 8-Bit: “10110010 ”

16-Bit: “0100110110110010 ”
32-Bit: “00000101000101111100101000111111 ”
64-Bit:
1010110011100011110000111110000011110000111000110010101000111010
Note: If output at any TP’s not appear proper then Press RESET button
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Input Data Data ClockResulting Waveforms
Type Frequency
8-Bit 2KHz
CH1: Input Data (TP2), CH2: Demodulator out

(TP9)
8-Bit 2KHz
CH1: Input Data (TP2), CH2: Demodulator out

(TP9)
Note: If output at any TP’s not appear proper then Press RESET button
LBRCE, ECE 43
7. PRECAUTIONS:
teacher.
8. RESULT
Thus the ASK De-Modulation is performed and waveforms are observed.
9. VIVA QUESTIONS:
1. What is the principle of ASK?
2. What is the use of LPF in coherent detection of ASK?
3. What is another name of ASK?
LBRCE, ECE 44
FREQUENCY SHIFT KEYING EXPT. NO : 7
DATE :
1. AIM:
To generate FSK modulated and demodulated waveforms.

 FSK modulator and De-modulator kit
 CRO (32 MHz), Patch chords.
3. THEORY:
In FSK the modulating signal is a binary pulse stream that varies between two
discrete voltage levels. The modulated signal amplitude is constant (Vc), but the
frequency shift by an amount to +/- ∂/2 is proportional to the amplitude and polarity of
binary signal. For example binary input logic ‘1’ with +1 volt produce + ∂/2 and similarly
logic’0’ produce – ∂/2 phase shift. In binary FSK baud rate is always equal to bit rate.
Thus the carrier deviates between Wc+ ∂/2 and Wc- ∂/2 at the rate equal to fm the
output of FSK modulator logic’0’ corresponds space frequency f s and similarly
logic’1’corresponds mark frequency fm and band width equal to Wm-Ws= ∂
3.1. Data types:

NRZ: This is a level type code and is one that is widely used in serial data transmission.
A ‘0’ is low level and ‘1’ is high level.
RZ: This is an impulse type code where a ‘1’ is represented by a high level that return
to zero, its advantage is power conservation as transmission takes place only for ‘1’.
NRZ (mark): If the logic ‘0’ is to be transmitted the new level is the inverse of the
previous level that is change in level occurs if ‘1’ is transmitted and the level remains
unchanged.
Bi-phage(mark): This is an edge invertible self clocking code in which each of its cell
start with an edge and for ‘0’ an additional edge occurs during the middle of the bit cell.
Bi-Phase (Manchester): This is a level type of a code in which a one cell width cell is
initially high and then has a high to low transmission in the middle of the bit cell.
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CIRCUIT DIAGRAM :
4. BLOCK DIAGRAM:
MODULATOR:
1.44 M Hz
Modulating
Signal MODULATOR
-1
DATA Input
FSK Output
Signal
960 K Hz
Modulating
Signal MODULATOR
-2
Inverted
DATA Input
De – Modulator:
Bit Demodulated
FSK Input PLL L.P.F. Detector Output
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5. MODEL WAVEFORMS:
DATA
Clock
t
DATA
t
FSK
Signal
t
Demodulated
Signal
1. Switch ON the power supply.

2. Set the Data selection switch (‘DATA SELECTION’) to the desired code(say
11001100).
3. Set the switch (‘DATA ON-OFF) ON position. Observe the 8 Bit Word pattern at
TP12.
4. Observe the Data Clock at TP1 and also observe the NRZ(L) at TP2, RZ at
TP3, NRZ(M) at TP4, BIPHASE(MARK) at TP5, BIPHASE (MANCHESTER) at
TP6.
5. Connect the patch cord as shown in diagram 1. Observe the corresponding
FSK output at (when Data is logic ‘1’, the frequency is high and Data is logic ‘0’
the frequency is low) TP8.
6. Repeat the step 5 for other inputs.(like NRZ(M),RZ,BIPHASE) observe the
corresponding FSK outputs.
7. Now change the Data Selection and repeat the above steps 3 to 6 and observe
the corresponding FSK outputs.
LBRCE, ECE 47
7. PRECAUTIONS:

teacher.
8. OBSERVATION:
1. Input data sequence :______________

2. Mark Frequency _______________
3. Space frequency _______________
4. Phase difference between mark frequency and space frequency
signals_____________
5. Demodulated data output sequence________________
9. RESULT:
The Frequency Shift Keying modulation and demodulation is performed

1. Define FSK?
2. What is the other name of Binary FSK signaling?
3. What kind of modulator is used to generate FSK?
4. What are the applications of FSK?
5. What is the use of integrator in generation of FSK waveforms?
6. What is the use of decision-making device?
7. What is the use of delay line?
LBRCE, ECE 48
PHASE SHIFT KEYING EXPT. NO : 8
DATE :
1. AIM:
To generate PSK Modulated and Demodulated waveforms.

 PSK modulator and De-modulator trainer kit
 Dual channel CRO (30 MHz), Patch chords.
3. THEORY:
The PSK is form of angle modulation with constant amplitude and frequency. In
PSK two phases are available for a single carrier frequency. As the input signal changes
the state the phase of the output carrier shifts 180 degrees out of the phase. One output
phase represents a logic ’1’ and other a logic ‘0’. Another name given for BPSK is phage
reversal or bi-phase modulation. In general to generate BPSK a simple ring modulator is
used. The required band width for transmission of PSK is equal to applied bit rate. The
ASK is a linear modulation and PSK is a non linear modulation. Advantage of PSK
signaling lies in its superior performance over ASK operating under same power
limitation and noise environment. The mark frequency and space frequency are same in
PSK system, but only difference is in phase for logic ’1’ PSK output is out of the phase
with carrier and for logic’0’ PSK output is in phase with the carrier signal.
4. BLOCK DIAGRAM:
950 M Hz
Modul
Modulating
Signal
(in phase) MODULATOR
-1
DATA Input
PSK Output
Signal
950 M Hz
Modulating
Signal
(out of phase) MODULATOR
-2
Inverted
DATA Input
LBRCE, ECE 49
De - Modulator
Phase Bit Demodulated
PSK Input Detector L.P.F. Detector Output
4.CIRCUIT DIAGRAM :
LBRCE, ECE 50
5. MODEL WAVEFORMS:
DATA
Clock
t
DATA
t
PSK
Signal
t
Demodulated
Signal
1. Connect the AC Adaptor to the mains and the other side to the Experimental
Trainer. Switch ‘ON’ the power.
2. Apply the carrier signal to the input of the modulator.
3. Apply the modulating data signal to the modulator input and observe this signal
on channel 1 of the CRO.
4. Observe the output of the PSK modulator on the channel 2 of the CRO.
5. Apply this PSK output to the demodulator input and also apply the carrier input.
6. Observe the demodulator output and compare it with the modulating data signal
applied to the modulator input which is identical.
7. PRECAUTIONS:
teacher.
LBRCE, ECE 51
8. OBSERVATION:
1. Input data sequence :______________

2. Mark Frequency _______________
3. Space frequency ________________
4. PSK amplitude when input is logic’0’____________
5. PSK amplitude when input is logic’1’____________
6. Phase difference between mark frequency and space frequency
signals________
7. Demodulated data output sequence________________
9. RESULT:
The phase shift keying modulation and demodulation is performed

1. Define PSK?
2. What is the other name of Binary PSK signaling?
3. What kind of modulator is used to generate PSK?
4. What are the applications of PSK?
LBRCE, ECE 52
DIFFERENTIAL PHASE SHIFT KEYING EXPT. NO : 9(A)
MODULATION DATE :
1. AIM: Study and analysis of DBPSK Modulator

2. COMPONENTS AND TOOLS REQUIRED
 DBPSK modulation and demodulation trainer kit- Scientech2807
 Power Supply
 Test probe
3. THEORY:
Differential coding – Is used to provide polarity reversal protection Bit streams going
through the many communications circuits in the channel can be un-intentionally
inverted. Most signal processing circuits cannot tell if the whole stream is inverted. This
is also called phase ambiguity. Differential Encoding is used to protect against this
possibility. It is one of the simplest form of error protection coding done on a baseband
sequence prior to modulation Then the phase of the carrier is varied to represent binary
1 or 0 of encoded data. Both peak amplitude remains constant as the phase changes.
A Differential Coding system consists of a modulo 2 adder operation as shown below.
Differential Encoder
LBRCE, ECE 53
Block Diagram of DBPSK Transmitter
In DBPSK modulator incoming NRZ encoded data is fed into differential decoder .the
differential decoded output is then multiplied by carrier signal . thelogic high is produce
180 deg. phase shift in carrier signal while logic ‘0’ produce zero deg. Phase transition.
Waveform of DBPSK modulation
LBRCE, ECE 54
5. PROCEDURE:
Step2 : Select Differential BPSK modulator by Modulation technique selection
button on selection Differential BPSK LED on TP17 will glows.
Step3: Select input Data pattern using push button i.e. 8-Bit, 16-Bit, 32-Bit, 64- Bit. And
Step5 : Observe the encoded input data on test point (TP17).
Step6 : Observe the carrier signal on test point (TP20).
Step7 : Observe the DBPSK modulated output at test point (TP21)
LBRCE, ECE 55
6. OBSERVATIONS:
 Observe the input data clock atTP1.
 Observe the input data atTP2.
 Observe the encoded input data atTP17.
 Observe the Differential encoder output at TP18
 Observe the carrier signal atTP20.
 Observe the DBPSK modulated output at TP21 Observe the following data
Patterns on TP2
8-Bit: “10110010 ”
16-Bit: “0100110110110010 ”
32-Bit: “00000101000101111100101000111111 ”
64-Bit:
“1010110011100011110000111110000011110000111000110010101000111010”
LBRCE, ECE 56
Type Frequency
8-Bit 2KHz
CH1: encoded input data (TP17), CH2: Carrier

signal (TP20)
8-Bit 2KHz
CH1: Differential out (TP18) CH2: DBPSK output

(TP21)
LBRCE, ECE 57
8-Bit 2KHz
CH1: Carrier signal (TP20) CH2: DBPSK

output (TP21)
7. PRECAUTIONS:
teacher.
8. RESULT
Thus the Differential binary phase shift keying modulation is performed and graphs
were plotted.
9. VIVA QUESTIONS:
1. Compare DPSK with BPSK modulation scheme and mention advantages.
2. What is the principle of DPCM?
LBRCE, ECE 58
DIFFERENTIAL PHASE SHIFT KEYING EXPT. NO :9(B)
DEMODULATION DATE :
1. AIM: Study and analysis of DBPSK Demodulator

 DBPSK modulation and demodulation trainer kit- Scientech2807
 Power Supply
 Test probe
3. THEORY:
DBPSK Demodulator
The incoming modulated DBPSK signal is multiplied with the carrier signal. The output of
the multiplier contains high (fin+fnco) and low (fin-fnco) frequency components. Multiplier
output fed into integrator block . The output of Integrator is compared in comparator
block based on threshold value .this output is decoded at differential decoder where we
can recover input data.
Block Diagram of DBPSK Receiver
LBRCE, ECE 59
LBRCE, ECE 60
5. PROCEDURE:
Step 2: Select Differential BPSK modulator by Modulation technique selection button on
selection of Differential BPSK technique LED on TP17 will glows.
Step 3: Select input Data pattern using push button i.e. 8-Bit, 16-Bit, 32-Bit, 64- Bit. And
Step5 : Observe the change in carrier signal on test point (TP20) & test point (TP22).
Step6 : Observe the encoded input data pattern at test point (TP17).
Step7 : Observe the DBPSK modulated output at test point (TP21)
Step8 : Observe the complex multiplier output at test point (TP23)
Step9 : Observe the Integrator output at test point (TP24)
Step10: Observe the Comparator output at test point (TP25)
Step11: Observe the output of Demodulator on test point (TP27)
6. OBSERVATIONS:
 Observe the input data clock atTP1.

 Observe the input data atTP2.
 Observe the encoded input data atTP17.
 Observe the Differential encoder output at TP18
 Observe the carrier signal at TP20 &TP22.
 Observe the DBPSK modulated output atTP21
 Observe the complex multiplier output atTP23
 Observe the Integrator output atTP25
 Observe the Demodulator output at TP27 Observe the following data Patterns
onTP2
8-Bit: “10110010”
16-Bit: “0100110110110010”
32-Bit: “00000101000101111100101000111111”
64-Bit:
“1010110011100011110000111110000011110000111000110010101000111010”
LBRCE, ECE 61
Type Frequency
8-Bit 2KHz
CH1: DBPSK out (TP21)

CH2: Demodulator out (TP27)
8-Bit 2KHz
CH1: Encoded input data (TP17) CH2:

Demodulator out (TP27)
LBRCE, ECE 62
7. PRECAUTIONS:
 Before switch on the power supply get the circuit connections verified by
the teacher.
 After taking the readings bring back all the control knobs to minimum
position.
8. RESULT:
Thus the Differential binary phase shift keying demodulation is performed
and graphs were plotted.
9. VIVA QUESTIONS:
1. Mention the bandwidth of DPSK.
2. Differentiate DPSK with PSK in terms of detection process.
LBRCE, ECE 63
LINEAR BLOCK CODE- ENCODER AND EXPT. NO : 10
DECODER DATE :
1. AIM: To study Linear block code (Encoding and Decoding) of BCD bit
sequence in manual mode with single bit error.
2. EQUIPMENTS AND TOOLS REQUIRED:

 Block code encoder trainer kit - Scientech 2121A
 Block code decoder trainer kit - Scientech 2121B
 2 mm Banana cable
 Oscilloscope Scientech 803/831, or equivalent
3. THEORY:
Linear block codes:
Linear block codes are conceptually simple codes that are basically an
extension of single-bit parity check codes for error detection. A single-bit parity
check code is one of the most common forms of detecting transmission errors.
This code uses one extra bit in a block of n data bits to indicate whether the
number of 1s in a block is odd or even. Thus, if a single error occurs, either the
parity bit is corrupted or the number of detected 1s in the information bit
sequence will be different from the number used to compute the parity bit: in
either case the parity bit will not correspond to the number of detected 1s in the
information bit sequence, so the single error is detected.
Linear block codes extend this notion by using a larger number of parity bits to
either detect more than one error or correct for one or more errors. Unfortunately
linear block codes, along with convolutional codes, trade their error detection or
correction capability for either bandwidth expansion or a lower data rate, as will
be discussed in more detail below. We will restrict our attention to binary codes,
where both the original information and the corresponding code consist of bits
taking a value of either 0 or 1.
LBRCE, ECE 64
Binary Linear Block Codes:
A binary block code generates a block of n coded bits from k information bits.
We call this an (n, k) binary block code. The coded bits are also called codeword
symbols. The n codeword symbols can take on 2 n possible values
corresponding to all possible combinations of the n binary bits. We select 2k
codewords from these 2n possibilities to form the code, such that each k bit
information block is uniquely mapped to one of these 2k codewords.
The rate of the code is Rc = k/n information bits per codeword symbol. If we
assume that codeword symbols are transmitted across the channel at a rate of
Rs symbols/second, Then the information rate associated with an (n, k) block
code is Rb=RcRs =knRs bits/second. Thus we see that block coding reduces
the data rate compared to what we obtain with un-coded modulation by the code
rate Rc. A block code is called a linear code when the mapping of the k
information bits to the n codeword symbols is a linear mapping.
Generator Matrix:
The generator matrix is a compact description of how codewords are generated
from information bits in a linear block code. The design goal in linear block
codes is to find generator matrices such that their corresponding codes are easy
to encode and decode yet have powerful error correction/detection capabilities.
Consider an (n, k) code with k information bits denoted as
Those are encoded into the codeword
We represent the encoding operation as a set of n equations defined by
Where gij is binary (0 or 1) and binary (standard) multiplication is used. We can

write these n equations in matrix form as
LBRCE, ECE 65
Where the k × n generator matrix G for the code is defined as
Parity Check Matrix and Syndrome Testing:

The parity check matrix is used to decode linear block codes with generator
matrix G. The parity check matrix H corresponding to a generator matrix G =
[Ik|P] is defined as
It is easily verified that GHT = 0k, n−k, where 0k,n−k, denotes an all zero k
×(n−k) matrix. Recall that a given codeword Ci in the code is obtained by
multiplication of the information bit sequence Ui by the generator matrix G: Ci =
UiG. Thus,
For any input sequence Ui, where 0n−k denotes the all-zero row vector of length
n−k. Thus multiplication of any valid codeword with the parity check matrix
results in an all zero vector. This property is used to determine whether the
received vector is a valid codeword or has been corrupted, based on the notion
of syndrome testing, which we now define. Let R be the received codeword
resulting from transmission of codeword C. In the absence of channel errors,
R=C. However, if the transmission is corrupted, one or more of the codeword
LBRCE, ECE 66
symbols in R will differ from those in C. We therefore write the received
codeword as
Where e = [e1e2 . . . en] is the error vector indicating which codeword symbols
were corrupted by the channel. We define the syndrome of R as
If R is a valid codeword, i.e. R = Ci for some i, then S = CiHT = 0n−k by (8.14).

Thus, the syndrome equals the all zero vector if the transmitted codeword is not
corrupted, or is corrupted in a manner such that the received codeword is a valid
codeword in the code that is different from the transmitted codeword. If the
received codeword R contains detectable errors, then S ≠ 0n−k. If the received
codeword contains correctable errors, then the syndrome identifies the error
pattern corrupting the transmitted codeword, and these errors can then be
corrected. Note that the syndrome is a function only of the error pattern e and
not the transmitted codeword C, since
Since S = eHT corresponds to n − k equations in n unknowns, there are 2k

possible error patterns that can produce a given syndrome S. However, since
the probability of bit error is typically small and independent for each bit, the
most likely error pattern is the one with minimal weight, corresponding to the
least number of errors introduced in the channel. Thus, if an error pattern ê is
the most likely error associated with a given syndrome S, the transmitted
codeword is typically decoded as
When the most likely error pattern does occur, i.e. ˆe = e, then ˆC = C, i.e. the
corrupted codeword is correctly decoded
LBRCE, ECE 67
Let Cw denote a codeword in a given (n, k) code with minimum weight
(excluding the all-zero codeword). Then CwHT = 0n−k is just the sum of dmin
columns of HT, since dmin equals the number of 1s (the weight) in the minimum
weight codeword of the code. Since the rank of HT is at most n − k, this implies
that the minimum distance of an (n, k) block code is upper bounded by
4. CIRCUIT DIAGRAM:
LBRCE, ECE 68
5. PROCEDURE:
1. Connect the power supply mains cord to the Scientech 2121A,
but do not turn ON the power supply until connections are made
for this experiment.
2. Keep default/manual switch in Manual mode.
3. There are some conditions regarding H-Matrix selection manually which
are:
a. Any row should not be identically selected like there should
not all 1’s or all 0’s.
b. Each row selection should be different from other row.
c. The matrix should be so chosen that all the rows are distinct
and consist of at least two 1’s in them.
4. Switch ‘On’ the power supply and press reset button.
5. Check the clock pulse of 2 KHz on Oscilloscope at given test point.
6. Now repeat the steps 6 to 10 of Experiment 3.
7. Now with the help of patch cord connect horizontal bit stream to
vertical bit stream but with an error using inverter gate as per
connection diagram shown above.
8. At the output of parallel to serial convertor we receive a serially
out data stream. This is not exactly same as generated data
because we have given a single bit error to it.
9. For any selected data from 0-9, check the H matrix in the form of H= [P]
[Ik]; Parity matrix and Identity matrix.
10. Check the massage signal in vertical matrix ‘R’ in the form of (d3,
d2, d1, d0, p3, p2, p1) and check the status of Syndrome E m. As
there is a single bit error in the bits it will show one LED glowing.
11. Check the corrected code word and match it with the code word of
Encoder unit.
12. Also check the Decode Bits (d3, d2, d1, d0) and match with the
data at Encoder unit.
13. Hamming Code (7, 4) is capable of correcting single bit error
hence the detected data is the same as input data of Encoder
unit.
LBRCE, ECE 69
6. OBSERVATIONS:
Observation Table 1: Scientech 2121B Block Code Decoder

Syndrom Generator :
h matrix Identity Matrix

0 1 1 1 1 0 0
1 0 1 1 0 1 0
1 1 0 1 0 0 1
Observation Table 2:
Check Points for Default
Mode
Scientech 2121A Block Code Encoder Scientech 2121B Block Code

Decoder
Decimal Binary Code Word Corrected Code Word Decode Decimal

7 Segment d3 d2 d1 d0 d3 d2 d1 d0 p3 p2 p1 d3 d2 d1 d0 p3 p2 p1 Data
0 0000 d3 d2 d1 d0 7 Segment
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
7. RESULT:
Thus, the encoding and decoding of linear block code is studied and
observed the decoded data with single bit error.
8. VIVA QUESTIONS:
 What is hamming distance and its significance?
 What is meant by syndrome of linear block code?
 What are the error detection and correction capabilities of hamming
codes?
 How syndrome is calculated in Hamming codes?
LBRCE, ECE 70
BINARY CYCLIC CODE- ENCODER AND EXPT. NO : 11
DECODER DATE :
1. AIM: Study of Cyclic Encoding and Decoding of BCD bit sequence

 Error Detection & Correction Cyclic Code trainer kit - Scientech 2120
 2 mm Banana cable
 Oscilloscope Scientech 831 or equivalent
3. THEORY:
Error detection is the ability to detect the presence of errors caused by noise
or other impairments during transmission from the transmitter to the receiver.
Error correction is the additional ability to reconstruct the original, error-free
data.
There are two basic ways to design the channel code and protocol for an error
correcting system.
Automatic Repeat Request (ARQ): The transmitter sends the data and also
an error detection code, which the receiver uses to check for errors, and
requests retransmission of erroneous data. In many cases, the request is
implicit; the receiver sends an acknowledgment (ACK) of correctly received
data, and the transmitter re- sends anything not acknowledged within a
reasonable period of time.
Forward Error Correction (FEC): The transmitter encodes the data with an
error- correcting code (ECC) and sends the coded message. The receiver
never sends any messages back to the transmitter. The receiver decodes
what it receives into the "most likely" data. The codes are designed so that it
would take an "unreasonable" amount of noise to trick the receiver into
misinterpreting the data.
LBRCE, ECE 71
It is possible to combine the two, so that minor errors are corrected without
retransmission, and major errors are detected and a retransmission
requested. The combination is called Hybrid automatic repeat-request.
An error-detection technique used widely in today’s computer networks and

data storage devices is based on Cyclic Redundancy Check (CRC) codes.
In this simulator, we are implementing two different types of CRC codes: one
is the Systematic CRC code and the other is the standard CRC code. The
Systematic CRC code is also called “Separable” CRC because data word can
be located and retrieved from encoded word before the decoding process
takes place. The standard CRC, on the other hand, is called “Non-Separable”
CRC code because the data word cannot be separated from encoded word
before it goes through a decoding process. The basic idea of CRC coding is to
generate an encoded word of length n bits by using a k-bit data word and an
(n-k+1) bit generator polynomial whose degree is (n-k).
The encoding can be implemented by using a division circuit which is a shift

register with feedback connections based on the generator polynomial g(x), as
shown below. The right-most symbol of the word is the first symbol to enter
the encoder, subscript- order notwithstanding. The gate is turned on until all
the information digits have been shifted into the circuit. After the entire r(x) has
been shifted into the register, the contents in the register do not form the
syndrome of r(x); rather they form the syndrome s (n-k) (x) of r (n-k) (x), which
is the cyclic shift of r(x). This is because shifting r(x) from the right end is
equivalent to premultiplying r(x) by x (n-k). This says that, when r (n-k) (x) is
divided by g(x), ρ(x) is also the remainder. Therefore ρ(x) is s (n-k) (x) .
LBRCE, ECE 72
Encoder for (7, 4) Cyclic Code Generator by g(x) =1+x2+x3
Table showing the register contents of encoder
The following describes the encoding procedure for encoder shown above:
1. Switch 1 is closed during the first k shifts, to allow transmission of the
message into the n-k stage encoding shift register.
2. Switch 2 is in the down position to allow transmission of the message
bits directly to an output register during the first k shifts.
3. After transmission of the kth message bit, switch 1 is opened and switch
2 is moved to the up position.
4. The remaining n – k shifts clear the encoding register by moving the
parity bits to the output register.
5. The total number of shifts is equal to n, and the contents of the output
register is the codeword polynomial r(X) + xn-km(X).
LBRCE, ECE 73
LBRCE, ECE 74
5. PROCEDURE:
1. Connect the power supply mains cord to the Scientech 2120, but do not
turn ON the power supply until connections are made for this
experiment.
2. From Clock Section, connect 16 KHz Clock output to Clock Generator

(Clock input).
3. Connect the Data Clock of clock generation section to Data Clock of

Data Source.
4. Connect the Data Out of Data Source to Data In of Cyclic Encoder.
5. Connect the Code Clock of Clock Generation section to Code Clock of

Cyclic Encoder.
6. Switch ‘On’ the power supply and oscilloscope.
7. Observe the bit pattern of Code Word output of Cyclic Encoder on CRO.
The bit stream is a repeating 8 bit serial sequence of the input data
selected through BCD switches.
8. Change input data through BCD switches and observe the output of
Cyclic Encoder.
9. Now connect the Code Word output of Cyclic Encoder to Decoder and
output of Decoder to input of display.
10. Change the clock input to 8 KHz to 1 KHz and then observe the data
output.
LBRCE, ECE 75
6. OBSERVATIONS:
Clock and Data
Data and Codeword
LBRCE, ECE 76
7. OBSERVATIONS:
 The data output of Data Source is a repeating sequence of input data

selected through BCD switches.
 The 8 bits of output data are binary coded decimal values on BCD
switches.
 The output data rate of Data Sources is selected through the input data
clock.
 Encoded and decoded data stream is same as observed on segmental

display as well as waveforms on CRO.
8. RESULT:
 The data output of Data Sources on providing to Cyclic Encoder

generate the code word by inserting certain redundant bits to data bits.
 The code word is appearing correctly with different data clock applied
and the result is also verified on oscilloscope.
9. Viva questions:
1. What is cyclic encoding and decoding?
2. What do you understand by CRC?
3. What are BCD codes?
4. Classify the error messages?
5. Explain the function of parallel to serial converter and serial to

parallel converter?
LBRCE, ECE 77
LINE CODING SCHEMS EXPT. NO : 12
DATE :
1. AIM: To implement different line coding techniques for a given bit stream
using MATLAB.
2. EQUIPMENTS REQUIRED:
 Personal computer
 MATLAB version 9.1
3. THEORY:
A line code is the code used for data transmission of a digital signal over a
transmission line. This process of coding is chosen so as to avoid overlap and
distortion of signal such as inter-symbol interference. Some of the more
common binary line codes include:
NRZ–L: Non return to zero level. This is the standard positive logic signal format
used in digital circuits. For binary-1: forces a high level. For binary-0: forces a
low level
NRZ–M: Non return to zero mark. For binary-1: forces a transition. For binary-0:
does nothing (keeps sending the previous level)
NRZ–S: Non return to zero space. For binary-1: does nothing (keeps sending
the previous level). For binary-0: forces a transition
RZ: Return to zero. For binary-1: goes high for half the bit period and returns to
low. For binary-0: stays low for the entire period
Biphase–L: Manchester. Two consecutive bits of the same type force a
transition at the beginning of a bit period. For binary-1: forces a negative
transition in the middle of the bit. For binary-0: forces a positive transition in the
middle of the bit
Biphase–M: Variant of Differential Manchester. There is always a transition
halfway between the conditioned transitions. For binary-1: forces a transition.
For binary-0: keeps level constant
Biphase–S: Differential Manchester used in Token Ring. There is always a
transition halfway between the conditioned transitions. For binary-1: keeps level
constant. For binary-0: forces a transition
LBRCE, ECE 78
Bipolar: The positive and negative pulses alternate. For binary-1: forces a
positive or negative pulse for half the bit period. For binary-0: keeps a zero level
during bit period.
4. PROCEDURE:
1. Open the MATLAB software by double clicking the icon on desktop.
2. Open the new M-file by using file menu.
3. Write the program in new file.
4. Click on save and run the icon.
5. Perform error check which displayed on command window.
6. Plot the waveforms displayed on figure window.
5. PROGRAM:
Main program:
clear all;clc;
a = [1 0 1 1 0 1 0 0 1 0 1];%---Bit stream
A = 1; %---Amplitude
Tb = 10e-6; %---Bit time period
%---Get Unipolar NRZ
[x t] = LineEncoder('uninrz',a,Tb,A);
figure(1);
subplot(5,1,1);plot(t,x,'LineWidth',2);grid on;
title(['Unipolar NRZ line coding for ', num2str(a)]);
xlabel('Time in sec'); ylabel('Amplitude');
axis([0,max(t),min(x)-A,max(x)+A]);
%---Get Unipolar RZ
[x t] = LineEncoder('unirz',a,Tb,A);
title(['Unipolar RZ line coding for ', num2str(a)]);
%---Get Polar RZ
[x t] = LineEncoder('polrz',a,Tb,A);
title(['Polar RZ line coding for ', num2str(a)]);
%---Get Polar NRZ
[x t] = LineEncoder('polnrz',a,Tb,A);
title(['Polar NRZ line coding for ', num2str(a)]);
LBRCE, ECE 79
%---Get Manchester
[x t] = LineEncoder('manchester',a,Tb,A);
title(['Manchester line coding for ', num2str(a)]);
Line encoder function:
function [x T] = LineEncoder(type,inbits,Tb,A)
%---Checking input arguments
if nargin<4, A = 1;end
if nargin<3, Tb = 1e-9;end
if nargin<2, inbits = [1 0 1 0];end
if nargin<1, type = 'uninrz';end
%---Implementation starts here
Rb = 1/Tb; %---Bit rate
Fs = 4*Rb;
N = length(inbits); %---Bit Length of input bits
tTb = linspace(0,Tb); %---interval of bit time period
x = [];
switch lower(type)
case 'uninrz'
for k = 1:N
x = [x A*inbits(k)*ones(1,length(tTb))];
end
case 'unirz'
for k = 1:N
x = [x A*inbits(k)*ones(1,length(tTb)/2) 0*inbits(k)*ones(1,length(tTb)/2)];
end
case 'polrz'
for k = 1:N
c = ones(1,length(tTb)/2); b = zeros(1,length(tTb)/2); p = [c b];
x = [x ((-1)^(inbits(k)+1))*(A/2)*p];
end
case 'polnrz'
for k = 1:N
x = [x ((-1)^(inbits(k) + 1))*A/2*ones(1,length(tTb))];
end
case 'manchester'
for k = 1:N
c = ones(1,length(tTb)/2); b = -1*ones(1,length(tTb)/2); p = [c b];
x = [x ((-1)^(inbits(k)+1))*A/2*p];
end
case 'ami'
end
T = linspace(0,N*Tb,length(x)); %---Time vector for n bits
LBRCE, ECE 80
6. PRECAUTIONS:
1. Check out source file is with ‘.m’ extension or not.
2. The file name should begin with character and should not contain any
punctuation marks.
3. File name should not be any in built in function name or any keyword
4. Save the .m files preferably in work folder of MATLAB.
5. Don’t delete any file or folder without informing the system
administrator or lab in-charge.
7. MODEL WAVEFORMS:
8. RESULT:
Amplitude Shift Keying Modulation and demodulation performed using
MATLAB and Communication Toolbox.
LBRCE, ECE 81
ASK MODULATION AND DEMODULATION EXPT. NO : 13
DATE :
1. AIM: To implement the Amplitude Shift Keying Modulation and Demodulation

signals using MATLAB.
1. Personal computer
2. MATLAB version 9.1
3. THEORY:
Amplitude-Shift Keying (ASK) or On-Off Keying (OOK) is a form of modulation
that represents digital data as variations in the amplitude of a carrier wave. The
amplitude of an analog carrier signal varies in accordance with the bit stream
(modulating signal), keeping frequency and phase constant.
In ASK Modulator level of amplitude can be used to represent binary logic 0s
and 1s. We can think of a carrier signal as an ON or OFF switch. In the
modulated signal, logic 0 is represented by the absence of a carrier, thus giving
OFF/ON keying operation and hence the name given. Mathematically ASK is
given by
At receiver side ASK modulated signal is multiplied by the carrier signal which is
generated from the carrier generator the output of multiplier consist of higher
frequency and lower frequency components this output then integrated by
Integrator block and passed by comparator block . Comparator block recovers
digital data by comparing threshold value with integrated signal.
LBRCE, ECE 82
4. PROCEDURE:
5. PROGRAM:
%>>>>>>>>> MATLAB code for binary ASK modulation and de-modulation
>>>>>>>%
clc; clear all; close all;
x=[ 1 0 0 1 1 0 1]; % Binary Information
bp=.000001; % bit period
disp(' Binary information at Trans mitter :'); disp(x);
%XX representation of transmitting binary information as digital signal XXX
bit=[];
for n=1:1:length(x)
if x(n)==1;
se=ones(1,100);
else x(n)==0;
se=zeros(1,100);
end
bit=[bit se];
end
t1=bp/100:bp/100:100*length(x)*(bp/100);
subplot(3,1,1);
plot(t1,bit,'lineWidth',2.5);grid on;
axis([ 0 bp*length(x) -.5 1.5]);
ylabel('amplitude(volt)');
xlabel(' time(sec)');
title('transmitting information as digital signal');
%XXXXXXXXXXXXXXXXXXXXXXX Binary-ASK modulation
XXXXXXXXXXXXXXXXXXXXXXXXXXX%
A1=10; % Amplitude of carrier signal for information 1
A2=5; % Amplitude of carrier signal for information 0
br=1/bp; % bit rate
f=br*10; % carrier frequency
t2=bp/99:bp/99:bp;
ss=length(t2);
m=[];
for (i=1:1:length(x))
if (x(i)==1)
LBRCE, ECE 83
y=A1*cos(2*pi*f*t2);
else
y=A2*cos(2*pi*f*t2);
end
m=[m y];
end
t3=bp/99:bp/99:bp*length(x);
subplot(3,1,2);
plot(t3,m);
xlabel('time(sec)');
title('waveform for binary ASK modulation coresponding binary information');
%XXXXXXXXXXXXXXXXXXXX Binary ASK demodulation
XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
mn=[];
for n=ss:ss:length(m)
t=bp/99:bp/99:bp;
y=cos(2*pi*f*t); % carrier siignal
mm=y.*m((n-(ss-1)):n);
t4=bp/99:bp/99:bp;
z=trapz(t4,mm) % intregation
zz=round((2*z/bp))
if(zz>7.5) % logic level = (A1+A2)/2=7.5
a=1;
else
a=0;
end
mn=[mn a];
end
disp(' Binary information at Reciver :');
disp(mn);
%XXXXX Representation of binary information as digital signal which achived
%after ASK demodulation
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
bit=[];
for n=1:length(mn);
if mn(n)==1;
se=ones(1,100);
else mn(n)==0;
se=zeros(1,100);
end
bit=[bit se];
end
t4=bp/100:bp/100:100*length(mn)*(bp/100);
subplot(3,1,3)
plot(t4,bit,'LineWidth',2.5);grid on;
axis([ 0 bp*length(mn) -.5 1.5]);
LBRCE, ECE 84
ylabel('amplitude(volt)'); xlabel(' time(sec)'); title('recived information as digital
signal after binary ASK demodulation');
%>>>>>>>>>>>>>>>>>>>>>>>>>> end of program %
6. PRECAUTIONS:
punctuation marks.
7. MODEL WAVEFORMS:
8. RESULT:
Amplitude Shift Keying Modulation and demodulation performed using
LBRCE, ECE 85
FSK MODULATION AND DEMODULATION EXPT. NO : 14
DATE :
1. AIM: To implement the Frequency Shift Keying Modulation and Demodulation

3. THEORY:
In FSK Modulation, we change the frequency in response to information, one
particular frequency for Logic 1 and another frequency for Logic 0. For
Example:-Sin (2πf1t) is transmitted for logic ‘1’ and Sin (2πf 2t) is transmitted for
logic ‘0’.
The general expression for FSK is
From equation 1, it can be seen that the peak shift in the carrier ( f) is
proportional to the amplitude of the binary input signal (Vm(f)), and the direction
of the shift is determined by the polarity. The modulating signal is a normalized
waveform where logic 1 = +1 volt and logic 0 = -1volt.Thus, for a logic1 input,
equation1 can be written as
For logic 0 input, equation can be written as
With binary FSK, the carrier center frequency (fc) is shifted up and down in the
frequency domain by binary input signal. As the input changes from logic 1 to a
logic 0 and vice versa, the output frequency shift between two frequencies.
LBRCE, ECE 86
4. PROCEDURE:
5. PROGRAM:
%>>>>>>>>> MATLAB code for binary FSK modulation and de-modulation%
clc; clear all; close all;
disp(' Binary information at Trans mitter :'); disp(x);
bit=[];
for n=1:1:length(x)
if x(n)==1;
se=ones(1,100);
else x(n)==0;
se=zeros(1,100);
end
bit=[bit se];
end
t1=bp/100:bp/100:100*length(x)*(bp/100);
subplot(3,1,1);
ylabel('amplitude(volt)'); xlabel(' time(sec)');
%XXXXXXXXXXXXXXXXXXXXXXX Binary-FSK modulation XXXXXXXXXX%
A=5; % Amplitude of carrier signal
br=1/bp; % bit rate
f1=br*8; % carrier frequency for information as 1
f2=br*2; % carrier frequency for information as 0
t2=bp/99:bp/99:bp;
ss=length(t2);
m=[];
if (x(i)==1)
y=A*cos(2*pi*f1*t2);
else
y=A*cos(2*pi*f2*t2);
end
m=[m y];
LBRCE, ECE 87
end
subplot(3,1,2);
plot(t3,m);
xlabel('time(sec)'); ylabel('amplitude(volt)');
title('waveform for binary FSK modulation coresponding binary information');
%XXXXXXXXXXXXXXXXXXXX Binary FSK demodulation
XXXXXXXXXXXXXX
mn=[];
t=bp/99:bp/99:bp;
y1=cos(2*pi*f1*t); % carrier siignal for information 1
y2=cos(2*pi*f2*t); % carrier siignal for information 0
mm=y1.*m((n-(ss-1)):n);
mmm=y2.*m((n-(ss-1)):n);
t4=bp/99:bp/99:bp;
z1=trapz(t4,mm) % intregation
z2=trapz(t4,mmm) % intregation
zz1=round(2*z1/bp)
zz2= round(2*z2/bp)
if(zz1>A/2) % logic lavel= (0+A)/2 or (A+0)/2 or 2.5 ( in this case)
a=1;
else(zz2>A/2)
a=0;
end
mn=[mn a];
end
disp(mn);
%after demodulation XXXXXXXXXXXXX
bit=[];
for n=1:length(mn);
if mn(n)==1;
se=ones(1,100);
else mn(n)==0;
se=zeros(1,100);
end
bit=[bit se];
end
subplot(3,1,3)
title('recived information as digital signal after binary FSK demodulation');
%>>>>>>>>>>>>>>>>>>>>>>>>>> end of program %
LBRCE, ECE 88
6. PRECAUTIONS:
punctuation marks.
7. MODEL WAVEFORMS:
8. RESULT:
Frequency Shift Keying Modulation and demodulation performed using MATLAB
and Communication Toolbox.
LBRCE, ECE 89
PSK MODULATION AND DEMODULATION EXPT. NO : 15
DATE :
1. AIM: To implement the Phase Shift Keying Modulation and Demodulation

3. THEORY:
In BPSK modulation, the phase of the RF carrier is shifted 180 degrees in
accordance with a digital bit stream. A "one" causes a phase transition, and a
"zero" does not produce a transition.
In BPSK (Binary Shift Keying) Modulator, the phase of the carrier is varied to
represent binary 1 or 0. Both peak amplitude remains constant as the phase
changes. For example, if we start a phase of 0 deg. to represent binary ‘1’, then
we can change the phase to 180deg. to send binary ‘0’.
The incoming modulated BPSK signal is multiplied with the carrier signal
generated from the carrier generator. The output of the multiplier contains high
(fin -fnco) and low (fin -fnco) frequency components. The integrator block integrates
multiplier output. With the help of comparator by comparing thresh hold value
input data is received.
4. PROCEDURE:
LBRCE, ECE 90
5. PROGRAM:
%>>>>>>>>> MATLAB code for binary PSK modulation and de-modulation
>>>>>>>%
clc;
clear all;
close all;

disp(' Binary information at Trans mitter :');
disp(x);

bit=[];
for n=1:1:length(x)
if x(n)==1;
se=ones(1,100);
else x(n)==0;
se=zeros(1,100);
end
bit=[bit se];
end
t1=bp/100:bp/100:100*length(x)*(bp/100);
subplot(3,1,1);
xlabel(' time(sec)');
%XXXXXXXXXXXXXXXXXXXXXXX Binary-PSK modulation

XXXXXXXXXXXXXXXXXXXXXXXXXXX%
A=5; % Amplitude of carrier signal
br=1/bp; % bit rate
f=br*2; % carrier frequency
t2=bp/99:bp/99:bp;
ss=length(t2);
m=[];
if (x(i)==1)
y=A*cos(2*pi*f*t2);
else
y=A*cos(2*pi*f*t2+pi); %A*cos(2*pi*f*t+pi) means -A*cos(2*pi*f*t)
end
LBRCE, ECE 91
m=[m y];
end
subplot(3,1,2);
plot(t3,m);
xlabel('time(sec)'); ylabel('amplitude(volt)');
title('waveform for binary PSK modulation coresponding binary information');
%XXXXXXXXXXXXXXXXXXXX Binary PSK demodulation

XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
mn=[];
t=bp/99:bp/99:bp;
y=cos(2*pi*f*t); % carrier siignal
mm=y.*m((n-(ss-1)):n);
t4=bp/99:bp/99:bp;
z=trapz(t4,mm) % intregation
zz=round((2*z/bp))
if(zz>0) % logic level = (A+A)/2=0
%becouse A*cos(2*pi*f*t+pi) means -A*cos(2*pi*f*t)
a=1;
else
a=0;
end
mn=[mn a];
end
disp(mn);
%after PSK demodulation
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
bit=[];
for n=1:length(mn);
if mn(n)==1;
se=ones(1,100);
else mn(n)==0;
se=zeros(1,100);
end
bit=[bit se];
end
subplot(3,1,3)
title('recived information as digital signal after binary PSK demodulation');
%>>>>>>>>>>>>>>>>>>>>>>>>>> end of program %

LBRCE, ECE 92
6. PRECAUTIONS:
punctuation marks.
7. MODEL WAVEFORMS:
8. RESULT:
Phase Shift Keying Modulation and demodulation performed using
LBRCE, ECE 93
Additional Experiments
LBRCE, ECE 94
ANALYSIS OF NOISE IN DELTA MODULATION EXPT. NO : 16
DATE :
1. AIM: Study and analysis of slope overloading and granular noise problem
in delta modulation.
 Delta modulation and demodulation trainer kit – scientech2803
 Power Supply
 Test probe
3. THEORY:
The delta modulation has two major drawbacks as under:
1. Slope overload distortion
2. Granular or idle noise
1. Slope Overload Distortion:

This distortion arises because of large dynamic range of the input signal.
Fig.1: Quantization Errors in Delta Modulation
We can observe from fig.1 , the rate of rise of input signal x(t) is so high that the
staircase signal cannot approximate it, the step size ‘Δ’ becomes too small for
staircase signal u(t) to follow the step segment of x(t). Hence, there is a large
error between the staircase approximated signal and the original input signal
x(t). This error or noise is known as slope overload distortion.
To reduce this error, the step size must be increased when slope of signal x(t) is
high.
LBRCE, ECE 95
2. Granular or Idle Noise:
Granular or Idle noise occurs when the step size is too large compared to small
variation in the input signal. This means that for very small variations in the input
signal, the staircase signal is changed by large amount (Δ) because of large
step size. Fig.1 shows that when the input signal is almost flat, the staircase
signal u(t) keeps on oscillating by ±Δ around the signal. The error between the
input and approximated signal is called granular noise.
The solution to this problem is to make the step size small.
Solution:
In order to overcome the quantization errors due to slope overload and granular
noise, the step size (Δ) is made adaptive to variations in the input signal x(t).
Particularly in the steep segment of the signal x(t), the step size is increased.
And the step is decreased when the input is varying slowly.
This method is known as Adaptive Delta Modulation (ADM).
LBRCE, ECE 96
5. PROCEDURE:
Step 1 : Connect and switch on the Power Supply of Scientech 2803.
Step 2 : Select either internal mode or external mode for source

signal using switch at Signal Generator.
 If External Mode is selected:
Onboard signal type and signal frequency will be deactivated
 If Internal Mode is selected:
Step 2.1: Select square, Arbitrary1 and Arbitrary2 as input signal

type using push button. And respective LED will glow.
Observe the input signal on test point (TP1).
Step 2.2 : Select input signal frequency using push button i.e.
500Hz, 1 KHz, 1.5 KHz, 2 KHz and 3 KHz. Observe the
change in frequency on test point (TP1).
Step 3 : Delta Modulator is by default condition when switch on

the Power Supply of ST 2803 and LED of TP2 will glow.
Step 4 : Select Sampling Frequency to observe effects of

different sampling frequency on output.
Step 5 : Select Gain Control to observe effects of different step

size on integrator output.
6. OBSERVATIONS:
 Observe the input signal at TP1 by varying input signal type

and frequency on the oscilloscope screen.
 Observe the same input signal at TP2.
 Observe the sampled clock at TP3 and sampled
signal at TP4 by varying sampling frequency through
push button.
 Observe the integrator output at TP5 by varying step size
using gain control push button.
 Observe the slope overloading and granular noise by
comparing the signal of TP2 and TP5.

LBRCE, ECE 97



LBRCE, ECE 98


7. RESULT:
Thus, the slope overload and granular noise in delta modulation are analyzed
and waveforms are observed.
8. VIVA QUESTIONS:
1. Why slope overload occurs in delta modulation and what is the condition?
2. What are the drawbacks of Delta modulation?
3. How to eliminate slope overload and granular noise in delta modulation.
4. What are the advantages of delta modulation compared to PCM?
LBRCE, ECE 99
QUADRATURE PHASE SHIFT KEYING EXPT. NO : 17
DATE :
1. AIM: Study and analysis of QPSK Modulation.

 QPSK modulation and demodulation trainer kit - Scientech2808
 Power Supply
 Test probe
3. THEORY:
Quadrature Phase Shift Keying or Quadrature PSK as it is sometimes called,
is another form of angle-modulated, constant-amplitude digital modulation.
QPSK is an M-ary encoding scheme where N=2 and M=4(hence, the name
“quaternary” meaning “4”). With QPSK, four output phases are possible for a
single carrier frequency. Because the digital input to a QPSK modulator is a
binary signal, to produce four different input combinations, the modulator
requires more than a single input bit to determine the output condition.
QPSK involves the splitting of a data stream mk (t)=m0,m1,m2, . . ., into an

in-phase stream or Even data mI (t) = m0,m2,m4, . . . and a quadrature
stream or Odd data mQ(t) = m1,m3,m5, . . .. Both the streams have half the
bit rate of the data stream mk(t), and modulate the cosine and sine functions
of a carrier wave simultaneously. As a result, phase changes across intervals
of 2Tb, where Tb is the time interval of a single bit (mk (t). The phase
transitions can be as large as ±180. Sudden phase reversals of ±180 can
throw the amplifiers into saturation. The phase reversals of ±180 cause the
envelope to go to zero momentarily. This may make us susceptible to non-
linearity in amplifier circuitry. The above may be prevented using linear
amplifiers but they are more expensive and power consuming. A solution to
the above mentioned problem is the use of OQPSK. The two bit streams
generated from 1/2bit encoding technique are used as I channel data and Q
channel data respectively for modulation of Cosine and Sine wave.
LBRCE, ECE 100
Phase relation between I & Q channel data and carrier phase.
Channel Data Carrier Phase

Q-Data I-Data I Q
0 0 0º 225º
1 0 90º 315º
1 1 180º 45º
0 1 270º 315º
QPSK modulator block diagram:
QPSK Constellation Diagram:
Quadrature Phase Shift Keying Demodulator:

The incoming modulated signal is multiplied with the cosine and the sine
signal generated from the NCO. The output of the multiplier contains high
(fin+ fnco) and low (fin-fnco) frequency components. Then integrator integrate
the gain of signal and then with the help of comparator input signal is
received on I and Q channel of demodulator. Then this data form I and Q
channel is give to parallel to serial converter to give original data.
LBRCE, ECE 101

LBRCE, ECE 102

5. PROCEDURE:
Step 1 : Connect and switch on the Power Supply of Scientech 2808
Step 2 : Quadrature Phase Shift Keying Modulator is selected by default

and LEDs of corresponding technique will glow when user switch
on the power.
Step 3 : Select bit pattern using push button i.e. 8 bit, 16 bit, 32 bit and 64
bit. And respective LED will glow. Observe the bit pattern on test
point (TP2).
Step 4 : Select data rate using push button i.e. 2 KHz, 4 KHz, 8 KHz
and 16 KHz. Observe the change in frequency on test point (TP1).

6. OBSERVATIONS:
 Observe the input bit pattern at TP2 by varying bit pattern using
respective push button.
 Observe the data rate at TP1 by varying data rate using push button.
 Observe the 2-bit encoding i.e., I-Channel (TP3) and Q-Channel (TP4).
 Observe Carrier Signal i.e., Sine (TP6) and Cosine (TP5), Frequency of
Carrier signal will change w.r.t data rate.
 Observe I-Channel (TP7) and Q-Channel (TP8) Modulated Signal.
 Observe QPSK Modulated Signal at TP9.
LBRCE, ECE 103

7. RESULT:
Thus, the QPSK generation is performed and waveforms are observed.
8. VIVA QUESTIONS:
1. What is the bandwidth of QPSK signal?
2. How many bits are used for each symbol in QPSK?
3. Write the expression for QPSK modulated signal.
4. What are the advantages of QPSK compared to ASK, PSK, and FSK
LBRCE, ECE 104

LBRCE, ECE 105
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TIME DIVISION MULTIPLEXING EXPT.

2. COMPONENTS & TOOLS REQUIRED:

 TDM Trainer kit

TDM is used for transmitting several analog message signals over a

Function Transmitter Receiver TDM

1. CH0 Modulating frequency : ----------------

The 4-channel analog multiplexing and de-multiplexing techniques is done

9. VIVA -VOCE QUESTIONS:

1. What is the working principle of TDM?

2. COMPONENTS & TOOLS REQUIRED:

 PCM modulator and De-modulator kit

In PCM a message signal is represented by a sequence of coded pulse which is

1. Keep mode switch in fast position.

1. Amplitude of modulating signal :_______________

The pulse code modulation and demodulation is performed

9. VIVA -VOCE QUESTIONS:

2. COMPONENTS & TOOLS REQUIRED:

1. Amplitude of modulating signal : _______________

The differential pulse code modulation and demodulation is performed

9. VIVA -VOCE QUESTIONS:

1. AIM: To perform Delta modulation and observe the waveforms

2. COMPONENTS AND TOOLS REQUIRED:

Step1 : Connect and switch on the Power Supply of Scientech2803.

* Note: Press reset button when make any change

 Observe the same input signal atTP2.

 Check for loose contacts of wires and components.

 Keep all the control knobs in the minimum position.

 Adjust the control knobs smoothly.

1. Compare DPCM, PCM & Delta modulation.

2. How to reduce the quantization noise that occurs in DM?

3. Mention the applications of DM.

4. What are the drawbacks of the delta modulation?

1. AIM: To perform Delta Demodulation and observe the waveforms.

 Check for loose contacts of wires and components.

 Keep all the control knobs in the minimum position.

 Adjust the control knobs smoothly.

1. AIM: To perform Adaptive Delta modulation and observe output waveforms.

 Adaptive delta modulation and demodulation trainer kit – Scientech2803

 Observe the same input signal atTP19.

 Observe the step register output at TP23 andTP26.

 Observe the accumulator output at TP22 and TP27.

 Check for loose contacts of wires and components.

 Keep all the control knobs in the minimum position.

 Adjust the control knobs smoothly.

1. What is Adaptive Delta modulation and what are the advantages?

2. Distinguish between DM and ADM.

3. How slope overload distortion is reduced in ADM?

2. COMPONENTS AND TOOLS REQUIRED:

 Adaptive delta modulation and demodulation trainer kit – Scientech2803

 Observe the same input signal atTP19.

 Observe the step register output at TP23 andTP26.

 Observe the accumulator output at TP22 and TP27.

 Observe the output of Adaptive Delta Demodulator at TP27 changing different

Input Signal Input Signal Sampling Demodulated output

CH1: CDR Output (TP16),

 Check for loose contacts of wires and components.

 Keep all the control knobs in the minimum position.

 Adjust the control knobs smoothly.

1. What is Adaptive Delta modulation and what are the advantages?

2. Distinguish between DM and ADM in terms of demodulation process.

1. AIM: Study and analysis of ASK modulator.

 ASK modulation and demodulation trainer kit- Scientech2807

for logic0 equation reduces to