Microprocessors & Interfaces-CompleteNotes PDF

MICROPROCESSOR & INTERFACES
(CSE & IT SEM -V)
Prepared By:
SUDHA NAIR
LECTURER(E&TC)
R.C.E.T,BHILAI.
MYcsvtu Notes Rungta College of Engg. & Technology 1
UNIT- I
Microprocessor Architecture

Introduction to Microprocessors

What is a microprocessor?
 A microprocessor is a programmable digital electronic

component that incorporates the functions of a central
processing unit or CPU on a single semi conducting
integrated circuit.
 One or more typically serve as the CPU in computer

systems, embedded devices, or handheld devices.

What is a microprocessor?
 That means your laptop at home and the PC in your

computer lab!
 The advent of the microprocessor astounded many

people.
 It was an entire computation engine on one tiny chip.

Going from the ENIAC which filled an entire room and
used over 18,000 vacuum tubes to a 1/8th by 1/6th of an
inch (fingernail size) mega chip!

The First Microprocessor: Intel 4004
 Transistor count
 Today's Intel® Core™2 Duo processors contain over
291 million transistors.
 This is 100,000 times the number of transistors than

were in the 4004, which had 2,300 transistors when it
was introduced in 1971.

 A human hair
The Intel 4004 microprocessor circuit line width was 10
microns or 10,000 nanometers.
 Today Intel's microprocessors have circuit line widths
of .065 microns or 65 nanometers.
 A nanometer is one billionth of a meter.
 By comparison, a human hair is approximately 100
microns or 100,000 nanometers.

 Manufacturing
 The Intel 4004 microprocessor was produced on 2" wafers

initially and then on 3" wafers.
 Today's microprocessors are produced on 12" or 300mm
wafers.

 The Intel 4004 microprocessor is unique in that, if it is

not the smallest, it is one of the smallest microprocessor
designs that ever went into commercial production.
 The 4004 microprocessor is composed of 5 layers.

Intel 4004

Who invented the microprocessor and
when?
 In November 1971, a company called Intel, which we
are all familiar with today, is given most of the credit for
inventing the first microprocessor (Intel 4004).

Who invented the microprocessor and
when?
 Three Intel engineers named Federico Faggin, Ted
Hoff and Stan Mazor are said to be the brilliant
minds behind the microprocessor.


Why was the microprocessor invented?
 The microprocessor reduced the word size of the CPU

from 32 bits to 4 bits so that the transistors of its logic
circuits would fit onto a single part.
 Before the microprocessor, electronic CPUs were

typically made of big discrete switching devices
containing only a few transistors.

 The microprocessor greatly reduced the cost of
processor power and the physical size of the CPU.
 The evolution of microprocessors has been known to

follow Moore‟s Law which states that the complexity of
an integrated circuit, with respect to minimum
component cost, doubles every 24 months.

 This has held true throughout the years……………….

……………………….
ever since the microprocessor was created.

The “building block”
 Microprocessors forever changed the way that

computing systems are made.
 This breakthrough invention powered the calculator and

paved the way for embedding intelligence in inanimate
objects as well as the personal computer.

Applications of microprocessors
 Without this amazing invention, we would not be as

technologically advanced in computers as we have
become today.
 Embedded intelligence brought by microprocessors

Microprocessor’s interference in day to
day life……

Automation

Communication

Brief history of microprocessor
 Intel i4004 processor
 Identification
 Model name: i4004.
Supplier: Intel.
Component class: CPU.

Intel i4004 processor
 Architecture
 4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data
(Harvard architecture).

 Physics
 Manufacturing technology: PMOS.
 Number of transistors: 2250.
 Die size: 24 mm2.
 Packaging: 16 pin CerDIP.
 Dates
 Introduction date: 1970.
 First microprocessor ever built.

 Identification
Supplier: Intel.
 Compatibility
 Intel i4004 CPU with extra features:
 more instructions,
 interrupt support.

 Architecture
 4 bit data bus.


 Physics
 Manufacturing technology: PMOS
 Dates
 Introduction date: 1972

 Identification
Supplier: Intel.

 Architecture
 8 bit data bus.
 Clock speed300 kHz

 Physics
 Manufacturing technology: PMOS.
 Number of transistors: 3300.
 Dates
 Introduction date: April 1972.

Intel i8080/i8080A processor
 Identification
 Model name: i8080/i8080A.
Supplier: Intel.
 Generation
 Generation: 8080.
 Compatibility
 Intel i8008 CPU with stack.

Intel i8080/i8080A processor
 Architecture
 8 bit data bus.
16 bit address bus.
 Physics
 Introduction date: April 1974.

Intel i8085A/i8085AH processor
 Identification
 Model name: i8085A/i8085AH.
Supplier: Intel.
 Generation
 Generation: 8080.
 Compatibility
 Intel i8080 CPU upward instruction compatible.

 Extra instructions:
 SIM (Set Interrupt Mask)
 RIM (Read Interrupt Mask)
 Extra interrupt lines, including NMI (Non-Maskable
Interrupt).

 Architecture
 8 bit data bus.
16 bit address bus.
Data and address bus are multiplexed.
Separate address space for instructions and data .

 Clock speed
Clock Model Manufactu
speed ring
technolog
y
 Physics 3 MHz Intel I8085a NMOS
 Number of transistors: Intel

iM8085A
NMOS
6200. 5 MHz Intel

i8085AH-2
HMOS
 Packaging: 40 pin 6 MHz Intel HMOS

i8085AH-1 HMOS
CerDIP. Intel
iM8085AH

Major designers
 Intel
 Advanced Micro Devices (AMD)
 IBM Microelectronics
 AMCC
 Freescale Semiconductor
 ARM Holdings

Major designers
 MIPS Technologies
 Texas Instruments Semiconductors
 Renesas Technology
 VIA Technologies
 Western Design Center
 STMicroelectronics
 Sun Microsystems
 CPU Tech

Microprocessor based system

 The typical processor system consists of:

 CPU (central processing unit)
 ALU (arithmetic-logic unit)
 Control Logic
 Registers, etc…
 Memory
 Input / Output interfaces

 Interconnections between these units:

 Address Bus
 Data Bus
 Control Bus

Basic definitions
Bus: A shared group of wires used for communicating

signals among devices
 address bus: the device and the location within the
device that is being accessed
 data bus: the data value being communicated
 control bus: describes the action on the address
and data buses

Basic definitions
Memory: Where instructions (programs) and data are

stored-
 Organized in arrays of locations (addresses), each
storing one byte (8 bits) in general
 A read operation to a particular location always
returns the last value stored in that location

Basic definitions

Basic definitions
 Semiconductor Memories are classified according to
the type of data storage and the type of data access
mechanism into the following two main groups:
 Non-volatile Memory (NVM) also known as Read-Only

Memory (ROM) which retains information when the
power supply voltage is off.
 With respect to the data storage mechanism NVM are
divided into the following groups:

Basic definitions
 Mask programmed ROM. The required contents of
the memory is programmed during fabrication.
 Programmable ROM (PROM). The required contents

is written in a permanent way by burning out internal
interconnections (fuses). It is a one-off procedure.

Basic definitions
 Erasable PROM (EPROM). Data is stored as a charge

on an isolated gate capacitor (“floating gate”). Data is
removed by exposing the PROM to the ultraviolet light.
 Electrically Erasable PROM (EEPROM) also known
as Flash Memory. It is also based on the concept of the
floating gate. The contents can be re-programmed by
applying a suitable voltages to the EEPROM pins.

Basic definitions
 Read/Write (R/W) memory, also known as Random
Access Memory (RAM). From the point of view of the
data storage mechanism RAM are divided into two main
groups:
 Static RAM, where data is retained as long as there is

power supply on.
 Dynamic RAM, where data is stored on capacitors and

requires a periodic refreshment.

Basic definitions
I/O devices:
 Enable system to interact with the world.
 Interface between the computer and other

peripherals or human.

Basic definitions
 Can be classified by:

 Type of data stream:
Serial or parallel
 Type of interaction with the processor:
Programmed I/O, Interrupt Driven, or DMA
 Type of connection to the processor:
Memory-mapped I/O or I/O-mapped I/O

Basic microprocessor architecture
 A microprocessor consists of:

 ALU – performs arithmetic and logic calculation
 Registers – temporarily store data
 Control Unit – Synchronizes the operations of all
components

8085 Microprocessor-Features
 The Intel 8085 microprocessor is an NMOS 8-bit device.
 Sixteen address bits provide access to 65,536 bytes of

8 bits each.
 Eight bi-directional data lines provide access to a

system data bus.

 Control is provided by a variety of lines which support

memory and I/O interfacing, and a flexible interrupt
system.
 The 8085 provides an upward mobility in design from
the 8080 by supporting all of the 8080‟s instruction set
and interrupt capabilities.
 It requires only a 5 volt supply. In addition, the 8085 is
available in two clock speeds.

 The 8085 comes in two models, the 8085A and the

8085A-2.
 8085A -clock frequency of 3 MHz (single phase square
wave. )
 8085A-2 - clock frequency of 5 MHz. (single phase
square wave. )
 This single clock is generated within the 8085 itself,
requiring only a crystal externally.

 The 8085 supports the interrupt structure of the 8080.

 Includes the RST instruction and the eight vectors.
 Has additional four more interrupts(3 masked and use
vector areas between the existing ones of the 8080.)

 The 8085 has two pins dedicated to the generation or

reception of serial data. (allow the MP to send and
receive serial bits with a large software program. Hence
8085 is useful as a complete control device for remote
control applications.)
 The 8085 supports the entire 8080 instruction set. In
addition, two new instructions are added- RIM and SIM.

 Unlike the 8080 , 8085 makes use of multiplexing of the

lower 8 bits of the address with the data bits on the
same 8 pins.
 The 8085 has many new support devices to ease
design work.
 These include the 8259 Programmable Interrupt
controller, the 8202 Dynamic RAM controller, several
new I/O devices with various amounts of RAM, ROM,
parallel I/O and timer-counters.

8085 Microprocessor Architecture
 Internal architecture description

 Control Unit
 Generates signals within microprocessor to carry out
the instruction, which has been decoded.

Internal architecture description
 Arithmetic Logic Unit

 The ALU performs the actual numerical and logic
operation such as „add‟, „subtract',' AND‟, „OR‟, etc.
 Uses data from memory and from Accumulator to
perform arithmetic.
 Always stores result of operation in Accumulator

 Registers
 The 8085/8080A-programming model includes six

registers, one accumulator, and one flag register.
 In addition, it has two 16-bit registers:
the stack pointer and the program counter.

 The 8085/8080A has six general-purpose registers to

store 8-bit data; these are identified as B,C,D,E,H, and
L. They can be combined as register pairs - BC, DE,
and HL - to perform some 16-bit operations.
 The programmer can use these registers to store or
copy data into the registers by using data copy
instructions.

 Accumulator
 The accumulator is an 8-bit register that is a part of
arithmetic/logic unit (ALU).
 This register is used to store 8-bit data and to perform
arithmetic and logical operations.
 The result of an operation is stored in the accumulator.
The accumulator is also identified as register A.

 Flags
 The ALU includes five flip-flops, which are set or reset

after an operation according to data conditions of the
result in the accumulator and other registers.
 They are called Zero (Z), Carry (CY), Sign (S), Parity
(P), and Auxiliary Carry (AC) flags.

 The most commonly used flags are Zero, Carry, and

Sign. The microprocessor uses these flags to test data
conditions.
 For example, after an addition of two numbers, if the
sum in the accumulator is larger than eight bits, called
the Carry flag (CY) is set to one.
 When an arithmetic operation results in zero, the flip-
flop called the Zero (Z) flag is set to one.

 The 8-bit register, called the flag register is adjacent to

the accumulator.
 However, it is not used as a register; five bit positions

out of eight are used to store the outputs of the five flip-
flops.

 The flags are stored in the 8-bit register so that the

programmer can examine these flags (data conditions)
by accessing the register through an instruction

 These flags have critical importance in the decision-

making process of the microprocessor.
 The conditions (set or reset) of the flags are tested

through the software instructions.
 For example, the instruction JC (Jump on Carry) is

implemented to change the sequence of a program
when CY flag is set.

 Program Counter (PC)
 This 16-bit register deals with sequencing the execution

of instructions.
 This register is a memory pointer. Memory locations
have 16-bit addresses, and that is why this is a16-bit
register.
 The microprocessor uses this register to sequence the
execution of the instructions.

 Program Counter (PC)
 The function of the program counter is to point to the

memory address from which the next byte is to be
fetched.
 When a byte (machine code) is being fetched, the

program counter is incremented by one to point to the
next memory location

 Stack Pointer (SP)
 The stack pointer is also a 16-bit register used as a

memory pointer.
 It points to a memory location in R/W memory, called
the stack.
 The beginning of the stack is defined by loading 16-bit
address in the stack pointer.

 Instruction register & Decoder

 An Instruction Register and decoder system interpret
the programmer‟s instructions and implement them via
nano code.
 Temporary store for the current instruction of a
program. Latest instruction sent here from memory prior
to execution. Decoder then takes instruction and
„decodes‟ or interprets the instruction.
 Decoded instruction then passed to next stage.

Programming model of 8085

8085 System Bus
 A typical microprocessor communicates with memory

and other devices (input and output) using three
busses:
 Address Bus
 Data Bus and
 Control Bus.

8085 System Bus
 Address Bus:
 One wire for each bit, therefore 16 bits = 16 wires.

 Address Bus consists of 16 wires, therefore 16 bits.
 Its "width" is 16 bits.

8085 System Bus- Address Bus
 A 16 bit binary number allows 216 different numbers, or

32000 different numbers, ie 0000000000000000 up to
1111111111111111.
 Because memory consists of boxes, each with a unique

address, the size of the address bus determines the
size of memory, which can be used.

 To communicate with memory the microprocessor
sends an address on the address bus, eg
0000000000000011 (3 in decimal), to the memory.
 The memory the selects box number 3 for reading or

writing data.
 Address bus is unidirectional, ie numbers only sent from

microprocessor to memory, not other way.

 Question?: If you have a memory chip of size 256

kilobytes (256 x 1024 x 8 bits), how many wires does
the address bus need, in order to be able to specify an
address in this memory?

8085 System Bus
 Data Bus:
 Data Bus: carries „data‟, in binary form, between

microprocessor and other external units, such as
memory.
 Typical size is 8 or 16 bits.

8085 System Bus -Data Bus
 The Data Bus typically consists of 8 wires. Therefore,

28 combinations of binary digits.
 Data bus used to transmit "data“ , ie information, results

of arithmetic, etc, between memory and the
microprocessor.

 Bus is bi-directional.
 Size of the data bus determines what arithmetic can be
done.
 If only 8 bits wide then largest number is 11111111 (255
in decimal).
 Therefore, larger number have to be broken down into
chunks of 255.
 This slows microprocessor.

 Data Bus also carries instructions from memory to the

microprocessor.
 Size of the bus therefore limits the number of possible

instructions to 256, each specified by a separate
number.

8085 System Bus
 Control Bus:
 Control Bus are various lines which have specific

functions for coordinating and controlling
microprocessor operations.
 Eg: Read/Not Write line, single binary digit.

8085 System Bus
 Control whether memory is being „written to‟ (data

stored in memory) or „read from‟ (data taken out of
memory) 1 = Read, 0 = Write.
 May also include clock line (s) for timing/synchronizing,

„interrupts‟, „reset‟ etc.
 Cannot function correctly without these vital control

signals.

8085 System Bus- Control Bus
 The Control Bus carries control signals partly

unidirectional, partly bi-directional.
 Control signals are things like "read or write". This tells

memory that we are either reading from a location,
specified on the address bus, or writing to a location
specified.

8085 System Bus- Control Bus
 In the microprocessor the three busses are external to

the chip (except for the internal data bus).
 In case of external busses, the chip connects to the
busses via buffers, which are simply an electronic
connection between external bus and the internal data
bus.

Example: Memory Read Operation

Example: Instruction Fetch Operation
 Instructions (program steps) are stored in memory.
 To run a program, the individual instructions must be

read from the memory in sequence, and executed.
 Program counter puts the 16-bit memory address of

the instruction on the address bus.

Instruction Fetch Operation
 Control unit sends the Memory Read Enable signal

to access the memory.
 The 8-bit instruction stored in memory is placed on

the data bus and transferred to the instruction
decoder.
 Instruction is decoded and executed.



De multiplexing Address & Data Lines
 From the above description, it becomes obvious that

the AD7– AD0 lines are serving a dual purpose and
that they need to be demultiplexed to get all the
information.
 The high order bits of the address remain on the bus
for three clock periods. However, the low order bits
remain for only one clock period and they would be
lost if they are not saved externally. Also, notice that
the low order bits of the address disappear when
they are needed most.

De multiplexing Address & Data Lines
 To make sure we have the entire address for the full

three clock cycles, we will use an external latch to
save the value of AD7– AD0 when it is carrying the
address bits. We use the ALE signal to enable this
latch.
 Given that ALE operates as a pulse during T1, we
will be able to latch the address. Then when ALE
goes low, the address is saved and the AD7– AD0
lines can be used for their purpose as the bi-
directional data lines.
Demultiplexing Address & Data Lines

Generating Control Signals
 The 8085 generates a single RD signal. However, the

signal needs to be used with both memory and I/O. So,
it must be combined with the IO/M signal to generate
different control signals for the memory and I/O.
 Keeping in mind the operation of the IO/M signal we
can use the following circuitry to generate the right
set of signals:

Generating Control Signals

8085 Functional Block Diagram

8085 Pin description

 Pin Description
 ADDRESS LINES A8 - A15:

 These tri state lines are outbound only.
 They provide the upper 8 bits of the 16-bit-wide address
which identifies one unique 8-bit byte within the MP‟s
address space, or the 8-bit address of an I/O device.
 Sixteen address lines provide an address space of
65,536 locations.

 ADDRESS-DATA LINES AD0 - AD7:
 These tri state lines may by either inbound or outbound.

 They provide a multiplexing between the lower 8 bits of
the 16-bit-wide address early in a machine cycle and 8
data bits later in the cycle.

 ADDRESS-DATA LINES AD0 - AD7:

 When containing addresses, these lines are outbound
only; when containing data, they may be either inbound
or outbound, depending upon the nature of the machine
cycle.
 They also will contain the 8 bits of an I/O device

address during an I/O operation.

 ALE Address Latch Enable:
 It occurs during the first clock cycle of a machine state
and enables the address to get latched into the on chip
latch of peripherals.
 The falling edge of ALE is set to guarantee setup and

hold times for the address information.
 ALE can also be used to strobe the status information.

 ALE is never 3stated .
 This signal appears outbound early in a machine cycle

to advise the external circuitry that the AD0 - AD7 lines
contain the lower 8 bits of a memory address.

 It should be used to clock a catch-and-hold circuit such
as a 74LS245 or 74LS373, so that the full address will
be available to the system for the rest of the machine
cycle.
 The falling edge of ALE is the point at which the signals

on the AD lines, as well as the S0, S1, and I-O/M lines
will be stable and may be taken by the external circuitry.

 STATUS LINES S0, S1, & I-O/M:

 These three status lines serve to indicate the general
status of the processor with respect to what function the
MP will perform during the machine cycle.
 The S0 and S1 lines are made available for circuits
which need advanced warning of the ensuing operation,
such as very slow RAM or other specialized devices.

 STATUS LINES S0, S1, & I-O/M:
 The system may not normally need to monitor these

lines. The I-O/M line approximates in one line what the
S0 and S1 lines do in two.
 It indicates whether the operation will be directed

toward memory (line is low), or toward I/O (line is high).

 Data Bus Status. Encoded status of the bus cycle:

 S1 S0 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
 S1 can be used as an advanced R/W status.

 READ & WRITE (/RD & /WR):
 These lines indicate which direction the MP expects to

pass data between itself and the external data bus.
 These lines also serve to time the event, as well as
identify its direction.

 READ & WRITE (/RD & /WR):

 RD -READ; indicates the selected memory or 1/0
device is to be read and that the Data Bus is available
for the data transfer.
 WR-WRITE; indicates the data on the Data Bus is to be

written into the selected memory or I/O location. Data is
set up at the trailing edge of WR. 3stated during Hold
and Halt modes.

 READY :
 If Ready is high during a read or write cycle, it indicates

that the memory or peripheral is ready to send or
receive data.
 If Ready is low, the CPU will wait for Ready to go high
before completing the read or write cycle.

 This is an input line which may be used as a signal from

external RAM that a wait state is needed, since the
RAM is not able to provide the data or accept it in the
time allowed by the MP.
 The negation of Ready, by being pulled low, will cause

the 8085 to enter wait states.

 HOLD :
 These lines provide the 8085 with a DMA capability by
allowing another processor on the same system buses
to request control of the buses.
 It indicates that another Master is requesting the use of
the Address and Data Buses.
 The CPU, upon receiving the Hold request. will
relinquish the use of buses as soon as the completion
of the current machine cycle.

 HOLD :
 Internal processing can continue.
 Upon receipt of HOLD, the „ 85 will tri state its address,
data, and certain control lines, then generate HLDA.
 This signals the other processor that it may proceed.
 The „85 will remain off the buses until HOLD is negated.

 During this cycle a RESTART or CALL instruction can

be inserted to jump to the interrupt service routine.
 The INTR is enabled and disabled by software.
 The processor can regain the buses only after the Hold
is removed.
 When the Hold is acknowledged, the Address, Data,
RD, WR, and IO/M lines are 3stated.

 HLDA :
 HOLD ACKNOWLEDGE- indicates that the CPU has
received the Hold request and that it will relinquish the
buses in the next clock cycle.
 HLDA goes low after the Hold request is removed.
 The CPU takes the buses one half clock cycle after
HLDA goes low.

 INTR :
 INTERRUPT REQUEST:
 This line provides a vectored interrupt capability to the
8085.
 Upon receipt of INTR, the „85 will complete the

instruction in process, then generate INTA as it enters
the next machine cycle.

 INTR :
 The interrupting device will jam a Restart (RST)
instruction onto the data bus, which the „85 uses to
locate an interrupt vector in low RAM. is used as a
general purpose interrupt.
 It is sampled only during the next to the last clock cycle

of the instruction.

 INTR :
 If it is active, the Program Counter (PC) will be inhibited
from incrementing and an INTA will be issued.
 It is disabled by Reset and immediately after an

interrupt is accepted.

 INTA :
 INTERRUPT ACKNOWLEDGE- is used instead of (and
has the same timing as) RD during the Instruction cycle
after an INTR is accepted.
 It can be used to activate the 8259 Interrupt chip or

some other interrupt port.

 RST 5.5, 6.5, 7.5:
 These three lines are additional interrupt lines which

generate an automatic Restart, without jamming, to
vectors in low RAM which are between those used by
the normal INTR instruction.

 RST 5.5, 6.5, 7.5:

 The 5.5 line, for example, will cause an automatic
restart to a 4-byte vector located between 5 and 6 of the
normal vectors used by INTR.
 These lines have priority over the INTR line, and each
other.

 RST 5.5, 6.5, 7.5:

 They also have certain electrical characteristics for
assertion, and may be masked off or on by software.
 These three inputs have the same timing as

INTR except they cause an internal RESTART to be
automatically inserted.

 RST 7.5 - Highest Priority
 RST 6.5
 RST 5.5 - Lowest Priority
 The priority of these interrupts is ordered as shown

above.
 These interrupts have a higher priority than the INTR

 TRAP:
 This is an un maskable interrupt with a fixed vector in

low RAM.
 Trap interrupt is a non maskable restart interrupt.
 It is recognized at the same time as INTR.
 It is unaffected by any mask or Interrupt Enable. It has
the highest priority of any interrupt

 RESET IN :
 These lines provide for both MP and system reset.
 The reset circuitry in the 8224, used with the 8080, has
been brought inside the MP.
 The RESET IN line is generated asynchronously by
some sort of external circuit, such as an RC network or
Reset switch.

 RESET IN :
 Upon receipt of this signal, the „85 will internally
synchronize the Reset with the clock of the processor,
then generate RESET OUT for other devices in the
system.
 Reset sets the Program Counter to zero and resets the
Interrupt Enable and HLDA flip flops.

 RESET IN :
 None of the other flags or registers (except the
instruction register) are affected.
 The CPU is held in the reset condition as long as Reset

is applied.

 RESET OUT:
 Indicates CPU is being reset.

 Can be used as a system RESET.
 The signal is synchronized to the processor clock.

 X1, X2 :
 Crystal or R/C network connections to set the internal
clock generator.
 The input frequency is divided by 2 to give the internal
operating frequency.
 These two pins provide connection for an external
frequency determining circuit to feed the 8085‟s clock.

 X1, X2 :
 This is normally a crystal, although other resonant
circuits may be used. X1 alone may be used as a single
input from an external oscillator.
 The internal oscillator of the „85 will divide the frequency

by two for the system clock.

 CLK :
 Clock Output for use as a system clock when a crystal
or R/ C network is used as an input to the CPU.
 The period of CLK is twice the X1, X2 input period.
 This line provides a system clock signal to external
circuits which need to be in synchronization with the
MP.

 IO/M :
 IO/M indicates whether the Read/Write is to memory or

l/O.
 Tri stated during Hold and Halt modes

 SID:
 Serial input data line .
 The data on this line is loaded into accumulator bit 7

whenever a RIM instruction is executed.

 SOD :
 Serial output data line.
 The output SOD is set or reset as specified by the SIM

instruction.

 SID and SOD:

 These two lines provide for a single serial input or
output line to/from the 8085.
 These lines are brought into the device as D7, and may
be tested or set by the Read Interrupt Mask (RIM) or
Set Interrupt Mask (SIM) instructions.

 SID and SOD:

 These two instructions also have control over the mask
which controls the RST 5.5, 6.5, and 7.5, and TRAP,
interrupts.
 The SID and SOD lines are simple single bit I/O lines;
any timing required to provide external communication
via them must be provided by the software.

 Vcc:
+5 volt supply.
 Vss:
Ground Reference.

8085 Functional Description
 The 8085A is a complete 8 bit parallel central
processor.
 It requires a single +5 volt supply.
 Its basic clock speed is 3 MHz thus improving on the

present 8080's performance with higher system speed.

 Also it is designed to fit into a minimum system of three

IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO
chip
 The 8085A uses a multiplexed Data Bus.
 The address is split between the higher 8bit Address

Bus and the lower 8bit Address/Data Bus.

 During the first cycle the address is sent out.
 The lower 8bits are latched into the peripherals by the

Address Latch Enable (ALE).

 During the rest of the machine cycle the Data Bus is

used for memory or I/O data.
 The 8085A provides RD, WR, and IO/Memory signals

for bus control.
 An Interrupt Acknowledge signal (INTA) is also

provided. Hold, Ready, and all Interrupts are
synchronized.

 The 8085A also provides serial input data (SID) and

serial output data (SOD) lines for simple serial interface.
 In addition to these features, the 8085A has three

maskable, restart interrupts and one non-maskable trap
interrupt. The 8085A provides RD, WR and IO/M
signals for Bus control.

 Status Information:
 Status information is directly available from the 8085A.
 ALE serves as a status strobe.
 The status is partially encoded, and provides the user

with advanced timing of the type of bus transfer being
done.

 Status Information
 IO/M cycle status signal is provided directly also.
 Decoded So, S1 Carries the following status

information:
 HALT, WRITE, READ, FETCH

 Status Information
 S1 can be interpreted as R/W in all bus transfers. In the
8085A the 8 LSB of address are multiplexed with the
data instead of status.
 The ALE line is used as a strobe to enter the lower half
of the address into the memory or peripheral address
latch.
 This also frees extra pins for expanded interrupt
capability.

 Interrupt and Serial l/O

 The 8085A has5 interrupt inputs: INTR, RST5.5,
RST6.5, RST 7.5, and TRAP.
 INTR is identical in function to the 8080 INT.
 Each of the three RESTART inputs, 5.5, 6.5,7.5 has a
programmable mask.
 TRAP is also a RESTART interrupt except it is non
maskable.

 Interrupt and Serial l/O
 The three RESTART interrupts cause the internal
execution of RST (saving the program counter in the
stack and branching to the RESTART address) if the
interrupts are enabled and if the interrupt mask is not
set.
 The non-maskable TRAP causes the internal execution

of a RST independent of the state of the interrupt
enable or masks.

 The interrupts are arranged in a fixed priority that
determines which interrupt is to be recognized if more
than one is pending as follows:
 TRAP highest priority, RST 7.5,RST 6.5, RST 5.5, INTR

lowest priority.
 This priority scheme does not take into account the

priority of a routine that was started by a higher priority
interrupt.

 RST 5.5 can interrupt a RST 7.5 routine if the interrupts
were re-enabled before the end of the RST 7.5 routine.
 TRAP:
 The TRAP interrupt is useful for catastrophic errors
such as power failure or bus error.
 The TRAP input is recognized just as any other interrupt
but has the highest priority.
 It is not affected by any flag or mask.
 The TRAP input is both edge and level sensitive.

8085 Timings
 Instruction Cycle –
 The time required by the 8085 to fetch and execute one
machine language instruction is defined as an
Instruction Cycle.
 As in the 8080, the instructions may be of different

complexities, with the result that the more complicated
instructions take longer to execute.

8085 Timings
 Instruction Cycle –
 The 8085‟s method of instruction execution inside the
MP is more organized, however, and so the time
required to execute any instruction is more predictable
and more regular.

8085 Timings
 Machine Cycle –
 Each instruction is divided into one to five Machine
Cycles.
 Each machine cycle is essentially the result of the need,
by the instruction being executed, to access the RAM.
 The shortest instruction would require just one machine
cycle, in which the instruction itself is obtained from
RAM.

8085 Timings
 The longest, of five machine cycles, would consist of
five RAM accesses, the first to obtain the instruction
byte itself, and the remaining four to be divided into
fetching and saving other bytes.
 For example, cycles numbers 2 & 3 may be needed to

fetch two more bytes of an address, while numbers 4 &
5 may be needed to save a 2-byte address somewhere
else in RAM.

8085 Timings
 The type of machine cycle being executed is specified

by the status lines I-O/M, S0, and S1, and the control
lines /RD, /WR, and /INTA.
 These six lines can define seven different machine

cycle types as follows.

Types of machine cycle
 OPCODE FETCH:
 This is the first machine cycle of any instruction.
 It is defined with S0 and S1 asserted high, and I-O/M
and /RD low.
 It is a read cycle from RAM to obtain an instruction byte.

 MEMORY READ:
 This is a normal read cycle of any byte except the OP
code.
 It is defined with S0 and S1 set to 0, 1 respectively, and
I-O/M and /RD low.
 It is a read cycle from RAM to obtain a data or address
byte.

 MEMORY WRITE:
 This is a normal write cycle to memory.
I-O/M and /WR low.
 It is a write cycle to RAM to store one byte in the
specified address

 I/O READ:
 This is a normal read cycle from an I/O device.
with I-O/M high and /RD low.
 It is a read cycle which will bring one byte into the MP
from the input device specified.

 I/O WRITE:
 This is a normal write cycle to an I/O device.
with I-O/M high and /WR low.
 It is a write cycle which will send one byte outbound
from the MP to the specified output device.

 INTERRUPT ACKNOWLEDGE:
 This is a response to an interrupt request applied to the
MP via the INTR line.
 It is defined with S0 and S1 set to 1, 1 respectively, I-
O/M set high, and both /RD and /WR also high.

 The Interrupt Acknowledge pin is also held to a low

asserted level.
 It is neither a read nor write cycle, although the
interrupting device will jam an interrupt vector onto the
D0-D7 lines on the next machine cycle.

 BUS IDLE:
 This is an idle cycle in which no specific bus activity is
defined.
 It occurs under three differently defined conditions:

8085 Timings-Special instructions
 Double Add Instruction (DAD):

 This instruction requires enough execution time to merit
its own Idle cycle.
 It is defined with S0 and S1 set to 0, 1 respectively, I-
O/M set low, and neither /RD nor /WR asserted (both
high).
 Since neither a read nor a write are specified, no bus
action takes place.

 Acknowledge of Restart or Trap:

 This idle cycle allows time for the „85 to cope with a
RST or Trap interrupt request. All bits are held high.

 Halt:
 This idle cycle indicates that the MP has executed a
Halt instruction.
 The I-O/M, /RD, and /WR lines are all tri stated, which
would allow them to be controlled by other devices.
 INTA is held inactive, but not tri stated.
 The Hold line is really the proper one to use for DMA or
multiple processors.

8085 Timings-T-states-
 T-states-
 Each of the machine cycles defined above, during
which an access of a RAM address or an I/O device is
made (except the idle cycles), is further divided into T-
states.
 Each T-state, for an „85 with a 3 MHz clock, will be
about 333 nanoseconds in length.
 The first machine cycle, during which the OP code is
being fetched, will be either 4 or 6 T-states in length.

 T-states-
 Whether 4 or 6 T-states are used depends upon
whether the instruction needs further information from
RAM, or whether it can be executed to completion
straight away .
 If multiple accesses are needed, the cycle will be 4
states long; if the execution can run to completion, 6
states are required.

 The actions of the major signals of the „85 during each

of the 10 possible types of T-states. It may be
summarized as follows:
 T1 STATE:
 This state is the first of any machine cycle.
 S0-S1 lines, I-O/M, A8-A15, and AD0-AD7 contains
whatever would be appropriate for the type of
instruction being executed.

 T1 STATE:
 The S0-S1 and I-O/M lines will define, at this early point
in the machine cycle, whether the MP is attempting to
address a RAM location or an I/O device.
 The address lines will identify the location or I/O device

to be dealt with.
.
 T1 STATE:
 The Address Latch Enable (ALE) line will allow some
sort of external circuitry to catch and hold the contents
of the AD0-AD7 lines to be used as the low byte of the
address.
 The /RD, /WR, and /INTA lines are all negated at this
time.

 T1 STATE:
 Since the AD0-AD7 lines are being used to present an
address byte, it would be inappropriate to move data on
the data bus; besides, it‟s too early to do so.
 It‟s also too early for /INTA. ALE, however, is asserted,
since this is the time that the AD0-AD7 contents will
contain the lower address byte, which must be caught
and held outside the „85 for use by the following T-
states.

 T2 STATE:
 All lines except ALE (which will be inactive for the rest
of the machine cycle) will assume the proper level for
the type of instruction in progress.
 The address lines retain the bit pattern selecting one
byte from RAM or an I/O device;
 The AD0-AD7 lines will now prepare to either accept or
present a data byte (they are in a state of transition
during T2).

 T2 STATE:
 I-O/M and the S0, S1 lines are still displaying the
original settings of T1.
 Either /RD or /WR will assert during T2, to indicate the
nature of the data transaction.
 INTA will assert at T2 if an interrupt cycle has started.

 WAIT STATE:
 If the Ready line was negated during T2, a Tw is
inserted to allow the external circuitry more time to
prepare for data transmission.
 A specific point in T2 is defined, after which a late
negation of Ready will not cause the Tw to be inserted.
 This corresponds to the same actions in the 8080
device. All signals set up during T2 will remain constant
during Tw.

 T3 STATE:
 All lines set up during T2 will remain the same in T3,
except the AD0-AD7 lines, which will be conducting
data either into or out of the 8085.
 At the end of T3, the /RD or /WR line will negate to
indicate the end of the active function.
 This will cause the data byte standing on AD0-AD7 to
disappear

 T4 - T6 STATES:
 These states are required for time to permit the 8085 to
continue processing internally.
 No bus actions are required.
 The S0 & S1 lines are both asserted, while I-O/M is

negated, which specifies that the „85 is involved in an
Opcode fetch.

 T4 - T6 STATES:
 Since T4 through T6 will exist only on the first machine
cycle of an instruction, this corresponds correctly with
the Machine Cycle chart.
 The AD0-AD7 lines are tri stated; the A8-A15 retain
their original setting; the /RD, /WR, and INTA lines are
all negated.

8085 Timings-Special conditions
 Special conditions:
 In addition to the T-states described above, there are
also various conditions during states involved in Resets,
Halts, and Holds.
 It must be kept in mind that during any of these, the MP

clocks are still running, and the „85 is alive inside; it has
simply shut itself off the buses to allow external events
to occur.

 Special conditions:
 These states tri state the address, AD, I-O/M, /RD, and
/WR lines to allow external devices to control them.
 The other lines are held at inactive levels except the S0
& S1 lines, which do indicate what type of machine
cycle the system is in, i.e., whether it is a Reset, Hold,
or Halt

 HOLD AND HALT STATES :

 The 8085 has provisions for the execution of a Halt
instruction, which causes the system to go into T-halt
states.
 During this time, the „85 is simply waiting for something
to occur.
 There are three ways out of a Halt: A Reset, a Hold
Request, and an enabled interrupt.


 If a Hold Request occurs during a Halt, the „85 will
honor it by going into T-hold cycles as long as the Hold
line remains asserted.
 It will return to the halt condition when Hold negates.
 If an interrupt occurs during a halt, the MP will go into
an interrupt cycle if the interrupt was enabled.


 It will be ignored if it was not enabled.
 An enabled interrupt during a hold state will have to wait

until the hold clears before being given control of the
system.

8085 Timings- Example
 The instruction code 0100 1111 (4FH – MOV C, A) is

stored in memory location 2005H.
 Illustrate the steps and the timing of data flow when it is
being fetched

Example Mp Communication

Timing Diagram

Some Terminologies:
 After observing timing diagram we can say,

 4FH is a one – byte instruction
 One external operation – fetching 4F from 2005H
 Entire operation needs 4 clock periods

UNIT- II
INSTRUCTION SET
&
PROGRAMMING WITH 8085

Instruction
 An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
 The entire group of instructions, called the instruction

set, determines what functions the microprocessor can
perform.
 The 8085‟s instructions are made up of bytes.

Instruction
 In microprocessor parlance, a byte is described as 8

contiguous binary bits treated as a unit.
 The least significant bit is on the right, and is labeled Bit

0.
 The most significant bit is on the left, and is Bit 7. Thus,

the machine coding is "origin zero", unless noted
otherwise.

Instruction
 Note also that there is no parity bit, or provision for it, as

would be found in larger systems.
 The 8085‟s instructions are either one, two, or three
bytes long.
 In all cases, the first byte contains the essential
information, such as the OP code.
 The second and third bytes, if included, provide
operand information that won‟t fit in the first byte.

Instruction Set Classification
 These instructions can be classified into the following
five functional categories:
 data transfer (copy) operations

 arithmetic operations,
 logical operations,
 branching operations, and
 machine-control operations.

Data Transfer (Copy) Operations
 Data Transfer (Copy) Operations
 This group of instructions copy data from a location
called a source to another location called a destination,
without modifying the contents of the source.
 In technical manuals, the term data transfer is used for
this copying function.
 The various types of data transfer (copy) are listed
below together with examples of each type:

 Copy from source to destination

 MOV Rd, Rs
 This instruction copies the contents of the source M, Rs
register into the destination register; the contents of Rd,
M the source register are not altered.
 If one of the operands is a memory location, its location
is specified by the contents of the HL registers.
 Example: MOV B, C or MOV B, M

 Move immediate 8-bit

 MVI Rd, data
 The 8-bit data is stored in the destination register or M,
data memory.
 If the operand is a memory location, its location is
specified by the contents of the HL registers.
 Example: MVI B, 57H or MVI M, 57H

 Load accumulator
 LDA 16-bit address
 The contents of a memory location, specified by a16-bit
address in the operand, are copied to the accumulator.
 The contents of the source are not altered.
 Example: LDA 2034H

 Load accumulator indirect

 LDAX B/D Reg. pair
 The contents of the designated register pair point to a
memory location. This instruction copies the contents of
that memory location into the accumulator.
 The contents of either the register pair or the memory
location are not altered.
 Example: LDAX B

 Load register pair immediate

 LXI Reg. pair, 16-bit data
 The instruction loads 16-bit data in the register pair
designated in the operand.
 Example: LXI H, 2034H or LXI H, XYZ

 Load H and L registers direct

 LHLD 16-bit address
 The instruction copies the contents of the memory
location pointed out by the 16-bit address into register L
and copies the contents of the next memory location
into register H.
 The contents of source memory locations are not
altered.
 Example: LHLD 2040H

 Store accumulator direct
 STA 16-bit address
 The contents of the accumulator are copied into the
memory location specified by the operand.
 This is a 3-byte instruction, the second byte specifies
the low-order address and the third byte specifies the
high-order address.
 Example: STA 4350H

 Store accumulator indirect
 STAX Reg. pair
 The contents of the accumulator are copied into the
memory location specified by the contents of the
operand (register pair). The contents of the accumulator
are not altered.
 Example: STAX B

 Store H and L registers direct

 SHLD 16-bit address
 The contents of register L are stored into the
memory location specified by the 16-bit address in
the operand and the contents of H register are
stored into the next memory location by
incrementing the operand.
 This is a 3-byte instruction, the second byte
specifies the low-order address and the third byte
specifies the high-order address.
 Example: SHLD 2470H
 Exchange H and L with D and E

 XCHG none
 The contents of register H are exchanged with the
contents of register D, and the contents of register L are
exchanged with the contents of register E.
 Example: XCHG

 Copy H and L registers to the stack pointer
 SPHL none
 The instruction loads the contents of the H and L
registers into the stack pointer register, the contents of
the H register provide the high-order address and the
contents of the L register provide the low-order address.
 The contents of the H and L registers are not altered.
 Example: SPHL

 Exchange H and L with top of stack

 XTHL none
 The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack
pointer register.
 The contents of the H register are exchanged with the
next stack location (SP+1); however, the contents of the
stack pointer register are not altered.
 Example: XTHL

 Output data from accumulator to a port with 8-bit

address
 OUT 8-bit port address
 The contents of the accumulator are copied into the I/O
port specified by the operand.
 Example: OUT F8H

 Input data to accumulator from a port with 8-bit

address
 IN 8-bit port address
 The contents of the input port designated in the operand
are read and loaded into the accumulator.
 Example: IN 8CH

Arithmetic instructions
 Add register or memory to accumulator

 ADD R –
 The contents of the operand (register or memory) are M
added to the contents of the accumulator and the result
is stored in the accumulator.
 All flags are modified to reflect the result of the
addition.
 Example: ADD B or ADD M
 Add register to accumulator with carry
 ADC R
 The contents of the operand (register or memory) and
M the Carry flag are added to the contents of the
accumulator
and the result is stored in the accumulator.
 All flags are modified to reflect the result of the addition.
 Example: ADC B or ADC M

 Add immediate to accumulator

 ADI 8-bit data
 The 8-bit data (operand) is added to the contents of the
accumulator and the result is stored in the accumulator.
 Example: ADI 45H

 Add immediate to accumulator with carry

 ACI 8-bit data
 The 8-bit data (operand) and the Carry flag are added
to the contents of the accumulator and the result is
stored in the accumulator.
 Example: ACI 45H

 Add register pair to H and L registers

 DAD Reg. pair
 The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum is
stored in the HL register.
 The contents of the source register pair are not altered.
 If the result is larger than 16 bits, the CY flag is set.
 No other flags are affected.
 Example: DAD H
 Subtract register or memory from accumulator

 SUB R
 The contents of the operand (register or memory ) are
M subtracted from the contents of the accumulator, and
the result is stored in the accumulator.
subtraction. Example: SUB B or SUB M
 Subtract source and borrow from accumulator

 SBB R
 The contents of the operand (register or memory ) and
M the Borrow flag are subtracted from the contents of
the accumulator and the result is placed in the
accumulator.
subtraction. Example: SBB B or SBB M
 Subtract immediate from accumulator

 SUI 8-bit data
 The 8-bit data (operand) is subtracted from the contents
of the accumulator and the result is stored in the
accumulator.
subtraction.
 Example: SUI 45H

 Subtract immediate from accumulator with borrow

 SBI 8-bit data
 The 8-bit data (operand) and the Borrow flag are
subtracted from the contents of the accumulator and the
result is stored in the accumulator. All flags are modified
to reflect the result of the subtraction.
 Example: SBI 45H

 Increment register or memory by 1

 INR R The contents of the designated register or
memory) are M incremented by 1 and the result is
stored in the same place.
 Example: INR B or INR M

 Increment register pair by 1

 INX R
 The contents of the designated register pair are
incremented by 1 and the result is stored in the same
place.
 Example: INX H

 Decrement register or memory by 1

 DCR R
 The contents of the designated register or memory are
M decremented by 1 and the result is stored in the
same place.
 Example: DCR B or DCR M

 Decrement register pair by 1

 DCX R
 The contents of the designated register pair are
decremented by 1 and the result is stored in the same
place.
 Example: DCX H

 Decimal adjust accumulator
 DAA none The contents of the accumulator are

changed from a binary value to two 4-bit binary coded
decimal (BCD) digits.
 This is the only instruction that uses the auxiliary flag to
perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P,
CY flags are altered to reflect the results of the
operation.

 Decimal adjust accumulator

 If the value of the low-order 4-bits in the accumulator is
greater than 9 or if AC flag is set, the instruction adds 6
to the low-order four bits.
 If the value of the high-order 4-bits in the accumulator is
greater than 9 or if the Carry flag is set, the instruction
adds 6 to the high-order four bits.
 Example: DAA

Branching operations
 Jump unconditionally
 JMP 16-bit address The program sequence is
transferred to the memory location specified by the 16-
bit address given in the operand.
 Example: JMP 2034H or JMP XYZ

 Jump conditionally
 Operand: 16-bit address
 The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand based on the specified flag of the PSW as
described below.
 Example: JZ 2034H or JZ XYZ

 JC Jump on Carry CY = 1
 JNC Jump on no Carry CY = 0
 JP Jump on positive S = 0
 JM Jump on minus S = 1
 JZ Jump on zero Z = 1
 JNZ Jump on no zero Z = 0
 JPE Jump on parity even P = 1
 JPO Jump on parity odd P = 0

Subroutine
 Unconditional subroutine call
 CALL 16-bit address

operand.
 Before the transfer, the address of the next instruction
after CALL (the contents of the program counter) is
pushed onto the stack.
 Example: CALL 2034H or CALL XYZ
Subroutine
 Call conditionally
 Operand: 16-bit address
operand based on the specified flag of the PSW as
described below.
 Before the transfer, the address of the next instruction
after the call (the contents of the program counter) is
pushed onto the stack.
 Example: CZ 2034H or CZ XYZ

Subroutine
 CC Call on Carry CY = 1
 CNC Call on no Carry CY = 0
 CP Call on positive S = 0
 CM Call on minus S = 1
 CZ Call on zero Z = 1
 CNZ Call on no zero Z = 0
 CPE Call on parity even P = 1
 CPO Call on parity odd P = 0
Subroutine
 Return from subroutine unconditionally
 RET none
 The program sequence is transferred from the
subroutine to the calling program.
 The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
 Example: RET

Subroutine
 Return from subroutine conditionally

 Operand: none
 The program sequence is transferred from the
subroutine to the calling program based on the specified
flag of the PSW as described below.
 The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
 Example: RZ

Subroutine
 RC Return on Carry CY = 1
 RNC Return on no Carry CY = 0
 RP Return on positive S = 0
 RM Return on minus S = 1
 RZ Return on zero Z = 1
 RNZ Return on no zero Z = 0
 RPE Return on parity even P = 1
 RPO Return on parity odd P = 0

Other instructions
 Load program counter with HL contents

 PCHL none
 The contents of registers H and L are copied into the
program counter.
 The contents of H are placed as the high-order byte and
the contents of L as the low-order byte.
 Example: PCHL

Other instructions
 Restart
 RST 0-7 The RST instruction is equivalent to a 1-byte
call instruction to one of eight memory locations
depending upon the number.
 The instructions are generally used in conjunction with
interrupts and inserted using external hardware.
 However these can be used as software instructions in
a program to
 transfer program execution to one of the eight locations.
 The addresses are:
Restart
 Instruction Restart Address

 RST 0 0000H
 RST 1 0008H
 RST 2 0010H
 RST 3 0018H
 RST 4 0020H
 RST 5 0028H
 RST 6 0030H
 RST 7 0038H

Restart
 The 8085 has four additional interrupts and these

interrupts generate RST instructions internally and thus
do not require any external hardware.
 These instructions and their Restart addresses are:
 Interrupt Restart Address
 TRAP 0024H
 RST 5.5 002CH
 RST 6.5 0034H
 RST 7.5 003CH

Logical instructions
Compare register or memory with accumulator

 CMP R
 The contents of the operand (register or memory) are M
compared with the contents of the accumulator.
 Both contents are preserved .

 The result of the comparison is shown by setting the
flags of the PSW as follows:
 if (A) < (reg/mem): carry flag is set
 if (A) = (reg/mem): zero flag is set
 if (A) > (reg/mem): carry and zero flags are reset
 Example: CMP B or CMP M

 Compare immediate with accumulator

 CPI 8-bit data
 The second byte (8-bit data) is compared with the
contents of the accumulator.
 The values being compared remain unchanged.

 The result of the comparison is shown by setting the

flags of the PSW as follows:
 if (A) < data: carry flag is set
 if (A) = data: zero flag is set
 if (A) > data: carry and zero flags are reset
 Example: CPI 89H

 Logical AND register or memory with accumulator
 ANA R
 The contents of the accumulator are logically ANDed
with M the contents of the operand (register or
memory), and the result is placed in the accumulator.
 If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are
modified to reflect the result of the
operation.
 CY is reset.AC is set.
 Example: ANA B or ANA M
 Logical AND immediate with accumulator

 ANI 8-bit data
 The contents of the accumulator are logically ANDed
with the 8-bit data (operand) and the result is placed in
the accumulator.
 S, Z, P are modified to reflect the result of the operation.
 CY is reset.
 AC is set.
 Example: ANI 86H
 Exclusive OR register or memory with accumulator
 XRA R
 The contents of the accumulator are Exclusive ORed
with M the contents of the operand (register or
memory), and the result is placed in the accumulator.
specified by the contents of HL registers.
 CY and AC are reset.
 Example: XRA B or XRA M

 Exclusive OR immediate with accumulator

 XRI 8-bit data
 The contents of the accumulator are Exclusive ORed
with the 8-bit data (operand) and the result is placed in
the accumulator.
 Example: XRI 86H

 Logical OR register or memory with accumulator

 ORA R
 The contents of the accumulator are logically ORed with
M the contents of the operand (register or memory), and
the result is placed in the accumulator.
specified by the contents of HL registers.
 Example: ORA B or ORA M
 Logical OR immediate with accumulator
 ORI 8-bit data
 The contents of the accumulator are logically ORed with
the 8-bit data (operand) and the result is placed in the
accumulator.
 Example: ORI 86H

 Rotate accumulator left
 RLC none
 Each binary bit of the accumulator is rotated left by one
position.
 Bit D7 is placed in the position of D0 as well as in the
Carry flag.
 CY is modified according to bit D7.
 S, Z, P,AC are not affected.
 Example: RLC

 Rotate accumulator right

 RRC none
 Each binary bit of the accumulator is rotated right by
one position.
 Bit D0 is placed in the position of D7 as well as in the
Carry flag.
 S, Z, P,AC are not affected.
 Example: RRC
 Rotate accumulator left through carry

 RAL none
 Each binary bit of the accumulator is rotated left by one
position through the Carry flag.
 Bit D7 is placed in the Carry flag, and the Carry flag is
placed in the least significant position D0.
 S, Z, P, AC are not affected.
 Example: RAL
 Rotate accumulator right through carry

 RAR none
 Each binary bit of the accumulator is rotated right by
one position through the Carry flag.
 Bit D0 is placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.
 S, Z, P, AC are not affected.
 Example: RAR
 Complement accumulator
 CMA none
 The contents of the accumulator are complemented.
 No flags are affected.
 Example: CMA

 Complement carry
 CMC none
 The Carry flag is complemented.
 No other flags are affected.
 Example: CMC

 Set Carry
 STC none The Carry flag is set to 1. No other flags are
affected.
 Example: STC

Machine control instructions
 No operation
 NOP none
 No operation is performed.
 The instruction is fetched and decoded.
 However no operation is executed.
 Example: NOP

 Halt and enter wait state

 HLT none
 The CPU finishes executing the current instruction and
halts any further execution.
 An interrupt or reset is necessary to exit from the halt
state.
 Example: HLT

 Disable interrupts
 DI none
 The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled.
 No flags are affected.
 Example: DI

 Enable interrupts
 EI none
 The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected.
 After a system reset or the acknowledgement of an
interrupt, the interrupt enable flip flop is reset, thus
disabling the interrupts.
 This instruction is necessary to enable the interrupts
(except TRAP). Example: EI
 Read interrupt mask

 RIM none
 This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
 The instruction loads eight bits in the accumulator with
the following interpretations.
 Example: RIM

 Set interrupt mask

 SIM none
 This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output.
 The instruction interprets the accumulator contents as
follows.
 Example: SIM

Stack
 The Stack Pointer
 The stack on an 8080/8085 can be located anywhere in

RAM memory, pointed to by the stack pointer SP.
 Every time something is pushed on to the stack, the SP

pointer is decremented, so the stack is growing down in
memory.

Stack
 Stack operations are always performed with registers

pairs.
 A register pair is referenced by the name of the MSB
register: B, D or H.
 The only exception is PSW, which in fact is the LSB
register of the AF pair

Stack
 A push on the stack, whether it comes from the PUSH
instruction, a subroutine call, or interrupt has the
following sequence:
 Decrement SP by 1
 Save most significant byte of register pair
 Decrement SP by 1
 Save least significant byte of register pair
 Naturally a pop from the stack has just the opposite
effect:

Stack
 Load least significant byte of register pair

 Increment SP by 1
 Load most significant byte of register pair
 Increment SP by 1

Stack
 Push register pair onto stack
 PUSH Reg. pair
 The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence.
 The stack pointer register is decremented and the
contents of the high order register (B, D, H, A) are
copied into that location.
 The stack pointer register is decremented again and the
contents of the low-order register (C, E, L, flags) are
copied to that location.
 Example: PUSH B or PUSH A
Stack
 Pop off stack to register pair
 POP Reg. pair
 The contents of the memory location pointed out by the
stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand.
 The stack pointer is incremented by 1 and the contents
of that memory location are copied to the high-order
register (B, D, H, A) of the operand.
 The stack pointer register is again incremented by 1.
 Example: POP H or POP A

The 8085 Addressing Modes
 The instructions MOV B, A or MVI A, 82H are to copy

data from a source into a destination.
 In these instructions the source can be a register, an
input port, or an 8-bit number (00H to FFH).
 Similarly, a destination can be a register or an output
port.
 The sources and destination are operands.
 The various formats for specifying operands are called
the ADDRESSING MODES.
 For 8085, they are:

 Immediate addressing.
 Register addressing.
 Direct addressing.
 Indirect addressing.
 Implicit addressing

 Immediate addressing
 Data is present in the instruction. Load the immediate
data to the destination provided.
 Example: MVI R, data
 Register addressing
 Data is provided through the registers.
 Example: MOV Rd, Rs

 Direct addressing
 Used to accept data from outside devices to store in the
accumulator or send the data stored in the accumulator
to the outside device.
 Accept the data from the port 00H and store them into
the accumulator or Send the data from the accumulator
to the port 01H.
 Example: IN 00H or OUT 01H

 Indirect Addressing
 This means that the Effective Address is calculated by
the processor and the contents of the address (and the
one following) is used to form a second address.
 The second address is where the data is stored.
 Note that this requires several memory accesses; two
accesses to retrieve the 16-bit address and a further
access (or accesses) to retrieve the data which is to be
loaded into the register.

8085 Assembler Directives
 Assembler directives are instructions to the assembler
concerning the program being assembled.
 They are not translated into machine code or assigned
any memory locations in the object file.
 ORG (origin)
 org 20
 The next block of instructions or data should be stored
in memory locations starting at 2010.
 Either hex or decimal numbers are acceptable.

 END
 end
 start end of assembly.
 A HLT instruction may suggest the end of a program,
but does not necessarily mean it is the end of assembly.
 "start" is the label at the beginning of the program*.

 EQU
 (equate)
 lookup equ 2
 The value of the term, lookup, is equal to 2.
 lookup's value may be referred by name in the program.
 Similar to a constant statement.

 inbuf equ 2099

 The value of the term, inbuf, is 2099.
 This may be the memory location used as an input
buffer.

 DB
 (define byte)
 data: db 34 or data: db 34
 db A2,db 93
 Initializes an area byte by byte.
 Assembled bytes of data are stored in successive
memory locations until all values are stored.
 The label is optional and may be used as the memory
location of the beginning of the data.
 DW (define word)
 long: dw 2050 Initializes an area two bytes at a time.
 DS (define storage)
 table: ds 10
 Reserves a specified number of memory locations.In
this example,10 memory locations are reserved for
"table".
 The label may be used as the memory location of the
beginning of the block of memory.
Instruction Format
 An instruction is a command to the microprocessor to
perform a given task on a specified data.
 Each instruction has two parts: one is task to be

performed, called the operation code (opcode), and
the second is the data to be operated on, called the
operand.
 The operand (or data) can be specified in various

ways.It may include 8-bit (or 16-bit ) data, an internal
register, a memory location, or 8-bit (or 16-bit) address.

Instruction Format
 In some instructions, the operand is implicit.
 Instruction word size

 The 8085 instruction set is classified into the following
three groups according to word size:
 One-word or 1-byte instructions
 Two-word or 2-byte instructions
 Three-word or 3-byte instructions

Instruction Format
 One-Byte Instructions
 A 1-byte instruction includes the op code and operand

in the same byte.
 Operand (s) are internal register and are coded into the
instruction.
 For example:
 Copy the contents of the accumulator in the register C.
 MOV C,A 0100 1111 4FH

Instruction Format
 Add the contents of register B to the contents of the
accumulator.
 ADD B 1000 0000 80H
 Invert (compliment) each bit in the accumulator.

 CMA 0010 1111 2FH

Instruction Format
 MOV rd, rs
 rd <-- rs copies contents of rs into rd.
 Coded as 01 ddd sss where ddd is a code for one of the
7 general registers which is the destination of the data,
sss is the code of the source register.

Instruction Format
 Two-Byte Instructions
 In a two-byte instruction, the first byte specifies the

operation code and the second byte specifies the
operand.
 Source operand is a data byte immediately following the
op code.
 For example:
 Load an 8-bit data byte in the accumulator.
 MVI A, Data 3E

Instruction Format
 Assume that the data byte is 32H. The assembly
language instruction is written as
 Mnemonics Hex code
 MVI A, 32H - 3E 32H
 The instruction would require two memory locations to
store in memory.
 MVI r, data
 r <-- data
 Example: MVI A,30H coded as 3EH 30H as two
contiguous bytes.
Instruction Format
 ADI data
 A <-- A + data
 OUT port
where port is an 8-bit device address.
 (Port) <-- A.
 Since the byte is not the data but points directly to
where it is located this is called direct addressing.

Instruction Format
 Three-Byte Instructions
 In a three-byte instruction, the first byte specifies the op
code, and the following two bytes specify the 16-bit
address.
 Note that the second byte is the low-order address and
the third byte is the high-order address.
 Op code + data byte + data byte
 For example:
 Transfer the program sequence to the memory location
2085H.
 JMP 2085H Rungta College of Engg. & Technology 282
MYcsvtu Notes
Instruction Format
 C3 85 20
 First byte Second Byte Third Byte
 This instruction would require three memory locations to
store in memory.
 Three byte instructions - opcode + data byte + data byte
 LXI rp, data16

 rp is one of the pairs of registers BC, DE, HL used as
16-bit registers.
 The two data bytes are 16-bit data in L H order of
significance.
 rp <-- data16
Instruction Format
 Example:
 LXI H,0520H coded as 21H 20H 50H in three bytes.
 This is also immediate addressing.
 LDA addr
 A <-- (addr) Addr is a 16-bit address in L H order.
 Example: LDA 2134H coded as 3AH 34H 21H.
 This is also an example of direct addressing.

Delay generation
 Delay are generated using subroutine

 Delays are generated for different purpose
 Example- Traffic signal, counters (timer circuits) etc
 They may also be generated using NOP instruction.

Delay generation
 Ways to generate delay-

 Delay depends on the total number of T states present
in the subroutine
 To start with a “counter” is set up
 For small delays an 8 bit register is set up
 For large delays a 16 bit register is used as counter
 Nested lops are also used in which two registers are
used

Delay generation
 Small delay generation

 8 bit register is used as counter
 SUBROUTINE-
 Set an 8 bit register as a counter
 MVI B, FFH -7T
 DELAY DCR B -4T
 JNZ DELAY -10T/7T
 RET -10T

Delay generation
 The loop is executed count-1 times.

 For the last jump the condition becomes untrue and it
comes out the loop.
 Total T states in the above program
 =7T+(COUNT-1)(4T+10T)+(4T+7T)+10T
 =7T+254*14T+11T+10T
 =3584 T states

Delay generation
 Now if clock period=.5 micro secs

 Td= 3584*.5
 =1792 microseconds
 =1.792 mili secs

Delay generation
 Long delay generation

 16 bit register is used as counter
 LXI D,FFFF H-10T
 DELAY DCX D-6T
 MOV A,E-4T
 ORA D-4T
 JNZ DELAY-10T/7T
 RET-10T

Delay generation
 Total number of T states=

 10t+(6t+4t+4t+10t)*count-1+(6t+4t+4t+7t)+10t
 = 10t+(6t+4t+4t+10t)*65534+(6t+4t+4t+7t)+10t
 =1572857 t states
 If 1t=.5 micro secs
 Td=1572857*.5=
 =786.43ms

Delay generation
 Write a subroutine for 8085 to generate a delay of

10ms(assume .3333 micro secs clock cycle)
 Write a subroutine for 8085 to generate a delay of

100microsecs(assume 320 ns clock cycle)

Delay generation
 If the clock frequency of a 8085 system is
2MHz.Calculate the delay generated by the following
set of instructions
 LXI B,3480 H
 UP DCX B
 MOV A,C
 ORA B
 JNZ UP
 FREQUENCY=2 MHz

Delay programs
 Sol1-
 For .3333 micro secs clock cycle
 10 ms=(1/.3333)*10 = 30030.03 secs = 30030 t states
 It‟s a large value hence reg pair is used as counter
 Program
 LXI D,count H- 10T
 DELAY DCX D- 6T
 MOV A,E- 4T
 ORA D- 4T
 JNZ DELAY- 10T/7T
 RET- 10T
Delay programs
 30030*T = 10T+(6+4+4+10)* count-1

+(6+4+4+7)T+10T
Count = 1250.5 = (1250)d

Delay programs
 Sol 2
 Program
 MVI B, count H -7T
 DELAY DCR B -4T
 JNZ DELAY -10T/7T
 RET -10T

Delay programs
 100 micro secs = (100/320 ns)

= 312.5 t states
312.5 * T = 7T+(4T+10T) count-1 +(4T+7T)+
10T
Count = 21.32
=(21)d
= 15H

Delay programs
 Sol 3
 Given frequency = 2 MHz
 Count = (3480)H = (13440)d
 T = (1/2*10^6) = .5 micro secs
 Td= 10T+(6T+4T+4T+10T)* count-1
+(6+4+4+7)T+10T
Hence substituting the values of 1 T & count we have
Td = 161288.5 micro secs = 161.28 ms = .16 s

Programs for code conversion
 Binary to ASCII code conversion

 LXI SP, STACK
 LXI H, 4050 H
 LXI D, 4060 H
 MOV A,M
 MOV B,A

Binary to ASCII code conversion
 RRC
 RRC
 RRC
 RRC
 CALL ASCII
 STAX D
 INX D
 MOV A,B

Binary to ASCII code conversion
 CALL ASCII
 STAX D
 HLT
 ASCII- SUBROUTINE
 ANI 0F H
 CPI 0A H
 JC CODE
 ADI 30 H
 CODE ADI 30 H
 RET
ASCII TO BINARY
 SUBROUTINE
 SUI 30 H
 CPI 0A H
 RC
 SUI 07 H
 RET

BCD TO BINARY CONVERSION
 BCD TO BINARY CONVERSION

 LXI SP, STACK
 LXI H, 4050 H
 LXI B, 4060 H
 MOV A,M
 CALL BCD TO BINARY
 STAX B
 HLT

 SUBROUTINE BCD TO BINARY
 PUSH B
 PUSH D
 MOV C,A
 ANI OF H
 MOV B,A
 MOV A,C

 ANI F0 H
 RRC
 RRC
 RRC
 RRC
 MVI E,0A H
 MOV D,A
 XRA A

 SUM ADD E
 DCR D
 JNZ SUM
 ADD B
 POP D
 POP B
 RET

BINARY TO BCD CONVERSION
 LXI SP, 4FFF H

 LXI H, 4050 H
 MOV A,M
 CALL SUB1
 HLT
 SUB1 LXI H,4060 H
 MVI B, 64H

BINARY TO BCD CONVERSION
 CALL CONVERSION
 MVI B,0A H
 CALL CONVERSION
 MOV M,A
 CONVERSION
 MVI M, FF H
 LOOP INR M
 SUB B
 JNC LOOP
 ADD B
 INX H
 RET
BCD TO 7 SEGMENT LED CODE
CONVERSION
 LXI SP, 4FFF H
 LXI H, 4050 H
 MVI D, 03 H
 CALL UNPACK
 HLT
 UNPACK LXI B, 4060 H

CONVERSION
 AHEAD MOV A,M
 ANI F0 H
 RRC
 RRC
 RRC
 CALL LED CONVERSION
 INX B
 MOV A,M

CONVERSION
 ANI 0F H
 CALL LED CONVERSION
 INX B
 INX H
 DCR D
 JNZ AHEAD
 RET

CONVERSION
 LED CONVERSION
 PUSH H
 LXI H, CODE
 ADD L
 MOV L,A
 MOV A,M
 STAX B
 POP H
 RET

Sample Programs
 Write an assembly program to add two numbers

 Program
 MVI D, 8BH
 MVI C, 6FH
 MOV A, C
 ADD D
 OUT PORT1
 HLT

Sample Programs
 Write an assembly program to multiply a number by

8
 Program
 MVI A, 30H
 RRC
 RRC
 RRC
 OUT PORT1
 HLT

Sample Programs
 Write an assembly program to find greatest between
two numbers
 Program
 MVI B, 30H
 MVI C, 40H
 MOV A, B
 CMP C
 JZ EQU
 JC GRT
 OUT PORT1
 HLT
Sample Programs
 EQU: MVI A, 01H
 OUT PORT1
 HLT
 GRT: MOV A, C
 OUT PORT1
 HLT

Sample Programs
 Write a 8085 machine code program:
 Read two different memory locations

 Add the contents
 Send the result to output port 02 (display) if there is
no overflow
 Display “FF” if there is an overflow
 Stop

Sample Programs
2000 LDA 2050 3A

2001 50
2002 20
2003 MOV B,A 47
2004 LDA 2051 3A
2005 51
2006 20
2007 ADD B 80
2008 JNC 2013 D2

2009 13
2010 20
2011 MVI A,FF 3E
2012 FF
2013 OUT 02 D3
2014 02
2015 HLT 76

Sample Programs
 Multiply eight bit numbers using successive addition

method numbers are loaded in reg. D and C. Result is
stored in HL pair.

Sample Programs
 MVI D, 05
 LXI B, 0015
 LXI H, 0000
 DAD B
 DCR D
 JNZ C008
 HLT

Sample Programs
 Write a program to find the positive numbers in an array

of 10 elements. Assume the array starts from C200.
Store the result at C300.

Sample Programs
 MVI C , 09
 LDA C001
 LXI H, C002
 ADD M
 INX H
 DCR C
 JNZ D008
 STA C100
 HLT

UNIT- III
DATA TRANSFER
&
DEVICE SELECTION

Data transfer & device selection
 Input-Output (I/O) describes the transference of

information between main memory and the various
peripheral devices attached to a computer.
 Peripheral devices are slower than CPUs and require

special . Interface modules are used to match CPU and
main memory characteristics to those of the peripheral
devices

 I/O device characteristics
 The speed of data transfer and the quantity of data that

is transferred are two critical factors of I/O devices.
 For example, a keyboard is a character–based input
device, and each character of a keyboard is inputted
into a PC as an ASCII code. Keyboard input is very
slow.

 Task
 Why is character input slow?
 There are different types of character input from a
keyboard.
 There is an expected input by an application program in
response to a „read statement‟ of some kind that
requests input of data for the program, think about data-
entry into an expert system.

 On other occasions, the user may wish to interrupt what

the computer is doing.
 For example, under the „Unix‟ operating system typing
Control-c will stop a program that is running, in contrast
under a „Windows type‟ operating system typing
Control-c is an editing command to copy data and
typing Control, Alt, Delete will restart a PC.
 In terms of computation these are examples of
unexpected inputs, since the program that is
undergoing execution is not expecting such inputs or
interrupts.
 On a multi user system, many keyboards might be

connected to a single computer.
 The computer must have the capability to distinguish
between the different keyboards.
 The computer must not lose input data even if several
keyboards transmit a character input simultaneously.
 The computer must be able to respond quickly to each
keyboard, and the physical distances of the keyboards
to the computer may be long.

 Task
 How do you think a mouse action can act as an
interrupt?
 Disks, printers, screens and other I/O devices operate
under the CPU program control.
 VDUs and most printers are output devices, and the
output that is produced is determined by the program
undergoing execution.

 Disks are storage devices, but as we have previously

discussed there can be a „blur‟ to this concept and disks
can be considered to be both I/O devices as well as
storage devices, where the input and the output are
determined by the program undergoing execution.
 In these cases, it is always the program undergoing
execution in the CPU that initiates I/O data transfer.
 Furthermore, the CPU will continue processing other
tasks while waiting for a particular I/O operation to
complete.

 There are occasions when an I/O device being

addressed is busy or not ready.
 For example, a printer may already have a print job, or it
may be stalled due to a miss feed of paper.
 There might not be a floppy disk in a floppy disk drive or
a hard disk might be servicing a different request.
 In such cases, it is beneficial for the I/O device to be
able to provide status information to the CPU, in order
that appropriate action can be taken.

 Requirements for sufficient and effective handling of I/O

 a) There must be a means for individually addressing
different I/O devices.
 b) There must be mechanisms by which I/O devices can
communicate with the CPU.
 c) Programmed I/O is suitable for slow devices and
word transfers.
 d) Faster I/O devices must have mechanisms to transfer
blocks of data.
 e) There must be mechanisms to handle devices with
extremely different control requirements.
 Consequently, it is impractical to connect I/O devices
directly to a CPU without some form of interface unit
that is unique to each device.
 For example, the formats required by different devices

are different. Some devices require a single portion of
data, others a block of data. Some devices expect 8 bits
of data, others 16, 32 or even 64.

 Data may be transmitted serially or in parallel.
 Therefore, a computer system requires substantially

different interface hardware and software for each I/O
device.
 Incompatibilities in speed between the various I/O

devices and the CPU render synchronization a major
problem.

 Magnetic disks have electromechanical control

requirements that must be met.
 Such control requirements would consume a vast
amount of CPU time.
 I/O devices therefore have different requirements.
 Additionally, there is a necessity for the provision of
addressing, synchronization, status control and external
control capabilities.
 Consequently, each I/O device requires its own unique
interface module to serve between itself and the CPU.
Interface modules
 Interface modules
 Interface modules can be very simple and control a
single I/O device. Alternatively, interface modules can
be complex, controlling many I/O devices and may have
substantial built in intelligence

Interface modules
Serial & parallel data transfer
 There are many types of interface modules, but they all
have one important characteristic, which distinguishes
whether they support parallel data transfer or serial data
transfer.
 A parallel interface transfers multiple bits of data
simultaneously using a separate data line for each bit.

Interface modules
 Parallel data transfer

Interface modules
 In contrast, a serial interface transfers single bits of data
consecutively over a single data line.
 Serial data transfer

Interface modules
 It is possible to transfer data a word[1] at a time, which

is adequate for slow operating I/O devices.
 However, the amount of data that is transferred
between devices such as disks and tapes renders word
transfer far too slow for modern high-speed computers.
 Consequently, blocks of data are transferred.
 A further problem is that a computer has many I/O
devices, and many may attempt to transfer data
simultaneously.

Interface modules
 Therefore, there is a requirement to distinguish and
separate I/O from these different devices.
 Different devices operate at different speeds to each
other and the CPU. For example, a dot-matrix printer
may output 40 characters/sec, whereas a disk might
transfer data at millions of bytes/sec.
 To prevent data loss such I/O operations must be
synchronized.

Interface modules
 A simple parallel I/O interface.

 The unit is composed of three registers: a data register,
a control register and a status register, which can be
accessed by the CPU over the system bus.

Interface modules
 The external data bus is a collection of parallel data
lines that can be configured to be either input or output
by writing a suitable bit pattern into the control register.

Interface modules
 Once configured, data is transferred to or from the

external data bus by reading or writing from or to the
data register or port.
 This data port, therefore, serves as a buffer between
the system bus and the external data bus.
 The status register is used to flag whether a device is
ready and data is available.
 The CPU by using the control bus can inspect the
status register to determine whether data can be sent or
received.
Interface modules-Handshake concept
 The data bus must be able to support data transfer with

a wide range of peripheral devices.
 The speeds of the different peripheral devices are
usually known, therefore control or handshake signals
are provided to synchronize the bus activities of the
interface device and the I/O device, see Figure .

 The example typically represents how data is

transferred from an output port to a peripheral device
such as a printer.
 A handshake protocol is used that uses two control
lines: data available and data accepted.
 The handshake is initiated by the interface module,
which puts data on the data bus and asserts the data
available control line.

 When the peripheral device (in this case a printer)
detects this signal, it reads the data from the bus and
broadcasts an acknowledgement by asserting the data
accepted control line.
 When the interface module receives this
acknowledgement, it negates the data available control
line.
 After the printer has completed processing, it negates
the data accepted control line and the handshake is
completed.

 I/O operations consume large amounts of processing

time.
 Even if a block of data is transferred between a disk and
the CPU in a single instruction, a large amount of time
is wasted waiting for the task to complete.
 For example, a CPU could execute many instructions in
that time that a single character is printed.
 It is advantageous to enable the CPU to process other
tasks while a slow I/O transfer is taking place.

I/O DATA TRANSFER SCHEME
 I/O DATA TRANSFER SCHEME

 Its divided into two data transfer
 Programmed data transfer
1) synchronous data transfer 2) asynchronous data
transfer
 DMA data transfer

Programmed I/O data transfer
 Modes of I/O Transfer: Programmed I/O
 There are three ways by which the transfer of data

between an I/O device and memory can be managed or
scheduled:
 programmed I/O
 Interrupt-controlled I/O and
 Direct Memory Access (DMA).

 Many I/O modules permit control lines to be

programmed to suit the needs of a particular peripheral
device.
 With programmed I/O the CPU has control over all
aspects of the data transfer.
 Each data transfer is carried out by executing a polling
loop, such as the one shown in Figure.

Programmed I/O data transfer-
Polling loop

 In this example, the processor schedules data transfer

to a peripheral device by first reading the port status
register to see if the peripheral device is ready to
transmit or receive data.
 In the case that the I/O device is ready because the
examine flag is asserted, data is transferred and the
processor loops back.
 In the case that the I/O device is not ready because the
examine flag is negated, the processor loops back.

 The major disadvantage of programmed I/O is the

polling loop, or busy waiting, can waste large amounts
of CPU time, and it is therefore inefficient in terms of
CPU usage.
 Programmed I/O is slow and is suitable for character
transmission I/O devices such as printers, keyboards
and monitors.

Interrupt driven I/O
 Modes of I/O Transfer: Interrupt driven I/O
 With interrupt driven I/O the normal flow of a program is

interrupted to react to a special event.
 For example, typing Control, Alt, Delete on a PC
interrupts the program that is running and restarts the
PC.
 Interrupt driven I/O is more efficient than programmed
I/O, because an I/O device signals the CPU when it
requires a service.
 Consequently, interrupt driven I/O frees the CPU to

continue executing other tasks.
 Most computers have interrupt lines to detect and
record the arrival of an interrupt request.
 It is common for a PC to have between 8 and 15
interrupt lines, which are labeled IRQ1, IRQ2 and so on,
where IRQ represents Interrupt Request.

 In the case that an IRQ is asserted the computer

suspends the program that is undergoing execution.
 When an interrupt is accepted, the CPU passes
program control to an interrupt handler or service
routine.
 Before control is passes to the interrupt handler, the PC
and status register are saved by pushing them onto a
Return Address Stack (RAS).

 The interrupt handling program is now executed until a

Return from Exception (RTE) instruction is encountered
at the end of the interrupt.
 Once the interrupt has been completed the PC and
status register is popped from the RAS, and control is
passed back to the interrupted program.
 Multiple interrupts can occur together, in which case a
priority mechanism must decide the order in which the
interrupts are handled.

 There are two major disadvantages of interrupt driven

I/O.
 First, all data transfers involve moving data to and from
the CPU registers.
 Second, since the PC and Status Register are pushed
onto the RAS before control is passed to the interrupt
handler and they are popped from the RAS when an
RTE is encountered, then a significant overhead is
involved which can impact on processor performance

DMA I/O
 Modes of I/O Transfer: DMA I/O
 An alternative mechanism that avoids the use of the

CPU is called Direct Memory Access (DMA).
 Many device controllers, particularly those used for

block devices such as magnetic disks use DMA, see
storage device handout.

DMA I/O
 Data is directly transferred between a peripheral device
from main memory and the CPU is bypassed.
 Once the data has been transferred the Interface

module notifies the CPU, so that the CPU is aware that
the data transfer has completed and main memory
access can then resume.

DMA I/O
 Data transfer is initiated using programmed I/O by the

program that is undergoing execution in the CPU.
 The CPU is then bypassed for the remainder of the
interrupt.
 There are several advantages of DMA. First DMA is
particularly good at fast data transfers.
 Second, since the CPU can be used for other tasks,
then DMA is particularly useful in a multitasking system,
and multi user systems.

DMA I/O
 DMA is not restricted to I/O device – Memory transfers,

it can be used with other high-speed devices.
 For example, DMA is an effective means of transferring
video data from memory to a video I/O device for rapid
display.

Asynchronous and synchronous data
transmission
 Asynchronous and synchronous data transmission
 Asynchronous transmission uses start and stop bits to

signify the beginning bit ASCII character would actually
be transmitted using 10 bits
 e.g.: A "0100 0001" would become "1 0100 0001 0".
 The extra one (or zero depending on parity bit) at the
start and end of the transmission tells the receiver first
that a character is coming and secondly that the
character has ended.
transmission
 This method of transmission is used when data are sent
intermittently as opposed to in a solid stream.
 In the previous example the start and stop bits are in
bold.
 The start and stop bits must be of opposite polarity.
 This allows the receiver to recognize when the second
packet of information is being sent.

transmission
 Synchronous transmission uses no start and stop bits
but instead synchronizes transmission speeds at both
the receiving and sending end of the transmission using
clock signals built into each component.
 A continual stream of data is then sent between the two

nodes.

transmission
 Due to there being no start and stop bits the data
transfer rate is quicker although more errors will occur,
as the clocks will eventually get out of sync, and the
receiving device would have the wrong time that had
been agreed in protocol (computing) for
sending/receiving data, so some bytes could become
corrupted (by losing bits).
 Ways to get around this problem include re-

synchronization of the clocks and use of check digits to
ensure the byte is correctly interpreted and received.

transmission
 Synchronous and Asynchronous data transfer are two
methods of sending data over a phone line.
 In synchronous data transmission, data is sent via a bit-
stream, which sends a group of characters in a single
stream.
 In order to do this, modems gather groups of characters
into a buffer, where they are prepared to be sent as
such a stream.

transmission
 In order for the stream to be sent, synchronous
modems must be in perfect synchronization with each
other.
 They accomplish this by sending special characters,

called synchronization, or syn, characters.

transmission
 When the clocks of each modem are in synchronization,
the data stream is sent.
 In asynchronous transmission, data is coded into a
series of pulses, including a start bit and a stop bit.
 A start bit is sent by the sending modem to inform the
receiving modem that a character is to be sent.
 The character is then sent, followed by a stop bit
designating that the transfer of that bit is complete

Memory-Mapped I/O
 I/O devices are treated like memory locations

 Processor uses memory-access instructions and
addressing modes to access I/O devices
 I/O devices and memory locations cannot have the
same address
 Address is 16 bits wide
 Memory of 64K is shared with I/O devices

I/O-mapped I/O
 Processor controls I/O by a group of dedicated control

signals
 Processor uses special instructions to access these I/O
 Each I/O (or port) is identified by a unique port number
 IN and OUT instructions are used.
 256 combinations or 256 I/O devices can be assembled
 Same 8 bit address is copied to A0-A7 and A8 – A15.
 64 k memory and 256 I/O devices are available.

Memory structure & its requirements
Data Lines
RAM ROM
Input Buffer WR
Address Address CS
CS
Lines Lines
Output Buffer RD Output Buffer RD
Data Lines
Date
Lines
 The process of interfacing the above two chips is the

same.
 However, the ROM does not have a WR signal.
 8085 requires memory to-

 Read op code
 To read/write data
 Hence both EPROM & RAM are interfaced with it
 Multiple EPROM & RAM could be interfaced anywhere
with in the address range of 8085

 Memory chip consists of registers to store data

 They are represented as
 2k*8, 4k*8, 8k*8 etc
 2k*8 means it has address range of 2*1024 bytes.
 Each location stores 8 bit
 2*1024 registers & each register could store only 8 bits

Steps for memory interfacing with 8085
 Enable the memory chip

 Identify the address at which the data had to be
operated.
 8085 has 16 address lines
 It can address 64 k memory
 Interfacing means we have to place the available
memory chip (2k,4k,8k,16k EPROM/RAM) with in the
64 k byte address range)

 Placing in the address range is also referred as

“Mapping”
 Memory could be placed anywhere
 Mapping decides address of the memory component
 Its not necessary to use 64 KB of memory
 It depends on the application
 We can expand the memory in order to get the memory
size we want.

 We can have multiple EPROM and multiple RAM.

 Reset address of 8085 if 0000 h. So at least mapping of
one EPROM is necessary at 0000 h
 Some address lines of 8085 are used to connect
directly to the memory chip.
 Some are used for decoding the address of the memory
chip.
 This may require the use of the decoder IC 74LS138.
 All these steps depend on the range of the memory chip
to be connected to 8085
 Accessing memory can be summarized into the

following three steps:
 Select the chip.
 Identify the memory register.
 Enable the appropriate buffer.

 Translating this to microprocessor domain:

 The microprocessor places a 16-bit address on the
address bus.
 Part of the address bus will select the chip and the
other part will go through the address decoder to
select the register.
 The signals IO/M and RD combined indicate that a
memory read operation is in progress. The MEMR
signal can be used to enable the RD line on the
memory chip.

Address decoding
 The result of address decoding is the identification of a

register for a given address.
 A large part of the address bus is usually connected
directly to the address inputs of the memory chip.
 This portion is decoded internally within the chip.
 What concerns us is the other part that must be
decoded externally to select the chip.
 This can be done either using logic gates or a
decoder.
The Overall Picture
 Putting all of the concepts together, we get:

Chip Selection
A15- A10 Circuit
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR

Examples of memory interfacing with 8085
 Single EPROM & Single RAM- case1
0000 H
4K EPROM
0FFF H
1000 H
4K RAM
1FFF H

 Single EPROM & Single RAM-Case 2

0000 H
4K EPROM
0FFF H
2000 H
4K RAM
2FFF H
FFFF H

 Two EP ROMs and Single RAM

0000 H
4K EPROM
0FFF H
0FFF H
RAM
C000 H
COOO H
4K EPROM
CFFF H
FFFF H

 Interface 2KB of memory to 8085 with starting address

8000 H
 Sol-
 Placing the starting address of the chip on the address
lines of 8085 we have
 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

 2 KB = 2*2^10
 = 2 ^ 11
 Hence 11 address lines (A0-A10) are connected directly
to the memory chip and A15 to A11 are used for
selecting the chip

 The final address of the chip is obtained as follows-

 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
 Hence the range of the chip is from 8000 H to 87FF H.

 A15 to A11 are used to select the chip using the NAND gate.
 The chip is selected by providing a low signal at its chip select
pin.
 The A15 to A11 address lines are used as inputs to the NAND
gate.
 Their logic is so adjusted so that the output of NAND gate is low.

Shadow memory/Folded memory/Linear
decoding
 Its also known as partial or linear decoding
 In this type of decoding its not necessary to use all
address lines
 Address lines which are not really required for selection
of chip could be used for finding different address range
of a single memory chip

decoding
 Example-
 Interface 1K*8 EPROM to 8085 using linear decoding
 Sol
 Lets assume the starting address as 0000 H.
 The address range of the given chip is obtained as follows-
 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
 ie the range is 0000 H to 03FF H.

decoding
 Now if the logic of A15 and A14 lines are changed as
follows-
 A15 A14
0 0
0 1
1 0
1 1
 we have the different address range of the same chip
as follows-
decoding
 0000 H - 03FF H
 4000 H - 43FF H
 8000 H - 83FF H
 C000 H - C3FF H
 This results in wastage of address space.

decoding
0000 H
Actual Address
03FF H
4000 H
43FF H
8000 H
Folded
Address83FF H
C000 H
C3FF H
FFFF H

Absolute decoding
 In absolute decoding no address space is wasted

 Its used when number of peripherals is more
 More hardware is required

UNIT- IV
INTERRUPTS

Interrupts
 Interrupt is a process where an external device can get

the attention of the microprocessor.
 The process starts from the I/O device
 The process is asynchronous.

Interrupts
 Classification of Interrupts
 Interrupts can be classified into two types:
 Maskable Interrupts (Can be delayed or Rejected)
 Non-Maskable Interrupts (Can not be delayed or
Rejected)

Interrupts
 Interrupts can also be classified into:
 Vectored (the address of the service routine is hard-

wired)
 Non-vectored (the address of the service routine needs
to be supplied externally by the device)
 An interrupt is considered to be an emergency signal

that may be serviced. The Microprocessor may respond
to it as soon as possible.
Interrupts
 What happens when MP is interrupted ?
 When the Microprocessor receives an interrupt signal, it

suspends the currently executing program and jumps to
an Interrupt Service Routine (ISR) to respond to the
incoming interrupt.
 Each interrupt will most probably have its own ISR.

Responding to Interrupts
 Responding to an interrupt may be immediate or

delayed depending on whether the interrupt is maskable
or non-maskable and whether interrupts are being
masked or not.

Responding to Interrupts
 There are two ways of redirecting the execution to the

ISR depending on whether the interrupt is vectored or
non-vectored.
 Vectored: The address of the subroutine is already
known to the Microprocessor
 Non Vectored: The device will have to supply the
address of the subroutine to the Microprocessor

The 8085 Interrupts
 When a device interrupts, it actually wants the MP to

give a service which is equivalent to asking the MP to
call a subroutine. This subroutine is called ISR (Interrupt
Service Routine)
 The „EI‟ instruction is a one byte instruction and is used
to Enable the non-maskable interrupts.
 The „DI‟ instruction is a one byte instruction and is used
to Disable the non-maskable interrupts.

The 8085 Interrupts
 The 8085 has a single Non-Maskable interrupt.
 The non-maskable interrupt is not affected by the
value of the Interrupt Enable flip flop.

Interrupts in 8085
INTA
Interrupt
Save Send out

program Disable interupt
counter interrupts acknowledge
Main routine
Go to
service
Go back
routine
Get EI
original RET
program
counter Service routine

Saving the PC in Stack

Hardware Interrupts
 The 8085 has 5 interrupt inputs.

 The INTR input.
 The INTR input is the only non-vectored interrupt.
 INTR is maskable using the EI/DI instruction pair.
 RST 5.5, RST 6.5, RST 7.5 are all automatically

vectored.
 RST 5.5, RST 6.5, and RST 7.5 are all maskable.
 TRAP is the only non-maskable interrupt in the 8085

 TRAP is also automatically vectored

Interrupts
Interrupt name Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

8085 Interrupts
TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA

Interrupt Vectors and the Vector Table
 An interrupt vector is a pointer to where the ISR is

stored in memory.
 All interrupts (vectored or otherwise) are mapped onto a
memory area called the Interrupt Vector Table (IVT).
 The IVT is usually located in memory page 00
(0000H - 00FFH).
 The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when
an interrupt arrives.

Interrupt Vectors and the Vector Table
 Example: Let , a device interrupts the Microprocessor

using the RST 7.5 interrupt line.
 Because the RST 7.5 interrupt is vectored,
Microprocessor knows , in which memory location it has
to go using a call instruction to get the ISR address.
RST7.5 is knows as Call 003Ch to Microprocessor.
 Microprocessor goes to 003C location and will get a
JMP instruction to the actual ISR address.
 The Microprocessor will then, jump to the ISR location

The 8085 Non-Vectored Interrupt Process
• The interrupt process should be enabled using the EI

instruction.
• The 8085 checks for an interrupt during the execution
of every instruction.
• If INTR is high, MP completes current instruction,
disables the interrupt and sends INTA (Interrupt
acknowledge) signal to the device that interrupted

• INTA allows the I/O device to send a RST instruction

through data bus.
• Upon receiving the INTA signal, MP saves the memory
location of the next instruction on the stack and the
program is transferred to „call‟ location (ISR Call)
specified by the RST instruction

• Microprocessor Performs the ISR.

• ISR must include the „EI‟ instruction to enable the
further interrupt within the program.
• RET instruction at the end of the ISR allows the MP to
retrieve the return address from the stack and the
program is transferred back to where the program was
interrupted

 The 8085 recognizes 8 RESTART instructions:
 RST0 - RST7.
 Each of these would send the execution to a

predetermined hard-wired memory location:

Hard-wired memory location of Restart
Restart Instruction Equivalent to

RST0 CALL 0000H
RST1 CALL 0008H
RST2 CALL 0010H
RST3 CALL 0018H
RST4 CALL 0020H
RST5 CALL 0028H
RST6 CALL 0030H
RST7 CALL 0038H

Restart Sequence
 The restart sequence is made up of three machine

cycles
 In the 1st machine cycle:
 The microprocessor sends the INTA signal.
 While INTA is active the microprocessor reads
the data lines expecting to receive, from the

interrupting device, the opcode for the specific
RST instruction.

Restart Sequence
 In the 2nd and 3rd machine cycles:

 the 16-bit address of the next instruction is saved
on the stack.
 Then the microprocessor jumps to the address
associated with the specified RST instruction.

Timing Diagram of Restart Sequence

Hardware Generation of RST Op code
 How does the external device produce the op code for

the appropriate RST instruction?
 The op code is simply a collection of bits.
 So, the device needs to set the bits of the data bus
to the appropriate value in response to an INTA
signal.


 During the interrupt acknowledge machine cycle, (the

1st machine cycle of the RST operation):
 The Microprocessor activates the INTA signal.
 This signal will enable the Tri-state buffers, which will
place the value EFH on the data bus.
 Therefore, sending the Microprocessor the RST 5
instruction.
 The RST 5 instruction is exactly equivalent to CALL

0028H
Issues in Implementing INTR Interrupts
 How long must INTR remain high?

 The microprocessor checks the INTR line one clock
cycle before the last T-state of each instruction.
 The INTR must remain active long enough to allow
for the longest instruction.
 The longest instruction for the 8085 is the conditional
CALL instruction which requires 18 T-states.

 Therefore, the INTR must remain active for 17.5 T-

states.
 If f= 3MHZ then T=1/f and so, INTR must remain
active for [ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].

 How long can the INTR remain high?

 The INTR line must be deactivated before the EI is
executed. Otherwise, the microprocessor will be
interrupted again.
 Once the microprocessor starts to respond to an
INTR interrupt, INTA becomes active (=0).
Therefore, INTR should be turned off as soon as the
INTA signal is received.

Multiple Interrupts & Priorities
 How do we allow multiple devices to interrupt using the

INTR line?
 The microprocessor can only respond to one signal
on INTR at a time.
 Therefore, we must allow the signal from only one of
the devices to reach the microprocessor.
 We must assign some priority to the different devices
and allow their signals to reach the microprocessor
according to the priority.

Multiple Interrupts & Priorities using
Priority Encoder
 The solution is to use a circuit called the priority
encoder (74LS148).
 This circuit has 8 inputs and 3 outputs.
 The inputs are assigned increasing priorities
according to the increasing index of the input.
 Input 7 has highest priority and input 0 has the
lowest.
 The 3 outputs carry the index of the highest priority
active input.
Priority Encoder
 Note that the op codes for the different RST instructions
follow a set pattern.
 Bit D5, D4 and D3 of the op codes change in a
binary sequence from RST 7 down to RST 0.
 The other bits are always 1.
 This allows the code generated by the 74366 to

be used directly to choose the appropriate RST
instruction.
 The one draw back to this scheme is that the only way
to change the priority of the devices connected to the
74366 is to reconnect the hardware.
Priority Encoder

The 8085 Maskable/Vectored Interrupts
 The 8085 has 4 Masked/Vectored interrupt inputs.

 RST 5.5, RST 6.5, RST 7.5
 They are all maskable.
 They are automatically vectored according to the

following table:
 Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

The 8085 Maskable/Vectored Interrupts
 The vectors for these interrupt fall in between the

vectors for the RST instructions.
 That‟s why they have names like RST 5.5 (RST 5 and a
half).

Masking RST 5.5, RST 6.5 and RST 7.5
 These three interrupts are masked at two levels:

 Through the Interrupt Enable flip flop and the EI/DI
instructions.
 The Interrupt Enable flip flop controls the whole
maskable interrupt process.

 Through individual mask flip flops that control the
availability of the individual interrupts.
 These flip flops control the interrupts individually.

Interrupt Structure

The 8085 Maskable/Vectored Interrupt
Process
• The interrupt process should be enabled using the EI
instruction.
• The 8085 checks for an interrupt during the execution
of every instruction.
• If there is an interrupt, and if the interrupt is enabled
using the interrupt mask, the microprocessor will
complete the executing instruction, and reset the
interrupt flip flop.

The 8085 Maskable/Vectored Interrupt
Process
• The microprocessor then executes a call instruction
that sends the execution to the appropriate location in
the interrupt vector table.
• When the microprocessor executes the call
instruction, it saves the address of the next instruction
on the stack.
• The microprocessor jumps to the specific service
routine.
• The service routine must include the instruction EI to
re-enable the interrupt process.

Manipulating the Masks
 At the end of the service routine, the RET instruction

returns the execution to where the program was
interrupted.
 The Interrupt Enable flip flop is manipulated using the

EI/DI instructions.

Manipulating the Masks
 The individual masks for RST 5.5, RST 6.5 and RST 7.5
are manipulated using the SIM instruction.
 This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.

How SIM Interprets the Accumulator
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
MSE
SDO
R7.5
SDE
XXX
RST5.5 Mask 0 - Available
Serial Data Out RST6.5 Mask
RST7.5
} 1 - Masked
Mask
Enable Serial Data
0 - Ignore bit 7 Mask Set Enable
1 - Send bit 7 to SOD pin 0 - Ignore bits 0-2
1 - Set the masks according
to bits 0-2
Not Used Force RST7.5 Flip Flop to reset

SIM and the Interrupt Mask
 Bit 0 is the mask for RST 5.5

 Bit 1 is the mask for RST 6.5
 Bit 2 is the mask for RST 7.5.
 If the mask bit is 0, the interrupt is available.
 If the mask bit is 1, the interrupt is masked.

 Bit 3 (Mask Set Enable - MSE) is an enable for setting
the mask.
 If it is set to 0 the mask is ignored and the old settings
remain.
 If it is set to 1, the new setting are applied. The SIM
instruction is used for multiple purposes and not only for
setting interrupt masks.
 It is also used to control functionality such as Serial
Data Transmission.
 Therefore, bit 3 is necessary to tell the microprocessor
whether or not the interrupt masks should be modified
 The RST 7.5 interrupt is the only 8085 interrupt that has
memory.
 If a signal on RST7.5 arrives while it is masked, a flip
flop will remember the signal.
 When RST7.5 is unmasked, the microprocessor will
be interrupted even if the device has removed the
interrupt signal.
 This flip flop will be automatically reset when the
microprocessor responds to an RST 7.5 interrupt.

 Bit 4 of the accumulator in the SIM instruction allows
explicitly resetting the RST 7.5 memory even if the
microprocessor did not respond to it.
 Bit 5 is not used by the SIM instruction

Using the SIM Instruction to Modify the
Interrupt Masks
 Example: Set the interrupt masks so that RST5.5 is
enabled, RST6.5 is masked, and RST7.5 is enabled.

Interrupt Masks
First, determine the contents of the accumulator
 - Enable 5.5 bit 0 = 0
 - Disable 6.5 bit 1 = 1
 - Enable 7.5 bit 2 = 0
 - Allow setting the masks bit 3 = 1
 - Don‟t reset the flip flop bit 4 = 0
 - Bit 5 is not used bit 5 = 0
 - Don‟t use serial data bit 6 = 0
 - Serial data is ignored bit 7 = 0

Interrupt Masks
Contents of accumulator are: 0AH
 EI ; Enable interrupts including INTR
 MVI A, 0A ; Prepare the mask to enable RST 7.5, and
5.5, disable 6.5
 SIM ; Apply the settings RST masks

Triggering Levels
 RST 7.5 is positive edge sensitive.

 When a positive edge appears on the RST7.5
line, a logic 1 is stored in the flip-flop as a
“pending” interrupt.
 Since the value has been stored in the flip flop,
the line does not have to be high when the

microprocessor checks for the interrupt to be
recognized.
 The line must go to zero and back to one before a
new interrupt is recognized.

Triggering Levels
 RST 6.5 and RST 5.5 are level sensitive.

 The interrupting signal must remain present until
the microprocessor checks for interrupts.

Determining the Current Mask Settings
 RIM instruction: Read Interrupt Mask

 Load the accumulator with an 8-bit pattern showing
the status of each interrupt pin and mask.
RST7.5 Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
P6.5
P7.5
P5.5
SDI
IE
RST 6.5
M 6.5
RST 5.5
M 5.5
Interrupt Enable
MYcsvtu Notes Rungta College of Engg. & Technology Flip Flop 448
How RIM sets the Accumulator’s different
bits
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
P6.5
P7.5
P5.5
SDI
IE
RST5.5 Mask
Serial Data In RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked
RST7.5 Interrupt Pending

RST6.5 Interrupt Pending
RST5.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop

The RIM Instruction and the Masks
 Bits 0-2 show the current setting of the mask for each of
RST 7.5, RST 6.5 and RST 5.5
 They return the contents of the three mask flip
flops.
 They can be used by a program to read the mask
settings in order to modify only the right mask.

 Bit 3 shows whether the maskable interrupt process is
enabled or not.
 It returns the contents of the Interrupt Enable Flip
Flop.
 It can be used by a program to determine whether
or not interrupts are enabled.

 Bits 4-6 show whether or not there are pending

interrupts on RST 7.5, RST 6.5, and RST 5.5
 Bits 4 and 5 return the current value of the
RST5.5 and RST6.5 pins.

 Bit 6 returns the current value of the RST7.5
memory flip flop.

 Bit 7 is used for Serial Data Input.
 The RIM instruction reads the value of the SID
pin on the microprocessor and returns it in this
bit.

Pending Interrupts
 Since the 8085 has five interrupt lines, interrupts may

occur during an ISR and remain pending.
 Using the RIM instruction, it is possible to can read

the status of the interrupt lines and find if there are
any pending interrupts.

TRAP
 TRAP is the only non-maskable interrupt.

It does not need to be enabled because it cannot be
disabled.
 It has the highest priority amongst interrupts.
 It is edge and level sensitive.

TRAP
 It needs to be high and stay high to be recognized.
 Once it is recognized, it won‟t be recognized again
until it goes low, then high again.
 TRAP is usually used for power failure and emergency

shutoff.

The 8085 Interrupts
Interrupt Masking Triggering

Maskable Vectored Memory
Name Method Method
Level
INTR Yes DI / EI No No
Sensitive
RST 5.5 / DI / EI Level

Yes Yes No
RST 6.5 SIM Sensitive
DI / EI Edge
RST 7.5 Yes Yes Yes
SIM Sensitive
Level &
TRAP No None Yes No Edge
Sensitive
Interrupt Programs
 Enable all interrupts of 8085

 Sol- The SIM format will be
7 6 5 4 3 2 1 0
0
0
0
0
0

Interrupt Programs
 Program
 EI
 MVI A, 08 H
 SIM

Interrupt Programs
 Assume microprocessor is completing an RST 7.5

interrupt request, check to see if RST 6.5 is pending . If
it is pending enable RST 6.5 without affecting any other
interrupts, otherwise return to main program

Interrupt Programs
 Program
 RIM
 MOV B,A
 ANI 20H
 JNZ NEXT
 EI
 RET
 NEXT MOV A,B
 ANI 0D H
 ORI 08 H
 SIM
 RET
UNIT- V
ARCHITECTURE OF PERIPHERAL
INTERFACING DEVICES

Support devices for the 8085
 At the time of introduction of the 8085, several

additional support devices were introduced to enable
the „85 to be adapted to a great variety of system
organizations.
 A few are listed here.

Support devices for the 8085
 8155-RAM+ 3 I/O Ports+Timer

 8251-Communication Controller
 8253-Programmable Interval Timer
 8254-Programmable Interval Timer
 8255-Programmable Peripheral Interface
 8257-DMA Controller
 8259-Programmable Interrupt Controller
 8279-KeyBoard/Display Controller
 8755-EPROM+2 I/O Ports
8355/8755 Multifunction Device (memory
+IO)
 Features
 2kbytes ROM(8355) / EPROM(8755)
 Two bidirectional 8 bit I/O ports
 Each port line individually programmable for I or O
 Internal AD demux using ALE
 Generates ready signal
 Separate control lines for I/O section

Block diagram- 8355/8755
 Vdd=25V for programming EPROM

 Vcc=5V, Vss=0V

8355/8755
 8085ROMI/OLSI 8355 for the 8085 circuit has been

designed around ROM and parallel I / O ports are
integrated in the LSI. 80858088
 Address and data bus interfaces directly by the state
because they can more 8085 to 8088 can also be
applied.
 ROM8755UV EPROM 8355 mask ROM, 8755 is a built-
in UV EPROM.

8355/8755
 Port and DDR

addresses
A1 A0 Port/DD
R
0 0 Port A
0 1 Port B
1 0 DDR A
1 1 DDR B

8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS
RECEIVER TRANSMITTER (USART)
 The 8251 is a USART (Universal Synchronous

Asynchronous Receiver Transmitter) for serial data
communication.
 As a peripheral device of a microcomputer system, the
8251 receives parallel data from the CPU and transmits
serial data after conversion.
 This device also receives serial data from the outside
and transmits parallel data to the CPU after conversion.

Block diagram of the 8251 USART

8251 USART
 The 8251 functional configuration is programmed by

software.
 Operation between the 8251 and a CPU is executed by
program control.
 Table shows the operation between a CPU and the
device.

8251 USART
 Control Words
 There are two types of control word.

 1. Mode instruction (setting of function)
 2. Command (setting of operation)

8251 USART
 Mode Instruction
 Mode instruction is used for setting the function of the
8251. Mode instruction will be in "wait for write" at either
internal reset or external reset. That is, the writing of a
control word after resetting will be recognized as a
"mode instruction."
 Items set by mode instruction are as follows:
 • Synchronous/asynchronous mode
 • Stop bit length (asynchronous mode)
 • Character length Rungta College of Engg. & Technology 473
MYcsvtu Notes
8251 USART
 Parity bit
 Baud rate factor (asynchronous mode)
 Internal/external synchronization (synchronous mode)
 Number of synchronous characters (Synchronous
mode)

8251 USART
 The bit configuration of mode instruction is shown in
Figures.
 In the case of synchronous mode, it is necessary to
write one-or two byte sync characters.
 If sync characters were written, a function will be set
because the writing of sync characters constitutes part
of mode instruction.

8251 USART-Bit configuration of mode instruction
(Asynchronous)

8251 USART-Bit configuration of mode instruction
(Synchronous)

8251 USART
 Command
 Command is used for setting the operation of the 8251.
It is possible to write a command whenever necessary
after writing a mode instruction and sync characters.

8251 USART
 Items to be set by command are as follows:
 Transmit Enable/Disable
 Receive Enable/Disable
 DTR, RTS Output of data.
 Resetting of error flag.
 Sending to break characters
 Internal resetting
 Hunt mode (synchronous mode)

8251 USART-Bit configuration of command
word

8251 USART
 Status Word
 It is possible to see the internal status of the 8251 by

reading a status word.
 The bit configuration of status word is shown in Fig

8251 USART-Bit configuration of status word

8251 USART Pin Description
 D 0 to D 7 (l/O terminal)
 This is bidirectional data bus which receive control
words and transmits data from the CPU and sends
status words and received data to CPU.
 RESET (Input terminal)

 A "High" on this input forces the 8251 into "reset
status."
 The device waits for the writing of "mode instruction."
 The min. reset width is six clock inputs during the
operating status of CLK.
 CLK (Input terminal)

 CLK signal is used to generate internal device timing.
CLK signal is independent of RXC or TXC.
 However, the frequency of CLK must be greater than 30
times the RXC and TXC at Synchronous mode and
Asynchronous "x1" mode, and must be greater than 5
times at Asynchronous "x16" and "x64" mode.

 WR (Input terminal)
 This is the "active low" input terminal which receives a
signal for writing transmit data and control words from
the CPU into the 8251.
 RD (Input terminal)
 This is the "active low" input terminal which receives a
signal for reading receive data and status words from
the 8251.

 C/D (Input terminal)

 This is an input terminal which receives a signal for
selecting data or command words and status words
when the 8251 is accessed by the CPU. If C/D = low,
data will be accessed. If C/D = high, command word or
status word will be accessed.

 CS (Input terminal)
 This is the "active low" input terminal which selects the
8251 at low level when the CPU accesses.
 Note: The device won‟t be in "standby status"; only
setting CS = High.

 TXD (output terminal)

 This is an output terminal for transmitting data from
which serial-converted data is sent out.
 The device is in "mark status" (high level) after resetting
or during a status when transmit is disabled.
 It is also possible to set the device in "break status" (low
level) by a command.

 TXRDY (output terminal)

 This is an output terminal which indicates that the
8251is ready to accept a transmitted data character.
 But the terminal is always at low level if CTS = high or
the device was set in "TX disable status" by a
command.
 Note: TXRDY status word indicates that transmit data
character is receivable, regardless of CTS or command.
 If the CPU writes a data character, TXRDY will be reset
by the leading edge or WR signal.
 TXEMPTY (Output terminal)

 This is an output terminal which indicates that the 8251
has transmitted all the characters and had no data
character.
 In "synchronous mode," the terminal is at high level, if
transmit data characters are no longer remaining and
sync characters are automatically transmitted.
 If the CPU writes a data character, TXEMPTY will be
reset by the leading edge of WR signal.

 Note : As the transmitter is disabled by setting CTS

"High" or command, data written before disable will be
sent out.
 Then TXD and TXEMPTY will be "High". Even if a data
is written after disable, that data is not sent out and TXE
will be "High".
 After the transmitter is enabled, it sent out.

 TXC (Input terminal)

 This is a clock input signal which determines the
transfer speed of transmitted data.
 In "synchronous mode," the baud rate will be the same
as the frequency of TXC.
 In "asynchronous mode", it is possible to select the
baud rate factor by mode instruction.
 It can be 1, 1/16 or 1/64 the TXC.
 The falling edge of TXC sifts the serial data out of the
8251.
 RXRDY (Output terminal)

 This is a terminal which indicates that the 8251 contains
a character that is ready to READ.
 If the CPU reads a data character, RXRDY will be reset
by the leading edge of RD signal.
 Unless the CPU reads a data character before the next
one is received completely, the preceding data will be
lost.
 In such a case, an overrun error flag status word will be
set.
 RXD (input terminal)

 This is a terminal which receives serial data.
 RXC (Input terminal)
 This is a clock input signal which determines the
transfer speed of received data.
 In "synchronous mode," the baud rate is the same as
the frequency of RXC.
 In "asynchronous mode," it is possible to select the
baud rate factor by mode instruction. It can be 1, 1/16,
1/64 the RXC.
 SYNDET/BD (Input or output terminal)

 This is a terminal whose function changes according to
mode.
 In "internal synchronous mode." this terminal is at high
level, if sync characters are received and synchronized.
 If a status word is read, the terminal will be reset.
 In "external synchronous mode, "this is an input
terminal.

 A "High" on this input forces the 8251 to start receiving

data characters.
 In "asynchronous mode," this is an output terminal
which generates "high level“ output upon the detection
of a "break" character if receiver data contains a "low-
level" space between the stop bits of two continuous
characters.
 The terminal will be reset, if RXD is at high level. After
Reset is active, the terminal will be output at low level.

 DSR (Input terminal)

 This is an input port for MODEM interface.
 The input status of the terminal can be recognized by
the CPU reading status words.
 DTR (Output terminal)

 This is an output port for MODEM interface.
 It is possible to set the status of DTR by a command.

 CTS (Input terminal)

 This is an input terminal for MODEM interface which is
used for controlling a transmit circuit.
 The terminal controls data transmission if the device is
set in "TX Enable" status by a command.
 Data is transmittable if the terminal is at low level.
 RTS (Output terminal)
 This is an output port for MODEM interface.
 It is possible to set the status RTS by a command.
8255 Programmable Peripheral Interface
 The Intel 8255 (or i8255) Programmable Peripheral
Interface chip is a peripheral chip originally developed
for the Intel 8085 microprocessor, and as such is a
member of a large array of such chips, known as the
MCS-85 Family.
 This chip was later also used with the Intel 8086 and its
descendants.
 It was later made (cloned) by many other
manufacturers.

 Are in DIP 40 and PLCC 44 pins encapsulated versions.
 This chip is used to give the CPU access to

programmable parallel I/O, and is similar to other such
chips like the Motorola 6520 PIA (Peripheral Interface
Adapter) the MOS Technology 6522 (Versatile Interface
adapter) and the MOS Technology CIA (Complex
interface Adapter) all developed for the 6502 family.
 Other such chips are the 2655 Programmable

 Peripheral Interface from the Signetics 2650 family of
microprocessors, the 6820 PIO
 (Peripheral Input/Output) from the Motorola 6800 family,

the Western Design Center WDC 65C21, an enhanced
6520, and many others.
 The 8255 are used in home computers as SV-328 and

all MSX, but is perhaps most well known for its use in
the original IBM-PC's parallel printer port (now largely
defunct and replaced by the USB standard, and
considered a legacy port).
 However, most often the functionality the 8255 offered

is now not implemented with the 8255 chip itself
anymore, but is embedded in a larger VLSI chip as a
sub function.
 The 8255 chip itself is still made, and is sometimes

used together with a micro controller to expand its I/O
capabilities.

8255 PPI- Pin diagram

8255 PPI
 Features:
 3 8-bit IO ports PA, PB, PC
 PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for
mode 0 and for BSR.
 Modes 1 and 2 are interrupt driven.
 PC has 2 4-bit parts: PC upper (PCU) and PC lower
(PCL), each can be set independently for I or O.
 Each PC bit can be set/reset individually in BSR mode.

8255 PPI
 PA and PCU are Group A (GA) and PB and PCL are

Group B (GB)
 Address/data bus must be externally demux'd.
 TTL compatible.
 Improved dc driving capability

8255 PPI
 Block diagram


8255 PPI
 The 8255A is a programmable peripheral interface (PPI)

device designed for use in Intel microcomputer
systems.
 Its function is that of a general purposes I/O component
to Interface peripheral equipment to the microcomputer
system bush.
 The functional configuration of the 8255A is
programmed by the systems software so that normally
no external logic is necessary to interface peripheral
devices or structures.

8255 PPI
 Data Bus Buffer

 This 3-stable bi-directional 8-bit buffer is used to
interface the 8255A to the systems data bus.
 Data is transmitted or received by the buffer upon
execution of input or output instructions by the CPU.
 Control words and status information are also
transferred through the data bus buffer.

8255 PPI
 Read/Write and Control Logic

 The function of this block is to manage all of the Internal
and External transfers of both Data and Control or
Status words.
 It accepts inputs from the CPU Address and Control
business and in turn, issues commands to both of the
Control Groups.

8255 PPI
 (CS) Chip Select

 A “low‟ on this input pin enables the communication
between the 8255A, and the CPU.
 (RD) Read.
 A “low” on this Input pin enables the 8255A to send the
data or status information to the CPU on the data bus.
 In essence, it allows the CPU to “read from the 8255A.

8255 PPI
 (WR) Write.
 A “ low” on the input pin enables the CPU to write data
or control words into the 8255A.
 (A0 and A1)

 Port Select 0 and Port Select 1.
 The Input signals, in conjunction with the RD and WR
Inputs, controls the selection of one of the three ports or
the control word registers.
 They are normally connected to the least significant bits
of the address bus (A0 and A1).
8255 PPI
 (RESET)
 Reset
 A “high” on this Input clears the control register and all
ports (A, B, C) are set to the Input mode

8255 PPI
 Group A and Group B Controls

 The functional configuration of each port is programmed
by the systems software.
 In essence, the CPU “output” a control word to the
8255A.
 The control word contains information such as “mode”,
bit set”, bit reset”, etc. that Initializes the functional
configuration of the 8255A.

8255 PPI
 Each of the Control blocks (Group A and Group B)

accepts commands from the Read/Write Control Logic,
receives control words from the internal data bus and
issues the proper commands to its associated ports.

8255 PPI
 Control Group A –
 Port A and Port C upper (C7 C4)
 Control Group B – Port B and Port C lower (C3 C0)
 The Control Word Register can only be written into.

 No Read operation of the Control Word Register is
allowed.

8255 PPI
 Ports A, B, and C
 The 8255A contains three 8-bit ports (A , B, and C).
 All can be configured in a wide variety of functional

characteristics by the system software but each has its
own special features or personally to further enhance
the power and flexibility of the 8255A.

8255 PPI
 Port A- One 8 bit data output latch/buffer and one 8-bit
data input latch.
 Port B - One 8-bit data output latch/buffer and one 8-bit
data input buffer.
 Port C-One 8-bit data output latch/buffer and one 8-bit
data input buffer (no latch for input).
 This port can be divided into two 4-bit ports under the
mode control.
 Each 4-bit port contains a 4-bit latch and it can be used
for the controls signal outputs and status signal inputs in
conjunction with ports A and B.

8255A OPERATIONAL DESCRIPTION
 Mode Selection
 There are three basic modes of operation that can be
selected by the systems software:
 Mode 0 – Basic Input/Output
 Mode 1 – Strobed Input/Output
 Mode 2 – Bi-Directional Bus

 When the reset Input goes “high” all ports will be set to
the Input mode (i.e., all 24 lines will be in the high
Impedance state).
 After the reset is removed the 8255A can remain in the
input mode with no additional Initialization required.
 During the execution of the systems program any of the
other modes may be selected using a single output
Instruction.
 This allows a single 8255A to service a variety of
peripheral devices with a simple software maintenance
routine.
 The modes for Ports A and Port B can be separately

defined, while Port C is divided into two portions as
required by the Port A and Port B definitions.
 All of the output registers, including the status flip-flops,
will be reset whenever the mode is changed.
 Modes may be combined so that their functional
definition can be “tailored” to almost any I/O stricture.
 For instance; Group B can be programmed in Mode 0 to
monitor simple switch closing or display computational
results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-
driven basis.


 The Mode definitions and possible mode combinations

may seem confusing at first but after a cursory review of
the complete device operation a simple , logical I/O
approach will surface.
 The design of the 8255A has taken into account things
such as efficient PC board layout, control signal
definition vs PC layout and complete functional
flexibility to support almost any peripheral device with
no use of the available pints.

 Single Bit Set/Reset Feature

 Any of the eight bits of Port C can be Set or Reset using
a single OUT put Instruction.
 This feature reduces software requirements in Control-
based applications.
 When Port C is being used as status/control for Port A
or B.These Bits can be set or reset by using the Bit
set/reset operation just as if they were data output port.


 Interrupt Control Functions

 When the 8255A is programmed to operate in mode 1
or mode 2, control signals are provided that can used
as interrupt request input to the CPU.
 The interrupt request signal generated from port C, can
be inhibited or enabled by setting or resetting the
associated INTE flip-flop, using the bit set/reset function
of port C.
 This function allows the Programmer to disallow or
allow a specific I/O device to interrupt the CPU without
affecting any other device in the interrupt structure.

 INTE flip-flop definition

 (BIT-SET) – INTE is SET – Interrupt enable
 (BIT-RESET) – INTE is RESET – Interrupt disable
 Note: All Mask flip-flops are automatically reset during
mode selection and device reset.

8255A Operating Modes
 Operating Modes
 Mode 0 (Basic Input/Output).
 This functional configuration provides simple input
operations for each of the three ports.
 No “handshaking” is required data is simply written to
or read from a specified port.

 Basic Functional Definitions:

 Two 8-bit ports and two 4-bit port
 Any port can be input or output.
 Outputs are not latched.
 Inputs are not latched.
 16 different Input/output configurations are not possible
in this Mode.

 MODE 1 (Strobed Input/Output).

 This functional configuration provides a means for
transferring I/O data to or from a specified port in
conjunction with strobes or “handshaking” signals. In
mode 1, port A and Port B use the lines on port C to
generate or accept these “handshaking” signals.


 Two groups (Group A and Group B)
 Each group contains one 8-bit data port and one 4-bit
control/data port
 The 8-bit data port can be either Inputs or output Both
inputs and outputs are latched.
 The 4-bit port is used for control and status of the 8-bit
data port.

 Input Control Signal Definition

 STB (Strobe Input).
 A “ low “ on the input loads data into the input latch.
 IBF (Input Buffer Full F/F)

 A “high” on this output indicates that the data has been
loaded into the input latch.
 In essence, an acknowledgement.
 IBF is set by STB input being low and is reset by the
rising edge of the RD input.

 INTR (Interrupt Request)

 A “high” on this output can be used to interrupt the CPU
when an input device is requesting service, INTR is set
by the STB is a “one”, IBF is a “one “ and INTE is “one
“.
 It is reset by the falling edge of RD.
 This procedure allows an input device to request
service from the CPU by simply strobing its data into
port.
 INTE A Controlled by bit set/reset of PC4
 INTE B Controlled by set/reset PC2

 Output Control Signal Definition
 OBF (Output Buffer Full F/F).

 The OBF output will go “low” to indicate that the CPU
has written data out to the specified port.
 The OBF F/F will be set by rising edge of the WR input
being low. ACK (Acknowledge Input).
 A “low” on this input informs the 8255A that the data
from port A or port B has been accepted.
 In essence, a response from the peripheral device

indicating that it has received the data output by
CPU. INTR (Interrupt Request).
 A “high” on the output can be used to interrupt the CPU
when an output device has accepted data transmitted
by the CPU. INTR is set when ACK is a “one”, OBF is a
“one”, and INTE is a “one”.
 It is reset by the falling edge of WR.
 INTE A - Controlled by bit set/reset of PC6.
 INTE B - Controlled by bit set/reset of PC2.

 Combination of MODE 1 Port A and B can be

Individually defined as Input or output in Mode 1 to
support a wide variety of strobed I/O application.

 Mode 2 (Strobed Bidirectional Bus I/O).
 This functional configuration provides a means for

communicating with a peripheral device or structure on
a single 8-bit bus for both transmitting and receiving
data (bi-directional bus I/O).
 “Handshaking” signals are provided to maintain proper
bus flow discipline in a similar manner to MODE.1.
 Interrupt generation and enable/disable functions are
also available.


 Used in Group A only.
 One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C).
 Both Inputs and Outputs are latched.
 The 5-bit control port (Port C) is used for control and
status for the 8-bit,bi-directional bus port (Port A).

 Bi-directional Bus I/O Control Signal Definition
 INTR (Interrupt Request).

 A high on this output can be used to interrupt the CPU
for both input or output operations.

 Output Operations
 OBF (Output Buffer Full).
 The OBF output will go “low” to indicate that the CPU
has written data out to port A. ACK (Acknowledge).
 A “low” on this input enables the tri-state output buffer of
port A to send out the data.
 Otherwise, the output buffer will be in the high
impedance state. INTE 1 (The INTE Flip-Flop
Associated with OBF).
 Controlled by bit set/reset of PC6
 Input Operations
 STB (Strobe Interrupt) STB (Strobed Input).
 A “low” on this input loads data into the input latch.
 IBF (Input Buffer Full F/F).
 A “high” on this output indicates that data has been
loaded into the input latch.
 INTE 2 (The INTE Flip-Flop Associated with IBF).
 Controlled by bit set/reset of PC4.

A1 A0 Select
0 0 PA
0 1 PB
1 0 PC
1 1 CONTROL
REGISTER
 BSR mode
 Bit set/reset, applicable
to PC only. One bit is
S/R at a time.
 Control word:
D7 D6 D5 D4 D3 D2 D1 D0
0(0=B X X X B2 B1 B0 S/R(
SR) S=1,
R=0)

 I/O mode
D7 D6 D5 D4 D3 D2 D1 D0
1 GA mode select PA PCU GB PB PCL

(1=I/O) mode
select

 D6, D5: GA mode select:

00 = mode0

 01 = mode1
 1X = mode2
 D4(PA), D3(PCU): 1=input 0=output
 D2: GB mode select: 0=mode0 1=mode1
 D1(PB), D0(PCL): 1=input 0=output

 Mode 0: No interrupts. Plain I/O.

 Two 8 bit ports PA, PB.
 Two 4 bit ports PCU and PCL. Outputs latched, inputs
buffered.
 Mode 1
 (Input and output data are latched)

 PC bits in input mode:

D7 D6 D5 D4 D3 D2 D1 D0
PC7 PC6 IBF-A INTE-A / INTR-A INTE-B / IBF-B INTR-B
STB-A- STB-B-
bar bar
PC BITS IN OUTPUT MODE

OBF-A- INTE-A / PC5 PC4 INTR-A INTE-B / OBF-B- INTR-B
bar ACK-A- ACK-B- bar
bar bar

 Input mode:
 D4, D2: Set/Reset INTE using BSR. STB-bar input is
connected to external peripheral's strobe output (i.e.
PC2, PC4 pin to external strobe).
 INTE is internal connection. STB-bar is external

connection.

 Output mode:
 D6, D2: Set/Reset INTE using BSR. ACK-bar input is
connected to external peripheral's acknowledge output
(i.e. PC2, PC6 pin to external ack).
 INTE is internal connection. ACK-bar is external

connection.

 Mode 2
 Only for PA
 Status:
D7 D6 D5 D4 D3 D2 D1 D0
OBF- INTE IBF-A INTE INTR X X X
A-bar 1(O/P 2(I/P) -A
)/ /
ACK- STB-
A- A-Bar
BAR

Programmable Keyboard/Display Interface -
8279
 A programmable keyboard and display interfacing chip.
 Scans and encodes up to a 64-key keyboard.
 Controls up to a 16-digit numerical display.
 Keyboard has a built-in FIFO 8 character buffer.
 The display is controlled from an internal 16x8 RAM that

stores the coded display information.

PIN DIAGRAM OF 8279

Pin out Definition of 8279
 A0: Selects data (0) or control/status (1) for reads and

writes between micro and 8279.
 BD: Output that blanks the displays.
 CLK: Used internally for timing. Max is 3 MHz.
 CN/ST: Control/strobe, connected to the control key on
the keyboard.
 CS: Chip select that enables programming, reading the
keyboard, etc.
 DB7-DB0: Consists of bidirectional pins that connect to
data bus on micro.

 IRQ: Interrupt request, becomes 1 when a key is

pressed, data is available.
 OUT A3-A0/B3-B0: Outputs that sends data to the most
significant/least significant nibble of display.
 RD(WR): Connects to micro's IORC or RD signal, reads
data/status registers.
 RESET: Connects to system RESET.

 RL7-RL0: Return lines are inputs used to sense key

depression in the keyboard matrix.
 Shift: Shift connects to Shift key on keyboard.
 SL3-SL0: Scan line outputs scan both the keyboard and
displays.

Keyboard Interface of 8279

 The keyboard matrix can be any size from 2x2 to 8x8.

 Pins SL2-SL0 sequentially scan each column through a
counting operation.
 The 74LS138 drives 0's on one line at a time.
 The 8279 scans RL pins synchronously with the
scan.
 RL pins incorporate internal pull-ups, no need for
external resistor pull-ups.

 D7 D6 D5 Function Purpose
 000 Mode set Selects the

number of display
positions, type of
key scan
 001 Clock Programs internal
clk, sets scan and
debounce times.
 010 Read FIFO Selects type
of FIFO read and address of
the read.
 D7 D6 D5 Function Purpose
 011 Read Display Selects type of
display read and address
 of the read.
 100 Write Display Selects type of write and
address of the write.
 101 Display write inhibit Allows half-
bytes to be blanked.
 110 Clear Clears the display or FIFO
 111 End interrupt Clears the IRQ signal to
microprocessor

 First three bits given below select one of 8 control

registers (opcode).
 000DDMMM
 Mode set: Opcode 000.
 DD sets displays mode.
 MMM sets keyboard mode.
 DD field selects either:

 8- or 16-digit display
 Whether new data are entered to the rightmost or
leftmost display position
 DD Function
 00 8-digit display with left entry
 01 16-digit display with left entry
 10 8-digit display with right entry
 11 16-digit display with right entry

MMM field:

 DD Function
 000 Encoded keyboard with 2-key lockout
 001 Decoded keyboard with 2-key lockout
 010 Encoded keyboard with N-key rollover
 011 Decoded keyboard with N-key rollover
 100 Encoded sensor matrix101Decoded
sensor matrix
 110 Strobed keyboard, encoded display scan
 111 Strobed keyboard, decoded display scan
 Encoded: Sl outputs are active-high, follow binary bit

pattern 0-7 or 0-15.
 Decoded: SL outputs are active-low (only one low at
any time).
 Pattern output: 1110, 1101, 1011, 0111.
 Strobed: An active high pulse on the CN/ST input pin

strobes data from the RL pins into an internal FIFO
for reading by micro later.


 2-key lockout/N-key rollover: Prevents 2 keys from

being recognized if pressed simultaneously/Accepts
all keys pressed from 1st to last.

 001PPPPP
 The clock command word programs the internal
clock driver.
 The code PPPPP divides the clock input pin (CLK) to
achieve the desired operating frequency, e.g.
100KHz requires 01010 for a 1 MHz CLK input.
 010Z0AAA
 The read FIFO control word selects the address
(AAA) of a keystroke from the FIFO buffer (000 to
111).
 Z selects auto-increment for the address.
 011ZAAAA
 The display read control word selects the read
address of one of the display RAM positions for
reading through the data port.
 100ZAAAA
 Selects write address -- Z selects auto-increment so
subsequent writes go to subsequent display
positions.
 1010WWBB
 The display write inhibit control word inhibits writing
to either the leftmost 4 bits of the display (left W) or
rightmost 4 bits.
 BB works similarly except that they blank (turn off)
half of the output pins.

 1100CCFA
The clear control word clears the display, FIFO or

both.
 Bit F clears FIFO and the display RAM status, and
sets address pointer to 000.
 If CC are 00 or 01, all display RAM locations
become 00000000.
 If CC is 10, --> 00100000, if CC is 11, -->
11111111.
 1110E000 -End of Interrupt control word is issued to
clear IRQ pin in sensor matrix mode.
 Clock must be programmed first. If 3.0 MHz drives CLK

input, PPPPP is programmed to 30 or 11110.
 Keyboard type is programmed next.

 The previous example illustrates an encoded
keyboard, external decoder used to drive matrix.
 Program the FIFO.

 Once done, a procedure is needed to read data from

the keyboard.
 To determine if a character has been typed, the
FIFO status register is checked.
 When this control port is addressed by the IN
instruction, the contents of the FIFO status word is
copied into register AL:


 Code given in text for reading keyboard.
 Data returned from 8279 contains raw data that need to

be translated to ASCII:

 Row and column number are given the rightmost 6

bits (scan/return).
 This can be converted to ASCII using the XLAT
instruction with an ASCII code lookup table.
 The CT and SH indicate whether the control or shift
keys were pressed.
 The Strobed Keyboard code is just the state of the
RLx bits at the time a 1 was `strobed' on the strobe
input pin.

Six Digit Display Interface of 8279

Programmable Interval Timer: 8254/8253
 Three independent 16-bit programmable counters

(timers).
 Each capable in of counting in binary or BCD with a
maximum frequency of 10MHz.
 Used for controlling real-time events such as real-time

clock, events counter, and motor speed and direction
control.

Programmable Interval Timer: 8254/8253
 Usually decoded at port address 40H-43H and has

following functions:
 Generates a basic timer interrupt that occurs at
approximately 18.2Hz.
 Interrupts the micro at interrupt vector 8 for a clock
tick.
 Causes DRAM memory system to be refreshed.
 Programmed with 15us on the PC/XT.
 Provides a timing source to the internal speaker and
other devices
8253/54 Functional Description

8253/54 Pin Definitions
 A1, A0:
 The address inputs select one of the four internal
registers with the 8254 as follows:

 CLK: The clock input is the timing source for each of the
internal counters.
 It is often connected to the PCLK signal from the bus
controller.
 CS: Chip Select enables the 8254 for programming, and
reading and writing.
 G: The gate input controls the operation of the counter
in some modes.

 OUT: A counter output is where the wave-form

generated by the timer is available.
 RD/WR: Read/Write causes data to be read/written

from the 8254 and often connects to the IORC/IOWC.

8253/54 Programming
 Each counter is individually programmed by writing a

control word, followed by the initial count.
 The control word allows the programmer to select the

counter, model of operation, binary or BCD count and
type of operation (read/write

8253/54 Programming

8253/54 Programming
 Each counter may be programmed with a count of 1 to

FFFFH.
 Minimum count is 1 all modes except 2 and 3 with
minimum count of 2.
 Each counter has a program control word used to select

the way the counter operates.
 If two bytes are programmed, then the first byte
(LSB) stops the count, and the second byte (MSB)
starts the counter with the new count.
8253/54 Modes
 There are 6 modes of operation for each counter:

 Mode 0: An events counter enabled with G.
 The output becomes a logic 0 when the control word
is written and remains there until N plus the number
of programmed counts.

8253/54 Modes
 Mode 1: One-shot mode.

 The G input triggers the counter to output a 0 pulse
for `count' clocks.
 Counter reloaded if G is pulsed again.

8253/54 Modes
 Mode 2: Counter generates a series of pulses 1 clock

pulse wide.
 The separation between pulses is determined by the
count.
 The cycle is repeated until reprogrammed or G pin
set to 0.

8253/54 Modes
 Mode 3: Generates a continuous square-wave with G

set to 1.
 If count is even, 50% duty cycle otherwise OUT is
high 1 cycle longer.

8253/54 Modes
 Mode 4: Software triggered one-shot (G must be 1).

8253/54 Modes
 Mode 5:
 Hardware triggered one-shot.
 G controls similar to Mode 1.

8253/54 Program
 Explain the 8253 control word format and set up the

8253 as a square wave generator with 1 ms period if
the input frequency to the 8253 is 1 MHz

8253/54 Program
 Sol-
 Assume counter 0 is used to generate the square wave
and the addresses of counter 0 = 10 H and the control
register is 13 H
 The output period required is 1 ms.The input frequency

is 1 MHz, so input period = 1 micro secs.

8253/54 Program
 Count value = Required period/Input period

 = 1 ms/ 1 micro secs= (1000)d
 The control word format to initialize counter 0, 16 bit
counter, BCD counting and square wave generator
mode will be as follows

8253/54 Program
7 6 5 4 3 2 1 0
1
0
1
1
0
1
1
0
BCD counting
Select counter 0
Mode 3 square
wave generator
Select counter 0
load lsb first then msb Read load lsb first then msb

8253/54 Program
 The 8253 initialization program will be as follows-

 MVI A, 37H
 OUT 13 H
 MVI A, 00H
 OUT 10 H
 MVI A, 10H
 OUT 10 H

8155 RAM
 256* 8 BIT WORDS

 Single +5 volt power supply
 Complete static operation
 Internal address latch
 2 programmable 8 bit I/O ports
 1 programmable 6 bit I/O ports
 Programmable 14 bit binary counter
 Multiplexed address and data bus

General Description of 8155
 8155 are RAM chips to be used with 8085

 The RAM portion is designed with 2K bit static cell
organized as 256 *8
 They have a maximum access time 400 ns to permit
use with no wait states in 8085 CPU.
 8155 has maximum access time of 300ns for use with
the 8085.
 The I/O portion consists of three general purpose I/O
ports.
General Description of 8155
 One of the three ports can be programmed to be status

pins, thus allowing the other two ports to operate in
handshake mode.
 A 14 bit programmable counter/timer is also included on
chip to provide either a square wave or terminal count
pulse for the CPU system depending on timer mode.

Block Diagram of 8155

Pin Diagram of 8155

Pin Description of 8155
 Reset (I)
 The reset signal is a pulse provided by 8085 to initialize
the system.
 Input high on this line resets the chip and initializes the
three I/O ports to input mode.
 The width of reset pin should typically be 600ns.

 AD0-AD7(I/O)
 These are three address or data lines that interface with
the CPU lower 8 bit data/address bus.
 The 8 bit address is latched into the address latch on
the falling edge of the ALE.
 The address can be either for the memory section or
the I/O section depending on the polarity of IO/M(bar)
signal

 The 8 bit data is either written into the chip or read from
the chip depending on the status of write and read
input signals
 CE(bar) (I)
 Chip enable
 This pin is active low

 RD(I)
 Input low on this line with the chip enable active enables
the AD0-7 buffers,
 If IO/M(bar) is low the RAM content will be read out to
the AD bus.
 Otherwise the content of the selected I/O port will be
read to the AD bus.

 WR(I)-
 Input low on this line with the chip enable active causes
the data on the AD lines to be written to the Ram or I/O
ports depending on the polarity of IO/M(bar)

 ALE(I)
 Address latch enable
 This control signal latches the address on the AD0-7
lines and the state of the chip enable and IO/M(bar) into
the chip at the falling edge of ALE.

 IO/M (bar) (I)
 IO/ memory select

 This line selects the memory if low and selects the IO if
high
 PA0-PA7(I/O)
 These 8 lines are general purpose IO lines.

 The in out direction is selected by programming the

command and status register
 PB0-PB7
 These 8 lines are general purpose IO lines.
 The in out direction is selected by programming the
command and status register

 PC0-PC5(I/O)
 These 6 pins can function as either input port , output
port or as control signal for Pa and PB.
 Programming is done through the C/S register
 When they are used as control signals they will provide
the following

 PC0- intr (port a interrupt)

 PC1- bf (port a buffer full)
 PC2- strobe (bar)-(port a strobe)
 PC3- intr (port b interrupt)
 PC4- bf (port b buffer full)
 PC5- strobe (bar)-(port b strobe)

 Timer in (I)
 This is the timer input to the control timer
 Timer out (O)

 this pin is the timer output
 this output can be either a square wave or a pulse
depending on the timer mode

 VCC(I)
 +5 volt power supply
 VSS
 Ground reference

Programming information
 The command register

 It consists of 8 latches, one for each bit
 Four bits(0-3) define the mode of the ports.
 Two bits(4-5) enable or disable the interrupts from port
C when it acts as control port.
 The last two bits are for timer.
 The C/S register contents can be altered at any time by
using the I/O address xxxxx000 during a write operation

Programming information
 Status register
 It consists of seven latches, one for each bit.
 6 bits(0-5) for the status of the port.
 One (6) for the status of the timer.
 The status of the timer and IO section can be polled by
reading the C/S register.

Timer section
 The timer is 14bit counter that counts the timer input

pulses.
 It provides a square wave or a pulse when terminal
count (TC) is reached.
 The timer has the IO address xxxxx100 for the lower
order byte of the register and the IO address xxxxx101
for the higher order byte of the register

Timer section
 Tp program the timer the count length register is loaded

first one byte at a time by selecting the timer addresses.
 Bits 0-13 will specify the length of the next count and
bits 14-15 will specify the timer output mode.
 The valve loaded into the count length register can have
any value from 2h through 3FFF h in bits 0-13

Timer section
 There are four modes to choose from-

 0- puts out low during the second half of the count
 1-square wave
 2-single pulse upon TC being reached
 3-repetitive single pulse every time TC is readied and
automatic reload of counter upon TC being reached un
till instructed to stop by a new command loaded into
C/S

Timer section
 Bits 6-7 of the C/S register are used to start and stop
the counter
 C/S7 C/S6 Function
0 0- NOP
0 1- STOP
1 0- STOP AFTER TC
1 1- START

Timer section
 Timer format

Timer section
 M2 and M1 define the timer mode as follows-
 M2 M1 Function
 0 0 Puts out low during
second half of the count.
 0 1 Square wave ie the
period of the square
equals the count length
programmed with
automatic reload at
terminal count
 1 0 Single pulse upon TC being
reached
 1 1 Automatic reload ie single pulse
every time TC being reached

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MICROPROCESSOR & INTERFACES

(CSE & IT SEM -V)

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 A microprocessor is a programmable digital electronic

 One or more typically serve as the CPU in computer

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 That means your laptop at home and the PC in your

 The advent of the microprocessor astounded many

 It was an entire computation engine on one tiny chip.

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 This is 100,000 times the number of transistors than

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 The Intel 4004 microprocessor was produced on 2" wafers

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 The Intel 4004 microprocessor is unique in that, if it is

 The 4004 microprocessor is composed of 5 layers.

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 The microprocessor reduced the word size of the CPU

 Before the microprocessor, electronic CPUs were

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 The evolution of microprocessors has been known to

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 This has held true throughout the years……………….

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 Microprocessors forever changed the way that

 This breakthrough invention powered the calculator and

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 Without this amazing invention, we would not be as

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 4 bit data bus.

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 Clock speed300 kHz

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 Number of transistors: Intel

6200. 5 MHz Intel

 Packaging: 40 pin 6 MHz Intel HMOS

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 The typical processor system consists of:

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