6 5 4 3 2 1

U1001-E

MT6752-SBS U1001-F

VCCK GPU MT6752-SBS

Note: 10-5
ACER S56 Note: 10-2 DVDD_GPU K9 VGPU_PMU GND AVDD & MD_A

CAP0402-10U
VCORE_AO_PMU K22 DVDD_TOP DVDD_GPU K10 VGPU_PMIC_FB [5]

CAP0402-10U
[5] VCORE_AO_PMIC_FB K24 DVDD_TOP DVDD_GPU L10 A1 GND AVDD18_MDPLLGP AJ19 VIO18_PMU

CAP0201
DVDD_GPU_GND [5]
[5] VCORE_AO_GND L16 DVDD_TOP DVDD_GPU L13 A31 GND AVDD18_MD AL11

1UF C1071 CAP0201

L17 L14 SH1007 SH1008 B2 AL17
DVDD_TOP DVDD_GPU GND AVDD18_AP VIO18_PMU

CAP0402-10U
SH1002 L18 DVDD_TOP DVDD_GPU M10 B4 GND
SH1001 L19 M9 C1040 47UF CAP0603 4V rated B7 AL14

C1073
DVDD_TOP DVDD_GPU GND AVDD28_DAC VTCXO_1_PMU

1UF C1072
L20 DVDD_TOP DVDD_GPU M14 B9 GND
L22 M13 C1041 10UF B12 AF17
DVDD_TOP DVDD_GPU GND AVSS18_MDPLLGP
4V rated C1001 47UF CAP0603 L23 DVDD_TOP DVDD_GPU N13 C1042 10UF C1043 2.2UF CAP0402 B14 GND AVSS18_MDPLLGP AG17 Note: 10-7
C1044

100NF
P15 DVDD_TOP DVDD_GPU N10 NC CAP0402 B17 GND AVSS18_MDPLLGP AH17
P16 N9 C1045 1UF B19 AJ17
DVDD_TOP DVDD_GPU C1046 GND AVSS18_MDPLLGP
10UF C1002 P17 L9 1UF B22
DVDD_TOP DVDD_GPU GND
D P18
R15
DVDD_TOP
DVDD_TOP
DVDD_GPU
DVDD_GPU
K13
K14
C1047
C1048
1UF
1UF
B24
B27
GND
GND
AVSS18_MD
AVSS18_MD
AF15
AL8
R16 C1049 100NF C1 AH9
C1003 CAP0402 DVDD_TOP GND AVSS18_MD
C1004
NC
4.7UF CAP0402
R17 DVDD_TOP DVFS1 C1050 NC C5 GND AVSS18_MD AH14
D
R18 DVDD_TOP C10 GND AVSS18_MD AJ9
C1005 2.2UF CAP0402 V15 R8 C15 AJ14
DVDD_TOP DVDD_DVFS GND AVSS18_MD
V16 DVDD_TOP DVDD_DVFS R10 C20 GND AVSS18_MD AK14
V17 DVDD_TOP DVDD_DVFS R12 C25 GND
C1006
C1007
1UF V18 DVDD_TOP DVDD_DVFS T7 D3 GND PLL
1UF P14 DVDD_TOP DVDD_DVFS T8 D6 GND
C1008 1UF W15 T9 D8 U4 VIO18_PMU
DVDD_TOP DVDD_DVFS GND AVDD18_PLLGP
C1009 1UF W16 T10 D11
DVDD_TOP DVDD_DVFS GND
C1010 1UF W17 T11 D13 F11
DVDD_TOP DVDD_DVFS GND AVDD18_MEMPLL VIO18_PMU

C1074

100NF C1075
C1011 1UF W18 T12 DVDD_DVFS1 D18
DVDD_TOP DVDD_DVFS GND
C1012 1UF W19 U7 D21 T6
DVDD_TOP DVDD_DVFS GND AVSS18_PLLGP
C1013 1UF AB15 U8 DVDD_DVFS_1_PMIC_FB [1] D23
DVDD_TOP DVDD_DVFS GND
C1014 100NF AB16 U9 D25 E11

100NF
DVDD_TOP DVDD_DVFS DVDD_DVFS1_GND [1] GND AVSS18_MEMPLL
C1015 NC AB17 U10 D27
DVDD_TOP DVDD_DVFS GND
C1016 NC AB18 U11 E1
DVDD_TOP DVDD_DVFS SH1009 SH1010 GND
AB19 DVDD_TOP DVDD_DVFS U12 E2 GND PERI_D
AC14 DVDD_TOP DVDD_DVFS V7 E7 GND
AC15 V8 C1051 47UF CAP0603 4V Rated E8 AL26
DVDD_TOP DVDD_DVFS GND DVDD28_BPI1 VIO18_PMU

100NF C1076
AC16 V12 C1052 47UF CAP0603 4V Rated E12
DVDD_TOP DVDD_DVFS GND
AC17 DVDD_TOP DVDD_DVFS AA7 C1053 22UF CAP0603 E17 GND DVDD28_BPI2 AL23 VIO18_PMU
22UF CAP0603

C1077
AC18 DVDD_TOP DVDD_DVFS V9 C1054 E18 GND
AC19 DVDD_TOP DVDD_DVFS AA10 E22 GND
AC20 DVDD_TOP DVDD_DVFS AA11 E26 GND DVDD28_MD W1
V14 DVDD_TOP DVDD_DVFS AA12 E27 GND
C1055 2.2UF CAP0402

100NF
AB14 DVDD_TOP DVDD_DVFS AB7 E29 GND
R14 AB10 C1056 2.2UF CAP0402 F2
DVDD_TOP DVDD_DVFS GND
W13 DVDD_TOP DVDD_DVFS AB11 F3 GND
W14 DVDD_TOP DVDD_DVFS AB12 F7 GND DVDD18_IO1 AC31 VIO18_PMU
L21 AC8 F8 AL22

C1079
C1078
DVDD_TOP DVDD_DVFS GND DVDD18_IO2

100NF C1080
L24 DVDD_TOP DVDD_DVFS AC9 F17 GND DVDD18_IO3 AK1
AD7 C1057 100NF F18 AL1
DVDD_DVFS GND DVDD18_IO3
Note: 10-3 VCCK2 DVDD_DVFS AD10 C1058 1UF
C1059
J2 GND

100NF

100NF
DVDD_DVFS AE7 1UF U17 GND
M21 AA8 C1060 1UF N27 V19
DVDD_LTE DVDD_DVFS GND DVDD_VQPS VEFUSE
M22 AA9 C1061 1UF N28
DVDD_LTE DVDD_DVFS GND
M23 AB8 C1062 1UF N19
DVDD_LTE DVDD_DVFS GND
C [5] VCORE_PD_PMIC_FB
VCORE_PD_PMU M24
N21
DVDD_LTE
DVDD_LTE
DVDD_DVFS
DVDD_DVFS
AB9
AD11
C1063
C1064 1UF
1UF P11
E23
GND
GND DVDD18_MSDC0 D31 VIO18_PMU C
N22 V10 C1065 1UF AJ22
[5]
DVDD_LTE DVDD_DVFS GND
VCORE_PD_GND N23 V11 C1066 1UF AD4 F1
DVDD_LTE DVDD_DVFS GND DVDD28_MSDC1 VMC_PMU
CAP0603

N20 C1067 1UF AG4

DVDD_LTE GND
M20 DVDD_LTE Note: 10-1 AG6 GND
SH1003 SH1004
T20 DVDD_LTE AG20 GND
T21 DVDD_LTE AG23 GND DVDD18_BIAS1 AL27 VIO18_PMU
R1001 NC
22UF C1020
T22 DVDD_LTE GND [1] DVDD_DVFS_1_PMIC_FB
DVDD_DVFS_1_PMIC_FB_6325 [5] AB27 GND
T23 DVDD_LTE W21 GND
T24 DVDD_LTE [1] R1002 Y8 GND
22UF C1021 U20 K11 DVDD_DVFS1_GND 0R DVDD_DVFS1_GND_6325 [5] Y9 K1
DVDD_LTE GND GND DVDD28_SIM1 VSIM1_PMU
U22 DVDD_LTE GND K12
U23 DVDD_LTE GND U13 [1] DVDD_DVFS_1_PMIC_FB R1003 DVDD_DVFS_1_PMIC_FB_6311 [6]

C1081
C1022 100NF 0R
U24 DVDD_LTE GND U19 DVDD28_SIM2 V1 VSIM2_PMU
C1023 100NF N24 P9
100NF DVDD_LTE GND [1] R1004 [6] CAP0201
C1024 Y20 P8 DVDD_DVFS1_GND 0R DVDD_DVFS1_GND_6311

C1082

C1083
100NF DVDD_LTE GND

1UF C1084

100NF C1085
C1025 Y21 DVDD_LTE GND P10

1UF
Y22 DVDD_LTE GND P12
DVDD_SRAM_PMU Y23 DVDD_LTE GND P13 Schematic design notice of "10_BB_POWER" page. DVDD18_BIAS2 K3

100NF

100NF
Y24 DVDD_LTE GND AA13 DVDD18_BIAS3 V2
AA20 DVDD_LTE GND P21
AA21 DVDD_LTE GND P22
AA22
AA23
DVDD_LTE GND P23
P24
Note 10-1: 4 mil GND trace with good shielding to PMIC PERI_A
DVDD_LTE GND
AA24 AC10 P1
U21
DVDD_LTE
DVDD_LTE
GND
GND R13 (Differential) AVDD18_MIPITX1 VIO18_PMU

GND R21 AVDD18_MIPIRX0 AK28

R22 AL28
GND Differential pair of DVFS1 remote sense must be AVDD18_MIPIRX1 VIO18_PMU

C1086

C1087
SH1020

SRAM GND R23

CAP0201 CAP0201
GND R24 AVSS18_MIPITX K5
GND T13 close to MT6752¡¦s ball. AVSS18_MIPITX M3
CAP0402
C1030 CAP0402

1UF

1UF
AE6 DVDD_SRAM GND T14 AVSS18_MIPITX N5
P7 DVDD_SRAM GND T15
GND T16 AVSS18_MIPIRX AF27
T17 AH28
GND
T18 Note 10-2: VCORE_AO remote sense must be close to AVSS18_MIPIRX
AJ28
C1031

C1032

GND AVSS18_MIPIRX
VDDQ GND U14 AVSS18_MIPIRX AL31

B GND U15
U16
MT6752¡¦s ball. U2 VIO18_PMU B
GND AVDD18_USB
4.7UF

100NF

4.7UF

E5 U18 P5 VUSB33_PMU
E6
DDRV
DDRV
GND
GND AC11 Remote sense trace with GNDshielding to PMIC AVDD33_USB_P0
AVDD33_USB_P1 R5
VUSB33_PMU
VDRAM_PMU E10 DDRV GND T19

C1088

C1090
E14 V22 (Differential)

C1089
DDRV GND
E15 DDRV GND V23 Note: 10-6
E20 V24 CAP0201 CAP0201
DDRV GND
E21 DDRV GND W9

100NF
1UF

1UF
F5 DDRV GND W7
Note 10-3: VCORE_PD remote sense must be close to
SH1021

F6 DDRV GND W8 AVSS33_USB T5

F10 DDRV GND AA5
DVDD12_EMI
F12 DDRV GND AF4
F15 DDRV GND AF5 MT6752¡¦s ball.
Note: 10-4 F20 DDRV GND W12
G12
F4
DDRV
DDRV_CLK
GND
GND
W22
W23
Remote sense trace with GNDshielding to PMIC
GND W24 AVDD18_WBG E30 VCN18_PMU
(Differential) VCN18_PMU

C1091
GND Y7 AVSS18_WBG G27
SH1005
GND Y10 G29
C1036
C1035

C1037

C1038

[5] VDRAM_PMIC_FB
C1034

GND AVSS18_WBG
10UF C1033

GND Y11 AVSS18_WBG H28

Y12 H29
Note 10-4: VDRAM remote sense must be close to

100NF
GND AVSS18_WBG
J22 GND GND Y13 AVSS18_WBG H30
4.7UF

100NF

100NF

J23 Y14 J27

100NF

100NF

GND GND AVSS18_WBG

[5]
DVDD_DRAM_GND
SH1006 M11
M12
GND GND Y15
Y16
MT6752¡¦s ball. AVSS18_WBG K26
M29
GND GND AVSS18_WBG
L15 GND GND Y17 AVSS18_WBG P29
M7 GND GND Y18 AVSS18_WBG P31
M8 Y19 H27
L11
GND
GND
GND
GND V13 Note 10-5: Differential pair of GPU remote sense AVSS18_WBG
L12 GND GND AA14
M15
M16
GND GND AA15
AA16
must be close to MT6752¡¦s ball.
GND GND
M17 GND GND AA17 GND
M18 GND GND AA18
M19
P20
GND
GND
GND
GND
AA19
AB13 Note 10-6: Connect AVDD33_USB_P1 (R5 ball)
N7 R19
A N8
N14
GND
GND
GND
GND
GND
GND
AB21
AB22
to "VSIM1_PMU" for IC-USB / Samrt A
P19
N11
GND
GND
GND
GND
AB23
AB24
card application.
N12 GND GND AB20
N15
N16
GND
GND
GND
GND
R20
AC21 Connect AVDD33_USB_P1 (R5 ball) to
N17 GND GND AC22
N18 GND GND AC23 "VUSB33_PMU" for USB application. DRAWN BY: MODULE TITLE:
V20 GND GND AC12
V21 GND GND W10
<NAME HERE> <MODULE NAME HERE> <TITLE NAME HERE>
W20 GND GND W11 AVDD28_DAC (AL14 ball) must be powered by
MT6752/677PIN
MT6752V/L Note 10-7: SIZE: DRAWING NO: REV:
"VTCXO_1_PMU". The de-coupling cap.has to MT6752/677PIN
CHECKED BY: A2 <NO>
MT6752V/L <DRAWN NO HERE>
be placed as close to BB as possible. <NAME HERE>
SHEET: No of No <DATE HERE>

6 5 4 3 2 1
 U1001-A

MT6752-SBS
PMU_IF DRAM_IF
[5] SYSRSTB AE4 SYSRSTB

[5,6] WATCHDOG AD2 WATCHDOG U1001-B

[5] SRCLKENA0 Y2 SRCLKENA0

MT6752-SBS
[5] SRCLKENA1 AA2 SRCLKENA1 SIM ABB_IF
VREF_CA E24 EVREF [2,13]
[20] SIM1_SCLK J1 SIM1_SCLK TDX26M_IN AF16
[20] SIM1_SIO J4 SIM1_SIO
VREF_DQ F22 EVREF [2,13] [20] SIM1_SRST J5 SIM1_SRST
TD_TX_BBIP AL15
32Khz input [20] SIM2_SCLK W3 SIM2_SCLK TD_TX_BBIN AK15
[5] RTC32K1V8 AE3 RTC32K_CK VREF_AP E25 [20] SIM2_SIO W2 SIM2_SIO
[20] SIM2_SRST W4 SIM2_SRST TD_TX_BBQP AL16
TD_TX_BBQN AK16
[2,5] PWRAP_SPI0_CSN AD5 PWRAP_SPI0_CSN
[5] PWRAP_SPI0_CK AB3 PWRAP_SPI0_CK BPI - W/G TD_RX_BBIP AG18
[5] PWRAP_SPI0_MO AB5
AC5
PWRAP_SPI0_MO
PWRAP_SPI0_MI
Note: 11-1
BPI11_DRX_V2 AK25 BPI_BUS14
TD_RX_BBIN AF18
[5] PWRAP_SPI0_MI [11]
Note: 11-2 EXTDN D1 R1101
240R AJ23 BPI_BUS13
TD_RX_BBQP
TD_RX_BBQN
AG19
AF19
[5] AUD_CLK_MOSI AC2 AUD_CLK_MOSI
[2,5] AUD_DAT_MOSI_1 AB1 AUD_DAT_MOSI AH23 BPI_BUS12
[9]

C1105
[5] AUD_DAT_MISO_1 AB2 BPI12_B28
AUD_DAT_MISO
CAP0201 AG24 BPI_BUS11
[11] BPI10_DRX_V1 AJ24 BPI_BUS10

100NF
[11] DRX_ANT_CTL1 AJ25 BPI_BUS9 APC AH16 LTE_APC1 [10]

AG25 BPI_BUS8 APC2 AJ16

PLLs Test Pin [11] DRX_ANT_EN AH25 BPI_BUS7

DDRV_VREF F21 DVDD12_EMI
AH26

C1101
[7]GPIO_SWCHG_EN BPI_BUS6
CAP0201 [14]GPIO_GPS_LNA_EN AJ26 BPI_BUS5
U5 TP
[7]

1UF
U6 TN GPIO_FL_CTL AK26 BPI_BUS4
[7] GPIO_FL_TXMASK AK27 BPI_BUS3
LTEX26M_IN AG14 LTE_LTEX26M_IN LTE_LTEX26M_IN [8]
[7] GPIO_FL_STROBE AJ27 BPI_BUS2
Note: 11-3
AH27 BPI_BUS1 LTE_TX_BBIP AG11 LTE_TX_BBIP [8]
LTE_TX_BBIN AH11 LTE_TX_BBIN [8]
AG26 BPI_BUS0
H12 TP_MEMPLL LTE_TX_BBQP AG12 LTE_TX_BBQP [8]
H13 TN_MEMPLL LTE_TX_BBQN AH12 LTE_TX_BBQN [8]
RFI_C
[8] LTE_RFIC0_BSI_EN AK22 RFIC0_BSI_EN
LTE_RX1_BBIP AK9 LTE_RX1_BBIP [8]
[8] LTE_RFIC0_BSI_CK AG22 RFIC0_BSI_CK LTE_RX1_BBIN AL9 LTE_RX1_BBIN [8]
[8] LTE_RFIC0_BSI_D2 AG21 AK10
RFIC0_BSI_D2 LTE_RX1_BBQP LTE_RX1_BBQP [8]
LTE_RX1_BBQN AL10 LTE_RX1_BBQN [8]
[8] LTE_RFIC0_BSI_D1 AH21 RFIC0_BSI_D1
LTE_RX2_BBIP AK12 LTE_RX2_BBIP [8]
[8] LTE_RFIC0_BSI_D0 AH22 AL12
RFIC0_BSI_D0 LTE_RX2_BBIN LTE_RX2_BBIN [8]

LTE_RX2_BBQP AK13 LTE_RX2_BBQP [8]

JTAG AK23 TD_TXBPI LTE_RX2_BBQN AL13 LTE_RX2_BBQN[8]

AJ20 RFIC1_BSI_EN
ET_P AG10
AF21 RFIC1_BSI_CK ET_N AG9

AL20 RFIC1_BSI_D2
AK20 RFIC1_BSI_D1
AJ21 RFIC1_BSI_D0

Misc
BPI - L MISC BSI
GND AD1 TESTMODE

[8] LTE_TXBPI AL3 LTE_TXBPI MISC_BSI_CS0B AJ3

AH5 BPI_BUS27 MISC_BSI_CS1B AK3

AG5 BPI_BUS26 MISC_BSI_CK AK5 LTE_MIPI0_SCLK [9,10]

NC [16] LCM_ID AH6 BPI_BUS25 MISC_BSI_DO AK4 LTE_MIPI0_SDATA [9,10]

[10] BPI8_B28B AJ6 BPI_BUS24 MISC_BSI_DI AK2

[19]
SUB_SW_CTL1 AL5 BPI_BUS23

[19]
SUB_SW_EN AK6 BPI_BUS22
AUX IN
[19]SUB_SW_CTL2 AK7 BPI_BUS21
AJ7 BPI_BUS20 AUXIN2 AH18
R1103 AH19 AUX_IN1_NTC [18]
PWRAP_SPI0_CSN [2,5] AUXIN1
NC AH7 BPI_BUS19 AUXIN0 AJ18 AUX_IN0_NTC [18]
MT6752/677PIN
MT6752V/L VIO18_PMU
R1102 AUD_DAT_MOSI_1 [2,5] AG7 BPI_BUS18
NC REF POWER
AH8 BPI_BUS17

1UF C1104
R1105 AJ8 AL18 REFP CAP0201
BPI_BUS16 REFP
NC REFN AK18
R1104 AL6 BPI_BUS15
NC
MT6752/677PIN
MT6752V/L

Close to AP IC.

PWRAP_SPI0_CSN AUD_DAT_MOSI JTAG Schematic design notice of "11_BB_1" page.

HI LO N/A GPIO default Note 11-1: The BPI_BUS0~BPI_BUS9 are capable of 2.8V I/O ,according to the input of DVDD28_BPI1 and DVDD28_BPI2

HI HI SPI_CSB/SPI_CLK/SPI_MO/SPI_MI Note 11-2: PWRAP_SPI0_CSN and AUD_DAT_MOSI are JTAG feature in bootstrap.

LO LO CAM_CLK0/CAM_RST0/CAM_RST1/CAM_PDN0
Note 11-3: The de-coupling cap. of DRAM VREF have to be placed as close to
LO HI MSDC1_CLK/MSDC1_CMD/MSDC1_DAT0/MSDC1_DAT1
BB as possible.
 U1001-C
U1001-D
MT6752-SBS
MT6752-SBS
CSI DSI
USB MSDCs
[17] RCP AE26 RCP TCP M5 TCP [16]
[17] RCN AE27 RCN TCN L5 TCN [16] [19] USB_DP T2 USB_DP_P0 MSDC0_RSTB E28 MSDC0_RSTB [13]
[19] USB_DM T1 USB_DM_P0
MSDC0_CMD B31 MSDC0_CMD [13]
[17] RDP0 AE31 RDP0 TDP0 M4 TDP0 [16]
[17] RDN0 AE30 RDN0 TDN0 N4 TDN0 [16] [5] USB_ID AB4 IDDIG MSDC0_CLK A29 MSDC0_CLK [13]
MSDC0_DSL A30 MSDC0_DSL [13]
[7] DRV_VBUS AA1 DRVBUS
[17] RDP1 AF30 RDP1 TDP1 N3 TDP1 [16] MSDC0_DAT7 D30 MSDC0_DAT7 [13]
[17] RDN1 AF31 RDN1 TDN1 N2 TDN1 [16] MSDC0_DAT6 B30 MSDC0_DAT6 [13]
MSDC0_DAT5 C29 MSDC0_DAT5 [13]
P3 USB_DP_P1 MSDC0_DAT4 D28 MSDC0_DAT4 [13]
[17] RDP2 AF28 RDP2 TDP2 M1 TDP2 [16] R2 USB_DM_P1 MSDC0_DAT3 C30 MSDC0_DAT3 [13]
[17] RDN2 AF29 RDN2 TDN2 M2 TDN2 [16] MSDC0_DAT2 D29 MSDC0_DAT2 [13]
MSDC0_DAT1 B29 MSDC0_DAT1 [13]
MSDC0_DAT0 B28 MSDC0_DAT0 [13]
[17] RDP3 AH30 RDP3 TDP3 L2 TDP3 [16]
[17] RDN3 AG30 RDN3 TDN3 K2 TDN3 [16]

MSDC1_CLK G1 MSDC1_CLK [12]

[17] RCP_A AH29 RCP_A MSDC1_CMD H4 MSDC1_CMD [12]

[17] RCN_A AG29 RCN_A
5.1KR MSDC1_DAT3 G2 MSDC1_DAT3 [12]
R1201 T4 H2
USB_VRT_P0
USB_VRT_P0 MSDC1_DAT2 MSDC1_DAT2 [12]
[17] RDP0_A AH31 RDP0_A +/-1% MSDC1_DAT1 G4 [12]
AJ31 H3 MSDC1_DAT1
[17] RDN0_A RDN0_A MIPI_VRT R1227 MSDC1_DAT0 MSDC1_DAT0 [12]
VRT N1
+/-1%
[17] RDP1_A AK30 RDP1_A 1.5K BC
[17] RDN1_A AJ30 RDN1_A
R4 CHD_DP_P0
AK29 RDP2_A R3 CHD_DM_P0
AJ29 RDN2_A [5] CHD_DP_P0
[5] CHD_DM_P0
AL29 RDP3_A
AL30 RDN3_A DISP_PWM AG1 DISP_PWM0 [7]
KEYPAD CONN_IF
LCM_RST AE2 LCM_RST [16]
[15] AC29 R1210 AG3 J29 WB_CTRL0 [14]
EINT_EAR CMPDAT0 KPROW1 WB_CTRL0
DSI_TE AE1 NC AF3 KPROW0 WB_CTRL1 J28 WB_CTRL1 [14]
DSI_TE [16] [14]
[18] EINT_A+GYRO AC28 CMPDAT1 WB_CTRL2 K28 WB_CTRL2
L29 WB_CTRL3 [14]
[19]
WB_CTRL3
[7] EINT_CHG_STAT AC27 GPIO_SUBID AF2 L28 WB_CTRL4 [14]
CMPCLK KPCOL1 WB_CTRL4
[20] KCOL0 AG2 M28 WB_CTRL5 [14]
KPCOL0 WB_CTRL5
[17] CAM_RST0_CLK AD28 CAM_RST0
[17] CAM_RST1 AD27 CAM_RST1 R1202 4.7KR WB_SCLK L27 CONN_SCLK [14]
VIO18_PMU
M27 CONN_SDATA [14]
WB_SDATA
[17] CAM_PDN0 AD29 CAM_PDN0 R1203 4.7KR WB_SEN P30 CONN_SEN [14]
I2C
[17] CAM_PDN1 AC30 CAM_PDN1
[6,7,16] SCL0 T30 J26 CONN_XO_IN [14]
SCL0 XIN_WBG
[6,7,16] SDA0 R30 SDA0
[17] CMMCLK AC26 CAM_CLK0 VIO18_PMU R1204 4.7KR
R1205 4.7KR
R28 SCL1 WB_RSTB N30 CONN_RSTB [14]
R29 SDA1
[17,18] SCL1
[17,18] SDA1
R26 SCL2
SPI DPI R27 SDA2 PCM (ext MD)
[16] GPIO_CTP_RSTB AJ1 SPI_CSB T27 SCL3
T28 SDA3
[15] AUDIOPA_SD
TP-0.5MM [6] SCL2
TP1202
AL2 SPI_CLK DPI_D0 W31
W30 [6] SDA2
DPI_D1
DPI_D2 Y28 UART
[20] EINT_SD AH1 SPI_MO DPI_D3 Y30 VIO18_PMU R1208 4.7KR
DPI_D4 Y27 R1209 4.7KR
DPI_D5 AA27 GPIO
AJ2 SPI_MI DPI_D6 AA30
DPI_D7 AB31 [17] SRCLKENAI AH3 SRCLKENAI SRCLKENAI
SCL3
DPI_D8 AB30
[17] SDA3
DPI_D9 V29 PWM_A AH2 EINT_CTP EINT_CTP [16]
DPI_D10 W28
I2S DPI_D11 AB29

[17] EINT_ALPS V30 I2S0_MCK DPI_DE Y31

[18] M_RESET U30 W29
I2S0_BCK DPI_CK
T31 I2S0_LRCK DPI_HSYNC W27 INT_SIM1 Y4 EINT_CARD [3,20]
WCN 6625
[6] EINT_MT6311 U31 I2S0_DI DPI_VSYNC V26 INT_SIM2 Y5 EINT_CARD [3,20]
[14] GPS_RX_IP G30 GPS_RXIP
V28 [14] GPS_RX_IN G31
[20] URXD0 I2S1_MCK GPS_RXIN
[14] GPS_RX_QP F31 GPS_RXQP
V27 [14] GPS_RX_QN F30
[20] UTXD0 I2S1_BCK GPS_RXQN
TP-0.5MM
TP1205
U27 I2S1_LRCK [14] F2W_CLK P28 F2W_CLK
TP-0.5MM [14] F2W_DATA P27 F2W_DATA
TP1206
U26 I2S1_DO
[14] WB_RX_IP N31 WB_RXIP
[5] VOW_CLK_MISO AB28 [14] WB_RX_IN M31
VOW_CLK_MISO WB_RXIN
MT6752/677PIN [14] WB_RX_QP M30 WB_RXQP
MT6752V/L [14] WB_RX_QN L30 WB_RXQN
[14] WB_TX_IP K30 WB_TXIP
[14] WB_TX_IN K31 WB_TXIN
[14] WB_TX_QP J31 WB_TXQP
[14] WB_TX_QN J30 WB_TXQN

MT6752/677PIN
MT6752V/L
 U1001-G

MT6752-SBS
EMI_IF
[13] DQ[0:31] CS0_N B3 CS0_N [13]
CS1_N A2 CS1_N [13]
DQ0 B13 DQ0
DQ1 C13 DQ1 CKE D5 CKE [13]
DQ2 A14 DQ2
DQ3 D14 DQ3 DQM0 D17 DQM0 [13]
DQ4 B15 DQ4 DQM1 C18 DQM1 [13]
DQ5 D15 DQ5 DQM2 D12 DQM2 [13]
DQ6 C16 DQ6 DQM3 C23 DQM3 [13]
DQ7 A17 DQ7
DQ8 B18 DQ8 DQS0_C E13 DQS0_C [13]
DQ9 A19 DQ9 DQS1_C E16 DQS1_C [13]
DQ10 D19 DQ10 DQS2_C F9 DQS2_C [13]
DQ11 B20 DQ11 DQS3_C F19 DQS3_C [13]
DQ12 D20 DQ12
DQ13 D22 DQ13 DQS0_T F13 DQS0_T [13]
DQ14 C21 DQ14 DQS1_T F16 DQS1_T [13]
DQ15 A22 DQ15 DQS2_T E9 DQS2_T [13]
DQ16 A9 DQ16 DQS3_T E19 DQS3_T [13]
DQ17 B8 DQ17
DQ18 C8 DQ18
DQ19 C11 DQ19 CLK0_T E4 CLK0_T [13]
DQ20 B10 DQ20 CLK0_C E3 CLK0_C [13]
DQ21 D9 DQ21
DQ22 A12 DQ22 CA[0:9] [13]
DQ23 D10 DQ23 CA0 A7 CA0
DQ24 D24 DQ24 CA1 D7 CA1
DQ25 B23 DQ25 CA2 B5 CA2
DQ26 D26 DQ26 CA3 C6 CA3
DQ27 B25 DQ27 CA4 A4 CA4
DQ28 A24 DQ28 CA5 D4 CA5
DQ29 C27 DQ29 CA6 C3 CA6
DQ30 A27 DQ30 CA7 B1 CA7
DQ31 C26 DQ31 CA8 C2 CA8
CA9 D2 CA9

MT6752/677PIN
MT6752V/L
 8 Core DVFS FB setting (8 Core and 4 Core Co-Layout)
Schematic design notice of "20_POWER_MT6325" page. DVDD_DVFS1

Note 20-1: PAD_PWRAP_SPI0_MI and PAD_PWRAP_SPI0_MO are DRAM feature in bootstrap. U2001-A
L2001
DVDD_DVFS1 [1,5,6]
CONTROL SIGNAL BUCK OUTPUT NC 4 mil GND trace with
P16 A16 good shielding from baseband
[7]PWRKEY_PMU PWRKEY VDVFS11
A17 (Differential)
VDVFS11
[20] HOMEKEY R13 HOMEKEY VDVFS11 B16
DVDD_DVFS_1_PMIC_FB_6325 [1,5]
DVDD_DVFS1_GND_6325 [1]
[2] SYSRSTB R19 RESETB VDVFS11_FB E16
GND_VDVFS_FB D16
[6] EXT_PMIC_EN R18 EXT_PMIC_EN [1,5] DVDD_DVFS_1_PMIC_FB_6325 R2001
A12 L2002 0R VIO18_PMU
VDVFS12
T17 PP_EN VDVFS12 A13 NC R2008
B13 NC VSYS
VDVFS12 4 mil. R2007
[2,6]WATCHDOG U10 WDTRSTB_IN 0R VIO18_PMU
VDVFS12_FB D17
R2003 200KR U4 UVLO_VTH L2003
A10 0.47UH
VGPU VGPU_PMU
V12 FSOURCE VGPU A11 4 mil GND trace with
UVLO_VTH R RANGE: VGPU C10 good shielding (Differential)
200KOHM ~ 250KOHM N15 PMU_TEST_MODE
VGPU_FB F13 VGPU_PMIC_FB [1]
[2] SRCLKENA0 T13 SRCLKEN_IN0 GND_VGPU_FB F14 DVDD_GPU_GND [1]

[2] SRCLKENA1 P14 A6 L2006 0.47UH

SRCLKEN_IN1 VCORE1 VCORE_PD_PMU
VCORE1 A7
[2]PWRAP_SPI0_CSN P11 SPI_CSN VCORE1 B7

Note: 20-1 [2] PWRAP_SPI0_CK U12 SPI_CLK VCORE1_FB

GND_VCORE1_FB
E8
E7
VCORE_PD_PMIC_FB
VCORE_PD_GND
[1]
[1]
[2] PWRAP_SPI0_MO P10 SPI_MOSI
A4 L2007 0.47UH
VCORE2 VCORE_AO_PMU
[2] PWRAP_SPI0_MI U11 SPI_MISO VCORE2 A5
VCORE2 B4
AUX ADC
U19 VAUXA28 VCORE2_FB F5 VCORE_AO_PMIC_FB [1]
GND_VCORE2_FB F6 VCORE_AO_GND [1]
R8 AVDD28_AUXADC
C2052 1UF B1 L2104 0.47UH
VDRAM VDRAM_PMU
T8 A1 4 mil GND trace with
AVSS28_AUXADC VDRAM
good shielding from baseband (Differential)
U8 AUXADC_VREF18 VDRAM_FB H5 VDRAM_PMIC_FB [1]
VSYS C2037 100NF G5
GND_VDRAM_FB DVDD_DRAM_GND [1]
V7 AUXADC_VIN L2008 0.47UH
D2001 PZ5D4V2H

VIO18 F1 VIO18_PMU

4.7UF C2110
50mil VBAT INPUT VIO18 E1
B17 VBAT_VDVFS11 VIO18 E2
C17 VBAT_VDVFS11
C12 J2
22UF C2007

VBAT_VDVFS12 VIO18_FB
CAP0603 D12 VBAT_VDVFS12 L2107
2.2UH

C2112
D11 VBAT_VGPU VRF18_0 A19 VRF18_PMU
C11 VBAT_VGPU VRF18_0_FB D18
D6 VBAT_VCORE1 L2106

C2111
C6 F19 2.2UH
VBAT_VCORE1 VPA VPA_PMU

4.7UF
C5 VBAT_VCORE2 VPA_FB G14
D5 VBAT_VCORE2
C1 VBAT_VDRAM VIO18_PMU

2.2UF
D1 SLDO INPUT

C2050 1UF
VBAT_VDRAM
G2 VBAT_VIO18 AVDD18_SLDO1 G3

C2047 1UF
CAP0402
CAP0402

CAP0402

C2013 CAP0402

CAP0402

CAP0402

CAP0402

CAP0402

VSYS F2 VBAT_VIO18 AVDD18_SLDO2 H2

1UF C2020 CAP0201

G1 VBAT_VIO18
B19 VBAT_VRF18_0
LDO OUTPUT
F18 VBAT_VPA VTCXO0 V6 VTCXO_1_PMU
E18 U17
C2011

C2012

C2015

C2017
C2016

C2018

C2021

VBAT_BUCK_CTRL1 VTCXO1
1UF C2043

VRF18_1 V18
VSIM1 T16 VSIM1_PMU
VSIM2 R16 VSIM2_PMU
2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

4.7UF

4.7UF

VOUT_SYS_BOOST VCN18 L2 VCN18_PMU

VCN28 U18 VCN28_PMU
V19 VBAT_LDOS1 VCN33 N1 VCN33_PMU
V15 VBAT_LDOS2
C2023 CAP0402

C2025 CAP0402

C2026 CAP0402
C2024 CAP0402

V5 VBAT_LDOS3 VSRAM_DVFS J3 DVDD_SRAM_PMU

P1 VBAT_LDOS4 VBIASN J4
VMIPI K2 VMIPI_PMU
L1 VBAT_LDOS5 VUSB33 M3 VUSB33_PMU
T1 VBAT_VIBR VIO28 N2 VIO28_PMU
1UF C2029

1UF C2035

VIO18_PMU VBIF28 V17 VBIF28_PMU

VEFUSE M1 VEFUSE
VGP1 CTP
DIG Power
2.2UF

V11 R14
2.2UF

2.2UF

DVDD18_IO VMC
2.2UF

VMC_PMU
Close to MT6325 R11 DVDD18_DIG VMCH U5 VMCH_PMU
VEMC_3V3 P2 VEMC_3V3_PMU
VGP2 MHL
1UF C2031

1UF C2114

VREF
V3 V16
1UF C2030

VREF VCAMA VCAMA_PMU

U3 GND_VREF VCAMAF U16 VCAM_AF_PMU
VCAMD H1 VCAMD_PMU
GND VCAMIO L3
A15 GND_VDVFS11
VCAM_IO_PMU
VGP3 Sub-Cam
B15 GND_VDVFS11 VGP1 U15 VGP1_PMU
C15 GND_VDVFS11 VGP2 J1

C2048

C2113

C2056
A14 GND_VDVFS12 VGP3 U14 VGP3_PMU
Close to MT6325 B14 GND_VDVFS12 The Layout constraint requires sufficient bypass cap. LDO will not have stability problems
C14 GND_VDVFS12
Vibrator Driver
A9 GND_VGPU VIBR_P R1

1UF

1UF
MOTO+

1UF
B9 GND_VGPU VRTC
C9 R2 VIO28_PMU
GND_VGPU VIBR_N
A8

C2039
GND_VCORE1
B8 GND_VCORE1
RTC
C8 GND_VCORE1 AVDD28_RTC P9
4 mil trace with good shielding (Differential) A3 GND_VCORE2

100NF C2032
B3 U9 NC
GND_VCORE2 XIN
A2 GND_VDRAM X2001
B2 GND_VDRAM XOUT V9
G4 GND_VIO18
32Khz output

C2033
Q13FC1350000400

C2034
1UF C2054

VSYS F3 GND_VIO18 RTC32K_2V8 T9

F4 GND_VIO18
G18 T12 [2]
A18
GND_VPA RTC32K_1V8_0 RTC32K1V8
32K

18PF
GND_VRF18_0

18PF
RTC32K_1V8_1 R12

C19 GND_DMY100MA ENBB R9 ENBB_6169 [8]

P4 GND_VIBR
1UF C2053

ISENSE U2001-C H4 GND_VBIASN XOSC_EN V8

Charger BC1.1/1.2 ACA_ID M14 USB_ID [3] E11 K12
Close to MT6325
L14 GND_LDO GND_LDO
VOUT_SYS_BOOST FCHR_ENB E12 K11
U1 GND_LDO GND_LDO
CHG_DM CHD_DM_P0 [3] F11 K10
VBUS
R5 GND_LDO GND_LDO
BATSNS F12 GND_LDO GND_LDO K9
T5
CHG_DP V1 CHD_DP_P0 [3] G7 GND_LDO GND_LDO K8
Audio
R2032

1UF C2051

ISENSE G8 GND_LDO GND_LDO K7

Gauge E19 4 mil trace with good shielding (Differential) U2001-B
+/-1%

CS_N CS_N [6] G9 GND_LDO GND_LDO K6

V4 VSYSSNS CS_P D19 CS_P G10 J12 [8] MT6169_XO4_CLK L12 CLK26M AU_MICBIAS1 N17 MICBIAS1
GND_LDO GND_LDO
330KR

[6] G11 GND_LDO GND_LDO J11

[6,20] BAT_ON R17 BATON
ISINK ISINK0 R7 G12 J10 [2] AUD_CLK_MOSI P12 N16
AUD_CLK AU_MICBIAS0

1UF C2044

1UF C2042
GND_LDO GND_LDO MICBIAS0
H7 GND_LDO GND_LDO J9 2.2UF
VCDT V2 P7 T11 J18 C2038
VCDT ISINK1 H8 GND_LDO GND_LDO J8 [2]AUD_DAT_MOSI_1 AUD_DAT_MOSI AU_FLYP
VCDT rating: 1.268V H9 J7
T3 T6 [20] GND_LDO GND_LDO
R2033

VDRV ISINK2 ISINK0 H10 H12 [2] AUD_DAT_MISO_1 P13 AUD_DAT_MISO AU_FLYN J17
GND_LDO GND_LDO
ISINK1 [20] H11 M6
+/-1%

R2006 T2 R6 GND_LDO GND_LDO

1UF C2022
[5,7,19,20] VBUS 1.5KR CHRLDO GND_ISINK ISINK2 [20] L5 M7 [3] VOW_CLK_MISO N14 VOICE_CLK_MISO VBAT_SPK H18 VSYS
GND_LDO GND_LDO
39KR

1UF C2041

L6 GND_LDO GND_LDO M8
MT6325V L7 M9 H19 SPK_P GND_SPK H13
GND_LDO GND_LDO
BGA_244PIN_0.4P_19X18_7.8X7.4 L8 GND_LDO GND_LDO M10
L9 M11 G19 SPK_N VAUD28 T19
GND_LDO GND_LDO
Close to PMIC L10 GND_LDO GND_LDO M12

1UF C2036
L11 R4 [15] AU_HSP J19 HSP AVDD28_AUD M16
GND_LDO GND_LDO
M5 GND_LDO GND_LDO F7
E9 F8 [15] AU_HSN K19 HSN AVSS28_AUD L15 single via to GND
GND_LDO GND_LDO
E10 GND_LDO GND_LDO F9
J14 L16 plane directly
GND_LDO F10 [15] AU_HPL HPL AVDD18_AUD
MT6325/244PIN
[15] AU_HPR H15 HPR AVSS18_AUD K16

C2027
[15] P17 ACCDET AVSS18N_AUD H16

C2040
ACCDET
VIO18_PMU
[15] AU_VIN0_P M19 AU_VIN0_P C2027/ C2038/ C2040 flying cap & holding cap :

2.2UF
[15] AU_VIN0_N N19 AU_VIN0_N
N18

2.2UF
[15] AU_VIN1_P AU_VIN1_P 4.7uF for 16ohm reciver
[15] AU_VIN1_N P18 AU_VIN1_N AU_REFN J15
[15] AU_VIN2_P L18 AU_VIN2_P 2.2uF for 32ohm reciver
[15] AU_VIN2_N M18 AU_VIN2_N

MT6325V

BGA_244PIN_0.4P_19X18_7.8X7.4
AU_REFN need single via to
GND plane directly
 2-Phase Buck
MT6311 / 2-Phase Buck I2C address: 0X6B (Write:0x, Read:0x)
Companion buck for VBAT@LV DVDD_DVFS1
U2103
TPS61280 I2C address: 0X75 (Write:0xEA, Read:0xEB)
VSYS L2105 0.33UH
VSYS
A5 A6
PVIN1 VSW1
D2102 A4 B6

C2105 10UF
PVIN1 VSW1
B5
VSW1
BGA_16PIN_0.4P_4X4_1.66X1.66
B4
VSW1
U2102 C6
PGND1
C5
PGND1
C4
PCSB25201T-R47MS C3 B3 PGND1
SW VOUT VOUT_SYS_BOOST
C4 SW VOUT B4 L2108
0.33UH
L2103 0.47UH Note: 22-1

47UF C2124
CAP0603 VSYS
A3 A1
PVIN2 VSW2
A2 B3

C2107 10UF
A3 PVIN2 VSW2
VIN B2
A4 VSW2
VSYS VIN B1
VSW2
22UF C2101

2 CAP0603 C3
PGND2
C2
PGND2
C1
PGND2
1 B1 A2 R2124 good shielding from baseband (Differential)
VSYS VSEL GPIO VSYS
2.2KR [3] SDA2 E4 E2 [1]
A1 SDA VFBP DVDD_DVFS_1_PMIC_FB_6311
EN E5
[3] SCL2 SCL
C1 NBYP PGND D2 D2
VFBN DVDD_DVFS1_GND_6311 [1]
[2,5] WATCHDOG D5
D3 WDTRSTB_IN
VIO18_PMU PGND [3] E3
EINT_MT6311 GPIO
D3
B2 D4 [5] EXT_PMIC_EN EN
SCL PGND
C2 SDA AGND D1 E1 E6
[3,7,16]
DVDD18_DIG VBAISN
SCL0
VSYS
D4
TPS61280A AVIN
[3,7,16] SDA0 D6
GND_VBAISN

1UF
D1

1UF
AGND
short together connect to GND 8 Core DVFS FB setting (8 Core and 4 Core Co-Layout)

C2103

C2102
MT6311/30PIN

Schematic design notice of "22_POWER_MT6311" page.

Note 22-1: MT6311 => Buck EN controlled by EXT_PMIC_EN from MT6325 and I2C.

BATTERY CONNECTOR
VBAT

J2101
60mil VBAT
1

2 BAT_ON [5,6,20]
7 3 [5,6,20]
BAT_ON
1UF C2127

8 4 2 CAP0201
R2103 24KR RES0201
VBIF28_PMU
5 +/-1%
6 Kelvin connection 1
T2101 T2102
CPB9506-0101F
Rfg

R2107 0.01R

+/-1% RES1206

Kelvin connection
Rfg > 0.5W
NC/R
1 2
CS_P [5]
SH2101
NC/R
1 2
CS_N [5]
SH2102
4 mil trace with good shielding (Differential)
 I2C Address
Switching Charger VBUS_1
FN5405 : 0xD4, 0xD5
FAN54015 : 0xD4, 0xD5
VBUS_1 U2201
BQ24158 : 0xD4, 0xD5
VBUS
40mil L2201
A1 C1
120R/100MHz VBUS1 SW1 40mil
WPN201610H1R0MT
A2 C2 2
VBUS2 SW2
R2202 1 33nF
16V rating SW3
C3
C2206
22PF 2 2

1 C2205
C2220 1 1UF 1

4.7UF
C2202 B1 A3
PMID1 BOOT

2
B2
GND GND PMID2
GND D1
PGND1
B3 ISENSE [5]
PMID3
D2
PGND2
R2214
A4 D3

1
[3,6,16] SCL0 SCL PGND3 0.056R
B4 RES0805

2
[3,6,16] SDA0 SDA
E1 40mil
CSIN
C4
[3] EINT_CHG_STAT STAT
CSOUT
E4 BATSENSE VSYS [5,6,7,20]
R2216 0R D4
[3] DRV_VBUS OTG 2 2
2

1UF C2204
[2]GPIO_SWCHG_EN
E2 E3 100NF 1 1 C2208
CD VREF 2 1

R2212
C2207 100NF 4.7UF
C2203
BQ24157YFFR GND

47KR
1 GND GND

10KR
R2213
GND GND

Flash LED 5V Boost

Flash LED I2C address: 0X63 (Write:0xC6, Read:0xC7)

U2206

L2206

10UF C2218
VBAT
C1 D1
CAP0402-10U LX VOUT
WPN201610H1R0MT

CW_CBLPM1_S1

LED2201
B2
VIN

A3 B3
[2,7] GPIO_FL_CTL CTRL FL

[2,7] GPIO_FL_TXMASK C2
TX 4.7UF
CAP0402 2
B1 A2
[2,7] GPIO_FL_STROBE STROBE RSET
1 T2201 T2202
C2219

AGND
PGND
PGND
PGND

15KR
LCM Backlight LED Driver KTD2693B

A1
C3
D2
D3
[2,7] GPIO_FL_CTL

R2201
TP1
[2,7]
GPIO_FL_TXMASK TP2

[2,7]
GPIO_FL_STROBE TP3

VLED_P
VBAT ONSemi MBR0540 and the ZETEX ZHCS400 are recommended
BLM15AG601SN1D D2210
L2210
B2210 WPN201610H100MT BLM15AG601SN1D

C2271 2.2UF
C2210 B2211
4

4.7UF U2250 VBAT VSYS

SW

U2270
C2216 1UF

6 B1 A1
IN VBAT VOUT
B2 A2 VBAT
GND VBAT VOUT
B3 A3
VBAT VOUT
5 1 R2271
[3] DISP_PWM0 CTRL FB C2270
R2223 0R NC D1 C2
VLED_N 2.2UF DELAY_ADJ DSR

47KR
RES0201 R2272
2

R2270
100KR
5.1R

COMP D2 D3
OFF SYS_WAKE
R2211
100KR

C2211 470NF

GND

GND

R2218

C3 C1
/SR0 GND
ETA1168D2G-T
3

GND
FTL75939UCX
[20] D2270
PWRKEY

PWRKEY_PMU [5]

boost£¿£¿£¿
 A
C

B
D
6

[11]
[11]

6
[9]

B28_DRX_P
B28_DRX_N
RX_RFIP1_B1
[9]RX_RFIN1_B3_DCS
[9]RX_RFIP1_B3_DCS

[9] RX_IN1_B5
[9] RX_IP1_B5

[11] B8_DRX_N
[11] B8_DRX_P
[9]RX_IN_DCS
[9] RX_IP_DCS
[9] RX_RFIN1_B1
[9]RX_RFIN1_B8_GSM
[9] RX_RFIP1_B8_GSM

B1
A1
A2
A3
B3
B4
B5
A5
A6
B6
B7
B8
A8
A9
B9
B10
B11
A11
A12
B12
A14
A15
B13
B14
U3101

RFIP2_LB3
RFIP2_LB2
RFIP2_LB1
RFIP1_LB3
RFIP1_LB2

RFIN2_LB3
RFIN2_LB2
RFIN2_LB1
RFIN1_LB3
RFIN1_LB2

RFIP2_HB2
RFIP2_HB1
RFIP1_HB3
RFIP1_HB2

RFIP2_MB1
RFIN2_HB2
RFIN2_HB1
RFIN1_HB3
RFIP1_MB2
RFIN1_HB2
RFIP1_MB1

RFIN2_MB1
RFIN1_MB2
RFIN1_MB1

B3_DRX_P C1 RFIP2_MB2 RFIN1_HB1 B15 RX_RFIN1_B2_PCS [9]

[11]
C2 RFIN2_MB2 RFIP1_HB1 C15 RX_RFIP1_B2_PCS [9]
[11] B3_DRX_N
D2 C14 B28A/B28B_RX_N [9]
RFIP2_HB3 RFIN1_LB1
E2 RFIN2_HB3 RFIP1_LB1 D14 B28A/B28B_RX_P [9]

TX_LB1 K14

5
5

TX_LB2 J14

TX_LB3 J15 TX_GSM_GSM850 [10]

TX_LB4 H15 B5/B8/B28_TX [10]

TX_MB1 G14 TX_DCS_PCS [10]

R3106 F1 H14
MT6169

OUT_32K TX_MB2 B1/B2/B3_TX [10]

2 J2 32K_EN
1 F3 F15
1KR TST1 TX_HB1

TX_HB2 F14

TXDET M13

R3103
1

G1
100R

XO3
[5] MT6169_XO4_CLK H2 XO4
MT6169_XO2_CLK H1 XO2
2

M1
R310162R

[2]LTE_LTEX26M_IN XO1
M15 [2]
TX_BBIP LTE_TX_BBIP

TX_BBIN N15
LTE_TX_BBIN [2] R3112 100R
TX_BBQN N14 LTE_TX_BBQN [2]

TX_BBQP N13 LTE_TX_BBQP [2]

K1 XTAL2 RX1_BBIP N8
4

LTE_RX1_BBIP [2]
K2 XTAL1

4
RX1_BBIN N7
LTE_TXDET

LTE_RX1_BBIN [2]
RX1_BBQN M7 LTE_RX1_BBQN [2]
[9]

RX1_BBQP M6 LTE_RX1_BBQP
[2]
RX2_BBIP M5 LTE_RX2_BBIP
1KR [2]
2
1 RX2_BBIN N5 LTE_RX2_BBIN
[2]

[1,5,8,9,10,11,19]
VTCXO_1_PMU
R3105 L2 XMODE
N1 CLK_SEL RX2_BBQN N4 LTE_RX2_BBQN [2]
N2 EN_26M_BB
RX2_BBQP M4 LTE_RX2_BBQP [2]

2.2UF C3101
1
2
VRF18_PMU

C3111 100NF

2
1
C8 VRXHF2
100NF C3102 D13 VRXHF1

4
1
2

M11 V28_ESD1
100NF C3103 N11

X3101
VTXHF
1
2

KT2520F26000DCW28QAK
OUT
K11 VTXLF
100NF C3104

26M
NC2 M8 VRXLF
1
2

5 L4 VDCXO_DIG
NC1 VCC
2 6 M3 VIO
GND VCON J1 VTCXO
3 1
DET_GND L13
C3 GND TXO_GND K13

1
C4 GND TXO_GND J13
C5 GND TXO_GND H13
ENBB_6169
ENBB_6169

C3109 100NF C6 GND TXO_GND G13

2
C7 GND TXO_GND F13
C9 GND TXO_GND E13

3
1
2

C10 E14
1
2

[5,8]

GND TXO_GND
[5,8]
3

100NF C3105 100NF C3106 C11 GND TXO_GND E15

C12 GND TXO_GND L14

D3 GND
D4 GND
D5 GND
D6 GND
D7
VIO18_PMU

GND
VIO18_PMU

D8 GND
100NF C3107 D9 GND
1
2

D10 GND
D11 GND
100NF C3108 D12 GND
1
2

E1 GND
E3 GND
E4 GND
E5 GND
E6 GND
E7 GND
E8 GND
E9 GND
E10 GND
E11 GND
VTCXO_1_PMU

E12 GND

F2 GND
F4 GND
F5 GND
F6 GND
F7 GND
F8 GND
F9 GND
2

F10 GND
2

F11 GND
F12 GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BSI_D2
BSI_D1
BSI_D0
BSI_EN
BSI_CK
TMEAS
TST2
VRT
TXBPI
TST3
TST4

J3
J4
J8
J9
J5
J6
J7

L3
L6
L7
L8
L9

K3
K7
K8
K9
K4
K6

H3
H4
H5
H6
H7
H8
H9

G2
G3
G4
G5
G6
G7
G8
G9
M9

J10
J11
J12
L10
L11
L12

K12
K10
N10

H10
H11
H12

G10
G11
G12
M10
M12

DRAWN BY:

<NAME HERE>
<NAME HERE>

CHECKED BY:
A2
SIZE:
MODULE

SHEET: No of No
RF PA
<MODULE NAME HERE>
LTE_TXBPI
[2]

1
LTE_RFIC0_BSI_EN [2]
LTE_RFIC0_BSI_CK [2]

LTE_RFIC0_BSI_D2 [2]
LTE_RFIC0_BSI_D0 [2]
LTE_RFIC0_BSI_D1 [2]

DRAWING NO:
1

R3104
<DRAWN NO HERE>

2
1
TITLE:

2KR
<TITLE NAME HERE>

<DATE HERE>
<NO>
REV:
A
C

B
D
 6 5 4 3 2 1
5 4 3 2 1

[10]
B5_PA_OUT [10]

[10]
B8_PA_OUT [10]
[9]

[9]
[10]

B1_PA_OUT [10]

B2_PA_OUT [10]
2G_HB_PA_OUT
B28B_TRX

2G_LB_PA_OUT

B3_PA_OUT
B28A_TRX

1
2
RX_RFIP1_B2_PCS [8]
C3206
3.9PF

2 L3206 1
3.9NH
L3203

4.3NH
NC
1
2
RX_RFIN1_B2_PCS [8]
3.9PF C3207

11

10
D

1
TRX2

BAND5_TX

BAND8_TX

GSM_LB_TX

GSM_HB_TX

TRX1

BAND1_TX

BAND2_TX

BAND4_TX

GND

GND
D
U3203
U3202 GND
46
2 CP1608-24R0822 5.1NH
GND1 C3203 GND RX_RFIP1_B8_GSM [8]
45
C3209

2
3 1

1
2

1
GND2 OUT OUT IN GND
22PF 18PF 44
C3201

2 L3208 1
18PFNC
4

L3207
C3228
GND3 GND2 GND1 GND GND

4.3NHNC
8.2NH
2.7NHNC
12 43

L3202
T COUPLE GND
ECT818000157 42

2
TRX3 GND
13 41
GND 5.1NH
RX_RFIN1_B8_GSM [8]

51R
LTE_TXDET [8] 40

R3201
1
C3210
GND GND
14 39

ANT BAND2_RX
15 38
VTCXO_1_PMU

C3204 10PF
GND BAND2_RX
16 37
1

VMIPI_PMU 2
VDD GND

C3205 10PF
17 36
1
2
VIO BAND8_RX
18 35

C [2,10] LTE_MIPI0_SDATA
19
SDATA BAND8_RX
34 C
GND GND
20 33

GND
32

LMSW6SGN-F70

BAND5_RX

BAND5_RX

BAND1_RX

BAND1_RX

BAND4_RX

BAND4_RX

1
RX_RFIP1_B3_DCS [8]

DCS_RX

DCS_RX
C3215 15PF

SCLK

TRX4

U3201
GND
21

22

23

24

25

26

27

28

29

30

31

2 L3210 1

2 L3211 1
4.3NH

4.3NH NC
2

1
LTE_MIPI0_SCLK RX_RFIN1_B3_DCS [8]
C3214 15PF

4.7PF C3217
RX_RFIN1_B1 [8]

1
2

2.7NHNC
2 2.7NH 1
R3204

L3214
R3203

L3213
[2,10]

B 1 NC10NH2 C3216
RX_RFIP1_B1 [8]
B

1
2
L3221 4.7PF

2 C3218 1
2 C3221 1

5.1NH
C3222 RX_IP1_B5 [8]
5.1NH

5.1NH

2 L3216 1
10NHNC
10NH
L3215
L3223
C3219
10NH RX_IN1_B5 [8]
5.1NH

RX_IP_DCS [8]

RX_IN_DCS [8]

2 C3236 1 U3204
5.1NH
2 L3238 1

U3206 10
10NHNC

PORT3_N
10NH
L3239

L3201
[9]B28B_TRX 6 1 1
ANT RX PORT3_P
10NH
C3208 5.6PF

C10
C3202 5.6PF

B28B_PA_OUT 3 8
TX RX PORT1_N
8 B28A/B28B_RX_P [8]
[10] 5.1NH
56PF C3230
GND
GND
GND
GND

7 B28A/B28B_RX_N [8]
PORT1_P
L3230

56PF C3229
10NH

B8532
4
7
5
4
2

PORT2_N
5
GND

PORT2_P

A VTCXO_1_PMU A
U3205

[9] B28A_TRX C3211 33PF 6 1 2 L3204 1 BPI12_B28

6
VCONT GND
2
ANT RX
5.1NH [2]
2 L3209 1

9 3
[10]B28A_PA_OUT 3 8 VDD GND
TX RX
10NHNC
10NH
L3205
GND
GND
GND
GND
10NH NC

DRAWN BY: MODULE TITLE:

0.1uF C7071
L3229

2
L3217

RF1624
0.1uF C7072

L3212
10NH

B8531 2
<NAME HERE> <MODULE NAME HERE> <TITLE NAME HERE>
7
5
4
2

5.1NH
1 SIZE: DRAWING NO: REV:
1
CHECKED BY: A2
1 <DRAWN NO HERE> <NO>
<NAME HERE>
SHEET: No of No <DATE HERE>

6 5 4 3 2 1
 6 5 4 3 2 1

100PF C3345
2

100NF C3336
2 VPA_PMU [5,10]

C3328 1UF
C3332 10PF

1NF
1
3.9NH 1 2

C3331
1
[9] 2 L3301 1
B3_PA_OUT

0.5PF C3301
NC
2

7.5NH
1 L3302

36

37

38

39

40

41

42

43

44

45

46

47

48
1

GND

B34/39

GND

VCC2G

GND

VCC2HB

VCC1HB

GND

GND

GND

GND

GND

GND
2 R3301
47PF LTE_APC1 [2]
1
D

10KR
24KR
2

270PF C3326
[9] 2

1PF C3303
B2_PA_OUT
C3302 2 35 1
B3/4 GND

1 L3303 2

NC
3.9NH

R3302
1 1
34 2
B2 VRAMP

C3325 2

1
33 3 TX_DCS_PCS [8]
GND GND 1 C3340 33PF

0R

C3324 33PF
NC 2.2NH
L3313
NC
1 L3304 2 32 4
B1_PA_OUT [9] B1 HB2G
3NH NC
2 2
0.5PF

C3305

0.5PF

C3304
[8]

1
31 5 B1/B2/B3_TX
1 1 GND HB3G C3477 12PF C3341 33PF

C3323
NC 2.2NH
L3314

3.3PF
30 6
HB2G_OUT VIO VMIPI_PMU

1NF
L3305

HRPF59640B
[9] 2G_HB_PA_OUT

C3322
2.2NH

U3301
29 7
GND CLK
1 L3307 NC

1 L3306 NC

LTE_MIPI0_SCLK[2,9,10]
2

2
9.1NH

9.1NH

28 8
GND DATA LTE_MIPI0_SDATA [2,9,10]

27 9 1 L3312 2 C3342
GND GND

1
B5/B8/B28_TX [8]
9.1NH 33PF
C C

NC 2.2NH
L3308

L3315
26 10

C3321
2G_LB_PA_OUT[9] LB2G_OUT LB3G

3.3PF
3.9NH
2 2
C3307

C3306

C3320
2.2PF

25 11
2.2PF

1
2

1
GND LB2G TX_GSM_GSM850[8]
1 1 C3343 33PF
12PF

NC 2.2NH
L3316
1
L3309
24 12

C3319
[9] B8_PA_OUT 2 B5/8 GND 2
6.2NH NC
1.2PF

2
1.2PF

C3308
C3309

1 1 23 13 VBAT
NC GND VBATT
U3302
TFSL06050915-4108B1

100PF

C3317 22UF
[6,7,10,15,20]

1NF
2 1 2.2NH 22 14
[9] B5_PA_OUT PUT PUT B5/8 GND

C3344

C3318
L3310
2
GND

GND

9.1NH
L3311

VCC2LB

VCC1LB
C3310
1.2PF

B13/20

B17/28

GND

GND

GND

GND

GND

GND

GND

GND

GND
1
4

21

20

19

18

17

16

15

49

50

51

52

53

54
VPA_PMU [5,10]

C3316 10PF

100NF C3315

C3314 10UF
2
1
2
1
B B

1
[9]

12PF

12PF
[5,10] VPA_PMU B28A_PA_OUT
C2 22PF
U3303
C3327 10NF

C3422

C3423
C3329 10UF

3
RF1 NC NC
5
RFIN
1

1
CTRL

RF2 [9]
12PF

12PF
B28B_PA_OUT
GND

VDD

C3400 22PF
BGS12PL6
2

C3403

U2 NC NC

C3
TX_B28 VTCXO_1_PMU
33PF C3357

C3330
22PF 1 10 [2] BPI8_B28B
VCC1 VCC2
NC

2 9
RF_IN RF_OUT 1
100PF C3335
18PF

C3334 2
C3333
C1

VBAT 3 8 0.5PF
C7118

VBAT
C7117 10NF

[6,7,10,15,20] VBATT SEL 22PF

NC
4.7UF

VMIPI_PMU 4 7
10NF C3356

VMIPI_PMU VIO GND

2

A GND
11
A
5 6
1 DATA CLK

LTE_MIPI0_SCLK [2,9,10]
[2,9,10] LTE_MIPI0_SDATA RF7941

DRAWN BY: MODULE TITLE:

<NAME HERE> <MODULE NAME HERE> <TITLE NAME HERE>
SIZE: DRAWING NO: REV:
CHECKED BY: A2 <DRAWN NO HERE> <NO>
<NAME HERE>
SHEET: No of No <DATE HERE>

6 5 4 3 2 1
 6 5 4 3 2 1

[2] BPI11_DRX_V2
D [2] BPI10_DRX_V1

P-JS-TT-08
ANT3401
VTCXO_1_PMU

D
P-JS-TT-08
ANT3402

10PF
C4
1

2
1

CTL1

CTL2

VDD
C3431 U3402 C3406
2 1 13 4

1
GND RF4

1
ANT IN
18PF 18PF

G2

G1
NC 18PF
12
C3432
1 GND
1
NC18PF

C3433

3
2 MM8030-2610 10 6 [11]
2 1 GND RF3 B8_DRX

C3404

NC18PF
2 8
GND
5 11
GND RF2 B28_DRX
[11]

8
U3401 7 9
ANT RF1 B3_DRX
[11]

RFC
L3426
2.2NH L3401 1 7 2.2NH NC
NC RF1 RF2 RF1614
2 6
GND GND RF1614A
9 5
GND VDD U1

VTCXO_1_PMU [1,5,8,9,10,11,19]
CTL

EN

100PF
C3401
RF1141A
3

C C
DRX_ANT_EN [2]
DRX_ANT_CTL1 [2]

RFBLN1005040YM1T69

U3405
BLC
U3404 C3405 3.3PF
B8323/AB11B B28_DRX_P [8]

NC 2.2NH
L340712NH L3408 12NH

15NH
1 OUTPUT 4

L3409

L3410
[11] B28_DRX INPUT
UNBLC GND

C3402 4.7PF

L340615NH
5

GND1
3 GND2
GND3
C3407 3.3PF
B28_DRX_N [8]

BLC
2
U3406 C3410 3.3PF
B SAFFB806MFA0F0A B8_DRX_N [8]
B

NC 2.2NH

15NH
L3402

L3404
1
2
[11] B8_DRX UNBALANCE1 BALANCE2
33PF C3409

2 L3405 1
BALANCE1

GND1

GND2
15NH
C3411 3.3PF B8_DRX_P [8]

ÌùSAFFB942MFM0F0A

C3426

1
2
B3_DRX_P [8]
U3407 4.7PF
SAFFB1G84FL0F0A

2 L3424 1
4.7NH NC

3.9NH
1 4

L3425
[11] B3_DRX UNBALANCE1 BALANCE2
12PF L3423
BALANCE1 3
GND1

GND2
3.9NH
L3403

C3427

A
2

1
B3_DRX_N [8]
A
2

4.7PF

DRAWN BY: MODULE TITLE:

<NAME HERE> <MODULE NAME HERE> <TITLE NAME HERE>
SIZE: DRAWING NO: REV:
CHECKED BY: A2 <DRAWN NO HERE> <NO>
<NAME HERE>
SHEET: No of No <DATE HERE>

6 5 4 3 2 1
 TFlash card
J4001

[3] MSDC1_DAT2 1

[3] MSDC1_DAT3 2

3
[3] MSDC1_CMD
4
VMCH_PMU
[3] R4001 5
MSDC1_CLK
33R
6

[3] MSDC1_DAT0 7

[3] MSDC1_DAT1 8

PMSD-8F-SMT-001-HB

SW: H= Card Inserting L= No Card

4.7UF
CAP0402
C4001
GND

Schematic design notice of "41_MEMORY_SD Card" page.

Note 41-1: The equivalent capacitance of ESD protection device must be <=0.5pF
 eMMC+LPDDR3 16GB eMMC + 16Gb LPDDR3
221 Ball, 0.5mm pitch

VDD1=1.8V
VDD2=1.20V
VDDCA=1.2V
VDDQ= 1.20V VDD1 : Core 1
DVDD18_EMI

VIO18_PMU DVDD18_EMI
[4] CA[0:9] SH4001
U4101

C4102
C4101
CA0 Y2 CA0 VDD1 F3
CA1 Y3 CA1 VDD1 F4 2 2
CA2 W2 CA2 VDD1 F9
CA3 W3 CA3 VDD1 G5

2.2UF

100NF
CA4 V3 CA4 VDD1 AA3
1 1
CA5 L3 CA5 VDD1 AA5 VDD2 : Core 2
CA6 K3 CA6 VDD1 AB3
DVDD12_EMI
CA7 J3 CA7 VDD1 AB4
[4] CA8 J2 CA8 VDD1 AB9
DQ[0:31]
CA9 H2 CA9
VDD2 F5
DQ0 W12 DQ0 VDD2 F8
DQ1 V11 DQ1 VDD2 J5
DQ2 V13 DQ2 VDD2 K5
DQ3 U11 DQ3 VDD2 L2
DQ4 U13 DQ4 VDD2 L5
DQ5 T11 DQ5 VDD2 M5
DQ6 T13 DQ6 VDD2 N5
DQ7 R12 DQ7 VDD2 P5
DQ8 N12 DQ8 VDD2 P8
DQ9 M13 DQ9 VDD2 P11
DQ10 M11 DQ10 VDD2 R5
DQ11 L13 DQ11 VDD2 T5
DQ12 L11 DQ12 VDD2 U5
DQ13 K11 DQ13 VDD2 V5
DQ14 K13 DQ14 VDD2 W5
DQ15 J12 DQ15 VDD2 AB5
DQ16 AB12 DQ16 VDD2 AB8
DQ17 AB11 DQ17
DQ18 AB10 DQ18 VDDQ G9

C4108
C4105

C4106

C4107
DQ19 AA13 H8

10UF C4103

10UF C4104
DQ19 VDDQ 2 2 2 2 2 2
DQ20 AA12 DQ20 VDDQ H12
DQ21 AA10 DQ21 VDDQ J11
DQ22 Y13 K10

100NF

100NF

100NF
DQ22 VDDQ

100NF
DQ23 Y11 DQ23 Power VDDQ K12 1 1 1 1 1 1
DQ24 H11 DQ24 VDDQ L8
DQ25 H13 DQ25 VDDQ L9
DQ26 G10 DQ26 VDDQ M10
DQ27 G12 DQ27 VDDQ M12
DQ28 G13 DQ28 VDDQ N11 1. VCC : Core Voltage 2.7v ~ 3.6v
DQ29 F10 DQ29 VDDQ R11 2. VCCQ : IO Voltage 1.7v~1.95v (low voltage range)
DQ30 F11 DQ30 VDDQ T10
DQ31 F12 DQ31 VDDQ T12
VDDQ U8
R4103 G2 U9
240R ZQ0 VDDQ
240R G3 ZQ1 VDDQ V10
R4104 VDDQ V12
F13 VSSQ VDDQ W11
G11 VSSQ VDDQ Y8
H10 VSSQ VDDQ Y12
J8 VSSQ VDDQ AA9
J13 VSSQ
K8 VSSQ VDDCA K2
K9 VSSQ VDDCA N2
L10 VSSQ VDDCA U2
L12 VSSQ VDDCA V2
M8 VSSQ
N13 VSSQ VCC B3 VEMC_3V3_PMU
P9 VSSQ VCC B12
R13 VSSQ VCC B13
T8 VSSQ VCC C4
U10 VSSQ VCC D8
U12 VSSQ VCCQ A4 VIO18_PMU
V8 VSSQ VCCQ B6
V9 VSSQ VCCQ B9
W8 VSSQ VCCQ C7
W13 VSSQ VCCQ C11
Y10 VSSQ VCCI A11
AA11 VSSQ

C4114
RFU A7 MSDC0_DSL [3]

C4109

C4113
C4111

C4112
F2 VSS CLKM B8 [3] 2

1UF C4110
MSDC0_CLK
G4 VSS RST C2 MSDC0_RSTB [3] 2 2 2 2 2
G8 VSS eMMC CMD A6 MSDC0_CMD [3]

100NF
H3 VSS

100NF

220nF

2.2UF
1

4.7UF
H5 VSS DAT7 B4 MSDC0_DAT7 [3] 1 1 1 1 1
L4 VSS DAT6 A5 MSDC0_DAT6 [3]
M3 VSS DAT5 A10 MSDC0_DAT5 [3]
M4 VSS DAT4 C9 MSDC0_DAT4 [3]
N4 VSS DAT3 B5 [3]
N8 VSS DAT2 C6
MSDC0_DAT3
MSDC0_DAT2 [3]
Close to Memory
P4 VSS DAT1 B10 MSDC0_DAT1 [3]
P12 VSS DAT0 A9 MSDC0_DAT0 [3]
R3 VSS
R4 VSS The eMMC VCC/VCCQ/VDDI bypass cap recommand value,
R8 VSS
T4 VSS
please refer to vendor datasheet or
Y4 U3
Y5
VSS
VSS
CS0#
CS1# T3
CS0_N
CS1_N
[4]
[4]
MT6593 Design Notice (eMMC power capacitor value reference)
AA2 VSS LP-DDR3
AA4 VSS CKE0 T2 CKE [4,13]
AA8 VSS CKE1 R2 CKE [4,13]

H4 VSSCA CLK P3 CLK0_T [4]

J4 VSSCA CLK# N3 CLK0_C [4]
K4 VSSCA
P2 VSSCA DQS0 T9 DQS0_T [4]
U4 VSSCA DQS0# R9 DQS0_C [4]
V4 VSSCA DQS1 M9 DQS1_T [4]
W4 VSSCA DQS1# N9 DQS1_C [4]
DQS2 Y9 DQS2_T [4]
A3 VSSM DQS2# W9 DQS2_C [4]
A8 VSSM DQS3 H9 DQS3_T [4]
A12 VSSM DQS3# J9 DQS3_C [4]
B2 VSSM
B7 VSSM DM0 R10 DQM0 [4]
B11 VSSM DM1 N10 DQM1 [4]
C3 VSSM DM2 W10 DQM2 [4]
C5 VSSM DM3 J10 DQM3 [4]
C8 VSSM
C10 VSSM VREFCA M2 EVREF [2,13]
C12 VSSM VREFDQ P13 EVREF [2,13]
C13 VSSM
D7 VSSM
AB14
C4116

DNU
C4115

A2 VSF DNU AB13

A13 AB2 2 2
VSF DNU
B1 VSF DNU AB1
B14 AA14
4.7UF

100NF

VSF DNU
D2 VSF DNU AA1 1 1
D3 VSF DNU A14
D4 VSF DNU A1
D5 VSF
D6 VSF

ODT P10

KMQ7X000SA-B315
BGA_221PIN_0.5P_14X22_11.5X13
 6 5 4 3 2 1

ANT5002
ANT5001

P-JS-TT-08
P-JS-TT-08
KT2520F26000ZAW18TAK
50 Ohm

1
1
U5005 GND GND
[3,14] CONN_XO_IN OUT VCC VCN28_PMU [5,14]
1 [14]
HF-PORT WB_ANT
L5003
50 Ohm U5002
2 1 5
D 0R
PORT

LF-PORT
3
GPS_RF_LNA [14]
C5006
C5001 100PF
26M

GND
GND
GND
NC39NH
1UF

L5001
NC
DP1608-V1524CAT/LF D

6
4
2
[3] WB_CTRL4 WB_CTRL3 [3]
[3] WB_CTRL5 WB_CTRL2 [3]

WB_CTRL1 [3]
[1,5,14] VCN18_PMU
WB_CTRL0 [3]

C5014 C5015
U5003 100NF 100PF WB_RX_IP [3]
B39242B9604P810
C5018 WB_RX_IN [3]
L5004 4 ANT 1
[14] WB_ANT 0R 2 TX/RX
1
22PF
U5001

30

29

28

27

26

25

24

23

22

21
5 NC C5020

GND1

3 GND2

C5019
GND3

22PF
NC 22PF

W_LNA_EXT

AVDD18_WBT

WB_CTRL5

WB_CTRL4

WB_CTRL3

WB_CTRL2

WB_CTRL1

WB_CTRL0

WB_RX_IP

WB_RX_IN
NC 27NH
C

L5002
L5011

2
0.5PF
NC 50 Ohm
31 20 [3]
C
WB_GPS_RF_IN WB_RX_QP WB_RX_QP

50 Ohm
32 GPS_DPX_RFOUT WB_RX_QN 19 WB_RX_QN [3]

[5] VCN33_PMU 33 AVDD33_WBT WB_TX_IP 18 WB_TX_IP [3]

C5012 C5011 GND

100PF 34 NC WB_TX_IN 17 WB_TX_IN [3]
4.7UF

C5017 35 16
10NF NC WB_TX_QP WB_TX_QP [3]

B5001
[5,14] VCN28_PMU 1

120R/100MHz
2 36 AVDD28_FM
MT6625L WB_TX_QN 15 WB_TX_QN [3]

37 14
C5013

[15] FM_RX_N_6625 FM_LANT_N GPS_RX_IP GPS_RX_IP [3]

18PF

[14] GPS_RF_LNA
2 1 L5006
[15] 38 FM_LANT_P GPS_RX_IN 13 GPS_RX_IN [3]
FM_ANT

NC100NH
82NH
NC

L5008
50 Ohm
100PF C5022
C5021 39 GPS_RFIN GPS_RX_QP 12 GPS_RX_QP [3]
2.2PF
NC

B [1,5,14] VCN18_PMU 40 AVDD18_GPS GPS_RX_QN 11 GPS_RX_QN [3] B

AVDD28_FSOURCE
C5003 4.7NF
C5004
1UF 41 DVSS

F2W_DATA
L5005
1

0R [5,14]

F2W_CLK
VCN28_PMU

FM_DBG
HRST_B

SDATA
INPUT

XO_IN
CEXT
SCLK
SAFEB1G57KE0F00R14

SEN
GND2 C5005
MT6627
U5012

3 100NF MT6627 SMD QFN40

10
GND1
2
GPIO_GPS_LNA_EN [2]
OUTPUT

GND 5 GND3 GND

GND

U5004
4

VCC

ENABLE

[3] CONN_RSTB [3,14]

L5010 CONN_XO_IN
L5009
RFIN RFOUT
33PFC5016 10NH 33PFC5036 0R
[3] F2W_DATA
GND2

GND1

C5007 C5009
C500833PF

C5010
2.2PF [3] 1UF
F2W_CLK 100PF

NC AR8159 [3] CONN_SCLK

GND GND
GND
[3] CONN_SDATA

[3] CONN_SEN

A A

DRAWN BY: MODULE TITLE:

<NAME HERE> <MODULE NAME HERE> <TITLE NAME HERE>
SIZE: DRAWING NO: REV:
CHECKED BY: A2 <DRAWN NO HERE> <NO>
<NAME HERE>
SHEET: No of No <DATE HERE>

6 5 4 3 2 1
 6 5 4 3 2 1

2
C6013 33PF
T6001
B6010

1
CAP0201
D [19] MICP_SUB
B6001 600R
AU_VIN0_P [5] [5] AU_HSN
1UF C6002 REC6011
600R

B6002 600R
C6015
1 D
100PF
[19] MICN_SUB AU_VIN0_N [5]
1UF C6003 B6009 2
CAP0201 RECEIVER
100PF
C6007 [5] AU_HSP
600R

2
33PF C6008

C6014 33PF
C6010 33PF

T6002

1
MICBIAS0
MIC 2 Close to BB Close to connector
L R GND MIC
Earphone R6024
Audio Jack 6
7
GND
C Close to MIC Close to BB
[3] EINT_EAR 47KR
1
GND
C
R6025 2 1800R M/G
470KR B6024 1

R6027

C6060 33PF
VIO18_PMU

1KR
3

C6021 33PF
[1,2,3,5,6,8,13,16,17,18] R
B6020 1 2 1800R
HP_MIC ok 5
L

CAP0201
[15]
R6020 B60211 2 1800R
B6041 [5,15] AU_HPL 33R
22UF C6050
R6021 B6022 1 2 1800R 4
1 2 [5] AU_HPR 33R DEC
[17] MICP_SUB2 AU_VIN2_P [5]
1UF C6046 22UF C6051 2
CAP0201
600R C6018 1NF G/M
C6000 J6002

C6061 33PF
C6022 33PF

R6026
100PF B6042 EJ-36924-GP

1KR

2
C6019 1NF

???
[17] MICN_SUB2 1 2
AU_VIN2_N [5]
1UF C6047
600R
C6017 1NF
100NF T6020 T6021 T6022
C6059

1
T6011 R6022

2.5KR
0R FM_ANT [14]

ESD9L5.0ST5G
RES0201
T6025

1
C6041 33PF

C6042 33PF

6PF

T6024
C6029

2
[5] MICBIAS1

B6023
R6023
0R FM_RX_N_6625 [14]
GND RES0201

R6030
1KR
CAP0201
Close to BB Close to MIC
B [5] AU_VIN1_N
1UF C6030 10UF C6035
B
GND of C435(10uF) and headset
Close to J420 should tie together and single

R6031
1.5KR
100PF
C6032
via to GND plane
VBAT

CAP0201
[5] AU_VIN1_P HP_MIC [15]
1UF C6031
C6071 10UF

100NF

C6033 33PF

C6034 33PF
C6070 [5] ACCDET 1KR
R6032

C6036 33PF
C6074
B2

B1

U6070 1NF
PVDD

AVDD
C6073 C6072

B6070
100NF 100NF

R6070 C1
[5,15] AU_HPL INN 1 2
51KR A3 [19]
VON SPK_N_1
220R
R6071 A1
51KR
INP B6071 tie together and single via to GND plane
C3 1 2
VOP SPK_P_1 [19]
C2
GND1

GND2

AUDIOPA_SD SHUTDOWN 220R

[3]
A2

B3

AW8110CSR/9PIN
C6075
1NF
R6072
100KR

A A

DRAWN BY: MODULE TITLE:

<NAME HERE> <MODULE NAME HERE> <TITLE NAME HERE>
SIZE: Audio
DRAWING NO: REV:
CHECKED BY: A2 <DRAWN NO HERE> <NO>
<NAME HERE>
SHEET: No of No <DATE HERE>

6 5 4 3 2 1
 C6101
4.7NF
J6101

LCM VGP1_PMU
VIO18_PMU
1
2
3
4
GND
VCC
IOVCC
GND
[3] LCM_RST 5 RERST
6 TE
[3] DSI_TE 7 LEDPWN
8 GND

33PF
9 DSI_D3P
[3] TDP3
VIO18_PMU 10 DSI_D3N
[3] TDN3 11 GND
12

C6114
[3] TDP2
DSI_D2P
13 DSI_D2N
[3] TDN2
14 GND

100KR
R6115
[3] TCP 15 DSI_CLKP
[3] TCN 16 DSI_CLKN
17 GND
18 DSI_D1P
[2] LCM_ID [3] TDP1
[3] TDN1 19 DSI_D1N

33PF
20 GND
[3] TDP0 21 DSI_D0P
22 DSI_D0N
[3] TDN0
23

C6115
GND
24 LEDK
VLED_N
25 LEDA
VLED_P

26
27
FH26-25S-0.3SHW(05)

VGP1_PMU VIO18_PMU VLED_P

C6104 4.7NF
C6103 1UF
C6102
2.2UF

CAP0402 CAP0201

GND GND GND

CTP VIO18_PMU

R6101 J6102
NC

24-5806-010-112-829+

R6103 750R 1 10
[3] EINT_CTP

[3,6,7] 2 9
SDA0
3 8
[3,6,7] SCL0
Modify to 6.8R R6102 4 7
VGP1_PMU
RES0201 5 6
[3] GPIO_CTP_RSTB 0R

C6105 C6106 C6107

11
12
13
14
C6109 10NF
C6108 1UF

470PF 15PF 15PF

GT917S's INT pin CANNOT be pulled-up.

 Main Camera
TP-0.5MM
J6201 TP6202

1 2
AGND PWDN CAM_PDN0 [3]
AF VCC 2.8V 3 4
[5] VCAM_AF_PMU MVDD SDA SDA3 [3,17]
5 MGND SCL
6 [3,17]
SCL3
R6210
VCAMA_PMU AVDD 2.8V 1 0R 2 7 AVDD28
8
STORBE

9 10 DOVDD 1.8V
1UF

DGND DOVDD18 VCAM_IO_PMU [5,17]

[3] 11 MDP3 12
RDP2 DGND
C6210

[3] 13 MDN3 MCLK 14

RDN2 CMMCLK [3]
15 DGND DGND
16

[3] RCP 17 MCP MDP1 18 [3]

RDP0
[3] 19 MCN MDN1 20 [3]
RCN RDN0
21 DGND DGND
22

[3] 23 MDP4 MDP2 24 [3]

RDP3 RDP1
[3] 25 MND4 MND2 26 [3]
RDN3 RDN1
DVDD, 1.05V
27 DGND 28
VCAMD_PMU DVDD105

29 DVDD105 30
NC C6274
100NF
100NF C6272
C6271 2.2UF

C6270 31 33
2.2UF C6273
CAP0201 2.2UF 32 34 I2C ADDR/IMX179: (WRITE) (READ)
CAP0201
I2C ADDR/IMX179: (WRITE) (READ)
WP7A-S030VA1-1

I2C address:(write:0X20 ;read:0X21 )

SUB CAM/PS/ALS CON

VIO18_PMU
C6223 1UF

J6220
R6204

24-5806-030-112-829+
4.7KR

1 30 CAM_RST1 [3]

[5,15,19] MICBIAS0 2 29 CAM_PDN1 [3]

3 28

4 27 RCN_A [3]
[15] MICP_SUB2
5 26 RCP_A [3]
[15] MICN_SUB2
6 25 SCL3 [3,17]

[3] RDN0_A 7 24 SDA3 [3,17]

[3] RDP0_A 8 23 VGP3_PMU [5]

9 22 VCAM_IO_PMU [5,17]
R6218
[5,17] VCAMA_PMU 0R 10 21
R6216
[5,17,18] VIO28_PMU 22R 11 20 RDN1_A [3]

[3] EINT_ALPS 12 19 RDP1_A [3]

[3,18] SDA1 13 18

[3,18] SCL1 14 17 CAM_RST0_CLK

[5,17,18] VIO28_PMU
15R R6221 15 16 [3]

2.2UF
C6222
C6221 1UF

C6224 1UF

31

32

33

34

100NF 100NF
C6226 C6225

I2C address:(write:0X6C ;read:0X6D )

 G SENSOR VIO18_PMU
M-SENSOR

R6300 I2C address:0x0C(write:0x18;read:0x19)

RES0201
0R

A2
VIO28_PMU U6310

12

11

10
U6301

CAD
SCL

VDDIO

NC
VIO28_PMU A1 A3
VDD TST

1 9
ADDR0 GND B1 B3
[3,17,18] VSS SCL SCL1 [3,17,18]
SCL1
[3,17,18] 2 8
SDA1 SDA GND
C1 C3

C6351
C6350
3 7 VIO18_PMU VID SDA SDA1 [3,17,18]
VDDIO VDD

100NF

RSTN
1UF
GND

INT1

INT2
C6304 AK09911C

C2
4

C6203

C6305

100NF
100NF
100NF M_RESET [3]
MC3430-I5

[3] EINT_A+GYRO

VIO18_PMU
VIO18_PMU
+/-1%

+/-1%

R6323
390K

390K
R6321

[2] AUX_IN0_NTC [2] AUX_IN1_NTC

1UF C6321

1UF C6322
R6322

R6324
CAP0201

CAP0201
 Sub board IO
J6401
24-5806-030-112-829+

1 30

[15,19] SPK_P_1 2 29 [5]

MOTO+
3 28 SUB_SW_CTL2
[15,19] SPK_P_1 [2]
[15,19] SPK_N_1 4 27
SUB_SW_CTL1 [2]

[15,19] SPK_N_1 5 26
SUB_SW_EN [2]
6 25
VTCXO_1_PMU [1,5,8,9,10,11]
[3] 7 24
GPIO_SUBID
8 23 [3,19]
USB_DP
9 22 [3,19]
USB_DM
10 21
[5,7,19,20] VBUS VBUS [5,7,19,20]
11 20

12 19

13 18 [15]
MICP_SUB

MICBIAS0 14 17
MICN_SUB [15]
15 16

1
D1111

31

32

33

34
2
10NF C1120

[3,19] USB_DP TP1101

[3,19] USB_DM TP1102

[5,7,19,20] VBUS TP1103

 [20] KCOL0_T

Vol+/- KEY SIM2 Card SIM1 Card

4
J6501

NTC311-FA1T-A160
[3] R6501
KCOL0 1KR GND
5
J6532 J6531
T6501
[2] SIM2_SCLK 3 6 [2] [2] 3 6 SIM1_SIO [2]
SIM2_SIO SIM1_SCLK

3
[2] SIM2_SRST 2 5 [2] SIM1_SRST 2 5

R6554 1 4 R6552 1 4

4
VSIM2_PMU NC VSIM1_PMU NC

J6502

NTC311-FA1T-A160

C6537
PSIM-6F-SMT-001-HB PSIM-6F-SMT-001-HB
R6502
[5] HOMEKEY 1KR
GND
5 R6551 C6540 15PF
15PF
NC
T6502
R6550

3
NC

Vol+: KCOL/GND

C6535
C6534
Vol-: FCHG_ENB/GND

C6536 1UF
15PF 15PF
C6531

C6532 1UF
C6530
15PF
CAP0201
15PF CAP0201

Power KEY GND

2

[20] PWRKEY_T
J6503

NTC311-FA1T-A160

R6503 GND
DET: L=NO SIM; H= INSERT CARD DET: H=NO SIM; L= INSERT CARD
[7] PWRKEY 1KR 5
C6501
T6503
100NF
1

GND

T6533 T6534

D6501
VBAT TP6501 TP-1.5MM
R6512
[5,7,19,20] VBUS 4 Blue 1 2
[20] PWRKEY_T TP6502 TP-1.5MM 1 200R
Red 2 R6513
5 2
TP6503 TP-1.5MM [5,6,7] VSYS ISINK1 [5]
1 200R
R6514
6 Green 3 2
ISINK0 [5]

1UF C6502
[5,6] BAT_ON TP6504 TP-1.5MM 1 200R
J6560
19-337/R6GHBHC-A01/2T
1
UTXD0 TP6505 TP-1.5MM
2 [3]
R6549
HOLE09MM

HOLE09MM

HOLE08MM

3 URXD0 TP6506 TP-1.5MM

H1

H2

H3

[3] 200R
4
1

5
[20] KCOL0_T TP6507 TP-1.5MM
6

3
Q6500
[5] ISINK2
7

C
8 SPRING1 B
1 [5,7,19,20] R6540 R6541 2
VBUS
2 [3,20] 100KR 1KR
9 EINT_CARD

1NF C6541

E
818002384
10 DTC143ZEBTL

1
11

MN_SIM_METAL_SHELL
1

J6511
MANIFOLD_SOLID_BREP

J1 J2 J3 J4 J5 J6 J7 J8
0R
R6570
[3,20] EINT_CARD EINT_SD [3] 1 1 1 1 1 1 1 1
RES0201
2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3
C6500

15PF LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L LO99-T1SMP-1WV-L